drivers/gpu/drm/bridge/analogix/analogix_dp_core.c

   1 /*
   2 * Analogix DP (Display Port) core interface driver.
   3 *
   4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5 * Author: Jingoo Han <jg1.han@samsung.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms of the GNU General Public License as published by the
   9 * Free Software Foundation; either version 2 of the License, or (at your
  10 * option) any later version.
  11 */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/err.h>
  16 #include <linux/clk.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/of.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/gpio.h>
  22 #include <linux/component.h>
  23 #include <linux/phy/phy.h>
  24
  25 #include <drm/drmP.h>
  26 #include <drm/drm_atomic_helper.h>
  27 #include <drm/drm_crtc.h>
  28 #include <drm/drm_crtc_helper.h>
  29 #include <drm/drm_panel.h>
  30
  31 #include <drm/bridge/analogix_dp.h>
  32
  33 #include "analogix_dp_core.h"
  34 #include "analogix_dp_reg.h"
  35
  36 #define to_dp(nm)       container_of(nm, struct analogix_dp_device, nm)
  37
  38 struct bridge_init {
  39         struct i2c_client *client;
  40         struct device_node *node;
  41 };
  42
  43 static void analogix_dp_init_dp(struct analogix_dp_device *dp)
  44 {
  45         analogix_dp_reset(dp);
  46
  47         analogix_dp_swreset(dp);
  48
  49         analogix_dp_init_analog_param(dp);
  50         analogix_dp_init_interrupt(dp);
  51
  52         /* SW defined function Normal operation */
  53         analogix_dp_enable_sw_function(dp);
  54
  55         analogix_dp_config_interrupt(dp);
  56         analogix_dp_init_analog_func(dp);
  57
  58         analogix_dp_init_hpd(dp);
  59         analogix_dp_init_aux(dp);
  60 }
  61
  62 static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
  63 {
  64         int timeout_loop = 0;
  65
  66         while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
  67                 if (analogix_dp_get_plug_in_status(dp) == 0)
  68                         return 0;
  69
  70                 timeout_loop++;
  71                 usleep_range(10, 11);
  72         }
  73
  74         /*
  75          * Some edp screen do not have hpd signal, so we can't just
  76          * return failed when hpd plug in detect failed, DT property
  77          * "force-hpd" would indicate whether driver need this.
  78          */
  79         if (!dp->force_hpd)
  80                 return -ETIMEDOUT;
  81
  82         /*
  83          * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
  84          * will not work, so we need to give a force hpd action to
  85          * set HPD_STATUS manually.
  86          */
  87         dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
  88
  89         analogix_dp_force_hpd(dp);
  90
  91         if (analogix_dp_get_plug_in_status(dp) != 0) {
  92                 dev_err(dp->dev, "failed to get hpd plug in status\n");
  93                 return -EINVAL;
  94         }
  95
  96         dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
  97
  98         return 0;
  99 }
 100
 101 int analogix_dp_enable_psr(struct device *dev)
 102 {
 103         struct analogix_dp_device *dp = dev_get_drvdata(dev);
 104         struct edp_vsc_psr psr_vsc;
 105
 106         if (!dp->psr_support)
 107                 return -EINVAL;
 108
 109         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 110         memset(&psr_vsc, 0, sizeof(psr_vsc));
 111         psr_vsc.sdp_header.HB0 = 0;
 112         psr_vsc.sdp_header.HB1 = 0x7;
 113         psr_vsc.sdp_header.HB2 = 0x2;
 114         psr_vsc.sdp_header.HB3 = 0x8;
 115
 116         psr_vsc.DB0 = 0;
 117         psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
 118
 119         analogix_dp_send_psr_spd(dp, &psr_vsc);
 120         return 0;
 121 }
 122 EXPORT_SYMBOL_GPL(analogix_dp_enable_psr);
 123
 124 int analogix_dp_disable_psr(struct device *dev)
 125 {
 126         struct analogix_dp_device *dp = dev_get_drvdata(dev);
 127         struct edp_vsc_psr psr_vsc;
 128
 129         if (!dp->psr_support)
 130                 return -EINVAL;
 131
 132         /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */
 133         memset(&psr_vsc, 0, sizeof(psr_vsc));
 134         psr_vsc.sdp_header.HB0 = 0;
 135         psr_vsc.sdp_header.HB1 = 0x7;
 136         psr_vsc.sdp_header.HB2 = 0x2;
 137         psr_vsc.sdp_header.HB3 = 0x8;
 138
 139         psr_vsc.DB0 = 0;
 140         psr_vsc.DB1 = 0;
 141
 142         analogix_dp_send_psr_spd(dp, &psr_vsc);
 143         return 0;
 144 }
 145 EXPORT_SYMBOL_GPL(analogix_dp_disable_psr);
 146
 147 static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp)
 148 {
 149         unsigned char psr_version;
 150
 151         drm_dp_dpcd_readb(&dp->aux, DP_PSR_SUPPORT, &psr_version);
 152         dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version);
 153
 154         return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false;
 155 }
 156
 157 static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp)
 158 {
 159         unsigned char psr_en;
 160
 161         /* Disable psr function */
 162         drm_dp_dpcd_readb(&dp->aux, DP_PSR_EN_CFG, &psr_en);
 163         psr_en &= ~DP_PSR_ENABLE;
 164         drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 165
 166         /* Main-Link transmitter remains active during PSR active states */
 167         psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION;
 168         drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 169
 170         /* Enable psr function */
 171         psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE |
 172                  DP_PSR_CRC_VERIFICATION;
 173         drm_dp_dpcd_writeb(&dp->aux, DP_PSR_EN_CFG, psr_en);
 174
 175         analogix_dp_enable_psr_crc(dp);
 176 }
 177
 178 static void
 179 analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
 180                                        bool enable)
 181 {
 182         u8 data;
 183
 184         drm_dp_dpcd_readb(&dp->aux, DP_LANE_COUNT_SET, &data);
 185
 186         if (enable)
 187                 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 188                                    DP_LANE_COUNT_ENHANCED_FRAME_EN |
 189                                         DPCD_LANE_COUNT_SET(data));
 190         else
 191                 drm_dp_dpcd_writeb(&dp->aux, DP_LANE_COUNT_SET,
 192                                    DPCD_LANE_COUNT_SET(data));
 193 }
 194
 195 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
 196 {
 197         u8 data;
 198         int retval;
 199
 200         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 201         retval = DPCD_ENHANCED_FRAME_CAP(data);
 202
 203         return retval;
 204 }
 205
 206 static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
 207 {
 208         u8 data;
 209
 210         data = analogix_dp_is_enhanced_mode_available(dp);
 211         analogix_dp_enable_rx_to_enhanced_mode(dp, data);
 212         analogix_dp_enable_enhanced_mode(dp, data);
 213 }
 214
 215 static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 216 {
 217         analogix_dp_set_training_pattern(dp, DP_NONE);
 218
 219         drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 220                            DP_TRAINING_PATTERN_DISABLE);
 221 }
 222
 223 static void
 224 analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
 225                                        int pre_emphasis, int lane)
 226 {
 227         switch (lane) {
 228         case 0:
 229                 analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 230                 break;
 231         case 1:
 232                 analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 233                 break;
 234
 235         case 2:
 236                 analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 237                 break;
 238
 239         case 3:
 240                 analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 241                 break;
 242         }
 243 }
 244
 245 static int analogix_dp_link_start(struct analogix_dp_device *dp)
 246 {
 247         u8 buf[4];
 248         int lane, lane_count, pll_tries, retval;
 249
 250         lane_count = dp->link_train.lane_count;
 251
 252         dp->link_train.lt_state = CLOCK_RECOVERY;
 253         dp->link_train.eq_loop = 0;
 254
 255         for (lane = 0; lane < lane_count; lane++)
 256                 dp->link_train.cr_loop[lane] = 0;
 257
 258         /* Set link rate and count as you want to establish*/
 259         analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 260         analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
 261
 262         /* Setup RX configuration */
 263         buf[0] = dp->link_train.link_rate;
 264         buf[1] = dp->link_train.lane_count;
 265         retval = drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, 2);
 266         if (retval < 0)
 267                 return retval;
 268
 269         /* Set TX pre-emphasis to minimum */
 270         for (lane = 0; lane < lane_count; lane++)
 271                 analogix_dp_set_lane_lane_pre_emphasis(dp,
 272                         PRE_EMPHASIS_LEVEL_0, lane);
 273
 274         /* Wait for PLL lock */
 275         pll_tries = 0;
 276         while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 277                 if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
 278                         dev_err(dp->dev, "Wait for PLL lock timed out\n");
 279                         return -ETIMEDOUT;
 280                 }
 281
 282                 pll_tries++;
 283                 usleep_range(90, 120);
 284         }
 285
 286         /* Set training pattern 1 */
 287         analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
 288
 289         /* Set RX training pattern */
 290         retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 291                                     DP_LINK_SCRAMBLING_DISABLE |
 292                                         DP_TRAINING_PATTERN_1);
 293         if (retval < 0)
 294                 return retval;
 295
 296         for (lane = 0; lane < lane_count; lane++)
 297                 buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
 298                             DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 299
 300         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, buf,
 301                                    lane_count);
 302         if (retval < 0)
 303                 return retval;
 304
 305         return 0;
 306 }
 307
 308 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 309 {
 310         int shift = (lane & 1) * 4;
 311         u8 link_value = link_status[lane >> 1];
 312
 313         return (link_value >> shift) & 0xf;
 314 }
 315
 316 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 317 {
 318         int lane;
 319         u8 lane_status;
 320
 321         for (lane = 0; lane < lane_count; lane++) {
 322                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 323                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 324                         return -EINVAL;
 325         }
 326         return 0;
 327 }
 328
 329 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 330                                      int lane_count)
 331 {
 332         int lane;
 333         u8 lane_status;
 334
 335         if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
 336                 return -EINVAL;
 337
 338         for (lane = 0; lane < lane_count; lane++) {
 339                 lane_status = analogix_dp_get_lane_status(link_status, lane);
 340                 lane_status &= DP_CHANNEL_EQ_BITS;
 341                 if (lane_status != DP_CHANNEL_EQ_BITS)
 342                         return -EINVAL;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static unsigned char
 349 analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 350 {
 351         int shift = (lane & 1) * 4;
 352         u8 link_value = adjust_request[lane >> 1];
 353
 354         return (link_value >> shift) & 0x3;
 355 }
 356
 357 static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 358                                         u8 adjust_request[2],
 359                                         int lane)
 360 {
 361         int shift = (lane & 1) * 4;
 362         u8 link_value = adjust_request[lane >> 1];
 363
 364         return ((link_value >> shift) & 0xc) >> 2;
 365 }
 366
 367 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 368                                                u8 training_lane_set, int lane)
 369 {
 370         switch (lane) {
 371         case 0:
 372                 analogix_dp_set_lane0_link_training(dp, training_lane_set);
 373                 break;
 374         case 1:
 375                 analogix_dp_set_lane1_link_training(dp, training_lane_set);
 376                 break;
 377
 378         case 2:
 379                 analogix_dp_set_lane2_link_training(dp, training_lane_set);
 380                 break;
 381
 382         case 3:
 383                 analogix_dp_set_lane3_link_training(dp, training_lane_set);
 384                 break;
 385         }
 386 }
 387
 388 static unsigned int
 389 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
 390                                    int lane)
 391 {
 392         u32 reg;
 393
 394         switch (lane) {
 395         case 0:
 396                 reg = analogix_dp_get_lane0_link_training(dp);
 397                 break;
 398         case 1:
 399                 reg = analogix_dp_get_lane1_link_training(dp);
 400                 break;
 401         case 2:
 402                 reg = analogix_dp_get_lane2_link_training(dp);
 403                 break;
 404         case 3:
 405                 reg = analogix_dp_get_lane3_link_training(dp);
 406                 break;
 407         default:
 408                 WARN_ON(1);
 409                 return 0;
 410         }
 411
 412         return reg;
 413 }
 414
 415 static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 416 {
 417         analogix_dp_training_pattern_dis(dp);
 418         analogix_dp_set_enhanced_mode(dp);
 419
 420         dp->link_train.lt_state = FAILED;
 421 }
 422
 423 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
 424                                                  u8 adjust_request[2])
 425 {
 426         int lane, lane_count;
 427         u8 voltage_swing, pre_emphasis, training_lane;
 428
 429         lane_count = dp->link_train.lane_count;
 430         for (lane = 0; lane < lane_count; lane++) {
 431                 voltage_swing = analogix_dp_get_adjust_request_voltage(
 432                                                 adjust_request, lane);
 433                 pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 434                                                 adjust_request, lane);
 435                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 436                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 437
 438                 if (voltage_swing == VOLTAGE_LEVEL_3)
 439                         training_lane |= DP_TRAIN_MAX_SWING_REACHED;
 440                 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 441                         training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 442
 443                 dp->link_train.training_lane[lane] = training_lane;
 444         }
 445 }
 446
 447 static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
 448 {
 449         int lane, lane_count, retval;
 450         u8 voltage_swing, pre_emphasis, training_lane;
 451         u8 link_status[2], adjust_request[2];
 452
 453         usleep_range(100, 101);
 454
 455         lane_count = dp->link_train.lane_count;
 456
 457         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 458         if (retval < 0)
 459                 return retval;
 460
 461         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 462                                   adjust_request, 2);
 463         if (retval < 0)
 464                 return retval;
 465
 466         if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 467                 /* set training pattern 2 for EQ */
 468                 analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
 469
 470                 retval = drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 471                                             DP_LINK_SCRAMBLING_DISABLE |
 472                                                 DP_TRAINING_PATTERN_2);
 473                 if (retval < 0)
 474                         return retval;
 475
 476                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 477                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 478         } else {
 479                 for (lane = 0; lane < lane_count; lane++) {
 480                         training_lane = analogix_dp_get_lane_link_training(
 481                                                         dp, lane);
 482                         voltage_swing = analogix_dp_get_adjust_request_voltage(
 483                                                         adjust_request, lane);
 484                         pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
 485                                                         adjust_request, lane);
 486
 487                         if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
 488                                         voltage_swing &&
 489                             DPCD_PRE_EMPHASIS_GET(training_lane) ==
 490                                         pre_emphasis)
 491                                 dp->link_train.cr_loop[lane]++;
 492
 493                         if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
 494                             voltage_swing == VOLTAGE_LEVEL_3 ||
 495                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 496                                 dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
 497                                         dp->link_train.cr_loop[lane],
 498                                         voltage_swing, pre_emphasis);
 499                                 analogix_dp_reduce_link_rate(dp);
 500                                 return -EIO;
 501                         }
 502                 }
 503         }
 504
 505         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 506
 507         for (lane = 0; lane < lane_count; lane++)
 508                 analogix_dp_set_lane_link_training(dp,
 509                         dp->link_train.training_lane[lane], lane);
 510
 511         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 512                                    dp->link_train.training_lane, lane_count);
 513         if (retval < 0)
 514                 return retval;
 515
 516         return 0;
 517 }
 518
 519 static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 520 {
 521         int lane, lane_count, retval;
 522         u32 reg;
 523         u8 link_align, link_status[2], adjust_request[2];
 524
 525         usleep_range(400, 401);
 526
 527         lane_count = dp->link_train.lane_count;
 528
 529         retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2);
 530         if (retval < 0)
 531                 return retval;
 532
 533         if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
 534                 analogix_dp_reduce_link_rate(dp);
 535                 return -EIO;
 536         }
 537
 538         retval = drm_dp_dpcd_read(&dp->aux, DP_ADJUST_REQUEST_LANE0_1,
 539                                   adjust_request, 2);
 540         if (retval < 0)
 541                 return retval;
 542
 543         retval = drm_dp_dpcd_readb(&dp->aux, DP_LANE_ALIGN_STATUS_UPDATED,
 544                                    &link_align);
 545         if (retval < 0)
 546                 return retval;
 547
 548         analogix_dp_get_adjust_training_lane(dp, adjust_request);
 549
 550         if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
 551                 /* traing pattern Set to Normal */
 552                 analogix_dp_training_pattern_dis(dp);
 553
 554                 dev_info(dp->dev, "Link Training success!\n");
 555
 556                 analogix_dp_get_link_bandwidth(dp, &reg);
 557                 dp->link_train.link_rate = reg;
 558                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 559                         dp->link_train.link_rate);
 560
 561                 analogix_dp_get_lane_count(dp, &reg);
 562                 dp->link_train.lane_count = reg;
 563                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 564                         dp->link_train.lane_count);
 565
 566                 /* set enhanced mode if available */
 567                 analogix_dp_set_enhanced_mode(dp);
 568                 dp->link_train.lt_state = FINISHED;
 569
 570                 return 0;
 571         }
 572
 573         /* not all locked */
 574         dp->link_train.eq_loop++;
 575
 576         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 577                 dev_err(dp->dev, "EQ Max loop\n");
 578                 analogix_dp_reduce_link_rate(dp);
 579                 return -EIO;
 580         }
 581
 582         for (lane = 0; lane < lane_count; lane++)
 583                 analogix_dp_set_lane_link_training(dp,
 584                         dp->link_train.training_lane[lane], lane);
 585
 586         retval = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET,
 587                                    dp->link_train.training_lane, lane_count);
 588         if (retval < 0)
 589                 return retval;
 590
 591         return 0;
 592 }
 593
 594 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 595                                              u8 *bandwidth)
 596 {
 597         u8 data;
 598
 599         /*
 600          * For DP rev.1.1, Maximum link rate of Main Link lanes
 601          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 602          * For DP rev.1.2, Maximum link rate of Main Link lanes
 603          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 604          */
 605         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LINK_RATE, &data);
 606         *bandwidth = data;
 607 }
 608
 609 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 610                                               u8 *lane_count)
 611 {
 612         u8 data;
 613
 614         /*
 615          * For DP rev.1.1, Maximum number of Main Link lanes
 616          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 617          */
 618         drm_dp_dpcd_readb(&dp->aux, DP_MAX_LANE_COUNT, &data);
 619         *lane_count = DPCD_MAX_LANE_COUNT(data);
 620 }
 621
 622 static void analogix_dp_init_training(struct analogix_dp_device *dp,
 623                                       enum link_lane_count_type max_lane,
 624                                       int max_rate)
 625 {
 626         /*
 627          * MACRO_RST must be applied after the PLL_LOCK to avoid
 628          * the DP inter pair skew issue for at least 10 us
 629          */
 630         analogix_dp_reset_macro(dp);
 631
 632         /* Initialize by reading RX's DPCD */
 633         analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 634         analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 635
 636         if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
 637             (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
 638             (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 639                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 640                         dp->link_train.link_rate);
 641                 dp->link_train.link_rate = DP_LINK_BW_1_62;
 642         }
 643
 644         if (dp->link_train.lane_count == 0) {
 645                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 646                         dp->link_train.lane_count);
 647                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 648         }
 649
 650         /* Setup TX lane count & rate */
 651         if (dp->link_train.lane_count > max_lane)
 652                 dp->link_train.lane_count = max_lane;
 653         if (dp->link_train.link_rate > max_rate)
 654                 dp->link_train.link_rate = max_rate;
 655
 656         /* All DP analog module power up */
 657         analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 658 }
 659
 660 static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 661 {
 662         int retval = 0, training_finished = 0;
 663
 664         dp->link_train.lt_state = START;
 665
 666         /* Process here */
 667         while (!retval && !training_finished) {
 668                 switch (dp->link_train.lt_state) {
 669                 case START:
 670                         retval = analogix_dp_link_start(dp);
 671                         if (retval)
 672                                 dev_err(dp->dev, "LT link start failed!\n");
 673                         break;
 674                 case CLOCK_RECOVERY:
 675                         retval = analogix_dp_process_clock_recovery(dp);
 676                         if (retval)
 677                                 dev_err(dp->dev, "LT CR failed!\n");
 678                         break;
 679                 case EQUALIZER_TRAINING:
 680                         retval = analogix_dp_process_equalizer_training(dp);
 681                         if (retval)
 682                                 dev_err(dp->dev, "LT EQ failed!\n");
 683                         break;
 684                 case FINISHED:
 685                         training_finished = 1;
 686                         break;
 687                 case FAILED:
 688                         return -EREMOTEIO;
 689                 }
 690         }
 691         if (retval)
 692                 dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
 693
 694         return retval;
 695 }
 696
 697 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
 698                                       u32 count, u32 bwtype)
 699 {
 700         int i;
 701         int retval;
 702
 703         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 704                 analogix_dp_init_training(dp, count, bwtype);
 705                 retval = analogix_dp_sw_link_training(dp);
 706                 if (retval == 0)
 707                         break;
 708
 709                 usleep_range(100, 110);
 710         }
 711
 712         return retval;
 713 }
 714
 715 static int analogix_dp_config_video(struct analogix_dp_device *dp)
 716 {
 717         int retval = 0;
 718         int timeout_loop = 0;
 719         int done_count = 0;
 720
 721         analogix_dp_config_video_slave_mode(dp);
 722
 723         analogix_dp_set_video_color_format(dp);
 724
 725         if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 726                 dev_err(dp->dev, "PLL is not locked yet.\n");
 727                 return -EINVAL;
 728         }
 729
 730         for (;;) {
 731                 timeout_loop++;
 732                 if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 733                         break;
 734                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 735                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 736                         return -ETIMEDOUT;
 737                 }
 738
 739                 usleep_range(1, 2);
 740         }
 741
 742         /* Set to use the register calculated M/N video */
 743         analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 744
 745         /* For video bist, Video timing must be generated by register */
 746         analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 747
 748         /* Disable video mute */
 749         analogix_dp_enable_video_mute(dp, 0);
 750
 751         /* Configure video slave mode */
 752         analogix_dp_enable_video_master(dp, 0);
 753
 754         timeout_loop = 0;
 755
 756         for (;;) {
 757                 timeout_loop++;
 758                 if (analogix_dp_is_video_stream_on(dp) == 0) {
 759                         done_count++;
 760                         if (done_count > 10)
 761                                 break;
 762                 } else if (done_count) {
 763                         done_count = 0;
 764                 }
 765                 if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 766                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 767                         return -ETIMEDOUT;
 768                 }
 769
 770                 usleep_range(1000, 1001);
 771         }
 772
 773         if (retval != 0)
 774                 dev_err(dp->dev, "Video stream is not detected!\n");
 775
 776         return retval;
 777 }
 778
 779 static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 780                                         bool enable)
 781 {
 782         u8 data;
 783
 784         if (enable) {
 785                 analogix_dp_enable_scrambling(dp);
 786
 787                 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
 788                 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 789                                    (u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 790         } else {
 791                 analogix_dp_disable_scrambling(dp);
 792
 793                 drm_dp_dpcd_readb(&dp->aux, DP_TRAINING_PATTERN_SET, &data);
 794                 drm_dp_dpcd_writeb(&dp->aux, DP_TRAINING_PATTERN_SET,
 795                                    (u8)(data | DP_LINK_SCRAMBLING_DISABLE));
 796         }
 797 }
 798
 799 static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 800 {
 801         struct analogix_dp_device *dp = arg;
 802         irqreturn_t ret = IRQ_NONE;
 803         enum dp_irq_type irq_type;
 804
 805         irq_type = analogix_dp_get_irq_type(dp);
 806         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 807                 analogix_dp_mute_hpd_interrupt(dp);
 808                 ret = IRQ_WAKE_THREAD;
 809         }
 810
 811         return ret;
 812 }
 813
 814 static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 815 {
 816         struct analogix_dp_device *dp = arg;
 817         enum dp_irq_type irq_type;
 818
 819         irq_type = analogix_dp_get_irq_type(dp);
 820         if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
 821             irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
 822                 dev_dbg(dp->dev, "Detected cable status changed!\n");
 823                 if (dp->drm_dev)
 824                         drm_helper_hpd_irq_event(dp->drm_dev);
 825         }
 826
 827         if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
 828                 analogix_dp_clear_hotplug_interrupts(dp);
 829                 analogix_dp_unmute_hpd_interrupt(dp);
 830         }
 831
 832         return IRQ_HANDLED;
 833 }
 834
 835 static void analogix_dp_commit(struct analogix_dp_device *dp)
 836 {
 837         int ret;
 838
 839         /* Keep the panel disabled while we configure video */
 840         if (dp->plat_data->panel) {
 841                 if (drm_panel_disable(dp->plat_data->panel))
 842                         DRM_ERROR("failed to disable the panel\n");
 843         }
 844
 845         ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 846                                          dp->video_info.max_link_rate);
 847         if (ret) {
 848                 dev_err(dp->dev, "unable to do link train\n");
 849                 return;
 850         }
 851
 852         analogix_dp_enable_scramble(dp, 1);
 853         analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 854         analogix_dp_enable_enhanced_mode(dp, 1);
 855
 856         analogix_dp_init_video(dp);
 857         ret = analogix_dp_config_video(dp);
 858         if (ret)
 859                 dev_err(dp->dev, "unable to config video\n");
 860
 861         /* Safe to enable the panel now */
 862         if (dp->plat_data->panel) {
 863                 if (drm_panel_enable(dp->plat_data->panel))
 864                         DRM_ERROR("failed to enable the panel\n");
 865         }
 866
 867         /* Enable video */
 868         analogix_dp_start_video(dp);
 869
 870         dp->psr_support = analogix_dp_detect_sink_psr(dp);
 871         if (dp->psr_support)
 872                 analogix_dp_enable_sink_psr(dp);
 873 }
 874
 875 /*
 876  * This function is a bit of a catch-all for panel preparation, hopefully
 877  * simplifying the logic of functions that need to prepare/unprepare the panel
 878  * below.
 879  *
 880  * If @prepare is true, this function will prepare the panel. Conversely, if it
 881  * is false, the panel will be unprepared.
 882  *
 883  * If @is_modeset_prepare is true, the function will disregard the current state
 884  * of the panel and either prepare/unprepare the panel based on @prepare. Once
 885  * it finishes, it will update dp->panel_is_modeset to reflect the current state
 886  * of the panel.
 887  */
 888 static int analogix_dp_prepare_panel(struct analogix_dp_device *dp,
 889                                      bool prepare, bool is_modeset_prepare)
 890 {
 891         int ret = 0;
 892
 893         if (!dp->plat_data->panel)
 894                 return 0;
 895
 896         mutex_lock(&dp->panel_lock);
 897
 898         /*
 899          * Exit early if this is a temporary prepare/unprepare and we're already
 900          * modeset (since we neither want to prepare twice or unprepare early).
 901          */
 902         if (dp->panel_is_modeset && !is_modeset_prepare)
 903                 goto out;
 904
 905         if (prepare)
 906                 ret = drm_panel_prepare(dp->plat_data->panel);
 907         else
 908                 ret = drm_panel_unprepare(dp->plat_data->panel);
 909
 910         if (ret)
 911                 goto out;
 912
 913         if (is_modeset_prepare)
 914                 dp->panel_is_modeset = prepare;
 915
 916 out:
 917         mutex_unlock(&dp->panel_lock);
 918         return ret;
 919 }
 920
 921 static int analogix_dp_get_modes(struct drm_connector *connector)
 922 {
 923         struct analogix_dp_device *dp = to_dp(connector);
 924         struct edid *edid;
 925         int ret, num_modes = 0;
 926
 927         if (dp->plat_data->panel) {
 928                 num_modes += drm_panel_get_modes(dp->plat_data->panel);
 929         } else {
 930                 ret = analogix_dp_prepare_panel(dp, true, false);
 931                 if (ret) {
 932                         DRM_ERROR("Failed to prepare panel (%d)\n", ret);
 933                         return 0;
 934                 }
 935
 936                 edid = drm_get_edid(connector, &dp->aux.ddc);
 937                 if (edid) {
 938                         drm_mode_connector_update_edid_property(&dp->connector,
 939                                                                 edid);
 940                         num_modes += drm_add_edid_modes(&dp->connector, edid);
 941                         kfree(edid);
 942                 }
 943
 944                 ret = analogix_dp_prepare_panel(dp, false, false);
 945                 if (ret)
 946                         DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
 947         }
 948
 949         if (dp->plat_data->get_modes)
 950                 num_modes += dp->plat_data->get_modes(dp->plat_data, connector);
 951
 952         return num_modes;
 953 }
 954
 955 static struct drm_encoder *
 956 analogix_dp_best_encoder(struct drm_connector *connector)
 957 {
 958         struct analogix_dp_device *dp = to_dp(connector);
 959
 960         return dp->encoder;
 961 }
 962
 963 static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
 964         .get_modes = analogix_dp_get_modes,
 965         .best_encoder = analogix_dp_best_encoder,
 966 };
 967
 968 static enum drm_connector_status
 969 analogix_dp_detect(struct drm_connector *connector, bool force)
 970 {
 971         struct analogix_dp_device *dp = to_dp(connector);
 972         enum drm_connector_status status = connector_status_disconnected;
 973         int ret;
 974
 975         if (dp->plat_data->panel)
 976                 return connector_status_connected;
 977
 978         ret = analogix_dp_prepare_panel(dp, true, false);
 979         if (ret) {
 980                 DRM_ERROR("Failed to prepare panel (%d)\n", ret);
 981                 return connector_status_disconnected;
 982         }
 983
 984         if (!analogix_dp_detect_hpd(dp))
 985                 status = connector_status_connected;
 986
 987         ret = analogix_dp_prepare_panel(dp, false, false);
 988         if (ret)
 989                 DRM_ERROR("Failed to unprepare panel (%d)\n", ret);
 990
 991         return status;
 992 }
 993
 994 static void analogix_dp_connector_destroy(struct drm_connector *connector)
 995 {
 996         drm_connector_unregister(connector);
 997         drm_connector_cleanup(connector);
 998
 999 }
1000
1001 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
1002         .dpms = drm_atomic_helper_connector_dpms,
1003         .fill_modes = drm_helper_probe_single_connector_modes,
1004         .detect = analogix_dp_detect,
1005         .destroy = analogix_dp_connector_destroy,
1006         .reset = drm_atomic_helper_connector_reset,
1007         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1008         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1009 };
1010
1011 static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
1012 {
1013         struct analogix_dp_device *dp = bridge->driver_private;
1014         struct drm_encoder *encoder = dp->encoder;
1015         struct drm_connector *connector = &dp->connector;
1016         int ret;
1017
1018         if (!bridge->encoder) {
1019                 DRM_ERROR("Parent encoder object not found");
1020                 return -ENODEV;
1021         }
1022
1023         connector->polled = DRM_CONNECTOR_POLL_HPD;
1024
1025         ret = drm_connector_init(dp->drm_dev, connector,
1026                                  &analogix_dp_connector_funcs,
1027                                  DRM_MODE_CONNECTOR_eDP);
1028         if (ret) {
1029                 DRM_ERROR("Failed to initialize connector with drm\n");
1030                 return ret;
1031         }
1032
1033         drm_connector_helper_add(connector,
1034                                  &analogix_dp_connector_helper_funcs);
1035         drm_mode_connector_attach_encoder(connector, encoder);
1036
1037         /*
1038          * NOTE: the connector registration is implemented in analogix
1039          * platform driver, that to say connector would be exist after
1040          * plat_data->attch return, that's why we record the connector
1041          * point after plat attached.
1042          */
1043          if (dp->plat_data->attach) {
1044                  ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
1045                  if (ret) {
1046                          DRM_ERROR("Failed at platform attch func\n");
1047                          return ret;
1048                  }
1049         }
1050
1051         if (dp->plat_data->panel) {
1052                 ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
1053                 if (ret) {
1054                         DRM_ERROR("Failed to attach panel\n");
1055                         return ret;
1056                 }
1057         }
1058
1059         return 0;
1060 }
1061
1062 static void analogix_dp_bridge_pre_enable(struct drm_bridge *bridge)
1063 {
1064         struct analogix_dp_device *dp = bridge->driver_private;
1065         int ret;
1066
1067         ret = analogix_dp_prepare_panel(dp, true, true);
1068         if (ret)
1069                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1070 }
1071
1072 static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
1073 {
1074         struct analogix_dp_device *dp = bridge->driver_private;
1075
1076         if (dp->dpms_mode == DRM_MODE_DPMS_ON)
1077                 return;
1078
1079         pm_runtime_get_sync(dp->dev);
1080
1081         if (dp->plat_data->power_on)
1082                 dp->plat_data->power_on(dp->plat_data);
1083
1084         phy_power_on(dp->phy);
1085         analogix_dp_init_dp(dp);
1086         enable_irq(dp->irq);
1087         analogix_dp_commit(dp);
1088
1089         dp->dpms_mode = DRM_MODE_DPMS_ON;
1090 }
1091
1092 static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
1093 {
1094         struct analogix_dp_device *dp = bridge->driver_private;
1095         int ret;
1096
1097         if (dp->dpms_mode != DRM_MODE_DPMS_ON)
1098                 return;
1099
1100         if (dp->plat_data->panel) {
1101                 if (drm_panel_disable(dp->plat_data->panel)) {
1102                         DRM_ERROR("failed to disable the panel\n");
1103                         return;
1104                 }
1105         }
1106
1107         disable_irq(dp->irq);
1108         phy_power_off(dp->phy);
1109
1110         if (dp->plat_data->power_off)
1111                 dp->plat_data->power_off(dp->plat_data);
1112
1113         pm_runtime_put_sync(dp->dev);
1114
1115         ret = analogix_dp_prepare_panel(dp, false, true);
1116         if (ret)
1117                 DRM_ERROR("failed to setup the panel ret = %d\n", ret);
1118
1119         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1120 }
1121
1122 static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
1123                                         struct drm_display_mode *orig_mode,
1124                                         struct drm_display_mode *mode)
1125 {
1126         struct analogix_dp_device *dp = bridge->driver_private;
1127         struct drm_display_info *display_info = &dp->connector.display_info;
1128         struct video_info *video = &dp->video_info;
1129         struct device_node *dp_node = dp->dev->of_node;
1130         int vic;
1131
1132         /* Input video interlaces & hsync pol & vsync pol */
1133         video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
1134         video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
1135         video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
1136
1137         /* Input video dynamic_range & colorimetry */
1138         vic = drm_match_cea_mode(mode);
1139         if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
1140             (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
1141                 video->dynamic_range = CEA;
1142                 video->ycbcr_coeff = COLOR_YCBCR601;
1143         } else if (vic) {
1144                 video->dynamic_range = CEA;
1145                 video->ycbcr_coeff = COLOR_YCBCR709;
1146         } else {
1147                 video->dynamic_range = VESA;
1148                 video->ycbcr_coeff = COLOR_YCBCR709;
1149         }
1150
1151         /* Input vide bpc and color_formats */
1152         switch (display_info->bpc) {
1153         case 12:
1154                 video->color_depth = COLOR_12;
1155                 break;
1156         case 10:
1157                 video->color_depth = COLOR_10;
1158                 break;
1159         case 8:
1160                 video->color_depth = COLOR_8;
1161                 break;
1162         case 6:
1163                 video->color_depth = COLOR_6;
1164                 break;
1165         default:
1166                 video->color_depth = COLOR_8;
1167                 break;
1168         }
1169         if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
1170                 video->color_space = COLOR_YCBCR444;
1171         else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
1172                 video->color_space = COLOR_YCBCR422;
1173         else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
1174                 video->color_space = COLOR_RGB;
1175         else
1176                 video->color_space = COLOR_RGB;
1177
1178         /*
1179          * NOTE: those property parsing code is used for providing backward
1180          * compatibility for samsung platform.
1181          * Due to we used the "of_property_read_u32" interfaces, when this
1182          * property isn't present, the "video_info" can keep the original
1183          * values and wouldn't be modified.
1184          */
1185         of_property_read_u32(dp_node, "samsung,color-space",
1186                              &video->color_space);
1187         of_property_read_u32(dp_node, "samsung,dynamic-range",
1188                              &video->dynamic_range);
1189         of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
1190                              &video->ycbcr_coeff);
1191         of_property_read_u32(dp_node, "samsung,color-depth",
1192                              &video->color_depth);
1193         if (of_property_read_bool(dp_node, "hsync-active-high"))
1194                 video->h_sync_polarity = true;
1195         if (of_property_read_bool(dp_node, "vsync-active-high"))
1196                 video->v_sync_polarity = true;
1197         if (of_property_read_bool(dp_node, "interlaced"))
1198                 video->interlaced = true;
1199 }
1200
1201 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
1202 {
1203         /* do nothing */
1204 }
1205
1206 static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
1207         .pre_enable = analogix_dp_bridge_pre_enable,
1208         .enable = analogix_dp_bridge_enable,
1209         .disable = analogix_dp_bridge_disable,
1210         .post_disable = analogix_dp_bridge_nop,
1211         .mode_set = analogix_dp_bridge_mode_set,
1212         .attach = analogix_dp_bridge_attach,
1213 };
1214
1215 static int analogix_dp_create_bridge(struct drm_device *drm_dev,
1216                                      struct analogix_dp_device *dp)
1217 {
1218         struct drm_bridge *bridge;
1219         int ret;
1220
1221         bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
1222         if (!bridge) {
1223                 DRM_ERROR("failed to allocate for drm bridge\n");
1224                 return -ENOMEM;
1225         }
1226
1227         dp->bridge = bridge;
1228
1229         dp->encoder->bridge = bridge;
1230         bridge->driver_private = dp;
1231         bridge->encoder = dp->encoder;
1232         bridge->funcs = &analogix_dp_bridge_funcs;
1233
1234         ret = drm_bridge_attach(drm_dev, bridge);
1235         if (ret) {
1236                 DRM_ERROR("failed to attach drm bridge\n");
1237                 return -EINVAL;
1238         }
1239
1240         return 0;
1241 }
1242
1243 static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
1244 {
1245         struct device_node *dp_node = dp->dev->of_node;
1246         struct video_info *video_info = &dp->video_info;
1247
1248         switch (dp->plat_data->dev_type) {
1249         case RK3288_DP:
1250         case RK3399_EDP:
1251                 /*
1252                  * Like Rk3288 DisplayPort TRM indicate that "Main link
1253                  * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
1254                  */
1255                 video_info->max_link_rate = 0x0A;
1256                 video_info->max_lane_count = 0x04;
1257                 break;
1258         case EXYNOS_DP:
1259                 /*
1260                  * NOTE: those property parseing code is used for
1261                  * providing backward compatibility for samsung platform.
1262                  */
1263                 of_property_read_u32(dp_node, "samsung,link-rate",
1264                                      &video_info->max_link_rate);
1265                 of_property_read_u32(dp_node, "samsung,lane-count",
1266                                      &video_info->max_lane_count);
1267                 break;
1268         }
1269
1270         return 0;
1271 }
1272
1273 static ssize_t analogix_dpaux_transfer(struct drm_dp_aux *aux,
1274                                        struct drm_dp_aux_msg *msg)
1275 {
1276         struct analogix_dp_device *dp = to_dp(aux);
1277
1278         return analogix_dp_transfer(dp, msg);
1279 }
1280
1281 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
1282                      struct analogix_dp_plat_data *plat_data)
1283 {
1284         struct platform_device *pdev = to_platform_device(dev);
1285         struct analogix_dp_device *dp;
1286         struct resource *res;
1287         unsigned int irq_flags;
1288         int ret;
1289
1290         if (!plat_data) {
1291                 dev_err(dev, "Invalided input plat_data\n");
1292                 return -EINVAL;
1293         }
1294
1295         dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
1296         if (!dp)
1297                 return -ENOMEM;
1298
1299         dev_set_drvdata(dev, dp);
1300
1301         dp->dev = &pdev->dev;
1302         dp->dpms_mode = DRM_MODE_DPMS_OFF;
1303
1304         mutex_init(&dp->panel_lock);
1305         dp->panel_is_modeset = false;
1306
1307         /*
1308          * platform dp driver need containor_of the plat_data to get
1309          * the driver private data, so we need to store the point of
1310          * plat_data, not the context of plat_data.
1311          */
1312         dp->plat_data = plat_data;
1313
1314         ret = analogix_dp_dt_parse_pdata(dp);
1315         if (ret)
1316                 return ret;
1317
1318         dp->phy = devm_phy_get(dp->dev, "dp");
1319         if (IS_ERR(dp->phy)) {
1320                 dev_err(dp->dev, "no DP phy configured\n");
1321                 ret = PTR_ERR(dp->phy);
1322                 if (ret) {
1323                         /*
1324                          * phy itself is not enabled, so we can move forward
1325                          * assigning NULL to phy pointer.
1326                          */
1327                         if (ret == -ENOSYS || ret == -ENODEV)
1328                                 dp->phy = NULL;
1329                         else
1330                                 return ret;
1331                 }
1332         }
1333
1334         dp->clock = devm_clk_get(&pdev->dev, "dp");
1335         if (IS_ERR(dp->clock)) {
1336                 dev_err(&pdev->dev, "failed to get clock\n");
1337                 return PTR_ERR(dp->clock);
1338         }
1339
1340         clk_prepare_enable(dp->clock);
1341
1342         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1343
1344         dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
1345         if (IS_ERR(dp->reg_base))
1346                 return PTR_ERR(dp->reg_base);
1347
1348         dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
1349
1350         dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
1351         if (!gpio_is_valid(dp->hpd_gpio))
1352                 dp->hpd_gpio = of_get_named_gpio(dev->of_node,
1353                                                  "samsung,hpd-gpio", 0);
1354
1355         if (gpio_is_valid(dp->hpd_gpio)) {
1356                 /*
1357                  * Set up the hotplug GPIO from the device tree as an interrupt.
1358                  * Simply specifying a different interrupt in the device tree
1359                  * doesn't work since we handle hotplug rather differently when
1360                  * using a GPIO.  We also need the actual GPIO specifier so
1361                  * that we can get the current state of the GPIO.
1362                  */
1363                 ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
1364                                             "hpd_gpio");
1365                 if (ret) {
1366                         dev_err(&pdev->dev, "failed to get hpd gpio\n");
1367                         return ret;
1368                 }
1369                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1370                 irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1371         } else {
1372                 dp->hpd_gpio = -ENODEV;
1373                 dp->irq = platform_get_irq(pdev, 0);
1374                 irq_flags = 0;
1375         }
1376
1377         if (dp->irq == -ENXIO) {
1378                 dev_err(&pdev->dev, "failed to get irq\n");
1379                 return -ENODEV;
1380         }
1381
1382         pm_runtime_enable(dev);
1383
1384         phy_power_on(dp->phy);
1385
1386         analogix_dp_init_dp(dp);
1387
1388         ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
1389                                         analogix_dp_hardirq,
1390                                         analogix_dp_irq_thread,
1391                                         irq_flags, "analogix-dp", dp);
1392         if (ret) {
1393                 dev_err(&pdev->dev, "failed to request irq\n");
1394                 goto err_disable_pm_runtime;
1395         }
1396         disable_irq(dp->irq);
1397
1398         dp->drm_dev = drm_dev;
1399         dp->encoder = dp->plat_data->encoder;
1400
1401         dp->aux.name = "DP-AUX";
1402         dp->aux.transfer = analogix_dpaux_transfer;
1403         dp->aux.dev = &pdev->dev;
1404
1405         ret = drm_dp_aux_register(&dp->aux);
1406         if (ret)
1407                 goto err_disable_pm_runtime;
1408
1409         ret = analogix_dp_create_bridge(drm_dev, dp);
1410         if (ret) {
1411                 DRM_ERROR("failed to create bridge (%d)\n", ret);
1412                 drm_encoder_cleanup(dp->encoder);
1413                 goto err_disable_pm_runtime;
1414         }
1415
1416         return 0;
1417
1418 err_disable_pm_runtime:
1419         pm_runtime_disable(dev);
1420
1421         return ret;
1422 }
1423 EXPORT_SYMBOL_GPL(analogix_dp_bind);
1424
1425 void analogix_dp_unbind(struct device *dev, struct device *master,
1426                         void *data)
1427 {
1428         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1429
1430         analogix_dp_bridge_disable(dp->bridge);
1431
1432         if (dp->plat_data->panel) {
1433                 if (drm_panel_unprepare(dp->plat_data->panel))
1434                         DRM_ERROR("failed to turnoff the panel\n");
1435         }
1436
1437         pm_runtime_disable(dev);
1438 }
1439 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
1440
1441 #ifdef CONFIG_PM
1442 int analogix_dp_suspend(struct device *dev)
1443 {
1444         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1445
1446         clk_disable_unprepare(dp->clock);
1447
1448         if (dp->plat_data->panel) {
1449                 if (drm_panel_unprepare(dp->plat_data->panel))
1450                         DRM_ERROR("failed to turnoff the panel\n");
1451         }
1452
1453         return 0;
1454 }
1455 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
1456
1457 int analogix_dp_resume(struct device *dev)
1458 {
1459         struct analogix_dp_device *dp = dev_get_drvdata(dev);
1460         int ret;
1461
1462         ret = clk_prepare_enable(dp->clock);
1463         if (ret < 0) {
1464                 DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
1465                 return ret;
1466         }
1467
1468         if (dp->plat_data->panel) {
1469                 if (drm_panel_prepare(dp->plat_data->panel)) {
1470                         DRM_ERROR("failed to setup the panel\n");
1471                         return -EBUSY;
1472                 }
1473         }
1474
1475         return 0;
1476 }
1477 EXPORT_SYMBOL_GPL(analogix_dp_resume);
1478 #endif
1479
1480 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1481 MODULE_DESCRIPTION("Analogix DP Core Driver");
1482 MODULE_LICENSE("GPL v2");