drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h

   1 /*
   2  * Register definition file for Analogix DP core driver
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #ifndef _ANALOGIX_DP_REG_H
  13 #define _ANALOGIX_DP_REG_H
  14
  15 #define ANALOGIX_DP_TX_SW_RESET                 0x14
  16 #define ANALOGIX_DP_FUNC_EN_1                   0x18
  17 #define ANALOGIX_DP_FUNC_EN_2                   0x1C
  18 #define ANALOGIX_DP_VIDEO_CTL_1                 0x20
  19 #define ANALOGIX_DP_VIDEO_CTL_2                 0x24
  20 #define ANALOGIX_DP_VIDEO_CTL_3                 0x28
  21
  22 #define ANALOGIX_DP_VIDEO_CTL_8                 0x3C
  23 #define ANALOGIX_DP_VIDEO_CTL_10                0x44
  24
  25 #define ANALOGIX_DP_PLL_REG_1                   0xfc
  26 #define ANALOGIX_DP_PLL_REG_2                   0x9e4
  27 #define ANALOGIX_DP_PLL_REG_3                   0x9e8
  28 #define ANALOGIX_DP_PLL_REG_4                   0x9ec
  29 #define ANALOGIX_DP_PLL_REG_5                   0xa00
  30
  31 #define ANALOGIX_DP_PD                          0x12c
  32
  33 #define ANALOGIX_DP_LANE_MAP                    0x35C
  34
  35 #define ANALOGIX_DP_ANALOG_CTL_1                0x370
  36 #define ANALOGIX_DP_ANALOG_CTL_2                0x374
  37 #define ANALOGIX_DP_ANALOG_CTL_3                0x378
  38 #define ANALOGIX_DP_PLL_FILTER_CTL_1            0x37C
  39 #define ANALOGIX_DP_TX_AMP_TUNING_CTL           0x380
  40
  41 #define ANALOGIX_DP_AUX_HW_RETRY_CTL            0x390
  42
  43 #define ANALOGIX_DP_COMMON_INT_STA_1            0x3C4
  44 #define ANALOGIX_DP_COMMON_INT_STA_2            0x3C8
  45 #define ANALOGIX_DP_COMMON_INT_STA_3            0x3CC
  46 #define ANALOGIX_DP_COMMON_INT_STA_4            0x3D0
  47 #define ANALOGIX_DP_INT_STA                     0x3DC
  48 #define ANALOGIX_DP_COMMON_INT_MASK_1           0x3E0
  49 #define ANALOGIX_DP_COMMON_INT_MASK_2           0x3E4
  50 #define ANALOGIX_DP_COMMON_INT_MASK_3           0x3E8
  51 #define ANALOGIX_DP_COMMON_INT_MASK_4           0x3EC
  52 #define ANALOGIX_DP_INT_STA_MASK                0x3F8
  53 #define ANALOGIX_DP_INT_CTL                     0x3FC
  54
  55 #define ANALOGIX_DP_SYS_CTL_1                   0x600
  56 #define ANALOGIX_DP_SYS_CTL_2                   0x604
  57 #define ANALOGIX_DP_SYS_CTL_3                   0x608
  58 #define ANALOGIX_DP_SYS_CTL_4                   0x60C
  59
  60 #define ANALOGIX_DP_PKT_SEND_CTL                0x640
  61 #define ANALOGIX_DP_HDCP_CTL                    0x648
  62
  63 #define ANALOGIX_DP_LINK_BW_SET                 0x680
  64 #define ANALOGIX_DP_LANE_COUNT_SET              0x684
  65 #define ANALOGIX_DP_TRAINING_PTN_SET            0x688
  66 #define ANALOGIX_DP_LN0_LINK_TRAINING_CTL       0x68C
  67 #define ANALOGIX_DP_LN1_LINK_TRAINING_CTL       0x690
  68 #define ANALOGIX_DP_LN2_LINK_TRAINING_CTL       0x694
  69 #define ANALOGIX_DP_LN3_LINK_TRAINING_CTL       0x698
  70
  71 #define ANALOGIX_DP_DEBUG_CTL                   0x6C0
  72 #define ANALOGIX_DP_HPD_DEGLITCH_L              0x6C4
  73 #define ANALOGIX_DP_HPD_DEGLITCH_H              0x6C8
  74 #define ANALOGIX_DP_LINK_DEBUG_CTL              0x6E0
  75
  76 #define ANALOGIX_DP_M_VID_0                     0x700
  77 #define ANALOGIX_DP_M_VID_1                     0x704
  78 #define ANALOGIX_DP_M_VID_2                     0x708
  79 #define ANALOGIX_DP_N_VID_0                     0x70C
  80 #define ANALOGIX_DP_N_VID_1                     0x710
  81 #define ANALOGIX_DP_N_VID_2                     0x714
  82
  83 #define ANALOGIX_DP_PLL_CTL                     0x71C
  84 #define ANALOGIX_DP_PHY_PD                      0x720
  85 #define ANALOGIX_DP_PHY_TEST                    0x724
  86
  87 #define ANALOGIX_DP_VIDEO_FIFO_THRD             0x730
  88 #define ANALOGIX_DP_AUDIO_MARGIN                0x73C
  89
  90 #define ANALOGIX_DP_M_VID_GEN_FILTER_TH         0x764
  91 #define ANALOGIX_DP_M_AUD_GEN_FILTER_TH         0x778
  92 #define ANALOGIX_DP_AUX_CH_STA                  0x780
  93 #define ANALOGIX_DP_AUX_CH_DEFER_CTL            0x788
  94 #define ANALOGIX_DP_AUX_RX_COMM                 0x78C
  95 #define ANALOGIX_DP_BUFFER_DATA_CTL             0x790
  96 #define ANALOGIX_DP_AUX_CH_CTL_1                0x794
  97 #define ANALOGIX_DP_AUX_ADDR_7_0                0x798
  98 #define ANALOGIX_DP_AUX_ADDR_15_8               0x79C
  99 #define ANALOGIX_DP_AUX_ADDR_19_16              0x7A0
 100 #define ANALOGIX_DP_AUX_CH_CTL_2                0x7A4
 101
 102 #define ANALOGIX_DP_BUF_DATA_0                  0x7C0
 103
 104 #define ANALOGIX_DP_SOC_GENERAL_CTL             0x800
 105
 106 /* ANALOGIX_DP_TX_SW_RESET */
 107 #define RESET_DP_TX                             (0x1 << 0)
 108
 109 /* ANALOGIX_DP_FUNC_EN_1 */
 110 #define MASTER_VID_FUNC_EN_N                    (0x1 << 7)
 111 #define SLAVE_VID_FUNC_EN_N                     (0x1 << 5)
 112 #define AUD_FIFO_FUNC_EN_N                      (0x1 << 4)
 113 #define AUD_FUNC_EN_N                           (0x1 << 3)
 114 #define HDCP_FUNC_EN_N                          (0x1 << 2)
 115 #define CRC_FUNC_EN_N                           (0x1 << 1)
 116 #define SW_FUNC_EN_N                            (0x1 << 0)
 117
 118 /* ANALOGIX_DP_FUNC_EN_2 */
 119 #define SSC_FUNC_EN_N                           (0x1 << 7)
 120 #define AUX_FUNC_EN_N                           (0x1 << 2)
 121 #define SERDES_FIFO_FUNC_EN_N                   (0x1 << 1)
 122 #define LS_CLK_DOMAIN_FUNC_EN_N                 (0x1 << 0)
 123
 124 /* ANALOGIX_DP_VIDEO_CTL_1 */
 125 #define VIDEO_EN                                (0x1 << 7)
 126 #define HDCP_VIDEO_MUTE                         (0x1 << 6)
 127
 128 /* ANALOGIX_DP_VIDEO_CTL_1 */
 129 #define IN_D_RANGE_MASK                         (0x1 << 7)
 130 #define IN_D_RANGE_SHIFT                        (7)
 131 #define IN_D_RANGE_CEA                          (0x1 << 7)
 132 #define IN_D_RANGE_VESA                         (0x0 << 7)
 133 #define IN_BPC_MASK                             (0x7 << 4)
 134 #define IN_BPC_SHIFT                            (4)
 135 #define IN_BPC_12_BITS                          (0x3 << 4)
 136 #define IN_BPC_10_BITS                          (0x2 << 4)
 137 #define IN_BPC_8_BITS                           (0x1 << 4)
 138 #define IN_BPC_6_BITS                           (0x0 << 4)
 139 #define IN_COLOR_F_MASK                         (0x3 << 0)
 140 #define IN_COLOR_F_SHIFT                        (0)
 141 #define IN_COLOR_F_YCBCR444                     (0x2 << 0)
 142 #define IN_COLOR_F_YCBCR422                     (0x1 << 0)
 143 #define IN_COLOR_F_RGB                          (0x0 << 0)
 144
 145 /* ANALOGIX_DP_VIDEO_CTL_3 */
 146 #define IN_YC_COEFFI_MASK                       (0x1 << 7)
 147 #define IN_YC_COEFFI_SHIFT                      (7)
 148 #define IN_YC_COEFFI_ITU709                     (0x1 << 7)
 149 #define IN_YC_COEFFI_ITU601                     (0x0 << 7)
 150 #define VID_CHK_UPDATE_TYPE_MASK                (0x1 << 4)
 151 #define VID_CHK_UPDATE_TYPE_SHIFT               (4)
 152 #define VID_CHK_UPDATE_TYPE_1                   (0x1 << 4)
 153 #define VID_CHK_UPDATE_TYPE_0                   (0x0 << 4)
 154
 155 /* ANALOGIX_DP_VIDEO_CTL_8 */
 156 #define VID_HRES_TH(x)                          (((x) & 0xf) << 4)
 157 #define VID_VRES_TH(x)                          (((x) & 0xf) << 0)
 158
 159 /* ANALOGIX_DP_VIDEO_CTL_10 */
 160 #define FORMAT_SEL                              (0x1 << 4)
 161 #define INTERACE_SCAN_CFG                       (0x1 << 2)
 162 #define VSYNC_POLARITY_CFG                      (0x1 << 1)
 163 #define HSYNC_POLARITY_CFG                      (0x1 << 0)
 164
 165 /* ANALOGIX_DP_PLL_REG_1 */
 166 #define REF_CLK_24M                             (0x1 << 1)
 167 #define REF_CLK_27M                             (0x0 << 1)
 168
 169 /* ANALOGIX_DP_LANE_MAP */
 170 #define LANE3_MAP_LOGIC_LANE_0                  (0x0 << 6)
 171 #define LANE3_MAP_LOGIC_LANE_1                  (0x1 << 6)
 172 #define LANE3_MAP_LOGIC_LANE_2                  (0x2 << 6)
 173 #define LANE3_MAP_LOGIC_LANE_3                  (0x3 << 6)
 174 #define LANE2_MAP_LOGIC_LANE_0                  (0x0 << 4)
 175 #define LANE2_MAP_LOGIC_LANE_1                  (0x1 << 4)
 176 #define LANE2_MAP_LOGIC_LANE_2                  (0x2 << 4)
 177 #define LANE2_MAP_LOGIC_LANE_3                  (0x3 << 4)
 178 #define LANE1_MAP_LOGIC_LANE_0                  (0x0 << 2)
 179 #define LANE1_MAP_LOGIC_LANE_1                  (0x1 << 2)
 180 #define LANE1_MAP_LOGIC_LANE_2                  (0x2 << 2)
 181 #define LANE1_MAP_LOGIC_LANE_3                  (0x3 << 2)
 182 #define LANE0_MAP_LOGIC_LANE_0                  (0x0 << 0)
 183 #define LANE0_MAP_LOGIC_LANE_1                  (0x1 << 0)
 184 #define LANE0_MAP_LOGIC_LANE_2                  (0x2 << 0)
 185 #define LANE0_MAP_LOGIC_LANE_3                  (0x3 << 0)
 186
 187 /* ANALOGIX_DP_ANALOG_CTL_1 */
 188 #define TX_TERMINAL_CTRL_50_OHM                 (0x1 << 4)
 189
 190 /* ANALOGIX_DP_ANALOG_CTL_2 */
 191 #define SEL_24M                                 (0x1 << 3)
 192 #define TX_DVDD_BIT_1_0625V                     (0x4 << 0)
 193
 194 /* ANALOGIX_DP_ANALOG_CTL_3 */
 195 #define DRIVE_DVDD_BIT_1_0625V                  (0x4 << 5)
 196 #define VCO_BIT_600_MICRO                       (0x5 << 0)
 197
 198 /* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 199 #define PD_RING_OSC                             (0x1 << 6)
 200 #define AUX_TERMINAL_CTRL_50_OHM                (0x2 << 4)
 201 #define TX_CUR1_2X                              (0x1 << 2)
 202 #define TX_CUR_16_MA                            (0x3 << 0)
 203
 204 /* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 205 #define CH3_AMP_400_MV                          (0x0 << 24)
 206 #define CH2_AMP_400_MV                          (0x0 << 16)
 207 #define CH1_AMP_400_MV                          (0x0 << 8)
 208 #define CH0_AMP_400_MV                          (0x0 << 0)
 209
 210 /* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 211 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)        (((x) & 0x7) << 8)
 212 #define AUX_HW_RETRY_INTERVAL_MASK              (0x3 << 3)
 213 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS  (0x0 << 3)
 214 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS  (0x1 << 3)
 215 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
 216 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
 217 #define AUX_HW_RETRY_COUNT_SEL(x)               (((x) & 0x7) << 0)
 218
 219 /* ANALOGIX_DP_COMMON_INT_STA_1 */
 220 #define VSYNC_DET                               (0x1 << 7)
 221 #define PLL_LOCK_CHG                            (0x1 << 6)
 222 #define SPDIF_ERR                               (0x1 << 5)
 223 #define SPDIF_UNSTBL                            (0x1 << 4)
 224 #define VID_FORMAT_CHG                          (0x1 << 3)
 225 #define AUD_CLK_CHG                             (0x1 << 2)
 226 #define VID_CLK_CHG                             (0x1 << 1)
 227 #define SW_INT                                  (0x1 << 0)
 228
 229 /* ANALOGIX_DP_COMMON_INT_STA_2 */
 230 #define ENC_EN_CHG                              (0x1 << 6)
 231 #define HW_BKSV_RDY                             (0x1 << 3)
 232 #define HW_SHA_DONE                             (0x1 << 2)
 233 #define HW_AUTH_STATE_CHG                       (0x1 << 1)
 234 #define HW_AUTH_DONE                            (0x1 << 0)
 235
 236 /* ANALOGIX_DP_COMMON_INT_STA_3 */
 237 #define AFIFO_UNDER                             (0x1 << 7)
 238 #define AFIFO_OVER                              (0x1 << 6)
 239 #define R0_CHK_FLAG                             (0x1 << 5)
 240
 241 /* ANALOGIX_DP_COMMON_INT_STA_4 */
 242 #define PSR_ACTIVE                              (0x1 << 7)
 243 #define PSR_INACTIVE                            (0x1 << 6)
 244 #define SPDIF_BI_PHASE_ERR                      (0x1 << 5)
 245 #define HOTPLUG_CHG                             (0x1 << 2)
 246 #define HPD_LOST                                (0x1 << 1)
 247 #define PLUG                                    (0x1 << 0)
 248
 249 /* ANALOGIX_DP_INT_STA */
 250 #define INT_HPD                                 (0x1 << 6)
 251 #define HW_TRAINING_FINISH                      (0x1 << 5)
 252 #define RPLY_RECEIV                             (0x1 << 1)
 253 #define AUX_ERR                                 (0x1 << 0)
 254
 255 /* ANALOGIX_DP_INT_CTL */
 256 #define SOFT_INT_CTRL                           (0x1 << 2)
 257 #define INT_POL1                                (0x1 << 1)
 258 #define INT_POL0                                (0x1 << 0)
 259
 260 /* ANALOGIX_DP_SYS_CTL_1 */
 261 #define DET_STA                                 (0x1 << 2)
 262 #define FORCE_DET                               (0x1 << 1)
 263 #define DET_CTRL                                (0x1 << 0)
 264
 265 /* ANALOGIX_DP_SYS_CTL_2 */
 266 #define CHA_CRI(x)                              (((x) & 0xf) << 4)
 267 #define CHA_STA                                 (0x1 << 2)
 268 #define FORCE_CHA                               (0x1 << 1)
 269 #define CHA_CTRL                                (0x1 << 0)
 270
 271 /* ANALOGIX_DP_SYS_CTL_3 */
 272 #define HPD_STATUS                              (0x1 << 6)
 273 #define F_HPD                                   (0x1 << 5)
 274 #define HPD_CTRL                                (0x1 << 4)
 275 #define HDCP_RDY                                (0x1 << 3)
 276 #define STRM_VALID                              (0x1 << 2)
 277 #define F_VALID                                 (0x1 << 1)
 278 #define VALID_CTRL                              (0x1 << 0)
 279
 280 /* ANALOGIX_DP_SYS_CTL_4 */
 281 #define FIX_M_AUD                               (0x1 << 4)
 282 #define ENHANCED                                (0x1 << 3)
 283 #define FIX_M_VID                               (0x1 << 2)
 284 #define M_VID_UPDATE_CTRL                       (0x3 << 0)
 285
 286 /* ANALOGIX_DP_TRAINING_PTN_SET */
 287 #define SCRAMBLER_TYPE                          (0x1 << 9)
 288 #define HW_LINK_TRAINING_PATTERN                (0x1 << 8)
 289 #define SCRAMBLING_DISABLE                      (0x1 << 5)
 290 #define SCRAMBLING_ENABLE                       (0x0 << 5)
 291 #define LINK_QUAL_PATTERN_SET_MASK              (0x3 << 2)
 292 #define LINK_QUAL_PATTERN_SET_PRBS7             (0x3 << 2)
 293 #define LINK_QUAL_PATTERN_SET_D10_2             (0x1 << 2)
 294 #define LINK_QUAL_PATTERN_SET_DISABLE           (0x0 << 2)
 295 #define SW_TRAINING_PATTERN_SET_MASK            (0x3 << 0)
 296 #define SW_TRAINING_PATTERN_SET_PTN2            (0x2 << 0)
 297 #define SW_TRAINING_PATTERN_SET_PTN1            (0x1 << 0)
 298 #define SW_TRAINING_PATTERN_SET_NORMAL          (0x0 << 0)
 299
 300 /* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 301 #define PRE_EMPHASIS_SET_MASK                   (0x3 << 3)
 302 #define PRE_EMPHASIS_SET_SHIFT                  (3)
 303
 304 /* ANALOGIX_DP_DEBUG_CTL */
 305 #define PLL_LOCK                                (0x1 << 4)
 306 #define F_PLL_LOCK                              (0x1 << 3)
 307 #define PLL_LOCK_CTRL                           (0x1 << 2)
 308 #define PN_INV                                  (0x1 << 0)
 309
 310 /* ANALOGIX_DP_PLL_CTL */
 311 #define DP_PLL_PD                               (0x1 << 7)
 312 #define DP_PLL_RESET                            (0x1 << 6)
 313 #define DP_PLL_LOOP_BIT_DEFAULT                 (0x1 << 4)
 314 #define DP_PLL_REF_BIT_1_1250V                  (0x5 << 0)
 315 #define DP_PLL_REF_BIT_1_2500V                  (0x7 << 0)
 316
 317 /* ANALOGIX_DP_PHY_PD */
 318 #define DP_PHY_PD                               (0x1 << 5)
 319 #define AUX_PD                                  (0x1 << 4)
 320 #define CH3_PD                                  (0x1 << 3)
 321 #define CH2_PD                                  (0x1 << 2)
 322 #define CH1_PD                                  (0x1 << 1)
 323 #define CH0_PD                                  (0x1 << 0)
 324
 325 /* ANALOGIX_DP_PHY_TEST */
 326 #define MACRO_RST                               (0x1 << 5)
 327 #define CH1_TEST                                (0x1 << 1)
 328 #define CH0_TEST                                (0x1 << 0)
 329
 330 /* ANALOGIX_DP_AUX_CH_STA */
 331 #define AUX_BUSY                                (0x1 << 4)
 332 #define AUX_STATUS_MASK                         (0xf << 0)
 333
 334 /* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 335 #define DEFER_CTRL_EN                           (0x1 << 7)
 336 #define DEFER_COUNT(x)                          (((x) & 0x7f) << 0)
 337
 338 /* ANALOGIX_DP_AUX_RX_COMM */
 339 #define AUX_RX_COMM_I2C_DEFER                   (0x2 << 2)
 340 #define AUX_RX_COMM_AUX_DEFER                   (0x2 << 0)
 341
 342 /* ANALOGIX_DP_BUFFER_DATA_CTL */
 343 #define BUF_CLR                                 (0x1 << 7)
 344 #define BUF_DATA_COUNT(x)                       (((x) & 0x1f) << 0)
 345
 346 /* ANALOGIX_DP_AUX_CH_CTL_1 */
 347 #define AUX_LENGTH(x)                           (((x - 1) & 0xf) << 4)
 348 #define AUX_TX_COMM_MASK                        (0xf << 0)
 349 #define AUX_TX_COMM_DP_TRANSACTION              (0x1 << 3)
 350 #define AUX_TX_COMM_I2C_TRANSACTION             (0x0 << 3)
 351 #define AUX_TX_COMM_MOT                         (0x1 << 2)
 352 #define AUX_TX_COMM_WRITE                       (0x0 << 0)
 353 #define AUX_TX_COMM_READ                        (0x1 << 0)
 354
 355 /* ANALOGIX_DP_AUX_ADDR_7_0 */
 356 #define AUX_ADDR_7_0(x)                         (((x) >> 0) & 0xff)
 357
 358 /* ANALOGIX_DP_AUX_ADDR_15_8 */
 359 #define AUX_ADDR_15_8(x)                        (((x) >> 8) & 0xff)
 360
 361 /* ANALOGIX_DP_AUX_ADDR_19_16 */
 362 #define AUX_ADDR_19_16(x)                       (((x) >> 16) & 0x0f)
 363
 364 /* ANALOGIX_DP_AUX_CH_CTL_2 */
 365 #define ADDR_ONLY                               (0x1 << 1)
 366 #define AUX_EN                                  (0x1 << 0)
 367
 368 /* ANALOGIX_DP_SOC_GENERAL_CTL */
 369 #define AUDIO_MODE_SPDIF_MODE                   (0x1 << 8)
 370 #define AUDIO_MODE_MASTER_MODE                  (0x0 << 8)
 371 #define MASTER_VIDEO_INTERLACE_EN               (0x1 << 4)
 372 #define VIDEO_MASTER_CLK_SEL                    (0x1 << 2)
 373 #define VIDEO_MASTER_MODE_EN                    (0x1 << 1)
 374 #define VIDEO_MODE_MASK                         (0x1 << 0)
 375 #define VIDEO_MODE_SLAVE_MODE                   (0x1 << 0)
 376 #define VIDEO_MODE_MASTER_MODE                  (0x0 << 0)
 377
 378 #endif /* _ANALOGIX_DP_REG_H */