2 * Copyright (C) 2013 Google, Inc.
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * Based on code obtained from Analogix Inc with copyright:
14 * Copyright(c) 2012, Analogix Semiconductor. All rights reserved.
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/i2c.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of_gpio.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/workqueue.h>
27 #include "anx7808regs.h"
29 #define ANX7808_DEVICE_ID 0x7808
30 #define AUX_WAIT_MS 100
31 #define AUX_BUFFER_SIZE 0x10
32 #define CABLE_DET_TIME_MS 1000
48 struct timer_list cable_det_timer;
49 struct regulator *vdd_mydp;
50 struct i2c_client *tx_p0;
51 struct i2c_client *tx_p1;
52 struct i2c_client *tx_p2;
53 struct i2c_client *rx_p0;
54 struct i2c_client *rx_p1;
55 struct delayed_work play_video;
56 struct workqueue_struct *wq;
59 static struct i2c_client *anx7808_addr_to_client(struct anx7808_data *anx7808,
64 return anx7808->tx_p0;
66 return anx7808->tx_p1;
68 return anx7808->tx_p2;
70 return anx7808->rx_p0;
72 return anx7808->rx_p1;
76 DRM_ERROR("Invalid i2c address %04x.\n", addr);
80 static int anx7808_read_reg(struct anx7808_data *anx7808, uint16_t addr,
84 struct i2c_client *client = anx7808_addr_to_client(anx7808, addr);
91 ret = i2c_smbus_read_byte_data(client, addr & 0xFF);
93 DRM_ERROR("Failed to read i2c addr=%04x.\n", addr);
101 static int anx7808_write_reg(struct anx7808_data *anx7808, uint16_t addr,
105 struct i2c_client *client = anx7808_addr_to_client(anx7808, addr);
110 ret = i2c_smbus_write_byte_data(client, addr & 0xFF, value);
112 DRM_ERROR("Failed to write i2c addr=%04x.\n", addr);
118 static int anx7808_set_bits(struct anx7808_data *anx7808, uint16_t addr,
123 ret = anx7808_read_reg(anx7808, addr, &c);
126 return anx7808_write_reg(anx7808, addr, c | bits);
129 static int anx7808_clear_bits(struct anx7808_data *anx7808, uint16_t addr,
134 ret = anx7808_read_reg(anx7808, addr, &c);
137 return anx7808_write_reg(anx7808, addr, c & (~bits));
140 static int anx7808_power_on(struct anx7808_data *anx7808)
144 DRM_INFO("Powering on ANX7808.\n");
146 gpio_set_value(anx7808->reset_gpio, 0);
147 usleep_range(1000, 2000);
148 gpio_set_value(anx7808->pd_gpio, 0);
149 usleep_range(2000, 4000);
150 ret = regulator_enable(anx7808->vdd_mydp);
152 DRM_ERROR("Failed to power on ANX7808: %d", ret);
156 gpio_set_value(anx7808->reset_gpio, 1);
160 static int anx7808_power_off(struct anx7808_data *anx7808)
164 DRM_INFO("Powering off ANX7808.\n");
166 gpio_set_value(anx7808->reset_gpio, 0);
167 usleep_range(1000, 2000);
168 ret = regulator_disable(anx7808->vdd_mydp);
170 DRM_ERROR("Failed to power off ANX7808: %d", ret);
173 usleep_range(5000, 10000);
174 gpio_set_value(anx7808->pd_gpio, 1);
175 usleep_range(1000, 2000);
179 static int anx7808_chip_located(struct anx7808_data *anx7808)
183 uint8_t idh = 0, idl = 0;
184 ret |= anx7808_read_reg(anx7808, SP_TX_DEV_IDL_REG, &idl);
185 ret |= anx7808_read_reg(anx7808, SP_TX_DEV_IDH_REG, &idh);
188 id = idl | (idh << 8);
189 if (id != ANX7808_DEVICE_ID) {
190 DRM_ERROR("ANX7808 not found. ID reg contains: %04x\n", id);
193 DRM_INFO("ANX7808 found.\n");
197 static int anx7808_vbus_power_on(struct anx7808_data *anx7808)
201 anx7808_set_bits(anx7808, SP_TX_PLL_FILTER_CTRL6,
202 P5V_PROTECT_PD | SHORT_PROTECT_PD);
203 anx7808_clear_bits(anx7808, SP_TX_PLL_FILTER_CTRL11, V33_SWITCH_ON);
204 anx7808_set_bits(anx7808, SP_TX_PLL_FILTER_CTRL11, V33_SWITCH_ON);
206 anx7808_read_reg(anx7808, SP_TX_PLL_FILTER_CTRL6, &status);
207 if (status & (P5V_PROTECT | SHORT_PROTECT)) {
208 DRM_ERROR("Failed to enable VBUS: 0x%02x.\n", status);
211 DRM_DEBUG_KMS("Enabled VBUS.\n");
215 static int anx7808_aux_wait(struct anx7808_data *anx7808)
219 unsigned long start = jiffies;
221 while ((jiffies - start) <= msecs_to_jiffies(AUX_WAIT_MS)) {
222 err = anx7808_read_reg(anx7808, SP_TX_AUX_STATUS, &status);
225 if (!(status & AUX_BUSY))
227 usleep_range(100, 200);
231 DRM_ERROR("Failed to read AUX channel: 0x%02x\n", status);
237 static int anx7808_aux_read(struct anx7808_data *anx7808, uint32_t addr,
238 uint8_t cmd, uint8_t count, uint8_t *pBuf)
242 int addrl = (addr >> 0) & 0xFF;
243 int addrm = (addr >> 8) & 0xFF;
244 int addrh = (addr >> 16) & 0x0F;
246 if (count > AUX_BUFFER_SIZE)
249 err |= anx7808_write_reg(anx7808, SP_TX_BUF_DATA_COUNT_REG, BUF_CLR);
250 err |= anx7808_write_reg(anx7808, SP_TX_AUX_CTRL_REG,
251 ((count - 1) << 4) | cmd);
252 err |= anx7808_write_reg(anx7808, SP_TX_AUX_ADDR_7_0_REG, addrl);
253 err |= anx7808_write_reg(anx7808, SP_TX_AUX_ADDR_15_8_REG, addrm);
254 err |= anx7808_write_reg(anx7808, SP_TX_AUX_ADDR_19_16_REG, addrh);
255 err |= anx7808_set_bits(anx7808, SP_TX_AUX_CTRL_REG2, AUX_OP_EN);
258 usleep_range(2000, 4000);
260 err = anx7808_aux_wait(anx7808);
264 for (i = 0; i < count; i++)
265 err |= anx7808_read_reg(anx7808, SP_TX_BUF_DATA_0_REG + i,
273 static int anx7808_aux_dpcd_read(struct anx7808_data *anx7808, uint32_t addr,
274 uint8_t count, uint8_t *pBuf)
276 return anx7808_aux_read(anx7808, addr, AUX_DPCD, count, pBuf);
279 static void anx7808_rx_initialization(struct anx7808_data *anx7808)
281 DRM_DEBUG_KMS("Initializing ANX7808 receiver.\n");
283 anx7808_write_reg(anx7808, HDMI_RX_HDMI_MUTE_CTRL_REG,
284 AUD_MUTE | VID_MUTE);
285 anx7808_set_bits(anx7808, HDMI_RX_CHIP_CTRL_REG,
286 MAN_HDMI5V_DET | PLLLOCK_CKDT_EN | DIGITAL_CKDT_EN);
287 anx7808_set_bits(anx7808, HDMI_RX_AEC_CTRL_REG, AVC_OE);
288 anx7808_set_bits(anx7808, HDMI_RX_SRST_REG, HDCP_MAN_RST);
289 usleep_range(1000, 2000);
290 anx7808_clear_bits(anx7808, HDMI_RX_SRST_REG, HDCP_MAN_RST);
291 anx7808_set_bits(anx7808, HDMI_RX_SRST_REG, SW_MAN_RST);
292 usleep_range(1000, 2000);
293 anx7808_clear_bits(anx7808, HDMI_RX_SRST_REG, SW_MAN_RST);
294 anx7808_set_bits(anx7808, HDMI_RX_SRST_REG, TMDS_RST);
295 anx7808_write_reg(anx7808, HDMI_RX_AEC_EN0_REG,
296 AEC_EN07 | AEC_EN06 | AEC_EN05 | AEC_EN02);
297 anx7808_write_reg(anx7808, HDMI_RX_AEC_EN1_REG,
298 AEC_EN12 | AEC_EN10 | AEC_EN09 | AEC_EN08);
299 anx7808_write_reg(anx7808, HDMI_RX_AEC_EN2_REG,
300 AEC_EN23 | AEC_EN22 | AEC_EN21 | AEC_EN20);
301 anx7808_set_bits(anx7808, HDMI_RX_AEC_CTRL_REG, AVC_EN);
302 anx7808_clear_bits(anx7808, HDMI_RX_SYS_PWDN1_REG, PWDN_CTRL);
304 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK1_REG, 0x00);
305 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK2_REG, 0x00);
306 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK3_REG, 0x00);
307 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK4_REG, 0x00);
308 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK5_REG, 0x00);
309 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK6_REG, 0x00);
310 anx7808_write_reg(anx7808, HDMI_RX_INT_MASK7_REG, 0x00);
312 anx7808_set_bits(anx7808, HDMI_RX_VID_DATA_RNG_CTRL_REG,
314 anx7808_write_reg(anx7808, HDMI_RX_CEC_CTRL_REG, CEC_RST);
315 anx7808_write_reg(anx7808, HDMI_RX_CEC_SPEED_CTRL_REG, CEC_SPEED_27M);
316 anx7808_write_reg(anx7808, HDMI_RX_CEC_CTRL_REG, CEC_RX_EN);
318 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG2, 0x00);
319 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG4, 0x28);
320 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG5, 0xE3);
321 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG7, 0x70);
322 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG19, 0x00);
323 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG21, 0x04);
324 anx7808_write_reg(anx7808, HDMI_RX_TMDS_CTRL_REG22, 0x38);
326 DRM_DEBUG_KMS("Issuing HPD low.\n");
327 anx7808_clear_bits(anx7808, SP_TX_VID_CTRL3_REG, HPD_OUT);
328 anx7808_set_bits(anx7808, HDMI_RX_TMDS_CTRL_REG6, TERM_PD);
331 static void anx7808_tx_initialization(struct anx7808_data *anx7808)
333 DRM_DEBUG_KMS("Initializing ANX7808 transmitter.\n");
335 anx7808_write_reg(anx7808, SP_TX_EXTRA_ADDR_REG, I2C_EXTRA_ADDR);
336 anx7808_set_bits(anx7808, SP_TX_HDCP_CTRL, LINK_POLLING);
337 anx7808_clear_bits(anx7808, SP_TX_HDCP_CTRL, AUTO_START | AUTO_EN);
338 anx7808_set_bits(anx7808, SP_TX_LINK_DEBUG_REG, M_VID_DEBUG);
339 anx7808_set_bits(anx7808, SP_TX_DEBUG_REG1,
340 FORCE_HPD | FORCE_PLL_LOCK | POLLING_EN);
341 anx7808_set_bits(anx7808, SP_TX_PLL_FILTER_CTRL11, AUX_TERM_50OHM);
342 anx7808_clear_bits(anx7808, SP_TX_PLL_FILTER_CTRL6,
343 P5V_PROTECT_PD | SHORT_PROTECT_PD);
344 anx7808_set_bits(anx7808, SP_TX_ANALOG_DEBUG_REG2, POWERON_TIME_1P5MS);
345 anx7808_set_bits(anx7808, SP_TX_HDCP_CTRL0_REG,
346 BKSV_SRM_PASS | KSVLIST_VLD);
348 anx7808_write_reg(anx7808, SP_TX_ANALOG_CTRL, 0xC5);
349 anx7808_write_reg(anx7808, I2C_GEN_10US_TIMER0, 0x0E);
350 anx7808_write_reg(anx7808, I2C_GEN_10US_TIMER1, 0x01);
352 anx7808_write_reg(anx7808, SP_TX_DP_POLLING_CTRL_REG,
353 AUTO_POLLING_DISABLE);
354 anx7808_write_reg(anx7808, SP_TX_LINK_CHK_TIMER, 0x1D);
356 anx7808_set_bits(anx7808, SP_TX_MISC_CTRL_REG, EQ_TRAINING_LOOP);
358 anx7808_write_reg(anx7808, SP_COMMON_INT_MASK1, 0x00);
359 anx7808_write_reg(anx7808, SP_COMMON_INT_MASK2, 0x00);
360 anx7808_write_reg(anx7808, SP_COMMON_INT_MASK3, 0x00);
361 anx7808_write_reg(anx7808, SP_COMMON_INT_MASK4, 0x00);
362 anx7808_write_reg(anx7808, SP_INT_MASK, 0x90);
363 anx7808_write_reg(anx7808, SP_TX_INT_CTRL_REG, 0x01);
365 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG0, 0x19);
366 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG4, 0x1B);
367 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG7, 0x22);
368 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG9, 0x23);
369 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG14, 0x09);
370 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG17, 0x16);
371 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG19, 0x1F);
372 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG1, 0x26);
373 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG5, 0x28);
374 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG8, 0x2F);
375 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG15, 0x10);
376 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG18, 0x1F);
377 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG2, 0x36);
378 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG6, 0x3C);
379 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG16, 0x18);
380 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG3, 0x3F);
383 static void anx7808_init_pipeline(struct anx7808_data *anx7808)
385 anx7808_rx_initialization(anx7808);
386 anx7808_tx_initialization(anx7808);
388 anx7808_vbus_power_on(anx7808);
391 DRM_DEBUG_KMS("Issuing HPD high.\n");
392 anx7808_set_bits(anx7808, SP_TX_VID_CTRL3_REG, HPD_OUT);
393 anx7808_clear_bits(anx7808, HDMI_RX_TMDS_CTRL_REG6, TERM_PD);
396 static int anx7808_detect_hdmi_input(struct anx7808_data *anx7808)
400 anx7808_read_reg(anx7808, HDMI_RX_SYS_STATUS_REG, &sys_status);
401 if (!(sys_status & TMDS_CLOCK_DET)) {
402 DRM_INFO("Waiting for HDMI clock.\n");
405 if (!(sys_status & TMDS_DE_DET)) {
406 DRM_INFO("Waiting for HDMI signal.\n");
410 anx7808_write_reg(anx7808, HDMI_RX_HDMI_MUTE_CTRL_REG, 0x00);
415 static int anx7808_dp_link_training(struct anx7808_data *anx7808)
417 uint8_t dp_bw, status;
420 err = anx7808_aux_dpcd_read(anx7808, MAX_LINK_RATE, 1, &dp_bw);
423 DRM_DEBUG_KMS("DP link bandwidth: 0x%02x\n", dp_bw);
425 anx7808_clear_bits(anx7808, SP_POWERD_CTRL_REG, VIDEO_PD);
426 anx7808_set_bits(anx7808, SP_TX_VID_CTRL1_REG, VIDEO_EN | VIDEO_MUTE);
430 anx7808_read_reg(anx7808, SP_TX_SYS_CTRL2_REG, &status);
431 anx7808_write_reg(anx7808, SP_TX_SYS_CTRL2_REG, status);
432 anx7808_read_reg(anx7808, SP_TX_SYS_CTRL2_REG, &status);
433 if (status & CHA_STA) {
434 DRM_INFO("Waiting for DP clock: 0x%02x\n", status);
438 anx7808_set_bits(anx7808, SP_TX_SYS_CTRL3_REG, STRM_VALID);
439 anx7808_read_reg(anx7808, SP_TX_SYS_CTRL3_REG, &status);
440 if (!(status & STRM_VALID)) {
441 DRM_INFO("Waiting for DP signal: 0x%02x\n", status);
445 anx7808_clear_bits(anx7808, SP_TX_VID_CTRL1_REG, VIDEO_EN);
447 anx7808_set_bits(anx7808, SP_TX_ANALOG_PD_REG, CH0_PD);
448 usleep_range(1000, 2000);
449 anx7808_clear_bits(anx7808, SP_TX_ANALOG_PD_REG, CH0_PD);
451 anx7808_set_bits(anx7808, SP_TX_PLL_CTRL_REG, PLL_RST);
452 usleep_range(1000, 2000);
453 anx7808_clear_bits(anx7808, SP_TX_PLL_CTRL_REG, PLL_RST);
455 anx7808_write_reg(anx7808, SP_TX_LINK_BW_SET_REG, 0x14);
456 anx7808_write_reg(anx7808, SP_TX_LT_CTRL_REG, SP_TX_LT_EN);
458 anx7808_read_reg(anx7808, SP_TX_LT_CTRL_REG, &status);
460 DRM_INFO("Waiting for DP link training: 0x%02x\n", status);
464 anx7808_clear_bits(anx7808, SP_TX_VID_CTRL1_REG, VIDEO_MUTE);
469 static void anx7808_config_dp_output(struct anx7808_data *anx7808)
471 anx7808_set_bits(anx7808, SP_TX_VID_CTRL1_REG, VIDEO_EN);
474 static int anx7808_check_polling_err(struct anx7808_data *anx7808)
476 uint8_t tx_int_status;
477 anx7808_read_reg(anx7808, SP_TX_INT_STATUS1, &tx_int_status);
478 anx7808_write_reg(anx7808, SP_TX_INT_STATUS1, tx_int_status);
479 if (tx_int_status & POLLING_ERR)
484 static void anx7808_play_video(struct work_struct *work)
486 struct delayed_work *dw =
487 container_of(work, struct delayed_work, work);
488 struct anx7808_data *anx7808 =
489 container_of(dw, struct anx7808_data, play_video);
491 enum anx7808_state state = STATE_CABLE_DETECTED;
493 ret = anx7808_power_on(anx7808);
497 anx7808_clear_bits(anx7808, SP_POWERD_CTRL_REG, REGISTER_PD);
498 anx7808_clear_bits(anx7808, SP_POWERD_CTRL_REG, TOTAL_PD);
499 anx7808_init_pipeline(anx7808);
501 while (state != STATE_INIT) {
502 DRM_DEBUG_KMS("State: %d\n", state);
504 /* Make progress towards playback state. */
506 case STATE_CABLE_DETECTED:
507 ret = anx7808_detect_hdmi_input(anx7808);
510 state = STATE_HDMI_OK;
513 ret = anx7808_dp_link_training(anx7808);
519 anx7808_config_dp_output(anx7808);
525 /* Check for failures */
526 if (state == STATE_PLAY) {
527 ret = anx7808_check_polling_err(anx7808);
529 DRM_INFO("Polling error: %02x", ret);
537 anx7808_power_off(anx7808);
540 static void anx7808_cable_det_timer(unsigned long data)
542 struct anx7808_data *anx7808 = (struct anx7808_data *)data;
543 DRM_INFO("anx7808_cable_det_timer");
544 queue_delayed_work(anx7808->wq, &anx7808->play_video, 0);
547 static irqreturn_t anx7808_cable_det_isr(int irq, void *data)
549 struct anx7808_data *anx7808 = data;
550 if (gpio_get_value(anx7808->cable_det_gpio)) {
551 DRM_INFO("Cable detected; Setting cable_det_timer.\n");
552 mod_timer(&anx7808->cable_det_timer,
553 jiffies + msecs_to_jiffies(CABLE_DET_TIME_MS));
555 DRM_INFO("Cable unplugged; Deleting cable_det_timer.\n");
556 del_timer(&anx7808->cable_det_timer);
561 static void anx7808_free_gpios(struct anx7808_data *anx7808)
563 gpio_free(anx7808->cable_det_gpio);
564 gpio_free(anx7808->intp_gpio);
565 gpio_free(anx7808->reset_gpio);
566 gpio_free(anx7808->pd_gpio);
569 static void unregister_i2c_clients(struct anx7808_data *anx7808)
572 i2c_unregister_device(anx7808->rx_p1);
574 i2c_unregister_device(anx7808->rx_p0);
576 i2c_unregister_device(anx7808->tx_p2);
578 i2c_unregister_device(anx7808->tx_p1);
581 static int anx7808_probe(struct i2c_client *client,
582 const struct i2c_device_id *id)
585 struct device_node *node = client->dev.of_node;
586 struct anx7808_data *anx7808;
588 anx7808 = devm_kzalloc(&client->dev, sizeof(struct anx7808_data),
591 DRM_ERROR("Failed to allocate platform_data.\n");
594 i2c_set_clientdata(client, anx7808);
596 INIT_DELAYED_WORK(&anx7808->play_video, anx7808_play_video);
598 setup_timer(&anx7808->cable_det_timer, anx7808_cable_det_timer,
599 (unsigned long)anx7808);
601 anx7808->vdd_mydp = regulator_get(&client->dev, "vdd_mydp");
602 if (IS_ERR(anx7808->vdd_mydp)) {
603 DRM_ERROR("Failed to find regulator vdd_mydp.\n");
604 return PTR_ERR(anx7808->vdd_mydp);
607 anx7808->pd_gpio = of_get_named_gpio(node, "pd-gpio", 0);
608 if (!gpio_is_valid(anx7808->pd_gpio)) {
609 DRM_ERROR("Failed to locate pd-gpio.\n");
610 ret = anx7808->pd_gpio;
614 anx7808->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
615 if (!gpio_is_valid(anx7808->reset_gpio)) {
616 DRM_ERROR("Failed to locate reset-gpio.\n");
617 ret = anx7808->reset_gpio;
621 anx7808->intp_gpio = of_get_named_gpio(node, "intp-gpio", 0);
622 if (!gpio_is_valid(anx7808->intp_gpio)) {
623 DRM_ERROR("Failed to locate intp-gpio.\n");
624 ret = anx7808->intp_gpio;
628 anx7808->cable_det_gpio = of_get_named_gpio(node, "cable-det-gpio", 0);
629 if (!gpio_is_valid(anx7808->cable_det_gpio)) {
630 DRM_ERROR("Failed to locate cable-det-gpio.\n");
631 ret = anx7808->cable_det_gpio;
635 ret = gpio_request_one(anx7808->pd_gpio, GPIOF_OUT_INIT_HIGH,
638 DRM_ERROR("Failed to request pd_gpio.\n");
642 ret = gpio_request_one(anx7808->reset_gpio, GPIOF_OUT_INIT_LOW,
643 "anx7808_reset_gpio");
645 DRM_ERROR("Failed to request reset_gpio.\n");
649 ret = gpio_request_one(anx7808->intp_gpio, GPIOF_DIR_IN,
650 "anx7808_intp_gpio");
652 DRM_ERROR("Failed to request intp_gpio.\n");
656 ret = gpio_request_one(anx7808->cable_det_gpio, GPIOF_DIR_IN,
657 "anx7808_cable_det_gpio");
659 DRM_ERROR("Failed to request cable_det_gpio.\n");
663 anx7808->tx_p0 = client;
664 if (!((anx7808->tx_p0->addr) == TX_P0 >> 1)) {
665 DRM_ERROR("I2C client address %02x != expected value %02x.\n",
666 anx7808->tx_p0->addr, TX_P0 >> 1);
669 anx7808->tx_p1 = i2c_new_dummy(client->adapter, TX_P1 >> 1);
670 if (!anx7808->tx_p1) {
671 DRM_ERROR("Failed to reserve i2c bus %02x.\n", TX_P1 >> 1);
675 anx7808->tx_p2 = i2c_new_dummy(client->adapter, TX_P2 >> 1);
676 if (!anx7808->tx_p2) {
677 DRM_ERROR("Failed to reserve i2c bus %02x.\n", TX_P2 >> 1);
681 anx7808->rx_p0 = i2c_new_dummy(client->adapter, RX_P0 >> 1);
682 if (!anx7808->rx_p0) {
683 DRM_ERROR("Failed to reserve i2c bus %02x.\n", RX_P0 >> 1);
687 anx7808->rx_p1 = i2c_new_dummy(client->adapter, RX_P1 >> 1);
688 if (!anx7808->rx_p1) {
689 DRM_ERROR("Failed to reserve i2c bus %02x.\n", RX_P1 >> 1);
694 anx7808_power_on(anx7808);
695 ret = anx7808_chip_located(anx7808);
696 anx7808_power_off(anx7808);
700 anx7808->cable_det_irq = gpio_to_irq(anx7808->cable_det_gpio);
701 if (anx7808->cable_det_irq < 0) {
702 DRM_ERROR("Failed to get irq: %d\n", anx7808->cable_det_irq);
706 anx7808->wq = create_singlethread_workqueue("anx7808_work");
707 if (anx7808->wq == NULL) {
708 DRM_ERROR("Failed to create work queue.\n");
713 ret = devm_request_irq(&client->dev,
714 anx7808->cable_det_irq,
715 anx7808_cable_det_isr,
716 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
720 DRM_ERROR("Failed to request irq: %d\n", ret);
724 DRM_INFO("ANX7808 initialization successful.\n");
728 destroy_workqueue(anx7808->wq);
730 unregister_i2c_clients(anx7808);
732 anx7808_free_gpios(anx7808);
734 regulator_put(anx7808->vdd_mydp);
738 static int anx7808_remove(struct i2c_client *client)
740 struct anx7808_data *anx7808 = i2c_get_clientdata(client);
741 destroy_workqueue(anx7808->wq);
742 unregister_i2c_clients(anx7808);
743 anx7808_free_gpios(anx7808);
744 regulator_put(anx7808->vdd_mydp);
748 static const struct i2c_device_id anx7808_id[] = {
753 MODULE_DEVICE_TABLE(i2c, anx7808_id);
755 static struct i2c_driver anx7808_driver = {
758 .owner = THIS_MODULE,
760 .probe = anx7808_probe,
761 .remove = anx7808_remove,
762 .id_table = anx7808_id,
765 static int __init anx7808_init(void)
769 ret = i2c_add_driver(&anx7808_driver);
771 DRM_ERROR("Failed to register anx7808 i2c driver.\n");
775 static void __exit anx7808_exit(void)
777 i2c_del_driver(&anx7808_driver);
780 module_init(anx7808_init);
781 module_exit(anx7808_exit);
783 MODULE_DESCRIPTION("ANX7808 driver");
784 MODULE_AUTHOR("Jeremy Thorpe <jeremyt@chromium.org>");
785 MODULE_LICENSE("GPL");