drivers/gpu/drm/bridge/dw-hdmi.c

   1 /*
   2  * Copyright (C) 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Designware High-Definition Multimedia Interface (HDMI) driver
  10  *
  11  * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  12  */
  13 #include <linux/module.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/hdmi.h>
  19 #include <linux/mutex.h>
  20 #include <linux/of_device.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drm_of.h>
  24 #include <drm/drmP.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_crtc_helper.h>
  27 #include <drm/drm_edid.h>
  28 #include <drm/drm_encoder_slave.h>
  29 #include <drm/bridge/dw_hdmi.h>
  30
  31 #include "dw-hdmi.h"
  32 #include "dw-hdmi-audio.h"
  33
  34 #define HDMI_EDID_LEN           512
  35
  36 #define RGB                     0
  37 #define YCBCR444                1
  38 #define YCBCR422_16BITS         2
  39 #define YCBCR422_8BITS          3
  40 #define XVYCC444                4
  41
  42 enum hdmi_datamap {
  43         RGB444_8B = 0x01,
  44         RGB444_10B = 0x03,
  45         RGB444_12B = 0x05,
  46         RGB444_16B = 0x07,
  47         YCbCr444_8B = 0x09,
  48         YCbCr444_10B = 0x0B,
  49         YCbCr444_12B = 0x0D,
  50         YCbCr444_16B = 0x0F,
  51         YCbCr422_8B = 0x16,
  52         YCbCr422_10B = 0x14,
  53         YCbCr422_12B = 0x12,
  54 };
  55
  56 static const u16 csc_coeff_default[3][4] = {
  57         { 0x2000, 0x0000, 0x0000, 0x0000 },
  58         { 0x0000, 0x2000, 0x0000, 0x0000 },
  59         { 0x0000, 0x0000, 0x2000, 0x0000 }
  60 };
  61
  62 static const u16 csc_coeff_rgb_out_eitu601[3][4] = {
  63         { 0x2000, 0x6926, 0x74fd, 0x010e },
  64         { 0x2000, 0x2cdd, 0x0000, 0x7e9a },
  65         { 0x2000, 0x0000, 0x38b4, 0x7e3b }
  66 };
  67
  68 static const u16 csc_coeff_rgb_out_eitu709[3][4] = {
  69         { 0x2000, 0x7106, 0x7a02, 0x00a7 },
  70         { 0x2000, 0x3264, 0x0000, 0x7e6d },
  71         { 0x2000, 0x0000, 0x3b61, 0x7e25 }
  72 };
  73
  74 static const u16 csc_coeff_rgb_in_eitu601[3][4] = {
  75         { 0x2591, 0x1322, 0x074b, 0x0000 },
  76         { 0x6535, 0x2000, 0x7acc, 0x0200 },
  77         { 0x6acd, 0x7534, 0x2000, 0x0200 }
  78 };
  79
  80 static const u16 csc_coeff_rgb_in_eitu709[3][4] = {
  81         { 0x2dc5, 0x0d9b, 0x049e, 0x0000 },
  82         { 0x62f0, 0x2000, 0x7d11, 0x0200 },
  83         { 0x6756, 0x78ab, 0x2000, 0x0200 }
  84 };
  85
  86 struct hdmi_vmode {
  87         bool mdataenablepolarity;
  88
  89         unsigned int mpixelclock;
  90         unsigned int mpixelrepetitioninput;
  91         unsigned int mpixelrepetitionoutput;
  92 };
  93
  94 struct hdmi_data_info {
  95         unsigned int enc_in_format;
  96         unsigned int enc_out_format;
  97         unsigned int enc_color_depth;
  98         unsigned int colorimetry;
  99         unsigned int pix_repet_factor;
 100         unsigned int hdcp_enable;
 101         struct hdmi_vmode video_mode;
 102 };
 103
 104 struct dw_hdmi {
 105         struct drm_connector connector;
 106         struct drm_encoder *encoder;
 107         struct drm_bridge *bridge;
 108
 109         struct platform_device *audio;
 110         enum dw_hdmi_devtype dev_type;
 111         struct device *dev;
 112         struct clk *isfr_clk;
 113         struct clk *iahb_clk;
 114
 115         struct hdmi_data_info hdmi_data;
 116         const struct dw_hdmi_plat_data *plat_data;
 117
 118         int vic;
 119
 120         u8 edid[HDMI_EDID_LEN];
 121         bool cable_plugin;
 122
 123         bool phy_enabled;
 124         struct drm_display_mode previous_mode;
 125
 126         struct i2c_adapter *ddc;
 127         void __iomem *regs;
 128         bool sink_is_hdmi;
 129         bool sink_has_audio;
 130
 131         struct mutex mutex;             /* for state below and previous_mode */
 132         enum drm_connector_force force; /* mutex-protected force state */
 133         bool disabled;                  /* DRM has disabled our bridge */
 134         bool bridge_is_on;              /* indicates the bridge is on */
 135         bool rxsense;                   /* rxsense state */
 136         u8 phy_mask;                    /* desired phy int mask settings */
 137
 138         spinlock_t audio_lock;
 139         struct mutex audio_mutex;
 140         unsigned int sample_rate;
 141         unsigned int audio_cts;
 142         unsigned int audio_n;
 143         bool audio_enable;
 144
 145         void (*write)(struct dw_hdmi *hdmi, u8 val, int offset);
 146         u8 (*read)(struct dw_hdmi *hdmi, int offset);
 147 };
 148
 149 #define HDMI_IH_PHY_STAT0_RX_SENSE \
 150         (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \
 151          HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3)
 152
 153 #define HDMI_PHY_RX_SENSE \
 154         (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \
 155          HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3)
 156
 157 static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
 158 {
 159         writel(val, hdmi->regs + (offset << 2));
 160 }
 161
 162 static u8 dw_hdmi_readl(struct dw_hdmi *hdmi, int offset)
 163 {
 164         return readl(hdmi->regs + (offset << 2));
 165 }
 166
 167 static void dw_hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 168 {
 169         writeb(val, hdmi->regs + offset);
 170 }
 171
 172 static u8 dw_hdmi_readb(struct dw_hdmi *hdmi, int offset)
 173 {
 174         return readb(hdmi->regs + offset);
 175 }
 176
 177 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset)
 178 {
 179         hdmi->write(hdmi, val, offset);
 180 }
 181
 182 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset)
 183 {
 184         return hdmi->read(hdmi, offset);
 185 }
 186
 187 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg)
 188 {
 189         u8 val = hdmi_readb(hdmi, reg) & ~mask;
 190
 191         val |= data & mask;
 192         hdmi_writeb(hdmi, val, reg);
 193 }
 194
 195 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg,
 196                              u8 shift, u8 mask)
 197 {
 198         hdmi_modb(hdmi, data << shift, mask, reg);
 199 }
 200
 201 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts,
 202                            unsigned int n)
 203 {
 204         /* Must be set/cleared first */
 205         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 206
 207         /* nshift factor = 0 */
 208         hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3);
 209
 210         hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) |
 211                     HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3);
 212         hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2);
 213         hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1);
 214
 215         hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3);
 216         hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2);
 217         hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
 218 }
 219
 220 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk)
 221 {
 222         unsigned int n = (128 * freq) / 1000;
 223         unsigned int mult = 1;
 224
 225         while (freq > 48000) {
 226                 mult *= 2;
 227                 freq /= 2;
 228         }
 229
 230         switch (freq) {
 231         case 32000:
 232                 if (pixel_clk == 25175000)
 233                         n = 4576;
 234                 else if (pixel_clk == 27027000)
 235                         n = 4096;
 236                 else if (pixel_clk == 74176000 || pixel_clk == 148352000)
 237                         n = 11648;
 238                 else
 239                         n = 4096;
 240                 n *= mult;
 241                 break;
 242
 243         case 44100:
 244                 if (pixel_clk == 25175000)
 245                         n = 7007;
 246                 else if (pixel_clk == 74176000)
 247                         n = 17836;
 248                 else if (pixel_clk == 148352000)
 249                         n = 8918;
 250                 else
 251                         n = 6272;
 252                 n *= mult;
 253                 break;
 254
 255         case 48000:
 256                 if (pixel_clk == 25175000)
 257                         n = 6864;
 258                 else if (pixel_clk == 27027000)
 259                         n = 6144;
 260                 else if (pixel_clk == 74176000)
 261                         n = 11648;
 262                 else if (pixel_clk == 148352000)
 263                         n = 5824;
 264                 else
 265                         n = 6144;
 266                 n *= mult;
 267                 break;
 268
 269         default:
 270                 break;
 271         }
 272
 273         return n;
 274 }
 275
 276 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi,
 277         unsigned long pixel_clk, unsigned int sample_rate)
 278 {
 279         unsigned long ftdms = pixel_clk;
 280         unsigned int n, cts;
 281         u64 tmp;
 282
 283         n = hdmi_compute_n(sample_rate, pixel_clk);
 284
 285         /*
 286          * Compute the CTS value from the N value.  Note that CTS and N
 287          * can be up to 20 bits in total, so we need 64-bit math.  Also
 288          * note that our TDMS clock is not fully accurate; it is accurate
 289          * to kHz.  This can introduce an unnecessary remainder in the
 290          * calculation below, so we don't try to warn about that.
 291          */
 292         tmp = (u64)ftdms * n;
 293         do_div(tmp, 128 * sample_rate);
 294         cts = tmp;
 295
 296         dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n",
 297                 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000,
 298                 n, cts);
 299
 300         spin_lock_irq(&hdmi->audio_lock);
 301         hdmi->audio_n = n;
 302         hdmi->audio_cts = cts;
 303         hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0);
 304         spin_unlock_irq(&hdmi->audio_lock);
 305 }
 306
 307 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi)
 308 {
 309         mutex_lock(&hdmi->audio_mutex);
 310         hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate);
 311         mutex_unlock(&hdmi->audio_mutex);
 312 }
 313
 314 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi)
 315 {
 316         mutex_lock(&hdmi->audio_mutex);
 317         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 318                                  hdmi->sample_rate);
 319         mutex_unlock(&hdmi->audio_mutex);
 320 }
 321
 322 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate)
 323 {
 324         mutex_lock(&hdmi->audio_mutex);
 325         hdmi->sample_rate = rate;
 326         hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock,
 327                                  hdmi->sample_rate);
 328         mutex_unlock(&hdmi->audio_mutex);
 329 }
 330 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate);
 331
 332 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi)
 333 {
 334         unsigned long flags;
 335
 336         spin_lock_irqsave(&hdmi->audio_lock, flags);
 337         hdmi->audio_enable = true;
 338         hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n);
 339         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 340 }
 341 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable);
 342
 343 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi)
 344 {
 345         unsigned long flags;
 346
 347         spin_lock_irqsave(&hdmi->audio_lock, flags);
 348         hdmi->audio_enable = false;
 349         hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0);
 350         spin_unlock_irqrestore(&hdmi->audio_lock, flags);
 351 }
 352 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable);
 353
 354 /*
 355  * this submodule is responsible for the video data synchronization.
 356  * for example, for RGB 4:4:4 input, the data map is defined as
 357  *                      pin{47~40} <==> R[7:0]
 358  *                      pin{31~24} <==> G[7:0]
 359  *                      pin{15~8}  <==> B[7:0]
 360  */
 361 static void hdmi_video_sample(struct dw_hdmi *hdmi)
 362 {
 363         int color_format = 0;
 364         u8 val;
 365
 366         if (hdmi->hdmi_data.enc_in_format == RGB) {
 367                 if (hdmi->hdmi_data.enc_color_depth == 8)
 368                         color_format = 0x01;
 369                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 370                         color_format = 0x03;
 371                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 372                         color_format = 0x05;
 373                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 374                         color_format = 0x07;
 375                 else
 376                         return;
 377         } else if (hdmi->hdmi_data.enc_in_format == YCBCR444) {
 378                 if (hdmi->hdmi_data.enc_color_depth == 8)
 379                         color_format = 0x09;
 380                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 381                         color_format = 0x0B;
 382                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 383                         color_format = 0x0D;
 384                 else if (hdmi->hdmi_data.enc_color_depth == 16)
 385                         color_format = 0x0F;
 386                 else
 387                         return;
 388         } else if (hdmi->hdmi_data.enc_in_format == YCBCR422_8BITS) {
 389                 if (hdmi->hdmi_data.enc_color_depth == 8)
 390                         color_format = 0x16;
 391                 else if (hdmi->hdmi_data.enc_color_depth == 10)
 392                         color_format = 0x14;
 393                 else if (hdmi->hdmi_data.enc_color_depth == 12)
 394                         color_format = 0x12;
 395                 else
 396                         return;
 397         }
 398
 399         val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE |
 400                 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) &
 401                 HDMI_TX_INVID0_VIDEO_MAPPING_MASK);
 402         hdmi_writeb(hdmi, val, HDMI_TX_INVID0);
 403
 404         /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */
 405         val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE |
 406                 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE |
 407                 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE;
 408         hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING);
 409         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0);
 410         hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1);
 411         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0);
 412         hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1);
 413         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0);
 414         hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1);
 415 }
 416
 417 static int is_color_space_conversion(struct dw_hdmi *hdmi)
 418 {
 419         return hdmi->hdmi_data.enc_in_format != hdmi->hdmi_data.enc_out_format;
 420 }
 421
 422 static int is_color_space_decimation(struct dw_hdmi *hdmi)
 423 {
 424         if (hdmi->hdmi_data.enc_out_format != YCBCR422_8BITS)
 425                 return 0;
 426         if (hdmi->hdmi_data.enc_in_format == RGB ||
 427             hdmi->hdmi_data.enc_in_format == YCBCR444)
 428                 return 1;
 429         return 0;
 430 }
 431
 432 static int is_color_space_interpolation(struct dw_hdmi *hdmi)
 433 {
 434         if (hdmi->hdmi_data.enc_in_format != YCBCR422_8BITS)
 435                 return 0;
 436         if (hdmi->hdmi_data.enc_out_format == RGB ||
 437             hdmi->hdmi_data.enc_out_format == YCBCR444)
 438                 return 1;
 439         return 0;
 440 }
 441
 442 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi)
 443 {
 444         const u16 (*csc_coeff)[3][4] = &csc_coeff_default;
 445         unsigned i;
 446         u32 csc_scale = 1;
 447
 448         if (is_color_space_conversion(hdmi)) {
 449                 if (hdmi->hdmi_data.enc_out_format == RGB) {
 450                         if (hdmi->hdmi_data.colorimetry ==
 451                                         HDMI_COLORIMETRY_ITU_601)
 452                                 csc_coeff = &csc_coeff_rgb_out_eitu601;
 453                         else
 454                                 csc_coeff = &csc_coeff_rgb_out_eitu709;
 455                 } else if (hdmi->hdmi_data.enc_in_format == RGB) {
 456                         if (hdmi->hdmi_data.colorimetry ==
 457                                         HDMI_COLORIMETRY_ITU_601)
 458                                 csc_coeff = &csc_coeff_rgb_in_eitu601;
 459                         else
 460                                 csc_coeff = &csc_coeff_rgb_in_eitu709;
 461                         csc_scale = 0;
 462                 }
 463         }
 464
 465         /* The CSC registers are sequential, alternating MSB then LSB */
 466         for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) {
 467                 u16 coeff_a = (*csc_coeff)[0][i];
 468                 u16 coeff_b = (*csc_coeff)[1][i];
 469                 u16 coeff_c = (*csc_coeff)[2][i];
 470
 471                 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2);
 472                 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2);
 473                 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2);
 474                 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2);
 475                 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2);
 476                 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2);
 477         }
 478
 479         hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK,
 480                   HDMI_CSC_SCALE);
 481 }
 482
 483 static void hdmi_video_csc(struct dw_hdmi *hdmi)
 484 {
 485         int color_depth = 0;
 486         int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE;
 487         int decimation = 0;
 488
 489         /* YCC422 interpolation to 444 mode */
 490         if (is_color_space_interpolation(hdmi))
 491                 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1;
 492         else if (is_color_space_decimation(hdmi))
 493                 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3;
 494
 495         if (hdmi->hdmi_data.enc_color_depth == 8)
 496                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP;
 497         else if (hdmi->hdmi_data.enc_color_depth == 10)
 498                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP;
 499         else if (hdmi->hdmi_data.enc_color_depth == 12)
 500                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP;
 501         else if (hdmi->hdmi_data.enc_color_depth == 16)
 502                 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP;
 503         else
 504                 return;
 505
 506         /* Configure the CSC registers */
 507         hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG);
 508         hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK,
 509                   HDMI_CSC_SCALE);
 510
 511         dw_hdmi_update_csc_coeffs(hdmi);
 512 }
 513
 514 /*
 515  * HDMI video packetizer is used to packetize the data.
 516  * for example, if input is YCC422 mode or repeater is used,
 517  * data should be repacked this module can be bypassed.
 518  */
 519 static void hdmi_video_packetize(struct dw_hdmi *hdmi)
 520 {
 521         unsigned int color_depth = 0;
 522         unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit;
 523         unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP;
 524         struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data;
 525         u8 val, vp_conf;
 526
 527         if (hdmi_data->enc_out_format == RGB ||
 528             hdmi_data->enc_out_format == YCBCR444) {
 529                 if (!hdmi_data->enc_color_depth) {
 530                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 531                 } else if (hdmi_data->enc_color_depth == 8) {
 532                         color_depth = 4;
 533                         output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS;
 534                 } else if (hdmi_data->enc_color_depth == 10) {
 535                         color_depth = 5;
 536                 } else if (hdmi_data->enc_color_depth == 12) {
 537                         color_depth = 6;
 538                 } else if (hdmi_data->enc_color_depth == 16) {
 539                         color_depth = 7;
 540                 } else {
 541                         return;
 542                 }
 543         } else if (hdmi_data->enc_out_format == YCBCR422_8BITS) {
 544                 if (!hdmi_data->enc_color_depth ||
 545                     hdmi_data->enc_color_depth == 8)
 546                         remap_size = HDMI_VP_REMAP_YCC422_16bit;
 547                 else if (hdmi_data->enc_color_depth == 10)
 548                         remap_size = HDMI_VP_REMAP_YCC422_20bit;
 549                 else if (hdmi_data->enc_color_depth == 12)
 550                         remap_size = HDMI_VP_REMAP_YCC422_24bit;
 551                 else
 552                         return;
 553                 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422;
 554         } else {
 555                 return;
 556         }
 557
 558         /* set the packetizer registers */
 559         val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) &
 560                 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) |
 561                 ((hdmi_data->pix_repet_factor <<
 562                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) &
 563                 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK);
 564         hdmi_writeb(hdmi, val, HDMI_VP_PR_CD);
 565
 566         hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE,
 567                   HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF);
 568
 569         /* Data from pixel repeater block */
 570         if (hdmi_data->pix_repet_factor > 1) {
 571                 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE |
 572                           HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER;
 573         } else { /* data from packetizer block */
 574                 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE |
 575                           HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER;
 576         }
 577
 578         hdmi_modb(hdmi, vp_conf,
 579                   HDMI_VP_CONF_PR_EN_MASK |
 580                   HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
 581
 582         hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
 583                   HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
 584
 585         hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
 586
 587         if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) {
 588                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 589                           HDMI_VP_CONF_PP_EN_ENABLE |
 590                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 591         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) {
 592                 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE |
 593                           HDMI_VP_CONF_PP_EN_DISABLE |
 594                           HDMI_VP_CONF_YCC422_EN_ENABLE;
 595         } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) {
 596                 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE |
 597                           HDMI_VP_CONF_PP_EN_DISABLE |
 598                           HDMI_VP_CONF_YCC422_EN_DISABLE;
 599         } else {
 600                 return;
 601         }
 602
 603         hdmi_modb(hdmi, vp_conf,
 604                   HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK |
 605                   HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF);
 606
 607         hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE |
 608                         HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE,
 609                   HDMI_VP_STUFF_PP_STUFFING_MASK |
 610                   HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF);
 611
 612         hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK,
 613                   HDMI_VP_CONF);
 614 }
 615
 616 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi,
 617                                        unsigned char bit)
 618 {
 619         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET,
 620                   HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0);
 621 }
 622
 623 static inline void hdmi_phy_test_enable(struct dw_hdmi *hdmi,
 624                                         unsigned char bit)
 625 {
 626         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTEN_OFFSET,
 627                   HDMI_PHY_TST0_TSTEN_MASK, HDMI_PHY_TST0);
 628 }
 629
 630 static inline void hdmi_phy_test_clock(struct dw_hdmi *hdmi,
 631                                        unsigned char bit)
 632 {
 633         hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLK_OFFSET,
 634                   HDMI_PHY_TST0_TSTCLK_MASK, HDMI_PHY_TST0);
 635 }
 636
 637 static inline void hdmi_phy_test_din(struct dw_hdmi *hdmi,
 638                                      unsigned char bit)
 639 {
 640         hdmi_writeb(hdmi, bit, HDMI_PHY_TST1);
 641 }
 642
 643 static inline void hdmi_phy_test_dout(struct dw_hdmi *hdmi,
 644                                       unsigned char bit)
 645 {
 646         hdmi_writeb(hdmi, bit, HDMI_PHY_TST2);
 647 }
 648
 649 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec)
 650 {
 651         u32 val;
 652
 653         while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) {
 654                 if (msec-- == 0)
 655                         return false;
 656                 udelay(1000);
 657         }
 658         hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0);
 659
 660         return true;
 661 }
 662
 663 static void __hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 664                                  unsigned char addr)
 665 {
 666         hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
 667         hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR);
 668         hdmi_writeb(hdmi, (unsigned char)(data >> 8),
 669                     HDMI_PHY_I2CM_DATAO_1_ADDR);
 670         hdmi_writeb(hdmi, (unsigned char)(data >> 0),
 671                     HDMI_PHY_I2CM_DATAO_0_ADDR);
 672         hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE,
 673                     HDMI_PHY_I2CM_OPERATION_ADDR);
 674         hdmi_phy_wait_i2c_done(hdmi, 1000);
 675 }
 676
 677 static int hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data,
 678                               unsigned char addr)
 679 {
 680         __hdmi_phy_i2c_write(hdmi, data, addr);
 681         return 0;
 682 }
 683
 684 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable)
 685 {
 686         hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0,
 687                          HDMI_PHY_CONF0_PDZ_OFFSET,
 688                          HDMI_PHY_CONF0_PDZ_MASK);
 689 }
 690
 691 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable)
 692 {
 693         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 694                          HDMI_PHY_CONF0_ENTMDS_OFFSET,
 695                          HDMI_PHY_CONF0_ENTMDS_MASK);
 696 }
 697
 698 static void dw_hdmi_phy_enable_spare(struct dw_hdmi *hdmi, u8 enable)
 699 {
 700         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 701                          HDMI_PHY_CONF0_SPARECTRL_OFFSET,
 702                          HDMI_PHY_CONF0_SPARECTRL_MASK);
 703 }
 704
 705 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable)
 706 {
 707         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 708                          HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET,
 709                          HDMI_PHY_CONF0_GEN2_PDDQ_MASK);
 710 }
 711
 712 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable)
 713 {
 714         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 715                          HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET,
 716                          HDMI_PHY_CONF0_GEN2_TXPWRON_MASK);
 717 }
 718
 719 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable)
 720 {
 721         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 722                          HDMI_PHY_CONF0_SELDATAENPOL_OFFSET,
 723                          HDMI_PHY_CONF0_SELDATAENPOL_MASK);
 724 }
 725
 726 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
 727 {
 728         hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0,
 729                          HDMI_PHY_CONF0_SELDIPIF_OFFSET,
 730                          HDMI_PHY_CONF0_SELDIPIF_MASK);
 731 }
 732
 733 static int hdmi_phy_configure(struct dw_hdmi *hdmi, unsigned char prep,
 734                               unsigned char res, int cscon)
 735 {
 736         unsigned res_idx;
 737         u8 val, msec;
 738         const struct dw_hdmi_plat_data *pdata = hdmi->plat_data;
 739         const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg;
 740         const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr;
 741         const struct dw_hdmi_phy_config *phy_config = pdata->phy_config;
 742
 743         if (prep)
 744                 return -EINVAL;
 745
 746         switch (res) {
 747         case 0: /* color resolution 0 is 8 bit colour depth */
 748         case 8:
 749                 res_idx = DW_HDMI_RES_8;
 750                 break;
 751         case 10:
 752                 res_idx = DW_HDMI_RES_10;
 753                 break;
 754         case 12:
 755                 res_idx = DW_HDMI_RES_12;
 756                 break;
 757         default:
 758                 return -EINVAL;
 759         }
 760
 761         /* PLL/MPLL Cfg - always match on final entry */
 762         for (; mpll_config->mpixelclock != ~0UL; mpll_config++)
 763                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 764                     mpll_config->mpixelclock)
 765                         break;
 766
 767         for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
 768                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 769                     curr_ctrl->mpixelclock)
 770                         break;
 771
 772         for (; phy_config->mpixelclock != ~0UL; phy_config++)
 773                 if (hdmi->hdmi_data.video_mode.mpixelclock <=
 774                     phy_config->mpixelclock)
 775                         break;
 776
 777         if (mpll_config->mpixelclock == ~0UL ||
 778             curr_ctrl->mpixelclock == ~0UL ||
 779             phy_config->mpixelclock == ~0UL) {
 780                 dev_err(hdmi->dev, "Pixel clock %d - unsupported by HDMI\n",
 781                         hdmi->hdmi_data.video_mode.mpixelclock);
 782                 return -EINVAL;
 783         }
 784
 785         /* Enable csc path */
 786         if (cscon)
 787                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH;
 788         else
 789                 val = HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS;
 790
 791         hdmi_writeb(hdmi, val, HDMI_MC_FLOWCTRL);
 792
 793         /* gen2 tx power off */
 794         dw_hdmi_phy_gen2_txpwron(hdmi, 0);
 795
 796         /* gen2 pddq */
 797         dw_hdmi_phy_gen2_pddq(hdmi, 1);
 798
 799         /* PHY reset */
 800         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_DEASSERT, HDMI_MC_PHYRSTZ);
 801         hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_ASSERT, HDMI_MC_PHYRSTZ);
 802
 803         hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST);
 804
 805         hdmi_phy_test_clear(hdmi, 1);
 806         hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
 807                     HDMI_PHY_I2CM_SLAVE_ADDR);
 808         hdmi_phy_test_clear(hdmi, 0);
 809
 810         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].cpce, 0x06);
 811         hdmi_phy_i2c_write(hdmi, mpll_config->res[res_idx].gmp, 0x15);
 812
 813         /* CURRCTRL */
 814         hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[res_idx], 0x10);
 815
 816         hdmi_phy_i2c_write(hdmi, 0x0000, 0x13);  /* PLLPHBYCTRL */
 817         hdmi_phy_i2c_write(hdmi, 0x0006, 0x17);
 818
 819         hdmi_phy_i2c_write(hdmi, phy_config->term, 0x19);  /* TXTERM */
 820         hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 0x09); /* CKSYMTXCTRL */
 821         hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 0x0E); /* VLEVCTRL */
 822
 823         /* REMOVE CLK TERM */
 824         hdmi_phy_i2c_write(hdmi, 0x8000, 0x05);  /* CKCALCTRL */
 825
 826         dw_hdmi_phy_enable_powerdown(hdmi, false);
 827
 828         /* toggle TMDS enable */
 829         dw_hdmi_phy_enable_tmds(hdmi, 0);
 830         dw_hdmi_phy_enable_tmds(hdmi, 1);
 831
 832         /* gen2 tx power on */
 833         dw_hdmi_phy_gen2_txpwron(hdmi, 1);
 834         dw_hdmi_phy_gen2_pddq(hdmi, 0);
 835
 836         if (hdmi->dev_type == RK3288_HDMI)
 837                 dw_hdmi_phy_enable_spare(hdmi, 1);
 838
 839         /*Wait for PHY PLL lock */
 840         msec = 5;
 841         do {
 842                 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK;
 843                 if (!val)
 844                         break;
 845
 846                 if (msec == 0) {
 847                         dev_err(hdmi->dev, "PHY PLL not locked\n");
 848                         return -ETIMEDOUT;
 849                 }
 850
 851                 udelay(1000);
 852                 msec--;
 853         } while (1);
 854
 855         return 0;
 856 }
 857
 858 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi)
 859 {
 860         int i, ret;
 861         bool cscon;
 862
 863         /*check csc whether needed activated in HDMI mode */
 864         cscon = hdmi->sink_is_hdmi && is_color_space_conversion(hdmi);
 865
 866         /* HDMI Phy spec says to do the phy initialization sequence twice */
 867         for (i = 0; i < 2; i++) {
 868                 dw_hdmi_phy_sel_data_en_pol(hdmi, 1);
 869                 dw_hdmi_phy_sel_interface_control(hdmi, 0);
 870                 dw_hdmi_phy_enable_tmds(hdmi, 0);
 871                 dw_hdmi_phy_enable_powerdown(hdmi, true);
 872
 873                 /* Enable CSC */
 874                 ret = hdmi_phy_configure(hdmi, 0, 8, cscon);
 875                 if (ret)
 876                         return ret;
 877         }
 878
 879         hdmi->phy_enabled = true;
 880         return 0;
 881 }
 882
 883 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi)
 884 {
 885         u8 de;
 886
 887         if (hdmi->hdmi_data.video_mode.mdataenablepolarity)
 888                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH;
 889         else
 890                 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW;
 891
 892         /* disable rx detect */
 893         hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE,
 894                   HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0);
 895
 896         hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG);
 897
 898         hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE,
 899                   HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1);
 900 }
 901
 902 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
 903 {
 904         struct hdmi_avi_infoframe frame;
 905         u8 val;
 906
 907         /* Initialise info frame from DRM mode */
 908         drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 909
 910         if (hdmi->hdmi_data.enc_out_format == YCBCR444)
 911                 frame.colorspace = HDMI_COLORSPACE_YUV444;
 912         else if (hdmi->hdmi_data.enc_out_format == YCBCR422_8BITS)
 913                 frame.colorspace = HDMI_COLORSPACE_YUV422;
 914         else
 915                 frame.colorspace = HDMI_COLORSPACE_RGB;
 916
 917         /* Set up colorimetry */
 918         if (hdmi->hdmi_data.enc_out_format == XVYCC444) {
 919                 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED;
 920                 if (hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_601)
 921                         frame.extended_colorimetry =
 922                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 923                 else /*hdmi->hdmi_data.colorimetry == HDMI_COLORIMETRY_ITU_709*/
 924                         frame.extended_colorimetry =
 925                                 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709;
 926         } else if (hdmi->hdmi_data.enc_out_format != RGB) {
 927                 frame.colorimetry = hdmi->hdmi_data.colorimetry;
 928                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 929         } else { /* Carries no data */
 930                 frame.colorimetry = HDMI_COLORIMETRY_NONE;
 931                 frame.extended_colorimetry = HDMI_EXTENDED_COLORIMETRY_XV_YCC_601;
 932         }
 933
 934         frame.scan_mode = HDMI_SCAN_MODE_NONE;
 935
 936         /*
 937          * The Designware IP uses a different byte format from standard
 938          * AVI info frames, though generally the bits are in the correct
 939          * bytes.
 940          */
 941
 942         /*
 943          * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6,
 944          * scan info in bits 4,5 rather than 0,1 and active aspect present in
 945          * bit 6 rather than 4.
 946          */
 947         val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3);
 948         if (frame.active_aspect & 15)
 949                 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT;
 950         if (frame.top_bar || frame.bottom_bar)
 951                 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR;
 952         if (frame.left_bar || frame.right_bar)
 953                 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR;
 954         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0);
 955
 956         /* AVI data byte 2 differences: none */
 957         val = ((frame.colorimetry & 0x3) << 6) |
 958               ((frame.picture_aspect & 0x3) << 4) |
 959               (frame.active_aspect & 0xf);
 960         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1);
 961
 962         /* AVI data byte 3 differences: none */
 963         val = ((frame.extended_colorimetry & 0x7) << 4) |
 964               ((frame.quantization_range & 0x3) << 2) |
 965               (frame.nups & 0x3);
 966         if (frame.itc)
 967                 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID;
 968         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2);
 969
 970         /* AVI data byte 4 differences: none */
 971         val = frame.video_code & 0x7f;
 972         hdmi_writeb(hdmi, val, HDMI_FC_AVIVID);
 973
 974         /* AVI Data Byte 5- set up input and output pixel repetition */
 975         val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) <<
 976                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) &
 977                 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) |
 978                 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput <<
 979                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) &
 980                 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK);
 981         hdmi_writeb(hdmi, val, HDMI_FC_PRCONF);
 982
 983         /*
 984          * AVI data byte 5 differences: content type in 0,1 rather than 4,5,
 985          * ycc range in bits 2,3 rather than 6,7
 986          */
 987         val = ((frame.ycc_quantization_range & 0x3) << 2) |
 988               (frame.content_type & 0x3);
 989         hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3);
 990
 991         /* AVI Data Bytes 6-13 */
 992         hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0);
 993         hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1);
 994         hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0);
 995         hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1);
 996         hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0);
 997         hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1);
 998         hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0);
 999         hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1);
1000 }
1001
1002 static void hdmi_av_composer(struct dw_hdmi *hdmi,
1003                              const struct drm_display_mode *mode)
1004 {
1005         u8 inv_val;
1006         struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode;
1007         int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len;
1008         unsigned int vdisplay;
1009
1010         vmode->mpixelclock = mode->clock * 1000;
1011
1012         dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock);
1013
1014         /* Set up HDMI_FC_INVIDCONF */
1015         inv_val = (hdmi->hdmi_data.hdcp_enable ?
1016                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
1017                 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
1018
1019         inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
1020                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
1021                 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW;
1022
1023         inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ?
1024                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
1025                 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW;
1026
1027         inv_val |= (vmode->mdataenablepolarity ?
1028                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH :
1029                 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW);
1030
1031         if (hdmi->vic == 39)
1032                 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH;
1033         else
1034                 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1035                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH :
1036                         HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW;
1037
1038         inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ?
1039                 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED :
1040                 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE;
1041
1042         inv_val |= hdmi->sink_is_hdmi ?
1043                 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE :
1044                 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE;
1045
1046         hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF);
1047
1048         vdisplay = mode->vdisplay;
1049         vblank = mode->vtotal - mode->vdisplay;
1050         v_de_vs = mode->vsync_start - mode->vdisplay;
1051         vsync_len = mode->vsync_end - mode->vsync_start;
1052
1053         /*
1054          * When we're setting an interlaced mode, we need
1055          * to adjust the vertical timing to suit.
1056          */
1057         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1058                 vdisplay /= 2;
1059                 vblank /= 2;
1060                 v_de_vs /= 2;
1061                 vsync_len /= 2;
1062         }
1063
1064         /* Set up horizontal active pixel width */
1065         hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1);
1066         hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0);
1067
1068         /* Set up vertical active lines */
1069         hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1);
1070         hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0);
1071
1072         /* Set up horizontal blanking pixel region width */
1073         hblank = mode->htotal - mode->hdisplay;
1074         hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1);
1075         hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0);
1076
1077         /* Set up vertical blanking pixel region width */
1078         hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK);
1079
1080         /* Set up HSYNC active edge delay width (in pixel clks) */
1081         h_de_hs = mode->hsync_start - mode->hdisplay;
1082         hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1);
1083         hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0);
1084
1085         /* Set up VSYNC active edge delay (in lines) */
1086         hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY);
1087
1088         /* Set up HSYNC active pulse width (in pixel clks) */
1089         hsync_len = mode->hsync_end - mode->hsync_start;
1090         hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1);
1091         hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0);
1092
1093         /* Set up VSYNC active edge delay (in lines) */
1094         hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH);
1095 }
1096
1097 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi)
1098 {
1099         if (!hdmi->phy_enabled)
1100                 return;
1101
1102         dw_hdmi_phy_enable_tmds(hdmi, 0);
1103         dw_hdmi_phy_enable_powerdown(hdmi, true);
1104
1105         hdmi->phy_enabled = false;
1106 }
1107
1108 /* HDMI Initialization Step B.4 */
1109 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi)
1110 {
1111         u8 clkdis;
1112
1113         /* control period minimum duration */
1114         hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR);
1115         hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR);
1116         hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC);
1117
1118         /* Set to fill TMDS data channels */
1119         hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM);
1120         hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM);
1121         hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM);
1122
1123         /* Enable pixel clock and tmds data path */
1124         clkdis = 0x7F;
1125         clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE;
1126         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1127
1128         clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE;
1129         hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1130
1131         /* Enable csc path */
1132         if (is_color_space_conversion(hdmi)) {
1133                 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE;
1134                 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS);
1135         }
1136 }
1137
1138 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi)
1139 {
1140         hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS);
1141 }
1142
1143 /* Workaround to clear the overflow condition */
1144 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi)
1145 {
1146         int count;
1147         u8 val;
1148
1149         /* TMDS software reset */
1150         hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ);
1151
1152         val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF);
1153         if (hdmi->dev_type == IMX6DL_HDMI) {
1154                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1155                 return;
1156         }
1157
1158         for (count = 0; count < 4; count++)
1159                 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF);
1160 }
1161
1162 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi)
1163 {
1164         hdmi_writeb(hdmi, 0, HDMI_FC_MASK2);
1165         hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2);
1166 }
1167
1168 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi)
1169 {
1170         hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK,
1171                     HDMI_IH_MUTE_FC_STAT2);
1172 }
1173
1174 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode)
1175 {
1176         int ret;
1177
1178         hdmi_disable_overflow_interrupts(hdmi);
1179
1180         hdmi->vic = drm_match_cea_mode(mode);
1181
1182         if (!hdmi->vic) {
1183                 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n");
1184         } else {
1185                 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic);
1186         }
1187
1188         if ((hdmi->vic == 6) || (hdmi->vic == 7) ||
1189             (hdmi->vic == 21) || (hdmi->vic == 22) ||
1190             (hdmi->vic == 2) || (hdmi->vic == 3) ||
1191             (hdmi->vic == 17) || (hdmi->vic == 18))
1192                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_601;
1193         else
1194                 hdmi->hdmi_data.colorimetry = HDMI_COLORIMETRY_ITU_709;
1195
1196         hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
1197         hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
1198
1199         /* TODO: Get input format from IPU (via FB driver interface) */
1200         hdmi->hdmi_data.enc_in_format = RGB;
1201
1202         hdmi->hdmi_data.enc_out_format = RGB;
1203
1204         hdmi->hdmi_data.enc_color_depth = 8;
1205         hdmi->hdmi_data.pix_repet_factor = 0;
1206         hdmi->hdmi_data.hdcp_enable = 0;
1207         hdmi->hdmi_data.video_mode.mdataenablepolarity = true;
1208
1209         /* HDMI Initialization Step B.1 */
1210         hdmi_av_composer(hdmi, mode);
1211
1212         /* HDMI Initializateion Step B.2 */
1213         ret = dw_hdmi_phy_init(hdmi);
1214         if (ret)
1215                 return ret;
1216
1217         /* HDMI Initialization Step B.3 */
1218         dw_hdmi_enable_video_path(hdmi);
1219
1220         if (hdmi->sink_has_audio) {
1221                 dev_dbg(hdmi->dev, "sink has audio support\n");
1222
1223                 /* HDMI Initialization Step E - Configure audio */
1224                 hdmi_clk_regenerator_update_pixel_clock(hdmi);
1225                 hdmi_enable_audio_clk(hdmi);
1226         }
1227
1228         /* not for DVI mode */
1229         if (hdmi->sink_is_hdmi) {
1230                 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__);
1231
1232                 /* HDMI Initialization Step F - Configure AVI InfoFrame */
1233                 hdmi_config_AVI(hdmi, mode);
1234         } else {
1235                 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__);
1236         }
1237
1238         hdmi_video_packetize(hdmi);
1239         hdmi_video_csc(hdmi);
1240         hdmi_video_sample(hdmi);
1241         hdmi_tx_hdcp_config(hdmi);
1242
1243         dw_hdmi_clear_overflow(hdmi);
1244         if (hdmi->cable_plugin && hdmi->sink_is_hdmi)
1245                 hdmi_enable_overflow_interrupts(hdmi);
1246
1247         return 0;
1248 }
1249
1250 /* Wait until we are registered to enable interrupts */
1251 static int dw_hdmi_fb_registered(struct dw_hdmi *hdmi)
1252 {
1253         hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL,
1254                     HDMI_PHY_I2CM_INT_ADDR);
1255
1256         hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL |
1257                     HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL,
1258                     HDMI_PHY_I2CM_CTLINT_ADDR);
1259
1260         /* enable cable hot plug irq */
1261         hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1262
1263         /* Clear Hotplug interrupts */
1264         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1265                     HDMI_IH_PHY_STAT0);
1266
1267         return 0;
1268 }
1269
1270 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi)
1271 {
1272         u8 ih_mute;
1273
1274         /*
1275          * Boot up defaults are:
1276          * HDMI_IH_MUTE   = 0x03 (disabled)
1277          * HDMI_IH_MUTE_* = 0x00 (enabled)
1278          *
1279          * Disable top level interrupt bits in HDMI block
1280          */
1281         ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) |
1282                   HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1283                   HDMI_IH_MUTE_MUTE_ALL_INTERRUPT;
1284
1285         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1286
1287         /* by default mask all interrupts */
1288         hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK);
1289         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0);
1290         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1);
1291         hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2);
1292         hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0);
1293         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR);
1294         hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR);
1295         hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT);
1296         hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT);
1297         hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK);
1298         hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK);
1299         hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
1300         hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK);
1301         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT);
1302         hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT);
1303
1304         /* Disable interrupts in the IH_MUTE_* registers */
1305         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0);
1306         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1);
1307         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2);
1308         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0);
1309         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0);
1310         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0);
1311         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0);
1312         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0);
1313         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0);
1314         hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0);
1315
1316         /* Enable top level interrupt bits in HDMI block */
1317         ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT |
1318                     HDMI_IH_MUTE_MUTE_ALL_INTERRUPT);
1319         hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE);
1320 }
1321
1322 static void dw_hdmi_poweron(struct dw_hdmi *hdmi)
1323 {
1324         hdmi->bridge_is_on = true;
1325         dw_hdmi_setup(hdmi, &hdmi->previous_mode);
1326 }
1327
1328 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi)
1329 {
1330         dw_hdmi_phy_disable(hdmi);
1331         hdmi->bridge_is_on = false;
1332 }
1333
1334 static void dw_hdmi_update_power(struct dw_hdmi *hdmi)
1335 {
1336         int force = hdmi->force;
1337
1338         if (hdmi->disabled) {
1339                 force = DRM_FORCE_OFF;
1340         } else if (force == DRM_FORCE_UNSPECIFIED) {
1341                 if (hdmi->rxsense)
1342                         force = DRM_FORCE_ON;
1343                 else
1344                         force = DRM_FORCE_OFF;
1345         }
1346
1347         if (force == DRM_FORCE_OFF) {
1348                 if (hdmi->bridge_is_on)
1349                         dw_hdmi_poweroff(hdmi);
1350         } else {
1351                 if (!hdmi->bridge_is_on)
1352                         dw_hdmi_poweron(hdmi);
1353         }
1354 }
1355
1356 /*
1357  * Adjust the detection of RXSENSE according to whether we have a forced
1358  * connection mode enabled, or whether we have been disabled.  There is
1359  * no point processing RXSENSE interrupts if we have a forced connection
1360  * state, or DRM has us disabled.
1361  *
1362  * We also disable rxsense interrupts when we think we're disconnected
1363  * to avoid floating TDMS signals giving false rxsense interrupts.
1364  *
1365  * Note: we still need to listen for HPD interrupts even when DRM has us
1366  * disabled so that we can detect a connect event.
1367  */
1368 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi)
1369 {
1370         u8 old_mask = hdmi->phy_mask;
1371
1372         if (hdmi->force || hdmi->disabled || !hdmi->rxsense)
1373                 hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
1374         else
1375                 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
1376
1377         if (old_mask != hdmi->phy_mask)
1378                 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0);
1379 }
1380
1381 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge,
1382                                     struct drm_display_mode *orig_mode,
1383                                     struct drm_display_mode *mode)
1384 {
1385         struct dw_hdmi *hdmi = bridge->driver_private;
1386
1387         mutex_lock(&hdmi->mutex);
1388
1389         /* Store the display mode for plugin/DKMS poweron events */
1390         memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode));
1391
1392         mutex_unlock(&hdmi->mutex);
1393 }
1394
1395 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge)
1396 {
1397         struct dw_hdmi *hdmi = bridge->driver_private;
1398
1399         mutex_lock(&hdmi->mutex);
1400         hdmi->disabled = true;
1401         dw_hdmi_update_power(hdmi);
1402         dw_hdmi_update_phy_mask(hdmi);
1403         mutex_unlock(&hdmi->mutex);
1404 }
1405
1406 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge)
1407 {
1408         struct dw_hdmi *hdmi = bridge->driver_private;
1409
1410         mutex_lock(&hdmi->mutex);
1411         hdmi->disabled = false;
1412         dw_hdmi_update_power(hdmi);
1413         dw_hdmi_update_phy_mask(hdmi);
1414         mutex_unlock(&hdmi->mutex);
1415 }
1416
1417 static enum drm_connector_status
1418 dw_hdmi_connector_detect(struct drm_connector *connector, bool force)
1419 {
1420         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1421                                              connector);
1422
1423         mutex_lock(&hdmi->mutex);
1424         hdmi->force = DRM_FORCE_UNSPECIFIED;
1425         dw_hdmi_update_power(hdmi);
1426         dw_hdmi_update_phy_mask(hdmi);
1427         mutex_unlock(&hdmi->mutex);
1428
1429         return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
1430                 connector_status_connected : connector_status_disconnected;
1431 }
1432
1433 static int dw_hdmi_connector_get_modes(struct drm_connector *connector)
1434 {
1435         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1436                                              connector);
1437         struct edid *edid;
1438         int ret = 0;
1439
1440         if (!hdmi->ddc)
1441                 return 0;
1442
1443         edid = drm_get_edid(connector, hdmi->ddc);
1444         if (edid) {
1445                 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n",
1446                         edid->width_cm, edid->height_cm);
1447
1448                 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid);
1449                 hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
1450                 drm_mode_connector_update_edid_property(connector, edid);
1451                 ret = drm_add_edid_modes(connector, edid);
1452                 /* Store the ELD */
1453                 drm_edid_to_eld(connector, edid);
1454                 kfree(edid);
1455         } else {
1456                 dev_dbg(hdmi->dev, "failed to get edid\n");
1457         }
1458
1459         return ret;
1460 }
1461
1462 static enum drm_mode_status
1463 dw_hdmi_connector_mode_valid(struct drm_connector *connector,
1464                              struct drm_display_mode *mode)
1465 {
1466         struct dw_hdmi *hdmi = container_of(connector,
1467                                            struct dw_hdmi, connector);
1468         enum drm_mode_status mode_status = MODE_OK;
1469
1470         /* We don't support double-clocked modes */
1471         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1472                 return MODE_BAD;
1473
1474         if (hdmi->plat_data->mode_valid)
1475                 mode_status = hdmi->plat_data->mode_valid(connector, mode);
1476
1477         return mode_status;
1478 }
1479
1480 static void dw_hdmi_connector_force(struct drm_connector *connector)
1481 {
1482         struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi,
1483                                              connector);
1484
1485         mutex_lock(&hdmi->mutex);
1486         hdmi->force = connector->force;
1487         dw_hdmi_update_power(hdmi);
1488         dw_hdmi_update_phy_mask(hdmi);
1489         mutex_unlock(&hdmi->mutex);
1490 }
1491
1492 static const struct drm_connector_funcs dw_hdmi_connector_funcs = {
1493         .dpms = drm_atomic_helper_connector_dpms,
1494         .fill_modes = drm_helper_probe_single_connector_modes,
1495         .detect = dw_hdmi_connector_detect,
1496         .destroy = drm_connector_cleanup,
1497         .force = dw_hdmi_connector_force,
1498         .reset = drm_atomic_helper_connector_reset,
1499         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1500         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1501 };
1502
1503 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = {
1504         .get_modes = dw_hdmi_connector_get_modes,
1505         .mode_valid = dw_hdmi_connector_mode_valid,
1506         .best_encoder = drm_atomic_helper_best_encoder,
1507 };
1508
1509 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = {
1510         .enable = dw_hdmi_bridge_enable,
1511         .disable = dw_hdmi_bridge_disable,
1512         .mode_set = dw_hdmi_bridge_mode_set,
1513 };
1514
1515 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id)
1516 {
1517         struct dw_hdmi *hdmi = dev_id;
1518         u8 intr_stat;
1519
1520         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1521         if (intr_stat)
1522                 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1523
1524         return intr_stat ? IRQ_WAKE_THREAD : IRQ_NONE;
1525 }
1526
1527 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
1528 {
1529         struct dw_hdmi *hdmi = dev_id;
1530         u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat;
1531
1532         intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0);
1533         phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0);
1534         phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0);
1535
1536         phy_pol_mask = 0;
1537         if (intr_stat & HDMI_IH_PHY_STAT0_HPD)
1538                 phy_pol_mask |= HDMI_PHY_HPD;
1539         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0)
1540                 phy_pol_mask |= HDMI_PHY_RX_SENSE0;
1541         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1)
1542                 phy_pol_mask |= HDMI_PHY_RX_SENSE1;
1543         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2)
1544                 phy_pol_mask |= HDMI_PHY_RX_SENSE2;
1545         if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3)
1546                 phy_pol_mask |= HDMI_PHY_RX_SENSE3;
1547
1548         if (phy_pol_mask)
1549                 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0);
1550
1551         /*
1552          * RX sense tells us whether the TDMS transmitters are detecting
1553          * load - in other words, there's something listening on the
1554          * other end of the link.  Use this to decide whether we should
1555          * power on the phy as HPD may be toggled by the sink to merely
1556          * ask the source to re-read the EDID.
1557          */
1558         if (intr_stat &
1559             (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) {
1560                 mutex_lock(&hdmi->mutex);
1561                 if (!hdmi->disabled && !hdmi->force) {
1562                         /*
1563                          * If the RX sense status indicates we're disconnected,
1564                          * clear the software rxsense status.
1565                          */
1566                         if (!(phy_stat & HDMI_PHY_RX_SENSE))
1567                                 hdmi->rxsense = false;
1568
1569                         /*
1570                          * Only set the software rxsense status when both
1571                          * rxsense and hpd indicates we're connected.
1572                          * This avoids what seems to be bad behaviour in
1573                          * at least iMX6S versions of the phy.
1574                          */
1575                         if (phy_stat & HDMI_PHY_HPD)
1576                                 hdmi->rxsense = true;
1577
1578                         dw_hdmi_update_power(hdmi);
1579                         dw_hdmi_update_phy_mask(hdmi);
1580                 }
1581                 mutex_unlock(&hdmi->mutex);
1582         }
1583
1584         if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
1585                 dev_dbg(hdmi->dev, "EVENT=%s\n",
1586                         phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout");
1587                 drm_helper_hpd_irq_event(hdmi->bridge->dev);
1588         }
1589
1590         hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0);
1591         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1592                     HDMI_IH_MUTE_PHY_STAT0);
1593
1594         return IRQ_HANDLED;
1595 }
1596
1597 static int dw_hdmi_register(struct drm_device *drm, struct dw_hdmi *hdmi)
1598 {
1599         struct drm_encoder *encoder = hdmi->encoder;
1600         struct drm_bridge *bridge;
1601         int ret;
1602
1603         bridge = devm_kzalloc(drm->dev, sizeof(*bridge), GFP_KERNEL);
1604         if (!bridge) {
1605                 DRM_ERROR("Failed to allocate drm bridge\n");
1606                 return -ENOMEM;
1607         }
1608
1609         hdmi->bridge = bridge;
1610         bridge->driver_private = hdmi;
1611         bridge->funcs = &dw_hdmi_bridge_funcs;
1612         ret = drm_bridge_attach(drm, bridge);
1613         if (ret) {
1614                 DRM_ERROR("Failed to initialize bridge with drm\n");
1615                 return -EINVAL;
1616         }
1617
1618         encoder->bridge = bridge;
1619         hdmi->connector.polled = DRM_CONNECTOR_POLL_HPD;
1620
1621         drm_connector_helper_add(&hdmi->connector,
1622                                  &dw_hdmi_connector_helper_funcs);
1623
1624         drm_connector_init(drm, &hdmi->connector,
1625                            &dw_hdmi_connector_funcs,
1626                            DRM_MODE_CONNECTOR_HDMIA);
1627
1628         drm_mode_connector_attach_encoder(&hdmi->connector, encoder);
1629
1630         return 0;
1631 }
1632
1633 int dw_hdmi_bind(struct device *dev, struct device *master,
1634                  void *data, struct drm_encoder *encoder,
1635                  struct resource *iores, int irq,
1636                  const struct dw_hdmi_plat_data *plat_data)
1637 {
1638         struct drm_device *drm = data;
1639         struct device_node *np = dev->of_node;
1640         struct platform_device_info pdevinfo;
1641         struct device_node *ddc_node;
1642         struct dw_hdmi_audio_data audio;
1643         struct dw_hdmi *hdmi;
1644         int ret;
1645         u32 val = 1;
1646
1647         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1648         if (!hdmi)
1649                 return -ENOMEM;
1650
1651         hdmi->connector.interlace_allowed = 1;
1652
1653         hdmi->plat_data = plat_data;
1654         hdmi->dev = dev;
1655         hdmi->dev_type = plat_data->dev_type;
1656         hdmi->sample_rate = 48000;
1657         hdmi->encoder = encoder;
1658         hdmi->disabled = true;
1659         hdmi->rxsense = true;
1660         hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE);
1661
1662         mutex_init(&hdmi->mutex);
1663         mutex_init(&hdmi->audio_mutex);
1664         spin_lock_init(&hdmi->audio_lock);
1665
1666         of_property_read_u32(np, "reg-io-width", &val);
1667
1668         switch (val) {
1669         case 4:
1670                 hdmi->write = dw_hdmi_writel;
1671                 hdmi->read = dw_hdmi_readl;
1672                 break;
1673         case 1:
1674                 hdmi->write = dw_hdmi_writeb;
1675                 hdmi->read = dw_hdmi_readb;
1676                 break;
1677         default:
1678                 dev_err(dev, "reg-io-width must be 1 or 4\n");
1679                 return -EINVAL;
1680         }
1681
1682         ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
1683         if (ddc_node) {
1684                 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1685                 of_node_put(ddc_node);
1686                 if (!hdmi->ddc) {
1687                         dev_dbg(hdmi->dev, "failed to read ddc node\n");
1688                         return -EPROBE_DEFER;
1689                 }
1690
1691         } else {
1692                 dev_dbg(hdmi->dev, "no ddc property found\n");
1693         }
1694
1695         hdmi->regs = devm_ioremap_resource(dev, iores);
1696         if (IS_ERR(hdmi->regs))
1697                 return PTR_ERR(hdmi->regs);
1698
1699         hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr");
1700         if (IS_ERR(hdmi->isfr_clk)) {
1701                 ret = PTR_ERR(hdmi->isfr_clk);
1702                 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret);
1703                 return ret;
1704         }
1705
1706         ret = clk_prepare_enable(hdmi->isfr_clk);
1707         if (ret) {
1708                 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret);
1709                 return ret;
1710         }
1711
1712         hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb");
1713         if (IS_ERR(hdmi->iahb_clk)) {
1714                 ret = PTR_ERR(hdmi->iahb_clk);
1715                 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret);
1716                 goto err_isfr;
1717         }
1718
1719         ret = clk_prepare_enable(hdmi->iahb_clk);
1720         if (ret) {
1721                 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret);
1722                 goto err_isfr;
1723         }
1724
1725         /* Product and revision IDs */
1726         dev_info(dev,
1727                  "Detected HDMI controller 0x%x:0x%x:0x%x:0x%x\n",
1728                  hdmi_readb(hdmi, HDMI_DESIGN_ID),
1729                  hdmi_readb(hdmi, HDMI_REVISION_ID),
1730                  hdmi_readb(hdmi, HDMI_PRODUCT_ID0),
1731                  hdmi_readb(hdmi, HDMI_PRODUCT_ID1));
1732
1733         initialize_hdmi_ih_mutes(hdmi);
1734
1735         ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq,
1736                                         dw_hdmi_irq, IRQF_SHARED,
1737                                         dev_name(dev), hdmi);
1738         if (ret)
1739                 goto err_iahb;
1740
1741         /*
1742          * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator
1743          * N and cts values before enabling phy
1744          */
1745         hdmi_init_clk_regenerator(hdmi);
1746
1747         /*
1748          * Configure registers related to HDMI interrupt
1749          * generation before registering IRQ.
1750          */
1751         hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0);
1752
1753         /* Clear Hotplug interrupts */
1754         hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE,
1755                     HDMI_IH_PHY_STAT0);
1756
1757         ret = dw_hdmi_fb_registered(hdmi);
1758         if (ret)
1759                 goto err_iahb;
1760
1761         ret = dw_hdmi_register(drm, hdmi);
1762         if (ret)
1763                 goto err_iahb;
1764
1765         /* Unmute interrupts */
1766         hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE),
1767                     HDMI_IH_MUTE_PHY_STAT0);
1768
1769         memset(&pdevinfo, 0, sizeof(pdevinfo));
1770         pdevinfo.parent = dev;
1771         pdevinfo.id = PLATFORM_DEVID_AUTO;
1772
1773         if (hdmi_readb(hdmi, HDMI_CONFIG1_ID) & HDMI_CONFIG1_AHB) {
1774                 audio.phys = iores->start;
1775                 audio.base = hdmi->regs;
1776                 audio.irq = irq;
1777                 audio.hdmi = hdmi;
1778                 audio.eld = hdmi->connector.eld;
1779
1780                 pdevinfo.name = "dw-hdmi-ahb-audio";
1781                 pdevinfo.data = &audio;
1782                 pdevinfo.size_data = sizeof(audio);
1783                 pdevinfo.dma_mask = DMA_BIT_MASK(32);
1784                 hdmi->audio = platform_device_register_full(&pdevinfo);
1785         }
1786
1787         dev_set_drvdata(dev, hdmi);
1788
1789         return 0;
1790
1791 err_iahb:
1792         clk_disable_unprepare(hdmi->iahb_clk);
1793 err_isfr:
1794         clk_disable_unprepare(hdmi->isfr_clk);
1795
1796         return ret;
1797 }
1798 EXPORT_SYMBOL_GPL(dw_hdmi_bind);
1799
1800 void dw_hdmi_unbind(struct device *dev, struct device *master, void *data)
1801 {
1802         struct dw_hdmi *hdmi = dev_get_drvdata(dev);
1803
1804         if (hdmi->audio && !IS_ERR(hdmi->audio))
1805                 platform_device_unregister(hdmi->audio);
1806
1807         /* Disable all interrupts */
1808         hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
1809
1810         clk_disable_unprepare(hdmi->iahb_clk);
1811         clk_disable_unprepare(hdmi->isfr_clk);
1812         i2c_put_adapter(hdmi->ddc);
1813 }
1814 EXPORT_SYMBOL_GPL(dw_hdmi_unbind);
1815
1816 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1817 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>");
1818 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
1819 MODULE_DESCRIPTION("DW HDMI transmitter driver");
1820 MODULE_LICENSE("GPL");
1821 MODULE_ALIAS("platform:dw-hdmi");