drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include "etnaviv_dump.h"
  22 #include "etnaviv_gpu.h"
  23 #include "etnaviv_gem.h"
  24 #include "etnaviv_mmu.h"
  25 #include "etnaviv_iommu.h"
  26 #include "etnaviv_iommu_v2.h"
  27 #include "common.xml.h"
  28 #include "state.xml.h"
  29 #include "state_hi.xml.h"
  30 #include "cmdstream.xml.h"
  31
  32 static const struct platform_device_id gpu_ids[] = {
  33         { .name = "etnaviv-gpu,2d" },
  34         { },
  35 };
  36
  37 static bool etnaviv_dump_core = true;
  38 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  39
  40 /*
  41  * Driver functions:
  42  */
  43
  44 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  45 {
  46         switch (param) {
  47         case ETNAVIV_PARAM_GPU_MODEL:
  48                 *value = gpu->identity.model;
  49                 break;
  50
  51         case ETNAVIV_PARAM_GPU_REVISION:
  52                 *value = gpu->identity.revision;
  53                 break;
  54
  55         case ETNAVIV_PARAM_GPU_FEATURES_0:
  56                 *value = gpu->identity.features;
  57                 break;
  58
  59         case ETNAVIV_PARAM_GPU_FEATURES_1:
  60                 *value = gpu->identity.minor_features0;
  61                 break;
  62
  63         case ETNAVIV_PARAM_GPU_FEATURES_2:
  64                 *value = gpu->identity.minor_features1;
  65                 break;
  66
  67         case ETNAVIV_PARAM_GPU_FEATURES_3:
  68                 *value = gpu->identity.minor_features2;
  69                 break;
  70
  71         case ETNAVIV_PARAM_GPU_FEATURES_4:
  72                 *value = gpu->identity.minor_features3;
  73                 break;
  74
  75         case ETNAVIV_PARAM_GPU_FEATURES_5:
  76                 *value = gpu->identity.minor_features4;
  77                 break;
  78
  79         case ETNAVIV_PARAM_GPU_FEATURES_6:
  80                 *value = gpu->identity.minor_features5;
  81                 break;
  82
  83         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  84                 *value = gpu->identity.stream_count;
  85                 break;
  86
  87         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  88                 *value = gpu->identity.register_max;
  89                 break;
  90
  91         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  92                 *value = gpu->identity.thread_count;
  93                 break;
  94
  95         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  96                 *value = gpu->identity.vertex_cache_size;
  97                 break;
  98
  99         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 100                 *value = gpu->identity.shader_core_count;
 101                 break;
 102
 103         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 104                 *value = gpu->identity.pixel_pipes;
 105                 break;
 106
 107         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 108                 *value = gpu->identity.vertex_output_buffer_size;
 109                 break;
 110
 111         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 112                 *value = gpu->identity.buffer_size;
 113                 break;
 114
 115         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 116                 *value = gpu->identity.instruction_count;
 117                 break;
 118
 119         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 120                 *value = gpu->identity.num_constants;
 121                 break;
 122
 123         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 124                 *value = gpu->identity.varyings_count;
 125                 break;
 126
 127         default:
 128                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 129                 return -EINVAL;
 130         }
 131
 132         return 0;
 133 }
 134
 135
 136 #define etnaviv_is_model_rev(gpu, mod, rev) \
 137         ((gpu)->identity.model == chipModel_##mod && \
 138          (gpu)->identity.revision == rev)
 139 #define etnaviv_field(val, field) \
 140         (((val) & field##__MASK) >> field##__SHIFT)
 141
 142 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 143 {
 144         if (gpu->identity.minor_features0 &
 145             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 146                 u32 specs[4];
 147                 unsigned int streams;
 148
 149                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 150                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 151                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 152                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 153
 154                 gpu->identity.stream_count = etnaviv_field(specs[0],
 155                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 156                 gpu->identity.register_max = etnaviv_field(specs[0],
 157                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 158                 gpu->identity.thread_count = etnaviv_field(specs[0],
 159                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 160                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 161                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 162                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 163                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 164                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 165                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 166                 gpu->identity.vertex_output_buffer_size =
 167                         etnaviv_field(specs[0],
 168                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 169
 170                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 171                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 172                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 173                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 174                 gpu->identity.num_constants = etnaviv_field(specs[1],
 175                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 176
 177                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 178                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 179
 180                 /* This overrides the value from older register if non-zero */
 181                 streams = etnaviv_field(specs[3],
 182                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 183                 if (streams)
 184                         gpu->identity.stream_count = streams;
 185         }
 186
 187         /* Fill in the stream count if not specified */
 188         if (gpu->identity.stream_count == 0) {
 189                 if (gpu->identity.model >= 0x1000)
 190                         gpu->identity.stream_count = 4;
 191                 else
 192                         gpu->identity.stream_count = 1;
 193         }
 194
 195         /* Convert the register max value */
 196         if (gpu->identity.register_max)
 197                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 198         else if (gpu->identity.model == chipModel_GC400)
 199                 gpu->identity.register_max = 32;
 200         else
 201                 gpu->identity.register_max = 64;
 202
 203         /* Convert thread count */
 204         if (gpu->identity.thread_count)
 205                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 206         else if (gpu->identity.model == chipModel_GC400)
 207                 gpu->identity.thread_count = 64;
 208         else if (gpu->identity.model == chipModel_GC500 ||
 209                  gpu->identity.model == chipModel_GC530)
 210                 gpu->identity.thread_count = 128;
 211         else
 212                 gpu->identity.thread_count = 256;
 213
 214         if (gpu->identity.vertex_cache_size == 0)
 215                 gpu->identity.vertex_cache_size = 8;
 216
 217         if (gpu->identity.shader_core_count == 0) {
 218                 if (gpu->identity.model >= 0x1000)
 219                         gpu->identity.shader_core_count = 2;
 220                 else
 221                         gpu->identity.shader_core_count = 1;
 222         }
 223
 224         if (gpu->identity.pixel_pipes == 0)
 225                 gpu->identity.pixel_pipes = 1;
 226
 227         /* Convert virtex buffer size */
 228         if (gpu->identity.vertex_output_buffer_size) {
 229                 gpu->identity.vertex_output_buffer_size =
 230                         1 << gpu->identity.vertex_output_buffer_size;
 231         } else if (gpu->identity.model == chipModel_GC400) {
 232                 if (gpu->identity.revision < 0x4000)
 233                         gpu->identity.vertex_output_buffer_size = 512;
 234                 else if (gpu->identity.revision < 0x4200)
 235                         gpu->identity.vertex_output_buffer_size = 256;
 236                 else
 237                         gpu->identity.vertex_output_buffer_size = 128;
 238         } else {
 239                 gpu->identity.vertex_output_buffer_size = 512;
 240         }
 241
 242         switch (gpu->identity.instruction_count) {
 243         case 0:
 244                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 245                     gpu->identity.model == chipModel_GC880)
 246                         gpu->identity.instruction_count = 512;
 247                 else
 248                         gpu->identity.instruction_count = 256;
 249                 break;
 250
 251         case 1:
 252                 gpu->identity.instruction_count = 1024;
 253                 break;
 254
 255         case 2:
 256                 gpu->identity.instruction_count = 2048;
 257                 break;
 258
 259         default:
 260                 gpu->identity.instruction_count = 256;
 261                 break;
 262         }
 263
 264         if (gpu->identity.num_constants == 0)
 265                 gpu->identity.num_constants = 168;
 266
 267         if (gpu->identity.varyings_count == 0) {
 268                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 269                         gpu->identity.varyings_count = 12;
 270                 else
 271                         gpu->identity.varyings_count = 8;
 272         }
 273
 274         /*
 275          * For some cores, two varyings are consumed for position, so the
 276          * maximum varying count needs to be reduced by one.
 277          */
 278         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 279             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 280             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 281             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 282             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 283             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 284             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 285             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 286             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 287             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 288             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 289                 gpu->identity.varyings_count -= 1;
 290 }
 291
 292 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 293 {
 294         u32 chipIdentity;
 295
 296         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 297
 298         /* Special case for older graphic cores. */
 299         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 300                 gpu->identity.model    = chipModel_GC500;
 301                 gpu->identity.revision = etnaviv_field(chipIdentity,
 302                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 303         } else {
 304
 305                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 306                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 307
 308                 /*
 309                  * !!!! HACK ALERT !!!!
 310                  * Because people change device IDs without letting software
 311                  * know about it - here is the hack to make it all look the
 312                  * same.  Only for GC400 family.
 313                  */
 314                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 315                     gpu->identity.model != chipModel_GC420) {
 316                         gpu->identity.model = gpu->identity.model & 0x0400;
 317                 }
 318
 319                 /* Another special case */
 320                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 321                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 322                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 323
 324                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 325                                 /*
 326                                  * This IP has an ECO; put the correct
 327                                  * revision in it.
 328                                  */
 329                                 gpu->identity.revision = 0x1051;
 330                         }
 331                 }
 332         }
 333
 334         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 335                  gpu->identity.model, gpu->identity.revision);
 336
 337         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 338
 339         /* Disable fast clear on GC700. */
 340         if (gpu->identity.model == chipModel_GC700)
 341                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 342
 343         if ((gpu->identity.model == chipModel_GC500 &&
 344              gpu->identity.revision < 2) ||
 345             (gpu->identity.model == chipModel_GC300 &&
 346              gpu->identity.revision < 0x2000)) {
 347
 348                 /*
 349                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 350                  * registers.
 351                  */
 352                 gpu->identity.minor_features0 = 0;
 353                 gpu->identity.minor_features1 = 0;
 354                 gpu->identity.minor_features2 = 0;
 355                 gpu->identity.minor_features3 = 0;
 356                 gpu->identity.minor_features4 = 0;
 357                 gpu->identity.minor_features5 = 0;
 358         } else
 359                 gpu->identity.minor_features0 =
 360                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 361
 362         if (gpu->identity.minor_features0 &
 363             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 364                 gpu->identity.minor_features1 =
 365                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 366                 gpu->identity.minor_features2 =
 367                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 368                 gpu->identity.minor_features3 =
 369                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 370                 gpu->identity.minor_features4 =
 371                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 372                 gpu->identity.minor_features5 =
 373                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 374         }
 375
 376         /* GC600 idle register reports zero bits where modules aren't present */
 377         if (gpu->identity.model == chipModel_GC600) {
 378                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 379                                  VIVS_HI_IDLE_STATE_RA |
 380                                  VIVS_HI_IDLE_STATE_SE |
 381                                  VIVS_HI_IDLE_STATE_PA |
 382                                  VIVS_HI_IDLE_STATE_SH |
 383                                  VIVS_HI_IDLE_STATE_PE |
 384                                  VIVS_HI_IDLE_STATE_DE |
 385                                  VIVS_HI_IDLE_STATE_FE;
 386         } else {
 387                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 388         }
 389
 390         etnaviv_hw_specs(gpu);
 391 }
 392
 393 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 394 {
 395         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 396                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 397         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 398 }
 399
 400 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 401 {
 402         u32 control, idle;
 403         unsigned long timeout;
 404         bool failed = true;
 405
 406         /* TODO
 407          *
 408          * - clock gating
 409          * - puls eater
 410          * - what about VG?
 411          */
 412
 413         /* We hope that the GPU resets in under one second */
 414         timeout = jiffies + msecs_to_jiffies(1000);
 415
 416         while (time_is_after_jiffies(timeout)) {
 417                 control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 418                           VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 419
 420                 /* enable clock */
 421                 etnaviv_gpu_load_clock(gpu, control);
 422
 423                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 424                 usleep_range(1000, 10000);
 425
 426                 /* isolate the GPU. */
 427                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 428                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 429
 430                 /* set soft reset. */
 431                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 432                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 433
 434                 /* wait for reset. */
 435                 msleep(1);
 436
 437                 /* reset soft reset bit. */
 438                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 439                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 440
 441                 /* reset GPU isolation. */
 442                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 443                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 444
 445                 /* read idle register. */
 446                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 447
 448                 /* try reseting again if FE it not idle */
 449                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 450                         dev_dbg(gpu->dev, "FE is not idle\n");
 451                         continue;
 452                 }
 453
 454                 /* read reset register. */
 455                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 456
 457                 /* is the GPU idle? */
 458                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 459                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 460                         dev_dbg(gpu->dev, "GPU is not idle\n");
 461                         continue;
 462                 }
 463
 464                 failed = false;
 465                 break;
 466         }
 467
 468         if (failed) {
 469                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 470                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 471
 472                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 473                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 474                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 475                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 476
 477                 return -EBUSY;
 478         }
 479
 480         /* We rely on the GPU running, so program the clock */
 481         control = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 482                   VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
 483
 484         /* enable clock */
 485         etnaviv_gpu_load_clock(gpu, control);
 486
 487         return 0;
 488 }
 489
 490 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 491 {
 492         u32 pmc, ppc;
 493
 494         /* enable clock gating */
 495         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 496         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 497
 498         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 499         if (gpu->identity.revision == 0x4301 ||
 500             gpu->identity.revision == 0x4302)
 501                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 502
 503         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 504
 505         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 506
 507         /* Disable PA clock gating for GC400+ except for GC420 */
 508         if (gpu->identity.model >= chipModel_GC400 &&
 509             gpu->identity.model != chipModel_GC420)
 510                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 511
 512         /*
 513          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 514          * present without a bug fix.
 515          */
 516         if (gpu->identity.revision < 0x5000 &&
 517             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 518             !(gpu->identity.minor_features1 &
 519               chipMinorFeatures1_DISABLE_PE_GATING))
 520                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 521
 522         if (gpu->identity.revision < 0x5422)
 523                 pmc |= BIT(15); /* Unknown bit */
 524
 525         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 526         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 527
 528         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 529 }
 530
 531 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 532 {
 533         u16 prefetch;
 534
 535         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 536              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 537             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 538                 u32 mc_memory_debug;
 539
 540                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 541
 542                 if (gpu->identity.revision == 0x5007)
 543                         mc_memory_debug |= 0x0c;
 544                 else
 545                         mc_memory_debug |= 0x08;
 546
 547                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 548         }
 549
 550         /* enable module-level clock gating */
 551         etnaviv_gpu_enable_mlcg(gpu);
 552
 553         /*
 554          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 555          * This is necessary to prevent the iMX6 SoC locking up.
 556          */
 557         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 558                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 559                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 560
 561         /* GC2000 rev 5108 needs a special bus config */
 562         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 563                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 564                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 565                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 566                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 567                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 568                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 569         }
 570
 571         /* set base addresses */
 572         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, gpu->memory_base);
 573         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, gpu->memory_base);
 574         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, gpu->memory_base);
 575         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, gpu->memory_base);
 576         gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, gpu->memory_base);
 577
 578         /* setup the MMU page table pointers */
 579         etnaviv_iommu_domain_restore(gpu, gpu->mmu->domain);
 580
 581         /* Start command processor */
 582         prefetch = etnaviv_buffer_init(gpu);
 583
 584         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 585         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS,
 586                   gpu->buffer->paddr - gpu->memory_base);
 587         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 588                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 589                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 590 }
 591
 592 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 593 {
 594         int ret, i;
 595         struct iommu_domain *iommu;
 596         enum etnaviv_iommu_version version;
 597         bool mmuv2;
 598
 599         ret = pm_runtime_get_sync(gpu->dev);
 600         if (ret < 0) {
 601                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 602                 return ret;
 603         }
 604
 605         etnaviv_hw_identify(gpu);
 606
 607         if (gpu->identity.model == 0) {
 608                 dev_err(gpu->dev, "Unknown GPU model\n");
 609                 ret = -ENXIO;
 610                 goto fail;
 611         }
 612
 613         /* Exclude VG cores with FE2.0 */
 614         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 615             gpu->identity.features & chipFeatures_FE20) {
 616                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 617                 ret = -ENXIO;
 618                 goto fail;
 619         }
 620
 621         /*
 622          * Set the GPU linear window to be at the end of the DMA window, where
 623          * the CMA area is likely to reside. This ensures that we are able to
 624          * map the command buffers while having the linear window overlap as
 625          * much RAM as possible, so we can optimize mappings for other buffers.
 626          *
 627          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 628          * to different views of the memory on the individual engines.
 629          */
 630         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 631             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 632                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 633                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 634                         gpu->memory_base = PHYS_OFFSET;
 635                 else
 636                         gpu->memory_base = dma_mask - SZ_2G + 1;
 637         }
 638
 639         ret = etnaviv_hw_reset(gpu);
 640         if (ret) {
 641                 dev_err(gpu->dev, "GPU reset failed\n");
 642                 goto fail;
 643         }
 644
 645         /* Setup IOMMU.. eventually we will (I think) do this once per context
 646          * and have separate page tables per context.  For now, to keep things
 647          * simple and to get something working, just use a single address space:
 648          */
 649         mmuv2 = gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION;
 650         dev_dbg(gpu->dev, "mmuv2: %d\n", mmuv2);
 651
 652         if (!mmuv2) {
 653                 iommu = etnaviv_iommu_domain_alloc(gpu);
 654                 version = ETNAVIV_IOMMU_V1;
 655         } else {
 656                 iommu = etnaviv_iommu_v2_domain_alloc(gpu);
 657                 version = ETNAVIV_IOMMU_V2;
 658         }
 659
 660         if (!iommu) {
 661                 dev_err(gpu->dev, "Failed to allocate GPU IOMMU domain\n");
 662                 ret = -ENOMEM;
 663                 goto fail;
 664         }
 665
 666         gpu->mmu = etnaviv_iommu_new(gpu, iommu, version);
 667         if (!gpu->mmu) {
 668                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 669                 iommu_domain_free(iommu);
 670                 ret = -ENOMEM;
 671                 goto fail;
 672         }
 673
 674         /* Create buffer: */
 675         gpu->buffer = etnaviv_gpu_cmdbuf_new(gpu, PAGE_SIZE, 0);
 676         if (!gpu->buffer) {
 677                 ret = -ENOMEM;
 678                 dev_err(gpu->dev, "could not create command buffer\n");
 679                 goto destroy_iommu;
 680         }
 681         if (gpu->buffer->paddr - gpu->memory_base > 0x80000000) {
 682                 ret = -EINVAL;
 683                 dev_err(gpu->dev,
 684                         "command buffer outside valid memory window\n");
 685                 goto free_buffer;
 686         }
 687
 688         /* Setup event management */
 689         spin_lock_init(&gpu->event_spinlock);
 690         init_completion(&gpu->event_free);
 691         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 692                 gpu->event[i].used = false;
 693                 complete(&gpu->event_free);
 694         }
 695
 696         /* Now program the hardware */
 697         mutex_lock(&gpu->lock);
 698         etnaviv_gpu_hw_init(gpu);
 699         gpu->exec_state = -1;
 700         mutex_unlock(&gpu->lock);
 701
 702         pm_runtime_mark_last_busy(gpu->dev);
 703         pm_runtime_put_autosuspend(gpu->dev);
 704
 705         return 0;
 706
 707 free_buffer:
 708         etnaviv_gpu_cmdbuf_free(gpu->buffer);
 709         gpu->buffer = NULL;
 710 destroy_iommu:
 711         etnaviv_iommu_destroy(gpu->mmu);
 712         gpu->mmu = NULL;
 713 fail:
 714         pm_runtime_mark_last_busy(gpu->dev);
 715         pm_runtime_put_autosuspend(gpu->dev);
 716
 717         return ret;
 718 }
 719
 720 #ifdef CONFIG_DEBUG_FS
 721 struct dma_debug {
 722         u32 address[2];
 723         u32 state[2];
 724 };
 725
 726 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 727 {
 728         u32 i;
 729
 730         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 731         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 732
 733         for (i = 0; i < 500; i++) {
 734                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 735                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 736
 737                 if (debug->address[0] != debug->address[1])
 738                         break;
 739
 740                 if (debug->state[0] != debug->state[1])
 741                         break;
 742         }
 743 }
 744
 745 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 746 {
 747         struct dma_debug debug;
 748         u32 dma_lo, dma_hi, axi, idle;
 749         int ret;
 750
 751         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 752
 753         ret = pm_runtime_get_sync(gpu->dev);
 754         if (ret < 0)
 755                 return ret;
 756
 757         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 758         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 759         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 760         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 761
 762         verify_dma(gpu, &debug);
 763
 764         seq_puts(m, "\tfeatures\n");
 765         seq_printf(m, "\t minor_features0: 0x%08x\n",
 766                    gpu->identity.minor_features0);
 767         seq_printf(m, "\t minor_features1: 0x%08x\n",
 768                    gpu->identity.minor_features1);
 769         seq_printf(m, "\t minor_features2: 0x%08x\n",
 770                    gpu->identity.minor_features2);
 771         seq_printf(m, "\t minor_features3: 0x%08x\n",
 772                    gpu->identity.minor_features3);
 773         seq_printf(m, "\t minor_features4: 0x%08x\n",
 774                    gpu->identity.minor_features4);
 775         seq_printf(m, "\t minor_features5: 0x%08x\n",
 776                    gpu->identity.minor_features5);
 777
 778         seq_puts(m, "\tspecs\n");
 779         seq_printf(m, "\t stream_count:  %d\n",
 780                         gpu->identity.stream_count);
 781         seq_printf(m, "\t register_max: %d\n",
 782                         gpu->identity.register_max);
 783         seq_printf(m, "\t thread_count: %d\n",
 784                         gpu->identity.thread_count);
 785         seq_printf(m, "\t vertex_cache_size: %d\n",
 786                         gpu->identity.vertex_cache_size);
 787         seq_printf(m, "\t shader_core_count: %d\n",
 788                         gpu->identity.shader_core_count);
 789         seq_printf(m, "\t pixel_pipes: %d\n",
 790                         gpu->identity.pixel_pipes);
 791         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 792                         gpu->identity.vertex_output_buffer_size);
 793         seq_printf(m, "\t buffer_size: %d\n",
 794                         gpu->identity.buffer_size);
 795         seq_printf(m, "\t instruction_count: %d\n",
 796                         gpu->identity.instruction_count);
 797         seq_printf(m, "\t num_constants: %d\n",
 798                         gpu->identity.num_constants);
 799         seq_printf(m, "\t varyings_count: %d\n",
 800                         gpu->identity.varyings_count);
 801
 802         seq_printf(m, "\taxi: 0x%08x\n", axi);
 803         seq_printf(m, "\tidle: 0x%08x\n", idle);
 804         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 805         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 806                 seq_puts(m, "\t FE is not idle\n");
 807         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 808                 seq_puts(m, "\t DE is not idle\n");
 809         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 810                 seq_puts(m, "\t PE is not idle\n");
 811         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 812                 seq_puts(m, "\t SH is not idle\n");
 813         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 814                 seq_puts(m, "\t PA is not idle\n");
 815         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 816                 seq_puts(m, "\t SE is not idle\n");
 817         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 818                 seq_puts(m, "\t RA is not idle\n");
 819         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 820                 seq_puts(m, "\t TX is not idle\n");
 821         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 822                 seq_puts(m, "\t VG is not idle\n");
 823         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 824                 seq_puts(m, "\t IM is not idle\n");
 825         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 826                 seq_puts(m, "\t FP is not idle\n");
 827         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 828                 seq_puts(m, "\t TS is not idle\n");
 829         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 830                 seq_puts(m, "\t AXI low power mode\n");
 831
 832         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 833                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 834                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 835                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 836
 837                 seq_puts(m, "\tMC\n");
 838                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 839                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 840                 seq_printf(m, "\t write: 0x%08x\n", write);
 841         }
 842
 843         seq_puts(m, "\tDMA ");
 844
 845         if (debug.address[0] == debug.address[1] &&
 846             debug.state[0] == debug.state[1]) {
 847                 seq_puts(m, "seems to be stuck\n");
 848         } else if (debug.address[0] == debug.address[1]) {
 849                 seq_puts(m, "address is constant\n");
 850         } else {
 851                 seq_puts(m, "is running\n");
 852         }
 853
 854         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 855         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 856         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 857         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 858         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 859                    dma_lo, dma_hi);
 860
 861         ret = 0;
 862
 863         pm_runtime_mark_last_busy(gpu->dev);
 864         pm_runtime_put_autosuspend(gpu->dev);
 865
 866         return ret;
 867 }
 868 #endif
 869
 870 /*
 871  * Power Management:
 872  */
 873 static int enable_clk(struct etnaviv_gpu *gpu)
 874 {
 875         int ret;
 876
 877         if (gpu->clk_core) {
 878                 ret = clk_prepare_enable(gpu->clk_core);
 879                 if (ret)
 880                         return ret;
 881         }
 882
 883         if (gpu->clk_shader) {
 884                 ret = clk_prepare_enable(gpu->clk_shader);
 885                 if (ret)
 886                         goto disable_clk_core;
 887         }
 888
 889         return 0;
 890
 891 disable_clk_core:
 892         clk_disable_unprepare(gpu->clk_core);
 893         return ret;
 894 }
 895
 896 static int disable_clk(struct etnaviv_gpu *gpu)
 897 {
 898         if (gpu->clk_core)
 899                 clk_disable_unprepare(gpu->clk_core);
 900         if (gpu->clk_shader)
 901                 clk_disable_unprepare(gpu->clk_shader);
 902
 903         return 0;
 904 }
 905
 906 static int enable_axi(struct etnaviv_gpu *gpu)
 907 {
 908         int ret;
 909
 910         if (gpu->clk_bus) {
 911                 ret = clk_prepare_enable(gpu->clk_bus);
 912                 if (ret)
 913                         return ret;
 914         }
 915
 916         return 0;
 917 }
 918
 919 static int disable_axi(struct etnaviv_gpu *gpu)
 920 {
 921         if (gpu->clk_bus)
 922                 clk_disable_unprepare(gpu->clk_bus);
 923
 924         return 0;
 925 }
 926
 927 /*
 928  * Hangcheck detection for locked gpu:
 929  */
 930 static void recover_worker(struct work_struct *work)
 931 {
 932         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 933                                                recover_work);
 934         unsigned long flags;
 935         unsigned int i;
 936
 937         dev_err(gpu->dev, "hangcheck recover!\n");
 938
 939         if (pm_runtime_get_sync(gpu->dev) < 0)
 940                 return;
 941
 942         mutex_lock(&gpu->lock);
 943
 944         /* Only catch the first event, or when manually re-armed */
 945         if (etnaviv_dump_core) {
 946                 etnaviv_core_dump(gpu);
 947                 etnaviv_dump_core = false;
 948         }
 949
 950         etnaviv_hw_reset(gpu);
 951
 952         /* complete all events, the GPU won't do it after the reset */
 953         spin_lock_irqsave(&gpu->event_spinlock, flags);
 954         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 955                 if (!gpu->event[i].used)
 956                         continue;
 957                 fence_signal(gpu->event[i].fence);
 958                 gpu->event[i].fence = NULL;
 959                 gpu->event[i].used = false;
 960                 complete(&gpu->event_free);
 961         }
 962         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 963         gpu->completed_fence = gpu->active_fence;
 964
 965         etnaviv_gpu_hw_init(gpu);
 966         gpu->switch_context = true;
 967         gpu->exec_state = -1;
 968
 969         mutex_unlock(&gpu->lock);
 970         pm_runtime_mark_last_busy(gpu->dev);
 971         pm_runtime_put_autosuspend(gpu->dev);
 972
 973         /* Retire the buffer objects in a work */
 974         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 975 }
 976
 977 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 978 {
 979         DBG("%s", dev_name(gpu->dev));
 980         mod_timer(&gpu->hangcheck_timer,
 981                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 982 }
 983
 984 static void hangcheck_handler(unsigned long data)
 985 {
 986         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 987         u32 fence = gpu->completed_fence;
 988         bool progress = false;
 989
 990         if (fence != gpu->hangcheck_fence) {
 991                 gpu->hangcheck_fence = fence;
 992                 progress = true;
 993         }
 994
 995         if (!progress) {
 996                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 997                 int change = dma_addr - gpu->hangcheck_dma_addr;
 998
 999                 if (change < 0 || change > 16) {
1000                         gpu->hangcheck_dma_addr = dma_addr;
1001                         progress = true;
1002                 }
1003         }
1004
1005         if (!progress && fence_after(gpu->active_fence, fence)) {
1006                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
1007                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
1008                 dev_err(gpu->dev, "     active fence: %u\n",
1009                         gpu->active_fence);
1010                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
1011         }
1012
1013         /* if still more pending work, reset the hangcheck timer: */
1014         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
1015                 hangcheck_timer_reset(gpu);
1016 }
1017
1018 static void hangcheck_disable(struct etnaviv_gpu *gpu)
1019 {
1020         del_timer_sync(&gpu->hangcheck_timer);
1021         cancel_work_sync(&gpu->recover_work);
1022 }
1023
1024 /* fence object management */
1025 struct etnaviv_fence {
1026         struct etnaviv_gpu *gpu;
1027         struct fence base;
1028 };
1029
1030 static inline struct etnaviv_fence *to_etnaviv_fence(struct fence *fence)
1031 {
1032         return container_of(fence, struct etnaviv_fence, base);
1033 }
1034
1035 static const char *etnaviv_fence_get_driver_name(struct fence *fence)
1036 {
1037         return "etnaviv";
1038 }
1039
1040 static const char *etnaviv_fence_get_timeline_name(struct fence *fence)
1041 {
1042         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1043
1044         return dev_name(f->gpu->dev);
1045 }
1046
1047 static bool etnaviv_fence_enable_signaling(struct fence *fence)
1048 {
1049         return true;
1050 }
1051
1052 static bool etnaviv_fence_signaled(struct fence *fence)
1053 {
1054         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1055
1056         return fence_completed(f->gpu, f->base.seqno);
1057 }
1058
1059 static void etnaviv_fence_release(struct fence *fence)
1060 {
1061         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1062
1063         kfree_rcu(f, base.rcu);
1064 }
1065
1066 static const struct fence_ops etnaviv_fence_ops = {
1067         .get_driver_name = etnaviv_fence_get_driver_name,
1068         .get_timeline_name = etnaviv_fence_get_timeline_name,
1069         .enable_signaling = etnaviv_fence_enable_signaling,
1070         .signaled = etnaviv_fence_signaled,
1071         .wait = fence_default_wait,
1072         .release = etnaviv_fence_release,
1073 };
1074
1075 static struct fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1076 {
1077         struct etnaviv_fence *f;
1078
1079         f = kzalloc(sizeof(*f), GFP_KERNEL);
1080         if (!f)
1081                 return NULL;
1082
1083         f->gpu = gpu;
1084
1085         fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1086                    gpu->fence_context, ++gpu->next_fence);
1087
1088         return &f->base;
1089 }
1090
1091 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1092         unsigned int context, bool exclusive)
1093 {
1094         struct reservation_object *robj = etnaviv_obj->resv;
1095         struct reservation_object_list *fobj;
1096         struct fence *fence;
1097         int i, ret;
1098
1099         if (!exclusive) {
1100                 ret = reservation_object_reserve_shared(robj);
1101                 if (ret)
1102                         return ret;
1103         }
1104
1105         /*
1106          * If we have any shared fences, then the exclusive fence
1107          * should be ignored as it will already have been signalled.
1108          */
1109         fobj = reservation_object_get_list(robj);
1110         if (!fobj || fobj->shared_count == 0) {
1111                 /* Wait on any existing exclusive fence which isn't our own */
1112                 fence = reservation_object_get_excl(robj);
1113                 if (fence && fence->context != context) {
1114                         ret = fence_wait(fence, true);
1115                         if (ret)
1116                                 return ret;
1117                 }
1118         }
1119
1120         if (!exclusive || !fobj)
1121                 return 0;
1122
1123         for (i = 0; i < fobj->shared_count; i++) {
1124                 fence = rcu_dereference_protected(fobj->shared[i],
1125                                                 reservation_object_held(robj));
1126                 if (fence->context != context) {
1127                         ret = fence_wait(fence, true);
1128                         if (ret)
1129                                 return ret;
1130                 }
1131         }
1132
1133         return 0;
1134 }
1135
1136 /*
1137  * event management:
1138  */
1139
1140 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1141 {
1142         unsigned long ret, flags;
1143         unsigned int i, event = ~0U;
1144
1145         ret = wait_for_completion_timeout(&gpu->event_free,
1146                                           msecs_to_jiffies(10 * 10000));
1147         if (!ret)
1148                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1149
1150         spin_lock_irqsave(&gpu->event_spinlock, flags);
1151
1152         /* find first free event */
1153         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1154                 if (gpu->event[i].used == false) {
1155                         gpu->event[i].used = true;
1156                         event = i;
1157                         break;
1158                 }
1159         }
1160
1161         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1162
1163         return event;
1164 }
1165
1166 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1167 {
1168         unsigned long flags;
1169
1170         spin_lock_irqsave(&gpu->event_spinlock, flags);
1171
1172         if (gpu->event[event].used == false) {
1173                 dev_warn(gpu->dev, "event %u is already marked as free",
1174                          event);
1175                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1176         } else {
1177                 gpu->event[event].used = false;
1178                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1179
1180                 complete(&gpu->event_free);
1181         }
1182 }
1183
1184 /*
1185  * Cmdstream submission/retirement:
1186  */
1187
1188 struct etnaviv_cmdbuf *etnaviv_gpu_cmdbuf_new(struct etnaviv_gpu *gpu, u32 size,
1189         size_t nr_bos)
1190 {
1191         struct etnaviv_cmdbuf *cmdbuf;
1192         size_t sz = size_vstruct(nr_bos, sizeof(cmdbuf->bo_map[0]),
1193                                  sizeof(*cmdbuf));
1194
1195         cmdbuf = kzalloc(sz, GFP_KERNEL);
1196         if (!cmdbuf)
1197                 return NULL;
1198
1199         cmdbuf->vaddr = dma_alloc_wc(gpu->dev, size, &cmdbuf->paddr,
1200                                      GFP_KERNEL);
1201         if (!cmdbuf->vaddr) {
1202                 kfree(cmdbuf);
1203                 return NULL;
1204         }
1205
1206         cmdbuf->gpu = gpu;
1207         cmdbuf->size = size;
1208
1209         return cmdbuf;
1210 }
1211
1212 void etnaviv_gpu_cmdbuf_free(struct etnaviv_cmdbuf *cmdbuf)
1213 {
1214         dma_free_wc(cmdbuf->gpu->dev, cmdbuf->size, cmdbuf->vaddr,
1215                     cmdbuf->paddr);
1216         kfree(cmdbuf);
1217 }
1218
1219 static void retire_worker(struct work_struct *work)
1220 {
1221         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1222                                                retire_work);
1223         u32 fence = gpu->completed_fence;
1224         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1225         unsigned int i;
1226
1227         mutex_lock(&gpu->lock);
1228         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1229                 if (!fence_is_signaled(cmdbuf->fence))
1230                         break;
1231
1232                 list_del(&cmdbuf->node);
1233                 fence_put(cmdbuf->fence);
1234
1235                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1236                         struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i];
1237                         struct etnaviv_gem_object *etnaviv_obj = mapping->object;
1238
1239                         atomic_dec(&etnaviv_obj->gpu_active);
1240                         /* drop the refcount taken in etnaviv_gpu_submit */
1241                         etnaviv_gem_mapping_unreference(mapping);
1242                 }
1243
1244                 etnaviv_gpu_cmdbuf_free(cmdbuf);
1245                 /*
1246                  * We need to balance the runtime PM count caused by
1247                  * each submission.  Upon submission, we increment
1248                  * the runtime PM counter, and allocate one event.
1249                  * So here, we put the runtime PM count for each
1250                  * completed event.
1251                  */
1252                 pm_runtime_put_autosuspend(gpu->dev);
1253         }
1254
1255         gpu->retired_fence = fence;
1256
1257         mutex_unlock(&gpu->lock);
1258
1259         wake_up_all(&gpu->fence_event);
1260 }
1261
1262 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1263         u32 fence, struct timespec *timeout)
1264 {
1265         int ret;
1266
1267         if (fence_after(fence, gpu->next_fence)) {
1268                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1269                                 fence, gpu->next_fence);
1270                 return -EINVAL;
1271         }
1272
1273         if (!timeout) {
1274                 /* No timeout was requested: just test for completion */
1275                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1276         } else {
1277                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1278
1279                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1280                                                 fence_completed(gpu, fence),
1281                                                 remaining);
1282                 if (ret == 0) {
1283                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1284                                 fence, gpu->retired_fence,
1285                                 gpu->completed_fence);
1286                         ret = -ETIMEDOUT;
1287                 } else if (ret != -ERESTARTSYS) {
1288                         ret = 0;
1289                 }
1290         }
1291
1292         return ret;
1293 }
1294
1295 /*
1296  * Wait for an object to become inactive.  This, on it's own, is not race
1297  * free: the object is moved by the retire worker off the active list, and
1298  * then the iova is put.  Moreover, the object could be re-submitted just
1299  * after we notice that it's become inactive.
1300  *
1301  * Although the retirement happens under the gpu lock, we don't want to hold
1302  * that lock in this function while waiting.
1303  */
1304 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1305         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1306 {
1307         unsigned long remaining;
1308         long ret;
1309
1310         if (!timeout)
1311                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1312
1313         remaining = etnaviv_timeout_to_jiffies(timeout);
1314
1315         ret = wait_event_interruptible_timeout(gpu->fence_event,
1316                                                !is_active(etnaviv_obj),
1317                                                remaining);
1318         if (ret > 0) {
1319                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1320
1321                 /* Synchronise with the retire worker */
1322                 flush_workqueue(priv->wq);
1323                 return 0;
1324         } else if (ret == -ERESTARTSYS) {
1325                 return -ERESTARTSYS;
1326         } else {
1327                 return -ETIMEDOUT;
1328         }
1329 }
1330
1331 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1332 {
1333         return pm_runtime_get_sync(gpu->dev);
1334 }
1335
1336 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1337 {
1338         pm_runtime_mark_last_busy(gpu->dev);
1339         pm_runtime_put_autosuspend(gpu->dev);
1340 }
1341
1342 /* add bo's to gpu's ring, and kick gpu: */
1343 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1344         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1345 {
1346         struct fence *fence;
1347         unsigned int event, i;
1348         int ret;
1349
1350         ret = etnaviv_gpu_pm_get_sync(gpu);
1351         if (ret < 0)
1352                 return ret;
1353
1354         /*
1355          * TODO
1356          *
1357          * - flush
1358          * - data endian
1359          * - prefetch
1360          *
1361          */
1362
1363         event = event_alloc(gpu);
1364         if (unlikely(event == ~0U)) {
1365                 DRM_ERROR("no free event\n");
1366                 ret = -EBUSY;
1367                 goto out_pm_put;
1368         }
1369
1370         fence = etnaviv_gpu_fence_alloc(gpu);
1371         if (!fence) {
1372                 event_free(gpu, event);
1373                 ret = -ENOMEM;
1374                 goto out_pm_put;
1375         }
1376
1377         mutex_lock(&gpu->lock);
1378
1379         gpu->event[event].fence = fence;
1380         submit->fence = fence->seqno;
1381         gpu->active_fence = submit->fence;
1382
1383         if (gpu->lastctx != cmdbuf->ctx) {
1384                 gpu->mmu->need_flush = true;
1385                 gpu->switch_context = true;
1386                 gpu->lastctx = cmdbuf->ctx;
1387         }
1388
1389         etnaviv_buffer_queue(gpu, event, cmdbuf);
1390
1391         cmdbuf->fence = fence;
1392         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1393
1394         /* We're committed to adding this command buffer, hold a PM reference */
1395         pm_runtime_get_noresume(gpu->dev);
1396
1397         for (i = 0; i < submit->nr_bos; i++) {
1398                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1399
1400                 /* Each cmdbuf takes a refcount on the mapping */
1401                 etnaviv_gem_mapping_reference(submit->bos[i].mapping);
1402                 cmdbuf->bo_map[i] = submit->bos[i].mapping;
1403                 atomic_inc(&etnaviv_obj->gpu_active);
1404
1405                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1406                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1407                                                           fence);
1408                 else
1409                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1410                                                             fence);
1411         }
1412         cmdbuf->nr_bos = submit->nr_bos;
1413         hangcheck_timer_reset(gpu);
1414         ret = 0;
1415
1416         mutex_unlock(&gpu->lock);
1417
1418 out_pm_put:
1419         etnaviv_gpu_pm_put(gpu);
1420
1421         return ret;
1422 }
1423
1424 /*
1425  * Init/Cleanup:
1426  */
1427 static irqreturn_t irq_handler(int irq, void *data)
1428 {
1429         struct etnaviv_gpu *gpu = data;
1430         irqreturn_t ret = IRQ_NONE;
1431
1432         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1433
1434         if (intr != 0) {
1435                 int event;
1436
1437                 pm_runtime_mark_last_busy(gpu->dev);
1438
1439                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1440
1441                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1442                         dev_err(gpu->dev, "AXI bus error\n");
1443                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1444                 }
1445
1446                 while ((event = ffs(intr)) != 0) {
1447                         struct fence *fence;
1448
1449                         event -= 1;
1450
1451                         intr &= ~(1 << event);
1452
1453                         dev_dbg(gpu->dev, "event %u\n", event);
1454
1455                         fence = gpu->event[event].fence;
1456                         gpu->event[event].fence = NULL;
1457                         fence_signal(fence);
1458
1459                         /*
1460                          * Events can be processed out of order.  Eg,
1461                          * - allocate and queue event 0
1462                          * - allocate event 1
1463                          * - event 0 completes, we process it
1464                          * - allocate and queue event 0
1465                          * - event 1 and event 0 complete
1466                          * we can end up processing event 0 first, then 1.
1467                          */
1468                         if (fence_after(fence->seqno, gpu->completed_fence))
1469                                 gpu->completed_fence = fence->seqno;
1470
1471                         event_free(gpu, event);
1472                 }
1473
1474                 /* Retire the buffer objects in a work */
1475                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1476
1477                 ret = IRQ_HANDLED;
1478         }
1479
1480         return ret;
1481 }
1482
1483 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1484 {
1485         int ret;
1486
1487         ret = enable_clk(gpu);
1488         if (ret)
1489                 return ret;
1490
1491         ret = enable_axi(gpu);
1492         if (ret) {
1493                 disable_clk(gpu);
1494                 return ret;
1495         }
1496
1497         return 0;
1498 }
1499
1500 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1501 {
1502         int ret;
1503
1504         ret = disable_axi(gpu);
1505         if (ret)
1506                 return ret;
1507
1508         ret = disable_clk(gpu);
1509         if (ret)
1510                 return ret;
1511
1512         return 0;
1513 }
1514
1515 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1516 {
1517         if (gpu->buffer) {
1518                 unsigned long timeout;
1519
1520                 /* Replace the last WAIT with END */
1521                 etnaviv_buffer_end(gpu);
1522
1523                 /*
1524                  * We know that only the FE is busy here, this should
1525                  * happen quickly (as the WAIT is only 200 cycles).  If
1526                  * we fail, just warn and continue.
1527                  */
1528                 timeout = jiffies + msecs_to_jiffies(100);
1529                 do {
1530                         u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1531
1532                         if ((idle & gpu->idle_mask) == gpu->idle_mask)
1533                                 break;
1534
1535                         if (time_is_before_jiffies(timeout)) {
1536                                 dev_warn(gpu->dev,
1537                                          "timed out waiting for idle: idle=0x%x\n",
1538                                          idle);
1539                                 break;
1540                         }
1541
1542                         udelay(5);
1543                 } while (1);
1544         }
1545
1546         return etnaviv_gpu_clk_disable(gpu);
1547 }
1548
1549 #ifdef CONFIG_PM
1550 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1551 {
1552         u32 clock;
1553         int ret;
1554
1555         ret = mutex_lock_killable(&gpu->lock);
1556         if (ret)
1557                 return ret;
1558
1559         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
1560                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(0x40);
1561
1562         etnaviv_gpu_load_clock(gpu, clock);
1563         etnaviv_gpu_hw_init(gpu);
1564
1565         gpu->switch_context = true;
1566         gpu->exec_state = -1;
1567
1568         mutex_unlock(&gpu->lock);
1569
1570         return 0;
1571 }
1572 #endif
1573
1574 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1575         void *data)
1576 {
1577         struct drm_device *drm = data;
1578         struct etnaviv_drm_private *priv = drm->dev_private;
1579         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1580         int ret;
1581
1582 #ifdef CONFIG_PM
1583         ret = pm_runtime_get_sync(gpu->dev);
1584 #else
1585         ret = etnaviv_gpu_clk_enable(gpu);
1586 #endif
1587         if (ret < 0)
1588                 return ret;
1589
1590         gpu->drm = drm;
1591         gpu->fence_context = fence_context_alloc(1);
1592         spin_lock_init(&gpu->fence_spinlock);
1593
1594         INIT_LIST_HEAD(&gpu->active_cmd_list);
1595         INIT_WORK(&gpu->retire_work, retire_worker);
1596         INIT_WORK(&gpu->recover_work, recover_worker);
1597         init_waitqueue_head(&gpu->fence_event);
1598
1599         setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
1600                                (unsigned long)gpu);
1601
1602         priv->gpu[priv->num_gpus++] = gpu;
1603
1604         pm_runtime_mark_last_busy(gpu->dev);
1605         pm_runtime_put_autosuspend(gpu->dev);
1606
1607         return 0;
1608 }
1609
1610 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1611         void *data)
1612 {
1613         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1614
1615         DBG("%s", dev_name(gpu->dev));
1616
1617         hangcheck_disable(gpu);
1618
1619 #ifdef CONFIG_PM
1620         pm_runtime_get_sync(gpu->dev);
1621         pm_runtime_put_sync_suspend(gpu->dev);
1622 #else
1623         etnaviv_gpu_hw_suspend(gpu);
1624 #endif
1625
1626         if (gpu->buffer) {
1627                 etnaviv_gpu_cmdbuf_free(gpu->buffer);
1628                 gpu->buffer = NULL;
1629         }
1630
1631         if (gpu->mmu) {
1632                 etnaviv_iommu_destroy(gpu->mmu);
1633                 gpu->mmu = NULL;
1634         }
1635
1636         gpu->drm = NULL;
1637 }
1638
1639 static const struct component_ops gpu_ops = {
1640         .bind = etnaviv_gpu_bind,
1641         .unbind = etnaviv_gpu_unbind,
1642 };
1643
1644 static const struct of_device_id etnaviv_gpu_match[] = {
1645         {
1646                 .compatible = "vivante,gc"
1647         },
1648         { /* sentinel */ }
1649 };
1650
1651 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1652 {
1653         struct device *dev = &pdev->dev;
1654         struct etnaviv_gpu *gpu;
1655         int err = 0;
1656
1657         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1658         if (!gpu)
1659                 return -ENOMEM;
1660
1661         gpu->dev = &pdev->dev;
1662         mutex_init(&gpu->lock);
1663
1664         /* Map registers: */
1665         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1666         if (IS_ERR(gpu->mmio))
1667                 return PTR_ERR(gpu->mmio);
1668
1669         /* Get Interrupt: */
1670         gpu->irq = platform_get_irq(pdev, 0);
1671         if (gpu->irq < 0) {
1672                 err = gpu->irq;
1673                 dev_err(dev, "failed to get irq: %d\n", err);
1674                 goto fail;
1675         }
1676
1677         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1678                                dev_name(gpu->dev), gpu);
1679         if (err) {
1680                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1681                 goto fail;
1682         }
1683
1684         /* Get Clocks: */
1685         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1686         DBG("clk_bus: %p", gpu->clk_bus);
1687         if (IS_ERR(gpu->clk_bus))
1688                 gpu->clk_bus = NULL;
1689
1690         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1691         DBG("clk_core: %p", gpu->clk_core);
1692         if (IS_ERR(gpu->clk_core))
1693                 gpu->clk_core = NULL;
1694
1695         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1696         DBG("clk_shader: %p", gpu->clk_shader);
1697         if (IS_ERR(gpu->clk_shader))
1698                 gpu->clk_shader = NULL;
1699
1700         /* TODO: figure out max mapped size */
1701         dev_set_drvdata(dev, gpu);
1702
1703         /*
1704          * We treat the device as initially suspended.  The runtime PM
1705          * autosuspend delay is rather arbitary: no measurements have
1706          * yet been performed to determine an appropriate value.
1707          */
1708         pm_runtime_use_autosuspend(gpu->dev);
1709         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1710         pm_runtime_enable(gpu->dev);
1711
1712         err = component_add(&pdev->dev, &gpu_ops);
1713         if (err < 0) {
1714                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1715                 goto fail;
1716         }
1717
1718         return 0;
1719
1720 fail:
1721         return err;
1722 }
1723
1724 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1725 {
1726         component_del(&pdev->dev, &gpu_ops);
1727         pm_runtime_disable(&pdev->dev);
1728         return 0;
1729 }
1730
1731 #ifdef CONFIG_PM
1732 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1733 {
1734         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1735         u32 idle, mask;
1736
1737         /* If we have outstanding fences, we're not idle */
1738         if (gpu->completed_fence != gpu->active_fence)
1739                 return -EBUSY;
1740
1741         /* Check whether the hardware (except FE) is idle */
1742         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1743         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1744         if (idle != mask)
1745                 return -EBUSY;
1746
1747         return etnaviv_gpu_hw_suspend(gpu);
1748 }
1749
1750 static int etnaviv_gpu_rpm_resume(struct device *dev)
1751 {
1752         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1753         int ret;
1754
1755         ret = etnaviv_gpu_clk_enable(gpu);
1756         if (ret)
1757                 return ret;
1758
1759         /* Re-initialise the basic hardware state */
1760         if (gpu->drm && gpu->buffer) {
1761                 ret = etnaviv_gpu_hw_resume(gpu);
1762                 if (ret) {
1763                         etnaviv_gpu_clk_disable(gpu);
1764                         return ret;
1765                 }
1766         }
1767
1768         return 0;
1769 }
1770 #endif
1771
1772 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1773         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1774                            NULL)
1775 };
1776
1777 struct platform_driver etnaviv_gpu_driver = {
1778         .driver = {
1779                 .name = "etnaviv-gpu",
1780                 .owner = THIS_MODULE,
1781                 .pm = &etnaviv_gpu_pm_ops,
1782                 .of_match_table = etnaviv_gpu_match,
1783         },
1784         .probe = etnaviv_gpu_platform_probe,
1785         .remove = etnaviv_gpu_platform_remove,
1786         .id_table = gpu_ids,
1787 };