drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include "drmP.h"
  14 #include "drm_crtc_helper.h"
  15
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/gpio.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/of.h>
  26 #include <linux/workqueue.h>
  27
  28 #include <video/exynos_dp.h>
  29 #include "exynos_drm_drv.h"
  30 #include "exynos_drm_display.h"
  31
  32 #ifdef CONFIG_DRM_PTN3460
  33 #include "i2c/ptn3460.h"
  34 #endif
  35
  36 #include <plat/cpu.h>
  37
  38 #include "exynos_dp_core.h"
  39
  40 #define PLL_MAX_TRIES 100
  41
  42 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  43 {
  44         exynos_dp_reset(dp);
  45
  46         /* SW defined function Normal operation */
  47         exynos_dp_enable_sw_function(dp);
  48
  49         exynos_dp_init_analog_func(dp);
  50
  51         exynos_dp_init_hpd(dp);
  52         exynos_dp_init_aux(dp);
  53
  54         return 0;
  55 }
  56
  57 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  58 {
  59         int timeout_loop = 0;
  60
  61         if (gpio_is_valid(dp->hpd_gpio))
  62                 return !gpio_get_value(dp->hpd_gpio);
  63
  64         while (exynos_dp_get_plug_in_status(dp) != 0) {
  65                 timeout_loop++;
  66                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  67                         dev_err(dp->dev, "failed to get hpd plug status\n");
  68                         return -ETIMEDOUT;
  69                 }
  70                 udelay(10);
  71         }
  72
  73         return 0;
  74 }
  75
  76 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  77 {
  78         int i;
  79         unsigned char sum = 0;
  80
  81         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  82                 sum = sum + edid_data[i];
  83
  84         return sum;
  85 }
  86
  87 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  88 {
  89         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  90         unsigned int extend_block = 0;
  91         unsigned char sum;
  92         unsigned char test_vector;
  93         int retval;
  94
  95         /*
  96          * EDID device address is 0x50.
  97          * However, if necessary, you must have set upper address
  98          * into E-EDID in I2C device, 0x30.
  99          */
 100
 101         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 102         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 103                                 EDID_EXTENSION_FLAG,
 104                                 &extend_block);
 105         if (retval)
 106                 return retval;
 107
 108         if (extend_block > 0) {
 109                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 110
 111                 /* Read EDID data */
 112                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 113                                                 EDID_HEADER_PATTERN,
 114                                                 EDID_BLOCK_LENGTH,
 115                                                 &edid[EDID_HEADER_PATTERN]);
 116                 if (retval != 0) {
 117                         dev_err(dp->dev, "EDID Read failed!\n");
 118                         return -EIO;
 119                 }
 120                 sum = exynos_dp_calc_edid_check_sum(edid);
 121                 if (sum != 0) {
 122                         dev_err(dp->dev, "EDID bad checksum!\n");
 123                         return -EIO;
 124                 }
 125
 126                 /* Read additional EDID data */
 127                 retval = exynos_dp_read_bytes_from_i2c(dp,
 128                                 I2C_EDID_DEVICE_ADDR,
 129                                 EDID_BLOCK_LENGTH,
 130                                 EDID_BLOCK_LENGTH,
 131                                 &edid[EDID_BLOCK_LENGTH]);
 132                 if (retval != 0) {
 133                         dev_err(dp->dev, "EDID Read failed!\n");
 134                         return -EIO;
 135                 }
 136                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 137                 if (sum != 0) {
 138                         dev_err(dp->dev, "EDID bad checksum!\n");
 139                         return -EIO;
 140                 }
 141
 142                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 143                                         &test_vector);
 144                 if (test_vector & DPCD_TEST_EDID_READ) {
 145                         exynos_dp_write_byte_to_dpcd(dp,
 146                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 147                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 148                         exynos_dp_write_byte_to_dpcd(dp,
 149                                 DPCD_ADDR_TEST_RESPONSE,
 150                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 151                 }
 152         } else {
 153                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 154
 155                 /* Read EDID data */
 156                 retval = exynos_dp_read_bytes_from_i2c(dp,
 157                                 I2C_EDID_DEVICE_ADDR,
 158                                 EDID_HEADER_PATTERN,
 159                                 EDID_BLOCK_LENGTH,
 160                                 &edid[EDID_HEADER_PATTERN]);
 161                 if (retval != 0) {
 162                         dev_err(dp->dev, "EDID Read failed!\n");
 163                         return -EIO;
 164                 }
 165                 sum = exynos_dp_calc_edid_check_sum(edid);
 166                 if (sum != 0) {
 167                         dev_err(dp->dev, "EDID bad checksum!\n");
 168                         return -EIO;
 169                 }
 170
 171                 exynos_dp_read_byte_from_dpcd(dp,
 172                         DPCD_ADDR_TEST_REQUEST,
 173                         &test_vector);
 174                 if (test_vector & DPCD_TEST_EDID_READ) {
 175                         exynos_dp_write_byte_to_dpcd(dp,
 176                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 177                                 edid[EDID_CHECKSUM]);
 178                         exynos_dp_write_byte_to_dpcd(dp,
 179                                 DPCD_ADDR_TEST_RESPONSE,
 180                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 181                 }
 182         }
 183
 184         dev_err(dp->dev, "EDID Read success!\n");
 185         return 0;
 186 }
 187
 188 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 189 {
 190         u8 buf[12];
 191         int i;
 192         int ret;
 193
 194         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 195         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, 12, buf);
 196         if (ret)
 197                 return ret;
 198
 199         /* Read EDID */
 200         for (i = 0; i < 3; i++) {
 201                 ret = exynos_dp_read_edid(dp);
 202                 if (!ret)
 203                         break;
 204         }
 205
 206         return ret;
 207 }
 208
 209 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 210                                                 bool enable)
 211 {
 212         u8 data;
 213
 214         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 215
 216         if (enable)
 217                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 218                         DPCD_ENHANCED_FRAME_EN |
 219                         DPCD_LANE_COUNT_SET(data));
 220         else
 221                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 222                         DPCD_LANE_COUNT_SET(data));
 223 }
 224
 225 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 226 {
 227         u8 data;
 228         int retval;
 229
 230         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 231         retval = DPCD_ENHANCED_FRAME_CAP(data);
 232
 233         return retval;
 234 }
 235
 236 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 237 {
 238         u8 data;
 239
 240         data = exynos_dp_is_enhanced_mode_available(dp);
 241         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 242         exynos_dp_enable_enhanced_mode(dp, data);
 243 }
 244
 245 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 246 {
 247         exynos_dp_set_training_pattern(dp, DP_NONE);
 248
 249         exynos_dp_write_byte_to_dpcd(dp,
 250                 DPCD_ADDR_TRAINING_PATTERN_SET,
 251                 DPCD_TRAINING_PATTERN_DISABLED);
 252 }
 253
 254 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 255                                         int pre_emphasis, int lane)
 256 {
 257         switch (lane) {
 258         case 0:
 259                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 260                 break;
 261         case 1:
 262                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 263                 break;
 264
 265         case 2:
 266                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 267                 break;
 268
 269         case 3:
 270                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 271                 break;
 272         }
 273 }
 274
 275 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 276 {
 277         int ret, lane, lane_count, pll_tries;
 278         u8 buf[4];
 279
 280         lane_count = dp->link_train.lane_count;
 281
 282         dp->link_train.lt_state = CLOCK_RECOVERY;
 283         dp->link_train.eq_loop = 0;
 284
 285         for (lane = 0; lane < lane_count; lane++)
 286                 dp->link_train.cr_loop[lane] = 0;
 287
 288         /* Set link rate and count as you want to establish*/
 289         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 290         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 291
 292         /* Setup RX configuration */
 293         buf[0] = dp->link_train.link_rate;
 294         buf[1] = dp->link_train.lane_count;
 295         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 296         if (ret)
 297                 return ret;
 298
 299         /* Set TX pre-emphasis to minimum */
 300         for (lane = 0; lane < lane_count; lane++)
 301                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 302                         PRE_EMPHASIS_LEVEL_0, lane);
 303
 304         /* Wait for PLL lock */
 305         pll_tries = 0;
 306         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 307                 if (pll_tries == PLL_MAX_TRIES)
 308                         return -ETIMEDOUT;
 309
 310                 pll_tries++;
 311                 udelay(100);
 312         }
 313
 314         /* Set training pattern 1 */
 315         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 316
 317         /* Set RX training pattern */
 318         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 319                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 320         if (ret)
 321                 return ret;
 322
 323         for (lane = 0; lane < lane_count; lane++)
 324                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 325                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 326         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 327                 lane_count, buf);
 328         if (ret)
 329                 return ret;
 330
 331         return ret;
 332 }
 333
 334 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 335 {
 336         int shift = (lane & 1) * 4;
 337         u8 link_value = link_status[lane>>1];
 338
 339         return (link_value >> shift) & 0xf;
 340 }
 341
 342 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 343 {
 344         int lane;
 345         u8 lane_status;
 346
 347         for (lane = 0; lane < lane_count; lane++) {
 348                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 349                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 350                         return -EINVAL;
 351         }
 352         return 0;
 353 }
 354
 355 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 356 {
 357         int lane;
 358         u8 lane_align;
 359         u8 lane_status;
 360
 361         lane_align = link_status[2];
 362         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 363                 return -EINVAL;
 364
 365         for (lane = 0; lane < lane_count; lane++) {
 366                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 367                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 368                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 369                         return -EINVAL;
 370         }
 371         return 0;
 372 }
 373
 374 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 375                                                         int lane)
 376 {
 377         int shift = (lane & 1) * 4;
 378         u8 link_value = adjust_request[lane>>1];
 379
 380         return (link_value >> shift) & 0x3;
 381 }
 382
 383 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 384                                         u8 adjust_request[2],
 385                                         int lane)
 386 {
 387         int shift = (lane & 1) * 4;
 388         u8 link_value = adjust_request[lane>>1];
 389
 390         return ((link_value >> shift) & 0xc) >> 2;
 391 }
 392
 393 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 394                                         u8 training_lane_set, int lane)
 395 {
 396         switch (lane) {
 397         case 0:
 398                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 399                 break;
 400         case 1:
 401                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 402                 break;
 403
 404         case 2:
 405                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 406                 break;
 407
 408         case 3:
 409                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 410                 break;
 411         }
 412 }
 413
 414 static unsigned int exynos_dp_get_lane_link_training(
 415                                 struct exynos_dp_device *dp,
 416                                 int lane)
 417 {
 418         u32 reg = 0;
 419
 420         switch (lane) {
 421         case 0:
 422                 reg = exynos_dp_get_lane0_link_training(dp);
 423                 break;
 424         case 1:
 425                 reg = exynos_dp_get_lane1_link_training(dp);
 426                 break;
 427         case 2:
 428                 reg = exynos_dp_get_lane2_link_training(dp);
 429                 break;
 430         case 3:
 431                 reg = exynos_dp_get_lane3_link_training(dp);
 432                 break;
 433         }
 434
 435         return reg;
 436 }
 437
 438 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 439 {
 440         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 441                 /* set to reduced bit rate */
 442                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 443                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 444                         dp->link_train.link_rate);
 445                 dp->link_train.lt_state = START;
 446         } else {
 447                 exynos_dp_training_pattern_dis(dp);
 448                 /* set enhanced mode if available */
 449                 exynos_dp_set_enhanced_mode(dp);
 450                 dp->link_train.lt_state = FAILED;
 451         }
 452 }
 453
 454 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 455                                 u8 adjust_request[2])
 456 {
 457         int lane;
 458         int lane_count;
 459         u8 voltage_swing;
 460         u8 pre_emphasis;
 461         u8 training_lane;
 462
 463         lane_count = dp->link_train.lane_count;
 464         for (lane = 0; lane < lane_count; lane++) {
 465                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 466                                                 adjust_request, lane);
 467                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 468                                                 adjust_request, lane);
 469                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 470                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 471
 472                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 473                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 474                         training_lane |= DPCD_MAX_SWING_REACHED;
 475                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 476                 }
 477                 dp->link_train.training_lane[lane] = training_lane;
 478         }
 479 }
 480
 481 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 482                                         u8 voltage_swing)
 483 {
 484         int lane;
 485         int lane_count;
 486
 487         lane_count = dp->link_train.lane_count;
 488         for (lane = 0; lane < lane_count; lane++) {
 489                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 490                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 491                         return -EINVAL;
 492         }
 493         return 0;
 494 }
 495
 496 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 497 {
 498         int ret, lane, lane_count;
 499         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 500         u8 *adjust_request;
 501
 502         udelay(100);
 503
 504         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 505                         link_status);
 506         if (ret)
 507                 return ret;
 508
 509         lane_count = dp->link_train.lane_count;
 510         if (lane_count == 0)
 511                 return 0;
 512
 513         adjust_request = link_status + 4;
 514
 515         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 516                 /* set training pattern 2 for EQ */
 517                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 518
 519                 ret = exynos_dp_write_byte_to_dpcd(dp,
 520                         DPCD_ADDR_TRAINING_PATTERN_SET,
 521                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 522                 if (ret)
 523                         return ret;
 524
 525                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 526         } else {
 527                 for (lane = 0; lane < lane_count; lane++) {
 528                         training_lane = exynos_dp_get_lane_link_training(
 529                                                         dp, lane);
 530                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 531                                                         adjust_request, lane);
 532                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 533                                                         adjust_request, lane);
 534                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 535                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 536                                 dp->link_train.cr_loop[lane]++;
 537                         dp->link_train.training_lane[lane] = training_lane;
 538                 }
 539
 540                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 541                         exynos_dp_reduce_link_rate(dp);
 542                         return ret;
 543                 }
 544         }
 545
 546         exynos_dp_get_adjust_train(dp, adjust_request);
 547
 548         for (lane = 0; lane < lane_count; lane++) {
 549                 exynos_dp_set_lane_link_training(dp,
 550                         dp->link_train.training_lane[lane], lane);
 551                 ret = exynos_dp_write_byte_to_dpcd(dp,
 552                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 553                         dp->link_train.training_lane[lane]);
 554                 if (ret)
 555                         return ret;
 556         }
 557
 558         return ret;
 559 }
 560
 561 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 562 {
 563         int ret, lane, lane_count;
 564         u8 link_status[6];
 565         u32 reg;
 566         u8 *adjust_request;
 567
 568         udelay(400);
 569
 570         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 571                                 6, link_status);
 572         if (ret)
 573                 return ret;
 574
 575         adjust_request = link_status + 4;
 576         lane_count = dp->link_train.lane_count;
 577
 578         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 579                 exynos_dp_reduce_link_rate(dp);
 580                 return ret;
 581         }
 582         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 583                 /* traing pattern Set to Normal */
 584                 exynos_dp_training_pattern_dis(dp);
 585
 586                 dev_info(dp->dev, "Link Training success!\n");
 587
 588                 exynos_dp_get_link_bandwidth(dp, &reg);
 589                 dp->link_train.link_rate = reg;
 590                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 591                         dp->link_train.link_rate);
 592
 593                 exynos_dp_get_lane_count(dp, &reg);
 594                 dp->link_train.lane_count = reg;
 595                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 596                         dp->link_train.lane_count);
 597                 /* set enhanced mode if available */
 598                 exynos_dp_set_enhanced_mode(dp);
 599
 600                 dp->link_train.lt_state = FINISHED;
 601         } else {
 602                 /* not all locked */
 603                 dp->link_train.eq_loop++;
 604
 605                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 606                         exynos_dp_reduce_link_rate(dp);
 607                 } else {
 608                         exynos_dp_get_adjust_train(dp, adjust_request);
 609
 610                         for (lane = 0; lane < lane_count; lane++) {
 611                                 exynos_dp_set_lane_link_training(dp,
 612                                         dp->link_train.training_lane[lane],
 613                                         lane);
 614                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 615                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 616                                         dp->link_train.training_lane[lane]);
 617                                 if (ret)
 618                                         return ret;
 619                         }
 620                 }
 621         }
 622
 623         return ret;
 624 }
 625
 626 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 627                         u8 *bandwidth)
 628 {
 629         u8 data;
 630
 631         /*
 632          * For DP rev.1.1, Maximum link rate of Main Link lanes
 633          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 634          */
 635         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 636         *bandwidth = data;
 637 }
 638
 639 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 640                         u8 *lane_count)
 641 {
 642         u8 data;
 643
 644         /*
 645          * For DP rev.1.1, Maximum number of Main Link lanes
 646          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 647          */
 648         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 649         *lane_count = DPCD_MAX_LANE_COUNT(data);
 650 }
 651
 652 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 653                         enum link_lane_count_type max_lane,
 654                         enum link_rate_type max_rate)
 655 {
 656         /*
 657          * MACRO_RST must be applied after the PLL_LOCK to avoid
 658          * the DP inter pair skew issue for at least 10 us
 659          */
 660         exynos_dp_reset_macro(dp);
 661
 662         /* Initialize by reading RX's DPCD */
 663         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 664         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 665
 666         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 667            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 668                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 669                         dp->link_train.link_rate);
 670                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 671         }
 672
 673         if (dp->link_train.lane_count == 0) {
 674                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 675                         dp->link_train.lane_count);
 676                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 677         }
 678
 679         /* Setup TX lane count & rate */
 680         if (dp->link_train.lane_count > max_lane)
 681                 dp->link_train.lane_count = max_lane;
 682         if (dp->link_train.link_rate > max_rate)
 683                 dp->link_train.link_rate = max_rate;
 684
 685         /* All DP analog module power up */
 686         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 687 }
 688
 689 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 690 {
 691         int ret = 0, training_finished = 0;
 692
 693         /* Turn off unnecessary lanes */
 694         switch (dp->link_train.lane_count) {
 695         case LANE_COUNT1:
 696                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 697         case LANE_COUNT2:
 698                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 699                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 700                 break;
 701         default:
 702                 break;
 703         }
 704
 705         dp->link_train.lt_state = START;
 706
 707         /* Process here */
 708         while (!ret && !training_finished) {
 709                 switch (dp->link_train.lt_state) {
 710                 case START:
 711                         ret = exynos_dp_link_start(dp);
 712                         break;
 713                 case CLOCK_RECOVERY:
 714                         ret = exynos_dp_process_clock_recovery(dp);
 715                         break;
 716                 case EQUALIZER_TRAINING:
 717                         ret = exynos_dp_process_equalizer_training(dp);
 718                         break;
 719                 case FINISHED:
 720                         training_finished = 1;
 721                         break;
 722                 case FAILED:
 723                         return -EREMOTEIO;
 724                 }
 725         }
 726         if (ret)
 727                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 728
 729         return ret;
 730 }
 731
 732 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 733                                 u32 max_lane,
 734                                 u32 max_rate)
 735 {
 736         u32 status;
 737         int ret, lane;
 738
 739         exynos_dp_stop_video(dp);
 740
 741         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 742                 dev_err(dp->dev, "PLL is not locked yet.\n");
 743                 return -EAGAIN;
 744         }
 745
 746         exynos_dp_reset_macro(dp);
 747
 748         /* Set TX pre-emphasis to minimum */
 749         for (lane = 0; lane < max_lane; lane++)
 750                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 751                                 PRE_EMPHASIS_LEVEL_0, lane);
 752
 753         /* All DP analog module power up */
 754         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 755
 756         /* Initialize by reading RX's DPCD */
 757         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 758         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 759
 760         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 761                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 762                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 763                         dp->link_train.link_rate);
 764                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 765         }
 766
 767         if (dp->link_train.lane_count == 0) {
 768                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 769                         dp->link_train.lane_count);
 770                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 771         }
 772
 773         /* Setup TX lane count & rate */
 774         if (dp->link_train.lane_count > max_lane)
 775                 dp->link_train.lane_count = max_lane;
 776         if (dp->link_train.link_rate > max_rate)
 777                 dp->link_train.link_rate = max_rate;
 778
 779         /* Set link rate and count as you want to establish*/
 780         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 781         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 782
 783         /* Set sink to D0 (Sink Not Ready) mode. */
 784         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 785                                                 DPCD_SET_POWER_STATE_D0);
 786
 787         /* Enable H/W Link Training */
 788         ret = exynos_dp_enable_hw_link_training(dp);
 789
 790         if (ret) {
 791                 dev_err(dp->dev, " H/W link training failure: %d\n", ret);
 792                 return ret;
 793         }
 794
 795         exynos_dp_get_link_bandwidth(dp, &status);
 796         dp->link_train.link_rate = status;
 797         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 798                                 dp->link_train.link_rate);
 799
 800         exynos_dp_get_lane_count(dp, &status);
 801         dp->link_train.lane_count = status;
 802         dev_dbg(dp->dev, "final lane count = %.2x\n",
 803                                 dp->link_train.lane_count);
 804
 805         return 0;
 806 }
 807
 808 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 809                                 u32 count,
 810                                 u32 bwtype)
 811 {
 812         int i;
 813         int retval;
 814
 815         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 816                 exynos_dp_init_training(dp, count, bwtype);
 817                 retval = exynos_dp_sw_link_training(dp);
 818                 if (retval == 0)
 819                         break;
 820
 821                 udelay(100);
 822         }
 823
 824         return retval;
 825 }
 826
 827 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 828 {
 829         int retval = 0;
 830         int timeout_loop = 0;
 831
 832         exynos_dp_config_video_slave_mode(dp);
 833
 834         exynos_dp_set_video_color_format(dp);
 835
 836         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 837                 dev_err(dp->dev, "PLL is not locked yet.\n");
 838                 return -EINVAL;
 839         }
 840
 841         for (;;) {
 842                 timeout_loop++;
 843                 if (!exynos_dp_is_slave_video_stream_clock_on(dp))
 844                         break;
 845                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 846                         dev_err(dp->dev, "Wait for stream clock timed out\n");
 847                         return -ETIMEDOUT;
 848                 }
 849
 850                 usleep_range(1000, 5000);
 851         }
 852
 853         /* Set to use the register calculated M/N video */
 854         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 855
 856         /* For video bist, Video timing must be generated by register */
 857         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 858
 859         /* Disable video mute */
 860         exynos_dp_enable_video_mute(dp, 0);
 861
 862         /* Configure video slave mode */
 863         exynos_dp_enable_video_master(dp, 0);
 864
 865         /* Enable video */
 866         exynos_dp_start_video(dp);
 867
 868         timeout_loop = 0;
 869
 870         for (;;) {
 871                 timeout_loop++;
 872                 if (!exynos_dp_is_video_stream_on(dp))
 873                         break;
 874
 875                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 876                         dev_err(dp->dev, "Wait for video stream timed out\n");
 877                         return -ETIMEDOUT;
 878                 }
 879
 880                 usleep_range(1000, 5000);
 881         }
 882
 883         if (retval != 0)
 884                 dev_err(dp->dev, "Video stream is not detected!\n");
 885
 886         return retval;
 887 }
 888
 889 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 890 {
 891         u8 data;
 892
 893         if (enable) {
 894                 exynos_dp_enable_scrambling(dp);
 895
 896                 exynos_dp_read_byte_from_dpcd(dp,
 897                         DPCD_ADDR_TRAINING_PATTERN_SET,
 898                         &data);
 899                 exynos_dp_write_byte_to_dpcd(dp,
 900                         DPCD_ADDR_TRAINING_PATTERN_SET,
 901                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 902         } else {
 903                 exynos_dp_disable_scrambling(dp);
 904
 905                 exynos_dp_read_byte_from_dpcd(dp,
 906                         DPCD_ADDR_TRAINING_PATTERN_SET,
 907                         &data);
 908                 exynos_dp_write_byte_to_dpcd(dp,
 909                         DPCD_ADDR_TRAINING_PATTERN_SET,
 910                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 911         }
 912 }
 913
 914 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 915 {
 916         struct exynos_dp_device *dp = arg;
 917         enum dp_irq_type irq_type;
 918
 919         irq_type = exynos_dp_get_irq_type(dp);
 920         switch (irq_type) {
 921         case DP_IRQ_TYPE_HP_CABLE_IN:
 922         case DP_IRQ_TYPE_HP_CABLE_OUT:
 923                 dev_dbg(dp->dev, "Received irq - type=%d\n", irq_type);
 924                 schedule_work(&dp->hotplug_work);
 925                 exynos_dp_clear_hotplug_interrupts(dp);
 926                 break;
 927         case DP_IRQ_TYPE_HP_CHANGE:
 928                 /*
 929                  * We get these change notifications once in a while, but there
 930                  * is nothing we can do with them. Just ignore it for now and
 931                  * only handle cable changes.
 932                  */
 933                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 934                 exynos_dp_clear_hotplug_interrupts(dp);
 935                 break;
 936         default:
 937                 dev_err(dp->dev, "Received irq - unknown type!\n");
 938                 break;
 939         }
 940         return IRQ_HANDLED;
 941 }
 942
 943 static void exynos_dp_hotplug(struct work_struct *work)
 944 {
 945         struct exynos_dp_device *dp;
 946         int ret;
 947
 948         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 949
 950         /* Cable is disconnected, skip dp initialization */
 951         if (exynos_dp_detect_hpd(dp))
 952                 goto out;
 953
 954 #ifdef CONFIG_DRM_PTN3460
 955         ret = ptn3460_wait_until_ready(30 * 1000);
 956         if (ret) {
 957                 DRM_ERROR("PTN3460 is not ready, don't plug\n");
 958                 return;
 959         }
 960 #endif
 961
 962         ret = exynos_dp_handle_edid(dp);
 963         if (ret) {
 964                 dev_err(dp->dev, "unable to handle edid\n");
 965                 return;
 966         }
 967
 968         if (dp->training_type == SW_LINK_TRAINING)
 969                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 970                         dp->video_info->link_rate);
 971         else
 972                 ret = exynos_dp_set_hw_link_train(dp,
 973                         dp->video_info->lane_count, dp->video_info->link_rate);
 974         if (ret) {
 975                 dev_err(dp->dev, "unable to do link train\n");
 976                 return;
 977         }
 978
 979         exynos_dp_enable_scramble(dp, 1);
 980         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 981         exynos_dp_enable_enhanced_mode(dp, 1);
 982
 983         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 984         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 985
 986         exynos_dp_init_video(dp);
 987         exynos_dp_config_video(dp);
 988
 989 out:
 990         drm_helper_hpd_irq_event(dp->drm_dev);
 991 }
 992
 993 static int exynos_dp_power_off(struct exynos_dp_device *dp)
 994 {
 995         exynos_dp_disable_hpd(dp);
 996
 997         if (work_pending(&dp->hotplug_work))
 998                 flush_work_sync(&dp->hotplug_work);
 999
1000         if (dp->phy_ops.phy_exit)
1001                 dp->phy_ops.phy_exit();
1002
1003         clk_disable(dp->clock);
1004         return 0;
1005 }
1006
1007 static int exynos_dp_power_on(struct exynos_dp_device *dp)
1008 {
1009         if (dp->phy_ops.phy_init)
1010                 dp->phy_ops.phy_init();
1011
1012         clk_enable(dp->clock);
1013
1014         exynos_dp_init_dp(dp);
1015
1016         /*
1017          * DP controller is reset and needs HPD interrupt to trigger
1018          * re-configuration. If we don't have valid IRQ, this is never
1019          * going to happen. Let's reconfigure it here in this case.
1020          */
1021         if (dp->irq < 0 && !exynos_dp_detect_hpd(dp))
1022                 schedule_work(&dp->hotplug_work);
1023
1024         return 0;
1025 }
1026
1027 static int exynos_dp_power(void *ctx, int mode)
1028 {
1029         struct exynos_dp_device *dp = ctx;
1030
1031         switch (mode) {
1032         case DRM_MODE_DPMS_ON:
1033                 return exynos_dp_power_on(dp);
1034
1035         case DRM_MODE_DPMS_STANDBY:
1036         case DRM_MODE_DPMS_SUSPEND:
1037         case DRM_MODE_DPMS_OFF:
1038                 return exynos_dp_power_off(dp);
1039
1040         default:
1041                 DRM_ERROR("Unknown dpms mode %d\n", mode);
1042         }
1043         return -EINVAL;
1044 }
1045
1046 static int exynos_dp_check_timing(void *ctx, void *timing)
1047 {
1048         /*
1049          * TODO(seanpaul): The datasheet isn't terribly descriptive about the
1050          * limitations we have here. It's not vitally important to implement
1051          * this right now, but should be implemented once we use EDID to mode
1052          * set.
1053          */
1054         return 0;
1055 }
1056
1057 static bool exynos_dp_is_connected(void *ctx)
1058 {
1059         struct exynos_dp_device *dp = ctx;
1060         int ret;
1061
1062         ret = exynos_dp_detect_hpd(dp);
1063         return !ret;
1064 }
1065
1066 static int exynos_dp_subdrv_probe(void *ctx, struct drm_device *drm_dev)
1067 {
1068         struct exynos_dp_device *dp = ctx;
1069
1070         dp->drm_dev = drm_dev;
1071
1072         exynos_dp_power(dp, DRM_MODE_DPMS_ON);
1073
1074         return 0;
1075 }
1076
1077 static struct exynos_panel_ops dp_panel_ops = {
1078         .subdrv_probe = exynos_dp_subdrv_probe,
1079         .is_connected = exynos_dp_is_connected,
1080         .check_timing = exynos_dp_check_timing,
1081         .power = exynos_dp_power,
1082 };
1083
1084 static int __devinit exynos_dp_probe(struct platform_device *pdev)
1085 {
1086         struct resource *res;
1087         struct exynos_dp_device *dp;
1088         struct exynos_dp_platdata *pdata;
1089
1090         int ret = 0;
1091         int irqflags;
1092
1093         pdata = pdev->dev.platform_data;
1094         if (!pdata) {
1095                 dev_err(&pdev->dev, "no platform data\n");
1096                 return -EINVAL;
1097         }
1098
1099         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
1100         if (!dp) {
1101                 dev_err(&pdev->dev, "no memory for device data\n");
1102                 return -ENOMEM;
1103         }
1104
1105         dp->dev = &pdev->dev;
1106
1107         dp->clock = clk_get(&pdev->dev, "dp");
1108         if (IS_ERR(dp->clock)) {
1109                 dev_err(&pdev->dev, "failed to get clock\n");
1110                 ret = PTR_ERR(dp->clock);
1111                 goto err_dp;
1112         }
1113
1114         clk_enable(dp->clock);
1115
1116         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1117         if (!res) {
1118                 dev_err(&pdev->dev, "failed to get registers\n");
1119                 ret = -EINVAL;
1120                 goto err_clock;
1121         }
1122
1123         res = request_mem_region(res->start, resource_size(res),
1124                                 dev_name(&pdev->dev));
1125         if (!res) {
1126                 dev_err(&pdev->dev, "failed to request registers region\n");
1127                 ret = -EINVAL;
1128                 goto err_clock;
1129         }
1130
1131         dp->res = res;
1132
1133         dp->reg_base = ioremap(res->start, resource_size(res));
1134         if (!dp->reg_base) {
1135                 dev_err(&pdev->dev, "failed to ioremap\n");
1136                 ret = -ENOMEM;
1137                 goto err_req_region;
1138         }
1139
1140         if (gpio_is_valid(pdata->hpd_gpio)) {
1141                 dp->hpd_gpio = pdata->hpd_gpio;
1142                 ret = gpio_request_one(dp->hpd_gpio, GPIOF_IN, "dp_hpd");
1143                 if (ret)
1144                         goto err_ioremap;
1145                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1146                 irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1147         } else {
1148                 dp->hpd_gpio = -ENODEV;
1149                 dp->irq = platform_get_irq(pdev, 0);
1150                 irqflags = 0;
1151         }
1152
1153         dp->training_type = pdata->training_type;
1154         dp->video_info = pdata->video_info;
1155         if (pdata->phy_init) {
1156                 dp->phy_ops.phy_init = pdata->phy_init;
1157                 dp->phy_ops.phy_init();
1158         }
1159         if (pdata->phy_exit)
1160                 dp->phy_ops.phy_exit = pdata->phy_exit;
1161
1162         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1163
1164         if (dp->irq >= 0) {
1165                 ret = request_irq(dp->irq, exynos_dp_irq_handler, irqflags,
1166                                 "exynos-dp", dp);
1167                 if (ret) {
1168                         dev_err(&pdev->dev, "failed to request irq\n");
1169                         goto err_gpio;
1170                 }
1171         }
1172
1173         platform_set_drvdata(pdev, dp);
1174
1175         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_FIMD, &dp_panel_ops,
1176                         dp);
1177
1178         return 0;
1179
1180 err_gpio:
1181         if (gpio_is_valid(dp->hpd_gpio))
1182                 gpio_free(dp->hpd_gpio);
1183 err_ioremap:
1184         iounmap(dp->reg_base);
1185 err_req_region:
1186         release_mem_region(res->start, resource_size(res));
1187 err_clock:
1188         clk_put(dp->clock);
1189 err_dp:
1190         kfree(dp);
1191
1192         return ret;
1193 }
1194
1195 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1196 {
1197         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1198
1199         /* power_off will take care of flushing the hotplug_work */
1200         exynos_dp_power(dp, DRM_MODE_DPMS_OFF);
1201
1202         if (gpio_is_valid(dp->hpd_gpio))
1203                 gpio_free(dp->hpd_gpio);
1204
1205         free_irq(dp->irq, dp);
1206         iounmap(dp->reg_base);
1207
1208         clk_disable(dp->clock);
1209         clk_put(dp->clock);
1210
1211         release_mem_region(dp->res->start, resource_size(dp->res));
1212
1213         kfree(dp);
1214
1215         return 0;
1216 }
1217
1218 struct platform_driver dp_driver = {
1219         .probe          = exynos_dp_probe,
1220         .remove         = __devexit_p(exynos_dp_remove),
1221         .driver         = {
1222                 .name   = "s5p-dp",
1223                 .owner  = THIS_MODULE,
1224         },
1225 };