drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/io.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/delay.h>
  22 #include <linux/of.h>
  23 #include <linux/workqueue.h>
  24
  25 #include <video/exynos_dp.h>
  26 #include "exynos_drm_drv.h"
  27
  28 #include <plat/cpu.h>
  29
  30 #include "exynos_dp_core.h"
  31
  32 #define PLL_MAX_TRIES 100
  33
  34 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  35 {
  36         exynos_dp_reset(dp);
  37
  38         /* SW defined function Normal operation */
  39         exynos_dp_enable_sw_function(dp);
  40
  41         exynos_dp_init_analog_func(dp);
  42
  43         exynos_dp_init_hpd(dp);
  44         exynos_dp_init_aux(dp);
  45
  46         return 0;
  47 }
  48
  49 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  50 {
  51         int timeout_loop = 0;
  52
  53         while (exynos_dp_get_plug_in_status(dp) != 0) {
  54                 timeout_loop++;
  55                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  56                         dev_err(dp->dev, "failed to get hpd plug status\n");
  57                         return -ETIMEDOUT;
  58                 }
  59                 udelay(10);
  60         }
  61
  62         return 0;
  63 }
  64
  65 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  66 {
  67         int i;
  68         unsigned char sum = 0;
  69
  70         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  71                 sum = sum + edid_data[i];
  72
  73         return sum;
  74 }
  75
  76 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  77 {
  78         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  79         unsigned int extend_block = 0;
  80         unsigned char sum;
  81         unsigned char test_vector;
  82         int retval;
  83
  84         /*
  85          * EDID device address is 0x50.
  86          * However, if necessary, you must have set upper address
  87          * into E-EDID in I2C device, 0x30.
  88          */
  89
  90         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  91         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  92                                 EDID_EXTENSION_FLAG,
  93                                 &extend_block);
  94         if (retval)
  95                 return retval;
  96
  97         if (extend_block > 0) {
  98                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
  99
 100                 /* Read EDID data */
 101                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 102                                                 EDID_HEADER_PATTERN,
 103                                                 EDID_BLOCK_LENGTH,
 104                                                 &edid[EDID_HEADER_PATTERN]);
 105                 if (retval != 0) {
 106                         dev_err(dp->dev, "EDID Read failed!\n");
 107                         return -EIO;
 108                 }
 109                 sum = exynos_dp_calc_edid_check_sum(edid);
 110                 if (sum != 0) {
 111                         dev_err(dp->dev, "EDID bad checksum!\n");
 112                         return -EIO;
 113                 }
 114
 115                 /* Read additional EDID data */
 116                 retval = exynos_dp_read_bytes_from_i2c(dp,
 117                                 I2C_EDID_DEVICE_ADDR,
 118                                 EDID_BLOCK_LENGTH,
 119                                 EDID_BLOCK_LENGTH,
 120                                 &edid[EDID_BLOCK_LENGTH]);
 121                 if (retval != 0) {
 122                         dev_err(dp->dev, "EDID Read failed!\n");
 123                         return -EIO;
 124                 }
 125                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 126                 if (sum != 0) {
 127                         dev_err(dp->dev, "EDID bad checksum!\n");
 128                         return -EIO;
 129                 }
 130
 131                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 132                                         &test_vector);
 133                 if (test_vector & DPCD_TEST_EDID_READ) {
 134                         exynos_dp_write_byte_to_dpcd(dp,
 135                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 136                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 137                         exynos_dp_write_byte_to_dpcd(dp,
 138                                 DPCD_ADDR_TEST_RESPONSE,
 139                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 140                 }
 141         } else {
 142                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 143
 144                 /* Read EDID data */
 145                 retval = exynos_dp_read_bytes_from_i2c(dp,
 146                                 I2C_EDID_DEVICE_ADDR,
 147                                 EDID_HEADER_PATTERN,
 148                                 EDID_BLOCK_LENGTH,
 149                                 &edid[EDID_HEADER_PATTERN]);
 150                 if (retval != 0) {
 151                         dev_err(dp->dev, "EDID Read failed!\n");
 152                         return -EIO;
 153                 }
 154                 sum = exynos_dp_calc_edid_check_sum(edid);
 155                 if (sum != 0) {
 156                         dev_err(dp->dev, "EDID bad checksum!\n");
 157                         return -EIO;
 158                 }
 159
 160                 exynos_dp_read_byte_from_dpcd(dp,
 161                         DPCD_ADDR_TEST_REQUEST,
 162                         &test_vector);
 163                 if (test_vector & DPCD_TEST_EDID_READ) {
 164                         exynos_dp_write_byte_to_dpcd(dp,
 165                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 166                                 edid[EDID_CHECKSUM]);
 167                         exynos_dp_write_byte_to_dpcd(dp,
 168                                 DPCD_ADDR_TEST_RESPONSE,
 169                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 170                 }
 171         }
 172
 173         dev_err(dp->dev, "EDID Read success!\n");
 174         return 0;
 175 }
 176
 177 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 178 {
 179         u8 buf[12];
 180         int i;
 181         int ret;
 182
 183         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 184         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, 12, buf);
 185         if (ret)
 186                 return ret;
 187
 188         /* Read EDID */
 189         for (i = 0; i < 3; i++) {
 190                 ret = exynos_dp_read_edid(dp);
 191                 if (!ret)
 192                         break;
 193         }
 194
 195         return ret;
 196 }
 197
 198 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 199                                                 bool enable)
 200 {
 201         u8 data;
 202
 203         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 204
 205         if (enable)
 206                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 207                         DPCD_ENHANCED_FRAME_EN |
 208                         DPCD_LANE_COUNT_SET(data));
 209         else
 210                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 211                         DPCD_LANE_COUNT_SET(data));
 212 }
 213
 214 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 215 {
 216         u8 data;
 217         int retval;
 218
 219         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 220         retval = DPCD_ENHANCED_FRAME_CAP(data);
 221
 222         return retval;
 223 }
 224
 225 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 226 {
 227         u8 data;
 228
 229         data = exynos_dp_is_enhanced_mode_available(dp);
 230         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 231         exynos_dp_enable_enhanced_mode(dp, data);
 232 }
 233
 234 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 235 {
 236         exynos_dp_set_training_pattern(dp, DP_NONE);
 237
 238         exynos_dp_write_byte_to_dpcd(dp,
 239                 DPCD_ADDR_TRAINING_PATTERN_SET,
 240                 DPCD_TRAINING_PATTERN_DISABLED);
 241 }
 242
 243 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 244                                         int pre_emphasis, int lane)
 245 {
 246         switch (lane) {
 247         case 0:
 248                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 249                 break;
 250         case 1:
 251                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 252                 break;
 253
 254         case 2:
 255                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 256                 break;
 257
 258         case 3:
 259                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 260                 break;
 261         }
 262 }
 263
 264 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 265 {
 266         int ret, lane, lane_count, pll_tries;
 267         u8 buf[4];
 268
 269         lane_count = dp->link_train.lane_count;
 270
 271         dp->link_train.lt_state = CLOCK_RECOVERY;
 272         dp->link_train.eq_loop = 0;
 273
 274         for (lane = 0; lane < lane_count; lane++)
 275                 dp->link_train.cr_loop[lane] = 0;
 276
 277         /* Set link rate and count as you want to establish*/
 278         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 279         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 280
 281         /* Setup RX configuration */
 282         buf[0] = dp->link_train.link_rate;
 283         buf[1] = dp->link_train.lane_count;
 284         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 285         if (ret)
 286                 return ret;
 287
 288         /* Set TX pre-emphasis to minimum */
 289         for (lane = 0; lane < lane_count; lane++)
 290                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 291                         PRE_EMPHASIS_LEVEL_0, lane);
 292
 293         /* Wait for PLL lock */
 294         pll_tries = 0;
 295         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 296                 if (pll_tries == PLL_MAX_TRIES)
 297                         return -ETIMEDOUT;
 298
 299                 pll_tries++;
 300                 udelay(100);
 301         }
 302
 303         /* Set training pattern 1 */
 304         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 305
 306         /* Set RX training pattern */
 307         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 308                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 309         if (ret)
 310                 return ret;
 311
 312         for (lane = 0; lane < lane_count; lane++)
 313                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 314                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 315         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 316                 lane_count, buf);
 317         if (ret)
 318                 return ret;
 319
 320         return ret;
 321 }
 322
 323 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 324 {
 325         int shift = (lane & 1) * 4;
 326         u8 link_value = link_status[lane>>1];
 327
 328         return (link_value >> shift) & 0xf;
 329 }
 330
 331 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 332 {
 333         int lane;
 334         u8 lane_status;
 335
 336         for (lane = 0; lane < lane_count; lane++) {
 337                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 338                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 339                         return -EINVAL;
 340         }
 341         return 0;
 342 }
 343
 344 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 345 {
 346         int lane;
 347         u8 lane_align;
 348         u8 lane_status;
 349
 350         lane_align = link_status[2];
 351         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 352                 return -EINVAL;
 353
 354         for (lane = 0; lane < lane_count; lane++) {
 355                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 356                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 357                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 358                         return -EINVAL;
 359         }
 360         return 0;
 361 }
 362
 363 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 364                                                         int lane)
 365 {
 366         int shift = (lane & 1) * 4;
 367         u8 link_value = adjust_request[lane>>1];
 368
 369         return (link_value >> shift) & 0x3;
 370 }
 371
 372 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 373                                         u8 adjust_request[2],
 374                                         int lane)
 375 {
 376         int shift = (lane & 1) * 4;
 377         u8 link_value = adjust_request[lane>>1];
 378
 379         return ((link_value >> shift) & 0xc) >> 2;
 380 }
 381
 382 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 383                                         u8 training_lane_set, int lane)
 384 {
 385         switch (lane) {
 386         case 0:
 387                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 388                 break;
 389         case 1:
 390                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 391                 break;
 392
 393         case 2:
 394                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 395                 break;
 396
 397         case 3:
 398                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 399                 break;
 400         }
 401 }
 402
 403 static unsigned int exynos_dp_get_lane_link_training(
 404                                 struct exynos_dp_device *dp,
 405                                 int lane)
 406 {
 407         u32 reg = 0;
 408
 409         switch (lane) {
 410         case 0:
 411                 reg = exynos_dp_get_lane0_link_training(dp);
 412                 break;
 413         case 1:
 414                 reg = exynos_dp_get_lane1_link_training(dp);
 415                 break;
 416         case 2:
 417                 reg = exynos_dp_get_lane2_link_training(dp);
 418                 break;
 419         case 3:
 420                 reg = exynos_dp_get_lane3_link_training(dp);
 421                 break;
 422         }
 423
 424         return reg;
 425 }
 426
 427 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 428 {
 429         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 430                 /* set to reduced bit rate */
 431                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 432                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 433                         dp->link_train.link_rate);
 434                 dp->link_train.lt_state = START;
 435         } else {
 436                 exynos_dp_training_pattern_dis(dp);
 437                 /* set enhanced mode if available */
 438                 exynos_dp_set_enhanced_mode(dp);
 439                 dp->link_train.lt_state = FAILED;
 440         }
 441 }
 442
 443 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 444                                 u8 adjust_request[2])
 445 {
 446         int lane;
 447         int lane_count;
 448         u8 voltage_swing;
 449         u8 pre_emphasis;
 450         u8 training_lane;
 451
 452         lane_count = dp->link_train.lane_count;
 453         for (lane = 0; lane < lane_count; lane++) {
 454                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 455                                                 adjust_request, lane);
 456                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 457                                                 adjust_request, lane);
 458                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 459                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 460
 461                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 462                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 463                         training_lane |= DPCD_MAX_SWING_REACHED;
 464                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 465                 }
 466                 dp->link_train.training_lane[lane] = training_lane;
 467         }
 468 }
 469
 470 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 471                                         u8 voltage_swing)
 472 {
 473         int lane;
 474         int lane_count;
 475
 476         lane_count = dp->link_train.lane_count;
 477         for (lane = 0; lane < lane_count; lane++) {
 478                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 479                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 480                         return -EINVAL;
 481         }
 482         return 0;
 483 }
 484
 485 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 486 {
 487         int ret, lane, lane_count;
 488         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 489         u8 *adjust_request;
 490
 491         udelay(100);
 492
 493         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 494                         link_status);
 495         if (ret)
 496                 return ret;
 497
 498         lane_count = dp->link_train.lane_count;
 499         adjust_request = link_status + 4;
 500
 501         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 502                 /* set training pattern 2 for EQ */
 503                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 504
 505                 ret = exynos_dp_write_byte_to_dpcd(dp,
 506                         DPCD_ADDR_TRAINING_PATTERN_SET,
 507                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 508                 if (ret)
 509                         return ret;
 510
 511                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 512         } else {
 513                 for (lane = 0; lane < lane_count; lane++) {
 514                         training_lane = exynos_dp_get_lane_link_training(
 515                                                         dp, lane);
 516                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 517                                                         adjust_request, lane);
 518                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 519                                                         adjust_request, lane);
 520                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 521                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 522                                 dp->link_train.cr_loop[lane]++;
 523                         dp->link_train.training_lane[lane] = training_lane;
 524                 }
 525
 526                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 527                         exynos_dp_reduce_link_rate(dp);
 528                         return ret;
 529                 }
 530         }
 531
 532         exynos_dp_get_adjust_train(dp, adjust_request);
 533
 534         for (lane = 0; lane < lane_count; lane++) {
 535                 exynos_dp_set_lane_link_training(dp,
 536                         dp->link_train.training_lane[lane], lane);
 537                 ret = exynos_dp_write_byte_to_dpcd(dp,
 538                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 539                         dp->link_train.training_lane[lane]);
 540                 if (ret)
 541                         return ret;
 542         }
 543
 544         return ret;
 545 }
 546
 547 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 548 {
 549         int ret, lane, lane_count;
 550         u8 link_status[6];
 551         u32 reg;
 552         u8 *adjust_request;
 553
 554         udelay(400);
 555
 556         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 557                                 6, link_status);
 558         if (ret)
 559                 return ret;
 560
 561         adjust_request = link_status + 4;
 562         lane_count = dp->link_train.lane_count;
 563
 564         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 565                 exynos_dp_reduce_link_rate(dp);
 566                 return ret;
 567         }
 568         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 569                 /* traing pattern Set to Normal */
 570                 exynos_dp_training_pattern_dis(dp);
 571
 572                 dev_info(dp->dev, "Link Training success!\n");
 573
 574                 exynos_dp_get_link_bandwidth(dp, &reg);
 575                 dp->link_train.link_rate = reg;
 576                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 577                         dp->link_train.link_rate);
 578
 579                 exynos_dp_get_lane_count(dp, &reg);
 580                 dp->link_train.lane_count = reg;
 581                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 582                         dp->link_train.lane_count);
 583                 /* set enhanced mode if available */
 584                 exynos_dp_set_enhanced_mode(dp);
 585
 586                 dp->link_train.lt_state = FINISHED;
 587         } else {
 588                 /* not all locked */
 589                 dp->link_train.eq_loop++;
 590
 591                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 592                         exynos_dp_reduce_link_rate(dp);
 593                 } else {
 594                         exynos_dp_get_adjust_train(dp, adjust_request);
 595
 596                         for (lane = 0; lane < lane_count; lane++) {
 597                                 exynos_dp_set_lane_link_training(dp,
 598                                         dp->link_train.training_lane[lane],
 599                                         lane);
 600                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 601                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 602                                         dp->link_train.training_lane[lane]);
 603                                 if (ret)
 604                                         return ret;
 605                         }
 606                 }
 607         }
 608
 609         return ret;
 610 }
 611
 612 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 613                         u8 *bandwidth)
 614 {
 615         u8 data;
 616
 617         /*
 618          * For DP rev.1.1, Maximum link rate of Main Link lanes
 619          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 620          */
 621         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 622         *bandwidth = data;
 623 }
 624
 625 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 626                         u8 *lane_count)
 627 {
 628         u8 data;
 629
 630         /*
 631          * For DP rev.1.1, Maximum number of Main Link lanes
 632          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 633          */
 634         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 635         *lane_count = DPCD_MAX_LANE_COUNT(data);
 636 }
 637
 638 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 639                         enum link_lane_count_type max_lane,
 640                         enum link_rate_type max_rate)
 641 {
 642         /*
 643          * MACRO_RST must be applied after the PLL_LOCK to avoid
 644          * the DP inter pair skew issue for at least 10 us
 645          */
 646         exynos_dp_reset_macro(dp);
 647
 648         /* Initialize by reading RX's DPCD */
 649         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 650         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 651
 652         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 653            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 654                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 655                         dp->link_train.link_rate);
 656                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 657         }
 658
 659         if (dp->link_train.lane_count == 0) {
 660                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 661                         dp->link_train.lane_count);
 662                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 663         }
 664
 665         /* Setup TX lane count & rate */
 666         if (dp->link_train.lane_count > max_lane)
 667                 dp->link_train.lane_count = max_lane;
 668         if (dp->link_train.link_rate > max_rate)
 669                 dp->link_train.link_rate = max_rate;
 670
 671         /* All DP analog module power up */
 672         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 673 }
 674
 675 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 676 {
 677         int ret = 0, training_finished = 0;
 678
 679         /* Turn off unnecessary lanes */
 680         switch (dp->link_train.lane_count) {
 681         case LANE_COUNT1:
 682                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 683         case LANE_COUNT2:
 684                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 685                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 686                 break;
 687         default:
 688                 break;
 689         }
 690
 691         dp->link_train.lt_state = START;
 692
 693         /* Process here */
 694         while (!ret && !training_finished) {
 695                 switch (dp->link_train.lt_state) {
 696                 case START:
 697                         ret = exynos_dp_link_start(dp);
 698                         break;
 699                 case CLOCK_RECOVERY:
 700                         ret = exynos_dp_process_clock_recovery(dp);
 701                         break;
 702                 case EQUALIZER_TRAINING:
 703                         ret = exynos_dp_process_equalizer_training(dp);
 704                         break;
 705                 case FINISHED:
 706                         training_finished = 1;
 707                         break;
 708                 case FAILED:
 709                         return -EREMOTEIO;
 710                 }
 711         }
 712         if (ret)
 713                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 714
 715         return ret;
 716 }
 717
 718 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 719                                 u32 max_lane,
 720                                 u32 max_rate)
 721 {
 722         u32 status;
 723         int ret, lane;
 724
 725         exynos_dp_stop_video(dp);
 726
 727         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 728                 dev_err(dp->dev, "PLL is not locked yet.\n");
 729                 return -EAGAIN;
 730         }
 731
 732         exynos_dp_reset_macro(dp);
 733
 734         /* Set TX pre-emphasis to minimum */
 735         for (lane = 0; lane < max_lane; lane++)
 736                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 737                                 PRE_EMPHASIS_LEVEL_0, lane);
 738
 739         /* All DP analog module power up */
 740         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 741
 742         /* Initialize by reading RX's DPCD */
 743         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 744         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 745
 746         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 747                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 748                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 749                         dp->link_train.link_rate);
 750                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 751         }
 752
 753         if (dp->link_train.lane_count == 0) {
 754                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 755                         dp->link_train.lane_count);
 756                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 757         }
 758
 759         /* Setup TX lane count & rate */
 760         if (dp->link_train.lane_count > max_lane)
 761                 dp->link_train.lane_count = max_lane;
 762         if (dp->link_train.link_rate > max_rate)
 763                 dp->link_train.link_rate = max_rate;
 764
 765         /* Set link rate and count as you want to establish*/
 766         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 767         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 768
 769         /* Set sink to D0 (Sink Not Ready) mode. */
 770         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 771                                                 DPCD_SET_POWER_STATE_D0);
 772
 773         /* Enable H/W Link Training */
 774         ret = exynos_dp_enable_hw_link_training(dp);
 775
 776         if (ret) {
 777                 dev_err(dp->dev, " H/W link training failure: %d\n", ret);
 778                 return ret;
 779         }
 780
 781         exynos_dp_get_link_bandwidth(dp, &status);
 782         dp->link_train.link_rate = status;
 783         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 784                                 dp->link_train.link_rate);
 785
 786         exynos_dp_get_lane_count(dp, &status);
 787         dp->link_train.lane_count = status;
 788         dev_dbg(dp->dev, "final lane count = %.2x\n",
 789                                 dp->link_train.lane_count);
 790
 791         return 0;
 792 }
 793
 794 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 795                                 u32 count,
 796                                 u32 bwtype)
 797 {
 798         int i;
 799         int retval;
 800
 801         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 802                 exynos_dp_init_training(dp, count, bwtype);
 803                 retval = exynos_dp_sw_link_training(dp);
 804                 if (retval == 0)
 805                         break;
 806
 807                 udelay(100);
 808         }
 809
 810         return retval;
 811 }
 812
 813 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 814 {
 815         int retval = 0;
 816         int timeout_loop = 0;
 817         int done_count = 0;
 818
 819         exynos_dp_config_video_slave_mode(dp);
 820
 821         exynos_dp_set_video_color_format(dp);
 822
 823         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 824                 dev_err(dp->dev, "PLL is not locked yet.\n");
 825                 return -EINVAL;
 826         }
 827
 828         for (;;) {
 829                 timeout_loop++;
 830                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 831                         break;
 832                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 833                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 834                         return -ETIMEDOUT;
 835                 }
 836
 837                 msleep(100);
 838         }
 839
 840         /* Set to use the register calculated M/N video */
 841         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 842
 843         /* For video bist, Video timing must be generated by register */
 844         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 845
 846         /* Disable video mute */
 847         exynos_dp_enable_video_mute(dp, 0);
 848
 849         /* Configure video slave mode */
 850         exynos_dp_enable_video_master(dp, 0);
 851
 852         /* Enable video */
 853         exynos_dp_start_video(dp);
 854
 855         timeout_loop = 0;
 856
 857         for (;;) {
 858                 timeout_loop++;
 859                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 860                         done_count++;
 861                         if (done_count > 10)
 862                                 break;
 863                 } else if (done_count) {
 864                         done_count = 0;
 865                 }
 866                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 867                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 868                         return -ETIMEDOUT;
 869                 }
 870
 871                 msleep(100);
 872         }
 873
 874         if (retval != 0)
 875                 dev_err(dp->dev, "Video stream is not detected!\n");
 876
 877         return retval;
 878 }
 879
 880 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 881 {
 882         u8 data;
 883
 884         if (enable) {
 885                 exynos_dp_enable_scrambling(dp);
 886
 887                 exynos_dp_read_byte_from_dpcd(dp,
 888                         DPCD_ADDR_TRAINING_PATTERN_SET,
 889                         &data);
 890                 exynos_dp_write_byte_to_dpcd(dp,
 891                         DPCD_ADDR_TRAINING_PATTERN_SET,
 892                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 893         } else {
 894                 exynos_dp_disable_scrambling(dp);
 895
 896                 exynos_dp_read_byte_from_dpcd(dp,
 897                         DPCD_ADDR_TRAINING_PATTERN_SET,
 898                         &data);
 899                 exynos_dp_write_byte_to_dpcd(dp,
 900                         DPCD_ADDR_TRAINING_PATTERN_SET,
 901                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 902         }
 903 }
 904
 905 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 906 {
 907         struct exynos_dp_device *dp = arg;
 908         enum dp_irq_type irq_type;
 909
 910         irq_type = exynos_dp_get_irq_type(dp);
 911         switch (irq_type) {
 912         case DP_IRQ_TYPE_HP_CABLE_IN:
 913                 dev_dbg(dp->dev, "Received irq - cable in\n");
 914                 schedule_work(&dp->hotplug_work);
 915                 exynos_dp_clear_hotplug_interrupts(dp);
 916                 break;
 917         case DP_IRQ_TYPE_HP_CABLE_OUT:
 918                 dev_dbg(dp->dev, "Received irq - cable out\n");
 919                 exynos_dp_clear_hotplug_interrupts(dp);
 920                 break;
 921         case DP_IRQ_TYPE_HP_CHANGE:
 922                 /*
 923                  * We get these change notifications once in a while, but there
 924                  * is nothing we can do with them. Just ignore it for now and
 925                  * only handle cable changes.
 926                  */
 927                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 928                 exynos_dp_clear_hotplug_interrupts(dp);
 929                 break;
 930         default:
 931                 dev_err(dp->dev, "Received irq - unknown type!\n");
 932                 break;
 933         }
 934         return IRQ_HANDLED;
 935 }
 936
 937 static void exynos_dp_hotplug(struct work_struct *work)
 938 {
 939         struct exynos_dp_device *dp;
 940         int ret;
 941
 942         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 943
 944         ret = exynos_dp_detect_hpd(dp);
 945         if (ret) {
 946                 /* Cable has been disconnected, we're done */
 947                 return;
 948         }
 949
 950         ret = exynos_dp_handle_edid(dp);
 951         if (ret) {
 952                 dev_err(dp->dev, "unable to handle edid\n");
 953                 return;
 954         }
 955
 956         if (dp->training_type == SW_LINK_TRAINING)
 957                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 958                                                 dp->video_info->link_rate);
 959         else
 960                 ret = exynos_dp_set_hw_link_train(dp,
 961                         dp->video_info->lane_count, dp->video_info->link_rate);
 962         if (ret) {
 963                 dev_err(dp->dev, "unable to do link train\n");
 964                 return;
 965         }
 966
 967         exynos_dp_enable_scramble(dp, 1);
 968         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 969         exynos_dp_enable_enhanced_mode(dp, 1);
 970
 971         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 972         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 973
 974         exynos_dp_init_video(dp);
 975         exynos_dp_config_video(dp);
 976 }
 977
 978 static int __devinit exynos_dp_probe(struct platform_device *pdev)
 979 {
 980         struct resource *res;
 981         struct exynos_dp_device *dp;
 982         struct exynos_dp_platdata *pdata;
 983
 984         int ret = 0;
 985         int irqflags;
 986
 987         pdata = pdev->dev.platform_data;
 988         if (!pdata) {
 989                 dev_err(&pdev->dev, "no platform data\n");
 990                 return -EINVAL;
 991         }
 992
 993         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
 994         if (!dp) {
 995                 dev_err(&pdev->dev, "no memory for device data\n");
 996                 return -ENOMEM;
 997         }
 998
 999         dp->dev = &pdev->dev;
1000
1001         dp->clock = clk_get(&pdev->dev, "dp");
1002         if (IS_ERR(dp->clock)) {
1003                 dev_err(&pdev->dev, "failed to get clock\n");
1004                 ret = PTR_ERR(dp->clock);
1005                 goto err_dp;
1006         }
1007
1008         clk_enable(dp->clock);
1009
1010         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1011         if (!res) {
1012                 dev_err(&pdev->dev, "failed to get registers\n");
1013                 ret = -EINVAL;
1014                 goto err_clock;
1015         }
1016
1017         res = request_mem_region(res->start, resource_size(res),
1018                                 dev_name(&pdev->dev));
1019         if (!res) {
1020                 dev_err(&pdev->dev, "failed to request registers region\n");
1021                 ret = -EINVAL;
1022                 goto err_clock;
1023         }
1024
1025         dp->res = res;
1026
1027         dp->reg_base = ioremap(res->start, resource_size(res));
1028         if (!dp->reg_base) {
1029                 dev_err(&pdev->dev, "failed to ioremap\n");
1030                 ret = -ENOMEM;
1031                 goto err_req_region;
1032         }
1033
1034         if (gpio_is_valid(pdata->hpd_gpio)) {
1035                 dp->hpd_gpio = pdata->hpd_gpio;
1036                 ret = gpio_request_one(dp->hpd_gpio, GPIOF_IN, "dp_hpd");
1037                 if (ret)
1038                         goto err_ioremap;
1039                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1040                 irqflags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1041         } else {
1042                 dp->hpd_gpio = -ENODEV;
1043                 dp->irq = platform_get_irq(pdev, 0);
1044                 irqflags = 0;
1045         }
1046
1047         if (dp->irq < 0) {
1048                 dev_err(&pdev->dev, "failed to get irq\n");
1049                 ret = -ENODEV;
1050                 goto err_gpio;
1051         }
1052
1053         dp->training_type = pdata->training_type;
1054         dp->video_info = pdata->video_info;
1055         if (pdata->phy_init)
1056                 pdata->phy_init();
1057
1058         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1059
1060         ret = request_irq(dp->irq, exynos_dp_irq_handler, irqflags,
1061                         "exynos-dp", dp);
1062         if (ret) {
1063                 dev_err(&pdev->dev, "failed to request irq\n");
1064                 goto err_gpio;
1065         }
1066
1067         disable_irq(dp->irq);
1068
1069         platform_set_drvdata(pdev, dp);
1070
1071         exynos_fimd_dp_attach(dp->dev);
1072
1073         return 0;
1074
1075 err_gpio:
1076         if (gpio_is_valid(dp->hpd_gpio))
1077                 gpio_free(dp->hpd_gpio);
1078 err_ioremap:
1079         iounmap(dp->reg_base);
1080 err_req_region:
1081         release_mem_region(res->start, resource_size(res));
1082 err_clock:
1083         clk_put(dp->clock);
1084 err_dp:
1085         kfree(dp);
1086
1087         return ret;
1088 }
1089
1090 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1091 {
1092         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1093         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1094
1095         if (work_pending(&dp->hotplug_work))
1096                 flush_work_sync(&dp->hotplug_work);
1097
1098         if (pdata && pdata->phy_exit)
1099                 pdata->phy_exit();
1100
1101         if (gpio_is_valid(dp->hpd_gpio))
1102                 gpio_free(dp->hpd_gpio);
1103
1104         free_irq(dp->irq, dp);
1105         iounmap(dp->reg_base);
1106
1107         clk_disable(dp->clock);
1108         clk_put(dp->clock);
1109
1110         release_mem_region(dp->res->start, resource_size(dp->res));
1111
1112         kfree(dp);
1113
1114         return 0;
1115 }
1116
1117 #ifdef CONFIG_PM_SLEEP
1118 int exynos_dp_suspend(struct device *dev)
1119 {
1120         struct platform_device *pdev = to_platform_device(dev);
1121         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1122         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1123
1124         disable_irq(dp->irq);
1125
1126         if (work_pending(&dp->hotplug_work))
1127                 flush_work_sync(&dp->hotplug_work);
1128
1129         if (pdata && pdata->phy_exit)
1130                 pdata->phy_exit();
1131
1132         clk_disable(dp->clock);
1133
1134         return 0;
1135 }
1136
1137 int exynos_dp_resume(struct device *dev)
1138 {
1139         struct platform_device *pdev = to_platform_device(dev);
1140         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
1141         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1142
1143         if (pdata && pdata->phy_init)
1144                 pdata->phy_init();
1145
1146         clk_enable(dp->clock);
1147
1148         exynos_dp_init_dp(dp);
1149
1150         enable_irq(dp->irq);
1151
1152         return 0;
1153 }
1154 #else
1155 int exynos_dp_suspend(struct device *dev)
1156 {
1157         return 0;
1158 }
1159
1160 int exynos_dp_resume(struct device *dev)
1161 {
1162         return 0;
1163 }
1164 #endif
1165
1166 struct platform_driver dp_driver = {
1167         .probe          = exynos_dp_probe,
1168         .remove         = __devexit_p(exynos_dp_remove),
1169         .driver         = {
1170                 .name   = "s5p-dp",
1171                 .owner  = THIS_MODULE,
1172         },
1173 };