drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include "drmP.h"
  14 #include "drm_crtc_helper.h"
  15
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/gpio.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/of.h>
  26 #include <linux/workqueue.h>
  27
  28 #include <video/exynos_dp.h>
  29 #include "exynos_drm_drv.h"
  30 #include "exynos_drm_display.h"
  31
  32 #ifdef CONFIG_DRM_PTN3460
  33 #include "i2c/ptn3460.h"
  34 #endif
  35
  36 #include <plat/cpu.h>
  37 #include <plat/gpio-cfg.h>
  38
  39 #include "exynos_dp_core.h"
  40
  41 #define PLL_MAX_TRIES 100
  42
  43 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  44 {
  45         exynos_dp_reset(dp);
  46
  47         /* SW defined function Normal operation */
  48         exynos_dp_enable_sw_function(dp);
  49
  50         exynos_dp_init_analog_func(dp);
  51
  52         exynos_dp_init_hpd(dp);
  53         exynos_dp_init_aux(dp);
  54
  55         return 0;
  56 }
  57
  58 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  59 {
  60         int timeout_loop = 0;
  61
  62         if (gpio_is_valid(dp->hpd_gpio))
  63                 return !gpio_get_value(dp->hpd_gpio);
  64
  65         while (exynos_dp_get_plug_in_status(dp) != 0) {
  66                 timeout_loop++;
  67                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  68                         dev_err(dp->dev, "failed to get hpd plug status\n");
  69                         return -ETIMEDOUT;
  70                 }
  71                 udelay(10);
  72         }
  73
  74         return 0;
  75 }
  76
  77 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  78 {
  79         int i;
  80         unsigned char sum = 0;
  81
  82         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  83                 sum = sum + edid_data[i];
  84
  85         return sum;
  86 }
  87
  88 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  89 {
  90         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  91         unsigned int extend_block = 0;
  92         unsigned char sum;
  93         unsigned char test_vector;
  94         int retval;
  95
  96         /*
  97          * EDID device address is 0x50.
  98          * However, if necessary, you must have set upper address
  99          * into E-EDID in I2C device, 0x30.
 100          */
 101
 102         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 103         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 104                                 EDID_EXTENSION_FLAG,
 105                                 &extend_block);
 106         if (retval)
 107                 return retval;
 108
 109         if (extend_block > 0) {
 110                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 111
 112                 /* Read EDID data */
 113                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 114                                                 EDID_HEADER_PATTERN,
 115                                                 EDID_BLOCK_LENGTH,
 116                                                 &edid[EDID_HEADER_PATTERN]);
 117                 if (retval != 0) {
 118                         dev_err(dp->dev, "EDID Read failed!\n");
 119                         return -EIO;
 120                 }
 121                 sum = exynos_dp_calc_edid_check_sum(edid);
 122                 if (sum != 0) {
 123                         dev_err(dp->dev, "EDID bad checksum!\n");
 124                         return -EIO;
 125                 }
 126
 127                 /* Read additional EDID data */
 128                 retval = exynos_dp_read_bytes_from_i2c(dp,
 129                                 I2C_EDID_DEVICE_ADDR,
 130                                 EDID_BLOCK_LENGTH,
 131                                 EDID_BLOCK_LENGTH,
 132                                 &edid[EDID_BLOCK_LENGTH]);
 133                 if (retval != 0) {
 134                         dev_err(dp->dev, "EDID Read failed!\n");
 135                         return -EIO;
 136                 }
 137                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 138                 if (sum != 0) {
 139                         dev_err(dp->dev, "EDID bad checksum!\n");
 140                         return -EIO;
 141                 }
 142
 143                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 144                                         &test_vector);
 145                 if (test_vector & DPCD_TEST_EDID_READ) {
 146                         exynos_dp_write_byte_to_dpcd(dp,
 147                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 148                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 149                         exynos_dp_write_byte_to_dpcd(dp,
 150                                 DPCD_ADDR_TEST_RESPONSE,
 151                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 152                 }
 153         } else {
 154                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 155
 156                 /* Read EDID data */
 157                 retval = exynos_dp_read_bytes_from_i2c(dp,
 158                                 I2C_EDID_DEVICE_ADDR,
 159                                 EDID_HEADER_PATTERN,
 160                                 EDID_BLOCK_LENGTH,
 161                                 &edid[EDID_HEADER_PATTERN]);
 162                 if (retval != 0) {
 163                         dev_err(dp->dev, "EDID Read failed!\n");
 164                         return -EIO;
 165                 }
 166                 sum = exynos_dp_calc_edid_check_sum(edid);
 167                 if (sum != 0) {
 168                         dev_err(dp->dev, "EDID bad checksum!\n");
 169                         return -EIO;
 170                 }
 171
 172                 exynos_dp_read_byte_from_dpcd(dp,
 173                         DPCD_ADDR_TEST_REQUEST,
 174                         &test_vector);
 175                 if (test_vector & DPCD_TEST_EDID_READ) {
 176                         exynos_dp_write_byte_to_dpcd(dp,
 177                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 178                                 edid[EDID_CHECKSUM]);
 179                         exynos_dp_write_byte_to_dpcd(dp,
 180                                 DPCD_ADDR_TEST_RESPONSE,
 181                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 182                 }
 183         }
 184
 185         dev_err(dp->dev, "EDID Read success!\n");
 186         return 0;
 187 }
 188
 189 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 190 {
 191         u8 buf[12];
 192         int i;
 193         int ret;
 194
 195         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 196         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, 12, buf);
 197         if (ret)
 198                 return ret;
 199
 200         /* Read EDID */
 201         for (i = 0; i < 3; i++) {
 202                 ret = exynos_dp_read_edid(dp);
 203                 if (!ret)
 204                         break;
 205         }
 206
 207         return ret;
 208 }
 209
 210 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 211                                                 bool enable)
 212 {
 213         u8 data;
 214
 215         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 216
 217         if (enable)
 218                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 219                         DPCD_ENHANCED_FRAME_EN |
 220                         DPCD_LANE_COUNT_SET(data));
 221         else
 222                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 223                         DPCD_LANE_COUNT_SET(data));
 224 }
 225
 226 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 227 {
 228         u8 data;
 229         int retval;
 230
 231         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 232         retval = DPCD_ENHANCED_FRAME_CAP(data);
 233
 234         return retval;
 235 }
 236
 237 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 238 {
 239         u8 data;
 240
 241         data = exynos_dp_is_enhanced_mode_available(dp);
 242         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 243         exynos_dp_enable_enhanced_mode(dp, data);
 244 }
 245
 246 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 247 {
 248         exynos_dp_set_training_pattern(dp, DP_NONE);
 249
 250         exynos_dp_write_byte_to_dpcd(dp,
 251                 DPCD_ADDR_TRAINING_PATTERN_SET,
 252                 DPCD_TRAINING_PATTERN_DISABLED);
 253 }
 254
 255 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 256                                         int pre_emphasis, int lane)
 257 {
 258         switch (lane) {
 259         case 0:
 260                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 261                 break;
 262         case 1:
 263                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 264                 break;
 265
 266         case 2:
 267                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 268                 break;
 269
 270         case 3:
 271                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 272                 break;
 273         }
 274 }
 275
 276 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 277 {
 278         int ret, lane, lane_count, pll_tries;
 279         u8 buf[4];
 280
 281         lane_count = dp->link_train.lane_count;
 282
 283         dp->link_train.lt_state = CLOCK_RECOVERY;
 284         dp->link_train.eq_loop = 0;
 285
 286         for (lane = 0; lane < lane_count; lane++)
 287                 dp->link_train.cr_loop[lane] = 0;
 288
 289         /* Set link rate and count as you want to establish*/
 290         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 291         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 292
 293         /* Setup RX configuration */
 294         buf[0] = dp->link_train.link_rate;
 295         buf[1] = dp->link_train.lane_count;
 296         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 297         if (ret)
 298                 return ret;
 299
 300         /* Set TX pre-emphasis to minimum */
 301         for (lane = 0; lane < lane_count; lane++)
 302                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 303                         PRE_EMPHASIS_LEVEL_0, lane);
 304
 305         /* Wait for PLL lock */
 306         pll_tries = 0;
 307         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 308                 if (pll_tries == PLL_MAX_TRIES)
 309                         return -ETIMEDOUT;
 310
 311                 pll_tries++;
 312                 udelay(100);
 313         }
 314
 315         /* Set training pattern 1 */
 316         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 317
 318         /* Set RX training pattern */
 319         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 320                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 321         if (ret)
 322                 return ret;
 323
 324         for (lane = 0; lane < lane_count; lane++)
 325                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 326                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 327         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 328                 lane_count, buf);
 329         if (ret)
 330                 return ret;
 331
 332         return ret;
 333 }
 334
 335 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 336 {
 337         int shift = (lane & 1) * 4;
 338         u8 link_value = link_status[lane>>1];
 339
 340         return (link_value >> shift) & 0xf;
 341 }
 342
 343 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 344 {
 345         int lane;
 346         u8 lane_status;
 347
 348         for (lane = 0; lane < lane_count; lane++) {
 349                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 350                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 351                         return -EINVAL;
 352         }
 353         return 0;
 354 }
 355
 356 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 357 {
 358         int lane;
 359         u8 lane_align;
 360         u8 lane_status;
 361
 362         lane_align = link_status[2];
 363         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 364                 return -EINVAL;
 365
 366         for (lane = 0; lane < lane_count; lane++) {
 367                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 368                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 369                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 370                         return -EINVAL;
 371         }
 372         return 0;
 373 }
 374
 375 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 376                                                         int lane)
 377 {
 378         int shift = (lane & 1) * 4;
 379         u8 link_value = adjust_request[lane>>1];
 380
 381         return (link_value >> shift) & 0x3;
 382 }
 383
 384 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 385                                         u8 adjust_request[2],
 386                                         int lane)
 387 {
 388         int shift = (lane & 1) * 4;
 389         u8 link_value = adjust_request[lane>>1];
 390
 391         return ((link_value >> shift) & 0xc) >> 2;
 392 }
 393
 394 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 395                                         u8 training_lane_set, int lane)
 396 {
 397         switch (lane) {
 398         case 0:
 399                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 400                 break;
 401         case 1:
 402                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 403                 break;
 404
 405         case 2:
 406                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 407                 break;
 408
 409         case 3:
 410                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 411                 break;
 412         }
 413 }
 414
 415 static unsigned int exynos_dp_get_lane_link_training(
 416                                 struct exynos_dp_device *dp,
 417                                 int lane)
 418 {
 419         u32 reg = 0;
 420
 421         switch (lane) {
 422         case 0:
 423                 reg = exynos_dp_get_lane0_link_training(dp);
 424                 break;
 425         case 1:
 426                 reg = exynos_dp_get_lane1_link_training(dp);
 427                 break;
 428         case 2:
 429                 reg = exynos_dp_get_lane2_link_training(dp);
 430                 break;
 431         case 3:
 432                 reg = exynos_dp_get_lane3_link_training(dp);
 433                 break;
 434         }
 435
 436         return reg;
 437 }
 438
 439 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 440 {
 441         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 442                 /* set to reduced bit rate */
 443                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 444                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 445                         dp->link_train.link_rate);
 446                 dp->link_train.lt_state = START;
 447         } else {
 448                 exynos_dp_training_pattern_dis(dp);
 449                 /* set enhanced mode if available */
 450                 exynos_dp_set_enhanced_mode(dp);
 451                 dp->link_train.lt_state = FAILED;
 452         }
 453 }
 454
 455 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 456                                 u8 adjust_request[2])
 457 {
 458         int lane;
 459         int lane_count;
 460         u8 voltage_swing;
 461         u8 pre_emphasis;
 462         u8 training_lane;
 463
 464         lane_count = dp->link_train.lane_count;
 465         for (lane = 0; lane < lane_count; lane++) {
 466                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 467                                                 adjust_request, lane);
 468                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 469                                                 adjust_request, lane);
 470                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 471                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 472
 473                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 474                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 475                         training_lane |= DPCD_MAX_SWING_REACHED;
 476                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 477                 }
 478                 dp->link_train.training_lane[lane] = training_lane;
 479         }
 480 }
 481
 482 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 483                                         u8 voltage_swing)
 484 {
 485         int lane;
 486         int lane_count;
 487
 488         lane_count = dp->link_train.lane_count;
 489         for (lane = 0; lane < lane_count; lane++) {
 490                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 491                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 492                         return -EINVAL;
 493         }
 494         return 0;
 495 }
 496
 497 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 498 {
 499         int ret, lane, lane_count;
 500         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 501         u8 *adjust_request;
 502
 503         udelay(100);
 504
 505         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 506                         link_status);
 507         if (ret)
 508                 return ret;
 509
 510         lane_count = dp->link_train.lane_count;
 511         if (lane_count == 0)
 512                 return 0;
 513
 514         adjust_request = link_status + 4;
 515
 516         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 517                 /* set training pattern 2 for EQ */
 518                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 519
 520                 ret = exynos_dp_write_byte_to_dpcd(dp,
 521                         DPCD_ADDR_TRAINING_PATTERN_SET,
 522                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 523                 if (ret)
 524                         return ret;
 525
 526                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 527         } else {
 528                 for (lane = 0; lane < lane_count; lane++) {
 529                         training_lane = exynos_dp_get_lane_link_training(
 530                                                         dp, lane);
 531                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 532                                                         adjust_request, lane);
 533                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 534                                                         adjust_request, lane);
 535                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 536                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 537                                 dp->link_train.cr_loop[lane]++;
 538                         dp->link_train.training_lane[lane] = training_lane;
 539                 }
 540
 541                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 542                         exynos_dp_reduce_link_rate(dp);
 543                         return ret;
 544                 }
 545         }
 546
 547         exynos_dp_get_adjust_train(dp, adjust_request);
 548
 549         for (lane = 0; lane < lane_count; lane++) {
 550                 exynos_dp_set_lane_link_training(dp,
 551                         dp->link_train.training_lane[lane], lane);
 552                 ret = exynos_dp_write_byte_to_dpcd(dp,
 553                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 554                         dp->link_train.training_lane[lane]);
 555                 if (ret)
 556                         return ret;
 557         }
 558
 559         return ret;
 560 }
 561
 562 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 563 {
 564         int ret, lane, lane_count;
 565         u8 link_status[6];
 566         u32 reg;
 567         u8 *adjust_request;
 568
 569         udelay(400);
 570
 571         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 572                                 6, link_status);
 573         if (ret)
 574                 return ret;
 575
 576         adjust_request = link_status + 4;
 577         lane_count = dp->link_train.lane_count;
 578
 579         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 580                 exynos_dp_reduce_link_rate(dp);
 581                 return ret;
 582         }
 583         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 584                 /* traing pattern Set to Normal */
 585                 exynos_dp_training_pattern_dis(dp);
 586
 587                 dev_info(dp->dev, "Link Training success!\n");
 588
 589                 exynos_dp_get_link_bandwidth(dp, &reg);
 590                 dp->link_train.link_rate = reg;
 591                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 592                         dp->link_train.link_rate);
 593
 594                 exynos_dp_get_lane_count(dp, &reg);
 595                 dp->link_train.lane_count = reg;
 596                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 597                         dp->link_train.lane_count);
 598                 /* set enhanced mode if available */
 599                 exynos_dp_set_enhanced_mode(dp);
 600
 601                 dp->link_train.lt_state = FINISHED;
 602         } else {
 603                 /* not all locked */
 604                 dp->link_train.eq_loop++;
 605
 606                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 607                         exynos_dp_reduce_link_rate(dp);
 608                 } else {
 609                         exynos_dp_get_adjust_train(dp, adjust_request);
 610
 611                         for (lane = 0; lane < lane_count; lane++) {
 612                                 exynos_dp_set_lane_link_training(dp,
 613                                         dp->link_train.training_lane[lane],
 614                                         lane);
 615                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 616                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 617                                         dp->link_train.training_lane[lane]);
 618                                 if (ret)
 619                                         return ret;
 620                         }
 621                 }
 622         }
 623
 624         return ret;
 625 }
 626
 627 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 628                         u8 *bandwidth)
 629 {
 630         u8 data;
 631
 632         /*
 633          * For DP rev.1.1, Maximum link rate of Main Link lanes
 634          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 635          */
 636         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 637         *bandwidth = data;
 638 }
 639
 640 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 641                         u8 *lane_count)
 642 {
 643         u8 data;
 644
 645         /*
 646          * For DP rev.1.1, Maximum number of Main Link lanes
 647          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 648          */
 649         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 650         *lane_count = DPCD_MAX_LANE_COUNT(data);
 651 }
 652
 653 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 654                         enum link_lane_count_type max_lane,
 655                         enum link_rate_type max_rate)
 656 {
 657         /*
 658          * MACRO_RST must be applied after the PLL_LOCK to avoid
 659          * the DP inter pair skew issue for at least 10 us
 660          */
 661         exynos_dp_reset_macro(dp);
 662
 663         /* Initialize by reading RX's DPCD */
 664         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 665         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 666
 667         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 668            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 669                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 670                         dp->link_train.link_rate);
 671                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 672         }
 673
 674         if (dp->link_train.lane_count == 0) {
 675                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 676                         dp->link_train.lane_count);
 677                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 678         }
 679
 680         /* Setup TX lane count & rate */
 681         if (dp->link_train.lane_count > max_lane)
 682                 dp->link_train.lane_count = max_lane;
 683         if (dp->link_train.link_rate > max_rate)
 684                 dp->link_train.link_rate = max_rate;
 685
 686         /* All DP analog module power up */
 687         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 688 }
 689
 690 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 691 {
 692         int ret = 0, training_finished = 0;
 693
 694         /* Turn off unnecessary lanes */
 695         switch (dp->link_train.lane_count) {
 696         case LANE_COUNT1:
 697                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 698         case LANE_COUNT2:
 699                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 700                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 701                 break;
 702         default:
 703                 break;
 704         }
 705
 706         dp->link_train.lt_state = START;
 707
 708         /* Process here */
 709         while (!ret && !training_finished) {
 710                 switch (dp->link_train.lt_state) {
 711                 case START:
 712                         ret = exynos_dp_link_start(dp);
 713                         break;
 714                 case CLOCK_RECOVERY:
 715                         ret = exynos_dp_process_clock_recovery(dp);
 716                         break;
 717                 case EQUALIZER_TRAINING:
 718                         ret = exynos_dp_process_equalizer_training(dp);
 719                         break;
 720                 case FINISHED:
 721                         training_finished = 1;
 722                         break;
 723                 case FAILED:
 724                         return -EREMOTEIO;
 725                 }
 726         }
 727         if (ret)
 728                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 729
 730         return ret;
 731 }
 732
 733 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 734                                 u32 max_lane,
 735                                 u32 max_rate)
 736 {
 737         u32 status;
 738         int ret, lane;
 739
 740         exynos_dp_stop_video(dp);
 741
 742         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 743                 dev_err(dp->dev, "PLL is not locked yet.\n");
 744                 return -EAGAIN;
 745         }
 746
 747         exynos_dp_reset_macro(dp);
 748
 749         /* Set TX pre-emphasis to minimum */
 750         for (lane = 0; lane < max_lane; lane++)
 751                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 752                                 PRE_EMPHASIS_LEVEL_0, lane);
 753
 754         /* All DP analog module power up */
 755         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 756
 757         /* Initialize by reading RX's DPCD */
 758         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 759         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 760
 761         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 762                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 763                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 764                         dp->link_train.link_rate);
 765                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 766         }
 767
 768         if (dp->link_train.lane_count == 0) {
 769                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 770                         dp->link_train.lane_count);
 771                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 772         }
 773
 774         /* Setup TX lane count & rate */
 775         if (dp->link_train.lane_count > max_lane)
 776                 dp->link_train.lane_count = max_lane;
 777         if (dp->link_train.link_rate > max_rate)
 778                 dp->link_train.link_rate = max_rate;
 779
 780         /* Set link rate and count as you want to establish*/
 781         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 782         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 783
 784         /* Set sink to D0 (Sink Not Ready) mode. */
 785         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 786                                                 DPCD_SET_POWER_STATE_D0);
 787
 788         /* Enable H/W Link Training */
 789         ret = exynos_dp_enable_hw_link_training(dp);
 790
 791         if (ret) {
 792                 dev_err(dp->dev, " H/W link training failure: %d\n", ret);
 793                 return ret;
 794         }
 795
 796         exynos_dp_get_link_bandwidth(dp, &status);
 797         dp->link_train.link_rate = status;
 798         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 799                                 dp->link_train.link_rate);
 800
 801         exynos_dp_get_lane_count(dp, &status);
 802         dp->link_train.lane_count = status;
 803         dev_dbg(dp->dev, "final lane count = %.2x\n",
 804                                 dp->link_train.lane_count);
 805
 806         return 0;
 807 }
 808
 809 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 810                                 u32 count,
 811                                 u32 bwtype)
 812 {
 813         int i;
 814         int retval;
 815
 816         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 817                 exynos_dp_init_training(dp, count, bwtype);
 818                 retval = exynos_dp_sw_link_training(dp);
 819                 if (retval == 0)
 820                         break;
 821
 822                 udelay(100);
 823         }
 824
 825         return retval;
 826 }
 827
 828 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 829 {
 830         int retval = 0;
 831         int timeout_loop = 0;
 832
 833         exynos_dp_config_video_slave_mode(dp);
 834
 835         exynos_dp_set_video_color_format(dp);
 836
 837         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 838                 dev_err(dp->dev, "PLL is not locked yet.\n");
 839                 return -EINVAL;
 840         }
 841
 842         for (;;) {
 843                 timeout_loop++;
 844                 if (!exynos_dp_is_slave_video_stream_clock_on(dp))
 845                         break;
 846                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 847                         dev_err(dp->dev, "Wait for stream clock timed out\n");
 848                         return -ETIMEDOUT;
 849                 }
 850
 851                 usleep_range(1000, 5000);
 852         }
 853
 854         /* Set to use the register calculated M/N video */
 855         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 856
 857         /* For video bist, Video timing must be generated by register */
 858         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 859
 860         /* Disable video mute */
 861         exynos_dp_enable_video_mute(dp, 0);
 862
 863         /* Configure video slave mode */
 864         exynos_dp_enable_video_master(dp, 0);
 865
 866         /* Enable video */
 867         exynos_dp_start_video(dp);
 868
 869         timeout_loop = 0;
 870
 871         for (;;) {
 872                 timeout_loop++;
 873                 if (!exynos_dp_is_video_stream_on(dp))
 874                         break;
 875
 876                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 877                         dev_err(dp->dev, "Wait for video stream timed out\n");
 878                         return -ETIMEDOUT;
 879                 }
 880
 881                 usleep_range(1000, 5000);
 882         }
 883
 884         if (retval != 0)
 885                 dev_err(dp->dev, "Video stream is not detected!\n");
 886
 887         return retval;
 888 }
 889
 890 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 891 {
 892         u8 data;
 893
 894         if (enable) {
 895                 exynos_dp_enable_scrambling(dp);
 896
 897                 exynos_dp_read_byte_from_dpcd(dp,
 898                         DPCD_ADDR_TRAINING_PATTERN_SET,
 899                         &data);
 900                 exynos_dp_write_byte_to_dpcd(dp,
 901                         DPCD_ADDR_TRAINING_PATTERN_SET,
 902                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 903         } else {
 904                 exynos_dp_disable_scrambling(dp);
 905
 906                 exynos_dp_read_byte_from_dpcd(dp,
 907                         DPCD_ADDR_TRAINING_PATTERN_SET,
 908                         &data);
 909                 exynos_dp_write_byte_to_dpcd(dp,
 910                         DPCD_ADDR_TRAINING_PATTERN_SET,
 911                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 912         }
 913 }
 914
 915 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 916 {
 917         struct exynos_dp_device *dp = arg;
 918         enum dp_irq_type irq_type;
 919
 920         irq_type = exynos_dp_get_irq_type(dp);
 921         switch (irq_type) {
 922         case DP_IRQ_TYPE_HP_CABLE_IN:
 923         case DP_IRQ_TYPE_HP_CABLE_OUT:
 924                 dev_dbg(dp->dev, "Received irq - type=%d\n", irq_type);
 925                 schedule_work(&dp->hotplug_work);
 926                 exynos_dp_clear_hotplug_interrupts(dp);
 927                 break;
 928         case DP_IRQ_TYPE_HP_CHANGE:
 929                 /*
 930                  * We get these change notifications once in a while, but there
 931                  * is nothing we can do with them. Just ignore it for now and
 932                  * only handle cable changes.
 933                  */
 934                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 935                 exynos_dp_clear_hotplug_interrupts(dp);
 936                 break;
 937         default:
 938                 dev_err(dp->dev, "Received irq - unknown type!\n");
 939                 break;
 940         }
 941         return IRQ_HANDLED;
 942 }
 943
 944 static void exynos_dp_hotplug(struct work_struct *work)
 945 {
 946         struct exynos_dp_device *dp;
 947
 948         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 949
 950         drm_helper_hpd_irq_event(dp->drm_dev);
 951 }
 952
 953 static void exynos_dp_train_link(struct exynos_dp_device *dp)
 954 {
 955         int ret;
 956
 957 #ifdef CONFIG_DRM_PTN3460
 958         ret = ptn3460_wait_until_ready(30 * 1000);
 959         if (ret) {
 960                 DRM_ERROR("PTN3460 is not ready, don't plug\n");
 961                 return;
 962         }
 963 #endif
 964
 965         ret = exynos_dp_handle_edid(dp);
 966         if (ret) {
 967                 dev_err(dp->dev, "unable to handle edid\n");
 968                 return;
 969         }
 970
 971         if (dp->training_type == SW_LINK_TRAINING)
 972                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 973                         dp->video_info->link_rate);
 974         else
 975                 ret = exynos_dp_set_hw_link_train(dp,
 976                         dp->video_info->lane_count, dp->video_info->link_rate);
 977         if (ret) {
 978                 dev_err(dp->dev, "unable to do link train\n");
 979                 return;
 980         }
 981
 982         exynos_dp_enable_scramble(dp, 1);
 983         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 984         exynos_dp_enable_enhanced_mode(dp, 1);
 985
 986         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 987         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 988
 989         exynos_dp_init_video(dp);
 990 }
 991
 992 static void exynos_dp_commit(void *ctx)
 993 {
 994         struct exynos_dp_device *dp = ctx;
 995
 996         exynos_dp_config_video(dp);
 997 }
 998
 999 static int exynos_dp_power_off(struct exynos_dp_device *dp)
1000 {
1001         if (!dp->enabled)
1002                 return 0;
1003
1004         dp->enabled = false;
1005         exynos_dp_disable_hpd(dp);
1006
1007         if (work_pending(&dp->hotplug_work))
1008                 flush_work_sync(&dp->hotplug_work);
1009
1010         if (dp->phy_ops.phy_exit)
1011                 dp->phy_ops.phy_exit();
1012
1013         clk_disable(dp->clock);
1014         return 0;
1015 }
1016
1017 static int exynos_dp_power_on(struct exynos_dp_device *dp)
1018 {
1019         if (dp->enabled)
1020                 return 0;
1021
1022         if (dp->phy_ops.phy_init)
1023                 dp->phy_ops.phy_init();
1024
1025         clk_enable(dp->clock);
1026
1027         exynos_dp_init_dp(dp);
1028
1029         /*
1030          * DP controller is reset and needs HPD interrupt to trigger
1031          * re-configuration. If we don't have valid IRQ, this is never
1032          * going to happen. Let's reconfigure it here in this case.
1033          */
1034         if (dp->irq < 0 && !exynos_dp_detect_hpd(dp))
1035                 schedule_work(&dp->hotplug_work);
1036
1037         /*
1038          * These calls are required to make sure we train the dp link when dpms
1039          * off/on is called from userspace. In the boot and resume cases, the
1040          * link training is handled via the modeset, but unfortunately modeset
1041          * isn't being called in the dpms off/on case.
1042          */
1043         exynos_dp_train_link(dp);
1044         exynos_dp_commit(dp);
1045
1046         dp->enabled = true;
1047         return 0;
1048 }
1049
1050 static int exynos_dp_dpms(void *ctx, int mode)
1051 {
1052         struct exynos_dp_device *dp = ctx;
1053
1054         switch (mode) {
1055         case DRM_MODE_DPMS_ON:
1056                 return exynos_dp_power_on(dp);
1057
1058         case DRM_MODE_DPMS_STANDBY:
1059         case DRM_MODE_DPMS_SUSPEND:
1060         case DRM_MODE_DPMS_OFF:
1061                 return exynos_dp_power_off(dp);
1062
1063         default:
1064                 DRM_ERROR("Unknown dpms mode %d\n", mode);
1065         }
1066         return -EINVAL;
1067 }
1068
1069 static int exynos_dp_check_timing(void *ctx, void *timing)
1070 {
1071         /*
1072          * TODO(seanpaul): The datasheet isn't terribly descriptive about the
1073          * limitations we have here. It's not vitally important to implement
1074          * this right now, but should be implemented once we use EDID to mode
1075          * set.
1076          */
1077         return 0;
1078 }
1079
1080 static bool exynos_dp_is_connected(void *ctx)
1081 {
1082         struct exynos_dp_device *dp = ctx;
1083
1084         if (dp->force_connected)
1085                 return true;
1086         else
1087                 return !exynos_dp_detect_hpd(dp);
1088 }
1089
1090 static int exynos_dp_subdrv_probe(void *ctx, struct drm_device *drm_dev)
1091 {
1092         struct exynos_dp_device *dp = ctx;
1093         int ret;
1094
1095         dp->drm_dev = drm_dev;
1096
1097         if (dp->irq >= 0) {
1098                 ret = request_irq(dp->irq, exynos_dp_irq_handler, dp->irq_flags,
1099                                 "exynos-dp", dp);
1100                 if (ret) {
1101                         dev_err(dp->dev, "failed to request irq\n");
1102                         return ret;
1103                 }
1104         }
1105
1106         exynos_dp_dpms(dp, DRM_MODE_DPMS_ON);
1107
1108         return 0;
1109 }
1110
1111 static void exynos_dp_mode_set(void *ctx, struct drm_display_mode *mode)
1112 {
1113         struct exynos_dp_device *dp = ctx;
1114
1115         exynos_dp_train_link(dp);
1116 }
1117
1118 static struct exynos_panel_ops dp_panel_ops = {
1119         .subdrv_probe = exynos_dp_subdrv_probe,
1120         .is_connected = exynos_dp_is_connected,
1121         .check_timing = exynos_dp_check_timing,
1122         .dpms = exynos_dp_dpms,
1123         .mode_set = exynos_dp_mode_set,
1124         .commit = exynos_dp_commit,
1125 };
1126
1127 static int __devinit exynos_dp_probe(struct platform_device *pdev)
1128 {
1129         struct resource *res;
1130         struct exynos_dp_device *dp;
1131         struct exynos_dp_platdata *pdata;
1132
1133         int ret = 0;
1134
1135         pdata = pdev->dev.platform_data;
1136         if (!pdata) {
1137                 dev_err(&pdev->dev, "no platform data\n");
1138                 return -EINVAL;
1139         }
1140
1141         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
1142         if (!dp) {
1143                 dev_err(&pdev->dev, "no memory for device data\n");
1144                 return -ENOMEM;
1145         }
1146
1147         dp->dev = &pdev->dev;
1148
1149         dp->clock = clk_get(&pdev->dev, "dp");
1150         if (IS_ERR(dp->clock)) {
1151                 dev_err(&pdev->dev, "failed to get clock\n");
1152                 ret = PTR_ERR(dp->clock);
1153                 goto err_dp;
1154         }
1155
1156         clk_enable(dp->clock);
1157
1158         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1159         if (!res) {
1160                 dev_err(&pdev->dev, "failed to get registers\n");
1161                 ret = -EINVAL;
1162                 goto err_clock;
1163         }
1164
1165         res = request_mem_region(res->start, resource_size(res),
1166                                 dev_name(&pdev->dev));
1167         if (!res) {
1168                 dev_err(&pdev->dev, "failed to request registers region\n");
1169                 ret = -EINVAL;
1170                 goto err_clock;
1171         }
1172
1173         dp->res = res;
1174
1175         dp->reg_base = ioremap(res->start, resource_size(res));
1176         if (!dp->reg_base) {
1177                 dev_err(&pdev->dev, "failed to ioremap\n");
1178                 ret = -ENOMEM;
1179                 goto err_req_region;
1180         }
1181
1182         if (gpio_is_valid(pdata->hpd_gpio)) {
1183                 dp->hpd_gpio = pdata->hpd_gpio;
1184                 ret = gpio_request_one(dp->hpd_gpio, GPIOF_IN, "dp_hpd");
1185                 if (ret)
1186                         goto err_ioremap;
1187 #ifdef CONFIG_S5P_GPIO_INT
1188                 ret = s5p_register_gpio_interrupt(dp->hpd_gpio);
1189                 if (ret < 0) {
1190                         dev_err(&pdev->dev, "cannot register/get GPIO irq\n");
1191                         goto err_gpio;
1192                 }
1193                 s3c_gpio_cfgpin(dp->hpd_gpio, S3C_GPIO_SFN(0xf));
1194 #endif
1195                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1196                 dp->irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1197         } else {
1198                 dp->hpd_gpio = -ENODEV;
1199                 dp->irq = platform_get_irq(pdev, 0);
1200                 dp->irq_flags = 0;
1201         }
1202
1203         dp->enabled = false;
1204         dp->training_type = pdata->training_type;
1205         dp->video_info = pdata->video_info;
1206         dp->force_connected = pdata->force_connected;
1207         if (pdata->phy_init) {
1208                 dp->phy_ops.phy_init = pdata->phy_init;
1209                 dp->phy_ops.phy_init();
1210         }
1211         if (pdata->phy_exit)
1212                 dp->phy_ops.phy_exit = pdata->phy_exit;
1213
1214         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1215
1216         platform_set_drvdata(pdev, dp);
1217
1218         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_FIMD, &dp_panel_ops,
1219                         dp);
1220
1221         return 0;
1222
1223 err_gpio:
1224         if (gpio_is_valid(dp->hpd_gpio))
1225                 gpio_free(dp->hpd_gpio);
1226 err_ioremap:
1227         iounmap(dp->reg_base);
1228 err_req_region:
1229         release_mem_region(res->start, resource_size(res));
1230 err_clock:
1231         clk_put(dp->clock);
1232 err_dp:
1233         kfree(dp);
1234
1235         return ret;
1236 }
1237
1238 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1239 {
1240         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1241
1242         /* power_off will take care of flushing the hotplug_work */
1243         exynos_dp_dpms(dp, DRM_MODE_DPMS_OFF);
1244
1245         if (gpio_is_valid(dp->hpd_gpio))
1246                 gpio_free(dp->hpd_gpio);
1247
1248         free_irq(dp->irq, dp);
1249         iounmap(dp->reg_base);
1250
1251         clk_disable(dp->clock);
1252         clk_put(dp->clock);
1253
1254         release_mem_region(dp->res->start, resource_size(dp->res));
1255
1256         kfree(dp);
1257
1258         return 0;
1259 }
1260
1261 struct platform_driver dp_driver = {
1262         .probe          = exynos_dp_probe,
1263         .remove         = __devexit_p(exynos_dp_remove),
1264         .driver         = {
1265                 .name   = "s5p-dp",
1266                 .owner  = THIS_MODULE,
1267         },
1268 };