drivers/gpu/drm/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include "drmP.h"
  14 #include "drm_crtc_helper.h"
  15
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/err.h>
  20 #include <linux/clk.h>
  21 #include <linux/gpio.h>
  22 #include <linux/io.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/delay.h>
  25 #include <linux/of.h>
  26 #include <linux/workqueue.h>
  27
  28 #include <video/exynos_dp.h>
  29 #include "exynos_drm_drv.h"
  30 #include "exynos_drm_display.h"
  31
  32 #include <plat/cpu.h>
  33 #include <plat/gpio-cfg.h>
  34
  35 #include "exynos_dp_core.h"
  36
  37 #define PLL_MAX_TRIES 100
  38
  39 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  40 {
  41         exynos_dp_reset(dp);
  42
  43         /* SW defined function Normal operation */
  44         exynos_dp_enable_sw_function(dp);
  45
  46         exynos_dp_init_analog_func(dp);
  47
  48         exynos_dp_init_hpd(dp);
  49         exynos_dp_init_aux(dp);
  50
  51         return 0;
  52 }
  53
  54 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  55 {
  56         int timeout_loop = 0;
  57
  58         if (gpio_is_valid(dp->hpd_gpio))
  59                 return !gpio_get_value(dp->hpd_gpio);
  60
  61         while (exynos_dp_get_plug_in_status(dp) != 0) {
  62                 timeout_loop++;
  63                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  64                         dev_err(dp->dev, "failed to get hpd plug status\n");
  65                         return -ETIMEDOUT;
  66                 }
  67                 udelay(10);
  68         }
  69
  70         return 0;
  71 }
  72
  73 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  74 {
  75         int i;
  76         unsigned char sum = 0;
  77
  78         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  79                 sum = sum + edid_data[i];
  80
  81         return sum;
  82 }
  83
  84 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  85 {
  86         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  87         unsigned int extend_block = 0;
  88         unsigned char sum;
  89         unsigned char test_vector;
  90         int retval;
  91
  92         /*
  93          * EDID device address is 0x50.
  94          * However, if necessary, you must have set upper address
  95          * into E-EDID in I2C device, 0x30.
  96          */
  97
  98         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  99         retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 100                                 EDID_EXTENSION_FLAG,
 101                                 &extend_block);
 102         if (retval)
 103                 return retval;
 104
 105         if (extend_block > 0) {
 106                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 107
 108                 /* Read EDID data */
 109                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
 110                                                 EDID_HEADER_PATTERN,
 111                                                 EDID_BLOCK_LENGTH,
 112                                                 &edid[EDID_HEADER_PATTERN]);
 113                 if (retval != 0) {
 114                         dev_err(dp->dev, "EDID Read failed!\n");
 115                         return -EIO;
 116                 }
 117                 sum = exynos_dp_calc_edid_check_sum(edid);
 118                 if (sum != 0) {
 119                         dev_err(dp->dev, "EDID bad checksum!\n");
 120                         return -EIO;
 121                 }
 122
 123                 /* Read additional EDID data */
 124                 retval = exynos_dp_read_bytes_from_i2c(dp,
 125                                 I2C_EDID_DEVICE_ADDR,
 126                                 EDID_BLOCK_LENGTH,
 127                                 EDID_BLOCK_LENGTH,
 128                                 &edid[EDID_BLOCK_LENGTH]);
 129                 if (retval != 0) {
 130                         dev_err(dp->dev, "EDID Read failed!\n");
 131                         return -EIO;
 132                 }
 133                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 134                 if (sum != 0) {
 135                         dev_err(dp->dev, "EDID bad checksum!\n");
 136                         return -EIO;
 137                 }
 138
 139                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 140                                         &test_vector);
 141                 if (test_vector & DPCD_TEST_EDID_READ) {
 142                         exynos_dp_write_byte_to_dpcd(dp,
 143                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 144                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 145                         exynos_dp_write_byte_to_dpcd(dp,
 146                                 DPCD_ADDR_TEST_RESPONSE,
 147                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 148                 }
 149         } else {
 150                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 151
 152                 /* Read EDID data */
 153                 retval = exynos_dp_read_bytes_from_i2c(dp,
 154                                 I2C_EDID_DEVICE_ADDR,
 155                                 EDID_HEADER_PATTERN,
 156                                 EDID_BLOCK_LENGTH,
 157                                 &edid[EDID_HEADER_PATTERN]);
 158                 if (retval != 0) {
 159                         dev_err(dp->dev, "EDID Read failed!\n");
 160                         return -EIO;
 161                 }
 162                 sum = exynos_dp_calc_edid_check_sum(edid);
 163                 if (sum != 0) {
 164                         dev_err(dp->dev, "EDID bad checksum!\n");
 165                         return -EIO;
 166                 }
 167
 168                 exynos_dp_read_byte_from_dpcd(dp,
 169                         DPCD_ADDR_TEST_REQUEST,
 170                         &test_vector);
 171                 if (test_vector & DPCD_TEST_EDID_READ) {
 172                         exynos_dp_write_byte_to_dpcd(dp,
 173                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 174                                 edid[EDID_CHECKSUM]);
 175                         exynos_dp_write_byte_to_dpcd(dp,
 176                                 DPCD_ADDR_TEST_RESPONSE,
 177                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 178                 }
 179         }
 180
 181         dev_err(dp->dev, "EDID Read success!\n");
 182         return 0;
 183 }
 184
 185 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 186 {
 187         u8 buf[12];
 188         int i;
 189         int ret;
 190
 191         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 192         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_DPCD_REV, 12, buf);
 193         if (ret)
 194                 return ret;
 195
 196         /* Read EDID */
 197         for (i = 0; i < 3; i++) {
 198                 ret = exynos_dp_read_edid(dp);
 199                 if (!ret)
 200                         break;
 201         }
 202
 203         return ret;
 204 }
 205
 206 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 207                                                 bool enable)
 208 {
 209         u8 data;
 210
 211         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 212
 213         if (enable)
 214                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 215                         DPCD_ENHANCED_FRAME_EN |
 216                         DPCD_LANE_COUNT_SET(data));
 217         else
 218                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 219                         DPCD_LANE_COUNT_SET(data));
 220 }
 221
 222 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 223 {
 224         u8 data;
 225         int retval;
 226
 227         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 228         retval = DPCD_ENHANCED_FRAME_CAP(data);
 229
 230         return retval;
 231 }
 232
 233 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 234 {
 235         u8 data;
 236
 237         data = exynos_dp_is_enhanced_mode_available(dp);
 238         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 239         exynos_dp_enable_enhanced_mode(dp, data);
 240 }
 241
 242 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 243 {
 244         exynos_dp_set_training_pattern(dp, DP_NONE);
 245
 246         exynos_dp_write_byte_to_dpcd(dp,
 247                 DPCD_ADDR_TRAINING_PATTERN_SET,
 248                 DPCD_TRAINING_PATTERN_DISABLED);
 249 }
 250
 251 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 252                                         int pre_emphasis, int lane)
 253 {
 254         switch (lane) {
 255         case 0:
 256                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 257                 break;
 258         case 1:
 259                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 260                 break;
 261
 262         case 2:
 263                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 264                 break;
 265
 266         case 3:
 267                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 268                 break;
 269         }
 270 }
 271
 272 static int exynos_dp_link_start(struct exynos_dp_device *dp)
 273 {
 274         int ret, lane, lane_count, pll_tries;
 275         u8 buf[4];
 276
 277         lane_count = dp->link_train.lane_count;
 278
 279         dp->link_train.lt_state = CLOCK_RECOVERY;
 280         dp->link_train.eq_loop = 0;
 281
 282         for (lane = 0; lane < lane_count; lane++)
 283                 dp->link_train.cr_loop[lane] = 0;
 284
 285         /* Set link rate and count as you want to establish*/
 286         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 287         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 288
 289         /* Setup RX configuration */
 290         buf[0] = dp->link_train.link_rate;
 291         buf[1] = dp->link_train.lane_count;
 292         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf);
 293         if (ret)
 294                 return ret;
 295
 296         /* Set TX pre-emphasis to minimum */
 297         for (lane = 0; lane < lane_count; lane++)
 298                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 299                         PRE_EMPHASIS_LEVEL_0, lane);
 300
 301         /* Wait for PLL lock */
 302         pll_tries = 0;
 303         while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 304                 if (pll_tries == PLL_MAX_TRIES)
 305                         return -ETIMEDOUT;
 306
 307                 pll_tries++;
 308                 udelay(100);
 309         }
 310
 311         /* Set training pattern 1 */
 312         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 313
 314         /* Set RX training pattern */
 315         ret = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET,
 316                 DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_1);
 317         if (ret)
 318                 return ret;
 319
 320         for (lane = 0; lane < lane_count; lane++)
 321                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 322                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 323         ret = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET,
 324                 lane_count, buf);
 325         if (ret)
 326                 return ret;
 327
 328         return ret;
 329 }
 330
 331 static unsigned char exynos_dp_get_lane_status(u8 link_status[6], int lane)
 332 {
 333         int shift = (lane & 1) * 4;
 334         u8 link_value = link_status[lane>>1];
 335
 336         return (link_value >> shift) & 0xf;
 337 }
 338
 339 static int exynos_dp_clock_recovery_ok(u8 link_status[6], int lane_count)
 340 {
 341         int lane;
 342         u8 lane_status;
 343
 344         for (lane = 0; lane < lane_count; lane++) {
 345                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 346                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 347                         return -EINVAL;
 348         }
 349         return 0;
 350 }
 351
 352 static int exynos_dp_channel_eq_ok(u8 link_status[6], int lane_count)
 353 {
 354         int lane;
 355         u8 lane_align;
 356         u8 lane_status;
 357
 358         lane_align = link_status[2];
 359         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 360                 return -EINVAL;
 361
 362         for (lane = 0; lane < lane_count; lane++) {
 363                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 364                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 365                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 366                         return -EINVAL;
 367         }
 368         return 0;
 369 }
 370
 371 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 372                                                         int lane)
 373 {
 374         int shift = (lane & 1) * 4;
 375         u8 link_value = adjust_request[lane>>1];
 376
 377         return (link_value >> shift) & 0x3;
 378 }
 379
 380 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 381                                         u8 adjust_request[2],
 382                                         int lane)
 383 {
 384         int shift = (lane & 1) * 4;
 385         u8 link_value = adjust_request[lane>>1];
 386
 387         return ((link_value >> shift) & 0xc) >> 2;
 388 }
 389
 390 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 391                                         u8 training_lane_set, int lane)
 392 {
 393         switch (lane) {
 394         case 0:
 395                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 396                 break;
 397         case 1:
 398                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 399                 break;
 400
 401         case 2:
 402                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 403                 break;
 404
 405         case 3:
 406                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 407                 break;
 408         }
 409 }
 410
 411 static unsigned int exynos_dp_get_lane_link_training(
 412                                 struct exynos_dp_device *dp,
 413                                 int lane)
 414 {
 415         u32 reg = 0;
 416
 417         switch (lane) {
 418         case 0:
 419                 reg = exynos_dp_get_lane0_link_training(dp);
 420                 break;
 421         case 1:
 422                 reg = exynos_dp_get_lane1_link_training(dp);
 423                 break;
 424         case 2:
 425                 reg = exynos_dp_get_lane2_link_training(dp);
 426                 break;
 427         case 3:
 428                 reg = exynos_dp_get_lane3_link_training(dp);
 429                 break;
 430         }
 431
 432         return reg;
 433 }
 434
 435 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 436 {
 437         if (dp->link_train.link_rate == LINK_RATE_2_70GBPS) {
 438                 /* set to reduced bit rate */
 439                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 440                 dev_err(dp->dev, "set to bandwidth %.2x\n",
 441                         dp->link_train.link_rate);
 442                 dp->link_train.lt_state = START;
 443         } else {
 444                 exynos_dp_training_pattern_dis(dp);
 445                 /* set enhanced mode if available */
 446                 exynos_dp_set_enhanced_mode(dp);
 447                 dp->link_train.lt_state = FAILED;
 448         }
 449 }
 450
 451 static void exynos_dp_get_adjust_train(struct exynos_dp_device *dp,
 452                                 u8 adjust_request[2])
 453 {
 454         int lane;
 455         int lane_count;
 456         u8 voltage_swing;
 457         u8 pre_emphasis;
 458         u8 training_lane;
 459
 460         lane_count = dp->link_train.lane_count;
 461         for (lane = 0; lane < lane_count; lane++) {
 462                 voltage_swing = exynos_dp_get_adjust_request_voltage(
 463                                                 adjust_request, lane);
 464                 pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 465                                                 adjust_request, lane);
 466                 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 467                                 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 468
 469                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 470                    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 471                         training_lane |= DPCD_MAX_SWING_REACHED;
 472                         training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 473                 }
 474                 dp->link_train.training_lane[lane] = training_lane;
 475         }
 476 }
 477
 478 static int exynos_dp_check_max_cr_loop(struct exynos_dp_device *dp,
 479                                         u8 voltage_swing)
 480 {
 481         int lane;
 482         int lane_count;
 483
 484         lane_count = dp->link_train.lane_count;
 485         for (lane = 0; lane < lane_count; lane++) {
 486                 if (voltage_swing == VOLTAGE_LEVEL_3 ||
 487                         dp->link_train.cr_loop[lane] == MAX_CR_LOOP)
 488                         return -EINVAL;
 489         }
 490         return 0;
 491 }
 492
 493 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 494 {
 495         int ret, lane, lane_count;
 496         u8 voltage_swing, pre_emphasis, training_lane, link_status[6];
 497         u8 *adjust_request;
 498
 499         udelay(100);
 500
 501         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 6,
 502                         link_status);
 503         if (ret)
 504                 return ret;
 505
 506         lane_count = dp->link_train.lane_count;
 507         if (lane_count == 0)
 508                 return 0;
 509
 510         adjust_request = link_status + 4;
 511
 512         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 513                 /* set training pattern 2 for EQ */
 514                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 515
 516                 ret = exynos_dp_write_byte_to_dpcd(dp,
 517                         DPCD_ADDR_TRAINING_PATTERN_SET,
 518                         DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2);
 519                 if (ret)
 520                         return ret;
 521
 522                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 523         } else {
 524                 for (lane = 0; lane < lane_count; lane++) {
 525                         training_lane = exynos_dp_get_lane_link_training(
 526                                                         dp, lane);
 527                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 528                                                         adjust_request, lane);
 529                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 530                                                         adjust_request, lane);
 531                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) == voltage_swing) &&
 532                             (DPCD_PRE_EMPHASIS_GET(training_lane) == pre_emphasis))
 533                                 dp->link_train.cr_loop[lane]++;
 534                         dp->link_train.training_lane[lane] = training_lane;
 535                 }
 536
 537                 if (exynos_dp_check_max_cr_loop(dp, voltage_swing) != 0) {
 538                         exynos_dp_reduce_link_rate(dp);
 539                         return ret;
 540                 }
 541         }
 542
 543         exynos_dp_get_adjust_train(dp, adjust_request);
 544
 545         for (lane = 0; lane < lane_count; lane++) {
 546                 exynos_dp_set_lane_link_training(dp,
 547                         dp->link_train.training_lane[lane], lane);
 548                 ret = exynos_dp_write_byte_to_dpcd(dp,
 549                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 550                         dp->link_train.training_lane[lane]);
 551                 if (ret)
 552                         return ret;
 553         }
 554
 555         return ret;
 556 }
 557
 558 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 559 {
 560         int ret, lane, lane_count;
 561         u8 link_status[6];
 562         u32 reg;
 563         u8 *adjust_request;
 564
 565         udelay(400);
 566
 567         ret = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 568                                 6, link_status);
 569         if (ret)
 570                 return ret;
 571
 572         adjust_request = link_status + 4;
 573         lane_count = dp->link_train.lane_count;
 574
 575         if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
 576                 exynos_dp_reduce_link_rate(dp);
 577                 return ret;
 578         }
 579         if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 580                 /* traing pattern Set to Normal */
 581                 exynos_dp_training_pattern_dis(dp);
 582
 583                 dev_info(dp->dev, "Link Training success!\n");
 584
 585                 exynos_dp_get_link_bandwidth(dp, &reg);
 586                 dp->link_train.link_rate = reg;
 587                 dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 588                         dp->link_train.link_rate);
 589
 590                 exynos_dp_get_lane_count(dp, &reg);
 591                 dp->link_train.lane_count = reg;
 592                 dev_dbg(dp->dev, "final lane count = %.2x\n",
 593                         dp->link_train.lane_count);
 594                 /* set enhanced mode if available */
 595                 exynos_dp_set_enhanced_mode(dp);
 596
 597                 dp->link_train.lt_state = FINISHED;
 598         } else {
 599                 /* not all locked */
 600                 dp->link_train.eq_loop++;
 601
 602                 if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 603                         exynos_dp_reduce_link_rate(dp);
 604                 } else {
 605                         exynos_dp_get_adjust_train(dp, adjust_request);
 606
 607                         for (lane = 0; lane < lane_count; lane++) {
 608                                 exynos_dp_set_lane_link_training(dp,
 609                                         dp->link_train.training_lane[lane],
 610                                         lane);
 611                                 ret = exynos_dp_write_byte_to_dpcd(dp,
 612                                         DPCD_ADDR_TRAINING_LANE0_SET + lane,
 613                                         dp->link_train.training_lane[lane]);
 614                                 if (ret)
 615                                         return ret;
 616                         }
 617                 }
 618         }
 619
 620         return ret;
 621 }
 622
 623 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 624                         u8 *bandwidth)
 625 {
 626         u8 data;
 627
 628         /*
 629          * For DP rev.1.1, Maximum link rate of Main Link lanes
 630          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 631          */
 632         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 633         *bandwidth = data;
 634 }
 635
 636 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 637                         u8 *lane_count)
 638 {
 639         u8 data;
 640
 641         /*
 642          * For DP rev.1.1, Maximum number of Main Link lanes
 643          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 644          */
 645         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 646         *lane_count = DPCD_MAX_LANE_COUNT(data);
 647 }
 648
 649 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 650                         enum link_lane_count_type max_lane,
 651                         enum link_rate_type max_rate)
 652 {
 653         /*
 654          * MACRO_RST must be applied after the PLL_LOCK to avoid
 655          * the DP inter pair skew issue for at least 10 us
 656          */
 657         exynos_dp_reset_macro(dp);
 658
 659         /* Initialize by reading RX's DPCD */
 660         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 661         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 662
 663         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 664            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 665                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 666                         dp->link_train.link_rate);
 667                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 668         }
 669
 670         if (dp->link_train.lane_count == 0) {
 671                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 672                         dp->link_train.lane_count);
 673                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 674         }
 675
 676         /* Setup TX lane count & rate */
 677         if (dp->link_train.lane_count > max_lane)
 678                 dp->link_train.lane_count = max_lane;
 679         if (dp->link_train.link_rate > max_rate)
 680                 dp->link_train.link_rate = max_rate;
 681
 682         /* All DP analog module power up */
 683         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 684 }
 685
 686 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 687 {
 688         int ret = 0, training_finished = 0;
 689
 690         /* Turn off unnecessary lanes */
 691         switch (dp->link_train.lane_count) {
 692         case LANE_COUNT1:
 693                 exynos_dp_set_analog_power_down(dp, CH1_BLOCK, 1);
 694         case LANE_COUNT2:
 695                 exynos_dp_set_analog_power_down(dp, CH2_BLOCK, 1);
 696                 exynos_dp_set_analog_power_down(dp, CH3_BLOCK, 1);
 697                 break;
 698         default:
 699                 break;
 700         }
 701
 702         dp->link_train.lt_state = START;
 703
 704         /* Process here */
 705         while (!ret && !training_finished) {
 706                 switch (dp->link_train.lt_state) {
 707                 case START:
 708                         ret = exynos_dp_link_start(dp);
 709                         break;
 710                 case CLOCK_RECOVERY:
 711                         ret = exynos_dp_process_clock_recovery(dp);
 712                         break;
 713                 case EQUALIZER_TRAINING:
 714                         ret = exynos_dp_process_equalizer_training(dp);
 715                         break;
 716                 case FINISHED:
 717                         training_finished = 1;
 718                         break;
 719                 case FAILED:
 720                         return -EREMOTEIO;
 721                 }
 722         }
 723         if (ret)
 724                 dev_err(dp->dev, "eDP link training failed (%d)\n", ret);
 725
 726         return ret;
 727 }
 728
 729 static int exynos_dp_set_hw_link_train(struct exynos_dp_device *dp,
 730                                 u32 max_lane,
 731                                 u32 max_rate)
 732 {
 733         u32 status;
 734         int ret, lane;
 735
 736         exynos_dp_stop_video(dp);
 737
 738         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 739                 dev_err(dp->dev, "PLL is not locked yet.\n");
 740                 return -EAGAIN;
 741         }
 742
 743         exynos_dp_reset_macro(dp);
 744
 745         /* Set TX pre-emphasis to minimum */
 746         for (lane = 0; lane < max_lane; lane++)
 747                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 748                                 PRE_EMPHASIS_LEVEL_0, lane);
 749
 750         /* All DP analog module power up */
 751         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 752
 753         /* Initialize by reading RX's DPCD */
 754         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 755         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 756
 757         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 758                 (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 759                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 760                         dp->link_train.link_rate);
 761                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 762         }
 763
 764         if (dp->link_train.lane_count == 0) {
 765                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 766                         dp->link_train.lane_count);
 767                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 768         }
 769
 770         /* Setup TX lane count & rate */
 771         if (dp->link_train.lane_count > max_lane)
 772                 dp->link_train.lane_count = max_lane;
 773         if (dp->link_train.link_rate > max_rate)
 774                 dp->link_train.link_rate = max_rate;
 775
 776         /* Set link rate and count as you want to establish*/
 777         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 778         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 779
 780         /* Set sink to D0 (Sink Not Ready) mode. */
 781         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 782                                                 DPCD_SET_POWER_STATE_D0);
 783
 784         /* Enable H/W Link Training */
 785         ret = exynos_dp_enable_hw_link_training(dp);
 786
 787         if (ret) {
 788                 dev_err(dp->dev, " H/W link training failure: %d\n", ret);
 789                 return ret;
 790         }
 791
 792         exynos_dp_get_link_bandwidth(dp, &status);
 793         dp->link_train.link_rate = status;
 794         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 795                                 dp->link_train.link_rate);
 796
 797         exynos_dp_get_lane_count(dp, &status);
 798         dp->link_train.lane_count = status;
 799         dev_dbg(dp->dev, "final lane count = %.2x\n",
 800                                 dp->link_train.lane_count);
 801
 802         return 0;
 803 }
 804
 805 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 806                                 u32 count,
 807                                 u32 bwtype)
 808 {
 809         int i;
 810         int retval;
 811
 812         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 813                 exynos_dp_init_training(dp, count, bwtype);
 814                 retval = exynos_dp_sw_link_training(dp);
 815                 if (retval == 0)
 816                         break;
 817
 818                 udelay(100);
 819         }
 820
 821         return retval;
 822 }
 823
 824 static int exynos_dp_config_video(struct exynos_dp_device *dp)
 825 {
 826         int retval = 0;
 827         int timeout_loop = 0;
 828
 829         exynos_dp_config_video_slave_mode(dp);
 830
 831         exynos_dp_set_video_color_format(dp);
 832
 833         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 834                 dev_err(dp->dev, "PLL is not locked yet.\n");
 835                 return -EINVAL;
 836         }
 837
 838         for (;;) {
 839                 timeout_loop++;
 840                 if (!exynos_dp_is_slave_video_stream_clock_on(dp))
 841                         break;
 842                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 843                         dev_err(dp->dev, "Wait for stream clock timed out\n");
 844                         return -ETIMEDOUT;
 845                 }
 846
 847                 usleep_range(1000, 5000);
 848         }
 849
 850         /* Set to use the register calculated M/N video */
 851         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 852
 853         /* For video bist, Video timing must be generated by register */
 854         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 855
 856         /* Disable video mute */
 857         exynos_dp_enable_video_mute(dp, 0);
 858
 859         /* Configure video slave mode */
 860         exynos_dp_enable_video_master(dp, 0);
 861
 862         /* Enable video */
 863         exynos_dp_start_video(dp);
 864
 865         timeout_loop = 0;
 866
 867         for (;;) {
 868                 timeout_loop++;
 869                 if (!exynos_dp_is_video_stream_on(dp))
 870                         break;
 871
 872                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 873                         dev_err(dp->dev, "Wait for video stream timed out\n");
 874                         return -ETIMEDOUT;
 875                 }
 876
 877                 usleep_range(1000, 5000);
 878         }
 879
 880         if (retval != 0)
 881                 dev_err(dp->dev, "Video stream is not detected!\n");
 882
 883         return retval;
 884 }
 885
 886 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 887 {
 888         u8 data;
 889
 890         if (enable) {
 891                 exynos_dp_enable_scrambling(dp);
 892
 893                 exynos_dp_read_byte_from_dpcd(dp,
 894                         DPCD_ADDR_TRAINING_PATTERN_SET,
 895                         &data);
 896                 exynos_dp_write_byte_to_dpcd(dp,
 897                         DPCD_ADDR_TRAINING_PATTERN_SET,
 898                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 899         } else {
 900                 exynos_dp_disable_scrambling(dp);
 901
 902                 exynos_dp_read_byte_from_dpcd(dp,
 903                         DPCD_ADDR_TRAINING_PATTERN_SET,
 904                         &data);
 905                 exynos_dp_write_byte_to_dpcd(dp,
 906                         DPCD_ADDR_TRAINING_PATTERN_SET,
 907                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 908         }
 909 }
 910
 911 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 912 {
 913         struct exynos_dp_device *dp = arg;
 914         enum dp_irq_type irq_type;
 915
 916         irq_type = exynos_dp_get_irq_type(dp);
 917         switch (irq_type) {
 918         case DP_IRQ_TYPE_HP_CABLE_IN:
 919         case DP_IRQ_TYPE_HP_CABLE_OUT:
 920                 dev_dbg(dp->dev, "Received irq - type=%d\n", irq_type);
 921                 schedule_work(&dp->hotplug_work);
 922                 exynos_dp_clear_hotplug_interrupts(dp);
 923                 break;
 924         case DP_IRQ_TYPE_HP_CHANGE:
 925                 /*
 926                  * We get these change notifications once in a while, but there
 927                  * is nothing we can do with them. Just ignore it for now and
 928                  * only handle cable changes.
 929                  */
 930                 dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
 931                 exynos_dp_clear_hotplug_interrupts(dp);
 932                 break;
 933         default:
 934                 dev_err(dp->dev, "Received irq - unknown type!\n");
 935                 break;
 936         }
 937         return IRQ_HANDLED;
 938 }
 939
 940 static void exynos_dp_hotplug(struct work_struct *work)
 941 {
 942         struct exynos_dp_device *dp;
 943
 944         dp = container_of(work, struct exynos_dp_device, hotplug_work);
 945
 946         drm_helper_hpd_irq_event(dp->drm_dev);
 947 }
 948
 949 static void exynos_dp_train_link(struct exynos_dp_device *dp)
 950 {
 951         int ret;
 952
 953         ret = exynos_dp_handle_edid(dp);
 954         if (ret) {
 955                 dev_err(dp->dev, "unable to handle edid\n");
 956                 return;
 957         }
 958
 959         if (dp->training_type == SW_LINK_TRAINING)
 960                 ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 961                         dp->video_info->link_rate);
 962         else
 963                 ret = exynos_dp_set_hw_link_train(dp,
 964                         dp->video_info->lane_count, dp->video_info->link_rate);
 965         if (ret) {
 966                 dev_err(dp->dev, "unable to do link train\n");
 967                 return;
 968         }
 969
 970         exynos_dp_enable_scramble(dp, 1);
 971         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 972         exynos_dp_enable_enhanced_mode(dp, 1);
 973
 974         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 975         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 976
 977         exynos_dp_init_video(dp);
 978 }
 979
 980 static int exynos_dp_power_off(struct exynos_dp_device *dp)
 981 {
 982         if (!dp->enabled)
 983                 return 0;
 984
 985         dp->enabled = false;
 986         exynos_dp_disable_hpd(dp);
 987
 988         if (work_pending(&dp->hotplug_work))
 989                 flush_work_sync(&dp->hotplug_work);
 990
 991         if (dp->phy_ops.phy_exit)
 992                 dp->phy_ops.phy_exit();
 993
 994         clk_disable(dp->clock);
 995         return 0;
 996 }
 997
 998 static int exynos_dp_power_on(struct exynos_dp_device *dp)
 999 {
1000         if (dp->enabled)
1001                 return 0;
1002
1003         if (dp->phy_ops.phy_init)
1004                 dp->phy_ops.phy_init();
1005
1006         clk_enable(dp->clock);
1007
1008         exynos_dp_init_dp(dp);
1009
1010         /*
1011          * DP controller is reset and needs HPD interrupt to trigger
1012          * re-configuration. If we don't have valid IRQ, this is never
1013          * going to happen. Let's reconfigure it here in this case.
1014          */
1015         if (dp->irq < 0 && !exynos_dp_detect_hpd(dp))
1016                 schedule_work(&dp->hotplug_work);
1017
1018         exynos_dp_train_link(dp);
1019         exynos_dp_config_video(dp);
1020
1021         dp->enabled = true;
1022         return 0;
1023 }
1024
1025 static int exynos_dp_dpms(void *ctx, int mode)
1026 {
1027         struct exynos_dp_device *dp = ctx;
1028
1029         switch (mode) {
1030         case DRM_MODE_DPMS_ON:
1031                 return exynos_dp_power_on(dp);
1032
1033         case DRM_MODE_DPMS_STANDBY:
1034         case DRM_MODE_DPMS_SUSPEND:
1035         case DRM_MODE_DPMS_OFF:
1036                 return exynos_dp_power_off(dp);
1037
1038         default:
1039                 DRM_ERROR("Unknown dpms mode %d\n", mode);
1040         }
1041         return -EINVAL;
1042 }
1043
1044 static int exynos_dp_check_timing(void *ctx, void *timing)
1045 {
1046         /*
1047          * TODO(seanpaul): The datasheet isn't terribly descriptive about the
1048          * limitations we have here. It's not vitally important to implement
1049          * this right now, but should be implemented once we use EDID to mode
1050          * set.
1051          */
1052         return 0;
1053 }
1054
1055 static bool exynos_dp_is_connected(void *ctx)
1056 {
1057         struct exynos_dp_device *dp = ctx;
1058
1059         if (dp->force_connected)
1060                 return true;
1061         else
1062                 return !exynos_dp_detect_hpd(dp);
1063 }
1064
1065 static int exynos_dp_subdrv_probe(void *ctx, struct drm_device *drm_dev)
1066 {
1067         struct exynos_dp_device *dp = ctx;
1068         int ret;
1069
1070         dp->drm_dev = drm_dev;
1071
1072         if (dp->irq >= 0) {
1073                 ret = request_irq(dp->irq, exynos_dp_irq_handler, dp->irq_flags,
1074                                 "exynos-dp", dp);
1075                 if (ret) {
1076                         dev_err(dp->dev, "failed to request irq\n");
1077                         return ret;
1078                 }
1079         }
1080
1081         exynos_dp_dpms(dp, DRM_MODE_DPMS_ON);
1082
1083         return 0;
1084 }
1085
1086 static struct exynos_panel_ops dp_panel_ops = {
1087         .subdrv_probe = exynos_dp_subdrv_probe,
1088         .is_connected = exynos_dp_is_connected,
1089         .check_timing = exynos_dp_check_timing,
1090         .dpms = exynos_dp_dpms,
1091 };
1092
1093 static int __devinit exynos_dp_probe(struct platform_device *pdev)
1094 {
1095         struct resource *res;
1096         struct exynos_dp_device *dp;
1097         struct exynos_dp_platdata *pdata;
1098
1099         int ret = 0;
1100
1101         pdata = pdev->dev.platform_data;
1102         if (!pdata) {
1103                 dev_err(&pdev->dev, "no platform data\n");
1104                 return -EINVAL;
1105         }
1106
1107         dp = kzalloc(sizeof(struct exynos_dp_device), GFP_KERNEL);
1108         if (!dp) {
1109                 dev_err(&pdev->dev, "no memory for device data\n");
1110                 return -ENOMEM;
1111         }
1112
1113         dp->dev = &pdev->dev;
1114
1115         dp->clock = clk_get(&pdev->dev, "dp");
1116         if (IS_ERR(dp->clock)) {
1117                 dev_err(&pdev->dev, "failed to get clock\n");
1118                 ret = PTR_ERR(dp->clock);
1119                 goto err_dp;
1120         }
1121
1122         clk_enable(dp->clock);
1123
1124         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1125         if (!res) {
1126                 dev_err(&pdev->dev, "failed to get registers\n");
1127                 ret = -EINVAL;
1128                 goto err_clock;
1129         }
1130
1131         res = request_mem_region(res->start, resource_size(res),
1132                                 dev_name(&pdev->dev));
1133         if (!res) {
1134                 dev_err(&pdev->dev, "failed to request registers region\n");
1135                 ret = -EINVAL;
1136                 goto err_clock;
1137         }
1138
1139         dp->res = res;
1140
1141         dp->reg_base = ioremap(res->start, resource_size(res));
1142         if (!dp->reg_base) {
1143                 dev_err(&pdev->dev, "failed to ioremap\n");
1144                 ret = -ENOMEM;
1145                 goto err_req_region;
1146         }
1147
1148         if (gpio_is_valid(pdata->hpd_gpio)) {
1149                 dp->hpd_gpio = pdata->hpd_gpio;
1150                 ret = gpio_request_one(dp->hpd_gpio, GPIOF_IN, "dp_hpd");
1151                 if (ret)
1152                         goto err_ioremap;
1153 #ifdef CONFIG_S5P_GPIO_INT
1154                 ret = s5p_register_gpio_interrupt(dp->hpd_gpio);
1155                 if (ret < 0) {
1156                         dev_err(&pdev->dev, "cannot register/get GPIO irq\n");
1157                         goto err_gpio;
1158                 }
1159                 s3c_gpio_cfgpin(dp->hpd_gpio, S3C_GPIO_SFN(0xf));
1160 #endif
1161                 dp->irq = gpio_to_irq(dp->hpd_gpio);
1162                 dp->irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
1163         } else {
1164                 dp->hpd_gpio = -ENODEV;
1165                 dp->irq = platform_get_irq(pdev, 0);
1166                 dp->irq_flags = 0;
1167         }
1168
1169         dp->enabled = false;
1170         dp->training_type = pdata->training_type;
1171         dp->video_info = pdata->video_info;
1172         dp->force_connected = pdata->force_connected;
1173         if (pdata->phy_init) {
1174                 dp->phy_ops.phy_init = pdata->phy_init;
1175                 dp->phy_ops.phy_init();
1176         }
1177         if (pdata->phy_exit)
1178                 dp->phy_ops.phy_exit = pdata->phy_exit;
1179
1180         INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
1181
1182         platform_set_drvdata(pdev, dp);
1183
1184         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_FIMD, &dp_panel_ops,
1185                         dp);
1186
1187         return 0;
1188
1189 err_gpio:
1190         if (gpio_is_valid(dp->hpd_gpio))
1191                 gpio_free(dp->hpd_gpio);
1192 err_ioremap:
1193         iounmap(dp->reg_base);
1194 err_req_region:
1195         release_mem_region(res->start, resource_size(res));
1196 err_clock:
1197         clk_put(dp->clock);
1198 err_dp:
1199         kfree(dp);
1200
1201         return ret;
1202 }
1203
1204 static int __devexit exynos_dp_remove(struct platform_device *pdev)
1205 {
1206         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
1207
1208         /* power_off will take care of flushing the hotplug_work */
1209         exynos_dp_dpms(dp, DRM_MODE_DPMS_OFF);
1210
1211         if (gpio_is_valid(dp->hpd_gpio))
1212                 gpio_free(dp->hpd_gpio);
1213
1214         free_irq(dp->irq, dp);
1215         iounmap(dp->reg_base);
1216
1217         clk_disable(dp->clock);
1218         clk_put(dp->clock);
1219
1220         release_mem_region(dp->res->start, resource_size(dp->res));
1221
1222         kfree(dp);
1223
1224         return 0;
1225 }
1226
1227 struct platform_driver dp_driver = {
1228         .probe          = exynos_dp_probe,
1229         .remove         = __devexit_p(exynos_dp_remove),
1230         .driver         = {
1231                 .name   = "s5p-dp",
1232                 .owner  = THIS_MODULE,
1233         },
1234 };