2 * Header file for Samsung DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef _EXYNOS_DP_CORE_H
14 #define _EXYNOS_DP_CORE_H
16 #include <video/exynos_dp.h>
19 DP_IRQ_TYPE_HP_CABLE_IN,
20 DP_IRQ_TYPE_HP_CABLE_OUT,
21 DP_IRQ_TYPE_HP_CHANGE,
33 enum link_training_state lt_state;
37 void (*phy_init)(void);
38 void (*phy_exit)(void);
41 struct exynos_dp_device {
43 struct drm_device *drm_dev;
47 void __iomem *reg_base;
50 struct dp_phy_ops phy_ops;
51 struct video_info *video_info;
52 enum link_training_type training_type;
53 struct link_train link_train;
54 struct work_struct hotplug_work;
58 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
59 void exynos_dp_stop_video(struct exynos_dp_device *dp);
60 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
61 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
62 void exynos_dp_reset(struct exynos_dp_device *dp);
63 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
64 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
65 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
66 enum analog_power_block block,
68 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
69 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
70 void exynos_dp_disable_hpd(struct exynos_dp_device *dp);
71 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
72 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
73 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
74 void exynos_dp_init_aux(struct exynos_dp_device *dp);
75 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
76 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
77 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
78 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
79 unsigned int reg_addr,
81 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
82 unsigned int reg_addr,
84 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
85 unsigned int reg_addr,
87 unsigned char data[]);
88 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
89 unsigned int reg_addr,
91 unsigned char data[]);
92 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
93 unsigned int device_addr,
94 unsigned int reg_addr);
95 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
96 unsigned int device_addr,
97 unsigned int reg_addr,
99 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
100 unsigned int device_addr,
101 unsigned int reg_addr,
103 unsigned char edid[]);
104 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
105 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
106 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
107 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
108 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
109 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
110 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
111 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
112 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
113 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
114 enum pattern_set pattern);
115 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
116 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
117 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
118 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
119 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
121 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
123 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
125 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
127 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
128 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
129 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
130 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
131 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
132 int exynos_dp_init_video(struct exynos_dp_device *dp);
134 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
135 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
136 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
137 enum clock_recovery_m_value_type type,
140 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
141 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
142 void exynos_dp_start_video(struct exynos_dp_device *dp);
143 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
144 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
145 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
146 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
148 int exynos_dp_enable_hw_link_training(struct exynos_dp_device *dp);
150 /* I2C EDID Chip ID, Slave Address */
151 #define I2C_EDID_DEVICE_ADDR 0x50
152 #define I2C_E_EDID_DEVICE_ADDR 0x30
154 #define EDID_BLOCK_LENGTH 0x80
155 #define EDID_HEADER_PATTERN 0x00
156 #define EDID_EXTENSION_FLAG 0x7e
157 #define EDID_CHECKSUM 0x7f
159 /* Definition for DPCD Register */
160 #define DPCD_ADDR_DPCD_REV 0x0000
161 #define DPCD_ADDR_MAX_LINK_RATE 0x0001
162 #define DPCD_ADDR_MAX_LANE_COUNT 0x0002
163 #define DPCD_ADDR_LINK_BW_SET 0x0100
164 #define DPCD_ADDR_LANE_COUNT_SET 0x0101
165 #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
166 #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
167 #define DPCD_ADDR_LANE0_1_STATUS 0x0202
168 #define DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED 0x0204
169 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
170 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
171 #define DPCD_ADDR_TEST_REQUEST 0x0218
172 #define DPCD_ADDR_TEST_RESPONSE 0x0260
173 #define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
174 #define DPCD_ADDR_SINK_POWER_STATE 0x0600
176 /* DPCD_ADDR_MAX_LANE_COUNT */
177 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
178 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
180 /* DPCD_ADDR_LANE_COUNT_SET */
181 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
182 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
184 /* DPCD_ADDR_TRAINING_PATTERN_SET */
185 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
186 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
187 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
188 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
189 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
191 /* DPCD_ADDR_TRAINING_LANE0_SET */
192 #define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
193 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
194 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
195 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
196 #define DPCD_MAX_SWING_REACHED (0x1 << 2)
197 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
198 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
199 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
201 /* DPCD_ADDR_LANE0_1_STATUS */
202 #define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
203 #define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
204 #define DPCD_LANE_CR_DONE (0x1 << 0)
205 #define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
206 DPCD_LANE_CHANNEL_EQ_DONE|\
207 DPCD_LANE_SYMBOL_LOCKED)
209 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
210 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
211 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
212 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
214 /* DPCD_ADDR_TEST_REQUEST */
215 #define DPCD_TEST_EDID_READ (0x1 << 2)
217 /* DPCD_ADDR_TEST_RESPONSE */
218 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
220 /* DPCD_ADDR_SINK_POWER_STATE */
221 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
222 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
224 #endif /* _EXYNOS_DP_CORE_H */