drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include "drmP.h"
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/clk.h>
  20 #include <linux/pm_runtime.h>
  21
  22 #include <drm/exynos_drm.h>
  23 #include <plat/regs-fb-v4.h>
  24
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_fbdev.h"
  27 #include "exynos_drm_crtc.h"
  28
  29 /*
  30  * FIMD is stand for Fully Interactive Mobile Display and
  31  * as a display controller, it transfers contents drawn on memory
  32  * to a LCD Panel through Display Interfaces such as RGB or
  33  * CPU Interface.
  34  */
  35
  36 /* position control register for hardware window 0, 2 ~ 4.*/
  37 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  38 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  39 /* size control register for hardware window 0. */
  40 #define VIDOSD_C_SIZE_W0        (VIDOSD_BASE + 0x08)
  41 /* alpha control register for hardware window 1 ~ 4. */
  42 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x18 + (win) * 16)
  43 /* size control register for hardware window 1 ~ 4. */
  44 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  45
  46 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  47 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  48 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  49
  50 /* color key control register for hardware window 1 ~ 4. */
  51 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + (x * 8))
  52 /* color key value register for hardware window 1 ~ 4. */
  53 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + (x * 8))
  54
  55 /* FIMD has totally five hardware windows. */
  56 #define WINDOWS_NR      5
  57
  58 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  59
  60 struct fimd_win_data {
  61         unsigned int            offset_x;
  62         unsigned int            offset_y;
  63         unsigned int            ovl_width;
  64         unsigned int            ovl_height;
  65         unsigned int            fb_width;
  66         unsigned int            fb_height;
  67         unsigned int            fb_pitch;
  68         unsigned int            bpp;
  69         dma_addr_t              dma_addr;
  70         void __iomem            *vaddr;
  71         unsigned int            buf_offsize;
  72         unsigned int            line_size;      /* bytes */
  73         bool                    enabled;
  74 };
  75
  76 struct fimd_context {
  77         struct exynos_drm_subdrv        subdrv;
  78         int                             irq;
  79         struct drm_crtc                 *crtc;
  80         struct clk                      *bus_clk;
  81         struct clk                      *lcd_clk;
  82         struct resource                 *regs_res;
  83         void __iomem                    *regs;
  84         struct fimd_win_data            win_data[WINDOWS_NR];
  85         unsigned int                    clkdiv;
  86         unsigned int                    default_win;
  87         unsigned long                   irq_flags;
  88         u32                             vidcon0;
  89         u32                             vidcon1;
  90         bool                            suspended;
  91         struct mutex                    lock;
  92
  93         struct exynos_drm_panel_info *panel;
  94 };
  95
  96 static bool fimd_display_is_connected(struct device *dev)
  97 {
  98         DRM_DEBUG_KMS("%s\n", __FILE__);
  99
 100         /* TODO. */
 101
 102         return true;
 103 }
 104
 105 static void *fimd_get_panel(struct device *dev)
 106 {
 107         struct fimd_context *ctx = get_fimd_context(dev);
 108
 109         DRM_DEBUG_KMS("%s\n", __FILE__);
 110
 111         return ctx->panel;
 112 }
 113
 114 static int fimd_check_timing(struct device *dev, void *timing)
 115 {
 116         DRM_DEBUG_KMS("%s\n", __FILE__);
 117
 118         /* TODO. */
 119
 120         return 0;
 121 }
 122
 123 static int fimd_display_power_on(struct device *dev, int mode)
 124 {
 125         DRM_DEBUG_KMS("%s\n", __FILE__);
 126
 127         /* TODO */
 128
 129         return 0;
 130 }
 131
 132 static struct exynos_drm_display_ops fimd_display_ops = {
 133         .type = EXYNOS_DISPLAY_TYPE_LCD,
 134         .is_connected = fimd_display_is_connected,
 135         .get_panel = fimd_get_panel,
 136         .check_timing = fimd_check_timing,
 137         .power_on = fimd_display_power_on,
 138 };
 139
 140 static void fimd_dpms(struct device *subdrv_dev, int mode)
 141 {
 142         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 143
 144         DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
 145
 146         mutex_lock(&ctx->lock);
 147
 148         switch (mode) {
 149         case DRM_MODE_DPMS_ON:
 150                 /*
 151                  * enable fimd hardware only if suspended status.
 152                  *
 153                  * P.S. fimd_dpms function would be called at booting time so
 154                  * clk_enable could be called double time.
 155                  */
 156                 if (ctx->suspended)
 157                         pm_runtime_get_sync(subdrv_dev);
 158                 break;
 159         case DRM_MODE_DPMS_STANDBY:
 160         case DRM_MODE_DPMS_SUSPEND:
 161         case DRM_MODE_DPMS_OFF:
 162                 if (!ctx->suspended)
 163                         pm_runtime_put_sync(subdrv_dev);
 164                 break;
 165         default:
 166                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 167                 break;
 168         }
 169
 170         mutex_unlock(&ctx->lock);
 171 }
 172
 173 static void fimd_apply(struct device *subdrv_dev)
 174 {
 175         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 176         struct exynos_drm_manager *mgr = ctx->subdrv.manager;
 177         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 178         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 179         struct fimd_win_data *win_data;
 180         int i;
 181
 182         DRM_DEBUG_KMS("%s\n", __FILE__);
 183
 184         for (i = 0; i < WINDOWS_NR; i++) {
 185                 win_data = &ctx->win_data[i];
 186                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 187                         ovl_ops->commit(subdrv_dev, i);
 188         }
 189
 190         if (mgr_ops && mgr_ops->commit)
 191                 mgr_ops->commit(subdrv_dev);
 192 }
 193
 194 static void fimd_commit(struct device *dev)
 195 {
 196         struct fimd_context *ctx = get_fimd_context(dev);
 197         struct exynos_drm_panel_info *panel = ctx->panel;
 198         struct fb_videomode *timing = &panel->timing;
 199         u32 val;
 200
 201         if (ctx->suspended)
 202                 return;
 203
 204         DRM_DEBUG_KMS("%s\n", __FILE__);
 205
 206         /* setup polarity values from machine code. */
 207         writel(ctx->vidcon1, ctx->regs + VIDCON1);
 208
 209         /* setup vertical timing values. */
 210         val = VIDTCON0_VBPD(timing->upper_margin - 1) |
 211                VIDTCON0_VFPD(timing->lower_margin - 1) |
 212                VIDTCON0_VSPW(timing->vsync_len - 1);
 213         writel(val, ctx->regs + VIDTCON0);
 214
 215         /* setup horizontal timing values.  */
 216         val = VIDTCON1_HBPD(timing->left_margin - 1) |
 217                VIDTCON1_HFPD(timing->right_margin - 1) |
 218                VIDTCON1_HSPW(timing->hsync_len - 1);
 219         writel(val, ctx->regs + VIDTCON1);
 220
 221         /* setup horizontal and vertical display size. */
 222         val = VIDTCON2_LINEVAL(timing->yres - 1) |
 223                VIDTCON2_HOZVAL(timing->xres - 1);
 224         writel(val, ctx->regs + VIDTCON2);
 225
 226         /* setup clock source, clock divider, enable dma. */
 227         val = ctx->vidcon0;
 228         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 229
 230         if (ctx->clkdiv > 1)
 231                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 232         else
 233                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 234
 235         /*
 236          * fields of register with prefix '_F' would be updated
 237          * at vsync(same as dma start)
 238          */
 239         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 240         writel(val, ctx->regs + VIDCON0);
 241 }
 242
 243 static int fimd_enable_vblank(struct device *dev)
 244 {
 245         struct fimd_context *ctx = get_fimd_context(dev);
 246         u32 val;
 247
 248         DRM_DEBUG_KMS("%s\n", __FILE__);
 249
 250         if (ctx->suspended)
 251                 return -EPERM;
 252
 253         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 254                 val = readl(ctx->regs + VIDINTCON0);
 255
 256                 val |= VIDINTCON0_INT_ENABLE;
 257                 val |= VIDINTCON0_INT_FRAME;
 258
 259                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 260                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 261                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 262                 val |= VIDINTCON0_FRAMESEL1_NONE;
 263
 264                 writel(val, ctx->regs + VIDINTCON0);
 265         }
 266
 267         return 0;
 268 }
 269
 270 static void fimd_disable_vblank(struct device *dev)
 271 {
 272         struct fimd_context *ctx = get_fimd_context(dev);
 273         u32 val;
 274
 275         DRM_DEBUG_KMS("%s\n", __FILE__);
 276
 277         if (ctx->suspended)
 278                 return;
 279
 280         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 281                 val = readl(ctx->regs + VIDINTCON0);
 282
 283                 val &= ~VIDINTCON0_INT_FRAME;
 284                 val &= ~VIDINTCON0_INT_ENABLE;
 285
 286                 writel(val, ctx->regs + VIDINTCON0);
 287         }
 288 }
 289
 290 static struct exynos_drm_manager_ops fimd_manager_ops = {
 291         .dpms = fimd_dpms,
 292         .apply = fimd_apply,
 293         .commit = fimd_commit,
 294         .enable_vblank = fimd_enable_vblank,
 295         .disable_vblank = fimd_disable_vblank,
 296 };
 297
 298 static void fimd_win_mode_set(struct device *dev,
 299                               struct exynos_drm_overlay *overlay)
 300 {
 301         struct fimd_context *ctx = get_fimd_context(dev);
 302         struct fimd_win_data *win_data;
 303         int win;
 304         unsigned long offset;
 305
 306         DRM_DEBUG_KMS("%s\n", __FILE__);
 307
 308         if (!overlay) {
 309                 dev_err(dev, "overlay is NULL\n");
 310                 return;
 311         }
 312
 313         win = overlay->zpos;
 314         if (win == DEFAULT_ZPOS)
 315                 win = ctx->default_win;
 316
 317         if (win < 0 || win > WINDOWS_NR)
 318                 return;
 319
 320         offset = overlay->fb_x * (overlay->bpp >> 3);
 321         offset += overlay->fb_y * overlay->fb_pitch;
 322
 323         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n",
 324                 offset, overlay->fb_pitch);
 325
 326         win_data = &ctx->win_data[win];
 327
 328         win_data->offset_x = overlay->crtc_x;
 329         win_data->offset_y = overlay->crtc_y;
 330         win_data->ovl_width = overlay->crtc_width;
 331         win_data->ovl_height = overlay->crtc_height;
 332         win_data->fb_width = overlay->fb_width;
 333         win_data->fb_height = overlay->fb_height;
 334         win_data->fb_pitch = overlay->fb_pitch;
 335         win_data->dma_addr = overlay->dma_addr[0] + offset;
 336         win_data->vaddr = overlay->vaddr[0] + offset;
 337         win_data->bpp = overlay->bpp;
 338         win_data->buf_offsize = overlay->fb_pitch -
 339                 (overlay->fb_width * (overlay->bpp >> 3));
 340         win_data->line_size = overlay->fb_width * (overlay->bpp >> 3);
 341
 342         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 343                         win_data->offset_x, win_data->offset_y);
 344         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 345                         win_data->ovl_width, win_data->ovl_height);
 346         DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
 347                         (unsigned long)win_data->dma_addr,
 348                         (unsigned long)win_data->vaddr);
 349         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 350                         overlay->fb_width, overlay->crtc_width);
 351 }
 352
 353 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 354 {
 355         struct fimd_context *ctx = get_fimd_context(dev);
 356         struct fimd_win_data *win_data = &ctx->win_data[win];
 357         unsigned long val;
 358
 359         DRM_DEBUG_KMS("%s\n", __FILE__);
 360
 361         val = WINCONx_ENWIN;
 362
 363         switch (win_data->bpp) {
 364         case 1:
 365                 val |= WINCON0_BPPMODE_1BPP;
 366                 val |= WINCONx_BITSWP;
 367                 val |= WINCONx_BURSTLEN_4WORD;
 368                 break;
 369         case 2:
 370                 val |= WINCON0_BPPMODE_2BPP;
 371                 val |= WINCONx_BITSWP;
 372                 val |= WINCONx_BURSTLEN_8WORD;
 373                 break;
 374         case 4:
 375                 val |= WINCON0_BPPMODE_4BPP;
 376                 val |= WINCONx_BITSWP;
 377                 val |= WINCONx_BURSTLEN_8WORD;
 378                 break;
 379         case 8:
 380                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 381                 val |= WINCONx_BURSTLEN_8WORD;
 382                 val |= WINCONx_BYTSWP;
 383                 break;
 384         case 16:
 385                 val |= WINCON0_BPPMODE_16BPP_565;
 386                 val |= WINCONx_HAWSWP;
 387                 val |= WINCONx_BURSTLEN_16WORD;
 388                 break;
 389         case 24:
 390                 val |= WINCON0_BPPMODE_24BPP_888;
 391                 val |= WINCONx_WSWP;
 392                 val |= WINCONx_BURSTLEN_16WORD;
 393                 break;
 394         case 32:
 395                 val |= WINCON1_BPPMODE_28BPP_A4888
 396                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 397                 val |= WINCONx_WSWP;
 398                 val |= WINCONx_BURSTLEN_16WORD;
 399                 break;
 400         default:
 401                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 402
 403                 val |= WINCON0_BPPMODE_24BPP_888;
 404                 val |= WINCONx_WSWP;
 405                 val |= WINCONx_BURSTLEN_16WORD;
 406                 break;
 407         }
 408
 409         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 410
 411         writel(val, ctx->regs + WINCON(win));
 412 }
 413
 414 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 415 {
 416         struct fimd_context *ctx = get_fimd_context(dev);
 417         unsigned int keycon0 = 0, keycon1 = 0;
 418
 419         DRM_DEBUG_KMS("%s\n", __FILE__);
 420
 421         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 422                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 423
 424         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 425
 426         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 427         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 428 }
 429
 430 static void fimd_win_commit(struct device *dev, int zpos)
 431 {
 432         struct fimd_context *ctx = get_fimd_context(dev);
 433         struct fimd_win_data *win_data;
 434         int win = zpos;
 435         unsigned long val, alpha, size;
 436
 437         DRM_DEBUG_KMS("%s\n", __FILE__);
 438
 439         if (ctx->suspended)
 440                 return;
 441
 442         if (win == DEFAULT_ZPOS)
 443                 win = ctx->default_win;
 444
 445         if (win < 0 || win > WINDOWS_NR)
 446                 return;
 447
 448         win_data = &ctx->win_data[win];
 449
 450         /*
 451          * SHADOWCON register is used for enabling timing.
 452          *
 453          * for example, once only width value of a register is set,
 454          * if the dma is started then fimd hardware could malfunction so
 455          * with protect window setting, the register fields with prefix '_F'
 456          * wouldn't be updated at vsync also but updated once unprotect window
 457          * is set.
 458          */
 459
 460         /* protect windows */
 461         val = readl(ctx->regs + SHADOWCON);
 462         val |= SHADOWCON_WINx_PROTECT(win);
 463         writel(val, ctx->regs + SHADOWCON);
 464
 465         /* buffer start address */
 466         val = (unsigned long)win_data->dma_addr;
 467         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 468
 469         /* buffer end address */
 470         size = win_data->fb_height * win_data->fb_pitch;
 471         val = (unsigned long)(win_data->dma_addr + size);
 472         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 473
 474         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 475                         (unsigned long)win_data->dma_addr, val, size);
 476         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 477                         win_data->ovl_width, win_data->ovl_height);
 478
 479         /* buffer size */
 480         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 481                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
 482         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 483
 484         /* OSD position */
 485         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 486                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
 487         writel(val, ctx->regs + VIDOSD_A(win));
 488
 489         val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
 490                                         win_data->ovl_width - 1) |
 491                 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
 492                                         win_data->ovl_height - 1);
 493         writel(val, ctx->regs + VIDOSD_B(win));
 494
 495         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 496                         win_data->offset_x, win_data->offset_y,
 497                         win_data->offset_x + win_data->ovl_width - 1,
 498                         win_data->offset_y + win_data->ovl_height - 1);
 499
 500         /* hardware window 0 doesn't support alpha channel. */
 501         if (win != 0) {
 502                 /* OSD alpha */
 503                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 504                         VIDISD14C_ALPHA1_G(0xf) |
 505                         VIDISD14C_ALPHA1_B(0xf);
 506
 507                 writel(alpha, ctx->regs + VIDOSD_C(win));
 508         }
 509
 510         /* OSD size */
 511         if (win != 3 && win != 4) {
 512                 u32 offset = VIDOSD_D(win);
 513                 if (win == 0)
 514                         offset = VIDOSD_C_SIZE_W0;
 515                 val = win_data->ovl_width * win_data->ovl_height;
 516                 writel(val, ctx->regs + offset);
 517
 518                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 519         }
 520
 521         fimd_win_set_pixfmt(dev, win);
 522
 523         /* hardware window 0 doesn't support color key. */
 524         if (win != 0)
 525                 fimd_win_set_colkey(dev, win);
 526
 527         /* wincon */
 528         val = readl(ctx->regs + WINCON(win));
 529         val |= WINCONx_ENWIN;
 530         writel(val, ctx->regs + WINCON(win));
 531
 532         /* Enable DMA channel and unprotect windows */
 533         val = readl(ctx->regs + SHADOWCON);
 534         val |= SHADOWCON_CHx_ENABLE(win);
 535         val &= ~SHADOWCON_WINx_PROTECT(win);
 536         writel(val, ctx->regs + SHADOWCON);
 537
 538         win_data->enabled = true;
 539 }
 540
 541 static void fimd_win_disable(struct device *dev, int zpos)
 542 {
 543         struct fimd_context *ctx = get_fimd_context(dev);
 544         struct fimd_win_data *win_data;
 545         int win = zpos;
 546         u32 val;
 547
 548         DRM_DEBUG_KMS("%s\n", __FILE__);
 549
 550         if (win == DEFAULT_ZPOS)
 551                 win = ctx->default_win;
 552
 553         if (win < 0 || win > WINDOWS_NR)
 554                 return;
 555
 556         win_data = &ctx->win_data[win];
 557
 558         /* protect windows */
 559         val = readl(ctx->regs + SHADOWCON);
 560         val |= SHADOWCON_WINx_PROTECT(win);
 561         writel(val, ctx->regs + SHADOWCON);
 562
 563         /* wincon */
 564         val = readl(ctx->regs + WINCON(win));
 565         val &= ~WINCONx_ENWIN;
 566         writel(val, ctx->regs + WINCON(win));
 567
 568         /* unprotect windows */
 569         val = readl(ctx->regs + SHADOWCON);
 570         val &= ~SHADOWCON_CHx_ENABLE(win);
 571         val &= ~SHADOWCON_WINx_PROTECT(win);
 572         writel(val, ctx->regs + SHADOWCON);
 573
 574         win_data->enabled = false;
 575 }
 576
 577 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 578         .mode_set = fimd_win_mode_set,
 579         .commit = fimd_win_commit,
 580         .disable = fimd_win_disable,
 581 };
 582
 583 static struct exynos_drm_manager fimd_manager = {
 584         .pipe           = -1,
 585         .ops            = &fimd_manager_ops,
 586         .overlay_ops    = &fimd_overlay_ops,
 587         .display_ops    = &fimd_display_ops,
 588 };
 589
 590 static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc)
 591 {
 592         struct exynos_drm_private *dev_priv = drm_dev->dev_private;
 593         struct drm_pending_vblank_event *e, *t;
 594         struct timeval now;
 595         unsigned long flags;
 596         bool is_checked = false;
 597
 598         spin_lock_irqsave(&drm_dev->event_lock, flags);
 599
 600         list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list,
 601                         base.link) {
 602                 /* if event's pipe isn't same as crtc then ignore it. */
 603                 if (crtc != e->pipe)
 604                         continue;
 605
 606                 is_checked = true;
 607
 608                 do_gettimeofday(&now);
 609                 e->event.sequence = 0;
 610                 e->event.tv_sec = now.tv_sec;
 611                 e->event.tv_usec = now.tv_usec;
 612
 613                 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
 614                 wake_up_interruptible(&e->base.file_priv->event_wait);
 615         }
 616
 617         if (is_checked) {
 618                 /*
 619                  * call drm_vblank_put only in case that drm_vblank_get was
 620                  * called.
 621                  */
 622                 if (atomic_read(&drm_dev->vblank_refcount[crtc]) > 0)
 623                         drm_vblank_put(drm_dev, crtc);
 624
 625                 /*
 626                  * don't off vblank if vblank_disable_allowed is 1,
 627                  * because vblank would be off by timer handler.
 628                  */
 629                 if (!drm_dev->vblank_disable_allowed)
 630                         drm_vblank_off(drm_dev, crtc);
 631         }
 632
 633         /* set wait vsync event to zero and wake up queue. */
 634         atomic_set(&dev_priv->wait_vsync_event, 0);
 635         DRM_WAKEUP(&dev_priv->wait_vsync_queue);
 636
 637         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 638 }
 639
 640 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 641 {
 642         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 643         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 644         struct drm_device *drm_dev = subdrv->drm_dev;
 645         struct exynos_drm_manager *manager = subdrv->manager;
 646         u32 val;
 647
 648         val = readl(ctx->regs + VIDINTCON1);
 649
 650         if (val & VIDINTCON1_INT_FRAME)
 651                 /* VSYNC interrupt */
 652                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 653
 654         /* check the crtc is detached already from encoder */
 655         if (manager->pipe < 0)
 656                 goto out;
 657
 658         drm_handle_vblank(drm_dev, manager->pipe);
 659         fimd_finish_pageflip(drm_dev, manager->pipe);
 660
 661 out:
 662         return IRQ_HANDLED;
 663 }
 664
 665 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 666 {
 667         DRM_DEBUG_KMS("%s\n", __FILE__);
 668
 669         /*
 670          * enable drm irq mode.
 671          * - with irq_enabled = 1, we can use the vblank feature.
 672          *
 673          * P.S. note that we wouldn't use drm irq handler but
 674          *      just specific driver own one instead because
 675          *      drm framework supports only one irq handler.
 676          */
 677         drm_dev->irq_enabled = 1;
 678
 679         /*
 680          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 681          * by drm timer once a current process gives up ownership of
 682          * vblank event.(after drm_vblank_put function is called)
 683          */
 684         drm_dev->vblank_disable_allowed = 1;
 685
 686         return 0;
 687 }
 688
 689 static void fimd_subdrv_remove(struct drm_device *drm_dev)
 690 {
 691         DRM_DEBUG_KMS("%s\n", __FILE__);
 692
 693         /* TODO. */
 694 }
 695
 696 static int fimd_calc_clkdiv(struct fimd_context *ctx,
 697                             struct fb_videomode *timing)
 698 {
 699         unsigned long clk = clk_get_rate(ctx->lcd_clk);
 700         u32 retrace;
 701         u32 clkdiv;
 702         u32 best_framerate = 0;
 703         u32 framerate;
 704
 705         DRM_DEBUG_KMS("%s\n", __FILE__);
 706
 707         retrace = timing->left_margin + timing->hsync_len +
 708                                 timing->right_margin + timing->xres;
 709         retrace *= timing->upper_margin + timing->vsync_len +
 710                                 timing->lower_margin + timing->yres;
 711
 712         /* default framerate is 60Hz */
 713         if (!timing->refresh)
 714                 timing->refresh = 60;
 715
 716         clk /= retrace;
 717
 718         for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
 719                 int tmp;
 720
 721                 /* get best framerate */
 722                 framerate = clk / clkdiv;
 723                 tmp = timing->refresh - framerate;
 724                 if (tmp < 0) {
 725                         best_framerate = framerate;
 726                         continue;
 727                 } else {
 728                         if (!best_framerate)
 729                                 best_framerate = framerate;
 730                         else if (tmp < (best_framerate - framerate))
 731                                 best_framerate = framerate;
 732                         break;
 733                 }
 734         }
 735
 736         return clkdiv;
 737 }
 738
 739 static void fimd_clear_win(struct fimd_context *ctx, int win)
 740 {
 741         u32 val;
 742
 743         DRM_DEBUG_KMS("%s\n", __FILE__);
 744
 745         writel(0, ctx->regs + WINCON(win));
 746         writel(0, ctx->regs + VIDOSD_A(win));
 747         writel(0, ctx->regs + VIDOSD_B(win));
 748         writel(0, ctx->regs + VIDOSD_C(win));
 749
 750         if (win == 1 || win == 2)
 751                 writel(0, ctx->regs + VIDOSD_D(win));
 752
 753         val = readl(ctx->regs + SHADOWCON);
 754         val &= ~SHADOWCON_WINx_PROTECT(win);
 755         writel(val, ctx->regs + SHADOWCON);
 756 }
 757
 758 static int fimd_power_on(struct fimd_context *ctx, bool enable)
 759 {
 760         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 761         struct device *dev = subdrv->dev;
 762
 763         DRM_DEBUG_KMS("%s\n", __FILE__);
 764
 765         if (enable != false && enable != true)
 766                 return -EINVAL;
 767
 768         if (enable) {
 769                 int ret;
 770
 771                 ret = clk_enable(ctx->bus_clk);
 772                 if (ret < 0)
 773                         return ret;
 774
 775                 ret = clk_enable(ctx->lcd_clk);
 776                 if  (ret < 0) {
 777                         clk_disable(ctx->bus_clk);
 778                         return ret;
 779                 }
 780
 781                 ctx->suspended = false;
 782
 783                 /* if vblank was enabled status, enable it again. */
 784                 if (test_and_clear_bit(0, &ctx->irq_flags))
 785                         fimd_enable_vblank(dev);
 786
 787                 fimd_apply(dev);
 788         } else {
 789                 clk_disable(ctx->lcd_clk);
 790                 clk_disable(ctx->bus_clk);
 791
 792                 ctx->suspended = true;
 793         }
 794
 795         return 0;
 796 }
 797
 798 #ifdef CONFIG_EXYNOS_IOMMU
 799 static int iommu_init(struct platform_device *pdev)
 800 {
 801         struct platform_device *pds;
 802
 803         pds = find_sysmmu_dt(pdev, "sysmmu");
 804         if (pds==NULL) {
 805                 printk(KERN_ERR "No sysmmu found\n");
 806                 return -1;
 807         }
 808
 809         platform_set_sysmmu(&pds->dev, &pdev->dev);
 810         exynos_drm_common_mapping = s5p_create_iommu_mapping(&pdev->dev,
 811                                         0x20000000, SZ_256M, 4,
 812                                         exynos_drm_common_mapping);
 813
 814         if (!exynos_drm_common_mapping) {
 815                 printk(KERN_ERR "IOMMU mapping not created\n");
 816                 return -1;
 817         }
 818
 819         return 0;
 820 }
 821 #endif
 822 static int __devinit fimd_probe(struct platform_device *pdev)
 823 {
 824         struct device *dev = &pdev->dev;
 825         struct fimd_context *ctx;
 826         struct exynos_drm_subdrv *subdrv;
 827         struct exynos_drm_fimd_pdata *pdata;
 828         struct exynos_drm_panel_info *panel;
 829         struct resource *res;
 830         struct clk *clk_parent;
 831         int win;
 832         int ret = -EINVAL;
 833
 834 #ifdef CONFIG_EXYNOS_IOMMU
 835         ret = iommu_init(pdev);
 836         if (ret < 0) {
 837                 dev_err(dev, "failed to initialize IOMMU\n");
 838                 return -ENODEV;
 839         }
 840 #endif
 841         DRM_DEBUG_KMS("%s\n", __FILE__);
 842
 843         pdata = pdev->dev.platform_data;
 844         if (!pdata) {
 845                 dev_err(dev, "no platform data specified\n");
 846                 return -EINVAL;
 847         }
 848
 849         panel = &pdata->panel;
 850         if (!panel) {
 851                 dev_err(dev, "panel is null.\n");
 852                 return -EINVAL;
 853         }
 854
 855         ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
 856         if (!ctx)
 857                 return -ENOMEM;
 858
 859         ctx->bus_clk = clk_get(dev, "fimd");
 860         if (IS_ERR(ctx->bus_clk)) {
 861                 dev_err(dev, "failed to get bus clock\n");
 862                 ret = PTR_ERR(ctx->bus_clk);
 863                 goto err_clk_get;
 864         }
 865
 866         ctx->lcd_clk = clk_get(dev, "sclk_fimd");
 867         if (IS_ERR(ctx->lcd_clk)) {
 868                 dev_err(dev, "failed to get lcd clock\n");
 869                 ret = PTR_ERR(ctx->lcd_clk);
 870                 goto err_bus_clk;
 871         }
 872
 873         clk_parent = clk_get(NULL, "mout_mpll_user");
 874         if (IS_ERR(clk_parent)) {
 875                 ret = PTR_ERR(clk_parent);
 876                 goto err_clk;
 877         }
 878
 879         if (clk_set_parent(ctx->lcd_clk, clk_parent)) {
 880                 ret = PTR_ERR(ctx->lcd_clk);
 881                 goto err_clk;
 882         }
 883
 884         if (clk_set_rate(ctx->lcd_clk, pdata->clock_rate)) {
 885                 ret = PTR_ERR(ctx->lcd_clk);
 886                 goto err_clk;
 887         }
 888
 889         clk_put(clk_parent);
 890
 891         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 892         if (!res) {
 893                 dev_err(dev, "failed to find registers\n");
 894                 ret = -ENOENT;
 895                 goto err_clk;
 896         }
 897
 898         ctx->regs_res = request_mem_region(res->start, resource_size(res),
 899                                            dev_name(dev));
 900         if (!ctx->regs_res) {
 901                 dev_err(dev, "failed to claim register region\n");
 902                 ret = -ENOENT;
 903                 goto err_clk;
 904         }
 905
 906         ctx->regs = ioremap(res->start, resource_size(res));
 907         if (!ctx->regs) {
 908                 dev_err(dev, "failed to map registers\n");
 909                 ret = -ENXIO;
 910                 goto err_req_region_io;
 911         }
 912
 913         res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 914         if (!res) {
 915                 dev_err(dev, "irq request failed.\n");
 916                 goto err_req_region_irq;
 917         }
 918
 919         ctx->irq = res->start;
 920
 921         ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
 922         if (ret < 0) {
 923                 dev_err(dev, "irq request failed.\n");
 924                 goto err_req_irq;
 925         }
 926
 927         ctx->vidcon0 = pdata->vidcon0;
 928         ctx->vidcon1 = pdata->vidcon1;
 929         ctx->default_win = pdata->default_win;
 930         ctx->panel = panel;
 931
 932         subdrv = &ctx->subdrv;
 933
 934         subdrv->dev = dev;
 935         subdrv->manager = &fimd_manager;
 936         subdrv->probe = fimd_subdrv_probe;
 937         subdrv->remove = fimd_subdrv_remove;
 938
 939         mutex_init(&ctx->lock);
 940
 941         platform_set_drvdata(pdev, ctx);
 942
 943         pm_runtime_enable(dev);
 944         pm_runtime_get_sync(dev);
 945
 946         ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
 947         panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
 948
 949         DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
 950                         panel->timing.pixclock, ctx->clkdiv);
 951
 952         for (win = 0; win < WINDOWS_NR; win++)
 953                 fimd_clear_win(ctx, win);
 954
 955         if (pdata->panel_type == DP_LCD)
 956                 writel(DPCLKCON_ENABLE, ctx->regs + DPCLKCON);
 957
 958         exynos_drm_subdrv_register(subdrv);
 959
 960         return 0;
 961
 962 err_req_irq:
 963 err_req_region_irq:
 964         iounmap(ctx->regs);
 965
 966 err_req_region_io:
 967         release_resource(ctx->regs_res);
 968         kfree(ctx->regs_res);
 969
 970 err_clk:
 971         clk_disable(ctx->lcd_clk);
 972         clk_put(ctx->lcd_clk);
 973
 974 err_bus_clk:
 975         clk_disable(ctx->bus_clk);
 976         clk_put(ctx->bus_clk);
 977
 978 err_clk_get:
 979         kfree(ctx);
 980         return ret;
 981 }
 982
 983 static int __devexit fimd_remove(struct platform_device *pdev)
 984 {
 985         struct device *dev = &pdev->dev;
 986         struct fimd_context *ctx = platform_get_drvdata(pdev);
 987
 988         DRM_DEBUG_KMS("%s\n", __FILE__);
 989
 990         exynos_drm_subdrv_unregister(&ctx->subdrv);
 991
 992         if (ctx->suspended)
 993                 goto out;
 994
 995         clk_disable(ctx->lcd_clk);
 996         clk_disable(ctx->bus_clk);
 997
 998         pm_runtime_set_suspended(dev);
 999         pm_runtime_put_sync(dev);
1000
1001 out:
1002         pm_runtime_disable(dev);
1003
1004         clk_put(ctx->lcd_clk);
1005         clk_put(ctx->bus_clk);
1006
1007         iounmap(ctx->regs);
1008         release_resource(ctx->regs_res);
1009         kfree(ctx->regs_res);
1010         free_irq(ctx->irq, ctx);
1011
1012         kfree(ctx);
1013
1014         return 0;
1015 }
1016
1017 #ifdef CONFIG_PM_SLEEP
1018 static int fimd_suspend(struct device *dev)
1019 {
1020         struct fimd_context *ctx = get_fimd_context(dev);
1021
1022         if (pm_runtime_suspended(dev))
1023                 return 0;
1024
1025         /*
1026          * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1027          * called here, an error would be returned by that interface
1028          * because the usage_count of pm runtime is more than 1.
1029          */
1030         return fimd_power_on(ctx, false);
1031 }
1032
1033 static int fimd_resume(struct device *dev)
1034 {
1035         struct fimd_context *ctx = get_fimd_context(dev);
1036
1037         /*
1038          * if entered to sleep when lcd panel was on, the usage_count
1039          * of pm runtime would still be 1 so in this case, fimd driver
1040          * should be on directly not drawing on pm runtime interface.
1041          */
1042         if (!pm_runtime_suspended(dev))
1043                 return fimd_power_on(ctx, true);
1044
1045         return 0;
1046 }
1047 #endif
1048
1049 #ifdef CONFIG_PM_RUNTIME
1050 static int fimd_runtime_suspend(struct device *dev)
1051 {
1052         struct fimd_context *ctx = get_fimd_context(dev);
1053
1054         DRM_DEBUG_KMS("%s\n", __FILE__);
1055
1056         return fimd_power_on(ctx, false);
1057 }
1058
1059 static int fimd_runtime_resume(struct device *dev)
1060 {
1061         struct fimd_context *ctx = get_fimd_context(dev);
1062
1063         DRM_DEBUG_KMS("%s\n", __FILE__);
1064
1065         return fimd_power_on(ctx, true);
1066 }
1067 #endif
1068
1069 static struct platform_device_id exynos_drm_driver_ids[] = {
1070         {
1071                 .name           = "exynos4-fb",
1072         }, {
1073                 .name           = "exynos5-fb",
1074         },
1075         {},
1076 };
1077 MODULE_DEVICE_TABLE(platform, exynos_drm_driver_ids);
1078
1079 static const struct dev_pm_ops fimd_pm_ops = {
1080         SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1081         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1082 };
1083
1084 struct platform_driver fimd_driver = {
1085         .probe          = fimd_probe,
1086         .remove         = __devexit_p(fimd_remove),
1087         .id_table       = exynos_drm_driver_ids,
1088         .driver         = {
1089                 .name   = "exynos-drm-fimd",
1090                 .owner  = THIS_MODULE,
1091                 .pm     = &fimd_pm_ops,
1092         },
1093 };