3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/clk.h>
20 #include <linux/pm_runtime.h>
22 #include <drm/exynos_drm.h>
23 #include <plat/regs-fb-v4.h>
25 #include "exynos_drm_drv.h"
26 #include "exynos_drm_crtc.h"
27 #include "exynos_drm_fbdev.h"
30 * FIMD is stand for Fully Interactive Mobile Display and
31 * as a display controller, it transfers contents drawn on memory
32 * to a LCD Panel through Display Interfaces such as RGB or
36 /* position control register for hardware window 0, 2 ~ 4.*/
37 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
38 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
39 /* size control register for hardware window 0. */
40 #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08)
41 /* alpha control register for hardware window 1 ~ 4. */
42 #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16)
43 /* size control register for hardware window 1 ~ 4. */
44 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
46 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
47 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
48 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
50 /* color key control register for hardware window 1 ~ 4. */
51 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8))
52 /* color key value register for hardware window 1 ~ 4. */
53 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8))
55 /* FIMD has totally five hardware windows. */
58 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
60 struct fimd_win_data {
61 unsigned int offset_x;
62 unsigned int offset_y;
63 unsigned int ovl_width;
64 unsigned int ovl_height;
65 unsigned int fb_width;
66 unsigned int fb_height;
67 unsigned int fb_pitch;
71 unsigned int buf_offsize;
72 unsigned int line_size; /* bytes */
77 struct exynos_drm_subdrv subdrv;
79 struct drm_crtc *crtc;
82 struct resource *regs_res;
84 void __iomem *regs_mie;
85 struct fimd_win_data win_data[WINDOWS_NR];
86 unsigned int clkdiv[MAX_NR_PANELS];
87 unsigned int default_win;
88 unsigned long irq_flags;
95 struct exynos_drm_panel_info *panel;
98 static bool fimd_display_is_connected(struct device *dev)
100 DRM_DEBUG_KMS("%s\n", __FILE__);
107 static void *fimd_get_panel(struct device *dev)
109 struct fimd_context *ctx = get_fimd_context(dev);
111 DRM_DEBUG_KMS("%s\n", __FILE__);
116 static int fimd_check_timing(struct device *dev, void *timing)
118 struct fimd_context *ctx = get_fimd_context(dev);
119 struct fb_videomode *check_timing = timing;
122 DRM_DEBUG_KMS("%s\n", __FILE__);
124 for (i = 0;i< MAX_NR_PANELS;i++) {
125 if (ctx->panel[i].timing.xres == -1 &&
126 ctx->panel[i].timing.yres == -1)
129 if (ctx->panel[i].timing.xres == check_timing->xres &&
130 ctx->panel[i].timing.yres == check_timing->yres &&
131 ctx->panel[i].timing.refresh == check_timing->refresh
139 static int fimd_power_on(struct fimd_context *ctx, bool enable);
141 static int fimd_display_power_on(struct device *dev, int mode)
143 struct fimd_context *ctx = get_fimd_context(dev);
146 DRM_DEBUG_KMS("%s\n", __FILE__);
149 case DRM_MODE_DPMS_ON:
150 case DRM_MODE_DPMS_STANDBY:
153 case DRM_MODE_DPMS_SUSPEND:
154 case DRM_MODE_DPMS_OFF:
158 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
162 fimd_power_on(ctx, enable);
167 static struct exynos_drm_display_ops fimd_display_ops = {
168 .type = EXYNOS_DISPLAY_TYPE_LCD,
169 .is_connected = fimd_display_is_connected,
170 .get_panel = fimd_get_panel,
171 .check_timing = fimd_check_timing,
172 .power_on = fimd_display_power_on,
175 static void fimd_apply(struct device *subdrv_dev)
177 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
178 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
179 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
180 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
181 struct fimd_win_data *win_data;
184 DRM_DEBUG_KMS("%s\n", __FILE__);
186 for (i = 0; i < WINDOWS_NR; i++) {
187 win_data = &ctx->win_data[i];
188 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
189 ovl_ops->commit(subdrv_dev, i);
192 if (mgr_ops && mgr_ops->commit)
193 mgr_ops->commit(subdrv_dev);
196 static void fimd_commit(struct device *dev)
198 struct fimd_context *ctx = get_fimd_context(dev);
199 struct exynos_drm_panel_info *panel = &ctx->panel[ctx->idx];
200 struct fb_videomode *timing = &panel->timing;
206 DRM_DEBUG_KMS("%s\n", __FILE__);
208 /* setup polarity values from machine code. */
209 writel(ctx->vidcon1, ctx->regs + VIDCON1);
211 /* setup vertical timing values. */
212 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
213 VIDTCON0_VFPD(timing->lower_margin - 1) |
214 VIDTCON0_VSPW(timing->vsync_len - 1);
215 writel(val, ctx->regs + VIDTCON0);
217 /* setup horizontal timing values. */
218 val = VIDTCON1_HBPD(timing->left_margin - 1) |
219 VIDTCON1_HFPD(timing->right_margin - 1) |
220 VIDTCON1_HSPW(timing->hsync_len - 1);
221 writel(val, ctx->regs + VIDTCON1);
223 /* setup horizontal and vertical display size. */
224 val = VIDTCON2_LINEVAL(timing->yres - 1) |
225 VIDTCON2_HOZVAL(timing->xres - 1);
226 writel(val, ctx->regs + VIDTCON2);
228 /* setup clock source, clock divider, enable dma. */
230 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
232 if (ctx->clkdiv[ctx->idx] > 1)
233 val |= VIDCON0_CLKVAL_F(ctx->clkdiv[ctx->idx] - 1) | VIDCON0_CLKDIR;
235 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
238 * fields of register with prefix '_F' would be updated
239 * at vsync(same as dma start)
241 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
242 writel(val, ctx->regs + VIDCON0);
245 static int fimd_enable_vblank(struct device *dev)
247 struct fimd_context *ctx = get_fimd_context(dev);
250 DRM_DEBUG_KMS("%s\n", __FILE__);
255 if (!test_and_set_bit(0, &ctx->irq_flags)) {
256 val = readl(ctx->regs + VIDINTCON0);
258 val |= VIDINTCON0_INT_ENABLE;
259 val |= VIDINTCON0_INT_FRAME;
261 val &= ~VIDINTCON0_FRAMESEL0_MASK;
262 val |= VIDINTCON0_FRAMESEL0_VSYNC;
263 val &= ~VIDINTCON0_FRAMESEL1_MASK;
264 val |= VIDINTCON0_FRAMESEL1_NONE;
266 writel(val, ctx->regs + VIDINTCON0);
272 static void fimd_disable_vblank(struct device *dev)
274 struct fimd_context *ctx = get_fimd_context(dev);
277 DRM_DEBUG_KMS("%s\n", __FILE__);
282 if (test_and_clear_bit(0, &ctx->irq_flags)) {
283 val = readl(ctx->regs + VIDINTCON0);
285 val &= ~VIDINTCON0_INT_FRAME;
286 val &= ~VIDINTCON0_INT_ENABLE;
288 writel(val, ctx->regs + VIDINTCON0);
292 static struct exynos_drm_manager_ops fimd_manager_ops = {
294 .commit = fimd_commit,
295 .enable_vblank = fimd_enable_vblank,
296 .disable_vblank = fimd_disable_vblank,
299 static void fimd_win_mode_set(struct device *dev,
300 struct exynos_drm_overlay *overlay)
302 struct fimd_context *ctx = get_fimd_context(dev);
303 struct fimd_win_data *win_data;
305 unsigned long offset;
307 DRM_DEBUG_KMS("%s\n", __FILE__);
310 dev_err(dev, "overlay is NULL\n");
315 if (win == DEFAULT_ZPOS)
316 win = ctx->default_win;
318 if (win < 0 || win > WINDOWS_NR)
321 if(win == ctx->default_win) {
322 for(ctx->idx = 0;ctx->idx < MAX_NR_PANELS;ctx->idx++) {
323 if (ctx->panel[ctx->idx].timing.xres == -1 &&
324 ctx->panel[ctx->idx].timing.yres == -1) {
325 DRM_ERROR("Invalid panel parameters");
326 ctx->idx = 0; /* Reset to first panel index*/
329 if (ctx->panel[ctx->idx].timing.xres == overlay->fb_width &&
330 ctx->panel[ctx->idx].timing.yres == overlay->fb_height)
335 offset = overlay->fb_x * (overlay->bpp >> 3);
336 offset += overlay->fb_y * overlay->fb_pitch;
338 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n",
339 offset, overlay->fb_pitch);
341 win_data = &ctx->win_data[win];
343 win_data->offset_x = overlay->crtc_x;
344 win_data->offset_y = overlay->crtc_y;
345 win_data->ovl_width = overlay->crtc_width;
346 win_data->ovl_height = overlay->crtc_height;
347 win_data->fb_width = overlay->fb_width;
348 win_data->fb_height = overlay->fb_height;
349 win_data->fb_pitch = overlay->fb_pitch;
350 win_data->dma_addr = overlay->dma_addr[0] + offset;
351 win_data->vaddr = overlay->vaddr[0] + offset;
352 win_data->bpp = overlay->bpp;
353 win_data->buf_offsize = overlay->fb_pitch -
354 (overlay->fb_width * (overlay->bpp >> 3));
355 win_data->line_size = overlay->fb_width * (overlay->bpp >> 3);
357 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
358 win_data->offset_x, win_data->offset_y);
359 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
360 win_data->ovl_width, win_data->ovl_height);
361 DRM_DEBUG_KMS("paddr = 0x%lx, vaddr = 0x%lx\n",
362 (unsigned long)win_data->dma_addr,
363 (unsigned long)win_data->vaddr);
364 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
365 overlay->fb_width, overlay->crtc_width);
368 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
370 struct fimd_context *ctx = get_fimd_context(dev);
371 struct fimd_win_data *win_data = &ctx->win_data[win];
375 DRM_DEBUG_KMS("%s\n", __FILE__);
379 switch (win_data->bpp) {
381 val |= WINCON0_BPPMODE_1BPP;
382 val |= WINCONx_BITSWP;
383 bytes = win_data->fb_width >> 3;
386 val |= WINCON0_BPPMODE_2BPP;
387 val |= WINCONx_BITSWP;
388 bytes = win_data->fb_width >> 2;
391 val |= WINCON0_BPPMODE_4BPP;
392 val |= WINCONx_BITSWP;
393 bytes = win_data->fb_width >> 1;
396 val |= WINCON0_BPPMODE_8BPP_PALETTE;
397 val |= WINCONx_BYTSWP;
398 bytes = win_data->fb_width;
401 val |= WINCON0_BPPMODE_16BPP_565;
402 val |= WINCONx_HAWSWP;
403 bytes = win_data->fb_width << 1;
406 val |= WINCON0_BPPMODE_24BPP_888;
408 bytes = win_data->fb_width * 3;
411 val |= WINCON1_BPPMODE_28BPP_A4888
412 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
414 bytes = win_data->fb_width << 2;
417 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
418 bytes = win_data->fb_width * 3;
419 val |= WINCON0_BPPMODE_24BPP_888;
425 * Adjust the burst size based on the number of bytes to be read.
426 * Each WORD of the BURST is 8 bytes long. There are 3 BURST sizes
428 * WINCONx_BURSTLEN_4WORD = 32 bytes
429 * WINCONx_BURSTLEN_8WORD = 64 bytes
430 * WINCONx_BURSTLEN_16WORD = 128 bytes
432 if (win_data->fb_width <= 64)
433 val |= WINCONx_BURSTLEN_4WORD;
435 val |= WINCONx_BURSTLEN_16WORD;
437 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
439 writel(val, ctx->regs + WINCON(win));
442 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
444 struct fimd_context *ctx = get_fimd_context(dev);
445 unsigned int keycon0 = 0, keycon1 = 0;
447 DRM_DEBUG_KMS("%s\n", __FILE__);
449 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
450 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
452 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
454 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
455 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
458 static void mie_set_6bit_dithering(struct fimd_context *ctx)
460 struct fb_videomode *timing = &ctx->panel->timing;
464 writel(MIE_HRESOL(timing->xres) | MIE_VRESOL(timing->yres) |
465 MIE_MODE_UI, ctx->regs_mie + MIE_CTRL1);
467 writel(MIE_WINHADDR0(0) | MIE_WINHADDR1(timing->xres),
468 ctx->regs_mie + MIE_WINHADDR);
469 writel(MIE_WINVADDR0(0) | MIE_WINVADDR1(timing->yres),
470 ctx->regs_mie + MIE_WINVADDR);
472 val = (timing->xres + timing->left_margin +
473 timing->right_margin + timing->hsync_len) *
474 (timing->yres + timing->upper_margin +
475 timing->lower_margin + timing->vsync_len) /
477 writel(PWMCLKCNT(val), ctx->regs_mie + MIE_PWMCLKCNT);
479 writel((MIE_VBPD(timing->upper_margin)) |
480 MIE_VFPD(timing->lower_margin) |
481 MIE_VSPW(timing->vsync_len), ctx->regs_mie + MIE_PWMVIDTCON1);
483 writel(MIE_HBPD(timing->left_margin) |
484 MIE_HFPD(timing->right_margin) |
485 MIE_HSPW(timing->hsync_len), ctx->regs_mie + MIE_PWMVIDTCON2);
487 writel(MIE_DITHCON_EN | MIE_RGB6MODE,
488 ctx->regs_mie + MIE_AUXCON);
490 /* Bypass MIE image brightness enhancement */
491 for (i = 0; i <= 0x30; i += 4) {
492 writel(0, ctx->regs_mie + 0x100 + i);
493 writel(0, ctx->regs_mie + 0x200 + i);
497 static void fimd_win_commit(struct device *dev, int zpos)
499 struct fimd_context *ctx = get_fimd_context(dev);
500 struct fimd_win_data *win_data;
502 unsigned long val, alpha, size;
504 DRM_DEBUG_KMS("%s\n", __FILE__);
509 if (win == DEFAULT_ZPOS)
510 win = ctx->default_win;
512 if (win < 0 || win > WINDOWS_NR)
515 win_data = &ctx->win_data[win];
518 * SHADOWCON register is used for enabling timing.
520 * for example, once only width value of a register is set,
521 * if the dma is started then fimd hardware could malfunction so
522 * with protect window setting, the register fields with prefix '_F'
523 * wouldn't be updated at vsync also but updated once unprotect window
527 /* protect windows */
528 val = readl(ctx->regs + SHADOWCON);
529 val |= SHADOWCON_WINx_PROTECT(win);
530 writel(val, ctx->regs + SHADOWCON);
532 /* buffer start address */
533 val = (unsigned long)win_data->dma_addr;
534 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
536 /* buffer end address */
537 size = win_data->fb_height * win_data->fb_pitch;
538 val = (unsigned long)(win_data->dma_addr + size);
539 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
541 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
542 (unsigned long)win_data->dma_addr, val, size);
543 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
544 win_data->ovl_width, win_data->ovl_height);
547 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
548 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size);
549 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
552 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
553 VIDOSDxA_TOPLEFT_Y(win_data->offset_y);
554 writel(val, ctx->regs + VIDOSD_A(win));
556 val = VIDOSDxB_BOTRIGHT_X(win_data->offset_x +
557 win_data->ovl_width - 1) |
558 VIDOSDxB_BOTRIGHT_Y(win_data->offset_y +
559 win_data->ovl_height - 1);
560 writel(val, ctx->regs + VIDOSD_B(win));
562 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
563 win_data->offset_x, win_data->offset_y,
564 win_data->offset_x + win_data->ovl_width - 1,
565 win_data->offset_y + win_data->ovl_height - 1);
567 /* hardware window 0 doesn't support alpha channel. */
570 alpha = VIDISD14C_ALPHA1_R(0xf) |
571 VIDISD14C_ALPHA1_G(0xf) |
572 VIDISD14C_ALPHA1_B(0xf);
574 writel(alpha, ctx->regs + VIDOSD_C(win));
578 if (win != 3 && win != 4) {
579 u32 offset = VIDOSD_D(win);
581 offset = VIDOSD_C_SIZE_W0;
582 val = win_data->ovl_width * win_data->ovl_height;
583 writel(val, ctx->regs + offset);
585 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
588 fimd_win_set_pixfmt(dev, win);
590 /* hardware window 0 doesn't support color key. */
592 fimd_win_set_colkey(dev, win);
595 val = readl(ctx->regs + WINCON(win));
596 val |= WINCONx_ENWIN;
597 writel(val, ctx->regs + WINCON(win));
599 mie_set_6bit_dithering(ctx);
601 /* Enable DMA channel and unprotect windows */
602 val = readl(ctx->regs + SHADOWCON);
603 val |= SHADOWCON_CHx_ENABLE(win);
604 val &= ~SHADOWCON_WINx_PROTECT(win);
605 writel(val, ctx->regs + SHADOWCON);
607 win_data->enabled = true;
610 static void fimd_win_disable(struct device *dev, int zpos)
612 struct fimd_context *ctx = get_fimd_context(dev);
613 struct fimd_win_data *win_data;
617 DRM_DEBUG_KMS("%s\n", __FILE__);
621 if (win == DEFAULT_ZPOS)
622 win = ctx->default_win;
624 if (win < 0 || win > WINDOWS_NR)
627 win_data = &ctx->win_data[win];
629 /* protect windows */
630 val = readl(ctx->regs + SHADOWCON);
631 val |= SHADOWCON_WINx_PROTECT(win);
632 writel(val, ctx->regs + SHADOWCON);
635 val = readl(ctx->regs + WINCON(win));
636 val &= ~WINCONx_ENWIN;
637 writel(val, ctx->regs + WINCON(win));
639 /* unprotect windows */
640 val = readl(ctx->regs + SHADOWCON);
641 val &= ~SHADOWCON_CHx_ENABLE(win);
642 val &= ~SHADOWCON_WINx_PROTECT(win);
643 writel(val, ctx->regs + SHADOWCON);
645 win_data->enabled = false;
648 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
649 .mode_set = fimd_win_mode_set,
650 .commit = fimd_win_commit,
651 .disable = fimd_win_disable,
654 static struct exynos_drm_manager fimd_manager = {
656 .ops = &fimd_manager_ops,
657 .overlay_ops = &fimd_overlay_ops,
658 .display_ops = &fimd_display_ops,
661 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
663 struct fimd_context *ctx = (struct fimd_context *)dev_id;
664 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
665 struct drm_device *drm_dev = subdrv->drm_dev;
666 struct exynos_drm_manager *manager = subdrv->manager;
669 val = readl(ctx->regs + VIDINTCON1);
671 if (val & VIDINTCON1_INT_FRAME)
672 /* VSYNC interrupt */
673 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
675 /* check the crtc is detached already from encoder */
676 if (manager->pipe < 0)
679 drm_handle_vblank(drm_dev, manager->pipe);
680 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
686 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
688 DRM_DEBUG_KMS("%s\n", __FILE__);
691 * enable drm irq mode.
692 * - with irq_enabled = 1, we can use the vblank feature.
694 * P.S. note that we wouldn't use drm irq handler but
695 * just specific driver own one instead because
696 * drm framework supports only one irq handler.
698 drm_dev->irq_enabled = 1;
701 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
702 * by drm timer once a current process gives up ownership of
703 * vblank event.(after drm_vblank_put function is called)
705 drm_dev->vblank_disable_allowed = 1;
710 static void fimd_subdrv_remove(struct drm_device *drm_dev)
712 DRM_DEBUG_KMS("%s\n", __FILE__);
717 static int fimd_calc_clkdiv(struct fimd_context *ctx,
718 struct fb_videomode *timing)
720 unsigned long clk = clk_get_rate(ctx->lcd_clk);
723 u32 best_framerate = 0;
726 DRM_DEBUG_KMS("%s\n", __FILE__);
728 retrace = timing->left_margin + timing->hsync_len +
729 timing->right_margin + timing->xres;
730 retrace *= timing->upper_margin + timing->vsync_len +
731 timing->lower_margin + timing->yres;
733 /* default framerate is 60Hz */
734 if (!timing->refresh)
735 timing->refresh = 60;
739 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
742 /* get best framerate */
743 framerate = clk / clkdiv;
744 tmp = timing->refresh - framerate;
746 best_framerate = framerate;
750 best_framerate = framerate;
751 else if (tmp < (best_framerate - framerate))
752 best_framerate = framerate;
760 static void fimd_clear_win(struct fimd_context *ctx, int win)
764 DRM_DEBUG_KMS("%s\n", __FILE__);
766 writel(0, ctx->regs + WINCON(win));
767 writel(0, ctx->regs + VIDOSD_A(win));
768 writel(0, ctx->regs + VIDOSD_B(win));
769 writel(0, ctx->regs + VIDOSD_C(win));
771 if (win == 1 || win == 2)
772 writel(0, ctx->regs + VIDOSD_D(win));
774 val = readl(ctx->regs + SHADOWCON);
775 val &= ~SHADOWCON_WINx_PROTECT(win);
776 writel(val, ctx->regs + SHADOWCON);
779 static int fimd_power_on(struct fimd_context *ctx, bool enable)
781 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
782 struct device *dev = subdrv->dev;
783 struct exynos_drm_fimd_pdata *pdata = dev->platform_data;
785 DRM_DEBUG_KMS("%s\n", __FILE__);
787 if (enable != false && enable != true)
793 ret = clk_enable(ctx->bus_clk);
797 ret = clk_enable(ctx->lcd_clk);
799 clk_disable(ctx->bus_clk);
803 ctx->suspended = false;
805 /* if vblank was enabled status, enable it again. */
806 if (test_and_clear_bit(0, &ctx->irq_flags))
807 fimd_enable_vblank(dev);
811 if (pdata->panel_type == DP_LCD)
812 writel(MIE_CLK_ENABLE, ctx->regs + DPCLKCON);
814 clk_disable(ctx->lcd_clk);
815 clk_disable(ctx->bus_clk);
817 ctx->suspended = true;
819 if (pdata->panel_type == DP_LCD)
820 writel(0, ctx->regs + DPCLKCON);
826 #ifdef CONFIG_EXYNOS_IOMMU
827 static int iommu_init(struct platform_device *pdev)
829 struct platform_device *pds;
831 pds = find_sysmmu_dt(pdev, "sysmmu");
833 printk(KERN_ERR "No sysmmu found\n");
837 platform_set_sysmmu(&pds->dev, &pdev->dev);
838 exynos_drm_common_mapping = s5p_create_iommu_mapping(&pdev->dev,
839 0x20000000, SZ_256M, 4,
840 exynos_drm_common_mapping);
842 if (!exynos_drm_common_mapping) {
843 printk(KERN_ERR "IOMMU mapping not created\n");
850 static void iommu_deinit(struct platform_device *pdev)
852 s5p_destroy_iommu_mapping(&pdev->dev);
853 DRM_DEBUG("released the IOMMU mapping\n");
859 static int __devinit fimd_probe(struct platform_device *pdev)
861 struct device *dev = &pdev->dev;
862 struct fimd_context *ctx;
863 struct exynos_drm_subdrv *subdrv;
864 struct exynos_drm_fimd_pdata *pdata;
865 struct exynos_drm_panel_info *panel;
866 struct resource *res;
867 struct clk *clk_parent;
871 #ifdef CONFIG_EXYNOS_IOMMU
872 ret = iommu_init(pdev);
874 dev_err(dev, "failed to initialize IOMMU\n");
878 DRM_DEBUG_KMS("%s\n", __FILE__);
880 pdata = pdev->dev.platform_data;
882 dev_err(dev, "no platform data specified\n");
886 panel = pdata->panel;
888 dev_err(dev, "panel is null.\n");
892 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
896 ctx->bus_clk = clk_get(dev, "fimd");
897 if (IS_ERR(ctx->bus_clk)) {
898 dev_err(dev, "failed to get bus clock\n");
899 ret = PTR_ERR(ctx->bus_clk);
903 ctx->lcd_clk = clk_get(dev, "sclk_fimd");
904 if (IS_ERR(ctx->lcd_clk)) {
905 dev_err(dev, "failed to get lcd clock\n");
906 ret = PTR_ERR(ctx->lcd_clk);
910 clk_parent = clk_get(NULL, "sclk_vpll");
911 if (IS_ERR(clk_parent)) {
912 ret = PTR_ERR(clk_parent);
916 if (clk_set_parent(ctx->lcd_clk, clk_parent)) {
917 ret = PTR_ERR(ctx->lcd_clk);
921 if (clk_set_rate(ctx->lcd_clk, pdata->clock_rate)) {
922 ret = PTR_ERR(ctx->lcd_clk);
928 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
930 dev_err(dev, "failed to find registers\n");
935 ctx->regs_res = request_mem_region(res->start, resource_size(res),
937 if (!ctx->regs_res) {
938 dev_err(dev, "failed to claim register region\n");
943 ctx->regs = ioremap(res->start, resource_size(res));
945 dev_err(dev, "failed to map registers\n");
947 goto err_req_region_io;
950 ctx->regs_mie = ioremap(MIE_BASE_ADDRESS, 0x400);
951 if (!ctx->regs_mie) {
952 dev_err(dev, "failed to map registers\n");
954 goto err_req_region_io_mie;
957 res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
959 dev_err(dev, "irq request failed.\n");
960 goto err_req_region_irq;
963 ctx->irq = res->start;
965 ret = request_irq(ctx->irq, fimd_irq_handler, 0, "drm_fimd", ctx);
967 dev_err(dev, "irq request failed.\n");
971 ctx->vidcon0 = pdata->vidcon0;
972 ctx->vidcon1 = pdata->vidcon1;
973 ctx->default_win = pdata->default_win;
976 subdrv = &ctx->subdrv;
979 subdrv->manager = &fimd_manager;
980 subdrv->probe = fimd_subdrv_probe;
981 subdrv->remove = fimd_subdrv_remove;
983 mutex_init(&ctx->lock);
985 platform_set_drvdata(pdev, ctx);
987 pm_runtime_enable(dev);
988 pm_runtime_get_sync(dev);
990 for (i = 0;i < MAX_NR_PANELS;i++) {
991 if(panel[i].timing.xres == -1 && panel[i].timing.yres == -1)
994 ctx->clkdiv[i] = fimd_calc_clkdiv(ctx, &panel[i].timing);
995 panel[i].timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv[i];
996 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n for panel[%d]",
997 panel[i].timing.pixclock, ctx->clkdiv[i],i);
1000 for (win = 0; win < WINDOWS_NR; win++)
1001 fimd_clear_win(ctx, win);
1003 if (pdata->panel_type == DP_LCD)
1004 writel(MIE_CLK_ENABLE, ctx->regs + DPCLKCON);
1006 exynos_drm_subdrv_register(subdrv);
1012 iounmap(ctx->regs_mie);
1014 err_req_region_io_mie:
1018 release_resource(ctx->regs_res);
1019 kfree(ctx->regs_res);
1022 clk_disable(ctx->lcd_clk);
1023 clk_put(ctx->lcd_clk);
1026 clk_disable(ctx->bus_clk);
1027 clk_put(ctx->bus_clk);
1030 #ifdef CONFIG_EXYNOS_IOMMU
1037 static int __devexit fimd_remove(struct platform_device *pdev)
1039 struct device *dev = &pdev->dev;
1040 struct fimd_context *ctx = platform_get_drvdata(pdev);
1042 DRM_DEBUG_KMS("%s\n", __FILE__);
1044 exynos_drm_subdrv_unregister(&ctx->subdrv);
1049 clk_disable(ctx->lcd_clk);
1050 clk_disable(ctx->bus_clk);
1052 pm_runtime_set_suspended(dev);
1053 pm_runtime_put_sync(dev);
1056 pm_runtime_disable(dev);
1058 clk_put(ctx->lcd_clk);
1059 clk_put(ctx->bus_clk);
1061 iounmap(ctx->regs_mie);
1063 release_resource(ctx->regs_res);
1064 kfree(ctx->regs_res);
1065 free_irq(ctx->irq, ctx);
1066 #ifdef CONFIG_EXYNOS_IOMMU
1074 #ifdef CONFIG_PM_SLEEP
1075 static int fimd_suspend(struct device *dev)
1077 struct fimd_context *ctx = get_fimd_context(dev);
1079 if (pm_runtime_suspended(dev))
1083 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1084 * called here, an error would be returned by that interface
1085 * because the usage_count of pm runtime is more than 1.
1087 return fimd_power_on(ctx, false);
1090 static int fimd_resume(struct device *dev)
1092 struct fimd_context *ctx = get_fimd_context(dev);
1095 * if entered to sleep when lcd panel was on, the usage_count
1096 * of pm runtime would still be 1 so in this case, fimd driver
1097 * should be on directly not drawing on pm runtime interface.
1099 if (!pm_runtime_suspended(dev))
1100 return fimd_power_on(ctx, true);
1106 #ifdef CONFIG_PM_RUNTIME
1107 static int fimd_runtime_suspend(struct device *dev)
1109 struct fimd_context *ctx = get_fimd_context(dev);
1111 DRM_DEBUG_KMS("%s\n", __FILE__);
1113 return fimd_power_on(ctx, false);
1116 static int fimd_runtime_resume(struct device *dev)
1118 struct fimd_context *ctx = get_fimd_context(dev);
1120 DRM_DEBUG_KMS("%s\n", __FILE__);
1122 return fimd_power_on(ctx, true);
1126 static struct platform_device_id exynos_drm_driver_ids[] = {
1128 .name = "exynos4-fb",
1130 .name = "exynos5-fb",
1134 MODULE_DEVICE_TABLE(platform, exynos_drm_driver_ids);
1136 static const struct dev_pm_ops fimd_pm_ops = {
1137 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1138 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1141 struct platform_driver fimd_driver = {
1142 .probe = fimd_probe,
1143 .remove = __devexit_p(fimd_remove),
1144 .id_table = exynos_drm_driver_ids,
1146 .name = "exynos-drm-fimd",
1147 .owner = THIS_MODULE,