drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_crtc.h"
  34 #include "exynos_drm_plane.h"
  35 #include "exynos_drm_iommu.h"
  36
  37 /*
  38  * FIMD stands for Fully Interactive Mobile Display and
  39  * as a display controller, it transfers contents drawn on memory
  40  * to a LCD Panel through Display Interfaces such as RGB or
  41  * CPU Interface.
  42  */
  43
  44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  45
  46 /* position control register for hardware window 0, 2 ~ 4.*/
  47 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  48 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  49 /*
  50  * size control register for hardware windows 0 and alpha control register
  51  * for hardware windows 1 ~ 4
  52  */
  53 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  54 /* size control register for hardware windows 1 ~ 2. */
  55 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  56
  57 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  58 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  59
  60 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  61 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  62 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  63 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  64
  65 /* color key control register for hardware window 1 ~ 4. */
  66 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  67 /* color key value register for hardware window 1 ~ 4. */
  68 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  69
  70 /* I80 trigger control register */
  71 #define TRIGCON                         0x1A4
  72 #define TRGMODE_ENABLE                  (1 << 0)
  73 #define SWTRGCMD_ENABLE                 (1 << 1)
  74 /* Exynos3250, 3472, 4415, 5260 5410, 5420 and 5422 only supported. */
  75 #define HWTRGEN_ENABLE                  (1 << 3)
  76 #define HWTRGMASK_ENABLE                (1 << 4)
  77 /* Exynos3250, 3472, 4415, 5260, 5420 and 5422 only supported. */
  78 #define HWTRIGEN_PER_ENABLE             (1 << 31)
  79
  80 /* display mode change control register except exynos4 */
  81 #define VIDOUT_CON                      0x000
  82 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  83
  84 /* I80 interface control for main LDI register */
  85 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  86 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  87 #define LCD_CS_SETUP(x)                 ((x) << 16)
  88 #define LCD_WR_SETUP(x)                 ((x) << 12)
  89 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  90 #define LCD_WR_HOLD(x)                  ((x) << 4)
  91 #define I80IFEN_ENABLE                  (1 << 0)
  92
  93 /* FIMD has totally five hardware windows. */
  94 #define WINDOWS_NR      5
  95
  96 /* HW trigger flag on i80 panel. */
  97 #define I80_HW_TRG     (1 << 1)
  98
  99 struct fimd_driver_data {
 100         unsigned int timing_base;
 101         unsigned int lcdblk_offset;
 102         unsigned int lcdblk_vt_shift;
 103         unsigned int lcdblk_bypass_shift;
 104         unsigned int lcdblk_mic_bypass_shift;
 105         unsigned int trg_type;
 106
 107         unsigned int has_shadowcon:1;
 108         unsigned int has_clksel:1;
 109         unsigned int has_limited_fmt:1;
 110         unsigned int has_vidoutcon:1;
 111         unsigned int has_vtsel:1;
 112         unsigned int has_mic_bypass:1;
 113         unsigned int has_dp_clk:1;
 114         unsigned int has_hw_trigger:1;
 115         unsigned int has_trigger_per_te:1;
 116 };
 117
 118 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 119         .timing_base = 0x0,
 120         .has_clksel = 1,
 121         .has_limited_fmt = 1,
 122 };
 123
 124 static struct fimd_driver_data exynos3_fimd_driver_data = {
 125         .timing_base = 0x20000,
 126         .lcdblk_offset = 0x210,
 127         .lcdblk_bypass_shift = 1,
 128         .trg_type = I80_HW_TRG,
 129         .has_shadowcon = 1,
 130         .has_vidoutcon = 1,
 131         .has_trigger_per_te = 1,
 132 };
 133
 134 static struct fimd_driver_data exynos4_fimd_driver_data = {
 135         .timing_base = 0x0,
 136         .lcdblk_offset = 0x210,
 137         .lcdblk_vt_shift = 10,
 138         .lcdblk_bypass_shift = 1,
 139         .has_shadowcon = 1,
 140         .has_vtsel = 1,
 141 };
 142
 143 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 144         .timing_base = 0x20000,
 145         .lcdblk_offset = 0x210,
 146         .lcdblk_vt_shift = 10,
 147         .lcdblk_bypass_shift = 1,
 148         .trg_type = I80_HW_TRG,
 149         .has_shadowcon = 1,
 150         .has_vidoutcon = 1,
 151         .has_vtsel = 1,
 152         .has_trigger_per_te = 1,
 153 };
 154
 155 static struct fimd_driver_data exynos5_fimd_driver_data = {
 156         .timing_base = 0x20000,
 157         .lcdblk_offset = 0x214,
 158         .lcdblk_vt_shift = 24,
 159         .lcdblk_bypass_shift = 15,
 160         .has_shadowcon = 1,
 161         .has_vidoutcon = 1,
 162         .has_vtsel = 1,
 163         .has_dp_clk = 1,
 164 };
 165
 166 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 167         .timing_base = 0x20000,
 168         .lcdblk_offset = 0x214,
 169         .lcdblk_vt_shift = 24,
 170         .lcdblk_bypass_shift = 15,
 171         .lcdblk_mic_bypass_shift = 11,
 172         .has_shadowcon = 1,
 173         .has_vidoutcon = 1,
 174         .has_vtsel = 1,
 175         .has_mic_bypass = 1,
 176         .has_dp_clk = 1,
 177 };
 178
 179 struct fimd_context {
 180         struct device                   *dev;
 181         struct drm_device               *drm_dev;
 182         struct exynos_drm_crtc          *crtc;
 183         struct exynos_drm_plane         planes[WINDOWS_NR];
 184         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 185         struct clk                      *bus_clk;
 186         struct clk                      *lcd_clk;
 187         void __iomem                    *regs;
 188         struct regmap                   *sysreg;
 189         unsigned long                   irq_flags;
 190         u32                             vidcon0;
 191         u32                             vidcon1;
 192         u32                             vidout_con;
 193         u32                             i80ifcon;
 194         bool                            i80_if;
 195         bool                            suspended;
 196         int                             pipe;
 197         wait_queue_head_t               wait_vsync_queue;
 198         atomic_t                        wait_vsync_event;
 199         atomic_t                        win_updated;
 200         atomic_t                        triggering;
 201
 202         const struct fimd_driver_data *driver_data;
 203         struct drm_encoder *encoder;
 204         struct exynos_drm_clk           dp_clk;
 205 };
 206
 207 static const struct of_device_id fimd_driver_dt_match[] = {
 208         { .compatible = "samsung,s3c6400-fimd",
 209           .data = &s3c64xx_fimd_driver_data },
 210         { .compatible = "samsung,exynos3250-fimd",
 211           .data = &exynos3_fimd_driver_data },
 212         { .compatible = "samsung,exynos4210-fimd",
 213           .data = &exynos4_fimd_driver_data },
 214         { .compatible = "samsung,exynos4415-fimd",
 215           .data = &exynos4415_fimd_driver_data },
 216         { .compatible = "samsung,exynos5250-fimd",
 217           .data = &exynos5_fimd_driver_data },
 218         { .compatible = "samsung,exynos5420-fimd",
 219           .data = &exynos5420_fimd_driver_data },
 220         {},
 221 };
 222 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 223
 224 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 225         DRM_PLANE_TYPE_PRIMARY,
 226         DRM_PLANE_TYPE_OVERLAY,
 227         DRM_PLANE_TYPE_OVERLAY,
 228         DRM_PLANE_TYPE_OVERLAY,
 229         DRM_PLANE_TYPE_CURSOR,
 230 };
 231
 232 static const uint32_t fimd_formats[] = {
 233         DRM_FORMAT_C8,
 234         DRM_FORMAT_XRGB1555,
 235         DRM_FORMAT_RGB565,
 236         DRM_FORMAT_XRGB8888,
 237         DRM_FORMAT_ARGB8888,
 238 };
 239
 240 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 241 {
 242         struct fimd_context *ctx = crtc->ctx;
 243         u32 val;
 244
 245         if (ctx->suspended)
 246                 return -EPERM;
 247
 248         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 249                 val = readl(ctx->regs + VIDINTCON0);
 250
 251                 val |= VIDINTCON0_INT_ENABLE;
 252
 253                 if (ctx->i80_if) {
 254                         val |= VIDINTCON0_INT_I80IFDONE;
 255                         val |= VIDINTCON0_INT_SYSMAINCON;
 256                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 257                 } else {
 258                         val |= VIDINTCON0_INT_FRAME;
 259
 260                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 261                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 262                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 263                         val |= VIDINTCON0_FRAMESEL1_NONE;
 264                 }
 265
 266                 writel(val, ctx->regs + VIDINTCON0);
 267         }
 268
 269         return 0;
 270 }
 271
 272 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 273 {
 274         struct fimd_context *ctx = crtc->ctx;
 275         u32 val;
 276
 277         if (ctx->suspended)
 278                 return;
 279
 280         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 281                 val = readl(ctx->regs + VIDINTCON0);
 282
 283                 val &= ~VIDINTCON0_INT_ENABLE;
 284
 285                 if (ctx->i80_if) {
 286                         val &= ~VIDINTCON0_INT_I80IFDONE;
 287                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 288                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 289                 } else
 290                         val &= ~VIDINTCON0_INT_FRAME;
 291
 292                 writel(val, ctx->regs + VIDINTCON0);
 293         }
 294 }
 295
 296 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 297 {
 298         struct fimd_context *ctx = crtc->ctx;
 299
 300         if (ctx->suspended)
 301                 return;
 302
 303         atomic_set(&ctx->wait_vsync_event, 1);
 304
 305         /*
 306          * wait for FIMD to signal VSYNC interrupt or return after
 307          * timeout which is set to 50ms (refresh rate of 20).
 308          */
 309         if (!wait_event_timeout(ctx->wait_vsync_queue,
 310                                 !atomic_read(&ctx->wait_vsync_event),
 311                                 HZ/20))
 312                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 313 }
 314
 315 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 316                                         bool enable)
 317 {
 318         u32 val = readl(ctx->regs + WINCON(win));
 319
 320         if (enable)
 321                 val |= WINCONx_ENWIN;
 322         else
 323                 val &= ~WINCONx_ENWIN;
 324
 325         writel(val, ctx->regs + WINCON(win));
 326 }
 327
 328 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 329                                                 unsigned int win,
 330                                                 bool enable)
 331 {
 332         u32 val = readl(ctx->regs + SHADOWCON);
 333
 334         if (enable)
 335                 val |= SHADOWCON_CHx_ENABLE(win);
 336         else
 337                 val &= ~SHADOWCON_CHx_ENABLE(win);
 338
 339         writel(val, ctx->regs + SHADOWCON);
 340 }
 341
 342 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 343 {
 344         struct fimd_context *ctx = crtc->ctx;
 345         unsigned int win, ch_enabled = 0;
 346
 347         DRM_DEBUG_KMS("%s\n", __FILE__);
 348
 349         /* Hardware is in unknown state, so ensure it gets enabled properly */
 350         pm_runtime_get_sync(ctx->dev);
 351
 352         clk_prepare_enable(ctx->bus_clk);
 353         clk_prepare_enable(ctx->lcd_clk);
 354
 355         /* Check if any channel is enabled. */
 356         for (win = 0; win < WINDOWS_NR; win++) {
 357                 u32 val = readl(ctx->regs + WINCON(win));
 358
 359                 if (val & WINCONx_ENWIN) {
 360                         fimd_enable_video_output(ctx, win, false);
 361
 362                         if (ctx->driver_data->has_shadowcon)
 363                                 fimd_enable_shadow_channel_path(ctx, win,
 364                                                                 false);
 365
 366                         ch_enabled = 1;
 367                 }
 368         }
 369
 370         /* Wait for vsync, as disable channel takes effect at next vsync */
 371         if (ch_enabled) {
 372                 int pipe = ctx->pipe;
 373
 374                 /* ensure that vblank interrupt won't be reported to core */
 375                 ctx->suspended = false;
 376                 ctx->pipe = -1;
 377
 378                 fimd_enable_vblank(ctx->crtc);
 379                 fimd_wait_for_vblank(ctx->crtc);
 380                 fimd_disable_vblank(ctx->crtc);
 381
 382                 ctx->suspended = true;
 383                 ctx->pipe = pipe;
 384         }
 385
 386         clk_disable_unprepare(ctx->lcd_clk);
 387         clk_disable_unprepare(ctx->bus_clk);
 388
 389         pm_runtime_put(ctx->dev);
 390 }
 391
 392 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 393                 const struct drm_display_mode *mode)
 394 {
 395         unsigned long ideal_clk;
 396         u32 clkdiv;
 397
 398         if (mode->clock == 0) {
 399                 DRM_ERROR("Mode has zero clock value.\n");
 400                 return 0xff;
 401         }
 402
 403         ideal_clk = mode->clock * 1000;
 404
 405         if (ctx->i80_if) {
 406                 /*
 407                  * The frame done interrupt should be occurred prior to the
 408                  * next TE signal.
 409                  */
 410                 ideal_clk *= 2;
 411         }
 412
 413         /* Find the clock divider value that gets us closest to ideal_clk */
 414         clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk);
 415
 416         return (clkdiv < 0x100) ? clkdiv : 0xff;
 417 }
 418
 419 static void fimd_setup_trigger(struct fimd_context *ctx)
 420 {
 421         void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
 422         u32 trg_type = ctx->driver_data->trg_type;
 423         u32 val = readl(timing_base + TRIGCON);
 424
 425         val &= ~(TRGMODE_ENABLE);
 426
 427         if (trg_type == I80_HW_TRG) {
 428                 if (ctx->driver_data->has_hw_trigger)
 429                         val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
 430                 if (ctx->driver_data->has_trigger_per_te)
 431                         val |= HWTRIGEN_PER_ENABLE;
 432         } else {
 433                 val |= TRGMODE_ENABLE;
 434         }
 435
 436         writel(val, timing_base + TRIGCON);
 437 }
 438
 439 static void fimd_commit(struct exynos_drm_crtc *crtc)
 440 {
 441         struct fimd_context *ctx = crtc->ctx;
 442         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 443         const struct fimd_driver_data *driver_data = ctx->driver_data;
 444         void *timing_base = ctx->regs + driver_data->timing_base;
 445         u32 val, clkdiv;
 446
 447         if (ctx->suspended)
 448                 return;
 449
 450         /* nothing to do if we haven't set the mode yet */
 451         if (mode->htotal == 0 || mode->vtotal == 0)
 452                 return;
 453
 454         if (ctx->i80_if) {
 455                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 456                 writel(val, timing_base + I80IFCONFAx(0));
 457
 458                 /* disable auto frame rate */
 459                 writel(0, timing_base + I80IFCONFBx(0));
 460
 461                 /* set video type selection to I80 interface */
 462                 if (driver_data->has_vtsel && ctx->sysreg &&
 463                                 regmap_update_bits(ctx->sysreg,
 464                                         driver_data->lcdblk_offset,
 465                                         0x3 << driver_data->lcdblk_vt_shift,
 466                                         0x1 << driver_data->lcdblk_vt_shift)) {
 467                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 468                         return;
 469                 }
 470         } else {
 471                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 472                 u32 vidcon1;
 473
 474                 /* setup polarity values */
 475                 vidcon1 = ctx->vidcon1;
 476                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 477                         vidcon1 |= VIDCON1_INV_VSYNC;
 478                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 479                         vidcon1 |= VIDCON1_INV_HSYNC;
 480                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 481
 482                 /* setup vertical timing values. */
 483                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 484                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 485                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 486
 487                 val = VIDTCON0_VBPD(vbpd - 1) |
 488                         VIDTCON0_VFPD(vfpd - 1) |
 489                         VIDTCON0_VSPW(vsync_len - 1);
 490                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 491
 492                 /* setup horizontal timing values.  */
 493                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 494                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 495                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 496
 497                 val = VIDTCON1_HBPD(hbpd - 1) |
 498                         VIDTCON1_HFPD(hfpd - 1) |
 499                         VIDTCON1_HSPW(hsync_len - 1);
 500                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 501         }
 502
 503         if (driver_data->has_vidoutcon)
 504                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 505
 506         /* set bypass selection */
 507         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 508                                 driver_data->lcdblk_offset,
 509                                 0x1 << driver_data->lcdblk_bypass_shift,
 510                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 511                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 512                 return;
 513         }
 514
 515         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 516          * bit should be cleared.
 517          */
 518         if (driver_data->has_mic_bypass && ctx->sysreg &&
 519             regmap_update_bits(ctx->sysreg,
 520                                 driver_data->lcdblk_offset,
 521                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 522                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 523                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 524                 return;
 525         }
 526
 527         /* setup horizontal and vertical display size. */
 528         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 529                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 530                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 531                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 532         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 533
 534         fimd_setup_trigger(ctx);
 535
 536         /*
 537          * fields of register with prefix '_F' would be updated
 538          * at vsync(same as dma start)
 539          */
 540         val = ctx->vidcon0;
 541         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 542
 543         if (ctx->driver_data->has_clksel)
 544                 val |= VIDCON0_CLKSEL_LCD;
 545
 546         clkdiv = fimd_calc_clkdiv(ctx, mode);
 547         if (clkdiv > 1)
 548                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 549
 550         writel(val, ctx->regs + VIDCON0);
 551 }
 552
 553
 554 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 555                                 uint32_t pixel_format, int width)
 556 {
 557         unsigned long val;
 558
 559         val = WINCONx_ENWIN;
 560
 561         /*
 562          * In case of s3c64xx, window 0 doesn't support alpha channel.
 563          * So the request format is ARGB8888 then change it to XRGB8888.
 564          */
 565         if (ctx->driver_data->has_limited_fmt && !win) {
 566                 if (pixel_format == DRM_FORMAT_ARGB8888)
 567                         pixel_format = DRM_FORMAT_XRGB8888;
 568         }
 569
 570         switch (pixel_format) {
 571         case DRM_FORMAT_C8:
 572                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 573                 val |= WINCONx_BURSTLEN_8WORD;
 574                 val |= WINCONx_BYTSWP;
 575                 break;
 576         case DRM_FORMAT_XRGB1555:
 577                 val |= WINCON0_BPPMODE_16BPP_1555;
 578                 val |= WINCONx_HAWSWP;
 579                 val |= WINCONx_BURSTLEN_16WORD;
 580                 break;
 581         case DRM_FORMAT_RGB565:
 582                 val |= WINCON0_BPPMODE_16BPP_565;
 583                 val |= WINCONx_HAWSWP;
 584                 val |= WINCONx_BURSTLEN_16WORD;
 585                 break;
 586         case DRM_FORMAT_XRGB8888:
 587                 val |= WINCON0_BPPMODE_24BPP_888;
 588                 val |= WINCONx_WSWP;
 589                 val |= WINCONx_BURSTLEN_16WORD;
 590                 break;
 591         case DRM_FORMAT_ARGB8888:
 592                 val |= WINCON1_BPPMODE_25BPP_A1888
 593                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 594                 val |= WINCONx_WSWP;
 595                 val |= WINCONx_BURSTLEN_16WORD;
 596                 break;
 597         default:
 598                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 599
 600                 val |= WINCON0_BPPMODE_24BPP_888;
 601                 val |= WINCONx_WSWP;
 602                 val |= WINCONx_BURSTLEN_16WORD;
 603                 break;
 604         }
 605
 606         /*
 607          * Setting dma-burst to 16Word causes permanent tearing for very small
 608          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 609          * plane size is not recommended as plane size varies alot towards the
 610          * end of the screen and rapid movement causes unstable DMA, but it is
 611          * still better to change dma-burst than displaying garbage.
 612          */
 613
 614         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 615                 val &= ~WINCONx_BURSTLEN_MASK;
 616                 val |= WINCONx_BURSTLEN_4WORD;
 617         }
 618
 619         writel(val, ctx->regs + WINCON(win));
 620
 621         /* hardware window 0 doesn't support alpha channel. */
 622         if (win != 0) {
 623                 /* OSD alpha */
 624                 val = VIDISD14C_ALPHA0_R(0xf) |
 625                         VIDISD14C_ALPHA0_G(0xf) |
 626                         VIDISD14C_ALPHA0_B(0xf) |
 627                         VIDISD14C_ALPHA1_R(0xf) |
 628                         VIDISD14C_ALPHA1_G(0xf) |
 629                         VIDISD14C_ALPHA1_B(0xf);
 630
 631                 writel(val, ctx->regs + VIDOSD_C(win));
 632
 633                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 634                         VIDW_ALPHA_G(0xf);
 635                 writel(val, ctx->regs + VIDWnALPHA0(win));
 636                 writel(val, ctx->regs + VIDWnALPHA1(win));
 637         }
 638 }
 639
 640 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 641 {
 642         unsigned int keycon0 = 0, keycon1 = 0;
 643
 644         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 645                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 646
 647         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 648
 649         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 650         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 651 }
 652
 653 /**
 654  * shadow_protect_win() - disable updating values from shadow registers at vsync
 655  *
 656  * @win: window to protect registers for
 657  * @protect: 1 to protect (disable updates)
 658  */
 659 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 660                                     unsigned int win, bool protect)
 661 {
 662         u32 reg, bits, val;
 663
 664         /*
 665          * SHADOWCON/PRTCON register is used for enabling timing.
 666          *
 667          * for example, once only width value of a register is set,
 668          * if the dma is started then fimd hardware could malfunction so
 669          * with protect window setting, the register fields with prefix '_F'
 670          * wouldn't be updated at vsync also but updated once unprotect window
 671          * is set.
 672          */
 673
 674         if (ctx->driver_data->has_shadowcon) {
 675                 reg = SHADOWCON;
 676                 bits = SHADOWCON_WINx_PROTECT(win);
 677         } else {
 678                 reg = PRTCON;
 679                 bits = PRTCON_PROTECT;
 680         }
 681
 682         val = readl(ctx->regs + reg);
 683         if (protect)
 684                 val |= bits;
 685         else
 686                 val &= ~bits;
 687         writel(val, ctx->regs + reg);
 688 }
 689
 690 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 691 {
 692         struct fimd_context *ctx = crtc->ctx;
 693         int i;
 694
 695         if (ctx->suspended)
 696                 return;
 697
 698         for (i = 0; i < WINDOWS_NR; i++)
 699                 fimd_shadow_protect_win(ctx, i, true);
 700 }
 701
 702 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 703 {
 704         struct fimd_context *ctx = crtc->ctx;
 705         int i;
 706
 707         if (ctx->suspended)
 708                 return;
 709
 710         for (i = 0; i < WINDOWS_NR; i++)
 711                 fimd_shadow_protect_win(ctx, i, false);
 712 }
 713
 714 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 715                               struct exynos_drm_plane *plane)
 716 {
 717         struct exynos_drm_plane_state *state =
 718                                 to_exynos_plane_state(plane->base.state);
 719         struct fimd_context *ctx = crtc->ctx;
 720         struct drm_framebuffer *fb = state->base.fb;
 721         dma_addr_t dma_addr;
 722         unsigned long val, size, offset;
 723         unsigned int last_x, last_y, buf_offsize, line_size;
 724         unsigned int win = plane->index;
 725         unsigned int bpp = fb->bits_per_pixel >> 3;
 726         unsigned int pitch = fb->pitches[0];
 727
 728         if (ctx->suspended)
 729                 return;
 730
 731         offset = state->src.x * bpp;
 732         offset += state->src.y * pitch;
 733
 734         /* buffer start address */
 735         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 736         val = (unsigned long)dma_addr;
 737         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 738
 739         /* buffer end address */
 740         size = pitch * state->crtc.h;
 741         val = (unsigned long)(dma_addr + size);
 742         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 743
 744         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 745                         (unsigned long)dma_addr, val, size);
 746         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 747                         state->crtc.w, state->crtc.h);
 748
 749         /* buffer size */
 750         buf_offsize = pitch - (state->crtc.w * bpp);
 751         line_size = state->crtc.w * bpp;
 752         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 753                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 754                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 755                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 756         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 757
 758         /* OSD position */
 759         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 760                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 761                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 762                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 763         writel(val, ctx->regs + VIDOSD_A(win));
 764
 765         last_x = state->crtc.x + state->crtc.w;
 766         if (last_x)
 767                 last_x--;
 768         last_y = state->crtc.y + state->crtc.h;
 769         if (last_y)
 770                 last_y--;
 771
 772         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 773                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 774
 775         writel(val, ctx->regs + VIDOSD_B(win));
 776
 777         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 778                         state->crtc.x, state->crtc.y, last_x, last_y);
 779
 780         /* OSD size */
 781         if (win != 3 && win != 4) {
 782                 u32 offset = VIDOSD_D(win);
 783                 if (win == 0)
 784                         offset = VIDOSD_C(win);
 785                 val = state->crtc.w * state->crtc.h;
 786                 writel(val, ctx->regs + offset);
 787
 788                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 789         }
 790
 791         fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w);
 792
 793         /* hardware window 0 doesn't support color key. */
 794         if (win != 0)
 795                 fimd_win_set_colkey(ctx, win);
 796
 797         fimd_enable_video_output(ctx, win, true);
 798
 799         if (ctx->driver_data->has_shadowcon)
 800                 fimd_enable_shadow_channel_path(ctx, win, true);
 801
 802         if (ctx->i80_if)
 803                 atomic_set(&ctx->win_updated, 1);
 804 }
 805
 806 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 807                                struct exynos_drm_plane *plane)
 808 {
 809         struct fimd_context *ctx = crtc->ctx;
 810         unsigned int win = plane->index;
 811
 812         if (ctx->suspended)
 813                 return;
 814
 815         fimd_enable_video_output(ctx, win, false);
 816
 817         if (ctx->driver_data->has_shadowcon)
 818                 fimd_enable_shadow_channel_path(ctx, win, false);
 819 }
 820
 821 static void fimd_enable(struct exynos_drm_crtc *crtc)
 822 {
 823         struct fimd_context *ctx = crtc->ctx;
 824
 825         if (!ctx->suspended)
 826                 return;
 827
 828         ctx->suspended = false;
 829
 830         pm_runtime_get_sync(ctx->dev);
 831
 832         /* if vblank was enabled status, enable it again. */
 833         if (test_and_clear_bit(0, &ctx->irq_flags))
 834                 fimd_enable_vblank(ctx->crtc);
 835
 836         fimd_commit(ctx->crtc);
 837 }
 838
 839 static void fimd_disable(struct exynos_drm_crtc *crtc)
 840 {
 841         struct fimd_context *ctx = crtc->ctx;
 842         int i;
 843
 844         if (ctx->suspended)
 845                 return;
 846
 847         /*
 848          * We need to make sure that all windows are disabled before we
 849          * suspend that connector. Otherwise we might try to scan from
 850          * a destroyed buffer later.
 851          */
 852         for (i = 0; i < WINDOWS_NR; i++)
 853                 fimd_disable_plane(crtc, &ctx->planes[i]);
 854
 855         fimd_enable_vblank(crtc);
 856         fimd_wait_for_vblank(crtc);
 857         fimd_disable_vblank(crtc);
 858
 859         writel(0, ctx->regs + VIDCON0);
 860
 861         pm_runtime_put_sync(ctx->dev);
 862         ctx->suspended = true;
 863 }
 864
 865 static void fimd_trigger(struct device *dev)
 866 {
 867         struct fimd_context *ctx = dev_get_drvdata(dev);
 868         const struct fimd_driver_data *driver_data = ctx->driver_data;
 869         void *timing_base = ctx->regs + driver_data->timing_base;
 870         u32 reg;
 871
 872          /*
 873           * Skips triggering if in triggering state, because multiple triggering
 874           * requests can cause panel reset.
 875           */
 876         if (atomic_read(&ctx->triggering))
 877                 return;
 878
 879         /* Enters triggering mode */
 880         atomic_set(&ctx->triggering, 1);
 881
 882         reg = readl(timing_base + TRIGCON);
 883         reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
 884         writel(reg, timing_base + TRIGCON);
 885
 886         /*
 887          * Exits triggering mode if vblank is not enabled yet, because when the
 888          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 889          */
 890         if (!test_bit(0, &ctx->irq_flags))
 891                 atomic_set(&ctx->triggering, 0);
 892 }
 893
 894 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 895 {
 896         struct fimd_context *ctx = crtc->ctx;
 897         u32 trg_type = ctx->driver_data->trg_type;
 898
 899         /* Checks the crtc is detached already from encoder */
 900         if (ctx->pipe < 0 || !ctx->drm_dev)
 901                 return;
 902
 903         if (trg_type == I80_HW_TRG)
 904                 goto out;
 905
 906         /*
 907          * If there is a page flip request, triggers and handles the page flip
 908          * event so that current fb can be updated into panel GRAM.
 909          */
 910         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 911                 fimd_trigger(ctx->dev);
 912
 913 out:
 914         /* Wakes up vsync event queue */
 915         if (atomic_read(&ctx->wait_vsync_event)) {
 916                 atomic_set(&ctx->wait_vsync_event, 0);
 917                 wake_up(&ctx->wait_vsync_queue);
 918         }
 919
 920         if (test_bit(0, &ctx->irq_flags))
 921                 drm_crtc_handle_vblank(&ctx->crtc->base);
 922 }
 923
 924 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 925 {
 926         struct fimd_context *ctx = container_of(clk, struct fimd_context,
 927                                                 dp_clk);
 928         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 929         writel(val, ctx->regs + DP_MIE_CLKCON);
 930 }
 931
 932 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 933         .enable = fimd_enable,
 934         .disable = fimd_disable,
 935         .commit = fimd_commit,
 936         .enable_vblank = fimd_enable_vblank,
 937         .disable_vblank = fimd_disable_vblank,
 938         .atomic_begin = fimd_atomic_begin,
 939         .update_plane = fimd_update_plane,
 940         .disable_plane = fimd_disable_plane,
 941         .atomic_flush = fimd_atomic_flush,
 942         .te_handler = fimd_te_handler,
 943 };
 944
 945 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 946 {
 947         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 948         u32 val, clear_bit, start, start_s;
 949         int win;
 950
 951         val = readl(ctx->regs + VIDINTCON1);
 952
 953         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 954         if (val & clear_bit)
 955                 writel(clear_bit, ctx->regs + VIDINTCON1);
 956
 957         /* check the crtc is detached already from encoder */
 958         if (ctx->pipe < 0 || !ctx->drm_dev)
 959                 goto out;
 960
 961         if (!ctx->i80_if)
 962                 drm_crtc_handle_vblank(&ctx->crtc->base);
 963
 964         for (win = 0 ; win < WINDOWS_NR ; win++) {
 965                 struct exynos_drm_plane *plane = &ctx->planes[win];
 966
 967                 if (!plane->pending_fb)
 968                         continue;
 969
 970                 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
 971                 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
 972                 if (start == start_s)
 973                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 974         }
 975
 976         if (ctx->i80_if) {
 977                 /* Exits triggering mode */
 978                 atomic_set(&ctx->triggering, 0);
 979         } else {
 980                 /* set wait vsync event to zero and wake up queue. */
 981                 if (atomic_read(&ctx->wait_vsync_event)) {
 982                         atomic_set(&ctx->wait_vsync_event, 0);
 983                         wake_up(&ctx->wait_vsync_queue);
 984                 }
 985         }
 986
 987 out:
 988         return IRQ_HANDLED;
 989 }
 990
 991 static int fimd_bind(struct device *dev, struct device *master, void *data)
 992 {
 993         struct fimd_context *ctx = dev_get_drvdata(dev);
 994         struct drm_device *drm_dev = data;
 995         struct exynos_drm_private *priv = drm_dev->dev_private;
 996         struct exynos_drm_plane *exynos_plane;
 997         unsigned int i;
 998         int ret;
 999
1000         ctx->drm_dev = drm_dev;
1001         ctx->pipe = priv->pipe++;
1002
1003         for (i = 0; i < WINDOWS_NR; i++) {
1004                 ctx->configs[i].pixel_formats = fimd_formats;
1005                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1006                 ctx->configs[i].zpos = i;
1007                 ctx->configs[i].type = fimd_win_types[i];
1008                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1009                                         1 << ctx->pipe, &ctx->configs[i]);
1010                 if (ret)
1011                         return ret;
1012         }
1013
1014         exynos_plane = &ctx->planes[DEFAULT_WIN];
1015         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1016                                            ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
1017                                            &fimd_crtc_ops, ctx);
1018         if (IS_ERR(ctx->crtc))
1019                 return PTR_ERR(ctx->crtc);
1020
1021         if (ctx->driver_data->has_dp_clk) {
1022                 ctx->dp_clk.enable = fimd_dp_clock_enable;
1023                 ctx->crtc->pipe_clk = &ctx->dp_clk;
1024         }
1025
1026         if (ctx->encoder)
1027                 exynos_dpi_bind(drm_dev, ctx->encoder);
1028
1029         if (is_drm_iommu_supported(drm_dev))
1030                 fimd_clear_channels(ctx->crtc);
1031
1032         ret = drm_iommu_attach_device(drm_dev, dev);
1033         if (ret)
1034                 priv->pipe--;
1035
1036         return ret;
1037 }
1038
1039 static void fimd_unbind(struct device *dev, struct device *master,
1040                         void *data)
1041 {
1042         struct fimd_context *ctx = dev_get_drvdata(dev);
1043
1044         fimd_disable(ctx->crtc);
1045
1046         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1047
1048         if (ctx->encoder)
1049                 exynos_dpi_remove(ctx->encoder);
1050 }
1051
1052 static const struct component_ops fimd_component_ops = {
1053         .bind   = fimd_bind,
1054         .unbind = fimd_unbind,
1055 };
1056
1057 static int fimd_probe(struct platform_device *pdev)
1058 {
1059         struct device *dev = &pdev->dev;
1060         struct fimd_context *ctx;
1061         struct device_node *i80_if_timings;
1062         struct resource *res;
1063         int ret;
1064
1065         if (!dev->of_node)
1066                 return -ENODEV;
1067
1068         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1069         if (!ctx)
1070                 return -ENOMEM;
1071
1072         ctx->dev = dev;
1073         ctx->suspended = true;
1074         ctx->driver_data = of_device_get_match_data(dev);
1075
1076         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1077                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1078         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1079                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1080
1081         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1082         if (i80_if_timings) {
1083                 u32 val;
1084
1085                 ctx->i80_if = true;
1086
1087                 if (ctx->driver_data->has_vidoutcon)
1088                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1089                 else
1090                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1091                 /*
1092                  * The user manual describes that this "DSI_EN" bit is required
1093                  * to enable I80 24-bit data interface.
1094                  */
1095                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1096
1097                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1098                         val = 0;
1099                 ctx->i80ifcon = LCD_CS_SETUP(val);
1100                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1101                         val = 0;
1102                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1103                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1104                         val = 1;
1105                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1106                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1107                         val = 0;
1108                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1109         }
1110         of_node_put(i80_if_timings);
1111
1112         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1113                                                         "samsung,sysreg");
1114         if (IS_ERR(ctx->sysreg)) {
1115                 dev_warn(dev, "failed to get system register.\n");
1116                 ctx->sysreg = NULL;
1117         }
1118
1119         ctx->bus_clk = devm_clk_get(dev, "fimd");
1120         if (IS_ERR(ctx->bus_clk)) {
1121                 dev_err(dev, "failed to get bus clock\n");
1122                 return PTR_ERR(ctx->bus_clk);
1123         }
1124
1125         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1126         if (IS_ERR(ctx->lcd_clk)) {
1127                 dev_err(dev, "failed to get lcd clock\n");
1128                 return PTR_ERR(ctx->lcd_clk);
1129         }
1130
1131         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1132
1133         ctx->regs = devm_ioremap_resource(dev, res);
1134         if (IS_ERR(ctx->regs))
1135                 return PTR_ERR(ctx->regs);
1136
1137         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1138                                            ctx->i80_if ? "lcd_sys" : "vsync");
1139         if (!res) {
1140                 dev_err(dev, "irq request failed.\n");
1141                 return -ENXIO;
1142         }
1143
1144         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1145                                                         0, "drm_fimd", ctx);
1146         if (ret) {
1147                 dev_err(dev, "irq request failed.\n");
1148                 return ret;
1149         }
1150
1151         init_waitqueue_head(&ctx->wait_vsync_queue);
1152         atomic_set(&ctx->wait_vsync_event, 0);
1153
1154         platform_set_drvdata(pdev, ctx);
1155
1156         ctx->encoder = exynos_dpi_probe(dev);
1157         if (IS_ERR(ctx->encoder))
1158                 return PTR_ERR(ctx->encoder);
1159
1160         pm_runtime_enable(dev);
1161
1162         ret = component_add(dev, &fimd_component_ops);
1163         if (ret)
1164                 goto err_disable_pm_runtime;
1165
1166         return ret;
1167
1168 err_disable_pm_runtime:
1169         pm_runtime_disable(dev);
1170
1171         return ret;
1172 }
1173
1174 static int fimd_remove(struct platform_device *pdev)
1175 {
1176         pm_runtime_disable(&pdev->dev);
1177
1178         component_del(&pdev->dev, &fimd_component_ops);
1179
1180         return 0;
1181 }
1182
1183 #ifdef CONFIG_PM
1184 static int exynos_fimd_suspend(struct device *dev)
1185 {
1186         struct fimd_context *ctx = dev_get_drvdata(dev);
1187
1188         clk_disable_unprepare(ctx->lcd_clk);
1189         clk_disable_unprepare(ctx->bus_clk);
1190
1191         return 0;
1192 }
1193
1194 static int exynos_fimd_resume(struct device *dev)
1195 {
1196         struct fimd_context *ctx = dev_get_drvdata(dev);
1197         int ret;
1198
1199         ret = clk_prepare_enable(ctx->bus_clk);
1200         if (ret < 0) {
1201                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1202                 return ret;
1203         }
1204
1205         ret = clk_prepare_enable(ctx->lcd_clk);
1206         if  (ret < 0) {
1207                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1208                 return ret;
1209         }
1210
1211         return 0;
1212 }
1213 #endif
1214
1215 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1216         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1217 };
1218
1219 struct platform_driver fimd_driver = {
1220         .probe          = fimd_probe,
1221         .remove         = fimd_remove,
1222         .driver         = {
1223                 .name   = "exynos4-fb",
1224                 .owner  = THIS_MODULE,
1225                 .pm     = &exynos_fimd_pm_ops,
1226                 .of_match_table = fimd_driver_dt_match,
1227         },
1228 };