drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/clk.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of.h>
  37 #include <linux/of_i2c.h>
  38 #include <linux/of_gpio.h>
  39 #include <plat/gpio-cfg.h>
  40
  41 #include <drm/exynos_drm.h>
  42
  43 #include "exynos_drm_drv.h"
  44 #include "exynos_drm_display.h"
  45
  46 #include "exynos_hdmi.h"
  47
  48 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  49
  50 #define HOTPLUG_DEBOUNCE_MS             1100
  51
  52 struct hdmi_resources {
  53         struct clk                      *hdmi;
  54         struct clk                      *sclk_hdmi;
  55         struct clk                      *sclk_pixel;
  56         struct clk                      *sclk_hdmiphy;
  57         struct clk                      *hdmiphy;
  58         struct regulator_bulk_data      *regul_bulk;
  59         int                             regul_count;
  60 };
  61
  62 struct hdmi_tg_regs {
  63         u8 cmd[1];
  64         u8 h_fsz[2];
  65         u8 hact_st[2];
  66         u8 hact_sz[2];
  67         u8 v_fsz[2];
  68         u8 vsync[2];
  69         u8 vsync2[2];
  70         u8 vact_st[2];
  71         u8 vact_sz[2];
  72         u8 field_chg[2];
  73         u8 vact_st2[2];
  74         u8 vact_st3[2];
  75         u8 vact_st4[2];
  76         u8 vsync_top_hdmi[2];
  77         u8 vsync_bot_hdmi[2];
  78         u8 field_top_hdmi[2];
  79         u8 field_bot_hdmi[2];
  80         u8 tg_3d[1];
  81 };
  82
  83 struct hdmi_core_regs {
  84         u8 h_blank[2];
  85         u8 v2_blank[2];
  86         u8 v1_blank[2];
  87         u8 v_line[2];
  88         u8 h_line[2];
  89         u8 hsync_pol[1];
  90         u8 vsync_pol[1];
  91         u8 int_pro_mode[1];
  92         u8 v_blank_f0[2];
  93         u8 v_blank_f1[2];
  94         u8 h_sync_start[2];
  95         u8 h_sync_end[2];
  96         u8 v_sync_line_bef_2[2];
  97         u8 v_sync_line_bef_1[2];
  98         u8 v_sync_line_aft_2[2];
  99         u8 v_sync_line_aft_1[2];
 100         u8 v_sync_line_aft_pxl_2[2];
 101         u8 v_sync_line_aft_pxl_1[2];
 102         u8 v_blank_f2[2]; /* for 3D mode */
 103         u8 v_blank_f3[2]; /* for 3D mode */
 104         u8 v_blank_f4[2]; /* for 3D mode */
 105         u8 v_blank_f5[2]; /* for 3D mode */
 106         u8 v_sync_line_aft_3[2];
 107         u8 v_sync_line_aft_4[2];
 108         u8 v_sync_line_aft_5[2];
 109         u8 v_sync_line_aft_6[2];
 110         u8 v_sync_line_aft_pxl_3[2];
 111         u8 v_sync_line_aft_pxl_4[2];
 112         u8 v_sync_line_aft_pxl_5[2];
 113         u8 v_sync_line_aft_pxl_6[2];
 114         u8 vact_space_1[2];
 115         u8 vact_space_2[2];
 116         u8 vact_space_3[2];
 117         u8 vact_space_4[2];
 118         u8 vact_space_5[2];
 119         u8 vact_space_6[2];
 120 };
 121
 122 struct hdmi_mode_conf {
 123         int pixel_clock;
 124         struct hdmi_core_regs core;
 125         struct hdmi_tg_regs tg;
 126         u8 vic;
 127 };
 128
 129 struct hdmi_context {
 130         struct device                   *dev;
 131         struct drm_device               *drm_dev;
 132         struct fb_videomode             *default_timing;
 133         struct hdmi_mode_conf           mode_conf;
 134         unsigned int                    is_v13:1;
 135         unsigned int                    default_win;
 136         unsigned int                    default_bpp;
 137         bool                            hpd_handle;
 138         bool                            has_hdmi_sink;
 139         bool                            has_hdmi_audio;
 140         bool                            is_soc_exynos5;
 141         bool                            is_hdmi_powered_on;
 142         bool                            video_enabled;
 143
 144         struct resource                 *regs_res;
 145         void __iomem                    *regs;
 146         unsigned int                    external_irq;
 147         unsigned int                    internal_irq;
 148         unsigned int                    curr_irq;
 149         struct timer_list               hotplug_timer;
 150
 151         struct i2c_client               *ddc_port;
 152         struct i2c_client               *hdmiphy_port;
 153         int                             hpd_gpio;
 154         /* current hdmiphy conf index */
 155         int cur_conf;
 156
 157         struct hdmi_resources           res;
 158 };
 159
 160 /* HDMI Version 1.3 */
 161 static const u8 hdmiphy_v13_conf27[32] = {
 162         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 163         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 164         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 165         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 166 };
 167
 168 static const u8 hdmiphy_v13_conf27_027[32] = {
 169         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 170         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 171         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 172         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 173 };
 174
 175 static const u8 hdmiphy_v13_conf74_175[32] = {
 176         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 177         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 178         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 179         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 180 };
 181
 182 static const u8 hdmiphy_v13_conf74_25[32] = {
 183         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 184         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 185         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 186         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 187 };
 188
 189 static const u8 hdmiphy_v13_conf148_5[32] = {
 190         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 191         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 192         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 193         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 194 };
 195
 196 struct hdmi_v13_tg_regs {
 197         u8 cmd;
 198         u8 h_fsz_l;
 199         u8 h_fsz_h;
 200         u8 hact_st_l;
 201         u8 hact_st_h;
 202         u8 hact_sz_l;
 203         u8 hact_sz_h;
 204         u8 v_fsz_l;
 205         u8 v_fsz_h;
 206         u8 vsync_l;
 207         u8 vsync_h;
 208         u8 vsync2_l;
 209         u8 vsync2_h;
 210         u8 vact_st_l;
 211         u8 vact_st_h;
 212         u8 vact_sz_l;
 213         u8 vact_sz_h;
 214         u8 field_chg_l;
 215         u8 field_chg_h;
 216         u8 vact_st2_l;
 217         u8 vact_st2_h;
 218         u8 vsync_top_hdmi_l;
 219         u8 vsync_top_hdmi_h;
 220         u8 vsync_bot_hdmi_l;
 221         u8 vsync_bot_hdmi_h;
 222         u8 field_top_hdmi_l;
 223         u8 field_top_hdmi_h;
 224         u8 field_bot_hdmi_l;
 225         u8 field_bot_hdmi_h;
 226 };
 227
 228 struct hdmi_v13_core_regs {
 229         u8 h_blank[2];
 230         u8 v_blank[3];
 231         u8 h_v_line[3];
 232         u8 vsync_pol[1];
 233         u8 int_pro_mode[1];
 234         u8 v_blank_f[3];
 235         u8 h_sync_gen[3];
 236         u8 v_sync_gen1[3];
 237         u8 v_sync_gen2[3];
 238         u8 v_sync_gen3[3];
 239 };
 240
 241 struct hdmi_v13_preset_conf {
 242         struct hdmi_v13_core_regs core;
 243         struct hdmi_v13_tg_regs tg;
 244 };
 245
 246 struct hdmi_v13_conf {
 247         int width;
 248         int height;
 249         int vrefresh;
 250         bool interlace;
 251         const u8 *hdmiphy_data;
 252         const struct hdmi_v13_preset_conf *conf;
 253 };
 254
 255 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 256         .core = {
 257                 .h_blank = {0x8a, 0x00},
 258                 .v_blank = {0x0d, 0x6a, 0x01},
 259                 .h_v_line = {0x0d, 0xa2, 0x35},
 260                 .vsync_pol = {0x01},
 261                 .int_pro_mode = {0x00},
 262                 .v_blank_f = {0x00, 0x00, 0x00},
 263                 .h_sync_gen = {0x0e, 0x30, 0x11},
 264                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 265                 /* other don't care */
 266         },
 267         .tg = {
 268                 0x00, /* cmd */
 269                 0x5a, 0x03, /* h_fsz */
 270                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 271                 0x0d, 0x02, /* v_fsz */
 272                 0x01, 0x00, 0x33, 0x02, /* vsync */
 273                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 274                 0x33, 0x02, /* field_chg */
 275                 0x49, 0x02, /* vact_st2 */
 276                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 277                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 278         },
 279 };
 280
 281 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 282         .core = {
 283                 .h_blank = {0x72, 0x01},
 284                 .v_blank = {0xee, 0xf2, 0x00},
 285                 .h_v_line = {0xee, 0x22, 0x67},
 286                 .vsync_pol = {0x00},
 287                 .int_pro_mode = {0x00},
 288                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 289                 .h_sync_gen = {0x6c, 0x50, 0x02},
 290                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 291                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 292                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 293                 /* other don't care */
 294         },
 295         .tg = {
 296                 0x00, /* cmd */
 297                 0x72, 0x06, /* h_fsz */
 298                 0x71, 0x01, 0x01, 0x05, /* hact */
 299                 0xee, 0x02, /* v_fsz */
 300                 0x01, 0x00, 0x33, 0x02, /* vsync */
 301                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 302                 0x33, 0x02, /* field_chg */
 303                 0x49, 0x02, /* vact_st2 */
 304                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 305                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 306         },
 307 };
 308
 309 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 310         .core = {
 311                 .h_blank = {0xd0, 0x02},
 312                 .v_blank = {0x32, 0xB2, 0x00},
 313                 .h_v_line = {0x65, 0x04, 0xa5},
 314                 .vsync_pol = {0x00},
 315                 .int_pro_mode = {0x01},
 316                 .v_blank_f = {0x49, 0x2A, 0x23},
 317                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 318                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 319                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 320                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 321                 /* other don't care */
 322         },
 323         .tg = {
 324                 0x00, /* cmd */
 325                 0x50, 0x0A, /* h_fsz */
 326                 0xCF, 0x02, 0x81, 0x07, /* hact */
 327                 0x65, 0x04, /* v_fsz */
 328                 0x01, 0x00, 0x33, 0x02, /* vsync */
 329                 0x16, 0x00, 0x1c, 0x02, /* vact */
 330                 0x33, 0x02, /* field_chg */
 331                 0x49, 0x02, /* vact_st2 */
 332                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 333                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 334         },
 335 };
 336
 337 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 338         .core = {
 339                 .h_blank = {0xd0, 0x02},
 340                 .v_blank = {0x65, 0x6c, 0x01},
 341                 .h_v_line = {0x65, 0x04, 0xa5},
 342                 .vsync_pol = {0x00},
 343                 .int_pro_mode = {0x00},
 344                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 345                 .h_sync_gen = {0x0e, 0xea, 0x08},
 346                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 347                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 348                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 349                 /* other don't care */
 350         },
 351         .tg = {
 352                 0x00, /* cmd */
 353                 0x50, 0x0A, /* h_fsz */
 354                 0xCF, 0x02, 0x81, 0x07, /* hact */
 355                 0x65, 0x04, /* v_fsz */
 356                 0x01, 0x00, 0x33, 0x02, /* vsync */
 357                 0x2d, 0x00, 0x38, 0x04, /* vact */
 358                 0x33, 0x02, /* field_chg */
 359                 0x48, 0x02, /* vact_st2 */
 360                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 361                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 362         },
 363 };
 364
 365 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 366         .core = {
 367                 .h_blank = {0x18, 0x01},
 368                 .v_blank = {0x32, 0xB2, 0x00},
 369                 .h_v_line = {0x65, 0x84, 0x89},
 370                 .vsync_pol = {0x00},
 371                 .int_pro_mode = {0x01},
 372                 .v_blank_f = {0x49, 0x2A, 0x23},
 373                 .h_sync_gen = {0x56, 0x08, 0x02},
 374                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 375                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 376                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 377                 /* other don't care */
 378         },
 379         .tg = {
 380                 0x00, /* cmd */
 381                 0x98, 0x08, /* h_fsz */
 382                 0x17, 0x01, 0x81, 0x07, /* hact */
 383                 0x65, 0x04, /* v_fsz */
 384                 0x01, 0x00, 0x33, 0x02, /* vsync */
 385                 0x16, 0x00, 0x1c, 0x02, /* vact */
 386                 0x33, 0x02, /* field_chg */
 387                 0x49, 0x02, /* vact_st2 */
 388                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 389                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 390         },
 391 };
 392
 393 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 394         .core = {
 395                 .h_blank = {0x18, 0x01},
 396                 .v_blank = {0x65, 0x6c, 0x01},
 397                 .h_v_line = {0x65, 0x84, 0x89},
 398                 .vsync_pol = {0x00},
 399                 .int_pro_mode = {0x00},
 400                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 401                 .h_sync_gen = {0x56, 0x08, 0x02},
 402                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 403                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 404                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 405                 /* other don't care */
 406         },
 407         .tg = {
 408                 0x00, /* cmd */
 409                 0x98, 0x08, /* h_fsz */
 410                 0x17, 0x01, 0x81, 0x07, /* hact */
 411                 0x65, 0x04, /* v_fsz */
 412                 0x01, 0x00, 0x33, 0x02, /* vsync */
 413                 0x2d, 0x00, 0x38, 0x04, /* vact */
 414                 0x33, 0x02, /* field_chg */
 415                 0x48, 0x02, /* vact_st2 */
 416                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 417                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 418         },
 419 };
 420
 421 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 422         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 423         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 424         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 425         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 426         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 427                                  &hdmi_v13_conf_1080p50 },
 428         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 429         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 430                                  &hdmi_v13_conf_1080p60 },
 431 };
 432
 433 struct hdmiphy_config {
 434         int pixel_clock;
 435         u8 conf[32];
 436 };
 437
 438 static const struct hdmiphy_config phy_configs[] = {
 439         {
 440                 .pixel_clock = 25200000,
 441                 .conf = {
 442                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 443                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 444                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 445                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 446                 },
 447         },
 448         {
 449                 .pixel_clock = 27000000,
 450                 .conf = {
 451                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 452                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 453                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 454                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 455                 },
 456         },
 457         {
 458                 .pixel_clock = 27027000,
 459                 .conf = {
 460                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 461                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 462                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 463                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 464                 },
 465         },
 466         {
 467                 .pixel_clock = 36000000,
 468                 .conf = {
 469                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 470                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 471                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 472                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 473                 },
 474         },
 475         {
 476                 .pixel_clock = 40000000,
 477                 .conf = {
 478                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 479                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 480                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 481                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 482                 },
 483         },
 484         {
 485                 .pixel_clock = 65000000,
 486                 .conf = {
 487                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 488                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 489                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 490                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 491                 },
 492         },
 493         {
 494                 .pixel_clock = 74176000,
 495                 .conf = {
 496                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 497                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 498                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 499                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 500                 },
 501         },
 502         {
 503                 .pixel_clock = 74250000,
 504                 .conf = {
 505                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 506                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 507                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 508                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 509                 },
 510         },
 511         {
 512                 .pixel_clock = 83500000,
 513                 .conf = {
 514                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 515                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 516                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 517                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 518                 },
 519         },
 520         {
 521                 .pixel_clock = 106500000,
 522                 .conf = {
 523                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 524                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 525                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 526                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 527                 },
 528         },
 529         {
 530                 .pixel_clock = 108000000,
 531                 .conf = {
 532                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 533                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 534                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 535                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 536                 },
 537         },
 538         {
 539                 .pixel_clock = 146250000,
 540                 .conf = {
 541                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 542                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 543                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 544                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 545                 },
 546         },
 547         {
 548                 .pixel_clock = 148500000,
 549                 .conf = {
 550                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 551                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 552                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 553                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 554                 },
 555         },
 556 };
 557
 558 struct hdmi_infoframe {
 559         enum HDMI_PACKET_TYPE type;
 560         u8 ver;
 561         u8 len;
 562 };
 563
 564 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 565 {
 566         return readl(hdata->regs + reg_id);
 567 }
 568
 569 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 570                                  u32 reg_id, u8 value)
 571 {
 572         writeb(value, hdata->regs + reg_id);
 573 }
 574
 575 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 576                                  u32 reg_id, u32 value, u32 mask)
 577 {
 578         u32 old = readl(hdata->regs + reg_id);
 579         value = (value & mask) | (old & ~mask);
 580         writel(value, hdata->regs + reg_id);
 581 }
 582
 583 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 584 {
 585         if (external) {
 586                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 587                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 588         } else {
 589                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 590                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 591         }
 592 }
 593
 594 static int hdmi_get_hpd(struct hdmi_context *hdata)
 595 {
 596         return gpio_get_value(hdata->hpd_gpio);
 597 }
 598
 599 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 600 {
 601 #define DUMPREG(reg_id) \
 602         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 603         readl(hdata->regs + reg_id))
 604         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 605         DUMPREG(HDMI_INTC_FLAG);
 606         DUMPREG(HDMI_INTC_CON);
 607         DUMPREG(HDMI_HPD_STATUS);
 608         DUMPREG(HDMI_V13_PHY_RSTOUT);
 609         DUMPREG(HDMI_V13_PHY_VPLL);
 610         DUMPREG(HDMI_V13_PHY_CMU);
 611         DUMPREG(HDMI_V13_CORE_RSTOUT);
 612
 613         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 614         DUMPREG(HDMI_CON_0);
 615         DUMPREG(HDMI_CON_1);
 616         DUMPREG(HDMI_CON_2);
 617         DUMPREG(HDMI_SYS_STATUS);
 618         DUMPREG(HDMI_V13_PHY_STATUS);
 619         DUMPREG(HDMI_STATUS_EN);
 620         DUMPREG(HDMI_HPD);
 621         DUMPREG(HDMI_MODE_SEL);
 622         DUMPREG(HDMI_V13_HPD_GEN);
 623         DUMPREG(HDMI_V13_DC_CONTROL);
 624         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 625
 626         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 627         DUMPREG(HDMI_H_BLANK_0);
 628         DUMPREG(HDMI_H_BLANK_1);
 629         DUMPREG(HDMI_V13_V_BLANK_0);
 630         DUMPREG(HDMI_V13_V_BLANK_1);
 631         DUMPREG(HDMI_V13_V_BLANK_2);
 632         DUMPREG(HDMI_V13_H_V_LINE_0);
 633         DUMPREG(HDMI_V13_H_V_LINE_1);
 634         DUMPREG(HDMI_V13_H_V_LINE_2);
 635         DUMPREG(HDMI_VSYNC_POL);
 636         DUMPREG(HDMI_INT_PRO_MODE);
 637         DUMPREG(HDMI_V13_V_BLANK_F_0);
 638         DUMPREG(HDMI_V13_V_BLANK_F_1);
 639         DUMPREG(HDMI_V13_V_BLANK_F_2);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 641         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 642         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 650         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 651         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 652
 653         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 654         DUMPREG(HDMI_TG_CMD);
 655         DUMPREG(HDMI_TG_H_FSZ_L);
 656         DUMPREG(HDMI_TG_H_FSZ_H);
 657         DUMPREG(HDMI_TG_HACT_ST_L);
 658         DUMPREG(HDMI_TG_HACT_ST_H);
 659         DUMPREG(HDMI_TG_HACT_SZ_L);
 660         DUMPREG(HDMI_TG_HACT_SZ_H);
 661         DUMPREG(HDMI_TG_V_FSZ_L);
 662         DUMPREG(HDMI_TG_V_FSZ_H);
 663         DUMPREG(HDMI_TG_VSYNC_L);
 664         DUMPREG(HDMI_TG_VSYNC_H);
 665         DUMPREG(HDMI_TG_VSYNC2_L);
 666         DUMPREG(HDMI_TG_VSYNC2_H);
 667         DUMPREG(HDMI_TG_VACT_ST_L);
 668         DUMPREG(HDMI_TG_VACT_ST_H);
 669         DUMPREG(HDMI_TG_VACT_SZ_L);
 670         DUMPREG(HDMI_TG_VACT_SZ_H);
 671         DUMPREG(HDMI_TG_FIELD_CHG_L);
 672         DUMPREG(HDMI_TG_FIELD_CHG_H);
 673         DUMPREG(HDMI_TG_VACT_ST2_L);
 674         DUMPREG(HDMI_TG_VACT_ST2_H);
 675         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 677         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 678         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 681         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 682         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 683 #undef DUMPREG
 684 }
 685
 686 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 687 {
 688         int i;
 689
 690 #define DUMPREG(reg_id) \
 691         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 692         readl(hdata->regs + reg_id))
 693
 694         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 695         DUMPREG(HDMI_INTC_CON);
 696         DUMPREG(HDMI_INTC_FLAG);
 697         DUMPREG(HDMI_HPD_STATUS);
 698         DUMPREG(HDMI_INTC_CON_1);
 699         DUMPREG(HDMI_INTC_FLAG_1);
 700         DUMPREG(HDMI_PHY_STATUS_0);
 701         DUMPREG(HDMI_PHY_STATUS_PLL);
 702         DUMPREG(HDMI_PHY_CON_0);
 703         DUMPREG(HDMI_PHY_RSTOUT);
 704         DUMPREG(HDMI_PHY_VPLL);
 705         DUMPREG(HDMI_PHY_CMU);
 706         DUMPREG(HDMI_CORE_RSTOUT);
 707
 708         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 709         DUMPREG(HDMI_CON_0);
 710         DUMPREG(HDMI_CON_1);
 711         DUMPREG(HDMI_CON_2);
 712         DUMPREG(HDMI_SYS_STATUS);
 713         DUMPREG(HDMI_PHY_STATUS_0);
 714         DUMPREG(HDMI_STATUS_EN);
 715         DUMPREG(HDMI_HPD);
 716         DUMPREG(HDMI_MODE_SEL);
 717         DUMPREG(HDMI_ENC_EN);
 718         DUMPREG(HDMI_DC_CONTROL);
 719         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 720
 721         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 722         DUMPREG(HDMI_H_BLANK_0);
 723         DUMPREG(HDMI_H_BLANK_1);
 724         DUMPREG(HDMI_V2_BLANK_0);
 725         DUMPREG(HDMI_V2_BLANK_1);
 726         DUMPREG(HDMI_V1_BLANK_0);
 727         DUMPREG(HDMI_V1_BLANK_1);
 728         DUMPREG(HDMI_V_LINE_0);
 729         DUMPREG(HDMI_V_LINE_1);
 730         DUMPREG(HDMI_H_LINE_0);
 731         DUMPREG(HDMI_H_LINE_1);
 732         DUMPREG(HDMI_HSYNC_POL);
 733
 734         DUMPREG(HDMI_VSYNC_POL);
 735         DUMPREG(HDMI_INT_PRO_MODE);
 736         DUMPREG(HDMI_V_BLANK_F0_0);
 737         DUMPREG(HDMI_V_BLANK_F0_1);
 738         DUMPREG(HDMI_V_BLANK_F1_0);
 739         DUMPREG(HDMI_V_BLANK_F1_1);
 740
 741         DUMPREG(HDMI_H_SYNC_START_0);
 742         DUMPREG(HDMI_H_SYNC_START_1);
 743         DUMPREG(HDMI_H_SYNC_END_0);
 744         DUMPREG(HDMI_H_SYNC_END_1);
 745
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 748         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 749         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 750
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 753         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 754         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 755
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 758         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 759         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 760
 761         DUMPREG(HDMI_V_BLANK_F2_0);
 762         DUMPREG(HDMI_V_BLANK_F2_1);
 763         DUMPREG(HDMI_V_BLANK_F3_0);
 764         DUMPREG(HDMI_V_BLANK_F3_1);
 765         DUMPREG(HDMI_V_BLANK_F4_0);
 766         DUMPREG(HDMI_V_BLANK_F4_1);
 767         DUMPREG(HDMI_V_BLANK_F5_0);
 768         DUMPREG(HDMI_V_BLANK_F5_1);
 769
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 776         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 777         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 778
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 785         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 786         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 787
 788         DUMPREG(HDMI_VACT_SPACE_1_0);
 789         DUMPREG(HDMI_VACT_SPACE_1_1);
 790         DUMPREG(HDMI_VACT_SPACE_2_0);
 791         DUMPREG(HDMI_VACT_SPACE_2_1);
 792         DUMPREG(HDMI_VACT_SPACE_3_0);
 793         DUMPREG(HDMI_VACT_SPACE_3_1);
 794         DUMPREG(HDMI_VACT_SPACE_4_0);
 795         DUMPREG(HDMI_VACT_SPACE_4_1);
 796         DUMPREG(HDMI_VACT_SPACE_5_0);
 797         DUMPREG(HDMI_VACT_SPACE_5_1);
 798         DUMPREG(HDMI_VACT_SPACE_6_0);
 799         DUMPREG(HDMI_VACT_SPACE_6_1);
 800
 801         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 802         DUMPREG(HDMI_TG_CMD);
 803         DUMPREG(HDMI_TG_H_FSZ_L);
 804         DUMPREG(HDMI_TG_H_FSZ_H);
 805         DUMPREG(HDMI_TG_HACT_ST_L);
 806         DUMPREG(HDMI_TG_HACT_ST_H);
 807         DUMPREG(HDMI_TG_HACT_SZ_L);
 808         DUMPREG(HDMI_TG_HACT_SZ_H);
 809         DUMPREG(HDMI_TG_V_FSZ_L);
 810         DUMPREG(HDMI_TG_V_FSZ_H);
 811         DUMPREG(HDMI_TG_VSYNC_L);
 812         DUMPREG(HDMI_TG_VSYNC_H);
 813         DUMPREG(HDMI_TG_VSYNC2_L);
 814         DUMPREG(HDMI_TG_VSYNC2_H);
 815         DUMPREG(HDMI_TG_VACT_ST_L);
 816         DUMPREG(HDMI_TG_VACT_ST_H);
 817         DUMPREG(HDMI_TG_VACT_SZ_L);
 818         DUMPREG(HDMI_TG_VACT_SZ_H);
 819         DUMPREG(HDMI_TG_FIELD_CHG_L);
 820         DUMPREG(HDMI_TG_FIELD_CHG_H);
 821         DUMPREG(HDMI_TG_VACT_ST2_L);
 822         DUMPREG(HDMI_TG_VACT_ST2_H);
 823         DUMPREG(HDMI_TG_VACT_ST3_L);
 824         DUMPREG(HDMI_TG_VACT_ST3_H);
 825         DUMPREG(HDMI_TG_VACT_ST4_L);
 826         DUMPREG(HDMI_TG_VACT_ST4_H);
 827         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 828         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 829         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 830         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 831         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 832         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 833         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 834         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 835         DUMPREG(HDMI_TG_3D);
 836
 837         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 838         DUMPREG(HDMI_AVI_CON);
 839         DUMPREG(HDMI_AVI_HEADER0);
 840         DUMPREG(HDMI_AVI_HEADER1);
 841         DUMPREG(HDMI_AVI_HEADER2);
 842         DUMPREG(HDMI_AVI_CHECK_SUM);
 843         DUMPREG(HDMI_VSI_CON);
 844         DUMPREG(HDMI_VSI_HEADER0);
 845         DUMPREG(HDMI_VSI_HEADER1);
 846         DUMPREG(HDMI_VSI_HEADER2);
 847         for (i = 0; i < 7; ++i)
 848                 DUMPREG(HDMI_VSI_DATA(i));
 849
 850 #undef DUMPREG
 851 }
 852
 853 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 854 {
 855         if (hdata->is_v13)
 856                 hdmi_v13_regs_dump(hdata, prefix);
 857         else
 858                 hdmi_v14_regs_dump(hdata, prefix);
 859 }
 860
 861 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 862 {
 863         int i;
 864
 865         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 866                 if (hdmi_v13_confs[i].width == mode->crtc_hdisplay &&
 867                         hdmi_v13_confs[i].height == mode->crtc_vdisplay &&
 868                         hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 869                         hdmi_v13_confs[i].interlace ==
 870                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 871                                  true : false))
 872                         return i;
 873
 874         return -EINVAL;
 875 }
 876
 877 static bool hdmi_is_connected(void *ctx)
 878 {
 879         struct hdmi_context *hdata = ctx;
 880         if (hdata->is_hdmi_powered_on) {
 881                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 882                         DRM_DEBUG_KMS("hdmi is not connected\n");
 883                         return false;
 884                 }
 885         } else if (!hdmi_get_hpd(hdata)) {
 886                         DRM_DEBUG_KMS("hdmi is not connected\n");
 887                         return false;
 888         }
 889
 890         return true;
 891 }
 892
 893 static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
 894 {
 895         struct hdmi_context *hdata = ctx;
 896         struct edid *edid;
 897
 898         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", DRM_BASE_ID(connector),
 899                         drm_get_connector_name(connector));
 900
 901         if (!hdata->ddc_port)
 902                 return ERR_PTR(-ENODEV);
 903
 904         edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 905         if (!edid)
 906                 return ERR_PTR(-ENODEV);
 907
 908         /*
 909          * TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 910          * to get the edid and then call drm_detect_hdmi_monitor.
 911          */
 912         hdata->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
 913         hdata->has_hdmi_audio = drm_detect_monitor_audio(edid);
 914         DRM_DEBUG_KMS("%s monitor\n", hdata->has_hdmi_sink ? "hdmi" : "dvi");
 915
 916         return edid;
 917 }
 918
 919 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 920 {
 921         int i;
 922
 923         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 924                         check_timing->xres, check_timing->yres,
 925                         check_timing->refresh, (check_timing->vmode &
 926                         FB_VMODE_INTERLACED) ? true : false);
 927
 928         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 929                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 930                         hdmi_v13_confs[i].height == check_timing->yres &&
 931                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 932                         hdmi_v13_confs[i].interlace ==
 933                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 934                          true : false))
 935                                 return 0;
 936
 937         /* TODO */
 938
 939         return -EINVAL;
 940 }
 941
 942 static int find_hdmiphy_conf(int pixel_clock)
 943 {
 944         int i;
 945
 946         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 947                 if (phy_configs[i].pixel_clock == pixel_clock)
 948                         return i;
 949         }
 950         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 951         return -EINVAL;
 952 }
 953
 954 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 955 {
 956         int ret;
 957         enum exynos_mixer_mode_type mode_type;
 958
 959         /* Make sure the mixer can generate this mode */
 960         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 961         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 962                 return -EINVAL;
 963
 964         ret = find_hdmiphy_conf(mode->pixclock);
 965         return ret < 0 ? ret : 0;
 966 }
 967
 968 static u8 hdmi_chksum(struct hdmi_context *hdata,
 969                         u32 start, u8 len, u32 hdr_sum)
 970 {
 971         int i;
 972         /* hdr_sum : header0 + header1 + header2
 973         * start : start address of packet byte1
 974         * len : packet bytes - 1 */
 975         for (i = 0; i < len; ++i)
 976                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 977
 978         return (u8)(0x100 - (hdr_sum & 0xff));
 979 }
 980
 981 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 982                         struct hdmi_infoframe *infoframe)
 983 {
 984         u32 hdr_sum;
 985         u8 chksum;
 986         u32 aspect_ratio;
 987         u32 mod;
 988
 989         /* TODO: stringify HDMI_PACKET_TYPE */
 990         DRM_DEBUG_KMS("type: %d ver: %d len: %d\n", infoframe->type,
 991                         infoframe->ver, infoframe->len);
 992         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 993         if (!hdata->has_hdmi_sink) {
 994                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 995                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 996                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 997                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 998                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 999                 return;
1000         }
1001
1002         switch (infoframe->type) {
1003
1004         case HDMI_PACKET_TYPE_AVI:
1005                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1006                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1007                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1008                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1009                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1010                 /* Output format zero hardcoded ,RGB YBCR selection */
1011                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1012                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1013
1014                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1015
1016                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1017                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1018                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1019
1020                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1021                                         infoframe->len, hdr_sum);
1022                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1023                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1024                 break;
1025
1026         case HDMI_PACKET_TYPE_AUI:
1027                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1028                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1029                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1030                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1031                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1032                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1033                                         infoframe->len, hdr_sum);
1034                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1035                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1036                 break;
1037
1038         default:
1039                 break;
1040         }
1041 }
1042
1043 static int hdmi_check_timing(void *ctx, void *timing)
1044 {
1045         struct hdmi_context *hdata = ctx;
1046         struct fb_videomode *check_timing = timing;
1047
1048         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1049                         check_timing->yres, check_timing->refresh,
1050                         check_timing->vmode);
1051
1052         if (hdata->is_v13)
1053                 return hdmi_v13_check_timing(check_timing);
1054         else
1055                 return hdmi_v14_check_timing(check_timing);
1056 }
1057
1058 static void hdmi_set_acr(u32 freq, u8 *acr)
1059 {
1060         u32 n, cts;
1061
1062         switch (freq) {
1063         case 32000:
1064                 n = 4096;
1065                 cts = 27000;
1066                 break;
1067         case 44100:
1068                 n = 6272;
1069                 cts = 30000;
1070                 break;
1071         case 88200:
1072                 n = 12544;
1073                 cts = 30000;
1074                 break;
1075         case 176400:
1076                 n = 25088;
1077                 cts = 30000;
1078                 break;
1079         case 48000:
1080                 n = 6144;
1081                 cts = 27000;
1082                 break;
1083         case 96000:
1084                 n = 12288;
1085                 cts = 27000;
1086                 break;
1087         case 192000:
1088                 n = 24576;
1089                 cts = 27000;
1090                 break;
1091         default:
1092                 n = 0;
1093                 cts = 0;
1094                 break;
1095         }
1096
1097         acr[1] = cts >> 16;
1098         acr[2] = cts >> 8 & 0xff;
1099         acr[3] = cts & 0xff;
1100
1101         acr[4] = n >> 16;
1102         acr[5] = n >> 8 & 0xff;
1103         acr[6] = n & 0xff;
1104 }
1105
1106 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1107 {
1108         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1109         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1110         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1111         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1114         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1115         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1116         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1117
1118         if (hdata->is_v13)
1119                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1120         else
1121                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1122 }
1123
1124 static void hdmi_audio_init(struct hdmi_context *hdata)
1125 {
1126         u32 sample_rate, bits_per_sample, frame_size_code;
1127         u32 data_num, bit_ch, sample_frq;
1128         u32 val;
1129         u8 acr[7];
1130
1131         sample_rate = 44100;
1132         bits_per_sample = 16;
1133         frame_size_code = 0;
1134
1135         switch (bits_per_sample) {
1136         case 20:
1137                 data_num = 2;
1138                 bit_ch  = 1;
1139                 break;
1140         case 24:
1141                 data_num = 3;
1142                 bit_ch  = 1;
1143                 break;
1144         default:
1145                 data_num = 1;
1146                 bit_ch  = 0;
1147                 break;
1148         }
1149
1150         hdmi_set_acr(sample_rate, acr);
1151         hdmi_reg_acr(hdata, acr);
1152
1153         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1154                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1155                                 | HDMI_I2S_MUX_ENABLE);
1156
1157         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1158                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1159
1160         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1161
1162         sample_frq = (sample_rate == 44100) ? 0 :
1163                         (sample_rate == 48000) ? 2 :
1164                         (sample_rate == 32000) ? 3 :
1165                         (sample_rate == 96000) ? 0xa : 0x0;
1166
1167         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1168         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1169
1170         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1171         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1172
1173         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1174         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1175                         | HDMI_I2S_SEL_LRCK(6));
1176         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1177                         | HDMI_I2S_SEL_SDATA2(4));
1178         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1179                         | HDMI_I2S_SEL_SDATA2(2));
1180         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1181
1182         /* I2S_CON_1 & 2 */
1183         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1184                         | HDMI_I2S_L_CH_LOW_POL);
1185         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1186                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1187                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1188                         | HDMI_I2S_BASIC_FORMAT);
1189
1190         /* Configure register related to CUV information */
1191         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1192                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1193                         | HDMI_I2S_COPYRIGHT
1194                         | HDMI_I2S_LINEAR_PCM
1195                         | HDMI_I2S_CONSUMER_FORMAT);
1196         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1197         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1198         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1199                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1200         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1201                         HDMI_I2S_ORG_SMP_FREQ_44_1
1202                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1203                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1204
1205         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1206 }
1207
1208 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1209 {
1210         if (!hdata->has_hdmi_audio)
1211                 return;
1212
1213         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1214         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1215                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1216 }
1217
1218 static void hdmi_conf_reset(struct hdmi_context *hdata)
1219 {
1220         u32 reg;
1221
1222         /* disable hpd handle for drm */
1223         hdata->hpd_handle = false;
1224
1225         if (hdata->is_v13)
1226                 reg = HDMI_V13_CORE_RSTOUT;
1227         else
1228                 reg = HDMI_CORE_RSTOUT;
1229
1230         /* resetting HDMI core */
1231         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1232         mdelay(10);
1233         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1234         mdelay(10);
1235
1236         /* enable hpd handle for drm */
1237         hdata->hpd_handle = true;
1238 }
1239
1240 static void hdmi_enable_video(struct hdmi_context *hdata)
1241 {
1242         if (hdata->is_v13)
1243                 return;
1244
1245         hdata->video_enabled = true;
1246         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1247 }
1248
1249 static void hdmi_disable_video(struct hdmi_context *hdata)
1250 {
1251         if (hdata->is_v13)
1252                 return;
1253
1254         /* Set the blue screen color to black */
1255         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_0, 0);
1256         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_1, 0);
1257         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_0, 0);
1258         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_1, 0);
1259         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_0, 0);
1260         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_1, 0);
1261
1262         /* Enable the "blue screen", which effectively disconnects the mixer */
1263         hdata->video_enabled = false;
1264         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
1265 }
1266
1267 static void hdmi_conf_init(struct hdmi_context *hdata)
1268 {
1269         struct hdmi_infoframe infoframe;
1270         /* disable hpd handle for drm */
1271         hdata->hpd_handle = false;
1272
1273         /* enable HPD interrupts */
1274         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1275                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1276         mdelay(10);
1277         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1278                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1279
1280         /* choose HDMI mode */
1281         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1282                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1283
1284         if (hdata->video_enabled)
1285                 hdmi_enable_video(hdata);
1286         else
1287                 hdmi_disable_video(hdata);
1288
1289         if (!hdata->has_hdmi_sink) {
1290                 /* choose DVI mode */
1291                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1292                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1293                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1294                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1295         }
1296
1297         if (hdata->is_v13) {
1298                 /* choose bluescreen (fecal) color */
1299                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1300                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1301                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1302
1303                 /* enable AVI packet every vsync, fixes purple line problem */
1304                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1305                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1306                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1307                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1308
1309                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1310                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1311                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1312         } else {
1313                 /* enable AVI packet every vsync, fixes purple line problem */
1314                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1315
1316                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1317                 infoframe.ver = HDMI_AVI_VERSION;
1318                 infoframe.len = HDMI_AVI_LENGTH;
1319                 hdmi_reg_infoframe(hdata, &infoframe);
1320
1321                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1322                 infoframe.ver = HDMI_AUI_VERSION;
1323                 infoframe.len = HDMI_AUI_LENGTH;
1324                 hdmi_reg_infoframe(hdata, &infoframe);
1325
1326         }
1327
1328         /* enable hpd handle for drm */
1329         hdata->hpd_handle = true;
1330 }
1331
1332 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1333 {
1334         const struct hdmi_v13_preset_conf *conf =
1335                 hdmi_v13_confs[hdata->cur_conf].conf;
1336         const struct hdmi_v13_core_regs *core = &conf->core;
1337         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1338         int tries;
1339
1340         /* setting core registers */
1341         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1342         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1343         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1344         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1345         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1346         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1347         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1348         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1349         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1350         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1351         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1352         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1353         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1354         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1355         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1356         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1357         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1358         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1359         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1360         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1361         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1362         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1363         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1364         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1365         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1366         /* Timing generator registers */
1367         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1368         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1369         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1370         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1371         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1372         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1373         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1374         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1375         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1376         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1377         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1378         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1379         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1380         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1381         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1382         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1383         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1384         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1385         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1386         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1387         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1388         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1389         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1390         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1391         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1392         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1393         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1394         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1395
1396         /* waiting for HDMIPHY's PLL to get to steady state */
1397         for (tries = 100; tries; --tries) {
1398                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1399                 if (val & HDMI_PHY_STATUS_READY)
1400                         break;
1401                 mdelay(1);
1402         }
1403         /* steady state not achieved */
1404         if (tries == 0) {
1405                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1406                 hdmi_regs_dump(hdata, "timing apply");
1407         }
1408
1409         clk_disable(hdata->res.sclk_hdmi);
1410         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1411         clk_enable(hdata->res.sclk_hdmi);
1412
1413         /* enable HDMI and timing generator */
1414         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1415         if (core->int_pro_mode[0])
1416                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1417                                 HDMI_FIELD_EN);
1418         else
1419                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1420 }
1421
1422 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1423 {
1424         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1425         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1426         int tries;
1427
1428         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1429         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1430         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1431         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1432         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1433         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1434         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1435         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1436         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1437         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1438         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1439         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1440         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1441         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1442         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1443         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1444         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1445         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1446         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1447         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1448         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1449         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1450                         core->v_sync_line_bef_2[0]);
1451         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1452                         core->v_sync_line_bef_2[1]);
1453         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1454                         core->v_sync_line_bef_1[0]);
1455         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1456                         core->v_sync_line_bef_1[1]);
1457         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1458                         core->v_sync_line_aft_2[0]);
1459         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1460                         core->v_sync_line_aft_2[1]);
1461         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1462                         core->v_sync_line_aft_1[0]);
1463         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1464                         core->v_sync_line_aft_1[1]);
1465         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1466                         core->v_sync_line_aft_pxl_2[0]);
1467         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1468                         core->v_sync_line_aft_pxl_2[1]);
1469         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1470                         core->v_sync_line_aft_pxl_1[0]);
1471         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1472                         core->v_sync_line_aft_pxl_1[1]);
1473         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1474         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1475         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1476         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1477         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1478         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1479         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1480         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1481         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1482                         core->v_sync_line_aft_3[0]);
1483         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1484                         core->v_sync_line_aft_3[1]);
1485         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1486                         core->v_sync_line_aft_4[0]);
1487         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1488                         core->v_sync_line_aft_4[1]);
1489         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1490                         core->v_sync_line_aft_5[0]);
1491         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1492                         core->v_sync_line_aft_5[1]);
1493         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1494                         core->v_sync_line_aft_6[0]);
1495         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1496                         core->v_sync_line_aft_6[1]);
1497         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1498                         core->v_sync_line_aft_pxl_3[0]);
1499         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1500                         core->v_sync_line_aft_pxl_3[1]);
1501         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1502                         core->v_sync_line_aft_pxl_4[0]);
1503         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1504                         core->v_sync_line_aft_pxl_4[1]);
1505         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1506                         core->v_sync_line_aft_pxl_5[0]);
1507         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1508                         core->v_sync_line_aft_pxl_5[1]);
1509         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1510                         core->v_sync_line_aft_pxl_6[0]);
1511         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1512                         core->v_sync_line_aft_pxl_6[1]);
1513         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1514         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1515         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1516         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1517         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1518         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1519         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1520         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1521         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1522         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1523         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1524         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1525
1526         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1527         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1528         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1529         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1531         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1532         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1533         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1534         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1535         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1536         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1537         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1538         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1539         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1540         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1541         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1542         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1543         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1544         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1545         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1546         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1547         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1548         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1549         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1550         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1551         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1552         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1553         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1554         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1555         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1556         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1557         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1558         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1559
1560         /* waiting for HDMIPHY's PLL to get to steady state */
1561         for (tries = 100; tries; --tries) {
1562                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1563                 if (val & HDMI_PHY_STATUS_READY)
1564                         break;
1565                 mdelay(1);
1566         }
1567         /* steady state not achieved */
1568         if (tries == 0) {
1569                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1570                 hdmi_regs_dump(hdata, "timing apply");
1571         }
1572
1573         clk_disable(hdata->res.sclk_hdmi);
1574         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1575         clk_enable(hdata->res.sclk_hdmi);
1576
1577         /* enable HDMI and timing generator */
1578         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1579         if (core->int_pro_mode[0])
1580                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1581                                 HDMI_FIELD_EN);
1582         else
1583                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1584 }
1585
1586 static void hdmi_timing_apply(struct hdmi_context *hdata)
1587 {
1588         if (hdata->is_v13)
1589                 hdmi_v13_timing_apply(hdata);
1590         else
1591                 hdmi_v14_timing_apply(hdata);
1592 }
1593
1594 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1595 {
1596         u8 buffer[2];
1597         u32 reg;
1598
1599         clk_disable(hdata->res.sclk_hdmi);
1600         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1601         clk_enable(hdata->res.sclk_hdmi);
1602
1603         /* operation mode */
1604         buffer[0] = 0x1f;
1605         buffer[1] = 0x00;
1606
1607         if (hdata->hdmiphy_port)
1608                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1609
1610         if (hdata->is_v13)
1611                 reg = HDMI_V13_PHY_RSTOUT;
1612         else
1613                 reg = HDMI_PHY_RSTOUT;
1614
1615         /* reset hdmiphy */
1616         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1617         mdelay(10);
1618         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1619         mdelay(10);
1620 }
1621
1622 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1623 {
1624         const u8 *hdmiphy_data;
1625         u8 buffer[32];
1626         u8 operation[2];
1627         u8 read_buffer[32] = {0, };
1628         int ret;
1629         int i;
1630
1631         DRM_DEBUG_KMS("\n");
1632
1633         if (!hdata->hdmiphy_port) {
1634                 DRM_ERROR("hdmiphy is not attached\n");
1635                 return;
1636         }
1637
1638         /* pixel clock */
1639         if (hdata->is_v13) {
1640                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1641         } else {
1642                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1643                 hdmiphy_data = phy_configs[i].conf;
1644         }
1645
1646         memcpy(buffer, hdmiphy_data, 32);
1647         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1648         if (ret != 32) {
1649                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1650                 return;
1651         }
1652
1653         mdelay(10);
1654
1655         /* operation mode */
1656         operation[0] = 0x1f;
1657         operation[1] = 0x80;
1658
1659         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1660         if (ret != 2) {
1661                 DRM_ERROR("failed to enable hdmiphy\n");
1662                 return;
1663         }
1664
1665         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1666         if (ret < 0) {
1667                 DRM_ERROR("failed to read hdmiphy config\n");
1668                 return;
1669         }
1670
1671         for (i = 0; i < ret; i++)
1672                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1673                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1674 }
1675
1676 static void hdmi_conf_apply(struct hdmi_context *hdata)
1677 {
1678         DRM_DEBUG_KMS("\n");
1679
1680         hdmiphy_conf_reset(hdata);
1681         hdmiphy_conf_apply(hdata);
1682
1683         hdmi_conf_reset(hdata);
1684         hdmi_conf_init(hdata);
1685         if (!hdata->is_soc_exynos5)
1686                 hdmi_audio_init(hdata);
1687
1688         /* setting core registers */
1689         hdmi_timing_apply(hdata);
1690         if (!hdata->is_soc_exynos5)
1691                 hdmi_audio_control(hdata, true);
1692
1693         hdmi_regs_dump(hdata, "start");
1694 }
1695
1696 static void hdmi_mode_copy(struct drm_display_mode *dst,
1697         struct drm_display_mode *src)
1698 {
1699         struct drm_mode_object base;
1700
1701         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(src), src->name);
1702
1703         /* following information should be preserved,
1704          * required for releasing the drm_display_mode node,
1705          * duplicated to recieve adjustment info. */
1706
1707         base.id = dst->base.id;
1708         base.type = dst->base.type;
1709
1710         memcpy(dst, src, sizeof(struct drm_display_mode));
1711
1712         dst->base.id = base.id;
1713         dst->base.type = base.type;
1714 }
1715
1716 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1717                                 struct drm_display_mode *mode,
1718                                 struct drm_display_mode *adjusted_mode)
1719 {
1720         struct drm_display_mode *t, *con_mode;
1721         struct hdmi_context *hdata = ctx;
1722         int index;
1723
1724         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] [MODE:%d:%s]\n",
1725                         DRM_BASE_ID(connector),
1726                         drm_get_connector_name(connector),
1727                         DRM_BASE_ID(mode), mode->name);
1728
1729         /*
1730          * Match the incoming mode to a mode in the connector list and copy it
1731          * over. This is important since this might be an adjusted mode from the
1732          * mixer and those have differing crtc_* values.
1733          */
1734         list_for_each_entry_safe(con_mode, t, &connector->modes, head) {
1735                 if (mode->hdisplay == con_mode->hdisplay &&
1736                     mode->vdisplay == con_mode->vdisplay &&
1737                     mode->clock == con_mode->clock) {
1738                         hdmi_mode_copy(adjusted_mode, con_mode);
1739                         return;
1740                 }
1741         }
1742
1743         /*
1744          * We didn't find a mode which matched the desired resolution, so just
1745          * find something with the same clock.
1746          */
1747         list_for_each_entry_safe(con_mode, t, &connector->modes, head) {
1748                 if (hdata->is_v13)
1749                         index = hdmi_v13_conf_index(con_mode);
1750                 else
1751                         index = find_hdmiphy_conf(con_mode->clock * 1000);
1752
1753                 if (index >= 0) {
1754                         DRM_INFO("desired mode doesn't exist so\n");
1755                         DRM_INFO("use the most suitable mode among modes.\n");
1756                         hdmi_mode_copy(adjusted_mode, con_mode);
1757                         break;
1758                 }
1759         }
1760 }
1761
1762 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1763 {
1764         int i;
1765         BUG_ON(num_bytes > 4);
1766         for (i = 0; i < num_bytes; i++)
1767                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1768 }
1769
1770 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1771                         struct drm_display_mode *m)
1772 {
1773         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1774         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1775
1776         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(m), m->name);
1777
1778         hdata->mode_conf.vic = drm_match_cea_mode(m);
1779
1780         hdata->mode_conf.pixel_clock = m->clock * 1000;
1781         hdmi_set_reg(core->h_blank, 2, m->crtc_htotal - m->crtc_hdisplay);
1782         hdmi_set_reg(core->v_line, 2, m->crtc_vtotal);
1783         hdmi_set_reg(core->h_line, 2, m->crtc_htotal);
1784         hdmi_set_reg(core->hsync_pol, 1,
1785                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1786         hdmi_set_reg(core->vsync_pol, 1,
1787                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1788         hdmi_set_reg(core->int_pro_mode, 1,
1789                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1790
1791         /*
1792          * Quirk requirement for exynos 5 HDMI IP design,
1793          * 2 pixels less than the actual calculation for hsync_start
1794          * and end.
1795          */
1796
1797         /* Following values & calculations differ for different type of modes */
1798         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1799                 /* Interlaced Mode */
1800                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1801                         (m->crtc_vsync_end - m->crtc_vdisplay) / 2);
1802                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1803                         (m->crtc_vsync_start - m->crtc_vdisplay) / 2);
1804                 hdmi_set_reg(core->v2_blank, 2, m->crtc_vtotal / 2);
1805                 hdmi_set_reg(core->v1_blank, 2,
1806                                 (m->crtc_vtotal - m->crtc_vdisplay) / 2);
1807                 hdmi_set_reg(core->v_blank_f0, 2,
1808                         (m->crtc_vtotal +
1809                         ((m->crtc_vsync_end - m->crtc_vsync_start) * 4) + 5)
1810                         / 2);
1811                 hdmi_set_reg(core->v_blank_f1, 2, m->crtc_vtotal);
1812                 hdmi_set_reg(core->v_sync_line_aft_2, 2,
1813                         (m->crtc_vtotal / 2) + 7);
1814                 hdmi_set_reg(core->v_sync_line_aft_1, 2,
1815                         (m->crtc_vtotal / 2) + 2);
1816                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1817                         (m->crtc_htotal / 2) +
1818                         (m->crtc_hsync_start - m->crtc_hdisplay));
1819                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1820                         (m->crtc_htotal / 2) +
1821                         (m->crtc_hsync_start - m->crtc_hdisplay));
1822                 hdmi_set_reg(tg->vact_st, 2,
1823                         (m->crtc_vtotal - m->crtc_vdisplay) / 2);
1824                 hdmi_set_reg(tg->vact_sz, 2, m->crtc_vdisplay / 2);
1825                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1826                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1827                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1828         } else {
1829                 /* Progressive Mode */
1830                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1831                         m->crtc_vsync_end - m->crtc_vdisplay);
1832                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1833                         m->crtc_vsync_start - m->crtc_vdisplay);
1834                 hdmi_set_reg(core->v2_blank, 2, m->crtc_vtotal);
1835                 hdmi_set_reg(core->v1_blank, 2,
1836                         m->crtc_vtotal - m->crtc_vdisplay);
1837                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1838                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1839                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1840                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1841                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1842                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1843                 hdmi_set_reg(tg->vact_st, 2, m->crtc_vtotal - m->crtc_vdisplay);
1844                 hdmi_set_reg(tg->vact_sz, 2, m->crtc_vdisplay);
1845                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1846                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1847                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1848         }
1849
1850         /* Following values & calculations are same irrespective of mode type */
1851         hdmi_set_reg(core->h_sync_start, 2,
1852                 m->crtc_hsync_start - m->crtc_hdisplay - 2);
1853         hdmi_set_reg(core->h_sync_end, 2,
1854                 m->crtc_hsync_end - m->crtc_hdisplay - 2);
1855         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1856         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1857         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1858         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1859         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1860         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1861         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1862         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1863         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1864         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1865         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1866         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1867         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1868         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1869         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1870         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1871         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1872         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1873
1874         /* Timing generator registers */
1875         hdmi_set_reg(tg->cmd, 1, 0x0);
1876         hdmi_set_reg(tg->h_fsz, 2, m->crtc_htotal);
1877         hdmi_set_reg(tg->hact_st, 2, m->crtc_htotal - m->crtc_hdisplay);
1878         hdmi_set_reg(tg->hact_sz, 2, m->crtc_hdisplay);
1879         hdmi_set_reg(tg->v_fsz, 2, m->crtc_vtotal);
1880         hdmi_set_reg(tg->vsync, 2, 0x1);
1881         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1882         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1883         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1884         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1885         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1886         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1887         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1888
1889         /* Workaround 4 implementation for 1440x900 resolution support */
1890         if (hdata->is_soc_exynos5) {
1891                 if (m->crtc_hdisplay == 1440 && m->crtc_vdisplay == 900 &&
1892                     m->clock == 106500) {
1893                         hdmi_set_reg(tg->hact_st, 2,
1894                                 m->crtc_htotal - m->crtc_hdisplay - 0xe0);
1895                         hdmi_set_reg(tg->hact_sz, 2, m->crtc_hdisplay + 0xe0);
1896                 }
1897         }
1898 }
1899
1900 static void hdmi_mode_set(void *ctx, struct drm_display_mode *mode)
1901 {
1902         struct hdmi_context *hdata = ctx;
1903
1904         DRM_DEBUG_KMS("[MODE:%d:%s]\n", DRM_BASE_ID(mode), mode->name);
1905
1906         if (hdata->is_v13)
1907                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1908         else
1909                 hdmi_v14_mode_set(hdata, mode);
1910 }
1911
1912 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
1913                                u8 reg, u8 mask, u8 val)
1914 {
1915         int ret;
1916         u8 buffer[2];
1917
1918         buffer[0] = reg;
1919         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
1920         reg_cache[reg] = buffer[1];
1921
1922         ret = i2c_master_send(client, buffer, 2);
1923         if (ret != 2)
1924                 return -EIO;
1925
1926         return 0;
1927 }
1928
1929 static int hdmiphy_s_power(struct i2c_client *client, bool on)
1930 {
1931         u8 reg_cache[32] = { 0 };
1932         u8 buffer[2];
1933         int ret;
1934
1935         DRM_DEBUG_KMS("%s\n", on ? "on" : "off");
1936
1937         /* Cache all 32 registers to make the code below faster */
1938         buffer[0] = 0x0;
1939         ret = i2c_master_send(client, buffer, 1);
1940         if (ret != 1) {
1941                 ret = -EIO;
1942                 goto exit;
1943         }
1944         ret = i2c_master_recv(client, reg_cache, 32);
1945         if (ret != 32) {
1946                 ret = -EIO;
1947                 goto exit;
1948         }
1949
1950         /* Go to/from configuration from/to operation mode */
1951         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
1952                                   on ? 0x80 : 0x00);
1953         if (ret)
1954                 goto exit;
1955
1956         /*
1957          * Turn off undocumented "oscpad" if !on; it turns on again in
1958          * hdmiphy_conf_apply()
1959          */
1960         if (!on)
1961                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
1962                 if (ret)
1963                         goto exit;
1964
1965         /* Disable powerdown if on; enable if !on */
1966         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
1967                                   on ? 0 : ~0);
1968         if (ret)
1969                 goto exit;
1970         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
1971                                   on ? 0 : ~0);
1972         if (ret)
1973                 goto exit;
1974
1975         /*
1976          * Turn off bit 3 of reg 4 if !on; it turns on again in
1977          * hdmiphy_conf_apply().  It's unclear what this bit does.
1978          */
1979         if (!on)
1980                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
1981                 if (ret)
1982                         goto exit;
1983
1984 exit:
1985         /* Don't expect any errors so just do a single warn */
1986         WARN_ON(ret);
1987
1988         return ret;
1989 }
1990
1991 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1992 {
1993         struct hdmi_resources *res = &hdata->res;
1994
1995         hdata->is_hdmi_powered_on = true;
1996         hdmi_cfg_hpd(hdata, false);
1997
1998         /* irq change by TV power status */
1999         if (hdata->curr_irq == hdata->internal_irq)
2000                 return;
2001
2002         disable_irq(hdata->curr_irq);
2003
2004         hdata->curr_irq = hdata->internal_irq;
2005
2006         enable_irq(hdata->curr_irq);
2007
2008         /* turn HDMI power on */
2009         regulator_bulk_enable(res->regul_count, res->regul_bulk);
2010
2011         /* power-on hdmi clocks */
2012         clk_enable(res->hdmiphy);
2013
2014         hdmiphy_s_power(hdata->hdmiphy_port, 1);
2015         hdmiphy_conf_reset(hdata);
2016         hdmi_conf_reset(hdata);
2017         hdmi_conf_init(hdata);
2018         if (!hdata->is_soc_exynos5)
2019                 hdmi_audio_init(hdata);
2020         hdmi_conf_apply(hdata);
2021 }
2022
2023 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2024 {
2025         struct hdmi_resources *res = &hdata->res;
2026
2027         hdmi_cfg_hpd(hdata, true);
2028
2029         if (hdata->curr_irq == hdata->external_irq)
2030                 return;
2031
2032         disable_irq(hdata->curr_irq);
2033         hdata->curr_irq = hdata->external_irq;
2034
2035         enable_irq(hdata->curr_irq);
2036         hdata->is_hdmi_powered_on = false;
2037
2038         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2039         hdmiphy_conf_reset(hdata);
2040
2041         /* power-off hdmi clocks */
2042         clk_disable(res->hdmiphy);
2043
2044         /* turn HDMI power off */
2045         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2046 }
2047
2048 static int hdmi_dpms(void *ctx, int mode)
2049 {
2050         struct hdmi_context *hdata = ctx;
2051
2052         DRM_DEBUG_KMS("[DPMS:%s]\n", drm_get_dpms_name(mode));
2053
2054         switch (mode) {
2055         case DRM_MODE_DPMS_ON:
2056                 if (!hdata->is_hdmi_powered_on)
2057                         hdmi_resource_poweron(hdata);
2058                 hdmi_enable_video(hdata);
2059                 break;
2060         case DRM_MODE_DPMS_STANDBY:
2061                 hdmi_disable_video(hdata);
2062                 break;
2063         case DRM_MODE_DPMS_OFF:
2064         case DRM_MODE_DPMS_SUSPEND:
2065                 if (hdata->is_hdmi_powered_on)
2066                         hdmi_resource_poweroff(hdata);
2067                 break;
2068         default:
2069                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2070                 break;
2071         }
2072
2073         return 0;
2074 }
2075
2076 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
2077 {
2078         struct hdmi_context *hdata = ctx;
2079
2080         DRM_DEBUG_KMS("[DEV:%s]\n", drm_dev->devname);
2081
2082         hdata->drm_dev = drm_dev;
2083
2084         return 0;
2085 }
2086
2087 static struct exynos_panel_ops hdmi_ops = {
2088         /* display */
2089         .subdrv_probe   = hdmi_subdrv_probe,
2090         .is_connected   = hdmi_is_connected,
2091         .get_edid       = hdmi_get_edid,
2092         .check_timing   = hdmi_check_timing,
2093         .dpms           = hdmi_dpms,
2094
2095         /* manager */
2096         .mode_fixup     = hdmi_mode_fixup,
2097         .mode_set       = hdmi_mode_set,
2098 };
2099
2100 /*
2101  * Handle hotplug events outside the interrupt handler proper.
2102  */
2103 static void hdmi_hotplug_timer_func(unsigned long data)
2104 {
2105         struct hdmi_context *hdata = (struct hdmi_context *)data;
2106
2107         drm_helper_hpd_irq_event(hdata->drm_dev);
2108 }
2109
2110 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
2111 {
2112         struct hdmi_context *hdata = arg;
2113         u32 intc_flag, time_ms = HOTPLUG_DEBOUNCE_MS;
2114
2115         if (hdata->is_hdmi_powered_on) {
2116                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
2117                 /* clearing flags for HPD plug/unplug */
2118                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2119                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
2120                                 hdata->hpd_handle);
2121                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2122                                 HDMI_INTC_FLAG_HPD_UNPLUG);
2123                 }
2124                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2125                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
2126                                 hdata->hpd_handle);
2127                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2128                                 HDMI_INTC_FLAG_HPD_PLUG);
2129                 }
2130
2131                 /*
2132                  * No need to debounce if we're powered on, the hardware
2133                  * has already done it for us.
2134                  */
2135                 time_ms = 0;
2136         }
2137
2138         if (hdata->drm_dev && hdata->hpd_handle)
2139                 mod_timer(&hdata->hotplug_timer,
2140                                 jiffies + msecs_to_jiffies(time_ms));
2141
2142         return IRQ_HANDLED;
2143 }
2144
2145 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2146 {
2147         struct device *dev = hdata->dev;
2148         struct hdmi_resources *res = &hdata->res;
2149 #ifndef CONFIG_ARCH_EXYNOS5
2150         static char *supply[] = {
2151                 "hdmi-en",
2152                 "vdd",
2153                 "vdd_osc",
2154                 "vdd_pll",
2155         };
2156         int i, ret;
2157 #endif
2158
2159         DRM_DEBUG_KMS("HDMI resource init\n");
2160
2161         memset(res, 0, sizeof *res);
2162
2163         /* get clocks, power */
2164         res->hdmi = clk_get(dev, "hdmi");
2165         if (IS_ERR_OR_NULL(res->hdmi)) {
2166                 DRM_ERROR("failed to get clock 'hdmi'\n");
2167                 goto fail;
2168         }
2169         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
2170         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
2171                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2172                 goto fail;
2173         }
2174         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2175         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2176                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2177                 goto fail;
2178         }
2179         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2180         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2181                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2182                 goto fail;
2183         }
2184         res->hdmiphy = clk_get(dev, "hdmiphy");
2185         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2186                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2187                 goto fail;
2188         }
2189
2190         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2191
2192 #ifndef CONFIG_ARCH_EXYNOS5
2193         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2194                 sizeof res->regul_bulk[0], GFP_KERNEL);
2195         if (!res->regul_bulk) {
2196                 DRM_ERROR("failed to get memory for regulators\n");
2197                 goto fail;
2198         }
2199         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2200                 res->regul_bulk[i].supply = supply[i];
2201                 res->regul_bulk[i].consumer = NULL;
2202         }
2203         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2204         if (ret) {
2205                 DRM_ERROR("failed to get regulators\n");
2206                 goto fail;
2207         }
2208         res->regul_count = ARRAY_SIZE(supply);
2209 #endif
2210         /* TODO:
2211          * These clocks also should be added in
2212          * runtime resume and runtime suspend
2213          */
2214         clk_enable(res->hdmi);
2215         clk_enable(res->sclk_hdmi);
2216
2217         return 0;
2218 fail:
2219         DRM_ERROR("HDMI resource init - failed\n");
2220         return -ENODEV;
2221 }
2222
2223 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2224 {
2225         struct hdmi_resources *res = &hdata->res;
2226
2227         regulator_bulk_free(res->regul_count, res->regul_bulk);
2228         /* kfree is NULL-safe */
2229         kfree(res->regul_bulk);
2230         if (!IS_ERR_OR_NULL(res->hdmiphy))
2231                 clk_put(res->hdmiphy);
2232         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2233                 clk_put(res->sclk_hdmiphy);
2234         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2235                 clk_put(res->sclk_pixel);
2236         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2237                 clk_put(res->sclk_hdmi);
2238         if (!IS_ERR_OR_NULL(res->hdmi))
2239                 clk_put(res->hdmi);
2240         memset(res, 0, sizeof *res);
2241
2242         return 0;
2243 }
2244
2245 struct platform_device *hdmi_audio_device;
2246
2247 int hdmi_register_audio_device(struct platform_device *pdev)
2248 {
2249         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2250         struct platform_device *audio_dev;
2251         int ret;
2252
2253         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2254
2255         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2256         if (!audio_dev) {
2257                 DRM_ERROR("hdmi audio device allocation failed.\n");
2258                 ret = -ENOMEM;
2259                 goto err;
2260         }
2261
2262         ret = platform_device_add_resources(audio_dev, pdev->resource,
2263                         pdev->num_resources);
2264         if (ret) {
2265                 ret = -ENOMEM;
2266                 goto err_device;
2267         }
2268
2269         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2270         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2271
2272         ret = platform_device_add(audio_dev);
2273         if (ret) {
2274                 DRM_ERROR("hdmi audio device add failed.\n");
2275                 goto err_device;
2276         }
2277
2278         hdmi_audio_device = audio_dev;
2279         return 0;
2280
2281 err_device:
2282         platform_device_put(audio_dev);
2283
2284 err:
2285         return ret;
2286 }
2287
2288 void hdmi_unregister_audio_device(void)
2289 {
2290         DRM_DEBUG_KMS("\n");
2291         platform_device_unregister(hdmi_audio_device);
2292 }
2293
2294 static int __devinit hdmi_probe(struct platform_device *pdev)
2295 {
2296         struct device *dev = &pdev->dev;
2297         struct hdmi_context *hdata;
2298         struct exynos_drm_hdmi_pdata *pdata;
2299         struct resource *res;
2300         struct device_node *ddc_node, *phy_node;
2301         int ret;
2302         enum of_gpio_flags flags;
2303
2304         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2305
2306         pdata = pdev->dev.platform_data;
2307         if (!pdata) {
2308                 DRM_ERROR("no platform data specified\n");
2309                 return -EINVAL;
2310         }
2311
2312         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2313         if (!hdata) {
2314                 DRM_ERROR("out of memory\n");
2315                 return -ENOMEM;
2316         }
2317
2318         platform_set_drvdata(pdev, hdata);
2319
2320         hdata->is_v13 = pdata->is_v13;
2321         hdata->default_win = pdata->default_win;
2322         hdata->default_timing = &pdata->timing;
2323         hdata->default_bpp = pdata->bpp;
2324         hdata->dev = dev;
2325         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2326                 "samsung,exynos5-hdmi");
2327
2328         ret = hdmi_resources_init(hdata);
2329         if (ret) {
2330                 ret = -EINVAL;
2331                 goto err_data;
2332         }
2333
2334         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2335         if (!res) {
2336                 DRM_ERROR("failed to find registers\n");
2337                 ret = -ENOENT;
2338                 goto err_resource;
2339         }
2340
2341         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2342                                            dev_name(dev));
2343         if (!hdata->regs_res) {
2344                 DRM_ERROR("failed to claim register region\n");
2345                 ret = -ENOENT;
2346                 goto err_resource;
2347         }
2348
2349         hdata->regs = ioremap(res->start, resource_size(res));
2350         if (!hdata->regs) {
2351                 DRM_ERROR("failed to map registers\n");
2352                 ret = -ENXIO;
2353                 goto err_req_region;
2354         }
2355
2356         /* DDC i2c driver */
2357         ddc_node = of_find_node_by_name(NULL, "exynos_ddc");
2358         if (!ddc_node) {
2359                 DRM_ERROR("Failed to find ddc node in device tree\n");
2360                 ret = -ENODEV;
2361                 goto err_iomap;
2362         }
2363         hdata->ddc_port = of_find_i2c_device_by_node(ddc_node);
2364         if (!hdata->ddc_port) {
2365                 DRM_ERROR("Failed to get ddc i2c client by node\n");
2366                 ret = -ENODEV;
2367                 goto err_iomap;
2368         }
2369
2370         /* hdmiphy i2c driver */
2371         phy_node = of_find_node_by_name(NULL, "exynos_hdmiphy");
2372         if (!phy_node) {
2373                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2374                 ret = -ENODEV;
2375                 goto err_ddc;
2376         }
2377         hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2378         if (!hdata->hdmiphy_port) {
2379                 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2380                 ret = -ENODEV;
2381                 goto err_ddc;
2382         }
2383
2384         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2385         if (res == NULL) {
2386                 DRM_ERROR("get interrupt resource failed.\n");
2387                 ret = -ENXIO;
2388                 goto err_hdmiphy;
2389         }
2390
2391         hdata->internal_irq = res->start;
2392
2393         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2394                                 "hpd-gpio", 0, &flags);
2395
2396         if (!gpio_is_valid(hdata->hpd_gpio)) {
2397                 DRM_ERROR("failed to get hpd gpio.");
2398                 ret = -EINVAL;
2399                 goto err_hdmiphy;
2400         }
2401
2402         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2403
2404         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2405                         IRQF_SHARED, "int_hdmi", hdata);
2406         if (ret) {
2407                 DRM_ERROR("request int interrupt failed.\n");
2408                 goto err_hdmiphy;
2409         }
2410         disable_irq(hdata->internal_irq);
2411
2412         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2413                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2414                 hdata);
2415         if (ret) {
2416                 DRM_ERROR("request ext interrupt failed.\n");
2417                 goto err_int_irq;
2418         }
2419         disable_irq(hdata->external_irq);
2420
2421         setup_timer(&hdata->hotplug_timer, hdmi_hotplug_timer_func,
2422                         (unsigned long)hdata);
2423
2424         if (of_device_is_compatible(dev->of_node,
2425                 "samsung,exynos5-hdmi")) {
2426                 ret = hdmi_register_audio_device(pdev);
2427                 if (ret) {
2428                         DRM_ERROR("hdmi-audio device registering failed.\n");
2429                         goto err_ext_irq;
2430                 }
2431         }
2432
2433         hdmi_resource_poweron(hdata);
2434
2435         if (!hdmi_is_connected(hdata)) {
2436                 hdmi_resource_poweroff(hdata);
2437                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2438         }
2439
2440         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2441                         hdata);
2442
2443         return 0;
2444
2445 err_ext_irq:
2446         free_irq(hdata->external_irq, hdata);
2447 err_int_irq:
2448         free_irq(hdata->internal_irq, hdata);
2449 err_hdmiphy:
2450         put_device(&hdata->hdmiphy_port->dev);
2451 err_ddc:
2452         put_device(&hdata->ddc_port->dev);
2453 err_iomap:
2454         iounmap(hdata->regs);
2455 err_req_region:
2456         release_mem_region(hdata->regs_res->start,
2457                         resource_size(hdata->regs_res));
2458 err_resource:
2459         hdmi_resources_cleanup(hdata);
2460 err_data:
2461         kfree(hdata);
2462         return ret;
2463 }
2464
2465 static int __devexit hdmi_remove(struct platform_device *pdev)
2466 {
2467         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2468         struct hdmi_resources *res = &hdata->res;
2469
2470         DRM_DEBUG_KMS("[PDEV:%s]\n", pdev->name);
2471
2472         hdmi_resource_poweroff(hdata);
2473
2474         hdmi_unregister_audio_device();
2475
2476         disable_irq(hdata->curr_irq);
2477         free_irq(hdata->internal_irq, hdata);
2478         free_irq(hdata->external_irq, hdata);
2479
2480         del_timer(&hdata->hotplug_timer);
2481
2482         clk_disable(res->hdmi);
2483         clk_disable(res->sclk_hdmi);
2484         hdmi_resources_cleanup(hdata);
2485
2486         iounmap(hdata->regs);
2487
2488         release_mem_region(hdata->regs_res->start,
2489                         resource_size(hdata->regs_res));
2490
2491         put_device(&hdata->hdmiphy_port->dev);
2492         put_device(&hdata->ddc_port->dev);
2493
2494         kfree(hdata);
2495
2496         return 0;
2497 }
2498
2499 struct platform_driver hdmi_driver = {
2500         .probe          = hdmi_probe,
2501         .remove         = __devexit_p(hdmi_remove),
2502         .driver         = {
2503 #ifdef CONFIG_ARCH_EXYNOS5
2504                 .name   = "exynos5-hdmi",
2505 #else
2506                 .name   = "exynos4-hdmi",
2507 #endif
2508                 .owner  = THIS_MODULE,
2509         },
2510 };