2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
19 #include "drm_crtc_helper.h"
22 #include "regs-hdmi.h"
24 #include <linux/kernel.h>
25 #include <linux/spinlock.h>
26 #include <linux/wait.h>
27 #include <linux/i2c.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/irq.h>
32 #include <linux/delay.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/clk.h>
35 #include <linux/regulator/consumer.h>
37 #include <drm/exynos_drm.h>
39 #include "exynos_drm_drv.h"
40 #include "exynos_drm_hdmi.h"
42 #include "exynos_hdmi.h"
44 #define MAX_WIDTH 1920
45 #define MAX_HEIGHT 1080
46 #define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev))
48 struct hdmi_resources {
50 struct clk *sclk_hdmi;
51 struct clk *sclk_pixel;
52 struct clk *sclk_hdmiphy;
54 struct regulator_bulk_data *regul_bulk;
79 struct hdmi_core_regs {
92 u8 v_sync_line_bef_2[2];
93 u8 v_sync_line_bef_1[2];
94 u8 v_sync_line_aft_2[2];
95 u8 v_sync_line_aft_1[2];
96 u8 v_sync_line_aft_pxl_2[2];
97 u8 v_sync_line_aft_pxl_1[2];
98 u8 v_blank_f2[2]; /* for 3D mode */
99 u8 v_blank_f3[2]; /* for 3D mode */
100 u8 v_blank_f4[2]; /* for 3D mode */
101 u8 v_blank_f5[2]; /* for 3D mode */
102 u8 v_sync_line_aft_3[2];
103 u8 v_sync_line_aft_4[2];
104 u8 v_sync_line_aft_5[2];
105 u8 v_sync_line_aft_6[2];
106 u8 v_sync_line_aft_pxl_3[2];
107 u8 v_sync_line_aft_pxl_4[2];
108 u8 v_sync_line_aft_pxl_5[2];
109 u8 v_sync_line_aft_pxl_6[2];
118 struct hdmi_mode_conf {
120 struct hdmi_core_regs core;
121 struct hdmi_tg_regs tg;
125 struct hdmi_context {
127 struct drm_device *drm_dev;
128 struct fb_videomode *default_timing;
129 struct hdmi_mode_conf mode_conf;
130 unsigned int is_v13:1;
131 unsigned int default_win;
132 unsigned int default_bpp;
139 struct resource *regs_res;
142 struct workqueue_struct *wq;
143 struct work_struct hotplug_work;
145 struct i2c_client *ddc_port;
146 struct i2c_client *hdmiphy_port;
148 /* current hdmiphy conf index */
151 struct hdmi_resources res;
155 /* HDMI Version 1.3 */
156 static const u8 hdmiphy_v13_conf27[32] = {
157 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
158 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
159 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
160 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
163 static const u8 hdmiphy_v13_conf27_027[32] = {
164 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
165 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
166 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
167 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
170 static const u8 hdmiphy_v13_conf74_175[32] = {
171 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
172 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
173 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
174 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
177 static const u8 hdmiphy_v13_conf74_25[32] = {
178 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
179 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
180 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
181 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
184 static const u8 hdmiphy_v13_conf148_5[32] = {
185 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
186 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
187 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
188 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
191 struct hdmi_v13_tg_regs {
223 struct hdmi_v13_core_regs {
236 struct hdmi_v13_preset_conf {
237 struct hdmi_v13_core_regs core;
238 struct hdmi_v13_tg_regs tg;
241 struct hdmi_v13_conf {
246 const u8 *hdmiphy_data;
247 const struct hdmi_v13_preset_conf *conf;
250 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
252 .h_blank = {0x8a, 0x00},
253 .v_blank = {0x0d, 0x6a, 0x01},
254 .h_v_line = {0x0d, 0xa2, 0x35},
256 .int_pro_mode = {0x00},
257 .v_blank_f = {0x00, 0x00, 0x00},
258 .h_sync_gen = {0x0e, 0x30, 0x11},
259 .v_sync_gen1 = {0x0f, 0x90, 0x00},
260 /* other don't care */
264 0x5a, 0x03, /* h_fsz */
265 0x8a, 0x00, 0xd0, 0x02, /* hact */
266 0x0d, 0x02, /* v_fsz */
267 0x01, 0x00, 0x33, 0x02, /* vsync */
268 0x2d, 0x00, 0xe0, 0x01, /* vact */
269 0x33, 0x02, /* field_chg */
270 0x49, 0x02, /* vact_st2 */
271 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
272 0x01, 0x00, 0x33, 0x02, /* field top/bot */
276 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
278 .h_blank = {0x72, 0x01},
279 .v_blank = {0xee, 0xf2, 0x00},
280 .h_v_line = {0xee, 0x22, 0x67},
282 .int_pro_mode = {0x00},
283 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
284 .h_sync_gen = {0x6c, 0x50, 0x02},
285 .v_sync_gen1 = {0x0a, 0x50, 0x00},
286 .v_sync_gen2 = {0x01, 0x10, 0x00},
287 .v_sync_gen3 = {0x01, 0x10, 0x00},
288 /* other don't care */
292 0x72, 0x06, /* h_fsz */
293 0x71, 0x01, 0x01, 0x05, /* hact */
294 0xee, 0x02, /* v_fsz */
295 0x01, 0x00, 0x33, 0x02, /* vsync */
296 0x1e, 0x00, 0xd0, 0x02, /* vact */
297 0x33, 0x02, /* field_chg */
298 0x49, 0x02, /* vact_st2 */
299 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
300 0x01, 0x00, 0x33, 0x02, /* field top/bot */
304 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
306 .h_blank = {0xd0, 0x02},
307 .v_blank = {0x32, 0xB2, 0x00},
308 .h_v_line = {0x65, 0x04, 0xa5},
310 .int_pro_mode = {0x01},
311 .v_blank_f = {0x49, 0x2A, 0x23},
312 .h_sync_gen = {0x0E, 0xEA, 0x08},
313 .v_sync_gen1 = {0x07, 0x20, 0x00},
314 .v_sync_gen2 = {0x39, 0x42, 0x23},
315 .v_sync_gen3 = {0x38, 0x87, 0x73},
316 /* other don't care */
320 0x50, 0x0A, /* h_fsz */
321 0xCF, 0x02, 0x81, 0x07, /* hact */
322 0x65, 0x04, /* v_fsz */
323 0x01, 0x00, 0x33, 0x02, /* vsync */
324 0x16, 0x00, 0x1c, 0x02, /* vact */
325 0x33, 0x02, /* field_chg */
326 0x49, 0x02, /* vact_st2 */
327 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
328 0x01, 0x00, 0x33, 0x02, /* field top/bot */
332 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
334 .h_blank = {0xd0, 0x02},
335 .v_blank = {0x65, 0x6c, 0x01},
336 .h_v_line = {0x65, 0x04, 0xa5},
338 .int_pro_mode = {0x00},
339 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
340 .h_sync_gen = {0x0e, 0xea, 0x08},
341 .v_sync_gen1 = {0x09, 0x40, 0x00},
342 .v_sync_gen2 = {0x01, 0x10, 0x00},
343 .v_sync_gen3 = {0x01, 0x10, 0x00},
344 /* other don't care */
348 0x50, 0x0A, /* h_fsz */
349 0xCF, 0x02, 0x81, 0x07, /* hact */
350 0x65, 0x04, /* v_fsz */
351 0x01, 0x00, 0x33, 0x02, /* vsync */
352 0x2d, 0x00, 0x38, 0x04, /* vact */
353 0x33, 0x02, /* field_chg */
354 0x48, 0x02, /* vact_st2 */
355 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
356 0x01, 0x00, 0x33, 0x02, /* field top/bot */
360 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
362 .h_blank = {0x18, 0x01},
363 .v_blank = {0x32, 0xB2, 0x00},
364 .h_v_line = {0x65, 0x84, 0x89},
366 .int_pro_mode = {0x01},
367 .v_blank_f = {0x49, 0x2A, 0x23},
368 .h_sync_gen = {0x56, 0x08, 0x02},
369 .v_sync_gen1 = {0x07, 0x20, 0x00},
370 .v_sync_gen2 = {0x39, 0x42, 0x23},
371 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
372 /* other don't care */
376 0x98, 0x08, /* h_fsz */
377 0x17, 0x01, 0x81, 0x07, /* hact */
378 0x65, 0x04, /* v_fsz */
379 0x01, 0x00, 0x33, 0x02, /* vsync */
380 0x16, 0x00, 0x1c, 0x02, /* vact */
381 0x33, 0x02, /* field_chg */
382 0x49, 0x02, /* vact_st2 */
383 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
384 0x01, 0x00, 0x33, 0x02, /* field top/bot */
388 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
390 .h_blank = {0x18, 0x01},
391 .v_blank = {0x65, 0x6c, 0x01},
392 .h_v_line = {0x65, 0x84, 0x89},
394 .int_pro_mode = {0x00},
395 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
396 .h_sync_gen = {0x56, 0x08, 0x02},
397 .v_sync_gen1 = {0x09, 0x40, 0x00},
398 .v_sync_gen2 = {0x01, 0x10, 0x00},
399 .v_sync_gen3 = {0x01, 0x10, 0x00},
400 /* other don't care */
404 0x98, 0x08, /* h_fsz */
405 0x17, 0x01, 0x81, 0x07, /* hact */
406 0x65, 0x04, /* v_fsz */
407 0x01, 0x00, 0x33, 0x02, /* vsync */
408 0x2d, 0x00, 0x38, 0x04, /* vact */
409 0x33, 0x02, /* field_chg */
410 0x48, 0x02, /* vact_st2 */
411 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
412 0x01, 0x00, 0x33, 0x02, /* field top/bot */
416 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
417 { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
418 { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
419 { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
420 { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
421 { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
422 &hdmi_v13_conf_1080p50 },
423 { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
424 { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
425 &hdmi_v13_conf_1080p60 },
428 struct hdmiphy_config {
433 static const struct hdmiphy_config phy_configs[] = {
435 .pixel_clock = 27000000,
437 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
438 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
439 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
440 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
444 .pixel_clock = 27027000,
446 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
447 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
448 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
449 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
453 .pixel_clock = 74176000,
455 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
456 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
457 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
458 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
462 .pixel_clock = 74250000,
464 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
465 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
466 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
467 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
471 .pixel_clock = 148500000,
473 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
474 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
475 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
476 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
481 struct hdmi_infoframe {
482 enum HDMI_PACKET_TYPE type;
487 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
489 return readl(hdata->regs + reg_id);
492 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
493 u32 reg_id, u8 value)
495 writeb(value, hdata->regs + reg_id);
498 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
499 u32 reg_id, u32 value, u32 mask)
501 u32 old = readl(hdata->regs + reg_id);
502 value = (value & mask) | (old & ~mask);
503 writel(value, hdata->regs + reg_id);
506 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
508 #define DUMPREG(reg_id) \
509 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
510 readl(hdata->regs + reg_id))
511 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
512 DUMPREG(HDMI_INTC_FLAG);
513 DUMPREG(HDMI_INTC_CON);
514 DUMPREG(HDMI_HPD_STATUS);
515 DUMPREG(HDMI_V13_PHY_RSTOUT);
516 DUMPREG(HDMI_V13_PHY_VPLL);
517 DUMPREG(HDMI_V13_PHY_CMU);
518 DUMPREG(HDMI_V13_CORE_RSTOUT);
520 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
524 DUMPREG(HDMI_SYS_STATUS);
525 DUMPREG(HDMI_V13_PHY_STATUS);
526 DUMPREG(HDMI_STATUS_EN);
528 DUMPREG(HDMI_MODE_SEL);
529 DUMPREG(HDMI_V13_HPD_GEN);
530 DUMPREG(HDMI_V13_DC_CONTROL);
531 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
533 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
534 DUMPREG(HDMI_H_BLANK_0);
535 DUMPREG(HDMI_H_BLANK_1);
536 DUMPREG(HDMI_V13_V_BLANK_0);
537 DUMPREG(HDMI_V13_V_BLANK_1);
538 DUMPREG(HDMI_V13_V_BLANK_2);
539 DUMPREG(HDMI_V13_H_V_LINE_0);
540 DUMPREG(HDMI_V13_H_V_LINE_1);
541 DUMPREG(HDMI_V13_H_V_LINE_2);
542 DUMPREG(HDMI_VSYNC_POL);
543 DUMPREG(HDMI_INT_PRO_MODE);
544 DUMPREG(HDMI_V13_V_BLANK_F_0);
545 DUMPREG(HDMI_V13_V_BLANK_F_1);
546 DUMPREG(HDMI_V13_V_BLANK_F_2);
547 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
548 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
549 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
550 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
551 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
552 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
553 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
554 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
555 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
556 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
557 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
558 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
560 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
561 DUMPREG(HDMI_TG_CMD);
562 DUMPREG(HDMI_TG_H_FSZ_L);
563 DUMPREG(HDMI_TG_H_FSZ_H);
564 DUMPREG(HDMI_TG_HACT_ST_L);
565 DUMPREG(HDMI_TG_HACT_ST_H);
566 DUMPREG(HDMI_TG_HACT_SZ_L);
567 DUMPREG(HDMI_TG_HACT_SZ_H);
568 DUMPREG(HDMI_TG_V_FSZ_L);
569 DUMPREG(HDMI_TG_V_FSZ_H);
570 DUMPREG(HDMI_TG_VSYNC_L);
571 DUMPREG(HDMI_TG_VSYNC_H);
572 DUMPREG(HDMI_TG_VSYNC2_L);
573 DUMPREG(HDMI_TG_VSYNC2_H);
574 DUMPREG(HDMI_TG_VACT_ST_L);
575 DUMPREG(HDMI_TG_VACT_ST_H);
576 DUMPREG(HDMI_TG_VACT_SZ_L);
577 DUMPREG(HDMI_TG_VACT_SZ_H);
578 DUMPREG(HDMI_TG_FIELD_CHG_L);
579 DUMPREG(HDMI_TG_FIELD_CHG_H);
580 DUMPREG(HDMI_TG_VACT_ST2_L);
581 DUMPREG(HDMI_TG_VACT_ST2_H);
582 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
583 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
584 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
585 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
586 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
587 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
588 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
589 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
593 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
597 #define DUMPREG(reg_id) \
598 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
599 readl(hdata->regs + reg_id))
601 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
602 DUMPREG(HDMI_INTC_CON);
603 DUMPREG(HDMI_INTC_FLAG);
604 DUMPREG(HDMI_HPD_STATUS);
605 DUMPREG(HDMI_INTC_CON_1);
606 DUMPREG(HDMI_INTC_FLAG_1);
607 DUMPREG(HDMI_PHY_STATUS_0);
608 DUMPREG(HDMI_PHY_STATUS_PLL);
609 DUMPREG(HDMI_PHY_CON_0);
610 DUMPREG(HDMI_PHY_RSTOUT);
611 DUMPREG(HDMI_PHY_VPLL);
612 DUMPREG(HDMI_PHY_CMU);
613 DUMPREG(HDMI_CORE_RSTOUT);
615 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
619 DUMPREG(HDMI_SYS_STATUS);
620 DUMPREG(HDMI_PHY_STATUS_0);
621 DUMPREG(HDMI_STATUS_EN);
623 DUMPREG(HDMI_MODE_SEL);
624 DUMPREG(HDMI_ENC_EN);
625 DUMPREG(HDMI_DC_CONTROL);
626 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
628 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
629 DUMPREG(HDMI_H_BLANK_0);
630 DUMPREG(HDMI_H_BLANK_1);
631 DUMPREG(HDMI_V2_BLANK_0);
632 DUMPREG(HDMI_V2_BLANK_1);
633 DUMPREG(HDMI_V1_BLANK_0);
634 DUMPREG(HDMI_V1_BLANK_1);
635 DUMPREG(HDMI_V_LINE_0);
636 DUMPREG(HDMI_V_LINE_1);
637 DUMPREG(HDMI_H_LINE_0);
638 DUMPREG(HDMI_H_LINE_1);
639 DUMPREG(HDMI_HSYNC_POL);
641 DUMPREG(HDMI_VSYNC_POL);
642 DUMPREG(HDMI_INT_PRO_MODE);
643 DUMPREG(HDMI_V_BLANK_F0_0);
644 DUMPREG(HDMI_V_BLANK_F0_1);
645 DUMPREG(HDMI_V_BLANK_F1_0);
646 DUMPREG(HDMI_V_BLANK_F1_1);
648 DUMPREG(HDMI_H_SYNC_START_0);
649 DUMPREG(HDMI_H_SYNC_START_1);
650 DUMPREG(HDMI_H_SYNC_END_0);
651 DUMPREG(HDMI_H_SYNC_END_1);
653 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
654 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
655 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
656 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
658 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
659 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
660 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
661 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
663 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
664 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
665 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
666 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
668 DUMPREG(HDMI_V_BLANK_F2_0);
669 DUMPREG(HDMI_V_BLANK_F2_1);
670 DUMPREG(HDMI_V_BLANK_F3_0);
671 DUMPREG(HDMI_V_BLANK_F3_1);
672 DUMPREG(HDMI_V_BLANK_F4_0);
673 DUMPREG(HDMI_V_BLANK_F4_1);
674 DUMPREG(HDMI_V_BLANK_F5_0);
675 DUMPREG(HDMI_V_BLANK_F5_1);
677 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
678 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
679 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
680 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
681 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
682 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
683 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
684 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
686 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
687 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
688 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
689 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
690 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
691 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
692 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
693 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
695 DUMPREG(HDMI_VACT_SPACE_1_0);
696 DUMPREG(HDMI_VACT_SPACE_1_1);
697 DUMPREG(HDMI_VACT_SPACE_2_0);
698 DUMPREG(HDMI_VACT_SPACE_2_1);
699 DUMPREG(HDMI_VACT_SPACE_3_0);
700 DUMPREG(HDMI_VACT_SPACE_3_1);
701 DUMPREG(HDMI_VACT_SPACE_4_0);
702 DUMPREG(HDMI_VACT_SPACE_4_1);
703 DUMPREG(HDMI_VACT_SPACE_5_0);
704 DUMPREG(HDMI_VACT_SPACE_5_1);
705 DUMPREG(HDMI_VACT_SPACE_6_0);
706 DUMPREG(HDMI_VACT_SPACE_6_1);
708 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
709 DUMPREG(HDMI_TG_CMD);
710 DUMPREG(HDMI_TG_H_FSZ_L);
711 DUMPREG(HDMI_TG_H_FSZ_H);
712 DUMPREG(HDMI_TG_HACT_ST_L);
713 DUMPREG(HDMI_TG_HACT_ST_H);
714 DUMPREG(HDMI_TG_HACT_SZ_L);
715 DUMPREG(HDMI_TG_HACT_SZ_H);
716 DUMPREG(HDMI_TG_V_FSZ_L);
717 DUMPREG(HDMI_TG_V_FSZ_H);
718 DUMPREG(HDMI_TG_VSYNC_L);
719 DUMPREG(HDMI_TG_VSYNC_H);
720 DUMPREG(HDMI_TG_VSYNC2_L);
721 DUMPREG(HDMI_TG_VSYNC2_H);
722 DUMPREG(HDMI_TG_VACT_ST_L);
723 DUMPREG(HDMI_TG_VACT_ST_H);
724 DUMPREG(HDMI_TG_VACT_SZ_L);
725 DUMPREG(HDMI_TG_VACT_SZ_H);
726 DUMPREG(HDMI_TG_FIELD_CHG_L);
727 DUMPREG(HDMI_TG_FIELD_CHG_H);
728 DUMPREG(HDMI_TG_VACT_ST2_L);
729 DUMPREG(HDMI_TG_VACT_ST2_H);
730 DUMPREG(HDMI_TG_VACT_ST3_L);
731 DUMPREG(HDMI_TG_VACT_ST3_H);
732 DUMPREG(HDMI_TG_VACT_ST4_L);
733 DUMPREG(HDMI_TG_VACT_ST4_H);
734 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
735 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
736 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
737 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
738 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
739 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
740 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
741 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
744 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
745 DUMPREG(HDMI_AVI_CON);
746 DUMPREG(HDMI_AVI_HEADER0);
747 DUMPREG(HDMI_AVI_HEADER1);
748 DUMPREG(HDMI_AVI_HEADER2);
749 DUMPREG(HDMI_AVI_CHECK_SUM);
750 DUMPREG(HDMI_VSI_CON);
751 DUMPREG(HDMI_VSI_HEADER0);
752 DUMPREG(HDMI_VSI_HEADER1);
753 DUMPREG(HDMI_VSI_HEADER2);
754 for (i = 0; i < 7; ++i)
755 DUMPREG(HDMI_VSI_DATA(i));
760 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
763 hdmi_v13_regs_dump(hdata, prefix);
765 hdmi_v14_regs_dump(hdata, prefix);
768 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
772 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
773 if (hdmi_v13_confs[i].width == mode->hdisplay &&
774 hdmi_v13_confs[i].height == mode->vdisplay &&
775 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
776 hdmi_v13_confs[i].interlace ==
777 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
784 static bool hdmi_is_connected(void *ctx)
786 struct hdmi_context *hdata = ctx;
787 u32 val = hdmi_reg_read(hdata, HDMI_HPD_STATUS);
795 static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
798 struct edid *raw_edid;
799 struct hdmi_context *hdata = ctx;
801 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
803 if (!hdata->ddc_port)
806 raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
808 /* TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
809 * to get the edid and then call drm_detect_hdmi_monitor.
811 hdata->has_hdmi_sink = drm_detect_hdmi_monitor(raw_edid);
812 hdata->has_hdmi_audio = drm_detect_monitor_audio(raw_edid);
813 memcpy(edid, raw_edid, min((1 + raw_edid->extensions)
814 * EDID_LENGTH, len));
815 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
816 (hdata->has_hdmi_sink ? "hdmi monitor" : "dvi monitor"),
817 raw_edid->width_cm, raw_edid->height_cm);
825 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
829 DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
830 check_timing->xres, check_timing->yres,
831 check_timing->refresh, (check_timing->vmode &
832 FB_VMODE_INTERLACED) ? true : false);
834 for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
835 if (hdmi_v13_confs[i].width == check_timing->xres &&
836 hdmi_v13_confs[i].height == check_timing->yres &&
837 hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
838 hdmi_v13_confs[i].interlace ==
839 ((check_timing->vmode & FB_VMODE_INTERLACED) ?
848 static int find_hdmiphy_conf(int pixel_clock)
852 for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
853 if (phy_configs[i].pixel_clock == pixel_clock)
856 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
860 static int hdmi_v14_check_timing(struct fb_videomode *mode)
865 * No support for interlaced since there's no clear way to convert the
866 * timing values in drm_display_mode to exynos register values.
868 if (mode->vmode == FB_VMODE_INTERLACED)
871 ret = find_hdmiphy_conf(mode->pixclock);
872 return ret < 0 ? ret : 0;
875 static u8 hdmi_chksum(struct hdmi_context *hdata,
876 u32 start, u8 len, u32 hdr_sum)
879 /* hdr_sum : header0 + header1 + header2
880 * start : start address of packet byte1
881 * len : packet bytes - 1 */
882 for (i = 0; i < len; ++i)
883 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
885 return (u8)(0x100 - (hdr_sum & 0xff));
888 void hdmi_reg_infoframe(struct hdmi_context *hdata,
889 struct hdmi_infoframe *infoframe)
896 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
897 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
898 if (!hdata->has_hdmi_sink) {
899 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
900 HDMI_VSI_CON_DO_NOT_TRANSMIT);
901 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
902 HDMI_AVI_CON_DO_NOT_TRANSMIT);
903 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
907 switch (infoframe->type) {
909 case HDMI_PACKET_TYPE_AVI:
910 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
911 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
912 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
913 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
914 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
915 /* Output format zero hardcoded ,RGB YBCR selection */
916 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
917 AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
919 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
921 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
922 AVI_SAME_AS_PIC_ASPECT_RATIO);
923 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
925 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
926 infoframe->len, hdr_sum);
927 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
928 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
931 case HDMI_PACKET_TYPE_AUI:
932 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
933 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
934 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
935 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
936 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
937 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
938 infoframe->len, hdr_sum);
939 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
940 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
948 static int hdmi_check_timing(void *ctx, void *timing)
950 struct hdmi_context *hdata = ctx;
951 struct fb_videomode *check_timing = timing;
953 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
955 DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
956 check_timing->yres, check_timing->refresh,
957 check_timing->vmode);
960 return hdmi_v13_check_timing(check_timing);
962 return hdmi_v14_check_timing(check_timing);
965 static int hdmi_display_power_on(void *ctx, int mode)
967 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
970 case DRM_MODE_DPMS_ON:
971 DRM_DEBUG_KMS("hdmi [on]\n");
973 case DRM_MODE_DPMS_STANDBY:
975 case DRM_MODE_DPMS_SUSPEND:
977 case DRM_MODE_DPMS_OFF:
978 DRM_DEBUG_KMS("hdmi [off]\n");
987 static void hdmi_set_acr(u32 freq, u8 *acr)
1027 acr[2] = cts >> 8 & 0xff;
1028 acr[3] = cts & 0xff;
1031 acr[5] = n >> 8 & 0xff;
1035 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1037 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1038 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1039 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1040 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1041 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1042 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1043 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1044 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1045 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1048 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1050 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1053 static void hdmi_audio_init(struct hdmi_context *hdata)
1055 u32 sample_rate, bits_per_sample, frame_size_code;
1056 u32 data_num, bit_ch, sample_frq;
1060 sample_rate = 44100;
1061 bits_per_sample = 16;
1062 frame_size_code = 0;
1064 switch (bits_per_sample) {
1079 hdmi_set_acr(sample_rate, acr);
1080 hdmi_reg_acr(hdata, acr);
1082 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1083 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1084 | HDMI_I2S_MUX_ENABLE);
1086 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1087 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1089 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1091 sample_frq = (sample_rate == 44100) ? 0 :
1092 (sample_rate == 48000) ? 2 :
1093 (sample_rate == 32000) ? 3 :
1094 (sample_rate == 96000) ? 0xa : 0x0;
1096 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1097 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1099 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1100 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1102 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1103 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1104 | HDMI_I2S_SEL_LRCK(6));
1105 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1106 | HDMI_I2S_SEL_SDATA2(4));
1107 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1108 | HDMI_I2S_SEL_SDATA2(2));
1109 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1112 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1113 | HDMI_I2S_L_CH_LOW_POL);
1114 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1115 | HDMI_I2S_SET_BIT_CH(bit_ch)
1116 | HDMI_I2S_SET_SDATA_BIT(data_num)
1117 | HDMI_I2S_BASIC_FORMAT);
1119 /* Configure register related to CUV information */
1120 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1121 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1122 | HDMI_I2S_COPYRIGHT
1123 | HDMI_I2S_LINEAR_PCM
1124 | HDMI_I2S_CONSUMER_FORMAT);
1125 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1126 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1127 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1128 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1129 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1130 HDMI_I2S_ORG_SMP_FREQ_44_1
1131 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1132 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1134 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1137 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1139 if (!hdata->has_hdmi_audio)
1142 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1143 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1144 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1147 static void hdmi_conf_reset(struct hdmi_context *hdata)
1151 /* disable hpd handle for drm */
1152 hdata->hpd_handle = false;
1155 reg = HDMI_V13_CORE_RSTOUT;
1157 reg = HDMI_CORE_RSTOUT;
1159 /* resetting HDMI core */
1160 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
1162 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1165 /* enable hpd handle for drm */
1166 hdata->hpd_handle = true;
1169 static void hdmi_conf_init(struct hdmi_context *hdata)
1171 struct hdmi_infoframe infoframe;
1172 /* disable hpd handle for drm */
1173 hdata->hpd_handle = false;
1175 /* enable HPD interrupts */
1176 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1177 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1179 hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1180 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1182 /* choose HDMI mode */
1183 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1184 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1185 /* disable bluescreen */
1186 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1188 if (!hdata->has_hdmi_sink) {
1189 /* choose DVI mode */
1190 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1191 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1192 hdmi_reg_writeb(hdata, HDMI_CON_2,
1193 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1196 if (hdata->is_v13) {
1197 /* choose bluescreen (fecal) color */
1198 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1199 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1200 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1202 /* enable AVI packet every vsync, fixes purple line problem */
1203 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1204 /* force RGB, look to CEA-861-D, table 7 for more detail */
1205 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1206 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1208 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1209 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1210 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1212 /* enable AVI packet every vsync, fixes purple line problem */
1213 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1215 infoframe.type = HDMI_PACKET_TYPE_AVI;
1216 infoframe.ver = HDMI_AVI_VERSION;
1217 infoframe.len = HDMI_AVI_LENGTH;
1218 hdmi_reg_infoframe(hdata, &infoframe);
1220 infoframe.type = HDMI_PACKET_TYPE_AUI;
1221 infoframe.ver = HDMI_AUI_VERSION;
1222 infoframe.len = HDMI_AUI_LENGTH;
1223 hdmi_reg_infoframe(hdata, &infoframe);
1227 /* enable hpd handle for drm */
1228 hdata->hpd_handle = true;
1231 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1233 const struct hdmi_v13_preset_conf *conf =
1234 hdmi_v13_confs[hdata->cur_conf].conf;
1235 const struct hdmi_v13_core_regs *core = &conf->core;
1236 const struct hdmi_v13_tg_regs *tg = &conf->tg;
1239 /* setting core registers */
1240 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1241 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1242 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1243 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1244 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1245 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1246 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1247 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1248 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1249 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1250 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1251 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1252 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1253 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1254 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1255 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1256 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1257 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1258 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1259 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1260 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1261 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1262 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1263 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1264 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1265 /* Timing generator registers */
1266 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1267 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1268 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1269 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1270 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1271 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1272 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1273 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1274 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1275 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1276 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1277 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1278 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1279 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1280 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1281 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1282 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1283 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1284 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1285 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1286 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1287 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1288 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1289 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1290 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1291 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1292 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1293 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1295 /* waiting for HDMIPHY's PLL to get to steady state */
1296 for (tries = 100; tries; --tries) {
1297 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1298 if (val & HDMI_PHY_STATUS_READY)
1302 /* steady state not achieved */
1304 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1305 hdmi_regs_dump(hdata, "timing apply");
1308 clk_disable(hdata->res.sclk_hdmi);
1309 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1310 clk_enable(hdata->res.sclk_hdmi);
1312 /* enable HDMI and timing generator */
1313 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1314 if (core->int_pro_mode[0])
1315 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1318 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1321 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1323 struct hdmi_core_regs *core = &hdata->mode_conf.core;
1324 struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1327 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1328 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1329 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1330 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1331 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1332 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1333 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1334 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1335 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1336 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1337 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1338 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1339 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1340 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1341 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1342 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1343 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1344 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1345 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1346 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1347 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1348 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1349 core->v_sync_line_bef_2[0]);
1350 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1351 core->v_sync_line_bef_2[1]);
1352 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1353 core->v_sync_line_bef_1[0]);
1354 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1355 core->v_sync_line_bef_1[1]);
1356 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1357 core->v_sync_line_aft_2[0]);
1358 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1359 core->v_sync_line_aft_2[1]);
1360 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1361 core->v_sync_line_aft_1[0]);
1362 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1363 core->v_sync_line_aft_1[1]);
1364 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1365 core->v_sync_line_aft_pxl_2[0]);
1366 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1367 core->v_sync_line_aft_pxl_2[1]);
1368 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1369 core->v_sync_line_aft_pxl_1[0]);
1370 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1371 core->v_sync_line_aft_pxl_1[1]);
1372 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1373 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1374 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1375 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1376 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1377 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1378 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1379 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1380 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1381 core->v_sync_line_aft_3[0]);
1382 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1383 core->v_sync_line_aft_3[1]);
1384 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1385 core->v_sync_line_aft_4[0]);
1386 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1387 core->v_sync_line_aft_4[1]);
1388 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1389 core->v_sync_line_aft_5[0]);
1390 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1391 core->v_sync_line_aft_5[1]);
1392 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1393 core->v_sync_line_aft_6[0]);
1394 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1395 core->v_sync_line_aft_6[1]);
1396 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1397 core->v_sync_line_aft_pxl_3[0]);
1398 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1399 core->v_sync_line_aft_pxl_3[1]);
1400 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1401 core->v_sync_line_aft_pxl_4[0]);
1402 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1403 core->v_sync_line_aft_pxl_4[1]);
1404 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1405 core->v_sync_line_aft_pxl_5[0]);
1406 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1407 core->v_sync_line_aft_pxl_5[1]);
1408 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1409 core->v_sync_line_aft_pxl_6[0]);
1410 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1411 core->v_sync_line_aft_pxl_6[1]);
1412 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1413 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1414 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1415 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1416 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1417 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1418 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1419 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1420 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1421 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1422 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1423 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1425 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1426 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1427 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1428 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1429 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1430 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1431 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1432 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1433 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1434 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1435 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1436 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1437 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1438 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1439 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1440 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1441 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1442 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1443 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1444 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1445 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1446 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1447 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1448 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1449 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1450 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1451 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1452 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1453 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1454 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1455 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1456 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1457 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1459 /* waiting for HDMIPHY's PLL to get to steady state */
1460 for (tries = 100; tries; --tries) {
1461 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1462 if (val & HDMI_PHY_STATUS_READY)
1466 /* steady state not achieved */
1468 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1469 hdmi_regs_dump(hdata, "timing apply");
1472 clk_disable(hdata->res.sclk_hdmi);
1473 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1474 clk_enable(hdata->res.sclk_hdmi);
1476 /* enable HDMI and timing generator */
1477 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1478 if (core->int_pro_mode[0])
1479 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1482 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1485 static void hdmi_timing_apply(struct hdmi_context *hdata)
1488 hdmi_v13_timing_apply(hdata);
1490 hdmi_v14_timing_apply(hdata);
1493 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1498 clk_disable(hdata->res.sclk_hdmi);
1499 clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1500 clk_enable(hdata->res.sclk_hdmi);
1502 /* operation mode */
1506 if (hdata->hdmiphy_port)
1507 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1510 reg = HDMI_V13_PHY_RSTOUT;
1512 reg = HDMI_PHY_RSTOUT;
1515 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1517 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
1521 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1523 const u8 *hdmiphy_data;
1526 u8 read_buffer[32] = {0, };
1530 if (!hdata->hdmiphy_port) {
1531 DRM_ERROR("hdmiphy is not attached\n");
1536 if (hdata->is_v13) {
1537 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1539 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1540 hdmiphy_data = phy_configs[i].conf;
1543 memcpy(buffer, hdmiphy_data, 32);
1544 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1546 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1552 /* operation mode */
1553 operation[0] = 0x1f;
1554 operation[1] = 0x80;
1556 ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1558 DRM_ERROR("failed to enable hdmiphy\n");
1562 ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1564 DRM_ERROR("failed to read hdmiphy config\n");
1568 for (i = 0; i < ret; i++)
1569 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1570 "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1573 static void hdmi_conf_apply(struct hdmi_context *hdata)
1575 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1577 hdmiphy_conf_reset(hdata);
1578 hdmiphy_conf_apply(hdata);
1580 hdmi_conf_reset(hdata);
1581 hdmi_conf_init(hdata);
1582 if (!hdata->is_soc_exynos5)
1583 hdmi_audio_init(hdata);
1585 /* setting core registers */
1586 hdmi_timing_apply(hdata);
1587 if (!hdata->is_soc_exynos5)
1588 hdmi_audio_control(hdata, true);
1590 hdmi_regs_dump(hdata, "start");
1593 static void hdmi_mode_copy(struct drm_display_mode *dst,
1594 struct drm_display_mode *src)
1596 struct drm_mode_object base;
1598 /* following information should be preserved,
1599 * required for releasing the drm_display_mode node,
1600 * duplicated to recieve adjustment info. */
1602 base.id = dst->base.id;
1603 base.type = dst->base.type;
1605 memcpy(dst, src, sizeof(struct drm_display_mode));
1607 dst->base.id = base.id;
1608 dst->base.type = base.type;
1611 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1612 struct drm_display_mode *mode,
1613 struct drm_display_mode *adjusted_mode)
1615 struct drm_display_mode *m;
1616 struct hdmi_context *hdata = ctx;
1619 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1621 drm_mode_set_crtcinfo(adjusted_mode, 0);
1624 index = hdmi_v13_conf_index(adjusted_mode);
1626 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1628 /* just return if user desired mode exists. */
1633 * otherwise, find the most suitable mode among modes and change it
1636 list_for_each_entry(m, &connector->modes, head) {
1638 index = hdmi_v13_conf_index(m);
1640 index = find_hdmiphy_conf(m->clock * 1000);
1643 DRM_INFO("desired mode doesn't exist so\n");
1644 DRM_INFO("use the most suitable mode among modes.\n");
1645 hdmi_mode_copy(adjusted_mode, m);
1651 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1654 BUG_ON(num_bytes > 4);
1655 for (i = 0; i < num_bytes; i++)
1656 reg_pair[i] = (value >> (8 * i)) & 0xff;
1659 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1660 struct drm_display_mode *m)
1662 struct hdmi_core_regs *core = &hdata->mode_conf.core;
1663 struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1665 hdata->mode_conf.vic = drm_match_cea_mode(m);
1667 hdata->mode_conf.pixel_clock = m->clock * 1000;
1668 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1669 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1670 hdmi_set_reg(core->v_line, 2, m->vtotal);
1671 hdmi_set_reg(core->h_line, 2, m->htotal);
1672 hdmi_set_reg(core->hsync_pol, 1,
1673 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1674 hdmi_set_reg(core->vsync_pol, 1,
1675 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1676 hdmi_set_reg(core->int_pro_mode, 1,
1677 (m->flags >> DRM_MODE_FLAG_INTERLACE) & 0x01);
1678 /* Quirk requirement for exynos 5 HDMI IP design,
1679 * 2 pixels less than the actual calculation for hsync_start
1682 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1683 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1684 hdmi_set_reg(core->v_sync_line_bef_2, 2, m->vsync_end - m->vdisplay);
1685 hdmi_set_reg(core->v_sync_line_bef_1, 2, m->vsync_start - m->vdisplay);
1686 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1687 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1688 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1689 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1690 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1691 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1694 * The following values can be different when using interlaced mode.
1695 * Unfortunately the datasheet doesn't describe them. This is why we
1696 * reject interlaced modes. Once this is fixed, we can remove that
1699 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1700 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1701 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1702 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1703 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1704 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1705 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1706 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1707 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1708 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1709 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1710 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1711 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1712 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1713 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1714 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1715 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1716 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1717 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1719 /* Timing generator registers */
1720 hdmi_set_reg(tg->cmd, 1, 0x0);
1721 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1722 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1723 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1724 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1725 hdmi_set_reg(tg->vsync, 2, 0x1);
1726 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1727 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1728 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1729 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1730 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1731 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1732 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1733 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1734 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1735 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1736 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1737 hdmi_set_reg(tg->tg_3d, 1, 0x0);
1740 static void hdmi_mode_set(void *ctx, void *mode)
1742 struct hdmi_context *hdata = ctx;
1744 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1747 hdata->cur_conf = hdmi_v13_conf_index(mode);
1749 hdmi_v14_mode_set(hdata, mode);
1752 static void hdmi_commit(void *ctx)
1754 struct hdmi_context *hdata = ctx;
1756 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1757 hdmi_conf_apply(hdata);
1759 hdata->enabled = true;
1762 static void hdmi_disable(void *ctx)
1764 struct hdmi_context *hdata = ctx;
1766 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1768 if (hdata->enabled) {
1769 if (!hdata->is_soc_exynos5)
1770 hdmi_audio_control(hdata, false);
1771 hdmiphy_conf_reset(hdata);
1772 hdmi_conf_reset(hdata);
1776 static struct exynos_hdmi_ops hdmi_ops = {
1778 .is_connected = hdmi_is_connected,
1779 .get_edid = hdmi_get_edid,
1780 .check_timing = hdmi_check_timing,
1781 .power_on = hdmi_display_power_on,
1784 .mode_fixup = hdmi_mode_fixup,
1785 .mode_set = hdmi_mode_set,
1786 .commit = hdmi_commit,
1787 .disable = hdmi_disable,
1791 * Handle hotplug events outside the interrupt handler proper.
1793 static void hdmi_hotplug_func(struct work_struct *work)
1795 struct hdmi_context *hdata =
1796 container_of(work, struct hdmi_context, hotplug_work);
1797 struct exynos_drm_hdmi_context *ctx =
1798 (struct exynos_drm_hdmi_context *)hdata->parent_ctx;
1800 drm_helper_hpd_irq_event(ctx->drm_dev);
1803 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
1805 struct exynos_drm_hdmi_context *ctx = arg;
1806 struct hdmi_context *hdata = ctx->ctx;
1809 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
1810 /* clearing flags for HPD plug/unplug */
1811 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
1812 DRM_DEBUG_KMS("unplugged, handling:%d\n", hdata->hpd_handle);
1813 hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1814 HDMI_INTC_FLAG_HPD_UNPLUG);
1816 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
1817 DRM_DEBUG_KMS("plugged, handling:%d\n", hdata->hpd_handle);
1818 hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1819 HDMI_INTC_FLAG_HPD_PLUG);
1822 if (ctx->drm_dev && hdata->hpd_handle)
1823 queue_work(hdata->wq, &hdata->hotplug_work);
1828 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
1830 struct device *dev = hdata->dev;
1831 struct hdmi_resources *res = &hdata->res;
1832 #ifndef CONFIG_ARCH_EXYNOS5
1833 static char *supply[] = {
1842 DRM_DEBUG_KMS("HDMI resource init\n");
1844 memset(res, 0, sizeof *res);
1846 /* get clocks, power */
1847 res->hdmi = clk_get(dev, "hdmi");
1848 if (IS_ERR_OR_NULL(res->hdmi)) {
1849 DRM_ERROR("failed to get clock 'hdmi'\n");
1852 res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
1853 if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
1854 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1857 res->sclk_pixel = clk_get(dev, "sclk_pixel");
1858 if (IS_ERR_OR_NULL(res->sclk_pixel)) {
1859 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1862 res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
1863 if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
1864 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1867 res->hdmiphy = clk_get(dev, "hdmiphy");
1868 if (IS_ERR_OR_NULL(res->hdmiphy)) {
1869 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1873 clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
1875 #ifndef CONFIG_ARCH_EXYNOS5
1876 res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
1877 sizeof res->regul_bulk[0], GFP_KERNEL);
1878 if (!res->regul_bulk) {
1879 DRM_ERROR("failed to get memory for regulators\n");
1882 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1883 res->regul_bulk[i].supply = supply[i];
1884 res->regul_bulk[i].consumer = NULL;
1886 ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
1888 DRM_ERROR("failed to get regulators\n");
1891 res->regul_count = ARRAY_SIZE(supply);
1896 DRM_ERROR("HDMI resource init - failed\n");
1900 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
1902 struct hdmi_resources *res = &hdata->res;
1904 regulator_bulk_free(res->regul_count, res->regul_bulk);
1905 /* kfree is NULL-safe */
1906 kfree(res->regul_bulk);
1907 if (!IS_ERR_OR_NULL(res->hdmiphy))
1908 clk_put(res->hdmiphy);
1909 if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
1910 clk_put(res->sclk_hdmiphy);
1911 if (!IS_ERR_OR_NULL(res->sclk_pixel))
1912 clk_put(res->sclk_pixel);
1913 if (!IS_ERR_OR_NULL(res->sclk_hdmi))
1914 clk_put(res->sclk_hdmi);
1915 if (!IS_ERR_OR_NULL(res->hdmi))
1917 memset(res, 0, sizeof *res);
1922 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1924 struct hdmi_resources *res = &hdata->res;
1926 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1928 /* turn HDMI power on */
1929 regulator_bulk_enable(res->regul_count, res->regul_bulk);
1930 /* power-on hdmi physical interface */
1931 clk_enable(res->hdmiphy);
1932 /* turn clocks on */
1933 clk_enable(res->hdmi);
1934 clk_enable(res->sclk_hdmi);
1936 hdmiphy_conf_reset(hdata);
1937 hdmi_conf_reset(hdata);
1938 hdmi_conf_init(hdata);
1939 if (!hdata->is_soc_exynos5)
1940 hdmi_audio_init(hdata);
1943 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
1945 struct hdmi_resources *res = &hdata->res;
1947 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1949 /* turn clocks off */
1950 clk_disable(res->sclk_hdmi);
1951 clk_disable(res->hdmi);
1952 /* power-off hdmiphy */
1953 clk_disable(res->hdmiphy);
1954 /* turn HDMI power off */
1955 regulator_bulk_disable(res->regul_count, res->regul_bulk);
1958 static int hdmi_runtime_suspend(struct device *dev)
1960 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
1962 DRM_DEBUG_KMS("%s\n", __func__);
1964 hdmi_resource_poweroff(ctx->ctx);
1969 static int hdmi_runtime_resume(struct device *dev)
1971 struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
1973 DRM_DEBUG_KMS("%s\n", __func__);
1975 hdmi_resource_poweron(ctx->ctx);
1980 static const struct dev_pm_ops hdmi_pm_ops = {
1981 .runtime_suspend = hdmi_runtime_suspend,
1982 .runtime_resume = hdmi_runtime_resume,
1985 static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
1987 void hdmi_attach_ddc_client(struct i2c_client *ddc)
1993 void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
1996 hdmi_hdmiphy = hdmiphy;
1999 struct platform_device *hdmi_audio_device;
2001 static int __devinit hdmi_probe(struct platform_device *pdev)
2003 struct device *dev = &pdev->dev;
2004 struct exynos_drm_hdmi_context *drm_hdmi_ctx;
2005 struct hdmi_context *hdata;
2006 struct exynos_drm_hdmi_pdata *pdata;
2007 struct resource *res;
2010 DRM_DEBUG_KMS("[%d]\n", __LINE__);
2012 pdata = pdev->dev.platform_data;
2014 DRM_ERROR("no platform data specified\n");
2018 drm_hdmi_ctx = kzalloc(sizeof(*drm_hdmi_ctx), GFP_KERNEL);
2019 if (!drm_hdmi_ctx) {
2020 DRM_ERROR("failed to allocate common hdmi context.\n");
2024 hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2026 DRM_ERROR("out of memory\n");
2027 kfree(drm_hdmi_ctx);
2031 drm_hdmi_ctx->ctx = (void *)hdata;
2032 hdata->parent_ctx = (void *)drm_hdmi_ctx;
2034 platform_set_drvdata(pdev, drm_hdmi_ctx);
2036 hdata->is_v13 = pdata->is_v13;
2037 hdata->default_win = pdata->default_win;
2038 hdata->default_timing = &pdata->timing;
2039 hdata->default_bpp = pdata->bpp;
2041 hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2042 "samsung,exynos5-hdmi");
2044 ret = hdmi_resources_init(hdata);
2050 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2052 DRM_ERROR("failed to find registers\n");
2057 hdata->regs_res = request_mem_region(res->start, resource_size(res),
2059 if (!hdata->regs_res) {
2060 DRM_ERROR("failed to claim register region\n");
2065 hdata->regs = ioremap(res->start, resource_size(res));
2067 DRM_ERROR("failed to map registers\n");
2069 goto err_req_region;
2072 if (of_device_is_compatible(dev->of_node,
2073 "samsung,exynos5-hdmi")) {
2076 platform_device_alloc("exynos-hdmi-audio", -1);
2078 if (!hdmi_audio_device) {
2083 ret = platform_device_add_resources(hdmi_audio_device, res, 1);
2089 hdmi_audio_device->dev.of_node =
2090 of_get_next_child(dev->of_node, NULL);
2092 ret = platform_device_add(hdmi_audio_device);
2094 platform_device_put(hdmi_audio_device);
2097 /* DDC i2c driver */
2098 if (i2c_add_driver(&ddc_driver)) {
2099 DRM_ERROR("failed to register ddc i2c driver\n");
2104 hdata->ddc_port = hdmi_ddc;
2106 /* hdmiphy i2c driver */
2107 if (i2c_add_driver(&hdmiphy_driver)) {
2108 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2113 hdata->hdmiphy_port = hdmi_hdmiphy;
2115 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2117 DRM_ERROR("get interrupt resource failed.\n");
2122 /* create workqueue and hotplug work */
2123 hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2124 WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2125 if (hdata->wq == NULL) {
2126 DRM_ERROR("Failed to create workqueue.\n");
2130 INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2132 /* register hpd interrupt */
2133 ret = request_irq(res->start, hdmi_irq_handler, 0, "drm_hdmi",
2136 DRM_ERROR("request interrupt failed.\n");
2139 hdata->irq = res->start;
2141 /* Attach HDMI Driver to common hdmi. */
2142 exynos_hdmi_drv_attach(drm_hdmi_ctx);
2144 /* register specific callbacks to common hdmi. */
2145 exynos_hdmi_ops_register(&hdmi_ops);
2147 hdmi_resource_poweron(hdata);
2152 destroy_workqueue(hdata->wq);
2154 i2c_del_driver(&hdmiphy_driver);
2156 i2c_del_driver(&ddc_driver);
2158 iounmap(hdata->regs);
2160 release_mem_region(hdata->regs_res->start,
2161 resource_size(hdata->regs_res));
2163 hdmi_resources_cleanup(hdata);
2166 kfree(drm_hdmi_ctx);
2170 static int __devexit hdmi_remove(struct platform_device *pdev)
2172 struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
2173 struct hdmi_context *hdata = ctx->ctx;
2175 DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2177 hdmi_resource_poweroff(hdata);
2179 disable_irq(hdata->irq);
2180 free_irq(hdata->irq, hdata);
2182 cancel_work_sync(&hdata->hotplug_work);
2183 destroy_workqueue(hdata->wq);
2185 hdmi_resources_cleanup(hdata);
2187 iounmap(hdata->regs);
2189 release_mem_region(hdata->regs_res->start,
2190 resource_size(hdata->regs_res));
2192 /* hdmiphy i2c driver */
2193 i2c_del_driver(&hdmiphy_driver);
2194 /* DDC i2c driver */
2195 i2c_del_driver(&ddc_driver);
2202 struct platform_driver hdmi_driver = {
2203 .probe = hdmi_probe,
2204 .remove = __devexit_p(hdmi_remove),
2206 #ifdef CONFIG_ARCH_EXYNOS5
2207 .name = "exynos5-hdmi",
2209 .name = "exynos4-hdmi",
2211 .owner = THIS_MODULE,