drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/clk.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of_gpio.h>
  37 #include <plat/gpio-cfg.h>
  38
  39 #include <drm/exynos_drm.h>
  40
  41 #include "exynos_drm_drv.h"
  42 #include "exynos_drm_display.h"
  43
  44 #include "exynos_hdmi.h"
  45
  46 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  47
  48 struct hdmi_resources {
  49         struct clk                      *hdmi;
  50         struct clk                      *sclk_hdmi;
  51         struct clk                      *sclk_pixel;
  52         struct clk                      *sclk_hdmiphy;
  53         struct clk                      *hdmiphy;
  54         struct regulator_bulk_data      *regul_bulk;
  55         int                             regul_count;
  56 };
  57
  58 struct hdmi_tg_regs {
  59         u8 cmd[1];
  60         u8 h_fsz[2];
  61         u8 hact_st[2];
  62         u8 hact_sz[2];
  63         u8 v_fsz[2];
  64         u8 vsync[2];
  65         u8 vsync2[2];
  66         u8 vact_st[2];
  67         u8 vact_sz[2];
  68         u8 field_chg[2];
  69         u8 vact_st2[2];
  70         u8 vact_st3[2];
  71         u8 vact_st4[2];
  72         u8 vsync_top_hdmi[2];
  73         u8 vsync_bot_hdmi[2];
  74         u8 field_top_hdmi[2];
  75         u8 field_bot_hdmi[2];
  76         u8 tg_3d[1];
  77 };
  78
  79 struct hdmi_core_regs {
  80         u8 h_blank[2];
  81         u8 v2_blank[2];
  82         u8 v1_blank[2];
  83         u8 v_line[2];
  84         u8 h_line[2];
  85         u8 hsync_pol[1];
  86         u8 vsync_pol[1];
  87         u8 int_pro_mode[1];
  88         u8 v_blank_f0[2];
  89         u8 v_blank_f1[2];
  90         u8 h_sync_start[2];
  91         u8 h_sync_end[2];
  92         u8 v_sync_line_bef_2[2];
  93         u8 v_sync_line_bef_1[2];
  94         u8 v_sync_line_aft_2[2];
  95         u8 v_sync_line_aft_1[2];
  96         u8 v_sync_line_aft_pxl_2[2];
  97         u8 v_sync_line_aft_pxl_1[2];
  98         u8 v_blank_f2[2]; /* for 3D mode */
  99         u8 v_blank_f3[2]; /* for 3D mode */
 100         u8 v_blank_f4[2]; /* for 3D mode */
 101         u8 v_blank_f5[2]; /* for 3D mode */
 102         u8 v_sync_line_aft_3[2];
 103         u8 v_sync_line_aft_4[2];
 104         u8 v_sync_line_aft_5[2];
 105         u8 v_sync_line_aft_6[2];
 106         u8 v_sync_line_aft_pxl_3[2];
 107         u8 v_sync_line_aft_pxl_4[2];
 108         u8 v_sync_line_aft_pxl_5[2];
 109         u8 v_sync_line_aft_pxl_6[2];
 110         u8 vact_space_1[2];
 111         u8 vact_space_2[2];
 112         u8 vact_space_3[2];
 113         u8 vact_space_4[2];
 114         u8 vact_space_5[2];
 115         u8 vact_space_6[2];
 116 };
 117
 118 struct hdmi_mode_conf {
 119         int pixel_clock;
 120         struct hdmi_core_regs core;
 121         struct hdmi_tg_regs tg;
 122         u8 vic;
 123 };
 124
 125 struct hdmi_context {
 126         struct device                   *dev;
 127         struct drm_device               *drm_dev;
 128         struct fb_videomode             *default_timing;
 129         struct hdmi_mode_conf           mode_conf;
 130         unsigned int                    is_v13:1;
 131         unsigned int                    default_win;
 132         unsigned int                    default_bpp;
 133         bool                            hpd_handle;
 134         bool                            enabled;
 135         bool                            has_hdmi_sink;
 136         bool                            has_hdmi_audio;
 137         bool                            is_soc_exynos5;
 138         bool                            is_hdmi_powered_on;
 139         bool                            video_enabled;
 140
 141         struct resource                 *regs_res;
 142         void __iomem                    *regs;
 143         unsigned int                    external_irq;
 144         unsigned int                    internal_irq;
 145         unsigned int                    curr_irq;
 146         struct workqueue_struct         *wq;
 147         struct work_struct              hotplug_work;
 148
 149         struct i2c_client               *ddc_port;
 150         struct i2c_client               *hdmiphy_port;
 151         int                             hpd_gpio;
 152         /* current hdmiphy conf index */
 153         int cur_conf;
 154
 155         struct hdmi_resources           res;
 156 };
 157
 158 /* HDMI Version 1.3 */
 159 static const u8 hdmiphy_v13_conf27[32] = {
 160         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 161         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 162         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 163         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 164 };
 165
 166 static const u8 hdmiphy_v13_conf27_027[32] = {
 167         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 168         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 169         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 170         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 171 };
 172
 173 static const u8 hdmiphy_v13_conf74_175[32] = {
 174         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 175         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 176         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 177         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 178 };
 179
 180 static const u8 hdmiphy_v13_conf74_25[32] = {
 181         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 182         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 183         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 184         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 185 };
 186
 187 static const u8 hdmiphy_v13_conf148_5[32] = {
 188         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 189         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 190         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 191         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 192 };
 193
 194 struct hdmi_v13_tg_regs {
 195         u8 cmd;
 196         u8 h_fsz_l;
 197         u8 h_fsz_h;
 198         u8 hact_st_l;
 199         u8 hact_st_h;
 200         u8 hact_sz_l;
 201         u8 hact_sz_h;
 202         u8 v_fsz_l;
 203         u8 v_fsz_h;
 204         u8 vsync_l;
 205         u8 vsync_h;
 206         u8 vsync2_l;
 207         u8 vsync2_h;
 208         u8 vact_st_l;
 209         u8 vact_st_h;
 210         u8 vact_sz_l;
 211         u8 vact_sz_h;
 212         u8 field_chg_l;
 213         u8 field_chg_h;
 214         u8 vact_st2_l;
 215         u8 vact_st2_h;
 216         u8 vsync_top_hdmi_l;
 217         u8 vsync_top_hdmi_h;
 218         u8 vsync_bot_hdmi_l;
 219         u8 vsync_bot_hdmi_h;
 220         u8 field_top_hdmi_l;
 221         u8 field_top_hdmi_h;
 222         u8 field_bot_hdmi_l;
 223         u8 field_bot_hdmi_h;
 224 };
 225
 226 struct hdmi_v13_core_regs {
 227         u8 h_blank[2];
 228         u8 v_blank[3];
 229         u8 h_v_line[3];
 230         u8 vsync_pol[1];
 231         u8 int_pro_mode[1];
 232         u8 v_blank_f[3];
 233         u8 h_sync_gen[3];
 234         u8 v_sync_gen1[3];
 235         u8 v_sync_gen2[3];
 236         u8 v_sync_gen3[3];
 237 };
 238
 239 struct hdmi_v13_preset_conf {
 240         struct hdmi_v13_core_regs core;
 241         struct hdmi_v13_tg_regs tg;
 242 };
 243
 244 struct hdmi_v13_conf {
 245         int width;
 246         int height;
 247         int vrefresh;
 248         bool interlace;
 249         const u8 *hdmiphy_data;
 250         const struct hdmi_v13_preset_conf *conf;
 251 };
 252
 253 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 254         .core = {
 255                 .h_blank = {0x8a, 0x00},
 256                 .v_blank = {0x0d, 0x6a, 0x01},
 257                 .h_v_line = {0x0d, 0xa2, 0x35},
 258                 .vsync_pol = {0x01},
 259                 .int_pro_mode = {0x00},
 260                 .v_blank_f = {0x00, 0x00, 0x00},
 261                 .h_sync_gen = {0x0e, 0x30, 0x11},
 262                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 263                 /* other don't care */
 264         },
 265         .tg = {
 266                 0x00, /* cmd */
 267                 0x5a, 0x03, /* h_fsz */
 268                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 269                 0x0d, 0x02, /* v_fsz */
 270                 0x01, 0x00, 0x33, 0x02, /* vsync */
 271                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 272                 0x33, 0x02, /* field_chg */
 273                 0x49, 0x02, /* vact_st2 */
 274                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 275                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 276         },
 277 };
 278
 279 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 280         .core = {
 281                 .h_blank = {0x72, 0x01},
 282                 .v_blank = {0xee, 0xf2, 0x00},
 283                 .h_v_line = {0xee, 0x22, 0x67},
 284                 .vsync_pol = {0x00},
 285                 .int_pro_mode = {0x00},
 286                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 287                 .h_sync_gen = {0x6c, 0x50, 0x02},
 288                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 289                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 290                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 291                 /* other don't care */
 292         },
 293         .tg = {
 294                 0x00, /* cmd */
 295                 0x72, 0x06, /* h_fsz */
 296                 0x71, 0x01, 0x01, 0x05, /* hact */
 297                 0xee, 0x02, /* v_fsz */
 298                 0x01, 0x00, 0x33, 0x02, /* vsync */
 299                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 300                 0x33, 0x02, /* field_chg */
 301                 0x49, 0x02, /* vact_st2 */
 302                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 303                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 304         },
 305 };
 306
 307 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 308         .core = {
 309                 .h_blank = {0xd0, 0x02},
 310                 .v_blank = {0x32, 0xB2, 0x00},
 311                 .h_v_line = {0x65, 0x04, 0xa5},
 312                 .vsync_pol = {0x00},
 313                 .int_pro_mode = {0x01},
 314                 .v_blank_f = {0x49, 0x2A, 0x23},
 315                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 316                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 317                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 318                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 319                 /* other don't care */
 320         },
 321         .tg = {
 322                 0x00, /* cmd */
 323                 0x50, 0x0A, /* h_fsz */
 324                 0xCF, 0x02, 0x81, 0x07, /* hact */
 325                 0x65, 0x04, /* v_fsz */
 326                 0x01, 0x00, 0x33, 0x02, /* vsync */
 327                 0x16, 0x00, 0x1c, 0x02, /* vact */
 328                 0x33, 0x02, /* field_chg */
 329                 0x49, 0x02, /* vact_st2 */
 330                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 331                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 332         },
 333 };
 334
 335 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 336         .core = {
 337                 .h_blank = {0xd0, 0x02},
 338                 .v_blank = {0x65, 0x6c, 0x01},
 339                 .h_v_line = {0x65, 0x04, 0xa5},
 340                 .vsync_pol = {0x00},
 341                 .int_pro_mode = {0x00},
 342                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 343                 .h_sync_gen = {0x0e, 0xea, 0x08},
 344                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 345                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 346                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 347                 /* other don't care */
 348         },
 349         .tg = {
 350                 0x00, /* cmd */
 351                 0x50, 0x0A, /* h_fsz */
 352                 0xCF, 0x02, 0x81, 0x07, /* hact */
 353                 0x65, 0x04, /* v_fsz */
 354                 0x01, 0x00, 0x33, 0x02, /* vsync */
 355                 0x2d, 0x00, 0x38, 0x04, /* vact */
 356                 0x33, 0x02, /* field_chg */
 357                 0x48, 0x02, /* vact_st2 */
 358                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 359                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 360         },
 361 };
 362
 363 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 364         .core = {
 365                 .h_blank = {0x18, 0x01},
 366                 .v_blank = {0x32, 0xB2, 0x00},
 367                 .h_v_line = {0x65, 0x84, 0x89},
 368                 .vsync_pol = {0x00},
 369                 .int_pro_mode = {0x01},
 370                 .v_blank_f = {0x49, 0x2A, 0x23},
 371                 .h_sync_gen = {0x56, 0x08, 0x02},
 372                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 373                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 374                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 375                 /* other don't care */
 376         },
 377         .tg = {
 378                 0x00, /* cmd */
 379                 0x98, 0x08, /* h_fsz */
 380                 0x17, 0x01, 0x81, 0x07, /* hact */
 381                 0x65, 0x04, /* v_fsz */
 382                 0x01, 0x00, 0x33, 0x02, /* vsync */
 383                 0x16, 0x00, 0x1c, 0x02, /* vact */
 384                 0x33, 0x02, /* field_chg */
 385                 0x49, 0x02, /* vact_st2 */
 386                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 387                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 388         },
 389 };
 390
 391 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 392         .core = {
 393                 .h_blank = {0x18, 0x01},
 394                 .v_blank = {0x65, 0x6c, 0x01},
 395                 .h_v_line = {0x65, 0x84, 0x89},
 396                 .vsync_pol = {0x00},
 397                 .int_pro_mode = {0x00},
 398                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 399                 .h_sync_gen = {0x56, 0x08, 0x02},
 400                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 401                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 402                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 403                 /* other don't care */
 404         },
 405         .tg = {
 406                 0x00, /* cmd */
 407                 0x98, 0x08, /* h_fsz */
 408                 0x17, 0x01, 0x81, 0x07, /* hact */
 409                 0x65, 0x04, /* v_fsz */
 410                 0x01, 0x00, 0x33, 0x02, /* vsync */
 411                 0x2d, 0x00, 0x38, 0x04, /* vact */
 412                 0x33, 0x02, /* field_chg */
 413                 0x48, 0x02, /* vact_st2 */
 414                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 415                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 416         },
 417 };
 418
 419 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 420         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 421         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 422         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 423         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 424         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 425                                  &hdmi_v13_conf_1080p50 },
 426         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 427         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 428                                  &hdmi_v13_conf_1080p60 },
 429 };
 430
 431 struct hdmiphy_config {
 432         int pixel_clock;
 433         u8 conf[32];
 434 };
 435
 436 static const struct hdmiphy_config phy_configs[] = {
 437         {
 438                 .pixel_clock = 25200000,
 439                 .conf = {
 440                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 441                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 442                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 443                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 444                 },
 445         },
 446         {
 447                 .pixel_clock = 27000000,
 448                 .conf = {
 449                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 450                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 451                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 452                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 453                 },
 454         },
 455         {
 456                 .pixel_clock = 27027000,
 457                 .conf = {
 458                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 459                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 460                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 461                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 462                 },
 463         },
 464         {
 465                 .pixel_clock = 36000000,
 466                 .conf = {
 467                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 468                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 469                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 470                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 471                 },
 472         },
 473         {
 474                 .pixel_clock = 40000000,
 475                 .conf = {
 476                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 477                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 478                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 479                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 480                 },
 481         },
 482         {
 483                 .pixel_clock = 65000000,
 484                 .conf = {
 485                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 486                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 487                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 488                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 489                 },
 490         },
 491         {
 492                 .pixel_clock = 74176000,
 493                 .conf = {
 494                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 495                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 496                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 497                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 498                 },
 499         },
 500         {
 501                 .pixel_clock = 74250000,
 502                 .conf = {
 503                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 504                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 505                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 506                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 507                 },
 508         },
 509         {
 510                 .pixel_clock = 83500000,
 511                 .conf = {
 512                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 513                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 514                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 515                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 516                 },
 517         },
 518         {
 519                 .pixel_clock = 106500000,
 520                 .conf = {
 521                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 522                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 523                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 524                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 525                 },
 526         },
 527         {
 528                 .pixel_clock = 108000000,
 529                 .conf = {
 530                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 531                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 532                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 533                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 534                 },
 535         },
 536         {
 537                 .pixel_clock = 146250000,
 538                 .conf = {
 539                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 540                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 541                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 542                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 543                 },
 544         },
 545         {
 546                 .pixel_clock = 148500000,
 547                 .conf = {
 548                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 549                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 550                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 551                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 552                 },
 553         },
 554 };
 555
 556 struct hdmi_infoframe {
 557         enum HDMI_PACKET_TYPE type;
 558         u8 ver;
 559         u8 len;
 560 };
 561
 562 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 563 {
 564         return readl(hdata->regs + reg_id);
 565 }
 566
 567 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 568                                  u32 reg_id, u8 value)
 569 {
 570         writeb(value, hdata->regs + reg_id);
 571 }
 572
 573 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 574                                  u32 reg_id, u32 value, u32 mask)
 575 {
 576         u32 old = readl(hdata->regs + reg_id);
 577         value = (value & mask) | (old & ~mask);
 578         writel(value, hdata->regs + reg_id);
 579 }
 580
 581 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 582 {
 583         if (external) {
 584                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 585                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 586         } else {
 587                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 588                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 589         }
 590 }
 591
 592 static int hdmi_get_hpd(struct hdmi_context *hdata)
 593 {
 594         return gpio_get_value(hdata->hpd_gpio);
 595 }
 596
 597 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 598 {
 599 #define DUMPREG(reg_id) \
 600         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 601         readl(hdata->regs + reg_id))
 602         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 603         DUMPREG(HDMI_INTC_FLAG);
 604         DUMPREG(HDMI_INTC_CON);
 605         DUMPREG(HDMI_HPD_STATUS);
 606         DUMPREG(HDMI_V13_PHY_RSTOUT);
 607         DUMPREG(HDMI_V13_PHY_VPLL);
 608         DUMPREG(HDMI_V13_PHY_CMU);
 609         DUMPREG(HDMI_V13_CORE_RSTOUT);
 610
 611         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 612         DUMPREG(HDMI_CON_0);
 613         DUMPREG(HDMI_CON_1);
 614         DUMPREG(HDMI_CON_2);
 615         DUMPREG(HDMI_SYS_STATUS);
 616         DUMPREG(HDMI_V13_PHY_STATUS);
 617         DUMPREG(HDMI_STATUS_EN);
 618         DUMPREG(HDMI_HPD);
 619         DUMPREG(HDMI_MODE_SEL);
 620         DUMPREG(HDMI_V13_HPD_GEN);
 621         DUMPREG(HDMI_V13_DC_CONTROL);
 622         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 623
 624         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 625         DUMPREG(HDMI_H_BLANK_0);
 626         DUMPREG(HDMI_H_BLANK_1);
 627         DUMPREG(HDMI_V13_V_BLANK_0);
 628         DUMPREG(HDMI_V13_V_BLANK_1);
 629         DUMPREG(HDMI_V13_V_BLANK_2);
 630         DUMPREG(HDMI_V13_H_V_LINE_0);
 631         DUMPREG(HDMI_V13_H_V_LINE_1);
 632         DUMPREG(HDMI_V13_H_V_LINE_2);
 633         DUMPREG(HDMI_VSYNC_POL);
 634         DUMPREG(HDMI_INT_PRO_MODE);
 635         DUMPREG(HDMI_V13_V_BLANK_F_0);
 636         DUMPREG(HDMI_V13_V_BLANK_F_1);
 637         DUMPREG(HDMI_V13_V_BLANK_F_2);
 638         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 639         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 641         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 642         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 650
 651         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 652         DUMPREG(HDMI_TG_CMD);
 653         DUMPREG(HDMI_TG_H_FSZ_L);
 654         DUMPREG(HDMI_TG_H_FSZ_H);
 655         DUMPREG(HDMI_TG_HACT_ST_L);
 656         DUMPREG(HDMI_TG_HACT_ST_H);
 657         DUMPREG(HDMI_TG_HACT_SZ_L);
 658         DUMPREG(HDMI_TG_HACT_SZ_H);
 659         DUMPREG(HDMI_TG_V_FSZ_L);
 660         DUMPREG(HDMI_TG_V_FSZ_H);
 661         DUMPREG(HDMI_TG_VSYNC_L);
 662         DUMPREG(HDMI_TG_VSYNC_H);
 663         DUMPREG(HDMI_TG_VSYNC2_L);
 664         DUMPREG(HDMI_TG_VSYNC2_H);
 665         DUMPREG(HDMI_TG_VACT_ST_L);
 666         DUMPREG(HDMI_TG_VACT_ST_H);
 667         DUMPREG(HDMI_TG_VACT_SZ_L);
 668         DUMPREG(HDMI_TG_VACT_SZ_H);
 669         DUMPREG(HDMI_TG_FIELD_CHG_L);
 670         DUMPREG(HDMI_TG_FIELD_CHG_H);
 671         DUMPREG(HDMI_TG_VACT_ST2_L);
 672         DUMPREG(HDMI_TG_VACT_ST2_H);
 673         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 674         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 675         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 677         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 678         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 681 #undef DUMPREG
 682 }
 683
 684 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 685 {
 686         int i;
 687
 688 #define DUMPREG(reg_id) \
 689         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 690         readl(hdata->regs + reg_id))
 691
 692         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 693         DUMPREG(HDMI_INTC_CON);
 694         DUMPREG(HDMI_INTC_FLAG);
 695         DUMPREG(HDMI_HPD_STATUS);
 696         DUMPREG(HDMI_INTC_CON_1);
 697         DUMPREG(HDMI_INTC_FLAG_1);
 698         DUMPREG(HDMI_PHY_STATUS_0);
 699         DUMPREG(HDMI_PHY_STATUS_PLL);
 700         DUMPREG(HDMI_PHY_CON_0);
 701         DUMPREG(HDMI_PHY_RSTOUT);
 702         DUMPREG(HDMI_PHY_VPLL);
 703         DUMPREG(HDMI_PHY_CMU);
 704         DUMPREG(HDMI_CORE_RSTOUT);
 705
 706         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 707         DUMPREG(HDMI_CON_0);
 708         DUMPREG(HDMI_CON_1);
 709         DUMPREG(HDMI_CON_2);
 710         DUMPREG(HDMI_SYS_STATUS);
 711         DUMPREG(HDMI_PHY_STATUS_0);
 712         DUMPREG(HDMI_STATUS_EN);
 713         DUMPREG(HDMI_HPD);
 714         DUMPREG(HDMI_MODE_SEL);
 715         DUMPREG(HDMI_ENC_EN);
 716         DUMPREG(HDMI_DC_CONTROL);
 717         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 718
 719         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 720         DUMPREG(HDMI_H_BLANK_0);
 721         DUMPREG(HDMI_H_BLANK_1);
 722         DUMPREG(HDMI_V2_BLANK_0);
 723         DUMPREG(HDMI_V2_BLANK_1);
 724         DUMPREG(HDMI_V1_BLANK_0);
 725         DUMPREG(HDMI_V1_BLANK_1);
 726         DUMPREG(HDMI_V_LINE_0);
 727         DUMPREG(HDMI_V_LINE_1);
 728         DUMPREG(HDMI_H_LINE_0);
 729         DUMPREG(HDMI_H_LINE_1);
 730         DUMPREG(HDMI_HSYNC_POL);
 731
 732         DUMPREG(HDMI_VSYNC_POL);
 733         DUMPREG(HDMI_INT_PRO_MODE);
 734         DUMPREG(HDMI_V_BLANK_F0_0);
 735         DUMPREG(HDMI_V_BLANK_F0_1);
 736         DUMPREG(HDMI_V_BLANK_F1_0);
 737         DUMPREG(HDMI_V_BLANK_F1_1);
 738
 739         DUMPREG(HDMI_H_SYNC_START_0);
 740         DUMPREG(HDMI_H_SYNC_START_1);
 741         DUMPREG(HDMI_H_SYNC_END_0);
 742         DUMPREG(HDMI_H_SYNC_END_1);
 743
 744         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 745         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 748
 749         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 750         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 753
 754         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 755         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 758
 759         DUMPREG(HDMI_V_BLANK_F2_0);
 760         DUMPREG(HDMI_V_BLANK_F2_1);
 761         DUMPREG(HDMI_V_BLANK_F3_0);
 762         DUMPREG(HDMI_V_BLANK_F3_1);
 763         DUMPREG(HDMI_V_BLANK_F4_0);
 764         DUMPREG(HDMI_V_BLANK_F4_1);
 765         DUMPREG(HDMI_V_BLANK_F5_0);
 766         DUMPREG(HDMI_V_BLANK_F5_1);
 767
 768         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 769         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 776
 777         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 778         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 785
 786         DUMPREG(HDMI_VACT_SPACE_1_0);
 787         DUMPREG(HDMI_VACT_SPACE_1_1);
 788         DUMPREG(HDMI_VACT_SPACE_2_0);
 789         DUMPREG(HDMI_VACT_SPACE_2_1);
 790         DUMPREG(HDMI_VACT_SPACE_3_0);
 791         DUMPREG(HDMI_VACT_SPACE_3_1);
 792         DUMPREG(HDMI_VACT_SPACE_4_0);
 793         DUMPREG(HDMI_VACT_SPACE_4_1);
 794         DUMPREG(HDMI_VACT_SPACE_5_0);
 795         DUMPREG(HDMI_VACT_SPACE_5_1);
 796         DUMPREG(HDMI_VACT_SPACE_6_0);
 797         DUMPREG(HDMI_VACT_SPACE_6_1);
 798
 799         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 800         DUMPREG(HDMI_TG_CMD);
 801         DUMPREG(HDMI_TG_H_FSZ_L);
 802         DUMPREG(HDMI_TG_H_FSZ_H);
 803         DUMPREG(HDMI_TG_HACT_ST_L);
 804         DUMPREG(HDMI_TG_HACT_ST_H);
 805         DUMPREG(HDMI_TG_HACT_SZ_L);
 806         DUMPREG(HDMI_TG_HACT_SZ_H);
 807         DUMPREG(HDMI_TG_V_FSZ_L);
 808         DUMPREG(HDMI_TG_V_FSZ_H);
 809         DUMPREG(HDMI_TG_VSYNC_L);
 810         DUMPREG(HDMI_TG_VSYNC_H);
 811         DUMPREG(HDMI_TG_VSYNC2_L);
 812         DUMPREG(HDMI_TG_VSYNC2_H);
 813         DUMPREG(HDMI_TG_VACT_ST_L);
 814         DUMPREG(HDMI_TG_VACT_ST_H);
 815         DUMPREG(HDMI_TG_VACT_SZ_L);
 816         DUMPREG(HDMI_TG_VACT_SZ_H);
 817         DUMPREG(HDMI_TG_FIELD_CHG_L);
 818         DUMPREG(HDMI_TG_FIELD_CHG_H);
 819         DUMPREG(HDMI_TG_VACT_ST2_L);
 820         DUMPREG(HDMI_TG_VACT_ST2_H);
 821         DUMPREG(HDMI_TG_VACT_ST3_L);
 822         DUMPREG(HDMI_TG_VACT_ST3_H);
 823         DUMPREG(HDMI_TG_VACT_ST4_L);
 824         DUMPREG(HDMI_TG_VACT_ST4_H);
 825         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 826         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 827         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 828         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 829         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 830         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 831         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 832         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 833         DUMPREG(HDMI_TG_3D);
 834
 835         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 836         DUMPREG(HDMI_AVI_CON);
 837         DUMPREG(HDMI_AVI_HEADER0);
 838         DUMPREG(HDMI_AVI_HEADER1);
 839         DUMPREG(HDMI_AVI_HEADER2);
 840         DUMPREG(HDMI_AVI_CHECK_SUM);
 841         DUMPREG(HDMI_VSI_CON);
 842         DUMPREG(HDMI_VSI_HEADER0);
 843         DUMPREG(HDMI_VSI_HEADER1);
 844         DUMPREG(HDMI_VSI_HEADER2);
 845         for (i = 0; i < 7; ++i)
 846                 DUMPREG(HDMI_VSI_DATA(i));
 847
 848 #undef DUMPREG
 849 }
 850
 851 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 852 {
 853         if (hdata->is_v13)
 854                 hdmi_v13_regs_dump(hdata, prefix);
 855         else
 856                 hdmi_v14_regs_dump(hdata, prefix);
 857 }
 858
 859 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 860 {
 861         int i;
 862
 863         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 864                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 865                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 866                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 867                                 hdmi_v13_confs[i].interlace ==
 868                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 869                                  true : false))
 870                         return i;
 871
 872         return -EINVAL;
 873 }
 874
 875 static bool hdmi_is_connected(void *ctx)
 876 {
 877         struct hdmi_context *hdata = ctx;
 878         if (hdata->is_hdmi_powered_on) {
 879                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 880                         DRM_DEBUG_KMS("hdmi is not connected\n");
 881                         return false;
 882                 }
 883         } else if (!hdmi_get_hpd(hdata)) {
 884                         DRM_DEBUG_KMS("hdmi is not connected\n");
 885                         return false;
 886         }
 887
 888         return true;
 889 }
 890
 891 static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
 892 {
 893         struct hdmi_context *hdata = ctx;
 894         struct edid *edid;
 895
 896         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 897
 898         if (!hdata->ddc_port)
 899                 return -ENODEV;
 900
 901         edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 902         if (!edid)
 903                 return ERR_PTR(-ENODEV);
 904
 905         /*
 906          * TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 907          * to get the edid and then call drm_detect_hdmi_monitor.
 908          */
 909         hdata->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
 910         hdata->has_hdmi_audio = drm_detect_monitor_audio(edid);
 911         DRM_DEBUG_KMS("%s monitor\n", hdata->has_hdmi_sink ? "hdmi" : "dvi");
 912
 913         return edid;
 914 }
 915
 916 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 917 {
 918         int i;
 919
 920         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 921                         check_timing->xres, check_timing->yres,
 922                         check_timing->refresh, (check_timing->vmode &
 923                         FB_VMODE_INTERLACED) ? true : false);
 924
 925         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 926                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 927                         hdmi_v13_confs[i].height == check_timing->yres &&
 928                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 929                         hdmi_v13_confs[i].interlace ==
 930                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 931                          true : false))
 932                                 return 0;
 933
 934         /* TODO */
 935
 936         return -EINVAL;
 937 }
 938
 939 static int find_hdmiphy_conf(int pixel_clock)
 940 {
 941         int i;
 942
 943         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 944                 if (phy_configs[i].pixel_clock == pixel_clock)
 945                         return i;
 946         }
 947         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 948         return -EINVAL;
 949 }
 950
 951 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 952 {
 953         int ret;
 954         enum exynos_mixer_mode_type mode_type;
 955
 956         /* Make sure the mixer can generate this mode */
 957         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 958         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 959                 return -EINVAL;
 960
 961         ret = find_hdmiphy_conf(mode->pixclock);
 962         return ret < 0 ? ret : 0;
 963 }
 964
 965 static u8 hdmi_chksum(struct hdmi_context *hdata,
 966                         u32 start, u8 len, u32 hdr_sum)
 967 {
 968         int i;
 969         /* hdr_sum : header0 + header1 + header2
 970         * start : start address of packet byte1
 971         * len : packet bytes - 1 */
 972         for (i = 0; i < len; ++i)
 973                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 974
 975         return (u8)(0x100 - (hdr_sum & 0xff));
 976 }
 977
 978 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 979                         struct hdmi_infoframe *infoframe)
 980 {
 981         u32 hdr_sum;
 982         u8 chksum;
 983         u32 aspect_ratio;
 984         u32 mod;
 985
 986         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 987         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 988         if (!hdata->has_hdmi_sink) {
 989                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 990                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 991                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 992                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 993                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 994                 return;
 995         }
 996
 997         switch (infoframe->type) {
 998
 999         case HDMI_PACKET_TYPE_AVI:
1000                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1001                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1002                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1003                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1004                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1005                 /* Output format zero hardcoded ,RGB YBCR selection */
1006                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1007                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1008
1009                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1010
1011                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1012                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1013                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1014
1015                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1016                                         infoframe->len, hdr_sum);
1017                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1018                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1019                 break;
1020
1021         case HDMI_PACKET_TYPE_AUI:
1022                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1023                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1024                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1025                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1026                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1027                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1028                                         infoframe->len, hdr_sum);
1029                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1030                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1031                 break;
1032
1033         default:
1034                 break;
1035         }
1036 }
1037
1038 static int hdmi_check_timing(void *ctx, void *timing)
1039 {
1040         struct hdmi_context *hdata = ctx;
1041         struct fb_videomode *check_timing = timing;
1042
1043         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1044
1045         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1046                         check_timing->yres, check_timing->refresh,
1047                         check_timing->vmode);
1048
1049         if (hdata->is_v13)
1050                 return hdmi_v13_check_timing(check_timing);
1051         else
1052                 return hdmi_v14_check_timing(check_timing);
1053 }
1054
1055 static void hdmi_set_acr(u32 freq, u8 *acr)
1056 {
1057         u32 n, cts;
1058
1059         switch (freq) {
1060         case 32000:
1061                 n = 4096;
1062                 cts = 27000;
1063                 break;
1064         case 44100:
1065                 n = 6272;
1066                 cts = 30000;
1067                 break;
1068         case 88200:
1069                 n = 12544;
1070                 cts = 30000;
1071                 break;
1072         case 176400:
1073                 n = 25088;
1074                 cts = 30000;
1075                 break;
1076         case 48000:
1077                 n = 6144;
1078                 cts = 27000;
1079                 break;
1080         case 96000:
1081                 n = 12288;
1082                 cts = 27000;
1083                 break;
1084         case 192000:
1085                 n = 24576;
1086                 cts = 27000;
1087                 break;
1088         default:
1089                 n = 0;
1090                 cts = 0;
1091                 break;
1092         }
1093
1094         acr[1] = cts >> 16;
1095         acr[2] = cts >> 8 & 0xff;
1096         acr[3] = cts & 0xff;
1097
1098         acr[4] = n >> 16;
1099         acr[5] = n >> 8 & 0xff;
1100         acr[6] = n & 0xff;
1101 }
1102
1103 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1104 {
1105         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1106         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1107         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1108         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1109         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1110         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1111         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1114
1115         if (hdata->is_v13)
1116                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1117         else
1118                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1119 }
1120
1121 static void hdmi_audio_init(struct hdmi_context *hdata)
1122 {
1123         u32 sample_rate, bits_per_sample, frame_size_code;
1124         u32 data_num, bit_ch, sample_frq;
1125         u32 val;
1126         u8 acr[7];
1127
1128         sample_rate = 44100;
1129         bits_per_sample = 16;
1130         frame_size_code = 0;
1131
1132         switch (bits_per_sample) {
1133         case 20:
1134                 data_num = 2;
1135                 bit_ch  = 1;
1136                 break;
1137         case 24:
1138                 data_num = 3;
1139                 bit_ch  = 1;
1140                 break;
1141         default:
1142                 data_num = 1;
1143                 bit_ch  = 0;
1144                 break;
1145         }
1146
1147         hdmi_set_acr(sample_rate, acr);
1148         hdmi_reg_acr(hdata, acr);
1149
1150         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1151                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1152                                 | HDMI_I2S_MUX_ENABLE);
1153
1154         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1155                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1156
1157         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1158
1159         sample_frq = (sample_rate == 44100) ? 0 :
1160                         (sample_rate == 48000) ? 2 :
1161                         (sample_rate == 32000) ? 3 :
1162                         (sample_rate == 96000) ? 0xa : 0x0;
1163
1164         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1165         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1166
1167         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1168         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1169
1170         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1171         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1172                         | HDMI_I2S_SEL_LRCK(6));
1173         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1174                         | HDMI_I2S_SEL_SDATA2(4));
1175         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1176                         | HDMI_I2S_SEL_SDATA2(2));
1177         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1178
1179         /* I2S_CON_1 & 2 */
1180         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1181                         | HDMI_I2S_L_CH_LOW_POL);
1182         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1183                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1184                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1185                         | HDMI_I2S_BASIC_FORMAT);
1186
1187         /* Configure register related to CUV information */
1188         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1189                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1190                         | HDMI_I2S_COPYRIGHT
1191                         | HDMI_I2S_LINEAR_PCM
1192                         | HDMI_I2S_CONSUMER_FORMAT);
1193         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1194         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1195         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1196                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1197         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1198                         HDMI_I2S_ORG_SMP_FREQ_44_1
1199                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1200                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1201
1202         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1203 }
1204
1205 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1206 {
1207         if (!hdata->has_hdmi_audio)
1208                 return;
1209
1210         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1211         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1212                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1213 }
1214
1215 static void hdmi_conf_reset(struct hdmi_context *hdata)
1216 {
1217         u32 reg;
1218
1219         /* disable hpd handle for drm */
1220         hdata->hpd_handle = false;
1221
1222         if (hdata->is_v13)
1223                 reg = HDMI_V13_CORE_RSTOUT;
1224         else
1225                 reg = HDMI_CORE_RSTOUT;
1226
1227         /* resetting HDMI core */
1228         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1229         mdelay(10);
1230         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1231         mdelay(10);
1232
1233         /* enable hpd handle for drm */
1234         hdata->hpd_handle = true;
1235 }
1236
1237 static void hdmi_enable_video(struct hdmi_context *hdata)
1238 {
1239         if (hdata->is_v13)
1240                 return;
1241
1242         hdata->video_enabled = true;
1243         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1244 }
1245
1246 static void hdmi_disable_video(struct hdmi_context *hdata)
1247 {
1248         if (hdata->is_v13)
1249                 return;
1250
1251         /* Set the blue screen color to black */
1252         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_0, 0);
1253         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_1, 0);
1254         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_0, 0);
1255         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_1, 0);
1256         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_0, 0);
1257         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_1, 0);
1258
1259         /* Enable the "blue screen", which effectively disconnects the mixer */
1260         hdata->video_enabled = false;
1261         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
1262 }
1263
1264 static void hdmi_conf_init(struct hdmi_context *hdata)
1265 {
1266         struct hdmi_infoframe infoframe;
1267         /* disable hpd handle for drm */
1268         hdata->hpd_handle = false;
1269
1270         /* enable HPD interrupts */
1271         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1272                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1273         mdelay(10);
1274         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1275                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1276
1277         /* choose HDMI mode */
1278         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1279                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1280
1281         if (hdata->video_enabled)
1282                 hdmi_enable_video(hdata);
1283         else
1284                 hdmi_disable_video(hdata);
1285
1286         if (!hdata->has_hdmi_sink) {
1287                 /* choose DVI mode */
1288                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1289                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1290                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1291                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1292         }
1293
1294         if (hdata->is_v13) {
1295                 /* choose bluescreen (fecal) color */
1296                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1297                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1298                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1299
1300                 /* enable AVI packet every vsync, fixes purple line problem */
1301                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1302                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1303                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1304                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1305
1306                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1307                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1308                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1309         } else {
1310                 /* enable AVI packet every vsync, fixes purple line problem */
1311                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1312
1313                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1314                 infoframe.ver = HDMI_AVI_VERSION;
1315                 infoframe.len = HDMI_AVI_LENGTH;
1316                 hdmi_reg_infoframe(hdata, &infoframe);
1317
1318                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1319                 infoframe.ver = HDMI_AUI_VERSION;
1320                 infoframe.len = HDMI_AUI_LENGTH;
1321                 hdmi_reg_infoframe(hdata, &infoframe);
1322
1323         }
1324
1325         /* enable hpd handle for drm */
1326         hdata->hpd_handle = true;
1327 }
1328
1329 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1330 {
1331         const struct hdmi_v13_preset_conf *conf =
1332                 hdmi_v13_confs[hdata->cur_conf].conf;
1333         const struct hdmi_v13_core_regs *core = &conf->core;
1334         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1335         int tries;
1336
1337         /* setting core registers */
1338         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1339         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1340         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1341         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1342         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1343         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1344         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1345         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1346         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1347         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1348         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1349         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1350         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1351         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1352         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1353         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1354         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1355         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1356         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1357         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1358         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1359         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1360         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1361         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1362         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1363         /* Timing generator registers */
1364         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1365         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1366         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1367         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1368         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1369         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1370         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1371         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1372         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1373         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1374         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1375         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1376         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1377         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1378         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1379         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1380         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1381         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1382         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1383         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1384         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1385         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1386         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1387         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1388         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1389         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1390         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1391         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1392
1393         /* waiting for HDMIPHY's PLL to get to steady state */
1394         for (tries = 100; tries; --tries) {
1395                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1396                 if (val & HDMI_PHY_STATUS_READY)
1397                         break;
1398                 mdelay(1);
1399         }
1400         /* steady state not achieved */
1401         if (tries == 0) {
1402                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1403                 hdmi_regs_dump(hdata, "timing apply");
1404         }
1405
1406         clk_disable(hdata->res.sclk_hdmi);
1407         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1408         clk_enable(hdata->res.sclk_hdmi);
1409
1410         /* enable HDMI and timing generator */
1411         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1412         if (core->int_pro_mode[0])
1413                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1414                                 HDMI_FIELD_EN);
1415         else
1416                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1417 }
1418
1419 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1420 {
1421         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1422         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1423         int tries;
1424
1425         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1426         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1427         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1428         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1429         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1430         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1431         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1432         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1433         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1434         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1435         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1436         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1437         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1438         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1439         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1440         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1441         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1442         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1443         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1444         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1445         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1446         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1447                         core->v_sync_line_bef_2[0]);
1448         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1449                         core->v_sync_line_bef_2[1]);
1450         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1451                         core->v_sync_line_bef_1[0]);
1452         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1453                         core->v_sync_line_bef_1[1]);
1454         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1455                         core->v_sync_line_aft_2[0]);
1456         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1457                         core->v_sync_line_aft_2[1]);
1458         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1459                         core->v_sync_line_aft_1[0]);
1460         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1461                         core->v_sync_line_aft_1[1]);
1462         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1463                         core->v_sync_line_aft_pxl_2[0]);
1464         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1465                         core->v_sync_line_aft_pxl_2[1]);
1466         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1467                         core->v_sync_line_aft_pxl_1[0]);
1468         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1469                         core->v_sync_line_aft_pxl_1[1]);
1470         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1471         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1472         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1473         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1474         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1475         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1476         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1477         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1478         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1479                         core->v_sync_line_aft_3[0]);
1480         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1481                         core->v_sync_line_aft_3[1]);
1482         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1483                         core->v_sync_line_aft_4[0]);
1484         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1485                         core->v_sync_line_aft_4[1]);
1486         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1487                         core->v_sync_line_aft_5[0]);
1488         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1489                         core->v_sync_line_aft_5[1]);
1490         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1491                         core->v_sync_line_aft_6[0]);
1492         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1493                         core->v_sync_line_aft_6[1]);
1494         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1495                         core->v_sync_line_aft_pxl_3[0]);
1496         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1497                         core->v_sync_line_aft_pxl_3[1]);
1498         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1499                         core->v_sync_line_aft_pxl_4[0]);
1500         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1501                         core->v_sync_line_aft_pxl_4[1]);
1502         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1503                         core->v_sync_line_aft_pxl_5[0]);
1504         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1505                         core->v_sync_line_aft_pxl_5[1]);
1506         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1507                         core->v_sync_line_aft_pxl_6[0]);
1508         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1509                         core->v_sync_line_aft_pxl_6[1]);
1510         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1511         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1512         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1513         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1514         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1515         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1516         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1517         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1518         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1519         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1520         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1521         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1522
1523         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1524         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1525         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1526         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1527         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1528         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1529         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1531         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1532         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1533         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1534         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1535         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1536         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1537         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1538         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1539         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1540         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1541         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1542         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1543         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1544         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1545         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1546         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1547         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1548         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1549         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1550         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1551         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1552         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1553         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1554         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1555         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1556
1557         /* waiting for HDMIPHY's PLL to get to steady state */
1558         for (tries = 100; tries; --tries) {
1559                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1560                 if (val & HDMI_PHY_STATUS_READY)
1561                         break;
1562                 mdelay(1);
1563         }
1564         /* steady state not achieved */
1565         if (tries == 0) {
1566                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1567                 hdmi_regs_dump(hdata, "timing apply");
1568         }
1569
1570         clk_disable(hdata->res.sclk_hdmi);
1571         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1572         clk_enable(hdata->res.sclk_hdmi);
1573
1574         /* enable HDMI and timing generator */
1575         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1576         if (core->int_pro_mode[0])
1577                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1578                                 HDMI_FIELD_EN);
1579         else
1580                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1581 }
1582
1583 static void hdmi_timing_apply(struct hdmi_context *hdata)
1584 {
1585         if (hdata->is_v13)
1586                 hdmi_v13_timing_apply(hdata);
1587         else
1588                 hdmi_v14_timing_apply(hdata);
1589 }
1590
1591 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1592 {
1593         u8 buffer[2];
1594         u32 reg;
1595
1596         clk_disable(hdata->res.sclk_hdmi);
1597         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1598         clk_enable(hdata->res.sclk_hdmi);
1599
1600         /* operation mode */
1601         buffer[0] = 0x1f;
1602         buffer[1] = 0x00;
1603
1604         if (hdata->hdmiphy_port)
1605                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1606
1607         if (hdata->is_v13)
1608                 reg = HDMI_V13_PHY_RSTOUT;
1609         else
1610                 reg = HDMI_PHY_RSTOUT;
1611
1612         /* reset hdmiphy */
1613         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1614         mdelay(10);
1615         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1616         mdelay(10);
1617 }
1618
1619 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1620 {
1621         const u8 *hdmiphy_data;
1622         u8 buffer[32];
1623         u8 operation[2];
1624         u8 read_buffer[32] = {0, };
1625         int ret;
1626         int i;
1627
1628         if (!hdata->hdmiphy_port) {
1629                 DRM_ERROR("hdmiphy is not attached\n");
1630                 return;
1631         }
1632
1633         /* pixel clock */
1634         if (hdata->is_v13) {
1635                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1636         } else {
1637                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1638                 hdmiphy_data = phy_configs[i].conf;
1639         }
1640
1641         memcpy(buffer, hdmiphy_data, 32);
1642         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1643         if (ret != 32) {
1644                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1645                 return;
1646         }
1647
1648         mdelay(10);
1649
1650         /* operation mode */
1651         operation[0] = 0x1f;
1652         operation[1] = 0x80;
1653
1654         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1655         if (ret != 2) {
1656                 DRM_ERROR("failed to enable hdmiphy\n");
1657                 return;
1658         }
1659
1660         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1661         if (ret < 0) {
1662                 DRM_ERROR("failed to read hdmiphy config\n");
1663                 return;
1664         }
1665
1666         for (i = 0; i < ret; i++)
1667                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1668                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1669 }
1670
1671 static void hdmi_conf_apply(struct hdmi_context *hdata)
1672 {
1673         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1674
1675         hdmiphy_conf_reset(hdata);
1676         hdmiphy_conf_apply(hdata);
1677
1678         hdmi_conf_reset(hdata);
1679         hdmi_conf_init(hdata);
1680         if (!hdata->is_soc_exynos5)
1681                 hdmi_audio_init(hdata);
1682
1683         /* setting core registers */
1684         hdmi_timing_apply(hdata);
1685         if (!hdata->is_soc_exynos5)
1686                 hdmi_audio_control(hdata, true);
1687
1688         hdmi_regs_dump(hdata, "start");
1689 }
1690
1691 static void hdmi_mode_copy(struct drm_display_mode *dst,
1692         struct drm_display_mode *src)
1693 {
1694         struct drm_mode_object base;
1695
1696         /* following information should be preserved,
1697          * required for releasing the drm_display_mode node,
1698          * duplicated to recieve adjustment info. */
1699
1700         base.id = dst->base.id;
1701         base.type = dst->base.type;
1702
1703         memcpy(dst, src, sizeof(struct drm_display_mode));
1704
1705         dst->base.id = base.id;
1706         dst->base.type = base.type;
1707 }
1708
1709 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1710                                 struct drm_display_mode *mode,
1711                                 struct drm_display_mode *adjusted_mode)
1712 {
1713         struct drm_display_mode *m;
1714         struct hdmi_context *hdata = ctx;
1715         int index;
1716
1717         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1718
1719         drm_mode_set_crtcinfo(adjusted_mode, 0);
1720
1721         if (hdata->is_v13)
1722                 index = hdmi_v13_conf_index(adjusted_mode);
1723         else
1724                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1725
1726         /* just return if user desired mode exists. */
1727         if (index >= 0)
1728                 return;
1729
1730         /*
1731          * otherwise, find the most suitable mode among modes and change it
1732          * to adjusted_mode.
1733          */
1734         list_for_each_entry(m, &connector->modes, head) {
1735                 if (hdata->is_v13)
1736                         index = hdmi_v13_conf_index(m);
1737                 else
1738                         index = find_hdmiphy_conf(m->clock * 1000);
1739
1740                 if (index >= 0) {
1741                         DRM_INFO("desired mode doesn't exist so\n");
1742                         DRM_INFO("use the most suitable mode among modes.\n");
1743                         hdmi_mode_copy(adjusted_mode, m);
1744                         break;
1745                 }
1746         }
1747 }
1748
1749 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1750 {
1751         int i;
1752         BUG_ON(num_bytes > 4);
1753         for (i = 0; i < num_bytes; i++)
1754                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1755 }
1756
1757 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1758                         struct drm_display_mode *m)
1759 {
1760         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1761         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1762
1763         hdata->mode_conf.vic = drm_match_cea_mode(m);
1764
1765         hdata->mode_conf.pixel_clock = m->clock * 1000;
1766         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1767         hdmi_set_reg(core->v_line, 2, m->vtotal);
1768         hdmi_set_reg(core->h_line, 2, m->htotal);
1769         hdmi_set_reg(core->hsync_pol, 1,
1770                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1771         hdmi_set_reg(core->vsync_pol, 1,
1772                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1773         hdmi_set_reg(core->int_pro_mode, 1,
1774                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1775
1776         /*
1777          * Quirk requirement for exynos 5 HDMI IP design,
1778          * 2 pixels less than the actual calculation for hsync_start
1779          * and end.
1780          */
1781
1782         /* Following values & calculations differ for different type of modes */
1783         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1784                 /* Interlaced Mode */
1785                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1786                         (m->vsync_end - m->vdisplay) / 2);
1787                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1788                         (m->vsync_start - m->vdisplay) / 2);
1789                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1790                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1791                 hdmi_set_reg(core->v_blank_f0, 2,
1792                         (m->vtotal + ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1793                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1794                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1795                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1796                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1797                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1798                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1799                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1800                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1801                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1802                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1803                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1804                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1805         } else {
1806                 /* Progressive Mode */
1807                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1808                         m->vsync_end - m->vdisplay);
1809                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1810                         m->vsync_start - m->vdisplay);
1811                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1812                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1813                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1814                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1815                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1816                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1817                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1818                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1819                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1820                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1821                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1822                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1823                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1824         }
1825
1826         /* Following values & calculations are same irrespective of mode type */
1827         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1828         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1829         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1830         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1831         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1832         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1833         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1834         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1835         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1836         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1837         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1838         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1839         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1840         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1841         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1842         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1843         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1844         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1845         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1846         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1847
1848         /* Timing generator registers */
1849         hdmi_set_reg(tg->cmd, 1, 0x0);
1850         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1851         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1852         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1853         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1854         hdmi_set_reg(tg->vsync, 2, 0x1);
1855         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1856         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1857         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1858         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1859         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1860         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1861         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1862
1863         if (hdata->is_soc_exynos5) {
1864                 /* Workaround 4 implementation for 1440x900 resolution support */
1865                 if (m->hdisplay == 1440 && m->vdisplay == 900 && m->clock == 106500) {
1866                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0xe0);
1867                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0xe0);
1868                 }
1869
1870                 /* Workaround 3 implementation for 800x600 resolution support */
1871                 if (m->hdisplay == 800 && m->vdisplay == 600 && m->clock == 40000) {
1872                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0x20);
1873                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0x20);
1874                 }
1875         }
1876 }
1877
1878 static void hdmi_mode_set(void *ctx, void *mode)
1879 {
1880         struct hdmi_context *hdata = ctx;
1881
1882         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1883
1884         if (hdata->is_v13)
1885                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1886         else
1887                 hdmi_v14_mode_set(hdata, mode);
1888 }
1889
1890 static void hdmi_commit(void *ctx)
1891 {
1892         struct hdmi_context *hdata = ctx;
1893
1894         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1895         if (!hdata->is_hdmi_powered_on)
1896                 return;
1897
1898         hdmi_conf_apply(hdata);
1899         hdata->enabled = true;
1900 }
1901
1902 static void hdmi_apply(void *ctx)
1903 {
1904         hdmi_commit(ctx);
1905 }
1906
1907 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
1908                                u8 reg, u8 mask, u8 val)
1909 {
1910         int ret;
1911         u8 buffer[2];
1912
1913         buffer[0] = reg;
1914         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
1915         reg_cache[reg] = buffer[1];
1916
1917         ret = i2c_master_send(client, buffer, 2);
1918         if (ret != 2)
1919                 return -EIO;
1920
1921         return 0;
1922 }
1923
1924 static int hdmiphy_s_power(struct i2c_client *client, bool on)
1925 {
1926         u8 reg_cache[32] = { 0 };
1927         u8 buffer[2];
1928         int ret;
1929
1930         DRM_DEBUG_KMS("%s: hdmiphy is %s\n", __func__, on ? "on" : "off");
1931
1932         /* Cache all 32 registers to make the code below faster */
1933         buffer[0] = 0x0;
1934         ret = i2c_master_send(client, buffer, 1);
1935         if (ret != 1) {
1936                 ret = -EIO;
1937                 goto exit;
1938         }
1939         ret = i2c_master_recv(client, reg_cache, 32);
1940         if (ret != 32) {
1941                 ret = -EIO;
1942                 goto exit;
1943         }
1944
1945         /* Go to/from configuration from/to operation mode */
1946         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
1947                                   on ? 0x80 : 0x00);
1948         if (ret)
1949                 goto exit;
1950
1951         /*
1952          * Turn off undocumented "oscpad" if !on; it turns on again in
1953          * hdmiphy_conf_apply()
1954          */
1955         if (!on)
1956                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
1957                 if (ret)
1958                         goto exit;
1959
1960         /* Disable powerdown if on; enable if !on */
1961         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
1962                                   on ? 0 : ~0);
1963         if (ret)
1964                 goto exit;
1965         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
1966                                   on ? 0 : ~0);
1967         if (ret)
1968                 goto exit;
1969
1970         /*
1971          * Turn off bit 3 of reg 4 if !on; it turns on again in
1972          * hdmiphy_conf_apply().  It's unclear what this bit does.
1973          */
1974         if (!on)
1975                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
1976                 if (ret)
1977                         goto exit;
1978
1979 exit:
1980         /* Don't expect any errors so just do a single warn */
1981         WARN_ON(ret);
1982
1983         return ret;
1984 }
1985
1986 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1987 {
1988         struct hdmi_resources *res = &hdata->res;
1989
1990         hdata->is_hdmi_powered_on = true;
1991         hdmi_cfg_hpd(hdata, false);
1992
1993         /* irq change by TV power status */
1994         if (hdata->curr_irq == hdata->internal_irq)
1995                 return;
1996
1997         disable_irq(hdata->curr_irq);
1998
1999         hdata->curr_irq = hdata->internal_irq;
2000
2001         enable_irq(hdata->curr_irq);
2002
2003         /* turn HDMI power on */
2004         regulator_bulk_enable(res->regul_count, res->regul_bulk);
2005
2006         /* power-on hdmi clocks */
2007         clk_enable(res->hdmiphy);
2008
2009         hdmiphy_s_power(hdata->hdmiphy_port, 1);
2010         hdmiphy_conf_reset(hdata);
2011         hdmi_conf_reset(hdata);
2012         hdmi_conf_init(hdata);
2013         if (!hdata->is_soc_exynos5)
2014                 hdmi_audio_init(hdata);
2015         hdmi_commit(hdata);
2016 }
2017
2018 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2019 {
2020         struct hdmi_resources *res = &hdata->res;
2021
2022         hdmi_cfg_hpd(hdata, true);
2023
2024         if (hdata->curr_irq == hdata->external_irq)
2025                 return;
2026
2027         disable_irq(hdata->curr_irq);
2028         hdata->curr_irq = hdata->external_irq;
2029
2030         enable_irq(hdata->curr_irq);
2031         hdata->is_hdmi_powered_on = false;
2032
2033         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2034         hdmiphy_conf_reset(hdata);
2035
2036         /* power-off hdmi clocks */
2037         clk_disable(res->hdmiphy);
2038
2039         /* turn HDMI power off */
2040         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2041 }
2042
2043 static int hdmi_power(void *ctx, int mode)
2044 {
2045         struct hdmi_context *hdata = ctx;
2046
2047         switch (mode) {
2048         case DRM_MODE_DPMS_ON:
2049                 if (!hdata->is_hdmi_powered_on)
2050                         hdmi_resource_poweron(hdata);
2051                 hdmi_enable_video(hdata);
2052                 break;
2053         case DRM_MODE_DPMS_STANDBY:
2054                 hdmi_disable_video(hdata);
2055                 break;
2056         case DRM_MODE_DPMS_OFF:
2057         case DRM_MODE_DPMS_SUSPEND:
2058                 if (hdata->is_hdmi_powered_on)
2059                         hdmi_resource_poweroff(hdata);
2060                 break;
2061         default:
2062                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2063                 break;
2064         }
2065
2066         return 0;
2067 }
2068
2069 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
2070 {
2071         struct hdmi_context *hdata = ctx;
2072
2073         hdata->drm_dev = drm_dev;
2074
2075         return 0;
2076 }
2077
2078 static struct exynos_panel_ops hdmi_ops = {
2079         /* display */
2080         .subdrv_probe   = hdmi_subdrv_probe,
2081         .is_connected   = hdmi_is_connected,
2082         .get_edid       = hdmi_get_edid,
2083         .check_timing   = hdmi_check_timing,
2084         .power          = hdmi_power,
2085
2086         /* manager */
2087         .mode_fixup     = hdmi_mode_fixup,
2088         .mode_set       = hdmi_mode_set,
2089         .commit         = hdmi_commit,
2090         .apply          = hdmi_apply,
2091 };
2092
2093 /*
2094  * Handle hotplug events outside the interrupt handler proper.
2095  */
2096 static void hdmi_hotplug_func(struct work_struct *work)
2097 {
2098         struct hdmi_context *hdata =
2099                 container_of(work, struct hdmi_context, hotplug_work);
2100
2101         drm_helper_hpd_irq_event(hdata->drm_dev);
2102 }
2103
2104 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
2105 {
2106         struct hdmi_context *hdata = arg;
2107         u32 intc_flag;
2108         if (hdata->is_hdmi_powered_on) {
2109                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
2110                 /* clearing flags for HPD plug/unplug */
2111                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2112                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
2113                                 hdata->hpd_handle);
2114                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2115                                 HDMI_INTC_FLAG_HPD_UNPLUG);
2116                 }
2117                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2118                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
2119                                 hdata->hpd_handle);
2120                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2121                                 HDMI_INTC_FLAG_HPD_PLUG);
2122                 }
2123         }
2124
2125         if (hdata->drm_dev && hdata->hpd_handle)
2126                 queue_work(hdata->wq, &hdata->hotplug_work);
2127
2128         return IRQ_HANDLED;
2129 }
2130
2131 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2132 {
2133         struct device *dev = hdata->dev;
2134         struct hdmi_resources *res = &hdata->res;
2135 #ifndef CONFIG_ARCH_EXYNOS5
2136         static char *supply[] = {
2137                 "hdmi-en",
2138                 "vdd",
2139                 "vdd_osc",
2140                 "vdd_pll",
2141         };
2142         int i, ret;
2143 #endif
2144
2145         DRM_DEBUG_KMS("HDMI resource init\n");
2146
2147         memset(res, 0, sizeof *res);
2148
2149         /* get clocks, power */
2150         res->hdmi = clk_get(dev, "hdmi");
2151         if (IS_ERR_OR_NULL(res->hdmi)) {
2152                 DRM_ERROR("failed to get clock 'hdmi'\n");
2153                 goto fail;
2154         }
2155         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
2156         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
2157                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2158                 goto fail;
2159         }
2160         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2161         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2162                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2163                 goto fail;
2164         }
2165         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2166         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2167                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2168                 goto fail;
2169         }
2170         res->hdmiphy = clk_get(dev, "hdmiphy");
2171         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2172                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2173                 goto fail;
2174         }
2175
2176         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2177
2178 #ifndef CONFIG_ARCH_EXYNOS5
2179         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2180                 sizeof res->regul_bulk[0], GFP_KERNEL);
2181         if (!res->regul_bulk) {
2182                 DRM_ERROR("failed to get memory for regulators\n");
2183                 goto fail;
2184         }
2185         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2186                 res->regul_bulk[i].supply = supply[i];
2187                 res->regul_bulk[i].consumer = NULL;
2188         }
2189         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2190         if (ret) {
2191                 DRM_ERROR("failed to get regulators\n");
2192                 goto fail;
2193         }
2194         res->regul_count = ARRAY_SIZE(supply);
2195 #endif
2196         /* TODO:
2197          * These clocks also should be added in
2198          * runtime resume and runtime suspend
2199          */
2200         clk_enable(res->hdmi);
2201         clk_enable(res->sclk_hdmi);
2202
2203         return 0;
2204 fail:
2205         DRM_ERROR("HDMI resource init - failed\n");
2206         return -ENODEV;
2207 }
2208
2209 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2210 {
2211         struct hdmi_resources *res = &hdata->res;
2212
2213         regulator_bulk_free(res->regul_count, res->regul_bulk);
2214         /* kfree is NULL-safe */
2215         kfree(res->regul_bulk);
2216         if (!IS_ERR_OR_NULL(res->hdmiphy))
2217                 clk_put(res->hdmiphy);
2218         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2219                 clk_put(res->sclk_hdmiphy);
2220         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2221                 clk_put(res->sclk_pixel);
2222         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2223                 clk_put(res->sclk_hdmi);
2224         if (!IS_ERR_OR_NULL(res->hdmi))
2225                 clk_put(res->hdmi);
2226         memset(res, 0, sizeof *res);
2227
2228         return 0;
2229 }
2230
2231 static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
2232
2233 void hdmi_attach_ddc_client(struct i2c_client *ddc)
2234 {
2235         if (ddc)
2236                 hdmi_ddc = ddc;
2237 }
2238
2239 void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
2240 {
2241         if (hdmiphy)
2242                 hdmi_hdmiphy = hdmiphy;
2243 }
2244
2245 struct platform_device *hdmi_audio_device;
2246
2247 int hdmi_register_audio_device(struct platform_device *pdev)
2248 {
2249         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2250         struct platform_device *audio_dev;
2251         int ret;
2252
2253         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2254         if (!audio_dev) {
2255                 DRM_ERROR("hdmi audio device allocation failed.\n");
2256                 ret = -ENOMEM;
2257                 goto err;
2258         }
2259
2260         ret = platform_device_add_resources(audio_dev, pdev->resource,
2261                         pdev->num_resources);
2262         if (ret) {
2263                 ret = -ENOMEM;
2264                 goto err_device;
2265         }
2266
2267         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2268         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2269
2270         ret = platform_device_add(audio_dev);
2271         if (ret) {
2272                 DRM_ERROR("hdmi audio device add failed.\n");
2273                 goto err_device;
2274         }
2275
2276         hdmi_audio_device = audio_dev;
2277         return 0;
2278
2279 err_device:
2280         platform_device_put(audio_dev);
2281
2282 err:
2283         return ret;
2284 }
2285
2286 void hdmi_unregister_audio_device(void)
2287 {
2288         platform_device_unregister(hdmi_audio_device);
2289 }
2290
2291 static int __devinit hdmi_probe(struct platform_device *pdev)
2292 {
2293         struct device *dev = &pdev->dev;
2294         struct hdmi_context *hdata;
2295         struct exynos_drm_hdmi_pdata *pdata;
2296         struct resource *res;
2297         int ret;
2298         enum of_gpio_flags flags;
2299
2300         DRM_DEBUG_KMS("[%d]\n", __LINE__);
2301
2302         pdata = pdev->dev.platform_data;
2303         if (!pdata) {
2304                 DRM_ERROR("no platform data specified\n");
2305                 return -EINVAL;
2306         }
2307
2308         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2309         if (!hdata) {
2310                 DRM_ERROR("out of memory\n");
2311                 return -ENOMEM;
2312         }
2313
2314         platform_set_drvdata(pdev, hdata);
2315
2316         hdata->is_v13 = pdata->is_v13;
2317         hdata->default_win = pdata->default_win;
2318         hdata->default_timing = &pdata->timing;
2319         hdata->default_bpp = pdata->bpp;
2320         hdata->dev = dev;
2321         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2322                 "samsung,exynos5-hdmi");
2323
2324         ret = hdmi_resources_init(hdata);
2325         if (ret) {
2326                 ret = -EINVAL;
2327                 goto err_data;
2328         }
2329
2330         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2331         if (!res) {
2332                 DRM_ERROR("failed to find registers\n");
2333                 ret = -ENOENT;
2334                 goto err_resource;
2335         }
2336
2337         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2338                                            dev_name(dev));
2339         if (!hdata->regs_res) {
2340                 DRM_ERROR("failed to claim register region\n");
2341                 ret = -ENOENT;
2342                 goto err_resource;
2343         }
2344
2345         hdata->regs = ioremap(res->start, resource_size(res));
2346         if (!hdata->regs) {
2347                 DRM_ERROR("failed to map registers\n");
2348                 ret = -ENXIO;
2349                 goto err_req_region;
2350         }
2351
2352         /* DDC i2c driver */
2353         if (i2c_add_driver(&ddc_driver)) {
2354                 DRM_ERROR("failed to register ddc i2c driver\n");
2355                 ret = -ENOENT;
2356                 goto err_iomap;
2357         }
2358
2359         hdata->ddc_port = hdmi_ddc;
2360
2361         /* hdmiphy i2c driver */
2362         if (i2c_add_driver(&hdmiphy_driver)) {
2363                 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2364                 ret = -ENOENT;
2365                 goto err_ddc;
2366         }
2367
2368         hdata->hdmiphy_port = hdmi_hdmiphy;
2369
2370         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2371         if (res == NULL) {
2372                 DRM_ERROR("get interrupt resource failed.\n");
2373                 ret = -ENXIO;
2374                 goto err_hdmiphy;
2375         }
2376
2377         hdata->internal_irq = res->start;
2378
2379         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2380                                 "hpd-gpio", 0, &flags);
2381
2382         if (!gpio_is_valid(hdata->hpd_gpio)) {
2383                 DRM_ERROR("failed to get hpd gpio.");
2384                 ret = -EINVAL;
2385                 goto err_hdmiphy;
2386         }
2387
2388         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2389
2390         /* create workqueue and hotplug work */
2391         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2392                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2393         if (hdata->wq == NULL) {
2394                 DRM_ERROR("Failed to create workqueue.\n");
2395                 ret = -ENOMEM;
2396                 goto err_hdmiphy;
2397         }
2398         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2399
2400         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2401                         IRQF_SHARED, "int_hdmi", hdata);
2402         if (ret) {
2403                 DRM_ERROR("request int interrupt failed.\n");
2404                 goto err_workqueue;
2405         }
2406         disable_irq(hdata->internal_irq);
2407
2408         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2409                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2410                 hdata);
2411         if (ret) {
2412                 DRM_ERROR("request ext interrupt failed.\n");
2413                 goto err_int_irq;
2414         }
2415         disable_irq(hdata->external_irq);
2416
2417         if (of_device_is_compatible(dev->of_node,
2418                 "samsung,exynos5-hdmi")) {
2419                 ret = hdmi_register_audio_device(pdev);
2420                 if (ret) {
2421                         DRM_ERROR("hdmi-audio device registering failed.\n");
2422                         goto err_ext_irq;
2423                 }
2424         }
2425
2426         hdmi_resource_poweron(hdata);
2427
2428         if (!hdmi_is_connected(hdata)) {
2429                 hdmi_resource_poweroff(hdata);
2430                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2431         }
2432
2433         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2434                         hdata);
2435
2436         return 0;
2437
2438 err_ext_irq:
2439         free_irq(hdata->external_irq, hdata);
2440 err_int_irq:
2441         free_irq(hdata->internal_irq, hdata);
2442  err_workqueue:
2443         destroy_workqueue(hdata->wq);
2444 err_hdmiphy:
2445         i2c_del_driver(&hdmiphy_driver);
2446 err_ddc:
2447         i2c_del_driver(&ddc_driver);
2448 err_iomap:
2449         iounmap(hdata->regs);
2450 err_req_region:
2451         release_mem_region(hdata->regs_res->start,
2452                         resource_size(hdata->regs_res));
2453 err_resource:
2454         hdmi_resources_cleanup(hdata);
2455 err_data:
2456         kfree(hdata);
2457         return ret;
2458 }
2459
2460 static int __devexit hdmi_remove(struct platform_device *pdev)
2461 {
2462         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2463         struct hdmi_resources *res = &hdata->res;
2464
2465         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2466
2467         hdmi_resource_poweroff(hdata);
2468
2469         hdmi_unregister_audio_device();
2470
2471         disable_irq(hdata->curr_irq);
2472         free_irq(hdata->internal_irq, hdata);
2473         free_irq(hdata->external_irq, hdata);
2474
2475         cancel_work_sync(&hdata->hotplug_work);
2476         destroy_workqueue(hdata->wq);
2477
2478         clk_disable(res->hdmi);
2479         clk_disable(res->sclk_hdmi);
2480         hdmi_resources_cleanup(hdata);
2481
2482         iounmap(hdata->regs);
2483
2484         release_mem_region(hdata->regs_res->start,
2485                         resource_size(hdata->regs_res));
2486
2487         /* hdmiphy i2c driver */
2488         i2c_del_driver(&hdmiphy_driver);
2489         /* DDC i2c driver */
2490         i2c_del_driver(&ddc_driver);
2491
2492         kfree(hdata);
2493
2494         return 0;
2495 }
2496
2497 struct platform_driver hdmi_driver = {
2498         .probe          = hdmi_probe,
2499         .remove         = __devexit_p(hdmi_remove),
2500         .driver         = {
2501 #ifdef CONFIG_ARCH_EXYNOS5
2502                 .name   = "exynos5-hdmi",
2503 #else
2504                 .name   = "exynos4-hdmi",
2505 #endif
2506                 .owner  = THIS_MODULE,
2507         },
2508 };