drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/clk.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/io.h>
  37 #include <linux/of_gpio.h>
  38 #include <plat/gpio-cfg.h>
  39
  40 #include <drm/exynos_drm.h>
  41
  42 #include "exynos_drm_drv.h"
  43 #include "exynos_drm_hdmi.h"
  44
  45 #include "exynos_hdmi.h"
  46
  47 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  48
  49 struct hdmi_resources {
  50         struct clk                      *hdmi;
  51         struct clk                      *sclk_hdmi;
  52         struct clk                      *sclk_pixel;
  53         struct clk                      *sclk_hdmiphy;
  54         struct clk                      *hdmiphy;
  55         struct regulator_bulk_data      *regul_bulk;
  56         int                             regul_count;
  57 };
  58
  59 struct hdmi_tg_regs {
  60         u8 cmd[1];
  61         u8 h_fsz[2];
  62         u8 hact_st[2];
  63         u8 hact_sz[2];
  64         u8 v_fsz[2];
  65         u8 vsync[2];
  66         u8 vsync2[2];
  67         u8 vact_st[2];
  68         u8 vact_sz[2];
  69         u8 field_chg[2];
  70         u8 vact_st2[2];
  71         u8 vact_st3[2];
  72         u8 vact_st4[2];
  73         u8 vsync_top_hdmi[2];
  74         u8 vsync_bot_hdmi[2];
  75         u8 field_top_hdmi[2];
  76         u8 field_bot_hdmi[2];
  77         u8 tg_3d[1];
  78 };
  79
  80 struct hdmi_core_regs {
  81         u8 h_blank[2];
  82         u8 v2_blank[2];
  83         u8 v1_blank[2];
  84         u8 v_line[2];
  85         u8 h_line[2];
  86         u8 hsync_pol[1];
  87         u8 vsync_pol[1];
  88         u8 int_pro_mode[1];
  89         u8 v_blank_f0[2];
  90         u8 v_blank_f1[2];
  91         u8 h_sync_start[2];
  92         u8 h_sync_end[2];
  93         u8 v_sync_line_bef_2[2];
  94         u8 v_sync_line_bef_1[2];
  95         u8 v_sync_line_aft_2[2];
  96         u8 v_sync_line_aft_1[2];
  97         u8 v_sync_line_aft_pxl_2[2];
  98         u8 v_sync_line_aft_pxl_1[2];
  99         u8 v_blank_f2[2]; /* for 3D mode */
 100         u8 v_blank_f3[2]; /* for 3D mode */
 101         u8 v_blank_f4[2]; /* for 3D mode */
 102         u8 v_blank_f5[2]; /* for 3D mode */
 103         u8 v_sync_line_aft_3[2];
 104         u8 v_sync_line_aft_4[2];
 105         u8 v_sync_line_aft_5[2];
 106         u8 v_sync_line_aft_6[2];
 107         u8 v_sync_line_aft_pxl_3[2];
 108         u8 v_sync_line_aft_pxl_4[2];
 109         u8 v_sync_line_aft_pxl_5[2];
 110         u8 v_sync_line_aft_pxl_6[2];
 111         u8 vact_space_1[2];
 112         u8 vact_space_2[2];
 113         u8 vact_space_3[2];
 114         u8 vact_space_4[2];
 115         u8 vact_space_5[2];
 116         u8 vact_space_6[2];
 117 };
 118
 119 struct hdmi_mode_conf {
 120         int pixel_clock;
 121         struct hdmi_core_regs core;
 122         struct hdmi_tg_regs tg;
 123         u8 vic;
 124 };
 125
 126 struct hdmi_context {
 127         struct device                   *dev;
 128         struct drm_device               *drm_dev;
 129         struct fb_videomode             *default_timing;
 130         struct hdmi_mode_conf           mode_conf;
 131         unsigned int                    is_v13:1;
 132         unsigned int                    default_win;
 133         unsigned int                    default_bpp;
 134         bool                            hpd_handle;
 135         bool                            enabled;
 136         bool                            has_hdmi_sink;
 137         bool                            has_hdmi_audio;
 138         bool                            is_soc_exynos5;
 139         bool                            is_hdmi_powered_on;
 140
 141         struct resource                 *regs_res;
 142         void __iomem                    *regs;
 143         unsigned int                    external_irq;
 144         unsigned int                    internal_irq;
 145         unsigned int                    curr_irq;
 146         struct workqueue_struct         *wq;
 147         struct work_struct              hotplug_work;
 148
 149         struct i2c_client               *ddc_port;
 150         struct i2c_client               *hdmiphy_port;
 151         int                             hpd_gpio;
 152         /* current hdmiphy conf index */
 153         int cur_conf;
 154
 155         struct hdmi_resources           res;
 156         void                            *parent_ctx;
 157 };
 158
 159 /* HDMI Version 1.3 */
 160 static const u8 hdmiphy_v13_conf27[32] = {
 161         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 162         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 163         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 164         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 165 };
 166
 167 static const u8 hdmiphy_v13_conf27_027[32] = {
 168         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 169         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 170         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 171         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 172 };
 173
 174 static const u8 hdmiphy_v13_conf74_175[32] = {
 175         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 176         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 177         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 178         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 179 };
 180
 181 static const u8 hdmiphy_v13_conf74_25[32] = {
 182         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 183         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 184         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 185         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 186 };
 187
 188 static const u8 hdmiphy_v13_conf148_5[32] = {
 189         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 190         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 191         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 192         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 193 };
 194
 195 struct hdmi_v13_tg_regs {
 196         u8 cmd;
 197         u8 h_fsz_l;
 198         u8 h_fsz_h;
 199         u8 hact_st_l;
 200         u8 hact_st_h;
 201         u8 hact_sz_l;
 202         u8 hact_sz_h;
 203         u8 v_fsz_l;
 204         u8 v_fsz_h;
 205         u8 vsync_l;
 206         u8 vsync_h;
 207         u8 vsync2_l;
 208         u8 vsync2_h;
 209         u8 vact_st_l;
 210         u8 vact_st_h;
 211         u8 vact_sz_l;
 212         u8 vact_sz_h;
 213         u8 field_chg_l;
 214         u8 field_chg_h;
 215         u8 vact_st2_l;
 216         u8 vact_st2_h;
 217         u8 vsync_top_hdmi_l;
 218         u8 vsync_top_hdmi_h;
 219         u8 vsync_bot_hdmi_l;
 220         u8 vsync_bot_hdmi_h;
 221         u8 field_top_hdmi_l;
 222         u8 field_top_hdmi_h;
 223         u8 field_bot_hdmi_l;
 224         u8 field_bot_hdmi_h;
 225 };
 226
 227 struct hdmi_v13_core_regs {
 228         u8 h_blank[2];
 229         u8 v_blank[3];
 230         u8 h_v_line[3];
 231         u8 vsync_pol[1];
 232         u8 int_pro_mode[1];
 233         u8 v_blank_f[3];
 234         u8 h_sync_gen[3];
 235         u8 v_sync_gen1[3];
 236         u8 v_sync_gen2[3];
 237         u8 v_sync_gen3[3];
 238 };
 239
 240 struct hdmi_v13_preset_conf {
 241         struct hdmi_v13_core_regs core;
 242         struct hdmi_v13_tg_regs tg;
 243 };
 244
 245 struct hdmi_v13_conf {
 246         int width;
 247         int height;
 248         int vrefresh;
 249         bool interlace;
 250         const u8 *hdmiphy_data;
 251         const struct hdmi_v13_preset_conf *conf;
 252 };
 253
 254 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 255         .core = {
 256                 .h_blank = {0x8a, 0x00},
 257                 .v_blank = {0x0d, 0x6a, 0x01},
 258                 .h_v_line = {0x0d, 0xa2, 0x35},
 259                 .vsync_pol = {0x01},
 260                 .int_pro_mode = {0x00},
 261                 .v_blank_f = {0x00, 0x00, 0x00},
 262                 .h_sync_gen = {0x0e, 0x30, 0x11},
 263                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 264                 /* other don't care */
 265         },
 266         .tg = {
 267                 0x00, /* cmd */
 268                 0x5a, 0x03, /* h_fsz */
 269                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 270                 0x0d, 0x02, /* v_fsz */
 271                 0x01, 0x00, 0x33, 0x02, /* vsync */
 272                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 273                 0x33, 0x02, /* field_chg */
 274                 0x49, 0x02, /* vact_st2 */
 275                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 276                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 277         },
 278 };
 279
 280 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 281         .core = {
 282                 .h_blank = {0x72, 0x01},
 283                 .v_blank = {0xee, 0xf2, 0x00},
 284                 .h_v_line = {0xee, 0x22, 0x67},
 285                 .vsync_pol = {0x00},
 286                 .int_pro_mode = {0x00},
 287                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 288                 .h_sync_gen = {0x6c, 0x50, 0x02},
 289                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 290                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 291                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 292                 /* other don't care */
 293         },
 294         .tg = {
 295                 0x00, /* cmd */
 296                 0x72, 0x06, /* h_fsz */
 297                 0x71, 0x01, 0x01, 0x05, /* hact */
 298                 0xee, 0x02, /* v_fsz */
 299                 0x01, 0x00, 0x33, 0x02, /* vsync */
 300                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 301                 0x33, 0x02, /* field_chg */
 302                 0x49, 0x02, /* vact_st2 */
 303                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 304                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 305         },
 306 };
 307
 308 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 309         .core = {
 310                 .h_blank = {0xd0, 0x02},
 311                 .v_blank = {0x32, 0xB2, 0x00},
 312                 .h_v_line = {0x65, 0x04, 0xa5},
 313                 .vsync_pol = {0x00},
 314                 .int_pro_mode = {0x01},
 315                 .v_blank_f = {0x49, 0x2A, 0x23},
 316                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 317                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 318                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 319                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 320                 /* other don't care */
 321         },
 322         .tg = {
 323                 0x00, /* cmd */
 324                 0x50, 0x0A, /* h_fsz */
 325                 0xCF, 0x02, 0x81, 0x07, /* hact */
 326                 0x65, 0x04, /* v_fsz */
 327                 0x01, 0x00, 0x33, 0x02, /* vsync */
 328                 0x16, 0x00, 0x1c, 0x02, /* vact */
 329                 0x33, 0x02, /* field_chg */
 330                 0x49, 0x02, /* vact_st2 */
 331                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 332                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 333         },
 334 };
 335
 336 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 337         .core = {
 338                 .h_blank = {0xd0, 0x02},
 339                 .v_blank = {0x65, 0x6c, 0x01},
 340                 .h_v_line = {0x65, 0x04, 0xa5},
 341                 .vsync_pol = {0x00},
 342                 .int_pro_mode = {0x00},
 343                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 344                 .h_sync_gen = {0x0e, 0xea, 0x08},
 345                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 346                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 347                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 348                 /* other don't care */
 349         },
 350         .tg = {
 351                 0x00, /* cmd */
 352                 0x50, 0x0A, /* h_fsz */
 353                 0xCF, 0x02, 0x81, 0x07, /* hact */
 354                 0x65, 0x04, /* v_fsz */
 355                 0x01, 0x00, 0x33, 0x02, /* vsync */
 356                 0x2d, 0x00, 0x38, 0x04, /* vact */
 357                 0x33, 0x02, /* field_chg */
 358                 0x48, 0x02, /* vact_st2 */
 359                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 360                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 361         },
 362 };
 363
 364 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 365         .core = {
 366                 .h_blank = {0x18, 0x01},
 367                 .v_blank = {0x32, 0xB2, 0x00},
 368                 .h_v_line = {0x65, 0x84, 0x89},
 369                 .vsync_pol = {0x00},
 370                 .int_pro_mode = {0x01},
 371                 .v_blank_f = {0x49, 0x2A, 0x23},
 372                 .h_sync_gen = {0x56, 0x08, 0x02},
 373                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 374                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 375                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 376                 /* other don't care */
 377         },
 378         .tg = {
 379                 0x00, /* cmd */
 380                 0x98, 0x08, /* h_fsz */
 381                 0x17, 0x01, 0x81, 0x07, /* hact */
 382                 0x65, 0x04, /* v_fsz */
 383                 0x01, 0x00, 0x33, 0x02, /* vsync */
 384                 0x16, 0x00, 0x1c, 0x02, /* vact */
 385                 0x33, 0x02, /* field_chg */
 386                 0x49, 0x02, /* vact_st2 */
 387                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 388                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 389         },
 390 };
 391
 392 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 393         .core = {
 394                 .h_blank = {0x18, 0x01},
 395                 .v_blank = {0x65, 0x6c, 0x01},
 396                 .h_v_line = {0x65, 0x84, 0x89},
 397                 .vsync_pol = {0x00},
 398                 .int_pro_mode = {0x00},
 399                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 400                 .h_sync_gen = {0x56, 0x08, 0x02},
 401                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 402                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 403                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 404                 /* other don't care */
 405         },
 406         .tg = {
 407                 0x00, /* cmd */
 408                 0x98, 0x08, /* h_fsz */
 409                 0x17, 0x01, 0x81, 0x07, /* hact */
 410                 0x65, 0x04, /* v_fsz */
 411                 0x01, 0x00, 0x33, 0x02, /* vsync */
 412                 0x2d, 0x00, 0x38, 0x04, /* vact */
 413                 0x33, 0x02, /* field_chg */
 414                 0x48, 0x02, /* vact_st2 */
 415                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 416                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 417         },
 418 };
 419
 420 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 421         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 422         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 423         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 424         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 425         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 426                                  &hdmi_v13_conf_1080p50 },
 427         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 428         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 429                                  &hdmi_v13_conf_1080p60 },
 430 };
 431
 432 struct hdmiphy_config {
 433         int pixel_clock;
 434         u8 conf[32];
 435 };
 436
 437 static const struct hdmiphy_config phy_configs[] = {
 438         {
 439                 .pixel_clock = 27000000,
 440                 .conf = {
 441                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 442                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 443                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 444                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 445                 },
 446         },
 447         {
 448                 .pixel_clock = 27027000,
 449                 .conf = {
 450                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 451                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 452                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 453                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 454                 },
 455         },
 456         {
 457                 .pixel_clock = 74176000,
 458                 .conf = {
 459                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 460                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 461                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 462                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 463                 },
 464         },
 465         {
 466                 .pixel_clock = 74250000,
 467                 .conf = {
 468                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 469                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 470                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 471                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 472                 },
 473         },
 474         {
 475                 .pixel_clock = 148500000,
 476                 .conf = {
 477                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 478                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 479                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 480                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 481                 },
 482         },
 483 };
 484
 485 struct hdmi_infoframe {
 486         enum HDMI_PACKET_TYPE type;
 487         u8 ver;
 488         u8 len;
 489 };
 490
 491 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 492 {
 493         return readl(hdata->regs + reg_id);
 494 }
 495
 496 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 497                                  u32 reg_id, u8 value)
 498 {
 499         writeb(value, hdata->regs + reg_id);
 500 }
 501
 502 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 503                                  u32 reg_id, u32 value, u32 mask)
 504 {
 505         u32 old = readl(hdata->regs + reg_id);
 506         value = (value & mask) | (old & ~mask);
 507         writel(value, hdata->regs + reg_id);
 508 }
 509
 510 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 511 {
 512         if (external) {
 513                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 514                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 515         } else {
 516                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 517                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 518         }
 519 }
 520
 521 static int hdmi_get_hpd(struct hdmi_context *hdata)
 522 {
 523         return gpio_get_value(hdata->hpd_gpio);
 524 }
 525
 526 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 527 {
 528 #define DUMPREG(reg_id) \
 529         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 530         readl(hdata->regs + reg_id))
 531         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 532         DUMPREG(HDMI_INTC_FLAG);
 533         DUMPREG(HDMI_INTC_CON);
 534         DUMPREG(HDMI_HPD_STATUS);
 535         DUMPREG(HDMI_V13_PHY_RSTOUT);
 536         DUMPREG(HDMI_V13_PHY_VPLL);
 537         DUMPREG(HDMI_V13_PHY_CMU);
 538         DUMPREG(HDMI_V13_CORE_RSTOUT);
 539
 540         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 541         DUMPREG(HDMI_CON_0);
 542         DUMPREG(HDMI_CON_1);
 543         DUMPREG(HDMI_CON_2);
 544         DUMPREG(HDMI_SYS_STATUS);
 545         DUMPREG(HDMI_V13_PHY_STATUS);
 546         DUMPREG(HDMI_STATUS_EN);
 547         DUMPREG(HDMI_HPD);
 548         DUMPREG(HDMI_MODE_SEL);
 549         DUMPREG(HDMI_V13_HPD_GEN);
 550         DUMPREG(HDMI_V13_DC_CONTROL);
 551         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 552
 553         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 554         DUMPREG(HDMI_H_BLANK_0);
 555         DUMPREG(HDMI_H_BLANK_1);
 556         DUMPREG(HDMI_V13_V_BLANK_0);
 557         DUMPREG(HDMI_V13_V_BLANK_1);
 558         DUMPREG(HDMI_V13_V_BLANK_2);
 559         DUMPREG(HDMI_V13_H_V_LINE_0);
 560         DUMPREG(HDMI_V13_H_V_LINE_1);
 561         DUMPREG(HDMI_V13_H_V_LINE_2);
 562         DUMPREG(HDMI_VSYNC_POL);
 563         DUMPREG(HDMI_INT_PRO_MODE);
 564         DUMPREG(HDMI_V13_V_BLANK_F_0);
 565         DUMPREG(HDMI_V13_V_BLANK_F_1);
 566         DUMPREG(HDMI_V13_V_BLANK_F_2);
 567         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 568         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 569         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 570         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 571         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 572         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 573         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 574         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 575         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 576         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 577         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 578         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 579
 580         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 581         DUMPREG(HDMI_TG_CMD);
 582         DUMPREG(HDMI_TG_H_FSZ_L);
 583         DUMPREG(HDMI_TG_H_FSZ_H);
 584         DUMPREG(HDMI_TG_HACT_ST_L);
 585         DUMPREG(HDMI_TG_HACT_ST_H);
 586         DUMPREG(HDMI_TG_HACT_SZ_L);
 587         DUMPREG(HDMI_TG_HACT_SZ_H);
 588         DUMPREG(HDMI_TG_V_FSZ_L);
 589         DUMPREG(HDMI_TG_V_FSZ_H);
 590         DUMPREG(HDMI_TG_VSYNC_L);
 591         DUMPREG(HDMI_TG_VSYNC_H);
 592         DUMPREG(HDMI_TG_VSYNC2_L);
 593         DUMPREG(HDMI_TG_VSYNC2_H);
 594         DUMPREG(HDMI_TG_VACT_ST_L);
 595         DUMPREG(HDMI_TG_VACT_ST_H);
 596         DUMPREG(HDMI_TG_VACT_SZ_L);
 597         DUMPREG(HDMI_TG_VACT_SZ_H);
 598         DUMPREG(HDMI_TG_FIELD_CHG_L);
 599         DUMPREG(HDMI_TG_FIELD_CHG_H);
 600         DUMPREG(HDMI_TG_VACT_ST2_L);
 601         DUMPREG(HDMI_TG_VACT_ST2_H);
 602         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 603         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 604         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 605         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 606         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 607         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 608         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 609         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 610 #undef DUMPREG
 611 }
 612
 613 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 614 {
 615         int i;
 616
 617 #define DUMPREG(reg_id) \
 618         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 619         readl(hdata->regs + reg_id))
 620
 621         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 622         DUMPREG(HDMI_INTC_CON);
 623         DUMPREG(HDMI_INTC_FLAG);
 624         DUMPREG(HDMI_HPD_STATUS);
 625         DUMPREG(HDMI_INTC_CON_1);
 626         DUMPREG(HDMI_INTC_FLAG_1);
 627         DUMPREG(HDMI_PHY_STATUS_0);
 628         DUMPREG(HDMI_PHY_STATUS_PLL);
 629         DUMPREG(HDMI_PHY_CON_0);
 630         DUMPREG(HDMI_PHY_RSTOUT);
 631         DUMPREG(HDMI_PHY_VPLL);
 632         DUMPREG(HDMI_PHY_CMU);
 633         DUMPREG(HDMI_CORE_RSTOUT);
 634
 635         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 636         DUMPREG(HDMI_CON_0);
 637         DUMPREG(HDMI_CON_1);
 638         DUMPREG(HDMI_CON_2);
 639         DUMPREG(HDMI_SYS_STATUS);
 640         DUMPREG(HDMI_PHY_STATUS_0);
 641         DUMPREG(HDMI_STATUS_EN);
 642         DUMPREG(HDMI_HPD);
 643         DUMPREG(HDMI_MODE_SEL);
 644         DUMPREG(HDMI_ENC_EN);
 645         DUMPREG(HDMI_DC_CONTROL);
 646         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 647
 648         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 649         DUMPREG(HDMI_H_BLANK_0);
 650         DUMPREG(HDMI_H_BLANK_1);
 651         DUMPREG(HDMI_V2_BLANK_0);
 652         DUMPREG(HDMI_V2_BLANK_1);
 653         DUMPREG(HDMI_V1_BLANK_0);
 654         DUMPREG(HDMI_V1_BLANK_1);
 655         DUMPREG(HDMI_V_LINE_0);
 656         DUMPREG(HDMI_V_LINE_1);
 657         DUMPREG(HDMI_H_LINE_0);
 658         DUMPREG(HDMI_H_LINE_1);
 659         DUMPREG(HDMI_HSYNC_POL);
 660
 661         DUMPREG(HDMI_VSYNC_POL);
 662         DUMPREG(HDMI_INT_PRO_MODE);
 663         DUMPREG(HDMI_V_BLANK_F0_0);
 664         DUMPREG(HDMI_V_BLANK_F0_1);
 665         DUMPREG(HDMI_V_BLANK_F1_0);
 666         DUMPREG(HDMI_V_BLANK_F1_1);
 667
 668         DUMPREG(HDMI_H_SYNC_START_0);
 669         DUMPREG(HDMI_H_SYNC_START_1);
 670         DUMPREG(HDMI_H_SYNC_END_0);
 671         DUMPREG(HDMI_H_SYNC_END_1);
 672
 673         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 674         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 675         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 676         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 677
 678         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 679         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 680         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 681         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 682
 683         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 684         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 685         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 686         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 687
 688         DUMPREG(HDMI_V_BLANK_F2_0);
 689         DUMPREG(HDMI_V_BLANK_F2_1);
 690         DUMPREG(HDMI_V_BLANK_F3_0);
 691         DUMPREG(HDMI_V_BLANK_F3_1);
 692         DUMPREG(HDMI_V_BLANK_F4_0);
 693         DUMPREG(HDMI_V_BLANK_F4_1);
 694         DUMPREG(HDMI_V_BLANK_F5_0);
 695         DUMPREG(HDMI_V_BLANK_F5_1);
 696
 697         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 698         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 699         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 700         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 701         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 702         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 703         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 704         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 705
 706         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 707         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 708         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 709         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 710         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 711         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 712         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 713         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 714
 715         DUMPREG(HDMI_VACT_SPACE_1_0);
 716         DUMPREG(HDMI_VACT_SPACE_1_1);
 717         DUMPREG(HDMI_VACT_SPACE_2_0);
 718         DUMPREG(HDMI_VACT_SPACE_2_1);
 719         DUMPREG(HDMI_VACT_SPACE_3_0);
 720         DUMPREG(HDMI_VACT_SPACE_3_1);
 721         DUMPREG(HDMI_VACT_SPACE_4_0);
 722         DUMPREG(HDMI_VACT_SPACE_4_1);
 723         DUMPREG(HDMI_VACT_SPACE_5_0);
 724         DUMPREG(HDMI_VACT_SPACE_5_1);
 725         DUMPREG(HDMI_VACT_SPACE_6_0);
 726         DUMPREG(HDMI_VACT_SPACE_6_1);
 727
 728         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 729         DUMPREG(HDMI_TG_CMD);
 730         DUMPREG(HDMI_TG_H_FSZ_L);
 731         DUMPREG(HDMI_TG_H_FSZ_H);
 732         DUMPREG(HDMI_TG_HACT_ST_L);
 733         DUMPREG(HDMI_TG_HACT_ST_H);
 734         DUMPREG(HDMI_TG_HACT_SZ_L);
 735         DUMPREG(HDMI_TG_HACT_SZ_H);
 736         DUMPREG(HDMI_TG_V_FSZ_L);
 737         DUMPREG(HDMI_TG_V_FSZ_H);
 738         DUMPREG(HDMI_TG_VSYNC_L);
 739         DUMPREG(HDMI_TG_VSYNC_H);
 740         DUMPREG(HDMI_TG_VSYNC2_L);
 741         DUMPREG(HDMI_TG_VSYNC2_H);
 742         DUMPREG(HDMI_TG_VACT_ST_L);
 743         DUMPREG(HDMI_TG_VACT_ST_H);
 744         DUMPREG(HDMI_TG_VACT_SZ_L);
 745         DUMPREG(HDMI_TG_VACT_SZ_H);
 746         DUMPREG(HDMI_TG_FIELD_CHG_L);
 747         DUMPREG(HDMI_TG_FIELD_CHG_H);
 748         DUMPREG(HDMI_TG_VACT_ST2_L);
 749         DUMPREG(HDMI_TG_VACT_ST2_H);
 750         DUMPREG(HDMI_TG_VACT_ST3_L);
 751         DUMPREG(HDMI_TG_VACT_ST3_H);
 752         DUMPREG(HDMI_TG_VACT_ST4_L);
 753         DUMPREG(HDMI_TG_VACT_ST4_H);
 754         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 755         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 756         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 757         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 758         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 759         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 760         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 761         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 762         DUMPREG(HDMI_TG_3D);
 763
 764         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 765         DUMPREG(HDMI_AVI_CON);
 766         DUMPREG(HDMI_AVI_HEADER0);
 767         DUMPREG(HDMI_AVI_HEADER1);
 768         DUMPREG(HDMI_AVI_HEADER2);
 769         DUMPREG(HDMI_AVI_CHECK_SUM);
 770         DUMPREG(HDMI_VSI_CON);
 771         DUMPREG(HDMI_VSI_HEADER0);
 772         DUMPREG(HDMI_VSI_HEADER1);
 773         DUMPREG(HDMI_VSI_HEADER2);
 774         for (i = 0; i < 7; ++i)
 775                 DUMPREG(HDMI_VSI_DATA(i));
 776
 777 #undef DUMPREG
 778 }
 779
 780 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 781 {
 782         if (hdata->is_v13)
 783                 hdmi_v13_regs_dump(hdata, prefix);
 784         else
 785                 hdmi_v14_regs_dump(hdata, prefix);
 786 }
 787
 788 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 789 {
 790         int i;
 791
 792         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 793                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 794                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 795                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 796                                 hdmi_v13_confs[i].interlace ==
 797                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 798                                  true : false))
 799                         return i;
 800
 801         return -EINVAL;
 802 }
 803
 804 static bool hdmi_is_connected(void *ctx)
 805 {
 806         struct hdmi_context *hdata = ctx;
 807         if (hdata->is_hdmi_powered_on) {
 808                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 809                         DRM_DEBUG_KMS("hdmi is not connected\n");
 810                         return false;
 811                 }
 812         } else if (!hdmi_get_hpd(hdata)) {
 813                         DRM_DEBUG_KMS("hdmi is not connected\n");
 814                         return false;
 815         }
 816
 817         return true;
 818 }
 819
 820 static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
 821                                 u8 *edid, int len)
 822 {
 823         struct edid *raw_edid;
 824         struct hdmi_context *hdata = ctx;
 825
 826         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 827
 828         if (!hdata->ddc_port)
 829                 return -ENODEV;
 830
 831         raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 832         if (raw_edid) {
 833         /* TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 834          * to get the edid and then call drm_detect_hdmi_monitor.
 835          */
 836                 hdata->has_hdmi_sink = drm_detect_hdmi_monitor(raw_edid);
 837                 hdata->has_hdmi_audio = drm_detect_monitor_audio(raw_edid);
 838                 memcpy(edid, raw_edid, min((1 + raw_edid->extensions)
 839                                         * EDID_LENGTH, len));
 840                 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 841                         (hdata->has_hdmi_sink ? "hdmi monitor" : "dvi monitor"),
 842                         raw_edid->width_cm, raw_edid->height_cm);
 843         } else {
 844                 return -ENODEV;
 845         }
 846
 847         return 0;
 848 }
 849
 850 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 851 {
 852         int i;
 853
 854         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 855                         check_timing->xres, check_timing->yres,
 856                         check_timing->refresh, (check_timing->vmode &
 857                         FB_VMODE_INTERLACED) ? true : false);
 858
 859         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 860                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 861                         hdmi_v13_confs[i].height == check_timing->yres &&
 862                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 863                         hdmi_v13_confs[i].interlace ==
 864                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 865                          true : false))
 866                                 return 0;
 867
 868         /* TODO */
 869
 870         return -EINVAL;
 871 }
 872
 873 static int find_hdmiphy_conf(int pixel_clock)
 874 {
 875         int i;
 876
 877         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 878                 if (phy_configs[i].pixel_clock == pixel_clock)
 879                         return i;
 880         }
 881         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 882         return -EINVAL;
 883 }
 884
 885 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 886 {
 887         int ret;
 888         enum exynos_mixer_mode_type mode_type;
 889
 890         /*
 891          * No support for interlaced since there's no clear way to convert the
 892          * timing values in drm_display_mode to exynos register values.
 893          */
 894         if (mode->vmode == FB_VMODE_INTERLACED)
 895                 return -EINVAL;
 896
 897         /* Make sure the mixer can generate this mode */
 898         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 899         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 900                 return -EINVAL;
 901
 902         ret = find_hdmiphy_conf(mode->pixclock);
 903         return ret < 0 ? ret : 0;
 904 }
 905
 906 static u8 hdmi_chksum(struct hdmi_context *hdata,
 907                         u32 start, u8 len, u32 hdr_sum)
 908 {
 909         int i;
 910         /* hdr_sum : header0 + header1 + header2
 911         * start : start address of packet byte1
 912         * len : packet bytes - 1 */
 913         for (i = 0; i < len; ++i)
 914                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 915
 916         return (u8)(0x100 - (hdr_sum & 0xff));
 917 }
 918
 919 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 920                         struct hdmi_infoframe *infoframe)
 921 {
 922         u32 hdr_sum;
 923         u8 chksum;
 924         u32 aspect_ratio;
 925         u32 mod;
 926
 927         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 928         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 929         if (!hdata->has_hdmi_sink) {
 930                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 931                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 932                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 933                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 934                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 935                 return;
 936         }
 937
 938         switch (infoframe->type) {
 939
 940         case HDMI_PACKET_TYPE_AVI:
 941                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
 942                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
 943                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
 944                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
 945                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
 946                 /* Output format zero hardcoded ,RGB YBCR selection */
 947                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
 948                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
 949
 950                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
 951
 952                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
 953                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
 954                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
 955
 956                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
 957                                         infoframe->len, hdr_sum);
 958                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
 959                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
 960                 break;
 961
 962         case HDMI_PACKET_TYPE_AUI:
 963                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
 964                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
 965                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
 966                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
 967                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
 968                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
 969                                         infoframe->len, hdr_sum);
 970                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
 971                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
 972                 break;
 973
 974         default:
 975                 break;
 976         }
 977 }
 978
 979 static int hdmi_check_timing(void *ctx, void *timing)
 980 {
 981         struct hdmi_context *hdata = ctx;
 982         struct fb_videomode *check_timing = timing;
 983
 984         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 985
 986         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
 987                         check_timing->yres, check_timing->refresh,
 988                         check_timing->vmode);
 989
 990         if (hdata->is_v13)
 991                 return hdmi_v13_check_timing(check_timing);
 992         else
 993                 return hdmi_v14_check_timing(check_timing);
 994 }
 995
 996 static void hdmi_set_acr(u32 freq, u8 *acr)
 997 {
 998         u32 n, cts;
 999
1000         switch (freq) {
1001         case 32000:
1002                 n = 4096;
1003                 cts = 27000;
1004                 break;
1005         case 44100:
1006                 n = 6272;
1007                 cts = 30000;
1008                 break;
1009         case 88200:
1010                 n = 12544;
1011                 cts = 30000;
1012                 break;
1013         case 176400:
1014                 n = 25088;
1015                 cts = 30000;
1016                 break;
1017         case 48000:
1018                 n = 6144;
1019                 cts = 27000;
1020                 break;
1021         case 96000:
1022                 n = 12288;
1023                 cts = 27000;
1024                 break;
1025         case 192000:
1026                 n = 24576;
1027                 cts = 27000;
1028                 break;
1029         default:
1030                 n = 0;
1031                 cts = 0;
1032                 break;
1033         }
1034
1035         acr[1] = cts >> 16;
1036         acr[2] = cts >> 8 & 0xff;
1037         acr[3] = cts & 0xff;
1038
1039         acr[4] = n >> 16;
1040         acr[5] = n >> 8 & 0xff;
1041         acr[6] = n & 0xff;
1042 }
1043
1044 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1045 {
1046         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1047         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1048         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1049         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1050         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1051         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1052         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1053         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1054         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1055
1056         if (hdata->is_v13)
1057                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1058         else
1059                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1060 }
1061
1062 static void hdmi_audio_init(struct hdmi_context *hdata)
1063 {
1064         u32 sample_rate, bits_per_sample, frame_size_code;
1065         u32 data_num, bit_ch, sample_frq;
1066         u32 val;
1067         u8 acr[7];
1068
1069         sample_rate = 44100;
1070         bits_per_sample = 16;
1071         frame_size_code = 0;
1072
1073         switch (bits_per_sample) {
1074         case 20:
1075                 data_num = 2;
1076                 bit_ch  = 1;
1077                 break;
1078         case 24:
1079                 data_num = 3;
1080                 bit_ch  = 1;
1081                 break;
1082         default:
1083                 data_num = 1;
1084                 bit_ch  = 0;
1085                 break;
1086         }
1087
1088         hdmi_set_acr(sample_rate, acr);
1089         hdmi_reg_acr(hdata, acr);
1090
1091         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1092                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1093                                 | HDMI_I2S_MUX_ENABLE);
1094
1095         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1096                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1097
1098         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1099
1100         sample_frq = (sample_rate == 44100) ? 0 :
1101                         (sample_rate == 48000) ? 2 :
1102                         (sample_rate == 32000) ? 3 :
1103                         (sample_rate == 96000) ? 0xa : 0x0;
1104
1105         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1106         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1107
1108         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1109         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1110
1111         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1112         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1113                         | HDMI_I2S_SEL_LRCK(6));
1114         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1115                         | HDMI_I2S_SEL_SDATA2(4));
1116         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1117                         | HDMI_I2S_SEL_SDATA2(2));
1118         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1119
1120         /* I2S_CON_1 & 2 */
1121         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1122                         | HDMI_I2S_L_CH_LOW_POL);
1123         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1124                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1125                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1126                         | HDMI_I2S_BASIC_FORMAT);
1127
1128         /* Configure register related to CUV information */
1129         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1130                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1131                         | HDMI_I2S_COPYRIGHT
1132                         | HDMI_I2S_LINEAR_PCM
1133                         | HDMI_I2S_CONSUMER_FORMAT);
1134         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1135         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1136         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1137                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1138         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1139                         HDMI_I2S_ORG_SMP_FREQ_44_1
1140                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1141                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1142
1143         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1144 }
1145
1146 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1147 {
1148         if (!hdata->has_hdmi_audio)
1149                 return;
1150
1151         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1152         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1153                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1154 }
1155
1156 static void hdmi_conf_reset(struct hdmi_context *hdata)
1157 {
1158         u32 reg;
1159
1160         /* disable hpd handle for drm */
1161         hdata->hpd_handle = false;
1162
1163         if (hdata->is_v13)
1164                 reg = HDMI_V13_CORE_RSTOUT;
1165         else
1166                 reg = HDMI_CORE_RSTOUT;
1167
1168         /* resetting HDMI core */
1169         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1170         mdelay(10);
1171         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1172         mdelay(10);
1173
1174         /* enable hpd handle for drm */
1175         hdata->hpd_handle = true;
1176 }
1177
1178 static void hdmi_conf_init(struct hdmi_context *hdata)
1179 {
1180         struct hdmi_infoframe infoframe;
1181         /* disable hpd handle for drm */
1182         hdata->hpd_handle = false;
1183
1184         /* enable HPD interrupts */
1185         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1186                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1187         mdelay(10);
1188         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1189                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1190
1191         /* choose HDMI mode */
1192         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1193                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1194         /* disable bluescreen */
1195         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1196
1197         if (!hdata->has_hdmi_sink) {
1198                 /* choose DVI mode */
1199                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1200                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1201                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1202                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1203         }
1204
1205         if (hdata->is_v13) {
1206                 /* choose bluescreen (fecal) color */
1207                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1208                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1209                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1210
1211                 /* enable AVI packet every vsync, fixes purple line problem */
1212                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1213                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1214                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1215                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1216
1217                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1218                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1219                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1220         } else {
1221                 /* enable AVI packet every vsync, fixes purple line problem */
1222                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1223
1224                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1225                 infoframe.ver = HDMI_AVI_VERSION;
1226                 infoframe.len = HDMI_AVI_LENGTH;
1227                 hdmi_reg_infoframe(hdata, &infoframe);
1228
1229                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1230                 infoframe.ver = HDMI_AUI_VERSION;
1231                 infoframe.len = HDMI_AUI_LENGTH;
1232                 hdmi_reg_infoframe(hdata, &infoframe);
1233
1234         }
1235
1236         /* enable hpd handle for drm */
1237         hdata->hpd_handle = true;
1238 }
1239
1240 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1241 {
1242         const struct hdmi_v13_preset_conf *conf =
1243                 hdmi_v13_confs[hdata->cur_conf].conf;
1244         const struct hdmi_v13_core_regs *core = &conf->core;
1245         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1246         int tries;
1247
1248         /* setting core registers */
1249         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1250         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1251         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1252         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1253         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1254         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1255         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1256         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1257         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1258         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1259         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1260         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1261         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1262         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1263         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1264         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1265         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1266         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1267         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1268         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1269         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1270         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1271         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1272         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1273         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1274         /* Timing generator registers */
1275         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1276         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1277         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1278         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1279         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1280         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1281         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1282         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1283         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1284         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1285         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1286         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1287         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1288         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1289         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1290         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1291         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1292         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1293         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1294         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1295         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1296         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1297         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1298         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1299         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1300         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1301         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1302         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1303
1304         /* waiting for HDMIPHY's PLL to get to steady state */
1305         for (tries = 100; tries; --tries) {
1306                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1307                 if (val & HDMI_PHY_STATUS_READY)
1308                         break;
1309                 mdelay(1);
1310         }
1311         /* steady state not achieved */
1312         if (tries == 0) {
1313                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1314                 hdmi_regs_dump(hdata, "timing apply");
1315         }
1316
1317         clk_disable(hdata->res.sclk_hdmi);
1318         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1319         clk_enable(hdata->res.sclk_hdmi);
1320
1321         /* enable HDMI and timing generator */
1322         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1323         if (core->int_pro_mode[0])
1324                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1325                                 HDMI_FIELD_EN);
1326         else
1327                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1328 }
1329
1330 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1331 {
1332         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1333         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1334         int tries;
1335
1336         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1337         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1338         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1339         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1340         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1341         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1342         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1343         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1344         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1345         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1346         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1347         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1348         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1349         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1350         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1351         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1352         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1353         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1354         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1355         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1356         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1357         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1358                         core->v_sync_line_bef_2[0]);
1359         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1360                         core->v_sync_line_bef_2[1]);
1361         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1362                         core->v_sync_line_bef_1[0]);
1363         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1364                         core->v_sync_line_bef_1[1]);
1365         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1366                         core->v_sync_line_aft_2[0]);
1367         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1368                         core->v_sync_line_aft_2[1]);
1369         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1370                         core->v_sync_line_aft_1[0]);
1371         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1372                         core->v_sync_line_aft_1[1]);
1373         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1374                         core->v_sync_line_aft_pxl_2[0]);
1375         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1376                         core->v_sync_line_aft_pxl_2[1]);
1377         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1378                         core->v_sync_line_aft_pxl_1[0]);
1379         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1380                         core->v_sync_line_aft_pxl_1[1]);
1381         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1382         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1383         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1384         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1385         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1386         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1387         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1388         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1389         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1390                         core->v_sync_line_aft_3[0]);
1391         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1392                         core->v_sync_line_aft_3[1]);
1393         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1394                         core->v_sync_line_aft_4[0]);
1395         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1396                         core->v_sync_line_aft_4[1]);
1397         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1398                         core->v_sync_line_aft_5[0]);
1399         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1400                         core->v_sync_line_aft_5[1]);
1401         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1402                         core->v_sync_line_aft_6[0]);
1403         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1404                         core->v_sync_line_aft_6[1]);
1405         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1406                         core->v_sync_line_aft_pxl_3[0]);
1407         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1408                         core->v_sync_line_aft_pxl_3[1]);
1409         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1410                         core->v_sync_line_aft_pxl_4[0]);
1411         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1412                         core->v_sync_line_aft_pxl_4[1]);
1413         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1414                         core->v_sync_line_aft_pxl_5[0]);
1415         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1416                         core->v_sync_line_aft_pxl_5[1]);
1417         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1418                         core->v_sync_line_aft_pxl_6[0]);
1419         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1420                         core->v_sync_line_aft_pxl_6[1]);
1421         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1422         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1423         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1424         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1425         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1426         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1427         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1428         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1429         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1430         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1431         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1432         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1433
1434         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1435         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1436         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1437         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1438         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1439         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1440         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1441         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1442         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1443         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1444         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1445         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1446         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1447         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1448         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1449         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1450         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1451         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1452         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1453         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1454         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1455         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1456         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1457         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1458         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1459         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1460         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1461         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1462         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1463         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1464         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1465         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1466         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1467
1468         /* waiting for HDMIPHY's PLL to get to steady state */
1469         for (tries = 100; tries; --tries) {
1470                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1471                 if (val & HDMI_PHY_STATUS_READY)
1472                         break;
1473                 mdelay(1);
1474         }
1475         /* steady state not achieved */
1476         if (tries == 0) {
1477                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1478                 hdmi_regs_dump(hdata, "timing apply");
1479         }
1480
1481         clk_disable(hdata->res.sclk_hdmi);
1482         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1483         clk_enable(hdata->res.sclk_hdmi);
1484
1485         /* enable HDMI and timing generator */
1486         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1487         if (core->int_pro_mode[0])
1488                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1489                                 HDMI_FIELD_EN);
1490         else
1491                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1492 }
1493
1494 static void hdmi_timing_apply(struct hdmi_context *hdata)
1495 {
1496         if (hdata->is_v13)
1497                 hdmi_v13_timing_apply(hdata);
1498         else
1499                 hdmi_v14_timing_apply(hdata);
1500 }
1501
1502 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1503 {
1504         u8 buffer[2];
1505         u32 reg;
1506
1507         clk_disable(hdata->res.sclk_hdmi);
1508         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1509         clk_enable(hdata->res.sclk_hdmi);
1510
1511         /* operation mode */
1512         buffer[0] = 0x1f;
1513         buffer[1] = 0x00;
1514
1515         if (hdata->hdmiphy_port)
1516                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1517
1518         if (hdata->is_v13)
1519                 reg = HDMI_V13_PHY_RSTOUT;
1520         else
1521                 reg = HDMI_PHY_RSTOUT;
1522
1523         /* reset hdmiphy */
1524         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1525         mdelay(10);
1526         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1527         mdelay(10);
1528 }
1529
1530 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1531 {
1532         const u8 *hdmiphy_data;
1533         u8 buffer[32];
1534         u8 operation[2];
1535         u8 read_buffer[32] = {0, };
1536         int ret;
1537         int i;
1538
1539         if (!hdata->hdmiphy_port) {
1540                 DRM_ERROR("hdmiphy is not attached\n");
1541                 return;
1542         }
1543
1544         /* pixel clock */
1545         if (hdata->is_v13) {
1546                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1547         } else {
1548                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1549                 hdmiphy_data = phy_configs[i].conf;
1550         }
1551
1552         memcpy(buffer, hdmiphy_data, 32);
1553         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1554         if (ret != 32) {
1555                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1556                 return;
1557         }
1558
1559         mdelay(10);
1560
1561         /* operation mode */
1562         operation[0] = 0x1f;
1563         operation[1] = 0x80;
1564
1565         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1566         if (ret != 2) {
1567                 DRM_ERROR("failed to enable hdmiphy\n");
1568                 return;
1569         }
1570
1571         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1572         if (ret < 0) {
1573                 DRM_ERROR("failed to read hdmiphy config\n");
1574                 return;
1575         }
1576
1577         for (i = 0; i < ret; i++)
1578                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1579                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1580 }
1581
1582 static void hdmi_conf_apply(struct hdmi_context *hdata)
1583 {
1584         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1585
1586         hdmiphy_conf_reset(hdata);
1587         hdmiphy_conf_apply(hdata);
1588
1589         hdmi_conf_reset(hdata);
1590         hdmi_conf_init(hdata);
1591         if (!hdata->is_soc_exynos5)
1592                 hdmi_audio_init(hdata);
1593
1594         /* setting core registers */
1595         hdmi_timing_apply(hdata);
1596         if (!hdata->is_soc_exynos5)
1597                 hdmi_audio_control(hdata, true);
1598
1599         hdmi_regs_dump(hdata, "start");
1600 }
1601
1602 static void hdmi_mode_copy(struct drm_display_mode *dst,
1603         struct drm_display_mode *src)
1604 {
1605         struct drm_mode_object base;
1606
1607         /* following information should be preserved,
1608          * required for releasing the drm_display_mode node,
1609          * duplicated to recieve adjustment info. */
1610
1611         base.id = dst->base.id;
1612         base.type = dst->base.type;
1613
1614         memcpy(dst, src, sizeof(struct drm_display_mode));
1615
1616         dst->base.id = base.id;
1617         dst->base.type = base.type;
1618 }
1619
1620 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1621                                 struct drm_display_mode *mode,
1622                                 struct drm_display_mode *adjusted_mode)
1623 {
1624         struct drm_display_mode *m;
1625         struct hdmi_context *hdata = ctx;
1626         int index;
1627
1628         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1629
1630         drm_mode_set_crtcinfo(adjusted_mode, 0);
1631
1632         if (hdata->is_v13)
1633                 index = hdmi_v13_conf_index(adjusted_mode);
1634         else
1635                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1636
1637         /* just return if user desired mode exists. */
1638         if (index >= 0)
1639                 return;
1640
1641         /*
1642          * otherwise, find the most suitable mode among modes and change it
1643          * to adjusted_mode.
1644          */
1645         list_for_each_entry(m, &connector->modes, head) {
1646                 if (hdata->is_v13)
1647                         index = hdmi_v13_conf_index(m);
1648                 else
1649                         index = find_hdmiphy_conf(m->clock * 1000);
1650
1651                 if (index >= 0) {
1652                         DRM_INFO("desired mode doesn't exist so\n");
1653                         DRM_INFO("use the most suitable mode among modes.\n");
1654                         hdmi_mode_copy(adjusted_mode, m);
1655                         break;
1656                 }
1657         }
1658 }
1659
1660 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1661 {
1662         int i;
1663         BUG_ON(num_bytes > 4);
1664         for (i = 0; i < num_bytes; i++)
1665                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1666 }
1667
1668 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1669                         struct drm_display_mode *m)
1670 {
1671         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1672         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1673
1674         hdata->mode_conf.vic = drm_match_cea_mode(m);
1675
1676         hdata->mode_conf.pixel_clock = m->clock * 1000;
1677         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1678         hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1679         hdmi_set_reg(core->v_line, 2, m->vtotal);
1680         hdmi_set_reg(core->h_line, 2, m->htotal);
1681         hdmi_set_reg(core->hsync_pol, 1,
1682                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1683         hdmi_set_reg(core->vsync_pol, 1,
1684                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1685         hdmi_set_reg(core->int_pro_mode, 1,
1686                         (m->flags >> DRM_MODE_FLAG_INTERLACE) & 0x01);
1687         /* Quirk requirement for exynos 5 HDMI IP design,
1688          * 2 pixels less than the actual calculation for hsync_start
1689          * and end.
1690          */
1691         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1692         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1693         hdmi_set_reg(core->v_sync_line_bef_2, 2, m->vsync_end - m->vdisplay);
1694         hdmi_set_reg(core->v_sync_line_bef_1, 2, m->vsync_start - m->vdisplay);
1695         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1696         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1697         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1698         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1699         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1700         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1701
1702         /*
1703          * The following values can be different when using interlaced mode.
1704          * Unfortunately the datasheet doesn't describe them. This is why we
1705          * reject interlaced modes. Once this is fixed, we can remove that
1706          * restriction.
1707          */
1708         hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1709         hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1710         hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1711         hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1712         hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1713         hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1714         hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1715         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1716         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1717         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1718         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1719         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1720         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1721         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1722         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1723         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1724         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1725         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1726         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1727
1728         /* Timing generator registers */
1729         hdmi_set_reg(tg->cmd, 1, 0x0);
1730         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1731         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1732         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1733         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1734         hdmi_set_reg(tg->vsync, 2, 0x1);
1735         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1736         hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1737         hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1738         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1739         hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1740         hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1741         hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1742         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1743         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1744         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1745         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1746         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1747 }
1748
1749 static void hdmi_mode_set(void *ctx, void *mode)
1750 {
1751         struct hdmi_context *hdata = ctx;
1752
1753         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1754
1755         if (hdata->is_v13)
1756                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1757         else
1758                 hdmi_v14_mode_set(hdata, mode);
1759 }
1760
1761 static void hdmi_commit(void *ctx)
1762 {
1763         struct hdmi_context *hdata = ctx;
1764
1765         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1766         if (!hdata->is_hdmi_powered_on)
1767                 return;
1768
1769         hdmi_conf_apply(hdata);
1770         hdata->enabled = true;
1771 }
1772
1773 static int hdmi_power_on(void *ctx, int mode)
1774 {
1775         struct hdmi_context *hdata = ctx;
1776
1777         switch (mode) {
1778         case DRM_MODE_DPMS_ON:
1779                 if (!hdata->is_hdmi_powered_on) {
1780                         pm_runtime_get_sync(hdata->dev);
1781                         hdmi_commit(ctx);
1782                 }
1783                 break;
1784         case DRM_MODE_DPMS_STANDBY:
1785                 break;
1786         case DRM_MODE_DPMS_SUSPEND:
1787                 break;
1788         case DRM_MODE_DPMS_OFF:
1789                 if (hdata->is_hdmi_powered_on)
1790                         pm_runtime_put_sync(hdata->dev);
1791                 break;
1792         default:
1793                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1794                 break;
1795         }
1796
1797         return 0;
1798 }
1799
1800 static struct exynos_hdmi_ops hdmi_ops = {
1801         /* display */
1802         .is_connected   = hdmi_is_connected,
1803         .get_edid       = hdmi_get_edid,
1804         .check_timing   = hdmi_check_timing,
1805         .power_on       = hdmi_power_on,
1806
1807         /* manager */
1808         .mode_fixup     = hdmi_mode_fixup,
1809         .mode_set       = hdmi_mode_set,
1810         .commit         = hdmi_commit,
1811 };
1812
1813 /*
1814  * Handle hotplug events outside the interrupt handler proper.
1815  */
1816 static void hdmi_hotplug_func(struct work_struct *work)
1817 {
1818         struct hdmi_context *hdata =
1819                 container_of(work, struct hdmi_context, hotplug_work);
1820         struct exynos_drm_hdmi_context *ctx =
1821                 (struct exynos_drm_hdmi_context *)hdata->parent_ctx;
1822
1823         drm_helper_hpd_irq_event(ctx->drm_dev);
1824 }
1825
1826 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
1827 {
1828         struct exynos_drm_hdmi_context *ctx = arg;
1829         struct hdmi_context *hdata = ctx->ctx;
1830         u32 intc_flag;
1831         if (hdata->is_hdmi_powered_on) {
1832                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
1833                 /* clearing flags for HPD plug/unplug */
1834                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
1835                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
1836                                 hdata->hpd_handle);
1837                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1838                                 HDMI_INTC_FLAG_HPD_UNPLUG);
1839                 }
1840                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
1841                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
1842                                 hdata->hpd_handle);
1843                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
1844                                 HDMI_INTC_FLAG_HPD_PLUG);
1845                 }
1846         }
1847
1848         if (ctx->drm_dev && hdata->hpd_handle)
1849                 queue_work(hdata->wq, &hdata->hotplug_work);
1850
1851         return IRQ_HANDLED;
1852 }
1853
1854 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
1855 {
1856         struct device *dev = hdata->dev;
1857         struct hdmi_resources *res = &hdata->res;
1858 #ifndef CONFIG_ARCH_EXYNOS5
1859         static char *supply[] = {
1860                 "hdmi-en",
1861                 "vdd",
1862                 "vdd_osc",
1863                 "vdd_pll",
1864         };
1865         int i, ret;
1866 #endif
1867
1868         DRM_DEBUG_KMS("HDMI resource init\n");
1869
1870         memset(res, 0, sizeof *res);
1871
1872         /* get clocks, power */
1873         res->hdmi = clk_get(dev, "hdmi");
1874         if (IS_ERR_OR_NULL(res->hdmi)) {
1875                 DRM_ERROR("failed to get clock 'hdmi'\n");
1876                 goto fail;
1877         }
1878         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
1879         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
1880                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1881                 goto fail;
1882         }
1883         res->sclk_pixel = clk_get(dev, "sclk_pixel");
1884         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
1885                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1886                 goto fail;
1887         }
1888         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
1889         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
1890                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1891                 goto fail;
1892         }
1893         res->hdmiphy = clk_get(dev, "hdmiphy");
1894         if (IS_ERR_OR_NULL(res->hdmiphy)) {
1895                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1896                 goto fail;
1897         }
1898
1899         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
1900
1901 #ifndef CONFIG_ARCH_EXYNOS5
1902         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
1903                 sizeof res->regul_bulk[0], GFP_KERNEL);
1904         if (!res->regul_bulk) {
1905                 DRM_ERROR("failed to get memory for regulators\n");
1906                 goto fail;
1907         }
1908         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1909                 res->regul_bulk[i].supply = supply[i];
1910                 res->regul_bulk[i].consumer = NULL;
1911         }
1912         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
1913         if (ret) {
1914                 DRM_ERROR("failed to get regulators\n");
1915                 goto fail;
1916         }
1917         res->regul_count = ARRAY_SIZE(supply);
1918 #endif
1919         /* TODO:
1920          * These clocks also should be added in
1921          * runtime resume and runtime suspend
1922          */
1923         clk_enable(res->hdmi);
1924         clk_enable(res->sclk_hdmi);
1925
1926         return 0;
1927 fail:
1928         DRM_ERROR("HDMI resource init - failed\n");
1929         return -ENODEV;
1930 }
1931
1932 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
1933 {
1934         struct hdmi_resources *res = &hdata->res;
1935
1936         regulator_bulk_free(res->regul_count, res->regul_bulk);
1937         /* kfree is NULL-safe */
1938         kfree(res->regul_bulk);
1939         if (!IS_ERR_OR_NULL(res->hdmiphy))
1940                 clk_put(res->hdmiphy);
1941         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
1942                 clk_put(res->sclk_hdmiphy);
1943         if (!IS_ERR_OR_NULL(res->sclk_pixel))
1944                 clk_put(res->sclk_pixel);
1945         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
1946                 clk_put(res->sclk_hdmi);
1947         if (!IS_ERR_OR_NULL(res->hdmi))
1948                 clk_put(res->hdmi);
1949         memset(res, 0, sizeof *res);
1950
1951         return 0;
1952 }
1953
1954 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1955 {
1956         struct hdmi_resources *res = &hdata->res;
1957
1958         hdata->is_hdmi_powered_on = true;
1959         hdmi_cfg_hpd(hdata, false);
1960
1961         /* irq change by TV power status */
1962         if (hdata->curr_irq == hdata->internal_irq)
1963                 return;
1964
1965         disable_irq(hdata->curr_irq);
1966
1967         hdata->curr_irq = hdata->internal_irq;
1968
1969         enable_irq(hdata->curr_irq);
1970
1971         /* turn HDMI power on */
1972         regulator_bulk_enable(res->regul_count, res->regul_bulk);
1973
1974         /* power-on hdmi clocks */
1975         clk_enable(res->hdmiphy);
1976
1977         hdmiphy_conf_reset(hdata);
1978         hdmi_conf_reset(hdata);
1979         hdmi_conf_init(hdata);
1980         if (!hdata->is_soc_exynos5)
1981                 hdmi_audio_init(hdata);
1982 }
1983
1984 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
1985 {
1986         struct hdmi_resources *res = &hdata->res;
1987
1988         hdmi_cfg_hpd(hdata, true);
1989
1990         if (hdata->curr_irq == hdata->external_irq)
1991                 return;
1992
1993         disable_irq(hdata->curr_irq);
1994         hdata->curr_irq = hdata->external_irq;
1995
1996         enable_irq(hdata->curr_irq);
1997         hdata->is_hdmi_powered_on = false;
1998
1999         hdmiphy_conf_reset(hdata);
2000
2001         /* power-off hdmi clocks */
2002         clk_disable(res->hdmiphy);
2003
2004         /* turn HDMI power off */
2005         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2006 }
2007
2008 #ifdef CONFIG_PM_SLEEP
2009 static int hdmi_suspend(struct device *dev)
2010 {
2011         struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2012         struct hdmi_context *hdata = ctx->ctx;
2013
2014         DRM_DEBUG_KMS("[hdmi] sleep suspend - start\n");
2015         if (pm_runtime_suspended(dev)) {
2016                 DRM_DEBUG_KMS("[hdmi] sleep suspend - already suspended\n");
2017                 return 0;
2018         }
2019
2020         hdmi_resource_poweroff(hdata);
2021         DRM_DEBUG_KMS("[hdmi] sleep suspend - end\n");
2022
2023         return 0;
2024 }
2025 static int hdmi_resume(struct device *dev)
2026 {
2027         struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2028         struct hdmi_context *hdata = ctx->ctx;
2029
2030         DRM_DEBUG_KMS("[hdmi] sleep resume - start\n");
2031
2032         if (!pm_runtime_suspended(dev)) {
2033                 hdmi_resource_poweron(hdata);
2034                 hdmi_commit(hdata);
2035                 DRM_DEBUG_KMS("[hdmi] sleep resuming\n");
2036         }
2037         DRM_DEBUG_KMS("[hdmi] sleep resume - end\n");
2038         return 0;
2039 }
2040 #endif
2041 #ifdef CONFIG_PM_RUNTIME
2042 static int hdmi_runtime_suspend(struct device *dev)
2043 {
2044         struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2045         struct hdmi_context *hdata = ctx->ctx;
2046
2047         DRM_DEBUG_KMS("[hdmi] runtime suspend - start\n");
2048         hdmi_resource_poweroff(hdata);
2049         DRM_DEBUG_KMS("[hdmi] runtime suspend - end\n");
2050
2051         return 0;
2052 }
2053
2054 static int hdmi_runtime_resume(struct device *dev)
2055 {
2056         struct exynos_drm_hdmi_context *ctx = get_hdmi_context(dev);
2057         struct hdmi_context *hdata = ctx->ctx;
2058
2059         DRM_DEBUG_KMS("[hdmi] runtime resume - start\n");
2060
2061         hdmi_resource_poweron(hdata);
2062
2063         DRM_DEBUG_KMS("[hdmi] runtime resume - end\n");
2064         return 0;
2065 }
2066 #endif
2067 static const struct dev_pm_ops hdmi_pm_ops = {
2068         SET_SYSTEM_SLEEP_PM_OPS(hdmi_suspend, hdmi_resume)
2069         SET_RUNTIME_PM_OPS(hdmi_runtime_suspend, hdmi_runtime_resume, NULL)
2070 };
2071
2072 static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
2073
2074 void hdmi_attach_ddc_client(struct i2c_client *ddc)
2075 {
2076         if (ddc)
2077                 hdmi_ddc = ddc;
2078 }
2079
2080 void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
2081 {
2082         if (hdmiphy)
2083                 hdmi_hdmiphy = hdmiphy;
2084 }
2085
2086 struct platform_device *hdmi_audio_device;
2087
2088 static int __devinit hdmi_probe(struct platform_device *pdev)
2089 {
2090         struct device *dev = &pdev->dev;
2091         struct exynos_drm_hdmi_context *drm_hdmi_ctx;
2092         struct hdmi_context *hdata;
2093         struct exynos_drm_hdmi_pdata *pdata;
2094         struct resource *res;
2095         int ret;
2096         enum of_gpio_flags flags;
2097
2098         DRM_DEBUG_KMS("[%d]\n", __LINE__);
2099
2100         pdata = pdev->dev.platform_data;
2101         if (!pdata) {
2102                 DRM_ERROR("no platform data specified\n");
2103                 return -EINVAL;
2104         }
2105
2106         drm_hdmi_ctx = kzalloc(sizeof(*drm_hdmi_ctx), GFP_KERNEL);
2107         if (!drm_hdmi_ctx) {
2108                 DRM_ERROR("failed to allocate common hdmi context.\n");
2109                 return -ENOMEM;
2110         }
2111
2112         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2113         if (!hdata) {
2114                 DRM_ERROR("out of memory\n");
2115                 kfree(drm_hdmi_ctx);
2116                 return -ENOMEM;
2117         }
2118
2119         drm_hdmi_ctx->ctx = (void *)hdata;
2120         hdata->parent_ctx = (void *)drm_hdmi_ctx;
2121
2122         platform_set_drvdata(pdev, drm_hdmi_ctx);
2123
2124         hdata->is_v13 = pdata->is_v13;
2125         hdata->default_win = pdata->default_win;
2126         hdata->default_timing = &pdata->timing;
2127         hdata->default_bpp = pdata->bpp;
2128         hdata->dev = dev;
2129         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2130                 "samsung,exynos5-hdmi");
2131
2132         ret = hdmi_resources_init(hdata);
2133         if (ret) {
2134                 ret = -EINVAL;
2135                 goto err_data;
2136         }
2137
2138         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2139         if (!res) {
2140                 DRM_ERROR("failed to find registers\n");
2141                 ret = -ENOENT;
2142                 goto err_resource;
2143         }
2144
2145         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2146                                            dev_name(dev));
2147         if (!hdata->regs_res) {
2148                 DRM_ERROR("failed to claim register region\n");
2149                 ret = -ENOENT;
2150                 goto err_resource;
2151         }
2152
2153         hdata->regs = ioremap(res->start, resource_size(res));
2154         if (!hdata->regs) {
2155                 DRM_ERROR("failed to map registers\n");
2156                 ret = -ENXIO;
2157                 goto err_req_region;
2158         }
2159
2160         if (of_device_is_compatible(dev->of_node,
2161                 "samsung,exynos5-hdmi")) {
2162
2163                 hdmi_audio_device =
2164                         platform_device_alloc("exynos-hdmi-audio", -1);
2165
2166                 if (!hdmi_audio_device) {
2167                         ret = -ENOMEM;
2168                         goto err_iomap;
2169                 }
2170
2171                 ret = platform_device_add_resources(hdmi_audio_device, res, 2);
2172                 if (ret) {
2173                         ret = -ENOMEM;
2174                         goto err_iomap;
2175                 }
2176
2177                 hdmi_audio_device->dev.of_node =
2178                         of_get_next_child(dev->of_node, NULL);
2179
2180                 ret = platform_device_add(hdmi_audio_device);
2181                 if (ret)
2182                         platform_device_put(hdmi_audio_device);
2183         }
2184
2185         /* DDC i2c driver */
2186         if (i2c_add_driver(&ddc_driver)) {
2187                 DRM_ERROR("failed to register ddc i2c driver\n");
2188                 ret = -ENOENT;
2189                 goto err_iomap;
2190         }
2191
2192         hdata->ddc_port = hdmi_ddc;
2193
2194         /* hdmiphy i2c driver */
2195         if (i2c_add_driver(&hdmiphy_driver)) {
2196                 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2197                 ret = -ENOENT;
2198                 goto err_ddc;
2199         }
2200
2201         hdata->hdmiphy_port = hdmi_hdmiphy;
2202
2203         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2204         if (res == NULL) {
2205                 DRM_ERROR("get interrupt resource failed.\n");
2206                 ret = -ENXIO;
2207                 goto err_hdmiphy;
2208         }
2209
2210         hdata->internal_irq = res->start;
2211
2212         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2213                                 "hpd-gpio", 0, &flags);
2214
2215         if (!gpio_is_valid(hdata->hpd_gpio)) {
2216                 DRM_ERROR("failed to get hpd gpio.");
2217                 ret = -EINVAL;
2218                 goto err_hdmiphy;
2219         }
2220
2221         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2222
2223         /* create workqueue and hotplug work */
2224         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2225                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2226         if (hdata->wq == NULL) {
2227                 DRM_ERROR("Failed to create workqueue.\n");
2228                 ret = -ENOMEM;
2229                 goto err_hdmiphy;
2230         }
2231         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2232
2233         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2234                         IRQF_SHARED, "int_hdmi", hdata->parent_ctx);
2235         if (ret) {
2236                 DRM_ERROR("request interrupt failed.\n");
2237                 goto err_workqueue;
2238         }
2239         disable_irq(hdata->internal_irq);
2240
2241         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2242                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2243                 hdata->parent_ctx);
2244         if (ret) {
2245                 DRM_ERROR("request interrupt failed.\n");
2246                 goto err_workqueue;
2247         }
2248         disable_irq(hdata->external_irq);
2249
2250         /* Attach HDMI Driver to common hdmi. */
2251         exynos_hdmi_drv_attach(drm_hdmi_ctx);
2252
2253         /* register specific callbacks to common hdmi. */
2254         exynos_hdmi_ops_register(&hdmi_ops);
2255         hdmi_resource_poweron(hdata);
2256         pm_runtime_enable(dev);
2257
2258         if (!hdmi_is_connected(hdata)) {
2259                 hdmi_resource_poweroff(hdata);
2260                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2261         } else {
2262                 pm_runtime_get_sync(dev);
2263         }
2264         return 0;
2265
2266 err_workqueue:
2267         destroy_workqueue(hdata->wq);
2268 err_hdmiphy:
2269         i2c_del_driver(&hdmiphy_driver);
2270 err_ddc:
2271         i2c_del_driver(&ddc_driver);
2272 err_iomap:
2273         iounmap(hdata->regs);
2274 err_req_region:
2275         release_mem_region(hdata->regs_res->start,
2276                         resource_size(hdata->regs_res));
2277 err_resource:
2278         hdmi_resources_cleanup(hdata);
2279 err_data:
2280         kfree(hdata);
2281         kfree(drm_hdmi_ctx);
2282         return ret;
2283 }
2284
2285 static int __devexit hdmi_remove(struct platform_device *pdev)
2286 {
2287         struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
2288         struct hdmi_context *hdata = ctx->ctx;
2289         struct hdmi_resources *res = &hdata->res;
2290
2291         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2292
2293         hdmi_resource_poweroff(hdata);
2294
2295         disable_irq(hdata->curr_irq);
2296         free_irq(hdata->internal_irq, hdata);
2297         free_irq(hdata->external_irq, hdata);
2298
2299         cancel_work_sync(&hdata->hotplug_work);
2300         destroy_workqueue(hdata->wq);
2301
2302         clk_disable(res->hdmi);
2303         clk_disable(res->sclk_hdmi);
2304         hdmi_resources_cleanup(hdata);
2305
2306         iounmap(hdata->regs);
2307
2308         release_mem_region(hdata->regs_res->start,
2309                         resource_size(hdata->regs_res));
2310
2311         /* hdmiphy i2c driver */
2312         i2c_del_driver(&hdmiphy_driver);
2313         /* DDC i2c driver */
2314         i2c_del_driver(&ddc_driver);
2315
2316         kfree(hdata);
2317
2318         return 0;
2319 }
2320
2321 struct platform_driver hdmi_driver = {
2322         .probe          = hdmi_probe,
2323         .remove         = __devexit_p(hdmi_remove),
2324         .driver         = {
2325 #ifdef CONFIG_ARCH_EXYNOS5
2326                 .name   = "exynos5-hdmi",
2327 #else
2328                 .name   = "exynos4-hdmi",
2329 #endif
2330                 .owner  = THIS_MODULE,
2331                 .pm = &hdmi_pm_ops,
2332         },
2333 };