drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/clk.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of_gpio.h>
  37 #include <plat/gpio-cfg.h>
  38
  39 #include <drm/exynos_drm.h>
  40
  41 #include "exynos_drm_drv.h"
  42 #include "exynos_drm_display.h"
  43
  44 #include "exynos_hdmi.h"
  45
  46 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  47
  48 struct hdmi_resources {
  49         struct clk                      *hdmi;
  50         struct clk                      *sclk_hdmi;
  51         struct clk                      *sclk_pixel;
  52         struct clk                      *sclk_hdmiphy;
  53         struct clk                      *hdmiphy;
  54         struct regulator_bulk_data      *regul_bulk;
  55         int                             regul_count;
  56 };
  57
  58 struct hdmi_tg_regs {
  59         u8 cmd[1];
  60         u8 h_fsz[2];
  61         u8 hact_st[2];
  62         u8 hact_sz[2];
  63         u8 v_fsz[2];
  64         u8 vsync[2];
  65         u8 vsync2[2];
  66         u8 vact_st[2];
  67         u8 vact_sz[2];
  68         u8 field_chg[2];
  69         u8 vact_st2[2];
  70         u8 vact_st3[2];
  71         u8 vact_st4[2];
  72         u8 vsync_top_hdmi[2];
  73         u8 vsync_bot_hdmi[2];
  74         u8 field_top_hdmi[2];
  75         u8 field_bot_hdmi[2];
  76         u8 tg_3d[1];
  77 };
  78
  79 struct hdmi_core_regs {
  80         u8 h_blank[2];
  81         u8 v2_blank[2];
  82         u8 v1_blank[2];
  83         u8 v_line[2];
  84         u8 h_line[2];
  85         u8 hsync_pol[1];
  86         u8 vsync_pol[1];
  87         u8 int_pro_mode[1];
  88         u8 v_blank_f0[2];
  89         u8 v_blank_f1[2];
  90         u8 h_sync_start[2];
  91         u8 h_sync_end[2];
  92         u8 v_sync_line_bef_2[2];
  93         u8 v_sync_line_bef_1[2];
  94         u8 v_sync_line_aft_2[2];
  95         u8 v_sync_line_aft_1[2];
  96         u8 v_sync_line_aft_pxl_2[2];
  97         u8 v_sync_line_aft_pxl_1[2];
  98         u8 v_blank_f2[2]; /* for 3D mode */
  99         u8 v_blank_f3[2]; /* for 3D mode */
 100         u8 v_blank_f4[2]; /* for 3D mode */
 101         u8 v_blank_f5[2]; /* for 3D mode */
 102         u8 v_sync_line_aft_3[2];
 103         u8 v_sync_line_aft_4[2];
 104         u8 v_sync_line_aft_5[2];
 105         u8 v_sync_line_aft_6[2];
 106         u8 v_sync_line_aft_pxl_3[2];
 107         u8 v_sync_line_aft_pxl_4[2];
 108         u8 v_sync_line_aft_pxl_5[2];
 109         u8 v_sync_line_aft_pxl_6[2];
 110         u8 vact_space_1[2];
 111         u8 vact_space_2[2];
 112         u8 vact_space_3[2];
 113         u8 vact_space_4[2];
 114         u8 vact_space_5[2];
 115         u8 vact_space_6[2];
 116 };
 117
 118 struct hdmi_mode_conf {
 119         int pixel_clock;
 120         struct hdmi_core_regs core;
 121         struct hdmi_tg_regs tg;
 122         u8 vic;
 123 };
 124
 125 struct hdmi_context {
 126         struct device                   *dev;
 127         struct drm_device               *drm_dev;
 128         struct fb_videomode             *default_timing;
 129         struct hdmi_mode_conf           mode_conf;
 130         unsigned int                    is_v13:1;
 131         unsigned int                    default_win;
 132         unsigned int                    default_bpp;
 133         bool                            hpd_handle;
 134         bool                            enabled;
 135         bool                            has_hdmi_sink;
 136         bool                            has_hdmi_audio;
 137         bool                            is_soc_exynos5;
 138         bool                            is_hdmi_powered_on;
 139         bool                            video_enabled;
 140
 141         struct resource                 *regs_res;
 142         void __iomem                    *regs;
 143         unsigned int                    external_irq;
 144         unsigned int                    internal_irq;
 145         unsigned int                    curr_irq;
 146         struct workqueue_struct         *wq;
 147         struct work_struct              hotplug_work;
 148
 149         struct i2c_client               *ddc_port;
 150         struct i2c_client               *hdmiphy_port;
 151         int                             hpd_gpio;
 152         /* current hdmiphy conf index */
 153         int cur_conf;
 154
 155         struct hdmi_resources           res;
 156 };
 157
 158 /* HDMI Version 1.3 */
 159 static const u8 hdmiphy_v13_conf27[32] = {
 160         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 161         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 162         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 163         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 164 };
 165
 166 static const u8 hdmiphy_v13_conf27_027[32] = {
 167         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 168         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 169         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 170         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 171 };
 172
 173 static const u8 hdmiphy_v13_conf74_175[32] = {
 174         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 175         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 176         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 177         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 178 };
 179
 180 static const u8 hdmiphy_v13_conf74_25[32] = {
 181         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 182         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 183         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 184         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 185 };
 186
 187 static const u8 hdmiphy_v13_conf148_5[32] = {
 188         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 189         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 190         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 191         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 192 };
 193
 194 struct hdmi_v13_tg_regs {
 195         u8 cmd;
 196         u8 h_fsz_l;
 197         u8 h_fsz_h;
 198         u8 hact_st_l;
 199         u8 hact_st_h;
 200         u8 hact_sz_l;
 201         u8 hact_sz_h;
 202         u8 v_fsz_l;
 203         u8 v_fsz_h;
 204         u8 vsync_l;
 205         u8 vsync_h;
 206         u8 vsync2_l;
 207         u8 vsync2_h;
 208         u8 vact_st_l;
 209         u8 vact_st_h;
 210         u8 vact_sz_l;
 211         u8 vact_sz_h;
 212         u8 field_chg_l;
 213         u8 field_chg_h;
 214         u8 vact_st2_l;
 215         u8 vact_st2_h;
 216         u8 vsync_top_hdmi_l;
 217         u8 vsync_top_hdmi_h;
 218         u8 vsync_bot_hdmi_l;
 219         u8 vsync_bot_hdmi_h;
 220         u8 field_top_hdmi_l;
 221         u8 field_top_hdmi_h;
 222         u8 field_bot_hdmi_l;
 223         u8 field_bot_hdmi_h;
 224 };
 225
 226 struct hdmi_v13_core_regs {
 227         u8 h_blank[2];
 228         u8 v_blank[3];
 229         u8 h_v_line[3];
 230         u8 vsync_pol[1];
 231         u8 int_pro_mode[1];
 232         u8 v_blank_f[3];
 233         u8 h_sync_gen[3];
 234         u8 v_sync_gen1[3];
 235         u8 v_sync_gen2[3];
 236         u8 v_sync_gen3[3];
 237 };
 238
 239 struct hdmi_v13_preset_conf {
 240         struct hdmi_v13_core_regs core;
 241         struct hdmi_v13_tg_regs tg;
 242 };
 243
 244 struct hdmi_v13_conf {
 245         int width;
 246         int height;
 247         int vrefresh;
 248         bool interlace;
 249         const u8 *hdmiphy_data;
 250         const struct hdmi_v13_preset_conf *conf;
 251 };
 252
 253 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 254         .core = {
 255                 .h_blank = {0x8a, 0x00},
 256                 .v_blank = {0x0d, 0x6a, 0x01},
 257                 .h_v_line = {0x0d, 0xa2, 0x35},
 258                 .vsync_pol = {0x01},
 259                 .int_pro_mode = {0x00},
 260                 .v_blank_f = {0x00, 0x00, 0x00},
 261                 .h_sync_gen = {0x0e, 0x30, 0x11},
 262                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 263                 /* other don't care */
 264         },
 265         .tg = {
 266                 0x00, /* cmd */
 267                 0x5a, 0x03, /* h_fsz */
 268                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 269                 0x0d, 0x02, /* v_fsz */
 270                 0x01, 0x00, 0x33, 0x02, /* vsync */
 271                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 272                 0x33, 0x02, /* field_chg */
 273                 0x49, 0x02, /* vact_st2 */
 274                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 275                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 276         },
 277 };
 278
 279 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 280         .core = {
 281                 .h_blank = {0x72, 0x01},
 282                 .v_blank = {0xee, 0xf2, 0x00},
 283                 .h_v_line = {0xee, 0x22, 0x67},
 284                 .vsync_pol = {0x00},
 285                 .int_pro_mode = {0x00},
 286                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 287                 .h_sync_gen = {0x6c, 0x50, 0x02},
 288                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 289                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 290                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 291                 /* other don't care */
 292         },
 293         .tg = {
 294                 0x00, /* cmd */
 295                 0x72, 0x06, /* h_fsz */
 296                 0x71, 0x01, 0x01, 0x05, /* hact */
 297                 0xee, 0x02, /* v_fsz */
 298                 0x01, 0x00, 0x33, 0x02, /* vsync */
 299                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 300                 0x33, 0x02, /* field_chg */
 301                 0x49, 0x02, /* vact_st2 */
 302                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 303                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 304         },
 305 };
 306
 307 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 308         .core = {
 309                 .h_blank = {0xd0, 0x02},
 310                 .v_blank = {0x32, 0xB2, 0x00},
 311                 .h_v_line = {0x65, 0x04, 0xa5},
 312                 .vsync_pol = {0x00},
 313                 .int_pro_mode = {0x01},
 314                 .v_blank_f = {0x49, 0x2A, 0x23},
 315                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 316                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 317                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 318                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 319                 /* other don't care */
 320         },
 321         .tg = {
 322                 0x00, /* cmd */
 323                 0x50, 0x0A, /* h_fsz */
 324                 0xCF, 0x02, 0x81, 0x07, /* hact */
 325                 0x65, 0x04, /* v_fsz */
 326                 0x01, 0x00, 0x33, 0x02, /* vsync */
 327                 0x16, 0x00, 0x1c, 0x02, /* vact */
 328                 0x33, 0x02, /* field_chg */
 329                 0x49, 0x02, /* vact_st2 */
 330                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 331                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 332         },
 333 };
 334
 335 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 336         .core = {
 337                 .h_blank = {0xd0, 0x02},
 338                 .v_blank = {0x65, 0x6c, 0x01},
 339                 .h_v_line = {0x65, 0x04, 0xa5},
 340                 .vsync_pol = {0x00},
 341                 .int_pro_mode = {0x00},
 342                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 343                 .h_sync_gen = {0x0e, 0xea, 0x08},
 344                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 345                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 346                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 347                 /* other don't care */
 348         },
 349         .tg = {
 350                 0x00, /* cmd */
 351                 0x50, 0x0A, /* h_fsz */
 352                 0xCF, 0x02, 0x81, 0x07, /* hact */
 353                 0x65, 0x04, /* v_fsz */
 354                 0x01, 0x00, 0x33, 0x02, /* vsync */
 355                 0x2d, 0x00, 0x38, 0x04, /* vact */
 356                 0x33, 0x02, /* field_chg */
 357                 0x48, 0x02, /* vact_st2 */
 358                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 359                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 360         },
 361 };
 362
 363 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 364         .core = {
 365                 .h_blank = {0x18, 0x01},
 366                 .v_blank = {0x32, 0xB2, 0x00},
 367                 .h_v_line = {0x65, 0x84, 0x89},
 368                 .vsync_pol = {0x00},
 369                 .int_pro_mode = {0x01},
 370                 .v_blank_f = {0x49, 0x2A, 0x23},
 371                 .h_sync_gen = {0x56, 0x08, 0x02},
 372                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 373                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 374                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 375                 /* other don't care */
 376         },
 377         .tg = {
 378                 0x00, /* cmd */
 379                 0x98, 0x08, /* h_fsz */
 380                 0x17, 0x01, 0x81, 0x07, /* hact */
 381                 0x65, 0x04, /* v_fsz */
 382                 0x01, 0x00, 0x33, 0x02, /* vsync */
 383                 0x16, 0x00, 0x1c, 0x02, /* vact */
 384                 0x33, 0x02, /* field_chg */
 385                 0x49, 0x02, /* vact_st2 */
 386                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 387                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 388         },
 389 };
 390
 391 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 392         .core = {
 393                 .h_blank = {0x18, 0x01},
 394                 .v_blank = {0x65, 0x6c, 0x01},
 395                 .h_v_line = {0x65, 0x84, 0x89},
 396                 .vsync_pol = {0x00},
 397                 .int_pro_mode = {0x00},
 398                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 399                 .h_sync_gen = {0x56, 0x08, 0x02},
 400                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 401                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 402                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 403                 /* other don't care */
 404         },
 405         .tg = {
 406                 0x00, /* cmd */
 407                 0x98, 0x08, /* h_fsz */
 408                 0x17, 0x01, 0x81, 0x07, /* hact */
 409                 0x65, 0x04, /* v_fsz */
 410                 0x01, 0x00, 0x33, 0x02, /* vsync */
 411                 0x2d, 0x00, 0x38, 0x04, /* vact */
 412                 0x33, 0x02, /* field_chg */
 413                 0x48, 0x02, /* vact_st2 */
 414                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 415                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 416         },
 417 };
 418
 419 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 420         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 421         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 422         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 423         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 424         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 425                                  &hdmi_v13_conf_1080p50 },
 426         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 427         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 428                                  &hdmi_v13_conf_1080p60 },
 429 };
 430
 431 struct hdmiphy_config {
 432         int pixel_clock;
 433         u8 conf[32];
 434 };
 435
 436 static const struct hdmiphy_config phy_configs[] = {
 437         {
 438                 .pixel_clock = 25200000,
 439                 .conf = {
 440                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 441                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 442                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 443                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 444                 },
 445         },
 446         {
 447                 .pixel_clock = 27000000,
 448                 .conf = {
 449                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 450                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 451                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 452                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 453                 },
 454         },
 455         {
 456                 .pixel_clock = 27027000,
 457                 .conf = {
 458                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 459                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 460                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 461                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 462                 },
 463         },
 464         {
 465                 .pixel_clock = 36000000,
 466                 .conf = {
 467                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 468                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 469                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 470                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 471                 },
 472         },
 473         {
 474                 .pixel_clock = 40000000,
 475                 .conf = {
 476                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 477                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 478                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 479                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 480                 },
 481         },
 482         {
 483                 .pixel_clock = 65000000,
 484                 .conf = {
 485                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 486                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 487                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 488                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 489                 },
 490         },
 491         {
 492                 .pixel_clock = 74176000,
 493                 .conf = {
 494                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 495                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 496                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 497                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 498                 },
 499         },
 500         {
 501                 .pixel_clock = 74250000,
 502                 .conf = {
 503                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 504                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 505                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 506                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 507                 },
 508         },
 509         {
 510                 .pixel_clock = 83500000,
 511                 .conf = {
 512                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 513                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 514                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 515                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 516                 },
 517         },
 518         {
 519                 .pixel_clock = 106500000,
 520                 .conf = {
 521                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 522                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 523                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 524                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 525                 },
 526         },
 527         {
 528                 .pixel_clock = 108000000,
 529                 .conf = {
 530                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 531                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 532                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 533                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 534                 },
 535         },
 536         {
 537                 .pixel_clock = 146250000,
 538                 .conf = {
 539                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 540                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 541                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 542                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 543                 },
 544         },
 545         {
 546                 .pixel_clock = 148500000,
 547                 .conf = {
 548                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 549                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 550                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 551                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 552                 },
 553         },
 554 };
 555
 556 struct hdmi_infoframe {
 557         enum HDMI_PACKET_TYPE type;
 558         u8 ver;
 559         u8 len;
 560 };
 561
 562 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 563 {
 564         return readl(hdata->regs + reg_id);
 565 }
 566
 567 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 568                                  u32 reg_id, u8 value)
 569 {
 570         writeb(value, hdata->regs + reg_id);
 571 }
 572
 573 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 574                                  u32 reg_id, u32 value, u32 mask)
 575 {
 576         u32 old = readl(hdata->regs + reg_id);
 577         value = (value & mask) | (old & ~mask);
 578         writel(value, hdata->regs + reg_id);
 579 }
 580
 581 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 582 {
 583         if (external) {
 584                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 585                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 586         } else {
 587                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 588                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 589         }
 590 }
 591
 592 static int hdmi_get_hpd(struct hdmi_context *hdata)
 593 {
 594         return gpio_get_value(hdata->hpd_gpio);
 595 }
 596
 597 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 598 {
 599 #define DUMPREG(reg_id) \
 600         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 601         readl(hdata->regs + reg_id))
 602         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 603         DUMPREG(HDMI_INTC_FLAG);
 604         DUMPREG(HDMI_INTC_CON);
 605         DUMPREG(HDMI_HPD_STATUS);
 606         DUMPREG(HDMI_V13_PHY_RSTOUT);
 607         DUMPREG(HDMI_V13_PHY_VPLL);
 608         DUMPREG(HDMI_V13_PHY_CMU);
 609         DUMPREG(HDMI_V13_CORE_RSTOUT);
 610
 611         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 612         DUMPREG(HDMI_CON_0);
 613         DUMPREG(HDMI_CON_1);
 614         DUMPREG(HDMI_CON_2);
 615         DUMPREG(HDMI_SYS_STATUS);
 616         DUMPREG(HDMI_V13_PHY_STATUS);
 617         DUMPREG(HDMI_STATUS_EN);
 618         DUMPREG(HDMI_HPD);
 619         DUMPREG(HDMI_MODE_SEL);
 620         DUMPREG(HDMI_V13_HPD_GEN);
 621         DUMPREG(HDMI_V13_DC_CONTROL);
 622         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 623
 624         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 625         DUMPREG(HDMI_H_BLANK_0);
 626         DUMPREG(HDMI_H_BLANK_1);
 627         DUMPREG(HDMI_V13_V_BLANK_0);
 628         DUMPREG(HDMI_V13_V_BLANK_1);
 629         DUMPREG(HDMI_V13_V_BLANK_2);
 630         DUMPREG(HDMI_V13_H_V_LINE_0);
 631         DUMPREG(HDMI_V13_H_V_LINE_1);
 632         DUMPREG(HDMI_V13_H_V_LINE_2);
 633         DUMPREG(HDMI_VSYNC_POL);
 634         DUMPREG(HDMI_INT_PRO_MODE);
 635         DUMPREG(HDMI_V13_V_BLANK_F_0);
 636         DUMPREG(HDMI_V13_V_BLANK_F_1);
 637         DUMPREG(HDMI_V13_V_BLANK_F_2);
 638         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 639         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 641         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 642         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 650
 651         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 652         DUMPREG(HDMI_TG_CMD);
 653         DUMPREG(HDMI_TG_H_FSZ_L);
 654         DUMPREG(HDMI_TG_H_FSZ_H);
 655         DUMPREG(HDMI_TG_HACT_ST_L);
 656         DUMPREG(HDMI_TG_HACT_ST_H);
 657         DUMPREG(HDMI_TG_HACT_SZ_L);
 658         DUMPREG(HDMI_TG_HACT_SZ_H);
 659         DUMPREG(HDMI_TG_V_FSZ_L);
 660         DUMPREG(HDMI_TG_V_FSZ_H);
 661         DUMPREG(HDMI_TG_VSYNC_L);
 662         DUMPREG(HDMI_TG_VSYNC_H);
 663         DUMPREG(HDMI_TG_VSYNC2_L);
 664         DUMPREG(HDMI_TG_VSYNC2_H);
 665         DUMPREG(HDMI_TG_VACT_ST_L);
 666         DUMPREG(HDMI_TG_VACT_ST_H);
 667         DUMPREG(HDMI_TG_VACT_SZ_L);
 668         DUMPREG(HDMI_TG_VACT_SZ_H);
 669         DUMPREG(HDMI_TG_FIELD_CHG_L);
 670         DUMPREG(HDMI_TG_FIELD_CHG_H);
 671         DUMPREG(HDMI_TG_VACT_ST2_L);
 672         DUMPREG(HDMI_TG_VACT_ST2_H);
 673         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 674         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 675         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 677         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 678         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 681 #undef DUMPREG
 682 }
 683
 684 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 685 {
 686         int i;
 687
 688 #define DUMPREG(reg_id) \
 689         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 690         readl(hdata->regs + reg_id))
 691
 692         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 693         DUMPREG(HDMI_INTC_CON);
 694         DUMPREG(HDMI_INTC_FLAG);
 695         DUMPREG(HDMI_HPD_STATUS);
 696         DUMPREG(HDMI_INTC_CON_1);
 697         DUMPREG(HDMI_INTC_FLAG_1);
 698         DUMPREG(HDMI_PHY_STATUS_0);
 699         DUMPREG(HDMI_PHY_STATUS_PLL);
 700         DUMPREG(HDMI_PHY_CON_0);
 701         DUMPREG(HDMI_PHY_RSTOUT);
 702         DUMPREG(HDMI_PHY_VPLL);
 703         DUMPREG(HDMI_PHY_CMU);
 704         DUMPREG(HDMI_CORE_RSTOUT);
 705
 706         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 707         DUMPREG(HDMI_CON_0);
 708         DUMPREG(HDMI_CON_1);
 709         DUMPREG(HDMI_CON_2);
 710         DUMPREG(HDMI_SYS_STATUS);
 711         DUMPREG(HDMI_PHY_STATUS_0);
 712         DUMPREG(HDMI_STATUS_EN);
 713         DUMPREG(HDMI_HPD);
 714         DUMPREG(HDMI_MODE_SEL);
 715         DUMPREG(HDMI_ENC_EN);
 716         DUMPREG(HDMI_DC_CONTROL);
 717         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 718
 719         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 720         DUMPREG(HDMI_H_BLANK_0);
 721         DUMPREG(HDMI_H_BLANK_1);
 722         DUMPREG(HDMI_V2_BLANK_0);
 723         DUMPREG(HDMI_V2_BLANK_1);
 724         DUMPREG(HDMI_V1_BLANK_0);
 725         DUMPREG(HDMI_V1_BLANK_1);
 726         DUMPREG(HDMI_V_LINE_0);
 727         DUMPREG(HDMI_V_LINE_1);
 728         DUMPREG(HDMI_H_LINE_0);
 729         DUMPREG(HDMI_H_LINE_1);
 730         DUMPREG(HDMI_HSYNC_POL);
 731
 732         DUMPREG(HDMI_VSYNC_POL);
 733         DUMPREG(HDMI_INT_PRO_MODE);
 734         DUMPREG(HDMI_V_BLANK_F0_0);
 735         DUMPREG(HDMI_V_BLANK_F0_1);
 736         DUMPREG(HDMI_V_BLANK_F1_0);
 737         DUMPREG(HDMI_V_BLANK_F1_1);
 738
 739         DUMPREG(HDMI_H_SYNC_START_0);
 740         DUMPREG(HDMI_H_SYNC_START_1);
 741         DUMPREG(HDMI_H_SYNC_END_0);
 742         DUMPREG(HDMI_H_SYNC_END_1);
 743
 744         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 745         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 748
 749         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 750         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 753
 754         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 755         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 758
 759         DUMPREG(HDMI_V_BLANK_F2_0);
 760         DUMPREG(HDMI_V_BLANK_F2_1);
 761         DUMPREG(HDMI_V_BLANK_F3_0);
 762         DUMPREG(HDMI_V_BLANK_F3_1);
 763         DUMPREG(HDMI_V_BLANK_F4_0);
 764         DUMPREG(HDMI_V_BLANK_F4_1);
 765         DUMPREG(HDMI_V_BLANK_F5_0);
 766         DUMPREG(HDMI_V_BLANK_F5_1);
 767
 768         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 769         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 776
 777         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 778         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 785
 786         DUMPREG(HDMI_VACT_SPACE_1_0);
 787         DUMPREG(HDMI_VACT_SPACE_1_1);
 788         DUMPREG(HDMI_VACT_SPACE_2_0);
 789         DUMPREG(HDMI_VACT_SPACE_2_1);
 790         DUMPREG(HDMI_VACT_SPACE_3_0);
 791         DUMPREG(HDMI_VACT_SPACE_3_1);
 792         DUMPREG(HDMI_VACT_SPACE_4_0);
 793         DUMPREG(HDMI_VACT_SPACE_4_1);
 794         DUMPREG(HDMI_VACT_SPACE_5_0);
 795         DUMPREG(HDMI_VACT_SPACE_5_1);
 796         DUMPREG(HDMI_VACT_SPACE_6_0);
 797         DUMPREG(HDMI_VACT_SPACE_6_1);
 798
 799         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 800         DUMPREG(HDMI_TG_CMD);
 801         DUMPREG(HDMI_TG_H_FSZ_L);
 802         DUMPREG(HDMI_TG_H_FSZ_H);
 803         DUMPREG(HDMI_TG_HACT_ST_L);
 804         DUMPREG(HDMI_TG_HACT_ST_H);
 805         DUMPREG(HDMI_TG_HACT_SZ_L);
 806         DUMPREG(HDMI_TG_HACT_SZ_H);
 807         DUMPREG(HDMI_TG_V_FSZ_L);
 808         DUMPREG(HDMI_TG_V_FSZ_H);
 809         DUMPREG(HDMI_TG_VSYNC_L);
 810         DUMPREG(HDMI_TG_VSYNC_H);
 811         DUMPREG(HDMI_TG_VSYNC2_L);
 812         DUMPREG(HDMI_TG_VSYNC2_H);
 813         DUMPREG(HDMI_TG_VACT_ST_L);
 814         DUMPREG(HDMI_TG_VACT_ST_H);
 815         DUMPREG(HDMI_TG_VACT_SZ_L);
 816         DUMPREG(HDMI_TG_VACT_SZ_H);
 817         DUMPREG(HDMI_TG_FIELD_CHG_L);
 818         DUMPREG(HDMI_TG_FIELD_CHG_H);
 819         DUMPREG(HDMI_TG_VACT_ST2_L);
 820         DUMPREG(HDMI_TG_VACT_ST2_H);
 821         DUMPREG(HDMI_TG_VACT_ST3_L);
 822         DUMPREG(HDMI_TG_VACT_ST3_H);
 823         DUMPREG(HDMI_TG_VACT_ST4_L);
 824         DUMPREG(HDMI_TG_VACT_ST4_H);
 825         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 826         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 827         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 828         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 829         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 830         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 831         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 832         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 833         DUMPREG(HDMI_TG_3D);
 834
 835         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 836         DUMPREG(HDMI_AVI_CON);
 837         DUMPREG(HDMI_AVI_HEADER0);
 838         DUMPREG(HDMI_AVI_HEADER1);
 839         DUMPREG(HDMI_AVI_HEADER2);
 840         DUMPREG(HDMI_AVI_CHECK_SUM);
 841         DUMPREG(HDMI_VSI_CON);
 842         DUMPREG(HDMI_VSI_HEADER0);
 843         DUMPREG(HDMI_VSI_HEADER1);
 844         DUMPREG(HDMI_VSI_HEADER2);
 845         for (i = 0; i < 7; ++i)
 846                 DUMPREG(HDMI_VSI_DATA(i));
 847
 848 #undef DUMPREG
 849 }
 850
 851 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 852 {
 853         if (hdata->is_v13)
 854                 hdmi_v13_regs_dump(hdata, prefix);
 855         else
 856                 hdmi_v14_regs_dump(hdata, prefix);
 857 }
 858
 859 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 860 {
 861         int i;
 862
 863         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 864                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 865                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 866                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 867                                 hdmi_v13_confs[i].interlace ==
 868                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 869                                  true : false))
 870                         return i;
 871
 872         return -EINVAL;
 873 }
 874
 875 static bool hdmi_is_connected(void *ctx)
 876 {
 877         struct hdmi_context *hdata = ctx;
 878         if (hdata->is_hdmi_powered_on) {
 879                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 880                         DRM_DEBUG_KMS("hdmi is not connected\n");
 881                         return false;
 882                 }
 883         } else if (!hdmi_get_hpd(hdata)) {
 884                         DRM_DEBUG_KMS("hdmi is not connected\n");
 885                         return false;
 886         }
 887
 888         return true;
 889 }
 890
 891 static int hdmi_get_edid(void *ctx, struct drm_connector *connector,
 892                                 u8 *edid, int len)
 893 {
 894         struct edid *raw_edid;
 895         struct hdmi_context *hdata = ctx;
 896
 897         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 898
 899         if (!hdata->ddc_port)
 900                 return -ENODEV;
 901
 902         raw_edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 903         if (raw_edid) {
 904         /* TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 905          * to get the edid and then call drm_detect_hdmi_monitor.
 906          */
 907                 hdata->has_hdmi_sink = drm_detect_hdmi_monitor(raw_edid);
 908                 hdata->has_hdmi_audio = drm_detect_monitor_audio(raw_edid);
 909                 memcpy(edid, raw_edid, min((1 + raw_edid->extensions)
 910                                         * EDID_LENGTH, len));
 911                 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
 912                         (hdata->has_hdmi_sink ? "hdmi monitor" : "dvi monitor"),
 913                         raw_edid->width_cm, raw_edid->height_cm);
 914                 kfree(raw_edid);
 915         } else {
 916                 return -ENODEV;
 917         }
 918
 919         return 0;
 920 }
 921
 922 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 923 {
 924         int i;
 925
 926         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 927                         check_timing->xres, check_timing->yres,
 928                         check_timing->refresh, (check_timing->vmode &
 929                         FB_VMODE_INTERLACED) ? true : false);
 930
 931         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 932                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 933                         hdmi_v13_confs[i].height == check_timing->yres &&
 934                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 935                         hdmi_v13_confs[i].interlace ==
 936                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 937                          true : false))
 938                                 return 0;
 939
 940         /* TODO */
 941
 942         return -EINVAL;
 943 }
 944
 945 static int find_hdmiphy_conf(int pixel_clock)
 946 {
 947         int i;
 948
 949         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 950                 if (phy_configs[i].pixel_clock == pixel_clock)
 951                         return i;
 952         }
 953         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 954         return -EINVAL;
 955 }
 956
 957 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 958 {
 959         int ret;
 960         enum exynos_mixer_mode_type mode_type;
 961
 962         /* Make sure the mixer can generate this mode */
 963         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 964         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 965                 return -EINVAL;
 966
 967         ret = find_hdmiphy_conf(mode->pixclock);
 968         return ret < 0 ? ret : 0;
 969 }
 970
 971 static u8 hdmi_chksum(struct hdmi_context *hdata,
 972                         u32 start, u8 len, u32 hdr_sum)
 973 {
 974         int i;
 975         /* hdr_sum : header0 + header1 + header2
 976         * start : start address of packet byte1
 977         * len : packet bytes - 1 */
 978         for (i = 0; i < len; ++i)
 979                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 980
 981         return (u8)(0x100 - (hdr_sum & 0xff));
 982 }
 983
 984 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 985                         struct hdmi_infoframe *infoframe)
 986 {
 987         u32 hdr_sum;
 988         u8 chksum;
 989         u32 aspect_ratio;
 990         u32 mod;
 991
 992         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 993         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 994         if (!hdata->has_hdmi_sink) {
 995                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 996                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 997                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 998                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 999                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
1000                 return;
1001         }
1002
1003         switch (infoframe->type) {
1004
1005         case HDMI_PACKET_TYPE_AVI:
1006                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1007                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1008                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1009                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1010                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1011                 /* Output format zero hardcoded ,RGB YBCR selection */
1012                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1013                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1014
1015                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1016
1017                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1018                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1019                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1020
1021                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1022                                         infoframe->len, hdr_sum);
1023                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1024                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1025                 break;
1026
1027         case HDMI_PACKET_TYPE_AUI:
1028                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1029                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1030                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1031                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1032                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1033                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1034                                         infoframe->len, hdr_sum);
1035                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1036                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1037                 break;
1038
1039         default:
1040                 break;
1041         }
1042 }
1043
1044 static int hdmi_check_timing(void *ctx, void *timing)
1045 {
1046         struct hdmi_context *hdata = ctx;
1047         struct fb_videomode *check_timing = timing;
1048
1049         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1050
1051         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1052                         check_timing->yres, check_timing->refresh,
1053                         check_timing->vmode);
1054
1055         if (hdata->is_v13)
1056                 return hdmi_v13_check_timing(check_timing);
1057         else
1058                 return hdmi_v14_check_timing(check_timing);
1059 }
1060
1061 static void hdmi_set_acr(u32 freq, u8 *acr)
1062 {
1063         u32 n, cts;
1064
1065         switch (freq) {
1066         case 32000:
1067                 n = 4096;
1068                 cts = 27000;
1069                 break;
1070         case 44100:
1071                 n = 6272;
1072                 cts = 30000;
1073                 break;
1074         case 88200:
1075                 n = 12544;
1076                 cts = 30000;
1077                 break;
1078         case 176400:
1079                 n = 25088;
1080                 cts = 30000;
1081                 break;
1082         case 48000:
1083                 n = 6144;
1084                 cts = 27000;
1085                 break;
1086         case 96000:
1087                 n = 12288;
1088                 cts = 27000;
1089                 break;
1090         case 192000:
1091                 n = 24576;
1092                 cts = 27000;
1093                 break;
1094         default:
1095                 n = 0;
1096                 cts = 0;
1097                 break;
1098         }
1099
1100         acr[1] = cts >> 16;
1101         acr[2] = cts >> 8 & 0xff;
1102         acr[3] = cts & 0xff;
1103
1104         acr[4] = n >> 16;
1105         acr[5] = n >> 8 & 0xff;
1106         acr[6] = n & 0xff;
1107 }
1108
1109 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1110 {
1111         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1114         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1115         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1116         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1117         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1118         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1119         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1120
1121         if (hdata->is_v13)
1122                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1123         else
1124                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1125 }
1126
1127 static void hdmi_audio_init(struct hdmi_context *hdata)
1128 {
1129         u32 sample_rate, bits_per_sample, frame_size_code;
1130         u32 data_num, bit_ch, sample_frq;
1131         u32 val;
1132         u8 acr[7];
1133
1134         sample_rate = 44100;
1135         bits_per_sample = 16;
1136         frame_size_code = 0;
1137
1138         switch (bits_per_sample) {
1139         case 20:
1140                 data_num = 2;
1141                 bit_ch  = 1;
1142                 break;
1143         case 24:
1144                 data_num = 3;
1145                 bit_ch  = 1;
1146                 break;
1147         default:
1148                 data_num = 1;
1149                 bit_ch  = 0;
1150                 break;
1151         }
1152
1153         hdmi_set_acr(sample_rate, acr);
1154         hdmi_reg_acr(hdata, acr);
1155
1156         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1157                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1158                                 | HDMI_I2S_MUX_ENABLE);
1159
1160         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1161                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1162
1163         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1164
1165         sample_frq = (sample_rate == 44100) ? 0 :
1166                         (sample_rate == 48000) ? 2 :
1167                         (sample_rate == 32000) ? 3 :
1168                         (sample_rate == 96000) ? 0xa : 0x0;
1169
1170         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1171         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1172
1173         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1174         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1175
1176         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1177         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1178                         | HDMI_I2S_SEL_LRCK(6));
1179         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1180                         | HDMI_I2S_SEL_SDATA2(4));
1181         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1182                         | HDMI_I2S_SEL_SDATA2(2));
1183         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1184
1185         /* I2S_CON_1 & 2 */
1186         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1187                         | HDMI_I2S_L_CH_LOW_POL);
1188         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1189                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1190                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1191                         | HDMI_I2S_BASIC_FORMAT);
1192
1193         /* Configure register related to CUV information */
1194         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1195                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1196                         | HDMI_I2S_COPYRIGHT
1197                         | HDMI_I2S_LINEAR_PCM
1198                         | HDMI_I2S_CONSUMER_FORMAT);
1199         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1200         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1201         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1202                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1203         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1204                         HDMI_I2S_ORG_SMP_FREQ_44_1
1205                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1206                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1207
1208         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1209 }
1210
1211 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1212 {
1213         if (!hdata->has_hdmi_audio)
1214                 return;
1215
1216         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1217         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1218                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1219 }
1220
1221 static void hdmi_conf_reset(struct hdmi_context *hdata)
1222 {
1223         u32 reg;
1224
1225         /* disable hpd handle for drm */
1226         hdata->hpd_handle = false;
1227
1228         if (hdata->is_v13)
1229                 reg = HDMI_V13_CORE_RSTOUT;
1230         else
1231                 reg = HDMI_CORE_RSTOUT;
1232
1233         /* resetting HDMI core */
1234         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1235         mdelay(10);
1236         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1237         mdelay(10);
1238
1239         /* enable hpd handle for drm */
1240         hdata->hpd_handle = true;
1241 }
1242
1243 static void hdmi_enable_video(struct hdmi_context *hdata)
1244 {
1245         if (hdata->is_v13)
1246                 return;
1247
1248         hdata->video_enabled = true;
1249         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1250 }
1251
1252 static void hdmi_disable_video(struct hdmi_context *hdata)
1253 {
1254         if (hdata->is_v13)
1255                 return;
1256
1257         /* Set the blue screen color to black */
1258         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_0, 0);
1259         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_1, 0);
1260         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_0, 0);
1261         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_1, 0);
1262         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_0, 0);
1263         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_1, 0);
1264
1265         /* Enable the "blue screen", which effectively disconnects the mixer */
1266         hdata->video_enabled = false;
1267         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
1268 }
1269
1270 static void hdmi_conf_init(struct hdmi_context *hdata)
1271 {
1272         struct hdmi_infoframe infoframe;
1273         /* disable hpd handle for drm */
1274         hdata->hpd_handle = false;
1275
1276         /* enable HPD interrupts */
1277         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1278                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1279         mdelay(10);
1280         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1281                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1282
1283         /* choose HDMI mode */
1284         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1285                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1286
1287         if (hdata->video_enabled)
1288                 hdmi_enable_video(hdata);
1289         else
1290                 hdmi_disable_video(hdata);
1291
1292         if (!hdata->has_hdmi_sink) {
1293                 /* choose DVI mode */
1294                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1295                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1296                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1297                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1298         }
1299
1300         if (hdata->is_v13) {
1301                 /* choose bluescreen (fecal) color */
1302                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1303                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1304                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1305
1306                 /* enable AVI packet every vsync, fixes purple line problem */
1307                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1308                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1309                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1310                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1311
1312                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1313                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1314                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1315         } else {
1316                 /* enable AVI packet every vsync, fixes purple line problem */
1317                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1318
1319                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1320                 infoframe.ver = HDMI_AVI_VERSION;
1321                 infoframe.len = HDMI_AVI_LENGTH;
1322                 hdmi_reg_infoframe(hdata, &infoframe);
1323
1324                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1325                 infoframe.ver = HDMI_AUI_VERSION;
1326                 infoframe.len = HDMI_AUI_LENGTH;
1327                 hdmi_reg_infoframe(hdata, &infoframe);
1328
1329         }
1330
1331         /* enable hpd handle for drm */
1332         hdata->hpd_handle = true;
1333 }
1334
1335 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1336 {
1337         const struct hdmi_v13_preset_conf *conf =
1338                 hdmi_v13_confs[hdata->cur_conf].conf;
1339         const struct hdmi_v13_core_regs *core = &conf->core;
1340         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1341         int tries;
1342
1343         /* setting core registers */
1344         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1345         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1346         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1347         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1348         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1349         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1350         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1351         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1352         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1353         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1354         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1355         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1356         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1357         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1358         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1359         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1360         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1361         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1362         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1363         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1364         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1365         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1366         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1367         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1368         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1369         /* Timing generator registers */
1370         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1371         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1372         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1373         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1374         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1375         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1376         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1377         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1378         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1379         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1380         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1381         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1382         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1383         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1384         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1385         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1386         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1387         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1388         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1389         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1390         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1391         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1392         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1393         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1394         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1395         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1396         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1397         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1398
1399         /* waiting for HDMIPHY's PLL to get to steady state */
1400         for (tries = 100; tries; --tries) {
1401                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1402                 if (val & HDMI_PHY_STATUS_READY)
1403                         break;
1404                 mdelay(1);
1405         }
1406         /* steady state not achieved */
1407         if (tries == 0) {
1408                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1409                 hdmi_regs_dump(hdata, "timing apply");
1410         }
1411
1412         clk_disable(hdata->res.sclk_hdmi);
1413         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1414         clk_enable(hdata->res.sclk_hdmi);
1415
1416         /* enable HDMI and timing generator */
1417         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1418         if (core->int_pro_mode[0])
1419                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1420                                 HDMI_FIELD_EN);
1421         else
1422                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1423 }
1424
1425 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1426 {
1427         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1428         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1429         int tries;
1430
1431         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1432         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1433         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1434         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1435         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1436         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1437         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1438         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1439         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1440         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1441         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1442         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1443         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1444         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1445         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1446         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1447         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1448         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1449         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1450         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1451         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1452         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1453                         core->v_sync_line_bef_2[0]);
1454         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1455                         core->v_sync_line_bef_2[1]);
1456         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1457                         core->v_sync_line_bef_1[0]);
1458         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1459                         core->v_sync_line_bef_1[1]);
1460         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1461                         core->v_sync_line_aft_2[0]);
1462         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1463                         core->v_sync_line_aft_2[1]);
1464         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1465                         core->v_sync_line_aft_1[0]);
1466         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1467                         core->v_sync_line_aft_1[1]);
1468         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1469                         core->v_sync_line_aft_pxl_2[0]);
1470         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1471                         core->v_sync_line_aft_pxl_2[1]);
1472         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1473                         core->v_sync_line_aft_pxl_1[0]);
1474         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1475                         core->v_sync_line_aft_pxl_1[1]);
1476         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1477         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1478         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1479         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1480         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1481         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1482         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1483         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1484         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1485                         core->v_sync_line_aft_3[0]);
1486         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1487                         core->v_sync_line_aft_3[1]);
1488         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1489                         core->v_sync_line_aft_4[0]);
1490         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1491                         core->v_sync_line_aft_4[1]);
1492         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1493                         core->v_sync_line_aft_5[0]);
1494         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1495                         core->v_sync_line_aft_5[1]);
1496         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1497                         core->v_sync_line_aft_6[0]);
1498         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1499                         core->v_sync_line_aft_6[1]);
1500         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1501                         core->v_sync_line_aft_pxl_3[0]);
1502         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1503                         core->v_sync_line_aft_pxl_3[1]);
1504         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1505                         core->v_sync_line_aft_pxl_4[0]);
1506         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1507                         core->v_sync_line_aft_pxl_4[1]);
1508         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1509                         core->v_sync_line_aft_pxl_5[0]);
1510         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1511                         core->v_sync_line_aft_pxl_5[1]);
1512         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1513                         core->v_sync_line_aft_pxl_6[0]);
1514         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1515                         core->v_sync_line_aft_pxl_6[1]);
1516         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1517         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1518         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1519         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1520         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1521         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1522         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1523         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1524         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1525         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1526         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1527         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1528
1529         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1531         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1532         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1533         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1534         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1535         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1536         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1537         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1538         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1539         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1540         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1541         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1542         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1543         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1544         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1545         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1546         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1547         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1548         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1549         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1550         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1551         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1552         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1553         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1554         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1555         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1556         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1557         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1558         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1559         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1560         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1561         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1562
1563         /* waiting for HDMIPHY's PLL to get to steady state */
1564         for (tries = 100; tries; --tries) {
1565                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1566                 if (val & HDMI_PHY_STATUS_READY)
1567                         break;
1568                 mdelay(1);
1569         }
1570         /* steady state not achieved */
1571         if (tries == 0) {
1572                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1573                 hdmi_regs_dump(hdata, "timing apply");
1574         }
1575
1576         clk_disable(hdata->res.sclk_hdmi);
1577         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1578         clk_enable(hdata->res.sclk_hdmi);
1579
1580         /* enable HDMI and timing generator */
1581         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1582         if (core->int_pro_mode[0])
1583                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1584                                 HDMI_FIELD_EN);
1585         else
1586                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1587 }
1588
1589 static void hdmi_timing_apply(struct hdmi_context *hdata)
1590 {
1591         if (hdata->is_v13)
1592                 hdmi_v13_timing_apply(hdata);
1593         else
1594                 hdmi_v14_timing_apply(hdata);
1595 }
1596
1597 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1598 {
1599         u8 buffer[2];
1600         u32 reg;
1601
1602         clk_disable(hdata->res.sclk_hdmi);
1603         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1604         clk_enable(hdata->res.sclk_hdmi);
1605
1606         /* operation mode */
1607         buffer[0] = 0x1f;
1608         buffer[1] = 0x00;
1609
1610         if (hdata->hdmiphy_port)
1611                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1612
1613         if (hdata->is_v13)
1614                 reg = HDMI_V13_PHY_RSTOUT;
1615         else
1616                 reg = HDMI_PHY_RSTOUT;
1617
1618         /* reset hdmiphy */
1619         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1620         mdelay(10);
1621         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1622         mdelay(10);
1623 }
1624
1625 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1626 {
1627         const u8 *hdmiphy_data;
1628         u8 buffer[32];
1629         u8 operation[2];
1630         u8 read_buffer[32] = {0, };
1631         int ret;
1632         int i;
1633
1634         if (!hdata->hdmiphy_port) {
1635                 DRM_ERROR("hdmiphy is not attached\n");
1636                 return;
1637         }
1638
1639         /* pixel clock */
1640         if (hdata->is_v13) {
1641                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1642         } else {
1643                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1644                 hdmiphy_data = phy_configs[i].conf;
1645         }
1646
1647         memcpy(buffer, hdmiphy_data, 32);
1648         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1649         if (ret != 32) {
1650                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1651                 return;
1652         }
1653
1654         mdelay(10);
1655
1656         /* operation mode */
1657         operation[0] = 0x1f;
1658         operation[1] = 0x80;
1659
1660         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1661         if (ret != 2) {
1662                 DRM_ERROR("failed to enable hdmiphy\n");
1663                 return;
1664         }
1665
1666         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1667         if (ret < 0) {
1668                 DRM_ERROR("failed to read hdmiphy config\n");
1669                 return;
1670         }
1671
1672         for (i = 0; i < ret; i++)
1673                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1674                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1675 }
1676
1677 static void hdmi_conf_apply(struct hdmi_context *hdata)
1678 {
1679         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1680
1681         hdmiphy_conf_reset(hdata);
1682         hdmiphy_conf_apply(hdata);
1683
1684         hdmi_conf_reset(hdata);
1685         hdmi_conf_init(hdata);
1686         if (!hdata->is_soc_exynos5)
1687                 hdmi_audio_init(hdata);
1688
1689         /* setting core registers */
1690         hdmi_timing_apply(hdata);
1691         if (!hdata->is_soc_exynos5)
1692                 hdmi_audio_control(hdata, true);
1693
1694         hdmi_regs_dump(hdata, "start");
1695 }
1696
1697 static void hdmi_mode_copy(struct drm_display_mode *dst,
1698         struct drm_display_mode *src)
1699 {
1700         struct drm_mode_object base;
1701
1702         /* following information should be preserved,
1703          * required for releasing the drm_display_mode node,
1704          * duplicated to recieve adjustment info. */
1705
1706         base.id = dst->base.id;
1707         base.type = dst->base.type;
1708
1709         memcpy(dst, src, sizeof(struct drm_display_mode));
1710
1711         dst->base.id = base.id;
1712         dst->base.type = base.type;
1713 }
1714
1715 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1716                                 struct drm_display_mode *mode,
1717                                 struct drm_display_mode *adjusted_mode)
1718 {
1719         struct drm_display_mode *m;
1720         struct hdmi_context *hdata = ctx;
1721         int index;
1722
1723         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1724
1725         drm_mode_set_crtcinfo(adjusted_mode, 0);
1726
1727         if (hdata->is_v13)
1728                 index = hdmi_v13_conf_index(adjusted_mode);
1729         else
1730                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1731
1732         /* just return if user desired mode exists. */
1733         if (index >= 0)
1734                 return;
1735
1736         /*
1737          * otherwise, find the most suitable mode among modes and change it
1738          * to adjusted_mode.
1739          */
1740         list_for_each_entry(m, &connector->modes, head) {
1741                 if (hdata->is_v13)
1742                         index = hdmi_v13_conf_index(m);
1743                 else
1744                         index = find_hdmiphy_conf(m->clock * 1000);
1745
1746                 if (index >= 0) {
1747                         DRM_INFO("desired mode doesn't exist so\n");
1748                         DRM_INFO("use the most suitable mode among modes.\n");
1749                         hdmi_mode_copy(adjusted_mode, m);
1750                         break;
1751                 }
1752         }
1753 }
1754
1755 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1756 {
1757         int i;
1758         BUG_ON(num_bytes > 4);
1759         for (i = 0; i < num_bytes; i++)
1760                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1761 }
1762
1763 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1764                         struct drm_display_mode *m)
1765 {
1766         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1767         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1768
1769         hdata->mode_conf.vic = drm_match_cea_mode(m);
1770
1771         hdata->mode_conf.pixel_clock = m->clock * 1000;
1772         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1773         hdmi_set_reg(core->v_line, 2, m->vtotal);
1774         hdmi_set_reg(core->h_line, 2, m->htotal);
1775         hdmi_set_reg(core->hsync_pol, 1,
1776                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1777         hdmi_set_reg(core->vsync_pol, 1,
1778                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1779         hdmi_set_reg(core->int_pro_mode, 1,
1780                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1781
1782         /*
1783          * Quirk requirement for exynos 5 HDMI IP design,
1784          * 2 pixels less than the actual calculation for hsync_start
1785          * and end.
1786          */
1787
1788         /* Following values & calculations differ for different type of modes */
1789         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1790                 /* Interlaced Mode */
1791                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1792                         (m->vsync_end - m->vdisplay) / 2);
1793                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1794                         (m->vsync_start - m->vdisplay) / 2);
1795                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1796                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1797                 hdmi_set_reg(core->v_blank_f0, 2,
1798                         (m->vtotal + ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1799                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1800                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1801                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1802                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1803                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1804                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1805                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1806                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1807                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1808                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1809                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1810                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1811         } else {
1812                 /* Progressive Mode */
1813                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1814                         m->vsync_end - m->vdisplay);
1815                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1816                         m->vsync_start - m->vdisplay);
1817                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1818                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1819                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1820                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1821                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1822                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1823                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1824                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1825                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1826                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1827                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1828                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1829                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1830         }
1831
1832         /* Following values & calculations are same irrespective of mode type */
1833         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1834         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1835         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1836         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1837         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1838         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1839         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1840         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1841         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1842         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1843         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1844         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1845         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1846         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1847         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1848         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1849         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1850         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1851         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1852         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1853
1854         /* Timing generator registers */
1855         hdmi_set_reg(tg->cmd, 1, 0x0);
1856         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1857         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1858         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1859         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1860         hdmi_set_reg(tg->vsync, 2, 0x1);
1861         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1862         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1863         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1864         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1865         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1866         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1867         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1868
1869         if (hdata->is_soc_exynos5) {
1870                 /* Workaround 4 implementation for 1440x900 resolution support */
1871                 if (m->hdisplay == 1440 && m->vdisplay == 900 && m->clock == 106500) {
1872                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0xe0);
1873                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0xe0);
1874                 }
1875
1876                 /* Workaround 3 implementation for 800x600 resolution support */
1877                 if (m->hdisplay == 800 && m->vdisplay == 600 && m->clock == 40000) {
1878                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0x20);
1879                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0x20);
1880                 }
1881         }
1882 }
1883
1884 static void hdmi_mode_set(void *ctx, void *mode)
1885 {
1886         struct hdmi_context *hdata = ctx;
1887
1888         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1889
1890         if (hdata->is_v13)
1891                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1892         else
1893                 hdmi_v14_mode_set(hdata, mode);
1894 }
1895
1896 static void hdmi_commit(void *ctx)
1897 {
1898         struct hdmi_context *hdata = ctx;
1899
1900         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1901         if (!hdata->is_hdmi_powered_on)
1902                 return;
1903
1904         hdmi_conf_apply(hdata);
1905         hdata->enabled = true;
1906 }
1907
1908 static void hdmi_apply(void *ctx)
1909 {
1910         hdmi_commit(ctx);
1911 }
1912
1913 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
1914                                u8 reg, u8 mask, u8 val)
1915 {
1916         int ret;
1917         u8 buffer[2];
1918
1919         buffer[0] = reg;
1920         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
1921         reg_cache[reg] = buffer[1];
1922
1923         ret = i2c_master_send(client, buffer, 2);
1924         if (ret != 2)
1925                 return -EIO;
1926
1927         return 0;
1928 }
1929
1930 static int hdmiphy_s_power(struct i2c_client *client, bool on)
1931 {
1932         u8 reg_cache[32] = { 0 };
1933         u8 buffer[2];
1934         int ret;
1935
1936         DRM_DEBUG_KMS("%s: hdmiphy is %s\n", __func__, on ? "on" : "off");
1937
1938         /* Cache all 32 registers to make the code below faster */
1939         buffer[0] = 0x0;
1940         ret = i2c_master_send(client, buffer, 1);
1941         if (ret != 1) {
1942                 ret = -EIO;
1943                 goto exit;
1944         }
1945         ret = i2c_master_recv(client, reg_cache, 32);
1946         if (ret != 32) {
1947                 ret = -EIO;
1948                 goto exit;
1949         }
1950
1951         /* Go to/from configuration from/to operation mode */
1952         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
1953                                   on ? 0x80 : 0x00);
1954         if (ret)
1955                 goto exit;
1956
1957         /*
1958          * Turn off undocumented "oscpad" if !on; it turns on again in
1959          * hdmiphy_conf_apply()
1960          */
1961         if (!on)
1962                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
1963                 if (ret)
1964                         goto exit;
1965
1966         /* Disable powerdown if on; enable if !on */
1967         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
1968                                   on ? 0 : ~0);
1969         if (ret)
1970                 goto exit;
1971         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
1972                                   on ? 0 : ~0);
1973         if (ret)
1974                 goto exit;
1975
1976         /*
1977          * Turn off bit 3 of reg 4 if !on; it turns on again in
1978          * hdmiphy_conf_apply().  It's unclear what this bit does.
1979          */
1980         if (!on)
1981                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
1982                 if (ret)
1983                         goto exit;
1984
1985 exit:
1986         /* Don't expect any errors so just do a single warn */
1987         WARN_ON(ret);
1988
1989         return ret;
1990 }
1991
1992 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1993 {
1994         struct hdmi_resources *res = &hdata->res;
1995
1996         hdata->is_hdmi_powered_on = true;
1997         hdmi_cfg_hpd(hdata, false);
1998
1999         /* irq change by TV power status */
2000         if (hdata->curr_irq == hdata->internal_irq)
2001                 return;
2002
2003         disable_irq(hdata->curr_irq);
2004
2005         hdata->curr_irq = hdata->internal_irq;
2006
2007         enable_irq(hdata->curr_irq);
2008
2009         /* turn HDMI power on */
2010         regulator_bulk_enable(res->regul_count, res->regul_bulk);
2011
2012         /* power-on hdmi clocks */
2013         clk_enable(res->hdmiphy);
2014
2015         hdmiphy_s_power(hdata->hdmiphy_port, 1);
2016         hdmiphy_conf_reset(hdata);
2017         hdmi_conf_reset(hdata);
2018         hdmi_conf_init(hdata);
2019         if (!hdata->is_soc_exynos5)
2020                 hdmi_audio_init(hdata);
2021         hdmi_commit(hdata);
2022 }
2023
2024 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2025 {
2026         struct hdmi_resources *res = &hdata->res;
2027
2028         hdmi_cfg_hpd(hdata, true);
2029
2030         if (hdata->curr_irq == hdata->external_irq)
2031                 return;
2032
2033         disable_irq(hdata->curr_irq);
2034         hdata->curr_irq = hdata->external_irq;
2035
2036         enable_irq(hdata->curr_irq);
2037         hdata->is_hdmi_powered_on = false;
2038
2039         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2040         hdmiphy_conf_reset(hdata);
2041
2042         /* power-off hdmi clocks */
2043         clk_disable(res->hdmiphy);
2044
2045         /* turn HDMI power off */
2046         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2047 }
2048
2049 static int hdmi_power(void *ctx, int mode)
2050 {
2051         struct hdmi_context *hdata = ctx;
2052
2053         switch (mode) {
2054         case DRM_MODE_DPMS_ON:
2055                 if (!hdata->is_hdmi_powered_on)
2056                         hdmi_resource_poweron(hdata);
2057                 hdmi_enable_video(hdata);
2058                 break;
2059         case DRM_MODE_DPMS_STANDBY:
2060                 hdmi_disable_video(hdata);
2061                 break;
2062         case DRM_MODE_DPMS_OFF:
2063         case DRM_MODE_DPMS_SUSPEND:
2064                 if (hdata->is_hdmi_powered_on)
2065                         hdmi_resource_poweroff(hdata);
2066                 break;
2067         default:
2068                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2069                 break;
2070         }
2071
2072         return 0;
2073 }
2074
2075 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
2076 {
2077         struct hdmi_context *hdata = ctx;
2078
2079         hdata->drm_dev = drm_dev;
2080
2081         return 0;
2082 }
2083
2084 static struct exynos_panel_ops hdmi_ops = {
2085         /* display */
2086         .subdrv_probe   = hdmi_subdrv_probe,
2087         .is_connected   = hdmi_is_connected,
2088         .get_edid       = hdmi_get_edid,
2089         .check_timing   = hdmi_check_timing,
2090         .power          = hdmi_power,
2091
2092         /* manager */
2093         .mode_fixup     = hdmi_mode_fixup,
2094         .mode_set       = hdmi_mode_set,
2095         .commit         = hdmi_commit,
2096         .apply          = hdmi_apply,
2097 };
2098
2099 /*
2100  * Handle hotplug events outside the interrupt handler proper.
2101  */
2102 static void hdmi_hotplug_func(struct work_struct *work)
2103 {
2104         struct hdmi_context *hdata =
2105                 container_of(work, struct hdmi_context, hotplug_work);
2106
2107         drm_helper_hpd_irq_event(hdata->drm_dev);
2108 }
2109
2110 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
2111 {
2112         struct hdmi_context *hdata = arg;
2113         u32 intc_flag;
2114         if (hdata->is_hdmi_powered_on) {
2115                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
2116                 /* clearing flags for HPD plug/unplug */
2117                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2118                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
2119                                 hdata->hpd_handle);
2120                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2121                                 HDMI_INTC_FLAG_HPD_UNPLUG);
2122                 }
2123                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2124                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
2125                                 hdata->hpd_handle);
2126                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2127                                 HDMI_INTC_FLAG_HPD_PLUG);
2128                 }
2129         }
2130
2131         if (hdata->drm_dev && hdata->hpd_handle)
2132                 queue_work(hdata->wq, &hdata->hotplug_work);
2133
2134         return IRQ_HANDLED;
2135 }
2136
2137 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2138 {
2139         struct device *dev = hdata->dev;
2140         struct hdmi_resources *res = &hdata->res;
2141 #ifndef CONFIG_ARCH_EXYNOS5
2142         static char *supply[] = {
2143                 "hdmi-en",
2144                 "vdd",
2145                 "vdd_osc",
2146                 "vdd_pll",
2147         };
2148         int i, ret;
2149 #endif
2150
2151         DRM_DEBUG_KMS("HDMI resource init\n");
2152
2153         memset(res, 0, sizeof *res);
2154
2155         /* get clocks, power */
2156         res->hdmi = clk_get(dev, "hdmi");
2157         if (IS_ERR_OR_NULL(res->hdmi)) {
2158                 DRM_ERROR("failed to get clock 'hdmi'\n");
2159                 goto fail;
2160         }
2161         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
2162         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
2163                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2164                 goto fail;
2165         }
2166         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2167         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2168                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2169                 goto fail;
2170         }
2171         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2172         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2173                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2174                 goto fail;
2175         }
2176         res->hdmiphy = clk_get(dev, "hdmiphy");
2177         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2178                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2179                 goto fail;
2180         }
2181
2182         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2183
2184 #ifndef CONFIG_ARCH_EXYNOS5
2185         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2186                 sizeof res->regul_bulk[0], GFP_KERNEL);
2187         if (!res->regul_bulk) {
2188                 DRM_ERROR("failed to get memory for regulators\n");
2189                 goto fail;
2190         }
2191         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2192                 res->regul_bulk[i].supply = supply[i];
2193                 res->regul_bulk[i].consumer = NULL;
2194         }
2195         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2196         if (ret) {
2197                 DRM_ERROR("failed to get regulators\n");
2198                 goto fail;
2199         }
2200         res->regul_count = ARRAY_SIZE(supply);
2201 #endif
2202         /* TODO:
2203          * These clocks also should be added in
2204          * runtime resume and runtime suspend
2205          */
2206         clk_enable(res->hdmi);
2207         clk_enable(res->sclk_hdmi);
2208
2209         return 0;
2210 fail:
2211         DRM_ERROR("HDMI resource init - failed\n");
2212         return -ENODEV;
2213 }
2214
2215 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2216 {
2217         struct hdmi_resources *res = &hdata->res;
2218
2219         regulator_bulk_free(res->regul_count, res->regul_bulk);
2220         /* kfree is NULL-safe */
2221         kfree(res->regul_bulk);
2222         if (!IS_ERR_OR_NULL(res->hdmiphy))
2223                 clk_put(res->hdmiphy);
2224         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2225                 clk_put(res->sclk_hdmiphy);
2226         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2227                 clk_put(res->sclk_pixel);
2228         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2229                 clk_put(res->sclk_hdmi);
2230         if (!IS_ERR_OR_NULL(res->hdmi))
2231                 clk_put(res->hdmi);
2232         memset(res, 0, sizeof *res);
2233
2234         return 0;
2235 }
2236
2237 static struct i2c_client *hdmi_ddc, *hdmi_hdmiphy;
2238
2239 void hdmi_attach_ddc_client(struct i2c_client *ddc)
2240 {
2241         if (ddc)
2242                 hdmi_ddc = ddc;
2243 }
2244
2245 void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy)
2246 {
2247         if (hdmiphy)
2248                 hdmi_hdmiphy = hdmiphy;
2249 }
2250
2251 struct platform_device *hdmi_audio_device;
2252
2253 int hdmi_register_audio_device(struct platform_device *pdev)
2254 {
2255         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2256         struct platform_device *audio_dev;
2257         int ret;
2258
2259         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2260         if (!audio_dev) {
2261                 DRM_ERROR("hdmi audio device allocation failed.\n");
2262                 ret = -ENOMEM;
2263                 goto err;
2264         }
2265
2266         ret = platform_device_add_resources(audio_dev, pdev->resource,
2267                         pdev->num_resources);
2268         if (ret) {
2269                 ret = -ENOMEM;
2270                 goto err_device;
2271         }
2272
2273         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2274         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2275
2276         ret = platform_device_add(audio_dev);
2277         if (ret) {
2278                 DRM_ERROR("hdmi audio device add failed.\n");
2279                 goto err_device;
2280         }
2281
2282         hdmi_audio_device = audio_dev;
2283         return 0;
2284
2285 err_device:
2286         platform_device_put(audio_dev);
2287
2288 err:
2289         return ret;
2290 }
2291
2292 void hdmi_unregister_audio_device(void)
2293 {
2294         platform_device_unregister(hdmi_audio_device);
2295 }
2296
2297 static int __devinit hdmi_probe(struct platform_device *pdev)
2298 {
2299         struct device *dev = &pdev->dev;
2300         struct hdmi_context *hdata;
2301         struct exynos_drm_hdmi_pdata *pdata;
2302         struct resource *res;
2303         int ret;
2304         enum of_gpio_flags flags;
2305
2306         DRM_DEBUG_KMS("[%d]\n", __LINE__);
2307
2308         pdata = pdev->dev.platform_data;
2309         if (!pdata) {
2310                 DRM_ERROR("no platform data specified\n");
2311                 return -EINVAL;
2312         }
2313
2314         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2315         if (!hdata) {
2316                 DRM_ERROR("out of memory\n");
2317                 return -ENOMEM;
2318         }
2319
2320         platform_set_drvdata(pdev, hdata);
2321
2322         hdata->is_v13 = pdata->is_v13;
2323         hdata->default_win = pdata->default_win;
2324         hdata->default_timing = &pdata->timing;
2325         hdata->default_bpp = pdata->bpp;
2326         hdata->dev = dev;
2327         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2328                 "samsung,exynos5-hdmi");
2329
2330         ret = hdmi_resources_init(hdata);
2331         if (ret) {
2332                 ret = -EINVAL;
2333                 goto err_data;
2334         }
2335
2336         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2337         if (!res) {
2338                 DRM_ERROR("failed to find registers\n");
2339                 ret = -ENOENT;
2340                 goto err_resource;
2341         }
2342
2343         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2344                                            dev_name(dev));
2345         if (!hdata->regs_res) {
2346                 DRM_ERROR("failed to claim register region\n");
2347                 ret = -ENOENT;
2348                 goto err_resource;
2349         }
2350
2351         hdata->regs = ioremap(res->start, resource_size(res));
2352         if (!hdata->regs) {
2353                 DRM_ERROR("failed to map registers\n");
2354                 ret = -ENXIO;
2355                 goto err_req_region;
2356         }
2357
2358         /* DDC i2c driver */
2359         if (i2c_add_driver(&ddc_driver)) {
2360                 DRM_ERROR("failed to register ddc i2c driver\n");
2361                 ret = -ENOENT;
2362                 goto err_iomap;
2363         }
2364
2365         hdata->ddc_port = hdmi_ddc;
2366
2367         /* hdmiphy i2c driver */
2368         if (i2c_add_driver(&hdmiphy_driver)) {
2369                 DRM_ERROR("failed to register hdmiphy i2c driver\n");
2370                 ret = -ENOENT;
2371                 goto err_ddc;
2372         }
2373
2374         hdata->hdmiphy_port = hdmi_hdmiphy;
2375
2376         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2377         if (res == NULL) {
2378                 DRM_ERROR("get interrupt resource failed.\n");
2379                 ret = -ENXIO;
2380                 goto err_hdmiphy;
2381         }
2382
2383         hdata->internal_irq = res->start;
2384
2385         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2386                                 "hpd-gpio", 0, &flags);
2387
2388         if (!gpio_is_valid(hdata->hpd_gpio)) {
2389                 DRM_ERROR("failed to get hpd gpio.");
2390                 ret = -EINVAL;
2391                 goto err_hdmiphy;
2392         }
2393
2394         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2395
2396         /* create workqueue and hotplug work */
2397         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2398                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2399         if (hdata->wq == NULL) {
2400                 DRM_ERROR("Failed to create workqueue.\n");
2401                 ret = -ENOMEM;
2402                 goto err_hdmiphy;
2403         }
2404         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2405
2406         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2407                         IRQF_SHARED, "int_hdmi", hdata);
2408         if (ret) {
2409                 DRM_ERROR("request int interrupt failed.\n");
2410                 goto err_workqueue;
2411         }
2412         disable_irq(hdata->internal_irq);
2413
2414         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2415                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2416                 hdata);
2417         if (ret) {
2418                 DRM_ERROR("request ext interrupt failed.\n");
2419                 goto err_int_irq;
2420         }
2421         disable_irq(hdata->external_irq);
2422
2423         if (of_device_is_compatible(dev->of_node,
2424                 "samsung,exynos5-hdmi")) {
2425                 ret = hdmi_register_audio_device(pdev);
2426                 if (ret) {
2427                         DRM_ERROR("hdmi-audio device registering failed.\n");
2428                         goto err_ext_irq;
2429                 }
2430         }
2431
2432         hdmi_resource_poweron(hdata);
2433
2434         if (!hdmi_is_connected(hdata)) {
2435                 hdmi_resource_poweroff(hdata);
2436                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2437         }
2438
2439         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2440                         hdata);
2441
2442         return 0;
2443
2444 err_ext_irq:
2445         free_irq(hdata->external_irq, hdata);
2446 err_int_irq:
2447         free_irq(hdata->internal_irq, hdata);
2448  err_workqueue:
2449         destroy_workqueue(hdata->wq);
2450 err_hdmiphy:
2451         i2c_del_driver(&hdmiphy_driver);
2452 err_ddc:
2453         i2c_del_driver(&ddc_driver);
2454 err_iomap:
2455         iounmap(hdata->regs);
2456 err_req_region:
2457         release_mem_region(hdata->regs_res->start,
2458                         resource_size(hdata->regs_res));
2459 err_resource:
2460         hdmi_resources_cleanup(hdata);
2461 err_data:
2462         kfree(hdata);
2463         return ret;
2464 }
2465
2466 static int __devexit hdmi_remove(struct platform_device *pdev)
2467 {
2468         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2469         struct hdmi_resources *res = &hdata->res;
2470
2471         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2472
2473         hdmi_resource_poweroff(hdata);
2474
2475         hdmi_unregister_audio_device();
2476
2477         disable_irq(hdata->curr_irq);
2478         free_irq(hdata->internal_irq, hdata);
2479         free_irq(hdata->external_irq, hdata);
2480
2481         cancel_work_sync(&hdata->hotplug_work);
2482         destroy_workqueue(hdata->wq);
2483
2484         clk_disable(res->hdmi);
2485         clk_disable(res->sclk_hdmi);
2486         hdmi_resources_cleanup(hdata);
2487
2488         iounmap(hdata->regs);
2489
2490         release_mem_region(hdata->regs_res->start,
2491                         resource_size(hdata->regs_res));
2492
2493         /* hdmiphy i2c driver */
2494         i2c_del_driver(&hdmiphy_driver);
2495         /* DDC i2c driver */
2496         i2c_del_driver(&ddc_driver);
2497
2498         kfree(hdata);
2499
2500         return 0;
2501 }
2502
2503 struct platform_driver hdmi_driver = {
2504         .probe          = hdmi_probe,
2505         .remove         = __devexit_p(hdmi_remove),
2506         .driver         = {
2507 #ifdef CONFIG_ARCH_EXYNOS5
2508                 .name   = "exynos5-hdmi",
2509 #else
2510                 .name   = "exynos4-hdmi",
2511 #endif
2512                 .owner  = THIS_MODULE,
2513         },
2514 };