drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include "drmP.h"
  18 #include "drm_edid.h"
  19 #include "drm_crtc_helper.h"
  20 #include "drm_crtc.h"
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c.h>
  28 #include <linux/module.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/delay.h>
  33 #include <linux/clk.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of.h>
  37 #include <linux/of_i2c.h>
  38 #include <linux/of_gpio.h>
  39 #include <plat/gpio-cfg.h>
  40
  41 #include <drm/exynos_drm.h>
  42
  43 #include "exynos_drm_drv.h"
  44 #include "exynos_drm_display.h"
  45
  46 #include "exynos_hdmi.h"
  47
  48 #define get_hdmi_context(dev)   platform_get_drvdata(to_platform_device(dev))
  49
  50 struct hdmi_resources {
  51         struct clk                      *hdmi;
  52         struct clk                      *sclk_hdmi;
  53         struct clk                      *sclk_pixel;
  54         struct clk                      *sclk_hdmiphy;
  55         struct clk                      *hdmiphy;
  56         struct regulator_bulk_data      *regul_bulk;
  57         int                             regul_count;
  58 };
  59
  60 struct hdmi_tg_regs {
  61         u8 cmd[1];
  62         u8 h_fsz[2];
  63         u8 hact_st[2];
  64         u8 hact_sz[2];
  65         u8 v_fsz[2];
  66         u8 vsync[2];
  67         u8 vsync2[2];
  68         u8 vact_st[2];
  69         u8 vact_sz[2];
  70         u8 field_chg[2];
  71         u8 vact_st2[2];
  72         u8 vact_st3[2];
  73         u8 vact_st4[2];
  74         u8 vsync_top_hdmi[2];
  75         u8 vsync_bot_hdmi[2];
  76         u8 field_top_hdmi[2];
  77         u8 field_bot_hdmi[2];
  78         u8 tg_3d[1];
  79 };
  80
  81 struct hdmi_core_regs {
  82         u8 h_blank[2];
  83         u8 v2_blank[2];
  84         u8 v1_blank[2];
  85         u8 v_line[2];
  86         u8 h_line[2];
  87         u8 hsync_pol[1];
  88         u8 vsync_pol[1];
  89         u8 int_pro_mode[1];
  90         u8 v_blank_f0[2];
  91         u8 v_blank_f1[2];
  92         u8 h_sync_start[2];
  93         u8 h_sync_end[2];
  94         u8 v_sync_line_bef_2[2];
  95         u8 v_sync_line_bef_1[2];
  96         u8 v_sync_line_aft_2[2];
  97         u8 v_sync_line_aft_1[2];
  98         u8 v_sync_line_aft_pxl_2[2];
  99         u8 v_sync_line_aft_pxl_1[2];
 100         u8 v_blank_f2[2]; /* for 3D mode */
 101         u8 v_blank_f3[2]; /* for 3D mode */
 102         u8 v_blank_f4[2]; /* for 3D mode */
 103         u8 v_blank_f5[2]; /* for 3D mode */
 104         u8 v_sync_line_aft_3[2];
 105         u8 v_sync_line_aft_4[2];
 106         u8 v_sync_line_aft_5[2];
 107         u8 v_sync_line_aft_6[2];
 108         u8 v_sync_line_aft_pxl_3[2];
 109         u8 v_sync_line_aft_pxl_4[2];
 110         u8 v_sync_line_aft_pxl_5[2];
 111         u8 v_sync_line_aft_pxl_6[2];
 112         u8 vact_space_1[2];
 113         u8 vact_space_2[2];
 114         u8 vact_space_3[2];
 115         u8 vact_space_4[2];
 116         u8 vact_space_5[2];
 117         u8 vact_space_6[2];
 118 };
 119
 120 struct hdmi_mode_conf {
 121         int pixel_clock;
 122         struct hdmi_core_regs core;
 123         struct hdmi_tg_regs tg;
 124         u8 vic;
 125 };
 126
 127 struct hdmi_context {
 128         struct device                   *dev;
 129         struct drm_device               *drm_dev;
 130         struct fb_videomode             *default_timing;
 131         struct hdmi_mode_conf           mode_conf;
 132         unsigned int                    is_v13:1;
 133         unsigned int                    default_win;
 134         unsigned int                    default_bpp;
 135         bool                            hpd_handle;
 136         bool                            enabled;
 137         bool                            has_hdmi_sink;
 138         bool                            has_hdmi_audio;
 139         bool                            is_soc_exynos5;
 140         bool                            is_hdmi_powered_on;
 141         bool                            video_enabled;
 142
 143         struct resource                 *regs_res;
 144         void __iomem                    *regs;
 145         unsigned int                    external_irq;
 146         unsigned int                    internal_irq;
 147         unsigned int                    curr_irq;
 148         struct workqueue_struct         *wq;
 149         struct work_struct              hotplug_work;
 150
 151         struct i2c_client               *ddc_port;
 152         struct i2c_client               *hdmiphy_port;
 153         int                             hpd_gpio;
 154         /* current hdmiphy conf index */
 155         int cur_conf;
 156
 157         struct hdmi_resources           res;
 158 };
 159
 160 /* HDMI Version 1.3 */
 161 static const u8 hdmiphy_v13_conf27[32] = {
 162         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 163         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 164         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 165         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 166 };
 167
 168 static const u8 hdmiphy_v13_conf27_027[32] = {
 169         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 170         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 171         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 172         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
 173 };
 174
 175 static const u8 hdmiphy_v13_conf74_175[32] = {
 176         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 177         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 178         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 179         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
 180 };
 181
 182 static const u8 hdmiphy_v13_conf74_25[32] = {
 183         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 184         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 185         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 186         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
 187 };
 188
 189 static const u8 hdmiphy_v13_conf148_5[32] = {
 190         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 191         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 192         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 193         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
 194 };
 195
 196 struct hdmi_v13_tg_regs {
 197         u8 cmd;
 198         u8 h_fsz_l;
 199         u8 h_fsz_h;
 200         u8 hact_st_l;
 201         u8 hact_st_h;
 202         u8 hact_sz_l;
 203         u8 hact_sz_h;
 204         u8 v_fsz_l;
 205         u8 v_fsz_h;
 206         u8 vsync_l;
 207         u8 vsync_h;
 208         u8 vsync2_l;
 209         u8 vsync2_h;
 210         u8 vact_st_l;
 211         u8 vact_st_h;
 212         u8 vact_sz_l;
 213         u8 vact_sz_h;
 214         u8 field_chg_l;
 215         u8 field_chg_h;
 216         u8 vact_st2_l;
 217         u8 vact_st2_h;
 218         u8 vsync_top_hdmi_l;
 219         u8 vsync_top_hdmi_h;
 220         u8 vsync_bot_hdmi_l;
 221         u8 vsync_bot_hdmi_h;
 222         u8 field_top_hdmi_l;
 223         u8 field_top_hdmi_h;
 224         u8 field_bot_hdmi_l;
 225         u8 field_bot_hdmi_h;
 226 };
 227
 228 struct hdmi_v13_core_regs {
 229         u8 h_blank[2];
 230         u8 v_blank[3];
 231         u8 h_v_line[3];
 232         u8 vsync_pol[1];
 233         u8 int_pro_mode[1];
 234         u8 v_blank_f[3];
 235         u8 h_sync_gen[3];
 236         u8 v_sync_gen1[3];
 237         u8 v_sync_gen2[3];
 238         u8 v_sync_gen3[3];
 239 };
 240
 241 struct hdmi_v13_preset_conf {
 242         struct hdmi_v13_core_regs core;
 243         struct hdmi_v13_tg_regs tg;
 244 };
 245
 246 struct hdmi_v13_conf {
 247         int width;
 248         int height;
 249         int vrefresh;
 250         bool interlace;
 251         const u8 *hdmiphy_data;
 252         const struct hdmi_v13_preset_conf *conf;
 253 };
 254
 255 static const struct hdmi_v13_preset_conf hdmi_v13_conf_480p = {
 256         .core = {
 257                 .h_blank = {0x8a, 0x00},
 258                 .v_blank = {0x0d, 0x6a, 0x01},
 259                 .h_v_line = {0x0d, 0xa2, 0x35},
 260                 .vsync_pol = {0x01},
 261                 .int_pro_mode = {0x00},
 262                 .v_blank_f = {0x00, 0x00, 0x00},
 263                 .h_sync_gen = {0x0e, 0x30, 0x11},
 264                 .v_sync_gen1 = {0x0f, 0x90, 0x00},
 265                 /* other don't care */
 266         },
 267         .tg = {
 268                 0x00, /* cmd */
 269                 0x5a, 0x03, /* h_fsz */
 270                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 271                 0x0d, 0x02, /* v_fsz */
 272                 0x01, 0x00, 0x33, 0x02, /* vsync */
 273                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 274                 0x33, 0x02, /* field_chg */
 275                 0x49, 0x02, /* vact_st2 */
 276                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 277                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 278         },
 279 };
 280
 281 static const struct hdmi_v13_preset_conf hdmi_v13_conf_720p60 = {
 282         .core = {
 283                 .h_blank = {0x72, 0x01},
 284                 .v_blank = {0xee, 0xf2, 0x00},
 285                 .h_v_line = {0xee, 0x22, 0x67},
 286                 .vsync_pol = {0x00},
 287                 .int_pro_mode = {0x00},
 288                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 289                 .h_sync_gen = {0x6c, 0x50, 0x02},
 290                 .v_sync_gen1 = {0x0a, 0x50, 0x00},
 291                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 292                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 293                 /* other don't care */
 294         },
 295         .tg = {
 296                 0x00, /* cmd */
 297                 0x72, 0x06, /* h_fsz */
 298                 0x71, 0x01, 0x01, 0x05, /* hact */
 299                 0xee, 0x02, /* v_fsz */
 300                 0x01, 0x00, 0x33, 0x02, /* vsync */
 301                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 302                 0x33, 0x02, /* field_chg */
 303                 0x49, 0x02, /* vact_st2 */
 304                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 305                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 306         },
 307 };
 308
 309 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i50 = {
 310         .core = {
 311                 .h_blank = {0xd0, 0x02},
 312                 .v_blank = {0x32, 0xB2, 0x00},
 313                 .h_v_line = {0x65, 0x04, 0xa5},
 314                 .vsync_pol = {0x00},
 315                 .int_pro_mode = {0x01},
 316                 .v_blank_f = {0x49, 0x2A, 0x23},
 317                 .h_sync_gen = {0x0E, 0xEA, 0x08},
 318                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 319                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 320                 .v_sync_gen3 = {0x38, 0x87, 0x73},
 321                 /* other don't care */
 322         },
 323         .tg = {
 324                 0x00, /* cmd */
 325                 0x50, 0x0A, /* h_fsz */
 326                 0xCF, 0x02, 0x81, 0x07, /* hact */
 327                 0x65, 0x04, /* v_fsz */
 328                 0x01, 0x00, 0x33, 0x02, /* vsync */
 329                 0x16, 0x00, 0x1c, 0x02, /* vact */
 330                 0x33, 0x02, /* field_chg */
 331                 0x49, 0x02, /* vact_st2 */
 332                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 333                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 334         },
 335 };
 336
 337 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p50 = {
 338         .core = {
 339                 .h_blank = {0xd0, 0x02},
 340                 .v_blank = {0x65, 0x6c, 0x01},
 341                 .h_v_line = {0x65, 0x04, 0xa5},
 342                 .vsync_pol = {0x00},
 343                 .int_pro_mode = {0x00},
 344                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 345                 .h_sync_gen = {0x0e, 0xea, 0x08},
 346                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 347                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 348                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 349                 /* other don't care */
 350         },
 351         .tg = {
 352                 0x00, /* cmd */
 353                 0x50, 0x0A, /* h_fsz */
 354                 0xCF, 0x02, 0x81, 0x07, /* hact */
 355                 0x65, 0x04, /* v_fsz */
 356                 0x01, 0x00, 0x33, 0x02, /* vsync */
 357                 0x2d, 0x00, 0x38, 0x04, /* vact */
 358                 0x33, 0x02, /* field_chg */
 359                 0x48, 0x02, /* vact_st2 */
 360                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 361                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 362         },
 363 };
 364
 365 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080i60 = {
 366         .core = {
 367                 .h_blank = {0x18, 0x01},
 368                 .v_blank = {0x32, 0xB2, 0x00},
 369                 .h_v_line = {0x65, 0x84, 0x89},
 370                 .vsync_pol = {0x00},
 371                 .int_pro_mode = {0x01},
 372                 .v_blank_f = {0x49, 0x2A, 0x23},
 373                 .h_sync_gen = {0x56, 0x08, 0x02},
 374                 .v_sync_gen1 = {0x07, 0x20, 0x00},
 375                 .v_sync_gen2 = {0x39, 0x42, 0x23},
 376                 .v_sync_gen3 = {0xa4, 0x44, 0x4a},
 377                 /* other don't care */
 378         },
 379         .tg = {
 380                 0x00, /* cmd */
 381                 0x98, 0x08, /* h_fsz */
 382                 0x17, 0x01, 0x81, 0x07, /* hact */
 383                 0x65, 0x04, /* v_fsz */
 384                 0x01, 0x00, 0x33, 0x02, /* vsync */
 385                 0x16, 0x00, 0x1c, 0x02, /* vact */
 386                 0x33, 0x02, /* field_chg */
 387                 0x49, 0x02, /* vact_st2 */
 388                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 389                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 390         },
 391 };
 392
 393 static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
 394         .core = {
 395                 .h_blank = {0x18, 0x01},
 396                 .v_blank = {0x65, 0x6c, 0x01},
 397                 .h_v_line = {0x65, 0x84, 0x89},
 398                 .vsync_pol = {0x00},
 399                 .int_pro_mode = {0x00},
 400                 .v_blank_f = {0x00, 0x00, 0x00}, /* don't care */
 401                 .h_sync_gen = {0x56, 0x08, 0x02},
 402                 .v_sync_gen1 = {0x09, 0x40, 0x00},
 403                 .v_sync_gen2 = {0x01, 0x10, 0x00},
 404                 .v_sync_gen3 = {0x01, 0x10, 0x00},
 405                 /* other don't care */
 406         },
 407         .tg = {
 408                 0x00, /* cmd */
 409                 0x98, 0x08, /* h_fsz */
 410                 0x17, 0x01, 0x81, 0x07, /* hact */
 411                 0x65, 0x04, /* v_fsz */
 412                 0x01, 0x00, 0x33, 0x02, /* vsync */
 413                 0x2d, 0x00, 0x38, 0x04, /* vact */
 414                 0x33, 0x02, /* field_chg */
 415                 0x48, 0x02, /* vact_st2 */
 416                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 417                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 418         },
 419 };
 420
 421 static const struct hdmi_v13_conf hdmi_v13_confs[] = {
 422         { 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 423         { 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
 424         { 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
 425         { 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
 426         { 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
 427                                  &hdmi_v13_conf_1080p50 },
 428         { 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
 429         { 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
 430                                  &hdmi_v13_conf_1080p60 },
 431 };
 432
 433 struct hdmiphy_config {
 434         int pixel_clock;
 435         u8 conf[32];
 436 };
 437
 438 static const struct hdmiphy_config phy_configs[] = {
 439         {
 440                 .pixel_clock = 25200000,
 441                 .conf = {
 442                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 443                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 444                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 445                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 446                 },
 447         },
 448         {
 449                 .pixel_clock = 27000000,
 450                 .conf = {
 451                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 452                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 453                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 454                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 455                 },
 456         },
 457         {
 458                 .pixel_clock = 27027000,
 459                 .conf = {
 460                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 461                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 462                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 463                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
 464                 },
 465         },
 466         {
 467                 .pixel_clock = 36000000,
 468                 .conf = {
 469                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 470                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 471                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 472                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 473                 },
 474         },
 475         {
 476                 .pixel_clock = 40000000,
 477                 .conf = {
 478                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 479                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 480                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 481                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 482                 },
 483         },
 484         {
 485                 .pixel_clock = 65000000,
 486                 .conf = {
 487                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 488                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 489                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 490                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 491                 },
 492         },
 493         {
 494                 .pixel_clock = 74176000,
 495                 .conf = {
 496                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 497                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 498                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 499                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 500                 },
 501         },
 502         {
 503                 .pixel_clock = 74250000,
 504                 .conf = {
 505                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 506                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 507                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 508                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
 509                 },
 510         },
 511         {
 512                 .pixel_clock = 83500000,
 513                 .conf = {
 514                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 515                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 516                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 517                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 518                 },
 519         },
 520         {
 521                 .pixel_clock = 106500000,
 522                 .conf = {
 523                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 524                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 525                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 526                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 527                 },
 528         },
 529         {
 530                 .pixel_clock = 108000000,
 531                 .conf = {
 532                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 533                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 534                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 535                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 536                 },
 537         },
 538         {
 539                 .pixel_clock = 146250000,
 540                 .conf = {
 541                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 542                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 543                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 544                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 545                 },
 546         },
 547         {
 548                 .pixel_clock = 148500000,
 549                 .conf = {
 550                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 551                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 552                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 553                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
 554                 },
 555         },
 556 };
 557
 558 struct hdmi_infoframe {
 559         enum HDMI_PACKET_TYPE type;
 560         u8 ver;
 561         u8 len;
 562 };
 563
 564 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 565 {
 566         return readl(hdata->regs + reg_id);
 567 }
 568
 569 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 570                                  u32 reg_id, u8 value)
 571 {
 572         writeb(value, hdata->regs + reg_id);
 573 }
 574
 575 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 576                                  u32 reg_id, u32 value, u32 mask)
 577 {
 578         u32 old = readl(hdata->regs + reg_id);
 579         value = (value & mask) | (old & ~mask);
 580         writel(value, hdata->regs + reg_id);
 581 }
 582
 583 static void hdmi_cfg_hpd(struct hdmi_context *hdata, bool external)
 584 {
 585         if (external) {
 586                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(0xf));
 587                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_DOWN);
 588         } else {
 589                 s3c_gpio_cfgpin(hdata->hpd_gpio, S3C_GPIO_SFN(3));
 590                 s3c_gpio_setpull(hdata->hpd_gpio, S3C_GPIO_PULL_NONE);
 591         }
 592 }
 593
 594 static int hdmi_get_hpd(struct hdmi_context *hdata)
 595 {
 596         return gpio_get_value(hdata->hpd_gpio);
 597 }
 598
 599 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 600 {
 601 #define DUMPREG(reg_id) \
 602         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 603         readl(hdata->regs + reg_id))
 604         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 605         DUMPREG(HDMI_INTC_FLAG);
 606         DUMPREG(HDMI_INTC_CON);
 607         DUMPREG(HDMI_HPD_STATUS);
 608         DUMPREG(HDMI_V13_PHY_RSTOUT);
 609         DUMPREG(HDMI_V13_PHY_VPLL);
 610         DUMPREG(HDMI_V13_PHY_CMU);
 611         DUMPREG(HDMI_V13_CORE_RSTOUT);
 612
 613         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 614         DUMPREG(HDMI_CON_0);
 615         DUMPREG(HDMI_CON_1);
 616         DUMPREG(HDMI_CON_2);
 617         DUMPREG(HDMI_SYS_STATUS);
 618         DUMPREG(HDMI_V13_PHY_STATUS);
 619         DUMPREG(HDMI_STATUS_EN);
 620         DUMPREG(HDMI_HPD);
 621         DUMPREG(HDMI_MODE_SEL);
 622         DUMPREG(HDMI_V13_HPD_GEN);
 623         DUMPREG(HDMI_V13_DC_CONTROL);
 624         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 625
 626         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 627         DUMPREG(HDMI_H_BLANK_0);
 628         DUMPREG(HDMI_H_BLANK_1);
 629         DUMPREG(HDMI_V13_V_BLANK_0);
 630         DUMPREG(HDMI_V13_V_BLANK_1);
 631         DUMPREG(HDMI_V13_V_BLANK_2);
 632         DUMPREG(HDMI_V13_H_V_LINE_0);
 633         DUMPREG(HDMI_V13_H_V_LINE_1);
 634         DUMPREG(HDMI_V13_H_V_LINE_2);
 635         DUMPREG(HDMI_VSYNC_POL);
 636         DUMPREG(HDMI_INT_PRO_MODE);
 637         DUMPREG(HDMI_V13_V_BLANK_F_0);
 638         DUMPREG(HDMI_V13_V_BLANK_F_1);
 639         DUMPREG(HDMI_V13_V_BLANK_F_2);
 640         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 641         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 642         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 643         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 644         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 645         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 646         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 647         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 648         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 649         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 650         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 651         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 652
 653         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 654         DUMPREG(HDMI_TG_CMD);
 655         DUMPREG(HDMI_TG_H_FSZ_L);
 656         DUMPREG(HDMI_TG_H_FSZ_H);
 657         DUMPREG(HDMI_TG_HACT_ST_L);
 658         DUMPREG(HDMI_TG_HACT_ST_H);
 659         DUMPREG(HDMI_TG_HACT_SZ_L);
 660         DUMPREG(HDMI_TG_HACT_SZ_H);
 661         DUMPREG(HDMI_TG_V_FSZ_L);
 662         DUMPREG(HDMI_TG_V_FSZ_H);
 663         DUMPREG(HDMI_TG_VSYNC_L);
 664         DUMPREG(HDMI_TG_VSYNC_H);
 665         DUMPREG(HDMI_TG_VSYNC2_L);
 666         DUMPREG(HDMI_TG_VSYNC2_H);
 667         DUMPREG(HDMI_TG_VACT_ST_L);
 668         DUMPREG(HDMI_TG_VACT_ST_H);
 669         DUMPREG(HDMI_TG_VACT_SZ_L);
 670         DUMPREG(HDMI_TG_VACT_SZ_H);
 671         DUMPREG(HDMI_TG_FIELD_CHG_L);
 672         DUMPREG(HDMI_TG_FIELD_CHG_H);
 673         DUMPREG(HDMI_TG_VACT_ST2_L);
 674         DUMPREG(HDMI_TG_VACT_ST2_H);
 675         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 676         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 677         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 678         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 679         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 680         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 681         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 682         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 683 #undef DUMPREG
 684 }
 685
 686 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 687 {
 688         int i;
 689
 690 #define DUMPREG(reg_id) \
 691         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 692         readl(hdata->regs + reg_id))
 693
 694         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 695         DUMPREG(HDMI_INTC_CON);
 696         DUMPREG(HDMI_INTC_FLAG);
 697         DUMPREG(HDMI_HPD_STATUS);
 698         DUMPREG(HDMI_INTC_CON_1);
 699         DUMPREG(HDMI_INTC_FLAG_1);
 700         DUMPREG(HDMI_PHY_STATUS_0);
 701         DUMPREG(HDMI_PHY_STATUS_PLL);
 702         DUMPREG(HDMI_PHY_CON_0);
 703         DUMPREG(HDMI_PHY_RSTOUT);
 704         DUMPREG(HDMI_PHY_VPLL);
 705         DUMPREG(HDMI_PHY_CMU);
 706         DUMPREG(HDMI_CORE_RSTOUT);
 707
 708         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 709         DUMPREG(HDMI_CON_0);
 710         DUMPREG(HDMI_CON_1);
 711         DUMPREG(HDMI_CON_2);
 712         DUMPREG(HDMI_SYS_STATUS);
 713         DUMPREG(HDMI_PHY_STATUS_0);
 714         DUMPREG(HDMI_STATUS_EN);
 715         DUMPREG(HDMI_HPD);
 716         DUMPREG(HDMI_MODE_SEL);
 717         DUMPREG(HDMI_ENC_EN);
 718         DUMPREG(HDMI_DC_CONTROL);
 719         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 720
 721         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 722         DUMPREG(HDMI_H_BLANK_0);
 723         DUMPREG(HDMI_H_BLANK_1);
 724         DUMPREG(HDMI_V2_BLANK_0);
 725         DUMPREG(HDMI_V2_BLANK_1);
 726         DUMPREG(HDMI_V1_BLANK_0);
 727         DUMPREG(HDMI_V1_BLANK_1);
 728         DUMPREG(HDMI_V_LINE_0);
 729         DUMPREG(HDMI_V_LINE_1);
 730         DUMPREG(HDMI_H_LINE_0);
 731         DUMPREG(HDMI_H_LINE_1);
 732         DUMPREG(HDMI_HSYNC_POL);
 733
 734         DUMPREG(HDMI_VSYNC_POL);
 735         DUMPREG(HDMI_INT_PRO_MODE);
 736         DUMPREG(HDMI_V_BLANK_F0_0);
 737         DUMPREG(HDMI_V_BLANK_F0_1);
 738         DUMPREG(HDMI_V_BLANK_F1_0);
 739         DUMPREG(HDMI_V_BLANK_F1_1);
 740
 741         DUMPREG(HDMI_H_SYNC_START_0);
 742         DUMPREG(HDMI_H_SYNC_START_1);
 743         DUMPREG(HDMI_H_SYNC_END_0);
 744         DUMPREG(HDMI_H_SYNC_END_1);
 745
 746         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 747         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 748         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 749         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 750
 751         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 752         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 753         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 754         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 755
 756         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 757         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 758         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 759         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 760
 761         DUMPREG(HDMI_V_BLANK_F2_0);
 762         DUMPREG(HDMI_V_BLANK_F2_1);
 763         DUMPREG(HDMI_V_BLANK_F3_0);
 764         DUMPREG(HDMI_V_BLANK_F3_1);
 765         DUMPREG(HDMI_V_BLANK_F4_0);
 766         DUMPREG(HDMI_V_BLANK_F4_1);
 767         DUMPREG(HDMI_V_BLANK_F5_0);
 768         DUMPREG(HDMI_V_BLANK_F5_1);
 769
 770         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 771         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 772         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 773         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 774         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 775         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 776         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 777         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 778
 779         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 780         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 781         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 782         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 783         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 784         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 785         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 786         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 787
 788         DUMPREG(HDMI_VACT_SPACE_1_0);
 789         DUMPREG(HDMI_VACT_SPACE_1_1);
 790         DUMPREG(HDMI_VACT_SPACE_2_0);
 791         DUMPREG(HDMI_VACT_SPACE_2_1);
 792         DUMPREG(HDMI_VACT_SPACE_3_0);
 793         DUMPREG(HDMI_VACT_SPACE_3_1);
 794         DUMPREG(HDMI_VACT_SPACE_4_0);
 795         DUMPREG(HDMI_VACT_SPACE_4_1);
 796         DUMPREG(HDMI_VACT_SPACE_5_0);
 797         DUMPREG(HDMI_VACT_SPACE_5_1);
 798         DUMPREG(HDMI_VACT_SPACE_6_0);
 799         DUMPREG(HDMI_VACT_SPACE_6_1);
 800
 801         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 802         DUMPREG(HDMI_TG_CMD);
 803         DUMPREG(HDMI_TG_H_FSZ_L);
 804         DUMPREG(HDMI_TG_H_FSZ_H);
 805         DUMPREG(HDMI_TG_HACT_ST_L);
 806         DUMPREG(HDMI_TG_HACT_ST_H);
 807         DUMPREG(HDMI_TG_HACT_SZ_L);
 808         DUMPREG(HDMI_TG_HACT_SZ_H);
 809         DUMPREG(HDMI_TG_V_FSZ_L);
 810         DUMPREG(HDMI_TG_V_FSZ_H);
 811         DUMPREG(HDMI_TG_VSYNC_L);
 812         DUMPREG(HDMI_TG_VSYNC_H);
 813         DUMPREG(HDMI_TG_VSYNC2_L);
 814         DUMPREG(HDMI_TG_VSYNC2_H);
 815         DUMPREG(HDMI_TG_VACT_ST_L);
 816         DUMPREG(HDMI_TG_VACT_ST_H);
 817         DUMPREG(HDMI_TG_VACT_SZ_L);
 818         DUMPREG(HDMI_TG_VACT_SZ_H);
 819         DUMPREG(HDMI_TG_FIELD_CHG_L);
 820         DUMPREG(HDMI_TG_FIELD_CHG_H);
 821         DUMPREG(HDMI_TG_VACT_ST2_L);
 822         DUMPREG(HDMI_TG_VACT_ST2_H);
 823         DUMPREG(HDMI_TG_VACT_ST3_L);
 824         DUMPREG(HDMI_TG_VACT_ST3_H);
 825         DUMPREG(HDMI_TG_VACT_ST4_L);
 826         DUMPREG(HDMI_TG_VACT_ST4_H);
 827         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 828         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 829         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 830         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 831         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 832         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 833         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 834         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 835         DUMPREG(HDMI_TG_3D);
 836
 837         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 838         DUMPREG(HDMI_AVI_CON);
 839         DUMPREG(HDMI_AVI_HEADER0);
 840         DUMPREG(HDMI_AVI_HEADER1);
 841         DUMPREG(HDMI_AVI_HEADER2);
 842         DUMPREG(HDMI_AVI_CHECK_SUM);
 843         DUMPREG(HDMI_VSI_CON);
 844         DUMPREG(HDMI_VSI_HEADER0);
 845         DUMPREG(HDMI_VSI_HEADER1);
 846         DUMPREG(HDMI_VSI_HEADER2);
 847         for (i = 0; i < 7; ++i)
 848                 DUMPREG(HDMI_VSI_DATA(i));
 849
 850 #undef DUMPREG
 851 }
 852
 853 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 854 {
 855         if (hdata->is_v13)
 856                 hdmi_v13_regs_dump(hdata, prefix);
 857         else
 858                 hdmi_v14_regs_dump(hdata, prefix);
 859 }
 860
 861 static int hdmi_v13_conf_index(struct drm_display_mode *mode)
 862 {
 863         int i;
 864
 865         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 866                 if (hdmi_v13_confs[i].width == mode->hdisplay &&
 867                                 hdmi_v13_confs[i].height == mode->vdisplay &&
 868                                 hdmi_v13_confs[i].vrefresh == mode->vrefresh &&
 869                                 hdmi_v13_confs[i].interlace ==
 870                                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ?
 871                                  true : false))
 872                         return i;
 873
 874         return -EINVAL;
 875 }
 876
 877 static bool hdmi_is_connected(void *ctx)
 878 {
 879         struct hdmi_context *hdata = ctx;
 880         if (hdata->is_hdmi_powered_on) {
 881                 if (!hdmi_reg_read(hdata, HDMI_HPD_STATUS)) {
 882                         DRM_DEBUG_KMS("hdmi is not connected\n");
 883                         return false;
 884                 }
 885         } else if (!hdmi_get_hpd(hdata)) {
 886                         DRM_DEBUG_KMS("hdmi is not connected\n");
 887                         return false;
 888         }
 889
 890         return true;
 891 }
 892
 893 static struct edid *hdmi_get_edid(void *ctx, struct drm_connector *connector)
 894 {
 895         struct hdmi_context *hdata = ctx;
 896         struct edid *edid;
 897
 898         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 899
 900         if (!hdata->ddc_port)
 901                 return ERR_PTR(-ENODEV);
 902
 903         edid = drm_get_edid(connector, hdata->ddc_port->adapter);
 904         if (!edid)
 905                 return ERR_PTR(-ENODEV);
 906
 907         /*
 908          * TODO : Need to call this in exynos_drm_connector.c, do a drm_get_edid
 909          * to get the edid and then call drm_detect_hdmi_monitor.
 910          */
 911         hdata->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
 912         hdata->has_hdmi_audio = drm_detect_monitor_audio(edid);
 913         DRM_DEBUG_KMS("%s monitor\n", hdata->has_hdmi_sink ? "hdmi" : "dvi");
 914
 915         return edid;
 916 }
 917
 918 static int hdmi_v13_check_timing(struct fb_videomode *check_timing)
 919 {
 920         int i;
 921
 922         DRM_DEBUG_KMS("valid mode : xres=%d, yres=%d, refresh=%d, intl=%d\n",
 923                         check_timing->xres, check_timing->yres,
 924                         check_timing->refresh, (check_timing->vmode &
 925                         FB_VMODE_INTERLACED) ? true : false);
 926
 927         for (i = 0; i < ARRAY_SIZE(hdmi_v13_confs); ++i)
 928                 if (hdmi_v13_confs[i].width == check_timing->xres &&
 929                         hdmi_v13_confs[i].height == check_timing->yres &&
 930                         hdmi_v13_confs[i].vrefresh == check_timing->refresh &&
 931                         hdmi_v13_confs[i].interlace ==
 932                         ((check_timing->vmode & FB_VMODE_INTERLACED) ?
 933                          true : false))
 934                                 return 0;
 935
 936         /* TODO */
 937
 938         return -EINVAL;
 939 }
 940
 941 static int find_hdmiphy_conf(int pixel_clock)
 942 {
 943         int i;
 944
 945         for (i = 0; i < ARRAY_SIZE(phy_configs); i++) {
 946                 if (phy_configs[i].pixel_clock == pixel_clock)
 947                         return i;
 948         }
 949         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
 950         return -EINVAL;
 951 }
 952
 953 static int hdmi_v14_check_timing(struct fb_videomode *mode)
 954 {
 955         int ret;
 956         enum exynos_mixer_mode_type mode_type;
 957
 958         /* Make sure the mixer can generate this mode */
 959         mode_type = exynos_mixer_get_mode_type(mode->xres, mode->yres);
 960         if (mode_type == EXYNOS_MIXER_MODE_INVALID)
 961                 return -EINVAL;
 962
 963         ret = find_hdmiphy_conf(mode->pixclock);
 964         return ret < 0 ? ret : 0;
 965 }
 966
 967 static u8 hdmi_chksum(struct hdmi_context *hdata,
 968                         u32 start, u8 len, u32 hdr_sum)
 969 {
 970         int i;
 971         /* hdr_sum : header0 + header1 + header2
 972         * start : start address of packet byte1
 973         * len : packet bytes - 1 */
 974         for (i = 0; i < len; ++i)
 975                 hdr_sum += hdmi_reg_read(hdata, start + i * 4);
 976
 977         return (u8)(0x100 - (hdr_sum & 0xff));
 978 }
 979
 980 void hdmi_reg_infoframe(struct hdmi_context *hdata,
 981                         struct hdmi_infoframe *infoframe)
 982 {
 983         u32 hdr_sum;
 984         u8 chksum;
 985         u32 aspect_ratio;
 986         u32 mod;
 987
 988         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 989         mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
 990         if (!hdata->has_hdmi_sink) {
 991                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
 992                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
 993                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
 994                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
 995                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
 996                 return;
 997         }
 998
 999         switch (infoframe->type) {
1000
1001         case HDMI_PACKET_TYPE_AVI:
1002                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1003                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
1004                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
1005                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
1006                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1007                 /* Output format zero hardcoded ,RGB YBCR selection */
1008                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1009                         AVI_ACTIVE_FORMAT_VALID | AVI_UNDERSCANNED_DISPLAY_VALID);
1010
1011                 aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
1012
1013                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
1014                                 AVI_SAME_AS_PIC_ASPECT_RATIO);
1015                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->mode_conf.vic);
1016
1017                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1018                                         infoframe->len, hdr_sum);
1019                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1020                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1021                 break;
1022
1023         case HDMI_PACKET_TYPE_AUI:
1024                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1025                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
1026                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
1027                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
1028                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
1029                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1030                                         infoframe->len, hdr_sum);
1031                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1032                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1033                 break;
1034
1035         default:
1036                 break;
1037         }
1038 }
1039
1040 static int hdmi_check_timing(void *ctx, void *timing)
1041 {
1042         struct hdmi_context *hdata = ctx;
1043         struct fb_videomode *check_timing = timing;
1044
1045         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1046
1047         DRM_DEBUG_KMS("[%d]x[%d] [%d]Hz [%x]\n", check_timing->xres,
1048                         check_timing->yres, check_timing->refresh,
1049                         check_timing->vmode);
1050
1051         if (hdata->is_v13)
1052                 return hdmi_v13_check_timing(check_timing);
1053         else
1054                 return hdmi_v14_check_timing(check_timing);
1055 }
1056
1057 static void hdmi_set_acr(u32 freq, u8 *acr)
1058 {
1059         u32 n, cts;
1060
1061         switch (freq) {
1062         case 32000:
1063                 n = 4096;
1064                 cts = 27000;
1065                 break;
1066         case 44100:
1067                 n = 6272;
1068                 cts = 30000;
1069                 break;
1070         case 88200:
1071                 n = 12544;
1072                 cts = 30000;
1073                 break;
1074         case 176400:
1075                 n = 25088;
1076                 cts = 30000;
1077                 break;
1078         case 48000:
1079                 n = 6144;
1080                 cts = 27000;
1081                 break;
1082         case 96000:
1083                 n = 12288;
1084                 cts = 27000;
1085                 break;
1086         case 192000:
1087                 n = 24576;
1088                 cts = 27000;
1089                 break;
1090         default:
1091                 n = 0;
1092                 cts = 0;
1093                 break;
1094         }
1095
1096         acr[1] = cts >> 16;
1097         acr[2] = cts >> 8 & 0xff;
1098         acr[3] = cts & 0xff;
1099
1100         acr[4] = n >> 16;
1101         acr[5] = n >> 8 & 0xff;
1102         acr[6] = n & 0xff;
1103 }
1104
1105 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1106 {
1107         hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1108         hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1109         hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1110         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1111         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1112         hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1113         hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1114         hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1115         hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1116
1117         if (hdata->is_v13)
1118                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1119         else
1120                 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1121 }
1122
1123 static void hdmi_audio_init(struct hdmi_context *hdata)
1124 {
1125         u32 sample_rate, bits_per_sample, frame_size_code;
1126         u32 data_num, bit_ch, sample_frq;
1127         u32 val;
1128         u8 acr[7];
1129
1130         sample_rate = 44100;
1131         bits_per_sample = 16;
1132         frame_size_code = 0;
1133
1134         switch (bits_per_sample) {
1135         case 20:
1136                 data_num = 2;
1137                 bit_ch  = 1;
1138                 break;
1139         case 24:
1140                 data_num = 3;
1141                 bit_ch  = 1;
1142                 break;
1143         default:
1144                 data_num = 1;
1145                 bit_ch  = 0;
1146                 break;
1147         }
1148
1149         hdmi_set_acr(sample_rate, acr);
1150         hdmi_reg_acr(hdata, acr);
1151
1152         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1153                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1154                                 | HDMI_I2S_MUX_ENABLE);
1155
1156         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1157                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1158
1159         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1160
1161         sample_frq = (sample_rate == 44100) ? 0 :
1162                         (sample_rate == 48000) ? 2 :
1163                         (sample_rate == 32000) ? 3 :
1164                         (sample_rate == 96000) ? 0xa : 0x0;
1165
1166         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1167         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1168
1169         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1170         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1171
1172         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1173         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1174                         | HDMI_I2S_SEL_LRCK(6));
1175         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1176                         | HDMI_I2S_SEL_SDATA2(4));
1177         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1178                         | HDMI_I2S_SEL_SDATA2(2));
1179         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1180
1181         /* I2S_CON_1 & 2 */
1182         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1183                         | HDMI_I2S_L_CH_LOW_POL);
1184         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1185                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1186                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1187                         | HDMI_I2S_BASIC_FORMAT);
1188
1189         /* Configure register related to CUV information */
1190         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1191                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1192                         | HDMI_I2S_COPYRIGHT
1193                         | HDMI_I2S_LINEAR_PCM
1194                         | HDMI_I2S_CONSUMER_FORMAT);
1195         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1196         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1197         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1198                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1199         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1200                         HDMI_I2S_ORG_SMP_FREQ_44_1
1201                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1202                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1203
1204         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1205 }
1206
1207 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1208 {
1209         if (!hdata->has_hdmi_audio)
1210                 return;
1211
1212         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1213         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1214                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1215 }
1216
1217 static void hdmi_conf_reset(struct hdmi_context *hdata)
1218 {
1219         u32 reg;
1220
1221         /* disable hpd handle for drm */
1222         hdata->hpd_handle = false;
1223
1224         if (hdata->is_v13)
1225                 reg = HDMI_V13_CORE_RSTOUT;
1226         else
1227                 reg = HDMI_CORE_RSTOUT;
1228
1229         /* resetting HDMI core */
1230         hdmi_reg_writemask(hdata, reg,  0, HDMI_CORE_SW_RSTOUT);
1231         mdelay(10);
1232         hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1233         mdelay(10);
1234
1235         /* enable hpd handle for drm */
1236         hdata->hpd_handle = true;
1237 }
1238
1239 static void hdmi_enable_video(struct hdmi_context *hdata)
1240 {
1241         if (hdata->is_v13)
1242                 return;
1243
1244         hdata->video_enabled = true;
1245         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1246 }
1247
1248 static void hdmi_disable_video(struct hdmi_context *hdata)
1249 {
1250         if (hdata->is_v13)
1251                 return;
1252
1253         /* Set the blue screen color to black */
1254         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_0, 0);
1255         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_R_1, 0);
1256         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_0, 0);
1257         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_G_1, 0);
1258         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_0, 0);
1259         hdmi_reg_writeb(hdata, HDMI_BLUE_SCREEN_B_1, 0);
1260
1261         /* Enable the "blue screen", which effectively disconnects the mixer */
1262         hdata->video_enabled = false;
1263         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
1264 }
1265
1266 static void hdmi_conf_init(struct hdmi_context *hdata)
1267 {
1268         struct hdmi_infoframe infoframe;
1269         /* disable hpd handle for drm */
1270         hdata->hpd_handle = false;
1271
1272         /* enable HPD interrupts */
1273         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1274                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1275         mdelay(10);
1276         hdmi_reg_writemask(hdata, HDMI_INTC_CON, ~0, HDMI_INTC_EN_GLOBAL |
1277                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1278
1279         /* choose HDMI mode */
1280         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1281                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1282
1283         if (hdata->video_enabled)
1284                 hdmi_enable_video(hdata);
1285         else
1286                 hdmi_disable_video(hdata);
1287
1288         if (!hdata->has_hdmi_sink) {
1289                 /* choose DVI mode */
1290                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1291                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1292                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1293                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1294         }
1295
1296         if (hdata->is_v13) {
1297                 /* choose bluescreen (fecal) color */
1298                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1299                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1300                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1301
1302                 /* enable AVI packet every vsync, fixes purple line problem */
1303                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1304                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1305                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1306                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1307
1308                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1309                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1310                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1311         } else {
1312                 /* enable AVI packet every vsync, fixes purple line problem */
1313                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1314
1315                 infoframe.type = HDMI_PACKET_TYPE_AVI;
1316                 infoframe.ver = HDMI_AVI_VERSION;
1317                 infoframe.len = HDMI_AVI_LENGTH;
1318                 hdmi_reg_infoframe(hdata, &infoframe);
1319
1320                 infoframe.type = HDMI_PACKET_TYPE_AUI;
1321                 infoframe.ver = HDMI_AUI_VERSION;
1322                 infoframe.len = HDMI_AUI_LENGTH;
1323                 hdmi_reg_infoframe(hdata, &infoframe);
1324
1325         }
1326
1327         /* enable hpd handle for drm */
1328         hdata->hpd_handle = true;
1329 }
1330
1331 static void hdmi_v13_timing_apply(struct hdmi_context *hdata)
1332 {
1333         const struct hdmi_v13_preset_conf *conf =
1334                 hdmi_v13_confs[hdata->cur_conf].conf;
1335         const struct hdmi_v13_core_regs *core = &conf->core;
1336         const struct hdmi_v13_tg_regs *tg = &conf->tg;
1337         int tries;
1338
1339         /* setting core registers */
1340         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1341         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1342         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1343         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1344         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1345         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1346         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1347         hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1348         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1349         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1350         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1351         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1352         hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1353         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1354         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1355         hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1356         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1357         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1358         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1359         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1360         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1361         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1362         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1363         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1364         hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1365         /* Timing generator registers */
1366         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
1367         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
1368         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st_l);
1369         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st_h);
1370         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
1371         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
1372         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
1373         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
1374         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync_l);
1375         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync_h);
1376         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2_l);
1377         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2_h);
1378         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st_l);
1379         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st_h);
1380         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
1381         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
1382         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
1383         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
1384         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
1385         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
1386         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
1387         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
1388         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
1389         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
1390         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
1391         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
1392         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
1393         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
1394
1395         /* waiting for HDMIPHY's PLL to get to steady state */
1396         for (tries = 100; tries; --tries) {
1397                 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1398                 if (val & HDMI_PHY_STATUS_READY)
1399                         break;
1400                 mdelay(1);
1401         }
1402         /* steady state not achieved */
1403         if (tries == 0) {
1404                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1405                 hdmi_regs_dump(hdata, "timing apply");
1406         }
1407
1408         clk_disable(hdata->res.sclk_hdmi);
1409         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1410         clk_enable(hdata->res.sclk_hdmi);
1411
1412         /* enable HDMI and timing generator */
1413         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1414         if (core->int_pro_mode[0])
1415                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1416                                 HDMI_FIELD_EN);
1417         else
1418                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1419 }
1420
1421 static void hdmi_v14_timing_apply(struct hdmi_context *hdata)
1422 {
1423         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1424         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1425         int tries;
1426
1427         hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1428         hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1429         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1430         hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1431         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1432         hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1433         hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1434         hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1435         hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1436         hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1437         hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1438         hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1439         hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1440         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1441         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1442         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1443         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1444         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1445         hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1446         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1447         hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1448         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1449                         core->v_sync_line_bef_2[0]);
1450         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1451                         core->v_sync_line_bef_2[1]);
1452         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1453                         core->v_sync_line_bef_1[0]);
1454         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1455                         core->v_sync_line_bef_1[1]);
1456         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1457                         core->v_sync_line_aft_2[0]);
1458         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1459                         core->v_sync_line_aft_2[1]);
1460         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1461                         core->v_sync_line_aft_1[0]);
1462         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1463                         core->v_sync_line_aft_1[1]);
1464         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1465                         core->v_sync_line_aft_pxl_2[0]);
1466         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1467                         core->v_sync_line_aft_pxl_2[1]);
1468         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1469                         core->v_sync_line_aft_pxl_1[0]);
1470         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1471                         core->v_sync_line_aft_pxl_1[1]);
1472         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1473         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1474         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1475         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1476         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1477         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1478         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1479         hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1480         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1481                         core->v_sync_line_aft_3[0]);
1482         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1483                         core->v_sync_line_aft_3[1]);
1484         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1485                         core->v_sync_line_aft_4[0]);
1486         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1487                         core->v_sync_line_aft_4[1]);
1488         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1489                         core->v_sync_line_aft_5[0]);
1490         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1491                         core->v_sync_line_aft_5[1]);
1492         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1493                         core->v_sync_line_aft_6[0]);
1494         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1495                         core->v_sync_line_aft_6[1]);
1496         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1497                         core->v_sync_line_aft_pxl_3[0]);
1498         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1499                         core->v_sync_line_aft_pxl_3[1]);
1500         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1501                         core->v_sync_line_aft_pxl_4[0]);
1502         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1503                         core->v_sync_line_aft_pxl_4[1]);
1504         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1505                         core->v_sync_line_aft_pxl_5[0]);
1506         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1507                         core->v_sync_line_aft_pxl_5[1]);
1508         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1509                         core->v_sync_line_aft_pxl_6[0]);
1510         hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1511                         core->v_sync_line_aft_pxl_6[1]);
1512         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1513         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1514         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1515         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1516         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1517         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1518         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1519         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1520         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1521         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1522         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1523         hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1524
1525         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1526         hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1527         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1528         hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1529         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1530         hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1531         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1532         hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1533         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1534         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1535         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1536         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1537         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1538         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1539         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1540         hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1541         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1542         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1543         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1544         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1545         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1546         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1547         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1548         hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1549         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1550         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1551         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1552         hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1553         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1554         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1555         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1556         hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1557         hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1558
1559         /* waiting for HDMIPHY's PLL to get to steady state */
1560         for (tries = 100; tries; --tries) {
1561                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1562                 if (val & HDMI_PHY_STATUS_READY)
1563                         break;
1564                 mdelay(1);
1565         }
1566         /* steady state not achieved */
1567         if (tries == 0) {
1568                 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1569                 hdmi_regs_dump(hdata, "timing apply");
1570         }
1571
1572         clk_disable(hdata->res.sclk_hdmi);
1573         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_hdmiphy);
1574         clk_enable(hdata->res.sclk_hdmi);
1575
1576         /* enable HDMI and timing generator */
1577         hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1578         if (core->int_pro_mode[0])
1579                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1580                                 HDMI_FIELD_EN);
1581         else
1582                 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1583 }
1584
1585 static void hdmi_timing_apply(struct hdmi_context *hdata)
1586 {
1587         if (hdata->is_v13)
1588                 hdmi_v13_timing_apply(hdata);
1589         else
1590                 hdmi_v14_timing_apply(hdata);
1591 }
1592
1593 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1594 {
1595         u8 buffer[2];
1596         u32 reg;
1597
1598         clk_disable(hdata->res.sclk_hdmi);
1599         clk_set_parent(hdata->res.sclk_hdmi, hdata->res.sclk_pixel);
1600         clk_enable(hdata->res.sclk_hdmi);
1601
1602         /* operation mode */
1603         buffer[0] = 0x1f;
1604         buffer[1] = 0x00;
1605
1606         if (hdata->hdmiphy_port)
1607                 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1608
1609         if (hdata->is_v13)
1610                 reg = HDMI_V13_PHY_RSTOUT;
1611         else
1612                 reg = HDMI_PHY_RSTOUT;
1613
1614         /* reset hdmiphy */
1615         hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1616         mdelay(10);
1617         hdmi_reg_writemask(hdata, reg,  0, HDMI_PHY_SW_RSTOUT);
1618         mdelay(10);
1619 }
1620
1621 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1622 {
1623         const u8 *hdmiphy_data;
1624         u8 buffer[32];
1625         u8 operation[2];
1626         u8 read_buffer[32] = {0, };
1627         int ret;
1628         int i;
1629
1630         if (!hdata->hdmiphy_port) {
1631                 DRM_ERROR("hdmiphy is not attached\n");
1632                 return;
1633         }
1634
1635         /* pixel clock */
1636         if (hdata->is_v13) {
1637                 hdmiphy_data = hdmi_v13_confs[hdata->cur_conf].hdmiphy_data;
1638         } else {
1639                 i = find_hdmiphy_conf(hdata->mode_conf.pixel_clock);
1640                 hdmiphy_data = phy_configs[i].conf;
1641         }
1642
1643         memcpy(buffer, hdmiphy_data, 32);
1644         ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1645         if (ret != 32) {
1646                 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1647                 return;
1648         }
1649
1650         mdelay(10);
1651
1652         /* operation mode */
1653         operation[0] = 0x1f;
1654         operation[1] = 0x80;
1655
1656         ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1657         if (ret != 2) {
1658                 DRM_ERROR("failed to enable hdmiphy\n");
1659                 return;
1660         }
1661
1662         ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1663         if (ret < 0) {
1664                 DRM_ERROR("failed to read hdmiphy config\n");
1665                 return;
1666         }
1667
1668         for (i = 0; i < ret; i++)
1669                 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1670                         "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1671 }
1672
1673 static void hdmi_conf_apply(struct hdmi_context *hdata)
1674 {
1675         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1676
1677         hdmiphy_conf_reset(hdata);
1678         hdmiphy_conf_apply(hdata);
1679
1680         hdmi_conf_reset(hdata);
1681         hdmi_conf_init(hdata);
1682         if (!hdata->is_soc_exynos5)
1683                 hdmi_audio_init(hdata);
1684
1685         /* setting core registers */
1686         hdmi_timing_apply(hdata);
1687         if (!hdata->is_soc_exynos5)
1688                 hdmi_audio_control(hdata, true);
1689
1690         hdmi_regs_dump(hdata, "start");
1691 }
1692
1693 static void hdmi_mode_copy(struct drm_display_mode *dst,
1694         struct drm_display_mode *src)
1695 {
1696         struct drm_mode_object base;
1697
1698         /* following information should be preserved,
1699          * required for releasing the drm_display_mode node,
1700          * duplicated to recieve adjustment info. */
1701
1702         base.id = dst->base.id;
1703         base.type = dst->base.type;
1704
1705         memcpy(dst, src, sizeof(struct drm_display_mode));
1706
1707         dst->base.id = base.id;
1708         dst->base.type = base.type;
1709 }
1710
1711 static void hdmi_mode_fixup(void *ctx, struct drm_connector *connector,
1712                                 struct drm_display_mode *mode,
1713                                 struct drm_display_mode *adjusted_mode)
1714 {
1715         struct drm_display_mode *m;
1716         struct hdmi_context *hdata = ctx;
1717         int index;
1718
1719         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1720
1721         drm_mode_set_crtcinfo(adjusted_mode, 0);
1722
1723         if (hdata->is_v13)
1724                 index = hdmi_v13_conf_index(adjusted_mode);
1725         else
1726                 index = find_hdmiphy_conf(adjusted_mode->clock * 1000);
1727
1728         /* just return if user desired mode exists. */
1729         if (index >= 0)
1730                 return;
1731
1732         /*
1733          * otherwise, find the most suitable mode among modes and change it
1734          * to adjusted_mode.
1735          */
1736         list_for_each_entry(m, &connector->modes, head) {
1737                 if (hdata->is_v13)
1738                         index = hdmi_v13_conf_index(m);
1739                 else
1740                         index = find_hdmiphy_conf(m->clock * 1000);
1741
1742                 if (index >= 0) {
1743                         DRM_INFO("desired mode doesn't exist so\n");
1744                         DRM_INFO("use the most suitable mode among modes.\n");
1745                         hdmi_mode_copy(adjusted_mode, m);
1746                         break;
1747                 }
1748         }
1749 }
1750
1751 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1752 {
1753         int i;
1754         BUG_ON(num_bytes > 4);
1755         for (i = 0; i < num_bytes; i++)
1756                 reg_pair[i] = (value >> (8 * i)) & 0xff;
1757 }
1758
1759 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1760                         struct drm_display_mode *m)
1761 {
1762         struct hdmi_core_regs *core = &hdata->mode_conf.core;
1763         struct hdmi_tg_regs *tg = &hdata->mode_conf.tg;
1764
1765         hdata->mode_conf.vic = drm_match_cea_mode(m);
1766
1767         hdata->mode_conf.pixel_clock = m->clock * 1000;
1768         hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1769         hdmi_set_reg(core->v_line, 2, m->vtotal);
1770         hdmi_set_reg(core->h_line, 2, m->htotal);
1771         hdmi_set_reg(core->hsync_pol, 1,
1772                         (m->flags & DRM_MODE_FLAG_NHSYNC)  ? 1 : 0);
1773         hdmi_set_reg(core->vsync_pol, 1,
1774                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1775         hdmi_set_reg(core->int_pro_mode, 1,
1776                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1777
1778         /*
1779          * Quirk requirement for exynos 5 HDMI IP design,
1780          * 2 pixels less than the actual calculation for hsync_start
1781          * and end.
1782          */
1783
1784         /* Following values & calculations differ for different type of modes */
1785         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1786                 /* Interlaced Mode */
1787                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1788                         (m->vsync_end - m->vdisplay) / 2);
1789                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1790                         (m->vsync_start - m->vdisplay) / 2);
1791                 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1792                 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1793                 hdmi_set_reg(core->v_blank_f0, 2,
1794                         (m->vtotal + ((m->vsync_end - m->vsync_start) * 4) + 5) / 2);
1795                 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1796                 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1797                 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1798                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1799                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1800                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1801                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1802                 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1803                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1804                 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1805                 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1806                 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1807         } else {
1808                 /* Progressive Mode */
1809                 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1810                         m->vsync_end - m->vdisplay);
1811                 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1812                         m->vsync_start - m->vdisplay);
1813                 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1814                 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1815                 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1816                 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1817                 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1818                 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1819                 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1820                 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1821                 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1822                 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1823                 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1824                 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1825                 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1826         }
1827
1828         /* Following values & calculations are same irrespective of mode type */
1829         hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1830         hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1831         hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1832         hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1833         hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1834         hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1835         hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1836         hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1837         hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1838         hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1839         hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1840         hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1841         hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1842         hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1843         hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1844         hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1845         hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1846         hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1847         hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1848         hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1849
1850         /* Timing generator registers */
1851         hdmi_set_reg(tg->cmd, 1, 0x0);
1852         hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1853         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1854         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1855         hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1856         hdmi_set_reg(tg->vsync, 2, 0x1);
1857         hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1858         hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1859         hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1860         hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1861         hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1862         hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1863         hdmi_set_reg(tg->tg_3d, 1, 0x0);
1864
1865         if (hdata->is_soc_exynos5) {
1866                 /* Workaround 4 implementation for 1440x900 resolution support */
1867                 if (m->hdisplay == 1440 && m->vdisplay == 900 && m->clock == 106500) {
1868                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0xe0);
1869                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0xe0);
1870                 }
1871
1872                 /* Workaround 3 implementation for 800x600 resolution support */
1873                 if (m->hdisplay == 800 && m->vdisplay == 600 && m->clock == 40000) {
1874                         hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay - 0x20);
1875                         hdmi_set_reg(tg->hact_sz, 2, m->hdisplay + 0x20);
1876                 }
1877         }
1878 }
1879
1880 static void hdmi_mode_set(void *ctx, struct drm_display_mode *mode)
1881 {
1882         struct hdmi_context *hdata = ctx;
1883
1884         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1885
1886         if (hdata->is_v13)
1887                 hdata->cur_conf = hdmi_v13_conf_index(mode);
1888         else
1889                 hdmi_v14_mode_set(hdata, mode);
1890 }
1891
1892 static void hdmi_commit(void *ctx)
1893 {
1894         struct hdmi_context *hdata = ctx;
1895
1896         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
1897         if (!hdata->is_hdmi_powered_on)
1898                 return;
1899
1900         hdmi_conf_apply(hdata);
1901         hdata->enabled = true;
1902 }
1903
1904 static void hdmi_apply(void *ctx)
1905 {
1906         hdmi_commit(ctx);
1907 }
1908
1909 static int hdmiphy_update_bits(struct i2c_client *client, u8 *reg_cache,
1910                                u8 reg, u8 mask, u8 val)
1911 {
1912         int ret;
1913         u8 buffer[2];
1914
1915         buffer[0] = reg;
1916         buffer[1] = (reg_cache[reg] & ~mask) | (val & mask);
1917         reg_cache[reg] = buffer[1];
1918
1919         ret = i2c_master_send(client, buffer, 2);
1920         if (ret != 2)
1921                 return -EIO;
1922
1923         return 0;
1924 }
1925
1926 static int hdmiphy_s_power(struct i2c_client *client, bool on)
1927 {
1928         u8 reg_cache[32] = { 0 };
1929         u8 buffer[2];
1930         int ret;
1931
1932         DRM_DEBUG_KMS("%s: hdmiphy is %s\n", __func__, on ? "on" : "off");
1933
1934         /* Cache all 32 registers to make the code below faster */
1935         buffer[0] = 0x0;
1936         ret = i2c_master_send(client, buffer, 1);
1937         if (ret != 1) {
1938                 ret = -EIO;
1939                 goto exit;
1940         }
1941         ret = i2c_master_recv(client, reg_cache, 32);
1942         if (ret != 32) {
1943                 ret = -EIO;
1944                 goto exit;
1945         }
1946
1947         /* Go to/from configuration from/to operation mode */
1948         ret = hdmiphy_update_bits(client, reg_cache, 0x1f, 0xff,
1949                                   on ? 0x80 : 0x00);
1950         if (ret)
1951                 goto exit;
1952
1953         /*
1954          * Turn off undocumented "oscpad" if !on; it turns on again in
1955          * hdmiphy_conf_apply()
1956          */
1957         if (!on)
1958                 ret = hdmiphy_update_bits(client, reg_cache, 0x0b, 0xc0, 0x00);
1959                 if (ret)
1960                         goto exit;
1961
1962         /* Disable powerdown if on; enable if !on */
1963         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x80,
1964                                   on ? 0 : ~0);
1965         if (ret)
1966                 goto exit;
1967         ret = hdmiphy_update_bits(client, reg_cache, 0x1d, 0x77,
1968                                   on ? 0 : ~0);
1969         if (ret)
1970                 goto exit;
1971
1972         /*
1973          * Turn off bit 3 of reg 4 if !on; it turns on again in
1974          * hdmiphy_conf_apply().  It's unclear what this bit does.
1975          */
1976         if (!on)
1977                 ret = hdmiphy_update_bits(client, reg_cache, 0x04, BIT(3), 0);
1978                 if (ret)
1979                         goto exit;
1980
1981 exit:
1982         /* Don't expect any errors so just do a single warn */
1983         WARN_ON(ret);
1984
1985         return ret;
1986 }
1987
1988 static void hdmi_resource_poweron(struct hdmi_context *hdata)
1989 {
1990         struct hdmi_resources *res = &hdata->res;
1991
1992         hdata->is_hdmi_powered_on = true;
1993         hdmi_cfg_hpd(hdata, false);
1994
1995         /* irq change by TV power status */
1996         if (hdata->curr_irq == hdata->internal_irq)
1997                 return;
1998
1999         disable_irq(hdata->curr_irq);
2000
2001         hdata->curr_irq = hdata->internal_irq;
2002
2003         enable_irq(hdata->curr_irq);
2004
2005         /* turn HDMI power on */
2006         regulator_bulk_enable(res->regul_count, res->regul_bulk);
2007
2008         /* power-on hdmi clocks */
2009         clk_enable(res->hdmiphy);
2010
2011         hdmiphy_s_power(hdata->hdmiphy_port, 1);
2012         hdmiphy_conf_reset(hdata);
2013         hdmi_conf_reset(hdata);
2014         hdmi_conf_init(hdata);
2015         if (!hdata->is_soc_exynos5)
2016                 hdmi_audio_init(hdata);
2017         hdmi_commit(hdata);
2018 }
2019
2020 static void hdmi_resource_poweroff(struct hdmi_context *hdata)
2021 {
2022         struct hdmi_resources *res = &hdata->res;
2023
2024         hdmi_cfg_hpd(hdata, true);
2025
2026         if (hdata->curr_irq == hdata->external_irq)
2027                 return;
2028
2029         disable_irq(hdata->curr_irq);
2030         hdata->curr_irq = hdata->external_irq;
2031
2032         enable_irq(hdata->curr_irq);
2033         hdata->is_hdmi_powered_on = false;
2034
2035         hdmiphy_s_power(hdata->hdmiphy_port, 0);
2036         hdmiphy_conf_reset(hdata);
2037
2038         /* power-off hdmi clocks */
2039         clk_disable(res->hdmiphy);
2040
2041         /* turn HDMI power off */
2042         regulator_bulk_disable(res->regul_count, res->regul_bulk);
2043 }
2044
2045 static int hdmi_power(void *ctx, int mode)
2046 {
2047         struct hdmi_context *hdata = ctx;
2048
2049         switch (mode) {
2050         case DRM_MODE_DPMS_ON:
2051                 if (!hdata->is_hdmi_powered_on)
2052                         hdmi_resource_poweron(hdata);
2053                 hdmi_enable_video(hdata);
2054                 break;
2055         case DRM_MODE_DPMS_STANDBY:
2056                 hdmi_disable_video(hdata);
2057                 break;
2058         case DRM_MODE_DPMS_OFF:
2059         case DRM_MODE_DPMS_SUSPEND:
2060                 if (hdata->is_hdmi_powered_on)
2061                         hdmi_resource_poweroff(hdata);
2062                 break;
2063         default:
2064                 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
2065                 break;
2066         }
2067
2068         return 0;
2069 }
2070
2071 static int hdmi_subdrv_probe(void *ctx, struct drm_device *drm_dev)
2072 {
2073         struct hdmi_context *hdata = ctx;
2074
2075         hdata->drm_dev = drm_dev;
2076
2077         return 0;
2078 }
2079
2080 static struct exynos_panel_ops hdmi_ops = {
2081         /* display */
2082         .subdrv_probe   = hdmi_subdrv_probe,
2083         .is_connected   = hdmi_is_connected,
2084         .get_edid       = hdmi_get_edid,
2085         .check_timing   = hdmi_check_timing,
2086         .power          = hdmi_power,
2087
2088         /* manager */
2089         .mode_fixup     = hdmi_mode_fixup,
2090         .mode_set       = hdmi_mode_set,
2091         .commit         = hdmi_commit,
2092         .apply          = hdmi_apply,
2093 };
2094
2095 /*
2096  * Handle hotplug events outside the interrupt handler proper.
2097  */
2098 static void hdmi_hotplug_func(struct work_struct *work)
2099 {
2100         struct hdmi_context *hdata =
2101                 container_of(work, struct hdmi_context, hotplug_work);
2102
2103         drm_helper_hpd_irq_event(hdata->drm_dev);
2104 }
2105
2106 static irqreturn_t hdmi_irq_handler(int irq, void *arg)
2107 {
2108         struct hdmi_context *hdata = arg;
2109         u32 intc_flag;
2110         if (hdata->is_hdmi_powered_on) {
2111                 intc_flag = hdmi_reg_read(hdata, HDMI_INTC_FLAG);
2112                 /* clearing flags for HPD plug/unplug */
2113                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2114                         DRM_DEBUG_KMS("int unplugged, handling:%d\n",
2115                                 hdata->hpd_handle);
2116                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2117                                 HDMI_INTC_FLAG_HPD_UNPLUG);
2118                 }
2119                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2120                         DRM_DEBUG_KMS("int plugged, handling:%d\n",
2121                                 hdata->hpd_handle);
2122                         hdmi_reg_writemask(hdata, HDMI_INTC_FLAG, ~0,
2123                                 HDMI_INTC_FLAG_HPD_PLUG);
2124                 }
2125         }
2126
2127         if (hdata->drm_dev && hdata->hpd_handle)
2128                 queue_work(hdata->wq, &hdata->hotplug_work);
2129
2130         return IRQ_HANDLED;
2131 }
2132
2133 static int __devinit hdmi_resources_init(struct hdmi_context *hdata)
2134 {
2135         struct device *dev = hdata->dev;
2136         struct hdmi_resources *res = &hdata->res;
2137 #ifndef CONFIG_ARCH_EXYNOS5
2138         static char *supply[] = {
2139                 "hdmi-en",
2140                 "vdd",
2141                 "vdd_osc",
2142                 "vdd_pll",
2143         };
2144         int i, ret;
2145 #endif
2146
2147         DRM_DEBUG_KMS("HDMI resource init\n");
2148
2149         memset(res, 0, sizeof *res);
2150
2151         /* get clocks, power */
2152         res->hdmi = clk_get(dev, "hdmi");
2153         if (IS_ERR_OR_NULL(res->hdmi)) {
2154                 DRM_ERROR("failed to get clock 'hdmi'\n");
2155                 goto fail;
2156         }
2157         res->sclk_hdmi = clk_get(dev, "sclk_hdmi");
2158         if (IS_ERR_OR_NULL(res->sclk_hdmi)) {
2159                 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
2160                 goto fail;
2161         }
2162         res->sclk_pixel = clk_get(dev, "sclk_pixel");
2163         if (IS_ERR_OR_NULL(res->sclk_pixel)) {
2164                 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
2165                 goto fail;
2166         }
2167         res->sclk_hdmiphy = clk_get(dev, "sclk_hdmiphy");
2168         if (IS_ERR_OR_NULL(res->sclk_hdmiphy)) {
2169                 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
2170                 goto fail;
2171         }
2172         res->hdmiphy = clk_get(dev, "hdmiphy");
2173         if (IS_ERR_OR_NULL(res->hdmiphy)) {
2174                 DRM_ERROR("failed to get clock 'hdmiphy'\n");
2175                 goto fail;
2176         }
2177
2178         clk_set_parent(res->sclk_hdmi, res->sclk_pixel);
2179
2180 #ifndef CONFIG_ARCH_EXYNOS5
2181         res->regul_bulk = kzalloc(ARRAY_SIZE(supply) *
2182                 sizeof res->regul_bulk[0], GFP_KERNEL);
2183         if (!res->regul_bulk) {
2184                 DRM_ERROR("failed to get memory for regulators\n");
2185                 goto fail;
2186         }
2187         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
2188                 res->regul_bulk[i].supply = supply[i];
2189                 res->regul_bulk[i].consumer = NULL;
2190         }
2191         ret = regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2192         if (ret) {
2193                 DRM_ERROR("failed to get regulators\n");
2194                 goto fail;
2195         }
2196         res->regul_count = ARRAY_SIZE(supply);
2197 #endif
2198         /* TODO:
2199          * These clocks also should be added in
2200          * runtime resume and runtime suspend
2201          */
2202         clk_enable(res->hdmi);
2203         clk_enable(res->sclk_hdmi);
2204
2205         return 0;
2206 fail:
2207         DRM_ERROR("HDMI resource init - failed\n");
2208         return -ENODEV;
2209 }
2210
2211 static int hdmi_resources_cleanup(struct hdmi_context *hdata)
2212 {
2213         struct hdmi_resources *res = &hdata->res;
2214
2215         regulator_bulk_free(res->regul_count, res->regul_bulk);
2216         /* kfree is NULL-safe */
2217         kfree(res->regul_bulk);
2218         if (!IS_ERR_OR_NULL(res->hdmiphy))
2219                 clk_put(res->hdmiphy);
2220         if (!IS_ERR_OR_NULL(res->sclk_hdmiphy))
2221                 clk_put(res->sclk_hdmiphy);
2222         if (!IS_ERR_OR_NULL(res->sclk_pixel))
2223                 clk_put(res->sclk_pixel);
2224         if (!IS_ERR_OR_NULL(res->sclk_hdmi))
2225                 clk_put(res->sclk_hdmi);
2226         if (!IS_ERR_OR_NULL(res->hdmi))
2227                 clk_put(res->hdmi);
2228         memset(res, 0, sizeof *res);
2229
2230         return 0;
2231 }
2232
2233 struct platform_device *hdmi_audio_device;
2234
2235 int hdmi_register_audio_device(struct platform_device *pdev)
2236 {
2237         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2238         struct platform_device *audio_dev;
2239         int ret;
2240
2241         audio_dev = platform_device_alloc("exynos-hdmi-audio", -1);
2242         if (!audio_dev) {
2243                 DRM_ERROR("hdmi audio device allocation failed.\n");
2244                 ret = -ENOMEM;
2245                 goto err;
2246         }
2247
2248         ret = platform_device_add_resources(audio_dev, pdev->resource,
2249                         pdev->num_resources);
2250         if (ret) {
2251                 ret = -ENOMEM;
2252                 goto err_device;
2253         }
2254
2255         audio_dev->dev.of_node = of_get_next_child(pdev->dev.of_node, NULL);
2256         audio_dev->dev.platform_data = (void *)hdata->hpd_gpio;
2257
2258         ret = platform_device_add(audio_dev);
2259         if (ret) {
2260                 DRM_ERROR("hdmi audio device add failed.\n");
2261                 goto err_device;
2262         }
2263
2264         hdmi_audio_device = audio_dev;
2265         return 0;
2266
2267 err_device:
2268         platform_device_put(audio_dev);
2269
2270 err:
2271         return ret;
2272 }
2273
2274 void hdmi_unregister_audio_device(void)
2275 {
2276         platform_device_unregister(hdmi_audio_device);
2277 }
2278
2279 static int __devinit hdmi_probe(struct platform_device *pdev)
2280 {
2281         struct device *dev = &pdev->dev;
2282         struct hdmi_context *hdata;
2283         struct exynos_drm_hdmi_pdata *pdata;
2284         struct resource *res;
2285         struct device_node *ddc_node, *phy_node;
2286         int ret;
2287         enum of_gpio_flags flags;
2288
2289         DRM_DEBUG_KMS("[%d]\n", __LINE__);
2290
2291         pdata = pdev->dev.platform_data;
2292         if (!pdata) {
2293                 DRM_ERROR("no platform data specified\n");
2294                 return -EINVAL;
2295         }
2296
2297         hdata = kzalloc(sizeof(struct hdmi_context), GFP_KERNEL);
2298         if (!hdata) {
2299                 DRM_ERROR("out of memory\n");
2300                 return -ENOMEM;
2301         }
2302
2303         platform_set_drvdata(pdev, hdata);
2304
2305         hdata->is_v13 = pdata->is_v13;
2306         hdata->default_win = pdata->default_win;
2307         hdata->default_timing = &pdata->timing;
2308         hdata->default_bpp = pdata->bpp;
2309         hdata->dev = dev;
2310         hdata->is_soc_exynos5 = of_device_is_compatible(dev->of_node,
2311                 "samsung,exynos5-hdmi");
2312
2313         ret = hdmi_resources_init(hdata);
2314         if (ret) {
2315                 ret = -EINVAL;
2316                 goto err_data;
2317         }
2318
2319         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2320         if (!res) {
2321                 DRM_ERROR("failed to find registers\n");
2322                 ret = -ENOENT;
2323                 goto err_resource;
2324         }
2325
2326         hdata->regs_res = request_mem_region(res->start, resource_size(res),
2327                                            dev_name(dev));
2328         if (!hdata->regs_res) {
2329                 DRM_ERROR("failed to claim register region\n");
2330                 ret = -ENOENT;
2331                 goto err_resource;
2332         }
2333
2334         hdata->regs = ioremap(res->start, resource_size(res));
2335         if (!hdata->regs) {
2336                 DRM_ERROR("failed to map registers\n");
2337                 ret = -ENXIO;
2338                 goto err_req_region;
2339         }
2340
2341         /* DDC i2c driver */
2342         ddc_node = of_find_node_by_name(NULL, "exynos_ddc");
2343         if (!ddc_node) {
2344                 DRM_ERROR("Failed to find ddc node in device tree\n");
2345                 ret = -ENODEV;
2346                 goto err_iomap;
2347         }
2348         hdata->ddc_port = of_find_i2c_device_by_node(ddc_node);
2349         if (!hdata->ddc_port) {
2350                 DRM_ERROR("Failed to get ddc i2c client by node\n");
2351                 ret = -ENODEV;
2352                 goto err_iomap;
2353         }
2354
2355         /* hdmiphy i2c driver */
2356         phy_node = of_find_node_by_name(NULL, "exynos_hdmiphy");
2357         if (!phy_node) {
2358                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2359                 ret = -ENODEV;
2360                 goto err_ddc;
2361         }
2362         hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2363         if (!hdata->hdmiphy_port) {
2364                 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2365                 ret = -ENODEV;
2366                 goto err_ddc;
2367         }
2368
2369         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2370         if (res == NULL) {
2371                 DRM_ERROR("get interrupt resource failed.\n");
2372                 ret = -ENXIO;
2373                 goto err_hdmiphy;
2374         }
2375
2376         hdata->internal_irq = res->start;
2377
2378         hdata->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
2379                                 "hpd-gpio", 0, &flags);
2380
2381         if (!gpio_is_valid(hdata->hpd_gpio)) {
2382                 DRM_ERROR("failed to get hpd gpio.");
2383                 ret = -EINVAL;
2384                 goto err_hdmiphy;
2385         }
2386
2387         hdata->external_irq = gpio_to_irq(hdata->hpd_gpio);
2388
2389         /* create workqueue and hotplug work */
2390         hdata->wq = alloc_workqueue("exynos-drm-hdmi",
2391                         WQ_UNBOUND | WQ_NON_REENTRANT, 1);
2392         if (hdata->wq == NULL) {
2393                 DRM_ERROR("Failed to create workqueue.\n");
2394                 ret = -ENOMEM;
2395                 goto err_hdmiphy;
2396         }
2397         INIT_WORK(&hdata->hotplug_work, hdmi_hotplug_func);
2398
2399         ret = request_irq(hdata->internal_irq, hdmi_irq_handler,
2400                         IRQF_SHARED, "int_hdmi", hdata);
2401         if (ret) {
2402                 DRM_ERROR("request int interrupt failed.\n");
2403                 goto err_workqueue;
2404         }
2405         disable_irq(hdata->internal_irq);
2406
2407         ret = request_irq(hdata->external_irq, hdmi_irq_handler,
2408                 IRQ_TYPE_EDGE_BOTH | IRQF_SHARED, "ext_hdmi",
2409                 hdata);
2410         if (ret) {
2411                 DRM_ERROR("request ext interrupt failed.\n");
2412                 goto err_int_irq;
2413         }
2414         disable_irq(hdata->external_irq);
2415
2416         if (of_device_is_compatible(dev->of_node,
2417                 "samsung,exynos5-hdmi")) {
2418                 ret = hdmi_register_audio_device(pdev);
2419                 if (ret) {
2420                         DRM_ERROR("hdmi-audio device registering failed.\n");
2421                         goto err_ext_irq;
2422                 }
2423         }
2424
2425         hdmi_resource_poweron(hdata);
2426
2427         if (!hdmi_is_connected(hdata)) {
2428                 hdmi_resource_poweroff(hdata);
2429                 DRM_DEBUG_KMS("gpio state is low. powering off!\n");
2430         }
2431
2432         exynos_display_attach_panel(EXYNOS_DRM_DISPLAY_TYPE_MIXER, &hdmi_ops,
2433                         hdata);
2434
2435         return 0;
2436
2437 err_ext_irq:
2438         free_irq(hdata->external_irq, hdata);
2439 err_int_irq:
2440         free_irq(hdata->internal_irq, hdata);
2441  err_workqueue:
2442         destroy_workqueue(hdata->wq);
2443 err_hdmiphy:
2444         put_device(&hdata->hdmiphy_port->dev);
2445 err_ddc:
2446         put_device(&hdata->ddc_port->dev);
2447 err_iomap:
2448         iounmap(hdata->regs);
2449 err_req_region:
2450         release_mem_region(hdata->regs_res->start,
2451                         resource_size(hdata->regs_res));
2452 err_resource:
2453         hdmi_resources_cleanup(hdata);
2454 err_data:
2455         kfree(hdata);
2456         return ret;
2457 }
2458
2459 static int __devexit hdmi_remove(struct platform_device *pdev)
2460 {
2461         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2462         struct hdmi_resources *res = &hdata->res;
2463
2464         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
2465
2466         hdmi_resource_poweroff(hdata);
2467
2468         hdmi_unregister_audio_device();
2469
2470         disable_irq(hdata->curr_irq);
2471         free_irq(hdata->internal_irq, hdata);
2472         free_irq(hdata->external_irq, hdata);
2473
2474         cancel_work_sync(&hdata->hotplug_work);
2475         destroy_workqueue(hdata->wq);
2476
2477         clk_disable(res->hdmi);
2478         clk_disable(res->sclk_hdmi);
2479         hdmi_resources_cleanup(hdata);
2480
2481         iounmap(hdata->regs);
2482
2483         release_mem_region(hdata->regs_res->start,
2484                         resource_size(hdata->regs_res));
2485
2486         put_device(&hdata->hdmiphy_port->dev);
2487         put_device(&hdata->ddc_port->dev);
2488
2489         kfree(hdata);
2490
2491         return 0;
2492 }
2493
2494 struct platform_driver hdmi_driver = {
2495         .probe          = hdmi_probe,
2496         .remove         = __devexit_p(hdmi_remove),
2497         .driver         = {
2498 #ifdef CONFIG_ARCH_EXYNOS5
2499                 .name   = "exynos5-hdmi",
2500 #else
2501                 .name   = "exynos4-hdmi",
2502 #endif
2503                 .owner  = THIS_MODULE,
2504         },
2505 };