drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * Freescale DCU drm device driver
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/regmap.h>
  14
  15 #include <drm/drmP.h>
  16 #include <drm/drm_atomic.h>
  17 #include <drm/drm_atomic_helper.h>
  18 #include <drm/drm_crtc.h>
  19 #include <drm/drm_crtc_helper.h>
  20
  21 #include "fsl_dcu_drm_crtc.h"
  22 #include "fsl_dcu_drm_drv.h"
  23 #include "fsl_dcu_drm_plane.h"
  24
  25 static void fsl_dcu_drm_crtc_atomic_begin(struct drm_crtc *crtc,
  26                                           struct drm_crtc_state *old_crtc_state)
  27 {
  28 }
  29
  30 static int fsl_dcu_drm_crtc_atomic_check(struct drm_crtc *crtc,
  31                                          struct drm_crtc_state *state)
  32 {
  33         return 0;
  34 }
  35
  36 static void fsl_dcu_drm_crtc_atomic_flush(struct drm_crtc *crtc,
  37                                           struct drm_crtc_state *old_crtc_state)
  38 {
  39 }
  40
  41 static void fsl_dcu_drm_disable_crtc(struct drm_crtc *crtc)
  42 {
  43         struct drm_device *dev = crtc->dev;
  44         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  45
  46         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  47                            DCU_MODE_DCU_MODE_MASK,
  48                            DCU_MODE_DCU_MODE(DCU_MODE_OFF));
  49         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  50                      DCU_UPDATE_MODE_READREG);
  51 }
  52
  53 static void fsl_dcu_drm_crtc_enable(struct drm_crtc *crtc)
  54 {
  55         struct drm_device *dev = crtc->dev;
  56         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  57
  58         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
  59                            DCU_MODE_DCU_MODE_MASK,
  60                            DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
  61         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
  62                      DCU_UPDATE_MODE_READREG);
  63 }
  64
  65 static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
  66 {
  67         struct drm_device *dev = crtc->dev;
  68         struct fsl_dcu_drm_device *fsl_dev = dev->dev_private;
  69         struct drm_display_mode *mode = &crtc->state->mode;
  70         unsigned int hbp, hfp, hsw, vbp, vfp, vsw, index, pol = 0;
  71
  72         index = drm_crtc_index(crtc);
  73         clk_set_rate(fsl_dev->pix_clk, mode->clock * 1000);
  74
  75         /* Configure timings: */
  76         hbp = mode->htotal - mode->hsync_end;
  77         hfp = mode->hsync_start - mode->hdisplay;
  78         hsw = mode->hsync_end - mode->hsync_start;
  79         vbp = mode->vtotal - mode->vsync_end;
  80         vfp = mode->vsync_start - mode->vdisplay;
  81         vsw = mode->vsync_end - mode->vsync_start;
  82
  83         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
  84                 pol |= DCU_SYN_POL_INV_HS_LOW;
  85
  86         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
  87                 pol |= DCU_SYN_POL_INV_VS_LOW;
  88
  89         regmap_write(fsl_dev->regmap, DCU_HSYN_PARA,
  90                      DCU_HSYN_PARA_BP(hbp) |
  91                      DCU_HSYN_PARA_PW(hsw) |
  92                      DCU_HSYN_PARA_FP(hfp));
  93         regmap_write(fsl_dev->regmap, DCU_VSYN_PARA,
  94                      DCU_VSYN_PARA_BP(vbp) |
  95                      DCU_VSYN_PARA_PW(vsw) |
  96                      DCU_VSYN_PARA_FP(vfp));
  97         regmap_write(fsl_dev->regmap, DCU_DISP_SIZE,
  98                      DCU_DISP_SIZE_DELTA_Y(mode->vdisplay) |
  99                      DCU_DISP_SIZE_DELTA_X(mode->hdisplay));
 100         regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol);
 101         regmap_write(fsl_dev->regmap, DCU_BGND, DCU_BGND_R(0) |
 102                      DCU_BGND_G(0) | DCU_BGND_B(0));
 103         regmap_write(fsl_dev->regmap, DCU_DCU_MODE,
 104                      DCU_MODE_BLEND_ITER(1) | DCU_MODE_RASTER_EN);
 105         regmap_write(fsl_dev->regmap, DCU_THRESHOLD,
 106                      DCU_THRESHOLD_LS_BF_VS(BF_VS_VAL) |
 107                      DCU_THRESHOLD_OUT_BUF_HIGH(BUF_MAX_VAL) |
 108                      DCU_THRESHOLD_OUT_BUF_LOW(BUF_MIN_VAL));
 109         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
 110                      DCU_UPDATE_MODE_READREG);
 111         return;
 112 }
 113
 114 static const struct drm_crtc_helper_funcs fsl_dcu_drm_crtc_helper_funcs = {
 115         .atomic_begin = fsl_dcu_drm_crtc_atomic_begin,
 116         .atomic_check = fsl_dcu_drm_crtc_atomic_check,
 117         .atomic_flush = fsl_dcu_drm_crtc_atomic_flush,
 118         .disable = fsl_dcu_drm_disable_crtc,
 119         .enable = fsl_dcu_drm_crtc_enable,
 120         .mode_set_nofb = fsl_dcu_drm_crtc_mode_set_nofb,
 121 };
 122
 123 static const struct drm_crtc_funcs fsl_dcu_drm_crtc_funcs = {
 124         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 125         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
 126         .destroy = drm_crtc_cleanup,
 127         .page_flip = drm_atomic_helper_page_flip,
 128         .reset = drm_atomic_helper_crtc_reset,
 129         .set_config = drm_atomic_helper_set_config,
 130 };
 131
 132 int fsl_dcu_drm_crtc_create(struct fsl_dcu_drm_device *fsl_dev)
 133 {
 134         struct drm_plane *primary;
 135         struct drm_crtc *crtc = &fsl_dev->crtc;
 136         unsigned int i, j, reg_num;
 137         int ret;
 138
 139         primary = fsl_dcu_drm_primary_create_plane(fsl_dev->drm);
 140         if (!primary)
 141                 return -ENOMEM;
 142
 143         ret = drm_crtc_init_with_planes(fsl_dev->drm, crtc, primary, NULL,
 144                                         &fsl_dcu_drm_crtc_funcs, NULL);
 145         if (ret) {
 146                 primary->funcs->destroy(primary);
 147                 return ret;
 148         }
 149
 150         drm_crtc_helper_add(crtc, &fsl_dcu_drm_crtc_helper_funcs);
 151
 152         if (!strcmp(fsl_dev->soc->name, "ls1021a"))
 153                 reg_num = LS1021A_LAYER_REG_NUM;
 154         else
 155                 reg_num = VF610_LAYER_REG_NUM;
 156         for (i = 0; i < fsl_dev->soc->total_layer; i++) {
 157                 for (j = 1; j <= reg_num; j++)
 158                         regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(i, j), 0);
 159         }
 160         regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
 161                            DCU_MODE_DCU_MODE_MASK,
 162                            DCU_MODE_DCU_MODE(DCU_MODE_OFF));
 163         regmap_write(fsl_dev->regmap, DCU_UPDATE_MODE,
 164                      DCU_UPDATE_MODE_READREG);
 165
 166         return 0;
 167 }