drivers/gpu/drm/gma500/cdv_intel_dp.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "drm_crtc.h"
  33 #include "drm_crtc_helper.h"
  34 #include "psb_drv.h"
  35 #include "psb_intel_drv.h"
  36 #include "psb_intel_reg.h"
  37 #include "drm_dp_helper.h"
  38
  39
  40 #define DP_LINK_STATUS_SIZE     6
  41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  42
  43 #define DP_LINK_CONFIGURATION_SIZE      9
  44
  45 #define CDV_FAST_LINK_TRAIN     1
  46
  47 struct cdv_intel_dp {
  48         uint32_t output_reg;
  49         uint32_t DP;
  50         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
  51         bool has_audio;
  52         int force_audio;
  53         uint32_t color_range;
  54         uint8_t link_bw;
  55         uint8_t lane_count;
  56         uint8_t dpcd[4];
  57         struct psb_intel_encoder *encoder;
  58         struct i2c_adapter adapter;
  59         struct i2c_algo_dp_aux_data algo;
  60         uint8_t train_set[4];
  61         uint8_t link_status[DP_LINK_STATUS_SIZE];
  62 };
  63
  64 struct ddi_regoff {
  65         uint32_t        PreEmph1;
  66         uint32_t        PreEmph2;
  67         uint32_t        VSwing1;
  68         uint32_t        VSwing2;
  69         uint32_t        VSwing3;
  70         uint32_t        VSwing4;
  71         uint32_t        VSwing5;
  72 };
  73
  74 static struct ddi_regoff ddi_DP_train_table[] = {
  75         {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
  76         .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
  77         .VSwing5 = 0x8158,},
  78         {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
  79         .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
  80         .VSwing5 = 0x8258,},
  81 };
  82
  83 static uint32_t dp_vswing_premph_table[] = {
  84         0x55338954,     0x4000,
  85         0x554d8954,     0x2000,
  86         0x55668954,     0,
  87         0x559ac0d4,     0x6000,
  88 };
  89 /**
  90  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  91  * @intel_dp: DP struct
  92  *
  93  * If a CPU or PCH DP output is attached to an eDP panel, this function
  94  * will return true, and false otherwise.
  95  */
  96 static bool is_edp(struct psb_intel_encoder *encoder)
  97 {
  98         return encoder->type == INTEL_OUTPUT_EDP;
  99 }
 100
 101
 102 static void cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder);
 103 static void cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder);
 104 static void cdv_intel_dp_link_down(struct psb_intel_encoder *encoder);
 105
 106 static int
 107 cdv_intel_dp_max_lane_count(struct psb_intel_encoder *encoder)
 108 {
 109         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 110         int max_lane_count = 4;
 111
 112         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
 113                 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
 114                 switch (max_lane_count) {
 115                 case 1: case 2: case 4:
 116                         break;
 117                 default:
 118                         max_lane_count = 4;
 119                 }
 120         }
 121         return max_lane_count;
 122 }
 123
 124 static int
 125 cdv_intel_dp_max_link_bw(struct psb_intel_encoder *encoder)
 126 {
 127         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 128         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 129
 130         switch (max_link_bw) {
 131         case DP_LINK_BW_1_62:
 132         case DP_LINK_BW_2_7:
 133                 break;
 134         default:
 135                 max_link_bw = DP_LINK_BW_1_62;
 136                 break;
 137         }
 138         return max_link_bw;
 139 }
 140
 141 static int
 142 cdv_intel_dp_link_clock(uint8_t link_bw)
 143 {
 144         if (link_bw == DP_LINK_BW_2_7)
 145                 return 270000;
 146         else
 147                 return 162000;
 148 }
 149
 150 static int
 151 cdv_intel_dp_link_required(int pixel_clock, int bpp)
 152 {
 153         return (pixel_clock * bpp + 7) / 8;
 154 }
 155
 156 static int
 157 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 158 {
 159         return (max_link_clock * max_lanes * 19) / 20;
 160 }
 161
 162 static int
 163 cdv_intel_dp_mode_valid(struct drm_connector *connector,
 164                     struct drm_display_mode *mode)
 165 {
 166         struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
 167         struct drm_device *dev = connector->dev;
 168         struct drm_psb_private *dev_priv = dev->dev_private;
 169         int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
 170         int max_lanes = cdv_intel_dp_max_lane_count(encoder);
 171
 172         if (is_edp(encoder) && dev_priv->panel_fixed_mode) {
 173                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
 174                         return MODE_PANEL;
 175
 176                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
 177                         return MODE_PANEL;
 178         }
 179
 180         /* only refuse the mode on non eDP since we have seen some weird eDP panels
 181            which are outside spec tolerances but somehow work by magic */
 182         if (!is_edp(encoder) &&
 183             (cdv_intel_dp_link_required(mode->clock, 24)
 184              > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
 185                 return MODE_CLOCK_HIGH;
 186
 187         if (mode->clock < 10000)
 188                 return MODE_CLOCK_LOW;
 189
 190         return MODE_OK;
 191 }
 192
 193 static uint32_t
 194 pack_aux(uint8_t *src, int src_bytes)
 195 {
 196         int     i;
 197         uint32_t v = 0;
 198
 199         if (src_bytes > 4)
 200                 src_bytes = 4;
 201         for (i = 0; i < src_bytes; i++)
 202                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 203         return v;
 204 }
 205
 206 static void
 207 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 208 {
 209         int i;
 210         if (dst_bytes > 4)
 211                 dst_bytes = 4;
 212         for (i = 0; i < dst_bytes; i++)
 213                 dst[i] = src >> ((3-i) * 8);
 214 }
 215
 216 static int
 217 cdv_intel_dp_aux_ch(struct psb_intel_encoder *encoder,
 218                 uint8_t *send, int send_bytes,
 219                 uint8_t *recv, int recv_size)
 220 {
 221         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 222         uint32_t output_reg = intel_dp->output_reg;
 223         struct drm_device *dev = encoder->base.dev;
 224         uint32_t ch_ctl = output_reg + 0x10;
 225         uint32_t ch_data = ch_ctl + 4;
 226         int i;
 227         int recv_bytes;
 228         uint32_t status;
 229         uint32_t aux_clock_divider;
 230         int try, precharge;
 231
 232         /* The clock divider is based off the hrawclk,
 233          * and would like to run at 2MHz. So, take the
 234          * hrawclk value and divide by 2 and use that
 235          * On CDV platform it uses 200MHz as hrawclk.
 236          *
 237          */
 238         aux_clock_divider = 200 / 2;
 239
 240         precharge = 4;
 241
 242         if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
 243                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
 244                           REG_READ(ch_ctl));
 245                 return -EBUSY;
 246         }
 247
 248         /* Must try at least 3 times according to DP spec */
 249         for (try = 0; try < 5; try++) {
 250                 /* Load the send data into the aux channel data registers */
 251                 for (i = 0; i < send_bytes; i += 4)
 252                         REG_WRITE(ch_data + i,
 253                                    pack_aux(send + i, send_bytes - i));
 254
 255                 /* Send the command and wait for it to complete */
 256                 REG_WRITE(ch_ctl,
 257                            DP_AUX_CH_CTL_SEND_BUSY |
 258                            DP_AUX_CH_CTL_TIME_OUT_400us |
 259                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 260                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 261                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 262                            DP_AUX_CH_CTL_DONE |
 263                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 264                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 265                 for (;;) {
 266                         status = REG_READ(ch_ctl);
 267                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 268                                 break;
 269                         udelay(100);
 270                 }
 271
 272                 /* Clear done status and any errors */
 273                 REG_WRITE(ch_ctl,
 274                            status |
 275                            DP_AUX_CH_CTL_DONE |
 276                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 277                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 278                 if (status & DP_AUX_CH_CTL_DONE)
 279                         break;
 280         }
 281
 282         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 283                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 284                 return -EBUSY;
 285         }
 286
 287         /* Check for timeout or receive error.
 288          * Timeouts occur when the sink is not connected
 289          */
 290         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 291                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 292                 return -EIO;
 293         }
 294
 295         /* Timeouts occur when the device isn't connected, so they're
 296          * "normal" -- don't fill the kernel log with these */
 297         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 298                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 299                 return -ETIMEDOUT;
 300         }
 301
 302         /* Unload any bytes sent back from the other side */
 303         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 304                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 305         if (recv_bytes > recv_size)
 306                 recv_bytes = recv_size;
 307
 308         for (i = 0; i < recv_bytes; i += 4)
 309                 unpack_aux(REG_READ(ch_data + i),
 310                            recv + i, recv_bytes - i);
 311
 312         return recv_bytes;
 313 }
 314
 315 /* Write data to the aux channel in native mode */
 316 static int
 317 cdv_intel_dp_aux_native_write(struct psb_intel_encoder *encoder,
 318                           uint16_t address, uint8_t *send, int send_bytes)
 319 {
 320         int ret;
 321         uint8_t msg[20];
 322         int msg_bytes;
 323         uint8_t ack;
 324
 325         if (send_bytes > 16)
 326                 return -1;
 327         msg[0] = AUX_NATIVE_WRITE << 4;
 328         msg[1] = address >> 8;
 329         msg[2] = address & 0xff;
 330         msg[3] = send_bytes - 1;
 331         memcpy(&msg[4], send, send_bytes);
 332         msg_bytes = send_bytes + 4;
 333         for (;;) {
 334                 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
 335                 if (ret < 0)
 336                         return ret;
 337                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 338                         break;
 339                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 340                         udelay(100);
 341                 else
 342                         return -EIO;
 343         }
 344         return send_bytes;
 345 }
 346
 347 /* Write a single byte to the aux channel in native mode */
 348 static int
 349 cdv_intel_dp_aux_native_write_1(struct psb_intel_encoder *encoder,
 350                             uint16_t address, uint8_t byte)
 351 {
 352         return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
 353 }
 354
 355 /* read bytes from a native aux channel */
 356 static int
 357 cdv_intel_dp_aux_native_read(struct psb_intel_encoder *encoder,
 358                          uint16_t address, uint8_t *recv, int recv_bytes)
 359 {
 360         uint8_t msg[4];
 361         int msg_bytes;
 362         uint8_t reply[20];
 363         int reply_bytes;
 364         uint8_t ack;
 365         int ret;
 366
 367         msg[0] = AUX_NATIVE_READ << 4;
 368         msg[1] = address >> 8;
 369         msg[2] = address & 0xff;
 370         msg[3] = recv_bytes - 1;
 371
 372         msg_bytes = 4;
 373         reply_bytes = recv_bytes + 1;
 374
 375         for (;;) {
 376                 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
 377                                       reply, reply_bytes);
 378                 if (ret == 0)
 379                         return -EPROTO;
 380                 if (ret < 0)
 381                         return ret;
 382                 ack = reply[0];
 383                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 384                         memcpy(recv, reply + 1, ret - 1);
 385                         return ret - 1;
 386                 }
 387                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 388                         udelay(100);
 389                 else
 390                         return -EIO;
 391         }
 392 }
 393
 394 static int
 395 cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 396                     uint8_t write_byte, uint8_t *read_byte)
 397 {
 398         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 399         struct cdv_intel_dp *intel_dp = container_of(adapter,
 400                                                 struct cdv_intel_dp,
 401                                                 adapter);
 402         struct psb_intel_encoder *encoder = intel_dp->encoder;
 403         uint16_t address = algo_data->address;
 404         uint8_t msg[5];
 405         uint8_t reply[2];
 406         unsigned retry;
 407         int msg_bytes;
 408         int reply_bytes;
 409         int ret;
 410
 411         /* Set up the command byte */
 412         if (mode & MODE_I2C_READ)
 413                 msg[0] = AUX_I2C_READ << 4;
 414         else
 415                 msg[0] = AUX_I2C_WRITE << 4;
 416
 417         if (!(mode & MODE_I2C_STOP))
 418                 msg[0] |= AUX_I2C_MOT << 4;
 419
 420         msg[1] = address >> 8;
 421         msg[2] = address;
 422
 423         switch (mode) {
 424         case MODE_I2C_WRITE:
 425                 msg[3] = 0;
 426                 msg[4] = write_byte;
 427                 msg_bytes = 5;
 428                 reply_bytes = 1;
 429                 break;
 430         case MODE_I2C_READ:
 431                 msg[3] = 0;
 432                 msg_bytes = 4;
 433                 reply_bytes = 2;
 434                 break;
 435         default:
 436                 msg_bytes = 3;
 437                 reply_bytes = 1;
 438                 break;
 439         }
 440
 441         for (retry = 0; retry < 5; retry++) {
 442                 ret = cdv_intel_dp_aux_ch(encoder,
 443                                       msg, msg_bytes,
 444                                       reply, reply_bytes);
 445                 if (ret < 0) {
 446                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 447                         return ret;
 448                 }
 449
 450                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 451                 case AUX_NATIVE_REPLY_ACK:
 452                         /* I2C-over-AUX Reply field is only valid
 453                          * when paired with AUX ACK.
 454                          */
 455                         break;
 456                 case AUX_NATIVE_REPLY_NACK:
 457                         DRM_DEBUG_KMS("aux_ch native nack\n");
 458                         return -EREMOTEIO;
 459                 case AUX_NATIVE_REPLY_DEFER:
 460                         udelay(100);
 461                         continue;
 462                 default:
 463                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 464                                   reply[0]);
 465                         return -EREMOTEIO;
 466                 }
 467
 468                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 469                 case AUX_I2C_REPLY_ACK:
 470                         if (mode == MODE_I2C_READ) {
 471                                 *read_byte = reply[1];
 472                         }
 473                         return reply_bytes - 1;
 474                 case AUX_I2C_REPLY_NACK:
 475                         DRM_DEBUG_KMS("aux_i2c nack\n");
 476                         return -EREMOTEIO;
 477                 case AUX_I2C_REPLY_DEFER:
 478                         DRM_DEBUG_KMS("aux_i2c defer\n");
 479                         udelay(100);
 480                         break;
 481                 default:
 482                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 483                         return -EREMOTEIO;
 484                 }
 485         }
 486
 487         DRM_ERROR("too many retries, giving up\n");
 488         return -EREMOTEIO;
 489 }
 490
 491 static int
 492 cdv_intel_dp_i2c_init(struct psb_intel_connector *connector, struct psb_intel_encoder *encoder, const char *name)
 493 {
 494         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 495         DRM_DEBUG_KMS("i2c_init %s\n", name);
 496         intel_dp->algo.running = false;
 497         intel_dp->algo.address = 0;
 498         intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
 499
 500         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
 501         intel_dp->adapter.owner = THIS_MODULE;
 502         intel_dp->adapter.class = I2C_CLASS_DDC;
 503         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 504         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 505         intel_dp->adapter.algo_data = &intel_dp->algo;
 506         intel_dp->adapter.dev.parent = &connector->base.kdev;
 507
 508         return i2c_dp_aux_add_bus(&intel_dp->adapter);
 509 }
 510
 511 static bool
 512 cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
 513                     struct drm_display_mode *adjusted_mode)
 514 {
 515         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 516         struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
 517         int lane_count, clock;
 518         int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
 519         int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
 520         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 521
 522
 523         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 524                 for (clock = max_clock; clock >= 0; clock--) {
 525                         int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
 526
 527                         if (cdv_intel_dp_link_required(mode->clock, 24)
 528                                         <= link_avail) {
 529                                 intel_dp->link_bw = bws[clock];
 530                                 intel_dp->lane_count = lane_count;
 531                                 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
 532                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
 533                                                 "count %d clock %d\n",
 534                                        intel_dp->link_bw, intel_dp->lane_count,
 535                                        adjusted_mode->clock);
 536                                 return true;
 537                         }
 538                 }
 539         }
 540
 541         return false;
 542 }
 543
 544 struct cdv_intel_dp_m_n {
 545         uint32_t        tu;
 546         uint32_t        gmch_m;
 547         uint32_t        gmch_n;
 548         uint32_t        link_m;
 549         uint32_t        link_n;
 550 };
 551
 552 static void
 553 psb_intel_reduce_ratio(uint32_t *num, uint32_t *den)
 554 {
 555         /*
 556         while (*num > 0xffffff || *den > 0xffffff) {
 557                 *num >>= 1;
 558                 *den >>= 1;
 559         }*/
 560         uint64_t value, m;
 561         m = *num;
 562         value = m * (0x800000);
 563         m = do_div(value, *den);
 564         *num = value;
 565         *den = 0x800000;
 566 }
 567
 568 static void
 569 cdv_intel_dp_compute_m_n(int bpp,
 570                      int nlanes,
 571                      int pixel_clock,
 572                      int link_clock,
 573                      struct cdv_intel_dp_m_n *m_n)
 574 {
 575         m_n->tu = 64;
 576         m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
 577         m_n->gmch_n = link_clock * nlanes;
 578         psb_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 579         m_n->link_m = pixel_clock;
 580         m_n->link_n = link_clock;
 581         psb_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 582 }
 583
 584 void
 585 cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 586                  struct drm_display_mode *adjusted_mode)
 587 {
 588         struct drm_device *dev = crtc->dev;
 589         struct drm_mode_config *mode_config = &dev->mode_config;
 590         struct drm_encoder *encoder;
 591         struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
 592         int lane_count = 4, bpp = 24;
 593         struct cdv_intel_dp_m_n m_n;
 594         int pipe = intel_crtc->pipe;
 595
 596         /*
 597          * Find the lane count in the intel_encoder private
 598          */
 599         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
 600                 struct psb_intel_encoder *intel_encoder;
 601                 struct cdv_intel_dp *intel_dp;
 602
 603                 if (encoder->crtc != crtc)
 604                         continue;
 605
 606                 intel_encoder = to_psb_intel_encoder(encoder);
 607                 intel_dp = intel_encoder->dev_priv;
 608                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
 609                         lane_count = intel_dp->lane_count;
 610                         break;
 611                 } else if (is_edp(intel_encoder)) {
 612                         lane_count = intel_dp->lane_count;
 613                         break;
 614                 }
 615         }
 616
 617         /*
 618          * Compute the GMCH and Link ratios. The '3' here is
 619          * the number of bytes_per_pixel post-LUT, which we always
 620          * set up for 8-bits of R/G/B, or 3 bytes total.
 621          */
 622         cdv_intel_dp_compute_m_n(bpp, lane_count,
 623                              mode->clock, adjusted_mode->clock, &m_n);
 624
 625         {
 626                 REG_WRITE(PIPE_GMCH_DATA_M(pipe),
 627                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
 628                            m_n.gmch_m);
 629                 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 630                 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 631                 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 632         }
 633 }
 634
 635 static void
 636 cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 637                   struct drm_display_mode *adjusted_mode)
 638 {
 639         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 640         struct drm_crtc *crtc = encoder->crtc;
 641         struct psb_intel_crtc *intel_crtc = to_psb_intel_crtc(crtc);
 642         struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
 643
 644
 645         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 646         intel_dp->DP |= intel_dp->color_range;
 647
 648         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 649                 intel_dp->DP |= DP_SYNC_HS_HIGH;
 650         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 651                 intel_dp->DP |= DP_SYNC_VS_HIGH;
 652
 653         intel_dp->DP |= DP_LINK_TRAIN_OFF;
 654
 655         switch (intel_dp->lane_count) {
 656         case 1:
 657                 intel_dp->DP |= DP_PORT_WIDTH_1;
 658                 break;
 659         case 2:
 660                 intel_dp->DP |= DP_PORT_WIDTH_2;
 661                 break;
 662         case 4:
 663                 intel_dp->DP |= DP_PORT_WIDTH_4;
 664                 break;
 665         }
 666         if (intel_dp->has_audio)
 667                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 668
 669         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 670         intel_dp->link_configuration[0] = intel_dp->link_bw;
 671         intel_dp->link_configuration[1] = intel_dp->lane_count;
 672
 673         /*
 674          * Check for DPCD version > 1.1 and enhanced framing support
 675          */
 676         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 677             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 678                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 679                 intel_dp->DP |= DP_ENHANCED_FRAMING;
 680         }
 681
 682         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
 683         if (intel_crtc->pipe == 1)
 684                 intel_dp->DP |= DP_PIPEB_SELECT;
 685
 686         DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
 687 }
 688
 689
 690 /* If the sink supports it, try to set the power state appropriately */
 691 static void cdv_intel_dp_sink_dpms(struct psb_intel_encoder *encoder, int mode)
 692 {
 693         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 694         int ret, i;
 695
 696         /* Should have a valid DPCD by this point */
 697         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
 698                 return;
 699
 700         if (mode != DRM_MODE_DPMS_ON) {
 701                 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
 702                                                   DP_SET_POWER_D3);
 703                 if (ret != 1)
 704                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
 705         } else {
 706                 /*
 707                  * When turning on, we need to retry for 1ms to give the sink
 708                  * time to wake up.
 709                  */
 710                 for (i = 0; i < 3; i++) {
 711                         ret = cdv_intel_dp_aux_native_write_1(encoder,
 712                                                           DP_SET_POWER,
 713                                                           DP_SET_POWER_D0);
 714                         if (ret == 1)
 715                                 break;
 716                         udelay(1000);
 717                 }
 718         }
 719 }
 720
 721 static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
 722 {
 723         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 724
 725         /* Wake up the sink first */
 726         cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
 727         cdv_intel_dp_link_down(intel_encoder);
 728 }
 729
 730 static void cdv_intel_dp_commit(struct drm_encoder *encoder)
 731 {
 732         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 733
 734         cdv_intel_dp_start_link_train(intel_encoder);
 735         cdv_intel_dp_complete_link_train(intel_encoder);
 736 }
 737
 738 static void
 739 cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
 740 {
 741         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 742         struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
 743         struct drm_device *dev = encoder->dev;
 744         uint32_t dp_reg = REG_READ(intel_dp->output_reg);
 745
 746         if (mode != DRM_MODE_DPMS_ON) {
 747                 cdv_intel_dp_sink_dpms(intel_encoder, mode);
 748                 cdv_intel_dp_link_down(intel_encoder);
 749         } else {
 750                 cdv_intel_dp_sink_dpms(intel_encoder, mode);
 751                 if (!(dp_reg & DP_PORT_EN)) {
 752                         cdv_intel_dp_start_link_train(intel_encoder);
 753                         cdv_intel_dp_complete_link_train(intel_encoder);
 754                 }
 755         }
 756 }
 757
 758 /*
 759  * Native read with retry for link status and receiver capability reads for
 760  * cases where the sink may still be asleep.
 761  */
 762 static bool
 763 cdv_intel_dp_aux_native_read_retry(struct psb_intel_encoder *encoder, uint16_t address,
 764                                uint8_t *recv, int recv_bytes)
 765 {
 766         int ret, i;
 767
 768         /*
 769          * Sinks are *supposed* to come up within 1ms from an off state,
 770          * but we're also supposed to retry 3 times per the spec.
 771          */
 772         for (i = 0; i < 3; i++) {
 773                 ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
 774                                                recv_bytes);
 775                 if (ret == recv_bytes)
 776                         return true;
 777                 udelay(1000);
 778         }
 779
 780         return false;
 781 }
 782
 783 /*
 784  * Fetch AUX CH registers 0x202 - 0x207 which contain
 785  * link status information
 786  */
 787 static bool
 788 cdv_intel_dp_get_link_status(struct psb_intel_encoder *encoder)
 789 {
 790         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 791         return cdv_intel_dp_aux_native_read_retry(encoder,
 792                                               DP_LANE0_1_STATUS,
 793                                               intel_dp->link_status,
 794                                               DP_LINK_STATUS_SIZE);
 795 }
 796
 797 static uint8_t
 798 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 799                      int r)
 800 {
 801         return link_status[r - DP_LANE0_1_STATUS];
 802 }
 803
 804 static uint8_t
 805 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
 806                                  int lane)
 807 {
 808         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 809         int         s = ((lane & 1) ?
 810                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 811                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 812         uint8_t l = cdv_intel_dp_link_status(link_status, i);
 813
 814         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 815 }
 816
 817 static uint8_t
 818 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
 819                                       int lane)
 820 {
 821         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 822         int         s = ((lane & 1) ?
 823                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 824                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 825         uint8_t l = cdv_intel_dp_link_status(link_status, i);
 826
 827         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 828 }
 829
 830
 831 #if 0
 832 static char     *voltage_names[] = {
 833         "0.4V", "0.6V", "0.8V", "1.2V"
 834 };
 835 static char     *pre_emph_names[] = {
 836         "0dB", "3.5dB", "6dB", "9.5dB"
 837 };
 838 static char     *link_train_names[] = {
 839         "pattern 1", "pattern 2", "idle", "off"
 840 };
 841 #endif
 842
 843 #define CDV_DP_VOLTAGE_MAX          DP_TRAIN_VOLTAGE_SWING_1200
 844 /*
 845 static uint8_t
 846 cdv_intel_dp_pre_emphasis_max(uint8_t voltage_swing)
 847 {
 848         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
 849         case DP_TRAIN_VOLTAGE_SWING_400:
 850                 return DP_TRAIN_PRE_EMPHASIS_6;
 851         case DP_TRAIN_VOLTAGE_SWING_600:
 852                 return DP_TRAIN_PRE_EMPHASIS_6;
 853         case DP_TRAIN_VOLTAGE_SWING_800:
 854                 return DP_TRAIN_PRE_EMPHASIS_3_5;
 855         case DP_TRAIN_VOLTAGE_SWING_1200:
 856         default:
 857                 return DP_TRAIN_PRE_EMPHASIS_0;
 858         }
 859 }
 860 */
 861 static void
 862 cdv_intel_get_adjust_train(struct psb_intel_encoder *encoder)
 863 {
 864         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 865         uint8_t v = 0;
 866         uint8_t p = 0;
 867         int lane;
 868
 869         for (lane = 0; lane < intel_dp->lane_count; lane++) {
 870                 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
 871                 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
 872
 873                 if (this_v > v)
 874                         v = this_v;
 875                 if (this_p > p)
 876                         p = this_p;
 877         }
 878
 879         if (v >= CDV_DP_VOLTAGE_MAX)
 880                 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
 881
 882         if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
 883                 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
 884
 885         for (lane = 0; lane < 4; lane++)
 886                 intel_dp->train_set[lane] = v | p;
 887 }
 888
 889
 890 static uint8_t
 891 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
 892                       int lane)
 893 {
 894         int i = DP_LANE0_1_STATUS + (lane >> 1);
 895         int s = (lane & 1) * 4;
 896         uint8_t l = cdv_intel_dp_link_status(link_status, i);
 897
 898         return (l >> s) & 0xf;
 899 }
 900
 901 /* Check for clock recovery is done on all channels */
 902 static bool
 903 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
 904 {
 905         int lane;
 906         uint8_t lane_status;
 907
 908         for (lane = 0; lane < lane_count; lane++) {
 909                 lane_status = cdv_intel_get_lane_status(link_status, lane);
 910                 if ((lane_status & DP_LANE_CR_DONE) == 0)
 911                         return false;
 912         }
 913         return true;
 914 }
 915
 916 /* Check to see if channel eq is done on all channels */
 917 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
 918                          DP_LANE_CHANNEL_EQ_DONE|\
 919                          DP_LANE_SYMBOL_LOCKED)
 920 static bool
 921 cdv_intel_channel_eq_ok(struct psb_intel_encoder *encoder)
 922 {
 923         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 924         uint8_t lane_align;
 925         uint8_t lane_status;
 926         int lane;
 927
 928         lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
 929                                           DP_LANE_ALIGN_STATUS_UPDATED);
 930         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
 931                 return false;
 932         for (lane = 0; lane < intel_dp->lane_count; lane++) {
 933                 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
 934                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
 935                         return false;
 936         }
 937         return true;
 938 }
 939
 940 static bool
 941 cdv_intel_dp_set_link_train(struct psb_intel_encoder *encoder,
 942                         uint32_t dp_reg_value,
 943                         uint8_t dp_train_pat)
 944 {
 945
 946         struct drm_device *dev = encoder->base.dev;
 947         int ret;
 948         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 949
 950         REG_WRITE(intel_dp->output_reg, dp_reg_value);
 951         REG_READ(intel_dp->output_reg);
 952
 953         ret = cdv_intel_dp_aux_native_write_1(encoder,
 954                                     DP_TRAINING_PATTERN_SET,
 955                                     dp_train_pat);
 956
 957         if (ret != 1) {
 958                 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
 959                                 dp_train_pat);
 960                 return false;
 961         }
 962
 963         return true;
 964 }
 965
 966
 967 static bool
 968 cdv_intel_dplink_set_level(struct psb_intel_encoder *encoder,
 969                         uint8_t dp_train_pat)
 970 {
 971
 972         int ret;
 973         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 974
 975         ret = cdv_intel_dp_aux_native_write(encoder,
 976                                         DP_TRAINING_LANE0_SET,
 977                                         intel_dp->train_set,
 978                                         intel_dp->lane_count);
 979
 980         if (ret != intel_dp->lane_count) {
 981                 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
 982                                 intel_dp->train_set[0], intel_dp->lane_count);
 983                 return false;
 984         }
 985         return true;
 986 }
 987
 988 static void
 989 cdv_intel_dp_set_vswing_premph(struct psb_intel_encoder *encoder, uint8_t signal_level)
 990 {
 991         struct drm_device *dev = encoder->base.dev;
 992         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
 993         struct ddi_regoff *ddi_reg;
 994         int vswing, premph, index;
 995
 996         if (intel_dp->output_reg == DP_B)
 997                 ddi_reg = &ddi_DP_train_table[0];
 998         else
 999                 ddi_reg = &ddi_DP_train_table[1];
1000
1001         vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
1002         premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
1003                                 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1004
1005         if (vswing + premph > 3)
1006                 return;
1007 #ifdef CDV_FAST_LINK_TRAIN
1008         return;
1009 #endif
1010         DRM_DEBUG_KMS("Test2\n");
1011         //return ;
1012         cdv_sb_reset(dev);
1013         /* ;Swing voltage programming
1014         ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
1015         cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
1016
1017         /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
1018         cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
1019
1020         /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1021          * The VSwing_PreEmph table is also considered based on the vswing/premp
1022          */
1023         index = (vswing + premph) * 2;
1024         if (premph == 1 && vswing == 1) {
1025                 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
1026         } else
1027                 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1028
1029         /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1030         if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_1200)
1031                 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1032         else
1033                 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
1034
1035         /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
1036         /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
1037
1038         /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
1039         cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
1040
1041         /* ;Pre emphasis programming
1042          * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1043          */
1044         cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
1045
1046         /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1047         index = 2 * premph + 1;
1048         cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
1049         return;
1050 }
1051
1052
1053 /* Enable corresponding port and start training pattern 1 */
1054 static void
1055 cdv_intel_dp_start_link_train(struct psb_intel_encoder *encoder)
1056 {
1057         struct drm_device *dev = encoder->base.dev;
1058         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1059         int i;
1060         uint8_t voltage;
1061         bool clock_recovery = false;
1062         int tries;
1063         u32 reg;
1064         uint32_t DP = intel_dp->DP;
1065
1066         DP |= DP_PORT_EN;
1067         DP &= ~DP_LINK_TRAIN_MASK;
1068
1069         reg = DP;
1070         reg |= DP_LINK_TRAIN_PAT_1;
1071         /* Enable output, wait for it to become active */
1072         REG_WRITE(intel_dp->output_reg, reg);
1073         REG_READ(intel_dp->output_reg);
1074         psb_intel_wait_for_vblank(dev);
1075
1076         DRM_DEBUG_KMS("Link config\n");
1077         /* Write the link configuration data */
1078         cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
1079                                   intel_dp->link_configuration,
1080                                   2);
1081
1082         memset(intel_dp->train_set, 0, 4);
1083         voltage = 0;
1084         tries = 0;
1085         clock_recovery = false;
1086
1087         DRM_DEBUG_KMS("Start train\n");
1088                 reg = DP | DP_LINK_TRAIN_PAT_1;
1089
1090
1091         for (;;) {
1092                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1093
1094                 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
1095                         DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1096                 }
1097                 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1098                 /* Set training pattern 1 */
1099
1100                 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
1101
1102                 udelay(200);
1103                 if (!cdv_intel_dp_get_link_status(encoder))
1104                         break;
1105
1106                 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1107                         DRM_DEBUG_KMS("PT1 train is done\n");
1108                         clock_recovery = true;
1109                         break;
1110                 }
1111
1112                 /* Check to see if we've tried the max voltage */
1113                 for (i = 0; i < intel_dp->lane_count; i++)
1114                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1115                                 break;
1116                 if (i == intel_dp->lane_count)
1117                         break;
1118
1119                 /* Check to see if we've tried the same voltage 5 times */
1120                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1121                         ++tries;
1122                         if (tries == 5)
1123                                 break;
1124                 } else
1125                         tries = 0;
1126                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1127
1128                 /* Compute new intel_dp->train_set as requested by target */
1129                 cdv_intel_get_adjust_train(encoder);
1130
1131         }
1132
1133         if (!clock_recovery) {
1134                 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1135         }
1136
1137         intel_dp->DP = DP;
1138 }
1139
1140 static void
1141 cdv_intel_dp_complete_link_train(struct psb_intel_encoder *encoder)
1142 {
1143         struct drm_device *dev = encoder->base.dev;
1144         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1145         bool channel_eq = false;
1146         int tries, cr_tries;
1147         u32 reg;
1148         uint32_t DP = intel_dp->DP;
1149
1150         /* channel equalization */
1151         tries = 0;
1152         cr_tries = 0;
1153         channel_eq = false;
1154
1155         DRM_DEBUG_KMS("\n");
1156                 reg = DP | DP_LINK_TRAIN_PAT_2;
1157
1158         for (;;) {
1159                 /* channel eq pattern */
1160                 if (!cdv_intel_dp_set_link_train(encoder, reg,
1161                                              DP_TRAINING_PATTERN_2)) {
1162                         DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1163                 }
1164                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1165
1166                 if (cr_tries > 5) {
1167                         DRM_ERROR("failed to train DP, aborting\n");
1168                         cdv_intel_dp_link_down(encoder);
1169                         break;
1170                 }
1171
1172                 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1173
1174                 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
1175
1176                 udelay(1000);
1177                 if (!cdv_intel_dp_get_link_status(encoder))
1178                         break;
1179
1180                 /* Make sure clock is still ok */
1181                 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1182                         cdv_intel_dp_start_link_train(encoder);
1183                         cr_tries++;
1184                         continue;
1185                 }
1186
1187                 if (cdv_intel_channel_eq_ok(encoder)) {
1188                         DRM_DEBUG_KMS("PT2 train is done\n");
1189                         channel_eq = true;
1190                         break;
1191                 }
1192
1193                 /* Try 5 times, then try clock recovery if that fails */
1194                 if (tries > 5) {
1195                         cdv_intel_dp_link_down(encoder);
1196                         cdv_intel_dp_start_link_train(encoder);
1197                         tries = 0;
1198                         cr_tries++;
1199                         continue;
1200                 }
1201
1202                 /* Compute new intel_dp->train_set as requested by target */
1203                 cdv_intel_get_adjust_train(encoder);
1204                 ++tries;
1205
1206         }
1207
1208         reg = DP | DP_LINK_TRAIN_OFF;
1209
1210         REG_WRITE(intel_dp->output_reg, reg);
1211         REG_READ(intel_dp->output_reg);
1212         cdv_intel_dp_aux_native_write_1(encoder,
1213                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1214 }
1215
1216 static void
1217 cdv_intel_dp_link_down(struct psb_intel_encoder *encoder)
1218 {
1219         struct drm_device *dev = encoder->base.dev;
1220         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1221         uint32_t DP = intel_dp->DP;
1222
1223         if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1224                 return;
1225
1226         DRM_DEBUG_KMS("\n");
1227
1228
1229         {
1230                 DP &= ~DP_LINK_TRAIN_MASK;
1231                 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1232         }
1233         REG_READ(intel_dp->output_reg);
1234
1235         msleep(17);
1236
1237         REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1238         REG_READ(intel_dp->output_reg);
1239 }
1240
1241 static enum drm_connector_status
1242 cdv_dp_detect(struct psb_intel_encoder *encoder)
1243 {
1244         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1245         enum drm_connector_status status;
1246
1247         status = connector_status_disconnected;
1248         if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1249                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1250         {
1251                 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1252                         status = connector_status_connected;
1253         }
1254         if (status == connector_status_connected)
1255                 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1256                         intel_dp->dpcd[0], intel_dp->dpcd[1],
1257                         intel_dp->dpcd[2], intel_dp->dpcd[3]);
1258         return status;
1259 }
1260
1261 /**
1262  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1263  *
1264  * \return true if DP port is connected.
1265  * \return false if DP port is disconnected.
1266  */
1267 static enum drm_connector_status
1268 cdv_intel_dp_detect(struct drm_connector *connector, bool force)
1269 {
1270         struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1271         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1272         enum drm_connector_status status;
1273         struct edid *edid = NULL;
1274
1275         intel_dp->has_audio = false;
1276
1277         status = cdv_dp_detect(encoder);
1278         if (status != connector_status_connected)
1279                 return status;
1280
1281         if (intel_dp->force_audio) {
1282                 intel_dp->has_audio = intel_dp->force_audio > 0;
1283         } else {
1284                 edid = drm_get_edid(connector, &intel_dp->adapter);
1285                 if (edid) {
1286                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1287                         connector->display_info.raw_edid = NULL;
1288                         kfree(edid);
1289                 }
1290         }
1291
1292         return connector_status_connected;
1293 }
1294
1295 static int cdv_intel_dp_get_modes(struct drm_connector *connector)
1296 {
1297         struct psb_intel_encoder *intel_encoder = psb_intel_attached_encoder(connector);
1298         struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1299         struct edid *edid = NULL;
1300         int ret = 0;
1301
1302
1303         edid = drm_get_edid(connector, &intel_dp->adapter);
1304         if (edid) {
1305                 drm_mode_connector_update_edid_property(connector, edid);
1306                 ret = drm_add_edid_modes(connector, edid);
1307                 kfree(edid);
1308         }
1309
1310         return ret;
1311 }
1312
1313 static bool
1314 cdv_intel_dp_detect_audio(struct drm_connector *connector)
1315 {
1316         struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1317         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1318         struct edid *edid;
1319         bool has_audio = false;
1320
1321         edid = drm_get_edid(connector, &intel_dp->adapter);
1322         if (edid) {
1323                 has_audio = drm_detect_monitor_audio(edid);
1324
1325                 connector->display_info.raw_edid = NULL;
1326                 kfree(edid);
1327         }
1328
1329         return has_audio;
1330 }
1331
1332 static int
1333 cdv_intel_dp_set_property(struct drm_connector *connector,
1334                       struct drm_property *property,
1335                       uint64_t val)
1336 {
1337         struct drm_psb_private *dev_priv = connector->dev->dev_private;
1338         struct psb_intel_encoder *encoder = psb_intel_attached_encoder(connector);
1339         struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1340         int ret;
1341
1342         ret = drm_connector_property_set_value(connector, property, val);
1343         if (ret)
1344                 return ret;
1345
1346         if (property == dev_priv->force_audio_property) {
1347                 int i = val;
1348                 bool has_audio;
1349
1350                 if (i == intel_dp->force_audio)
1351                         return 0;
1352
1353                 intel_dp->force_audio = i;
1354
1355                 if (i == 0)
1356                         has_audio = cdv_intel_dp_detect_audio(connector);
1357                 else
1358                         has_audio = i > 0;
1359
1360                 if (has_audio == intel_dp->has_audio)
1361                         return 0;
1362
1363                 intel_dp->has_audio = has_audio;
1364                 goto done;
1365         }
1366
1367         if (property == dev_priv->broadcast_rgb_property) {
1368                 if (val == !!intel_dp->color_range)
1369                         return 0;
1370
1371                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1372                 goto done;
1373         }
1374
1375         return -EINVAL;
1376
1377 done:
1378         if (encoder->base.crtc) {
1379                 struct drm_crtc *crtc = encoder->base.crtc;
1380                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1381                                          crtc->x, crtc->y,
1382                                          crtc->fb);
1383         }
1384
1385         return 0;
1386 }
1387
1388 static void
1389 cdv_intel_dp_destroy (struct drm_connector *connector)
1390 {
1391         struct psb_intel_encoder *psb_intel_encoder =
1392                                         psb_intel_attached_encoder(connector);
1393         struct cdv_intel_dp *intel_dp = psb_intel_encoder->dev_priv;
1394
1395         i2c_del_adapter(&intel_dp->adapter);
1396         drm_sysfs_connector_remove(connector);
1397         drm_connector_cleanup(connector);
1398         kfree(connector);
1399 }
1400
1401 static void cdv_intel_dp_encoder_destroy(struct drm_encoder *encoder)
1402 {
1403         drm_encoder_cleanup(encoder);
1404 }
1405
1406 static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
1407         .dpms = cdv_intel_dp_dpms,
1408         .mode_fixup = cdv_intel_dp_mode_fixup,
1409         .prepare = cdv_intel_dp_prepare,
1410         .mode_set = cdv_intel_dp_mode_set,
1411         .commit = cdv_intel_dp_commit,
1412 };
1413
1414 static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
1415         .dpms = drm_helper_connector_dpms,
1416         .detect = cdv_intel_dp_detect,
1417         .fill_modes = drm_helper_probe_single_connector_modes,
1418         .set_property = cdv_intel_dp_set_property,
1419         .destroy = cdv_intel_dp_destroy,
1420 };
1421
1422 static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
1423         .get_modes = cdv_intel_dp_get_modes,
1424         .mode_valid = cdv_intel_dp_mode_valid,
1425         .best_encoder = psb_intel_best_encoder,
1426 };
1427
1428 static const struct drm_encoder_funcs cdv_intel_dp_enc_funcs = {
1429         .destroy = cdv_intel_dp_encoder_destroy,
1430 };
1431
1432
1433 static void cdv_intel_dp_add_properties(struct drm_connector *connector)
1434 {
1435         cdv_intel_attach_force_audio_property(connector);
1436         cdv_intel_attach_broadcast_rgb_property(connector);
1437 }
1438
1439 void
1440 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
1441 {
1442         struct psb_intel_encoder *psb_intel_encoder;
1443         struct psb_intel_connector *psb_intel_connector;
1444         struct drm_connector *connector;
1445         struct drm_encoder *encoder;
1446         struct cdv_intel_dp *intel_dp;
1447         const char *name = NULL;
1448
1449         psb_intel_encoder = kzalloc(sizeof(struct psb_intel_encoder), GFP_KERNEL);
1450         if (!psb_intel_encoder)
1451                 return;
1452         psb_intel_connector = kzalloc(sizeof(struct psb_intel_connector), GFP_KERNEL);
1453         if (!psb_intel_connector)
1454                 goto err_connector;
1455         intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
1456         if (!intel_dp)
1457                 goto err_priv;
1458
1459         connector = &psb_intel_connector->base;
1460         encoder = &psb_intel_encoder->base;
1461
1462         drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
1463         drm_encoder_init(dev, encoder, &cdv_intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS);
1464
1465         psb_intel_connector_attach_encoder(psb_intel_connector, psb_intel_encoder);
1466         psb_intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1467
1468         psb_intel_encoder->dev_priv=intel_dp;
1469         intel_dp->encoder = psb_intel_encoder;
1470         intel_dp->output_reg = output_reg;
1471
1472         drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
1473         drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
1474
1475         connector->polled = DRM_CONNECTOR_POLL_HPD;
1476         connector->interlace_allowed = false;
1477         connector->doublescan_allowed = false;
1478
1479         drm_sysfs_connector_add(connector);
1480
1481         /* Set up the DDC bus. */
1482         switch (output_reg) {
1483                 case DP_B:
1484                         name = "DPDDC-B";
1485                         psb_intel_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
1486                         break;
1487                 case DP_C:
1488                         name = "DPDDC-C";
1489                         psb_intel_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
1490                         break;
1491         }
1492
1493         cdv_intel_dp_i2c_init(psb_intel_connector, psb_intel_encoder, name);
1494         /* FIXME:fail check */
1495         cdv_intel_dp_add_properties(connector);
1496         return;
1497
1498 err_priv:
1499         kfree(psb_intel_connector);
1500 err_connector:
1501         kfree(psb_intel_encoder);
1502 }