drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static char get_active_flag(struct drm_i915_gem_object *obj)
  93 {
  94         return obj->active ? '*' : ' ';
  95 }
  96
  97 static char get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         return obj->pin_display ? 'p' : ' ';
 100 }
 101
 102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 103 {
 104         switch (obj->tiling_mode) {
 105         default:
 106         case I915_TILING_NONE: return ' ';
 107         case I915_TILING_X: return 'X';
 108         case I915_TILING_Y: return 'Y';
 109         }
 110 }
 111
 112 static char get_global_flag(struct drm_i915_gem_object *obj)
 113 {
 114         return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
 115 }
 116
 117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->mapping ? 'M' : ' ';
 120 }
 121
 122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 123 {
 124         u64 size = 0;
 125         struct i915_vma *vma;
 126
 127         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 128                 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
 129                         size += vma->node.size;
 130         }
 131
 132         return size;
 133 }
 134
 135 static void
 136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 137 {
 138         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 139         struct intel_engine_cs *engine;
 140         struct i915_vma *vma;
 141         int pin_count = 0;
 142         enum intel_engine_id id;
 143
 144         lockdep_assert_held(&obj->base.dev->struct_mutex);
 145
 146         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 147                    &obj->base,
 148                    get_active_flag(obj),
 149                    get_pin_flag(obj),
 150                    get_tiling_flag(obj),
 151                    get_global_flag(obj),
 152                    get_pin_mapped_flag(obj),
 153                    obj->base.size / 1024,
 154                    obj->base.read_domains,
 155                    obj->base.write_domain);
 156         for_each_engine_id(engine, dev_priv, id)
 157                 seq_printf(m, "%x ",
 158                                 i915_gem_request_get_seqno(obj->last_read_req[id]));
 159         seq_printf(m, "] %x %x%s%s%s",
 160                    i915_gem_request_get_seqno(obj->last_write_req),
 161                    i915_gem_request_get_seqno(obj->last_fenced_req),
 162                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 163                    obj->dirty ? " dirty" : "",
 164                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 165         if (obj->base.name)
 166                 seq_printf(m, " (name: %d)", obj->base.name);
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (vma->pin_count > 0)
 169                         pin_count++;
 170         }
 171         seq_printf(m, " (pinned x %d)", pin_count);
 172         if (obj->pin_display)
 173                 seq_printf(m, " (display)");
 174         if (obj->fence_reg != I915_FENCE_REG_NONE)
 175                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 176         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 177                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 178                            vma->is_ggtt ? "g" : "pp",
 179                            vma->node.start, vma->node.size);
 180                 if (vma->is_ggtt)
 181                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 182                 seq_puts(m, ")");
 183         }
 184         if (obj->stolen)
 185                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 186         if (obj->pin_display || obj->fault_mappable) {
 187                 char s[3], *t = s;
 188                 if (obj->pin_display)
 189                         *t++ = 'p';
 190                 if (obj->fault_mappable)
 191                         *t++ = 'f';
 192                 *t = '\0';
 193                 seq_printf(m, " (%s mappable)", s);
 194         }
 195         if (obj->last_write_req != NULL)
 196                 seq_printf(m, " (%s)",
 197                            i915_gem_request_get_engine(obj->last_write_req)->name);
 198         if (obj->frontbuffer_bits)
 199                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 200 }
 201
 202 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 203 {
 204         struct drm_info_node *node = m->private;
 205         uintptr_t list = (uintptr_t) node->info_ent->data;
 206         struct list_head *head;
 207         struct drm_device *dev = node->minor->dev;
 208         struct drm_i915_private *dev_priv = to_i915(dev);
 209         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 210         struct i915_vma *vma;
 211         u64 total_obj_size, total_gtt_size;
 212         int count, ret;
 213
 214         ret = mutex_lock_interruptible(&dev->struct_mutex);
 215         if (ret)
 216                 return ret;
 217
 218         /* FIXME: the user of this interface might want more than just GGTT */
 219         switch (list) {
 220         case ACTIVE_LIST:
 221                 seq_puts(m, "Active:\n");
 222                 head = &ggtt->base.active_list;
 223                 break;
 224         case INACTIVE_LIST:
 225                 seq_puts(m, "Inactive:\n");
 226                 head = &ggtt->base.inactive_list;
 227                 break;
 228         default:
 229                 mutex_unlock(&dev->struct_mutex);
 230                 return -EINVAL;
 231         }
 232
 233         total_obj_size = total_gtt_size = count = 0;
 234         list_for_each_entry(vma, head, vm_link) {
 235                 seq_printf(m, "   ");
 236                 describe_obj(m, vma->obj);
 237                 seq_printf(m, "\n");
 238                 total_obj_size += vma->obj->base.size;
 239                 total_gtt_size += vma->node.size;
 240                 count++;
 241         }
 242         mutex_unlock(&dev->struct_mutex);
 243
 244         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 245                    count, total_obj_size, total_gtt_size);
 246         return 0;
 247 }
 248
 249 static int obj_rank_by_stolen(void *priv,
 250                               struct list_head *A, struct list_head *B)
 251 {
 252         struct drm_i915_gem_object *a =
 253                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 254         struct drm_i915_gem_object *b =
 255                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 256
 257         if (a->stolen->start < b->stolen->start)
 258                 return -1;
 259         if (a->stolen->start > b->stolen->start)
 260                 return 1;
 261         return 0;
 262 }
 263
 264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 265 {
 266         struct drm_info_node *node = m->private;
 267         struct drm_device *dev = node->minor->dev;
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269         struct drm_i915_gem_object *obj;
 270         u64 total_obj_size, total_gtt_size;
 271         LIST_HEAD(stolen);
 272         int count, ret;
 273
 274         ret = mutex_lock_interruptible(&dev->struct_mutex);
 275         if (ret)
 276                 return ret;
 277
 278         total_obj_size = total_gtt_size = count = 0;
 279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 list_add(&obj->obj_exec_link, &stolen);
 284
 285                 total_obj_size += obj->base.size;
 286                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 287                 count++;
 288         }
 289         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 list_add(&obj->obj_exec_link, &stolen);
 294
 295                 total_obj_size += obj->base.size;
 296                 count++;
 297         }
 298         list_sort(NULL, &stolen, obj_rank_by_stolen);
 299         seq_puts(m, "Stolen:\n");
 300         while (!list_empty(&stolen)) {
 301                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 302                 seq_puts(m, "   ");
 303                 describe_obj(m, obj);
 304                 seq_putc(m, '\n');
 305                 list_del_init(&obj->obj_exec_link);
 306         }
 307         mutex_unlock(&dev->struct_mutex);
 308
 309         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 310                    count, total_obj_size, total_gtt_size);
 311         return 0;
 312 }
 313
 314 #define count_objects(list, member) do { \
 315         list_for_each_entry(obj, list, member) { \
 316                 size += i915_gem_obj_total_ggtt_size(obj); \
 317                 ++count; \
 318                 if (obj->map_and_fenceable) { \
 319                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 320                         ++mappable_count; \
 321                 } \
 322         } \
 323 } while (0)
 324
 325 struct file_stats {
 326         struct drm_i915_file_private *file_priv;
 327         unsigned long count;
 328         u64 total, unbound;
 329         u64 global, shared;
 330         u64 active, inactive;
 331 };
 332
 333 static int per_file_stats(int id, void *ptr, void *data)
 334 {
 335         struct drm_i915_gem_object *obj = ptr;
 336         struct file_stats *stats = data;
 337         struct i915_vma *vma;
 338
 339         stats->count++;
 340         stats->total += obj->base.size;
 341
 342         if (obj->base.name || obj->base.dma_buf)
 343                 stats->shared += obj->base.size;
 344
 345         if (USES_FULL_PPGTT(obj->base.dev)) {
 346                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
 347                         struct i915_hw_ppgtt *ppgtt;
 348
 349                         if (!drm_mm_node_allocated(&vma->node))
 350                                 continue;
 351
 352                         if (vma->is_ggtt) {
 353                                 stats->global += obj->base.size;
 354                                 continue;
 355                         }
 356
 357                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 358                         if (ppgtt->file_priv != stats->file_priv)
 359                                 continue;
 360
 361                         if (obj->active) /* XXX per-vma statistic */
 362                                 stats->active += obj->base.size;
 363                         else
 364                                 stats->inactive += obj->base.size;
 365
 366                         return 0;
 367                 }
 368         } else {
 369                 if (i915_gem_obj_ggtt_bound(obj)) {
 370                         stats->global += obj->base.size;
 371                         if (obj->active)
 372                                 stats->active += obj->base.size;
 373                         else
 374                                 stats->inactive += obj->base.size;
 375                         return 0;
 376                 }
 377         }
 378
 379         if (!list_empty(&obj->global_list))
 380                 stats->unbound += obj->base.size;
 381
 382         return 0;
 383 }
 384
 385 #define print_file_stats(m, name, stats) do { \
 386         if (stats.count) \
 387                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 388                            name, \
 389                            stats.count, \
 390                            stats.total, \
 391                            stats.active, \
 392                            stats.inactive, \
 393                            stats.global, \
 394                            stats.shared, \
 395                            stats.unbound); \
 396 } while (0)
 397
 398 static void print_batch_pool_stats(struct seq_file *m,
 399                                    struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         struct file_stats stats;
 403         struct intel_engine_cs *engine;
 404         int j;
 405
 406         memset(&stats, 0, sizeof(stats));
 407
 408         for_each_engine(engine, dev_priv) {
 409                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 410                         list_for_each_entry(obj,
 411                                             &engine->batch_pool.cache_list[j],
 412                                             batch_pool_link)
 413                                 per_file_stats(0, obj, &stats);
 414                 }
 415         }
 416
 417         print_file_stats(m, "[k]batch pool", stats);
 418 }
 419
 420 static int per_file_ctx_stats(int id, void *ptr, void *data)
 421 {
 422         struct i915_gem_context *ctx = ptr;
 423         int n;
 424
 425         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 426                 if (ctx->engine[n].state)
 427                         per_file_stats(0, ctx->engine[n].state, data);
 428                 if (ctx->engine[n].ringbuf)
 429                         per_file_stats(0, ctx->engine[n].ringbuf->obj, data);
 430         }
 431
 432         return 0;
 433 }
 434
 435 static void print_context_stats(struct seq_file *m,
 436                                 struct drm_i915_private *dev_priv)
 437 {
 438         struct file_stats stats;
 439         struct drm_file *file;
 440
 441         memset(&stats, 0, sizeof(stats));
 442
 443         mutex_lock(&dev_priv->dev->struct_mutex);
 444         if (dev_priv->kernel_context)
 445                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 446
 447         list_for_each_entry(file, &dev_priv->dev->filelist, lhead) {
 448                 struct drm_i915_file_private *fpriv = file->driver_priv;
 449                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 450         }
 451         mutex_unlock(&dev_priv->dev->struct_mutex);
 452
 453         print_file_stats(m, "[k]contexts", stats);
 454 }
 455
 456 #define count_vmas(list, member) do { \
 457         list_for_each_entry(vma, list, member) { \
 458                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 459                 ++count; \
 460                 if (vma->obj->map_and_fenceable) { \
 461                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 462                         ++mappable_count; \
 463                 } \
 464         } \
 465 } while (0)
 466
 467 static int i915_gem_object_info(struct seq_file *m, void* data)
 468 {
 469         struct drm_info_node *node = m->private;
 470         struct drm_device *dev = node->minor->dev;
 471         struct drm_i915_private *dev_priv = to_i915(dev);
 472         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 473         u32 count, mappable_count, purgeable_count;
 474         u64 size, mappable_size, purgeable_size;
 475         unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
 476         u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
 477         struct drm_i915_gem_object *obj;
 478         struct drm_file *file;
 479         struct i915_vma *vma;
 480         int ret;
 481
 482         ret = mutex_lock_interruptible(&dev->struct_mutex);
 483         if (ret)
 484                 return ret;
 485
 486         seq_printf(m, "%u objects, %zu bytes\n",
 487                    dev_priv->mm.object_count,
 488                    dev_priv->mm.object_memory);
 489
 490         size = count = mappable_size = mappable_count = 0;
 491         count_objects(&dev_priv->mm.bound_list, global_list);
 492         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 493                    count, mappable_count, size, mappable_size);
 494
 495         size = count = mappable_size = mappable_count = 0;
 496         count_vmas(&ggtt->base.active_list, vm_link);
 497         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 498                    count, mappable_count, size, mappable_size);
 499
 500         size = count = mappable_size = mappable_count = 0;
 501         count_vmas(&ggtt->base.inactive_list, vm_link);
 502         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 503                    count, mappable_count, size, mappable_size);
 504
 505         size = count = purgeable_size = purgeable_count = 0;
 506         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 507                 size += obj->base.size, ++count;
 508                 if (obj->madv == I915_MADV_DONTNEED)
 509                         purgeable_size += obj->base.size, ++purgeable_count;
 510                 if (obj->mapping) {
 511                         pin_mapped_count++;
 512                         pin_mapped_size += obj->base.size;
 513                         if (obj->pages_pin_count == 0) {
 514                                 pin_mapped_purgeable_count++;
 515                                 pin_mapped_purgeable_size += obj->base.size;
 516                         }
 517                 }
 518         }
 519         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 520
 521         size = count = mappable_size = mappable_count = 0;
 522         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 523                 if (obj->fault_mappable) {
 524                         size += i915_gem_obj_ggtt_size(obj);
 525                         ++count;
 526                 }
 527                 if (obj->pin_display) {
 528                         mappable_size += i915_gem_obj_ggtt_size(obj);
 529                         ++mappable_count;
 530                 }
 531                 if (obj->madv == I915_MADV_DONTNEED) {
 532                         purgeable_size += obj->base.size;
 533                         ++purgeable_count;
 534                 }
 535                 if (obj->mapping) {
 536                         pin_mapped_count++;
 537                         pin_mapped_size += obj->base.size;
 538                         if (obj->pages_pin_count == 0) {
 539                                 pin_mapped_purgeable_count++;
 540                                 pin_mapped_purgeable_size += obj->base.size;
 541                         }
 542                 }
 543         }
 544         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 545                    purgeable_count, purgeable_size);
 546         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 547                    mappable_count, mappable_size);
 548         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 549                    count, size);
 550         seq_printf(m,
 551                    "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
 552                    pin_mapped_count, pin_mapped_purgeable_count,
 553                    pin_mapped_size, pin_mapped_purgeable_size);
 554
 555         seq_printf(m, "%llu [%llu] gtt total\n",
 556                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 557
 558         seq_putc(m, '\n');
 559         print_batch_pool_stats(m, dev_priv);
 560         mutex_unlock(&dev->struct_mutex);
 561
 562         mutex_lock(&dev->filelist_mutex);
 563         print_context_stats(m, dev_priv);
 564         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 565                 struct file_stats stats;
 566                 struct task_struct *task;
 567
 568                 memset(&stats, 0, sizeof(stats));
 569                 stats.file_priv = file->driver_priv;
 570                 spin_lock(&file->table_lock);
 571                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 572                 spin_unlock(&file->table_lock);
 573                 /*
 574                  * Although we have a valid reference on file->pid, that does
 575                  * not guarantee that the task_struct who called get_pid() is
 576                  * still alive (e.g. get_pid(current) => fork() => exit()).
 577                  * Therefore, we need to protect this ->comm access using RCU.
 578                  */
 579                 rcu_read_lock();
 580                 task = pid_task(file->pid, PIDTYPE_PID);
 581                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 582                 rcu_read_unlock();
 583         }
 584         mutex_unlock(&dev->filelist_mutex);
 585
 586         return 0;
 587 }
 588
 589 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 590 {
 591         struct drm_info_node *node = m->private;
 592         struct drm_device *dev = node->minor->dev;
 593         uintptr_t list = (uintptr_t) node->info_ent->data;
 594         struct drm_i915_private *dev_priv = dev->dev_private;
 595         struct drm_i915_gem_object *obj;
 596         u64 total_obj_size, total_gtt_size;
 597         int count, ret;
 598
 599         ret = mutex_lock_interruptible(&dev->struct_mutex);
 600         if (ret)
 601                 return ret;
 602
 603         total_obj_size = total_gtt_size = count = 0;
 604         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 605                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 606                         continue;
 607
 608                 seq_puts(m, "   ");
 609                 describe_obj(m, obj);
 610                 seq_putc(m, '\n');
 611                 total_obj_size += obj->base.size;
 612                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 613                 count++;
 614         }
 615
 616         mutex_unlock(&dev->struct_mutex);
 617
 618         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 619                    count, total_obj_size, total_gtt_size);
 620
 621         return 0;
 622 }
 623
 624 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 625 {
 626         struct drm_info_node *node = m->private;
 627         struct drm_device *dev = node->minor->dev;
 628         struct drm_i915_private *dev_priv = dev->dev_private;
 629         struct intel_crtc *crtc;
 630         int ret;
 631
 632         ret = mutex_lock_interruptible(&dev->struct_mutex);
 633         if (ret)
 634                 return ret;
 635
 636         for_each_intel_crtc(dev, crtc) {
 637                 const char pipe = pipe_name(crtc->pipe);
 638                 const char plane = plane_name(crtc->plane);
 639                 struct intel_flip_work *work;
 640
 641                 spin_lock_irq(&dev->event_lock);
 642                 work = crtc->flip_work;
 643                 if (work == NULL) {
 644                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 645                                    pipe, plane);
 646                 } else {
 647                         u32 pending;
 648                         u32 addr;
 649
 650                         pending = atomic_read(&work->pending);
 651                         if (pending) {
 652                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 653                                            pipe, plane);
 654                         } else {
 655                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 656                                            pipe, plane);
 657                         }
 658                         if (work->flip_queued_req) {
 659                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 660
 661                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 662                                            engine->name,
 663                                            i915_gem_request_get_seqno(work->flip_queued_req),
 664                                            dev_priv->next_seqno,
 665                                            engine->get_seqno(engine),
 666                                            i915_gem_request_completed(work->flip_queued_req, true));
 667                         } else
 668                                 seq_printf(m, "Flip not associated with any ring\n");
 669                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 670                                    work->flip_queued_vblank,
 671                                    work->flip_ready_vblank,
 672                                    intel_crtc_get_vblank_counter(crtc));
 673                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 674
 675                         if (INTEL_INFO(dev)->gen >= 4)
 676                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 677                         else
 678                                 addr = I915_READ(DSPADDR(crtc->plane));
 679                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 680
 681                         if (work->pending_flip_obj) {
 682                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 683                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 684                         }
 685                 }
 686                 spin_unlock_irq(&dev->event_lock);
 687         }
 688
 689         mutex_unlock(&dev->struct_mutex);
 690
 691         return 0;
 692 }
 693
 694 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 695 {
 696         struct drm_info_node *node = m->private;
 697         struct drm_device *dev = node->minor->dev;
 698         struct drm_i915_private *dev_priv = dev->dev_private;
 699         struct drm_i915_gem_object *obj;
 700         struct intel_engine_cs *engine;
 701         int total = 0;
 702         int ret, j;
 703
 704         ret = mutex_lock_interruptible(&dev->struct_mutex);
 705         if (ret)
 706                 return ret;
 707
 708         for_each_engine(engine, dev_priv) {
 709                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 710                         int count;
 711
 712                         count = 0;
 713                         list_for_each_entry(obj,
 714                                             &engine->batch_pool.cache_list[j],
 715                                             batch_pool_link)
 716                                 count++;
 717                         seq_printf(m, "%s cache[%d]: %d objects\n",
 718                                    engine->name, j, count);
 719
 720                         list_for_each_entry(obj,
 721                                             &engine->batch_pool.cache_list[j],
 722                                             batch_pool_link) {
 723                                 seq_puts(m, "   ");
 724                                 describe_obj(m, obj);
 725                                 seq_putc(m, '\n');
 726                         }
 727
 728                         total += count;
 729                 }
 730         }
 731
 732         seq_printf(m, "total: %d\n", total);
 733
 734         mutex_unlock(&dev->struct_mutex);
 735
 736         return 0;
 737 }
 738
 739 static int i915_gem_request_info(struct seq_file *m, void *data)
 740 {
 741         struct drm_info_node *node = m->private;
 742         struct drm_device *dev = node->minor->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct intel_engine_cs *engine;
 745         struct drm_i915_gem_request *req;
 746         int ret, any;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751
 752         any = 0;
 753         for_each_engine(engine, dev_priv) {
 754                 int count;
 755
 756                 count = 0;
 757                 list_for_each_entry(req, &engine->request_list, list)
 758                         count++;
 759                 if (count == 0)
 760                         continue;
 761
 762                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 763                 list_for_each_entry(req, &engine->request_list, list) {
 764                         struct task_struct *task;
 765
 766                         rcu_read_lock();
 767                         task = NULL;
 768                         if (req->pid)
 769                                 task = pid_task(req->pid, PIDTYPE_PID);
 770                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 771                                    req->seqno,
 772                                    (int) (jiffies - req->emitted_jiffies),
 773                                    task ? task->comm : "<unknown>",
 774                                    task ? task->pid : -1);
 775                         rcu_read_unlock();
 776                 }
 777
 778                 any++;
 779         }
 780         mutex_unlock(&dev->struct_mutex);
 781
 782         if (any == 0)
 783                 seq_puts(m, "No requests\n");
 784
 785         return 0;
 786 }
 787
 788 static void i915_ring_seqno_info(struct seq_file *m,
 789                                  struct intel_engine_cs *engine)
 790 {
 791         seq_printf(m, "Current sequence (%s): %x\n",
 792                    engine->name, engine->get_seqno(engine));
 793         seq_printf(m, "Current user interrupts (%s): %x\n",
 794                    engine->name, READ_ONCE(engine->user_interrupts));
 795 }
 796
 797 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 798 {
 799         struct drm_info_node *node = m->private;
 800         struct drm_device *dev = node->minor->dev;
 801         struct drm_i915_private *dev_priv = dev->dev_private;
 802         struct intel_engine_cs *engine;
 803         int ret;
 804
 805         ret = mutex_lock_interruptible(&dev->struct_mutex);
 806         if (ret)
 807                 return ret;
 808         intel_runtime_pm_get(dev_priv);
 809
 810         for_each_engine(engine, dev_priv)
 811                 i915_ring_seqno_info(m, engine);
 812
 813         intel_runtime_pm_put(dev_priv);
 814         mutex_unlock(&dev->struct_mutex);
 815
 816         return 0;
 817 }
 818
 819
 820 static int i915_interrupt_info(struct seq_file *m, void *data)
 821 {
 822         struct drm_info_node *node = m->private;
 823         struct drm_device *dev = node->minor->dev;
 824         struct drm_i915_private *dev_priv = dev->dev_private;
 825         struct intel_engine_cs *engine;
 826         int ret, i, pipe;
 827
 828         ret = mutex_lock_interruptible(&dev->struct_mutex);
 829         if (ret)
 830                 return ret;
 831         intel_runtime_pm_get(dev_priv);
 832
 833         if (IS_CHERRYVIEW(dev)) {
 834                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 835                            I915_READ(GEN8_MASTER_IRQ));
 836
 837                 seq_printf(m, "Display IER:\t%08x\n",
 838                            I915_READ(VLV_IER));
 839                 seq_printf(m, "Display IIR:\t%08x\n",
 840                            I915_READ(VLV_IIR));
 841                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 842                            I915_READ(VLV_IIR_RW));
 843                 seq_printf(m, "Display IMR:\t%08x\n",
 844                            I915_READ(VLV_IMR));
 845                 for_each_pipe(dev_priv, pipe)
 846                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 847                                    pipe_name(pipe),
 848                                    I915_READ(PIPESTAT(pipe)));
 849
 850                 seq_printf(m, "Port hotplug:\t%08x\n",
 851                            I915_READ(PORT_HOTPLUG_EN));
 852                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 853                            I915_READ(VLV_DPFLIPSTAT));
 854                 seq_printf(m, "DPINVGTT:\t%08x\n",
 855                            I915_READ(DPINVGTT));
 856
 857                 for (i = 0; i < 4; i++) {
 858                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 859                                    i, I915_READ(GEN8_GT_IMR(i)));
 860                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 861                                    i, I915_READ(GEN8_GT_IIR(i)));
 862                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 863                                    i, I915_READ(GEN8_GT_IER(i)));
 864                 }
 865
 866                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 867                            I915_READ(GEN8_PCU_IMR));
 868                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 869                            I915_READ(GEN8_PCU_IIR));
 870                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 871                            I915_READ(GEN8_PCU_IER));
 872         } else if (INTEL_INFO(dev)->gen >= 8) {
 873                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 874                            I915_READ(GEN8_MASTER_IRQ));
 875
 876                 for (i = 0; i < 4; i++) {
 877                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 878                                    i, I915_READ(GEN8_GT_IMR(i)));
 879                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 880                                    i, I915_READ(GEN8_GT_IIR(i)));
 881                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 882                                    i, I915_READ(GEN8_GT_IER(i)));
 883                 }
 884
 885                 for_each_pipe(dev_priv, pipe) {
 886                         enum intel_display_power_domain power_domain;
 887
 888                         power_domain = POWER_DOMAIN_PIPE(pipe);
 889                         if (!intel_display_power_get_if_enabled(dev_priv,
 890                                                                 power_domain)) {
 891                                 seq_printf(m, "Pipe %c power disabled\n",
 892                                            pipe_name(pipe));
 893                                 continue;
 894                         }
 895                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 896                                    pipe_name(pipe),
 897                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 898                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 899                                    pipe_name(pipe),
 900                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 901                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 902                                    pipe_name(pipe),
 903                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 904
 905                         intel_display_power_put(dev_priv, power_domain);
 906                 }
 907
 908                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 909                            I915_READ(GEN8_DE_PORT_IMR));
 910                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 911                            I915_READ(GEN8_DE_PORT_IIR));
 912                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 913                            I915_READ(GEN8_DE_PORT_IER));
 914
 915                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 916                            I915_READ(GEN8_DE_MISC_IMR));
 917                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 918                            I915_READ(GEN8_DE_MISC_IIR));
 919                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 920                            I915_READ(GEN8_DE_MISC_IER));
 921
 922                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 923                            I915_READ(GEN8_PCU_IMR));
 924                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 925                            I915_READ(GEN8_PCU_IIR));
 926                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 927                            I915_READ(GEN8_PCU_IER));
 928         } else if (IS_VALLEYVIEW(dev)) {
 929                 seq_printf(m, "Display IER:\t%08x\n",
 930                            I915_READ(VLV_IER));
 931                 seq_printf(m, "Display IIR:\t%08x\n",
 932                            I915_READ(VLV_IIR));
 933                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 934                            I915_READ(VLV_IIR_RW));
 935                 seq_printf(m, "Display IMR:\t%08x\n",
 936                            I915_READ(VLV_IMR));
 937                 for_each_pipe(dev_priv, pipe)
 938                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 939                                    pipe_name(pipe),
 940                                    I915_READ(PIPESTAT(pipe)));
 941
 942                 seq_printf(m, "Master IER:\t%08x\n",
 943                            I915_READ(VLV_MASTER_IER));
 944
 945                 seq_printf(m, "Render IER:\t%08x\n",
 946                            I915_READ(GTIER));
 947                 seq_printf(m, "Render IIR:\t%08x\n",
 948                            I915_READ(GTIIR));
 949                 seq_printf(m, "Render IMR:\t%08x\n",
 950                            I915_READ(GTIMR));
 951
 952                 seq_printf(m, "PM IER:\t\t%08x\n",
 953                            I915_READ(GEN6_PMIER));
 954                 seq_printf(m, "PM IIR:\t\t%08x\n",
 955                            I915_READ(GEN6_PMIIR));
 956                 seq_printf(m, "PM IMR:\t\t%08x\n",
 957                            I915_READ(GEN6_PMIMR));
 958
 959                 seq_printf(m, "Port hotplug:\t%08x\n",
 960                            I915_READ(PORT_HOTPLUG_EN));
 961                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 962                            I915_READ(VLV_DPFLIPSTAT));
 963                 seq_printf(m, "DPINVGTT:\t%08x\n",
 964                            I915_READ(DPINVGTT));
 965
 966         } else if (!HAS_PCH_SPLIT(dev)) {
 967                 seq_printf(m, "Interrupt enable:    %08x\n",
 968                            I915_READ(IER));
 969                 seq_printf(m, "Interrupt identity:  %08x\n",
 970                            I915_READ(IIR));
 971                 seq_printf(m, "Interrupt mask:      %08x\n",
 972                            I915_READ(IMR));
 973                 for_each_pipe(dev_priv, pipe)
 974                         seq_printf(m, "Pipe %c stat:         %08x\n",
 975                                    pipe_name(pipe),
 976                                    I915_READ(PIPESTAT(pipe)));
 977         } else {
 978                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 979                            I915_READ(DEIER));
 980                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 981                            I915_READ(DEIIR));
 982                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 983                            I915_READ(DEIMR));
 984                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 985                            I915_READ(SDEIER));
 986                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 987                            I915_READ(SDEIIR));
 988                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 989                            I915_READ(SDEIMR));
 990                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 991                            I915_READ(GTIER));
 992                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 993                            I915_READ(GTIIR));
 994                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 995                            I915_READ(GTIMR));
 996         }
 997         for_each_engine(engine, dev_priv) {
 998                 if (INTEL_INFO(dev)->gen >= 6) {
 999                         seq_printf(m,
1000                                    "Graphics Interrupt mask (%s):       %08x\n",
1001                                    engine->name, I915_READ_IMR(engine));
1002                 }
1003                 i915_ring_seqno_info(m, engine);
1004         }
1005         intel_runtime_pm_put(dev_priv);
1006         mutex_unlock(&dev->struct_mutex);
1007
1008         return 0;
1009 }
1010
1011 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1012 {
1013         struct drm_info_node *node = m->private;
1014         struct drm_device *dev = node->minor->dev;
1015         struct drm_i915_private *dev_priv = dev->dev_private;
1016         int i, ret;
1017
1018         ret = mutex_lock_interruptible(&dev->struct_mutex);
1019         if (ret)
1020                 return ret;
1021
1022         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1023         for (i = 0; i < dev_priv->num_fence_regs; i++) {
1024                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1025
1026                 seq_printf(m, "Fence %d, pin count = %d, object = ",
1027                            i, dev_priv->fence_regs[i].pin_count);
1028                 if (obj == NULL)
1029                         seq_puts(m, "unused");
1030                 else
1031                         describe_obj(m, obj);
1032                 seq_putc(m, '\n');
1033         }
1034
1035         mutex_unlock(&dev->struct_mutex);
1036         return 0;
1037 }
1038
1039 static int i915_hws_info(struct seq_file *m, void *data)
1040 {
1041         struct drm_info_node *node = m->private;
1042         struct drm_device *dev = node->minor->dev;
1043         struct drm_i915_private *dev_priv = dev->dev_private;
1044         struct intel_engine_cs *engine;
1045         const u32 *hws;
1046         int i;
1047
1048         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1049         hws = engine->status_page.page_addr;
1050         if (hws == NULL)
1051                 return 0;
1052
1053         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1054                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1055                            i * 4,
1056                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1057         }
1058         return 0;
1059 }
1060
1061 static ssize_t
1062 i915_error_state_write(struct file *filp,
1063                        const char __user *ubuf,
1064                        size_t cnt,
1065                        loff_t *ppos)
1066 {
1067         struct i915_error_state_file_priv *error_priv = filp->private_data;
1068         struct drm_device *dev = error_priv->dev;
1069         int ret;
1070
1071         DRM_DEBUG_DRIVER("Resetting error state\n");
1072
1073         ret = mutex_lock_interruptible(&dev->struct_mutex);
1074         if (ret)
1075                 return ret;
1076
1077         i915_destroy_error_state(dev);
1078         mutex_unlock(&dev->struct_mutex);
1079
1080         return cnt;
1081 }
1082
1083 static int i915_error_state_open(struct inode *inode, struct file *file)
1084 {
1085         struct drm_device *dev = inode->i_private;
1086         struct i915_error_state_file_priv *error_priv;
1087
1088         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1089         if (!error_priv)
1090                 return -ENOMEM;
1091
1092         error_priv->dev = dev;
1093
1094         i915_error_state_get(dev, error_priv);
1095
1096         file->private_data = error_priv;
1097
1098         return 0;
1099 }
1100
1101 static int i915_error_state_release(struct inode *inode, struct file *file)
1102 {
1103         struct i915_error_state_file_priv *error_priv = file->private_data;
1104
1105         i915_error_state_put(error_priv);
1106         kfree(error_priv);
1107
1108         return 0;
1109 }
1110
1111 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1112                                      size_t count, loff_t *pos)
1113 {
1114         struct i915_error_state_file_priv *error_priv = file->private_data;
1115         struct drm_i915_error_state_buf error_str;
1116         loff_t tmp_pos = 0;
1117         ssize_t ret_count = 0;
1118         int ret;
1119
1120         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1121         if (ret)
1122                 return ret;
1123
1124         ret = i915_error_state_to_str(&error_str, error_priv);
1125         if (ret)
1126                 goto out;
1127
1128         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1129                                             error_str.buf,
1130                                             error_str.bytes);
1131
1132         if (ret_count < 0)
1133                 ret = ret_count;
1134         else
1135                 *pos = error_str.start + ret_count;
1136 out:
1137         i915_error_state_buf_release(&error_str);
1138         return ret ?: ret_count;
1139 }
1140
1141 static const struct file_operations i915_error_state_fops = {
1142         .owner = THIS_MODULE,
1143         .open = i915_error_state_open,
1144         .read = i915_error_state_read,
1145         .write = i915_error_state_write,
1146         .llseek = default_llseek,
1147         .release = i915_error_state_release,
1148 };
1149
1150 static int
1151 i915_next_seqno_get(void *data, u64 *val)
1152 {
1153         struct drm_device *dev = data;
1154         struct drm_i915_private *dev_priv = dev->dev_private;
1155         int ret;
1156
1157         ret = mutex_lock_interruptible(&dev->struct_mutex);
1158         if (ret)
1159                 return ret;
1160
1161         *val = dev_priv->next_seqno;
1162         mutex_unlock(&dev->struct_mutex);
1163
1164         return 0;
1165 }
1166
1167 static int
1168 i915_next_seqno_set(void *data, u64 val)
1169 {
1170         struct drm_device *dev = data;
1171         int ret;
1172
1173         ret = mutex_lock_interruptible(&dev->struct_mutex);
1174         if (ret)
1175                 return ret;
1176
1177         ret = i915_gem_set_seqno(dev, val);
1178         mutex_unlock(&dev->struct_mutex);
1179
1180         return ret;
1181 }
1182
1183 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1184                         i915_next_seqno_get, i915_next_seqno_set,
1185                         "0x%llx\n");
1186
1187 static int i915_frequency_info(struct seq_file *m, void *unused)
1188 {
1189         struct drm_info_node *node = m->private;
1190         struct drm_device *dev = node->minor->dev;
1191         struct drm_i915_private *dev_priv = dev->dev_private;
1192         int ret = 0;
1193
1194         intel_runtime_pm_get(dev_priv);
1195
1196         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1197
1198         if (IS_GEN5(dev)) {
1199                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1200                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1201
1202                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1203                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1204                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1205                            MEMSTAT_VID_SHIFT);
1206                 seq_printf(m, "Current P-state: %d\n",
1207                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1208         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1209                 u32 freq_sts;
1210
1211                 mutex_lock(&dev_priv->rps.hw_lock);
1212                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1213                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1214                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1215
1216                 seq_printf(m, "actual GPU freq: %d MHz\n",
1217                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1218
1219                 seq_printf(m, "current GPU freq: %d MHz\n",
1220                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1221
1222                 seq_printf(m, "max GPU freq: %d MHz\n",
1223                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1224
1225                 seq_printf(m, "min GPU freq: %d MHz\n",
1226                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1227
1228                 seq_printf(m, "idle GPU freq: %d MHz\n",
1229                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1230
1231                 seq_printf(m,
1232                            "efficient (RPe) frequency: %d MHz\n",
1233                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1234                 mutex_unlock(&dev_priv->rps.hw_lock);
1235         } else if (INTEL_INFO(dev)->gen >= 6) {
1236                 u32 rp_state_limits;
1237                 u32 gt_perf_status;
1238                 u32 rp_state_cap;
1239                 u32 rpmodectl, rpinclimit, rpdeclimit;
1240                 u32 rpstat, cagf, reqf;
1241                 u32 rpupei, rpcurup, rpprevup;
1242                 u32 rpdownei, rpcurdown, rpprevdown;
1243                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1244                 int max_freq;
1245
1246                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1247                 if (IS_BROXTON(dev)) {
1248                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1249                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1250                 } else {
1251                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1252                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1253                 }
1254
1255                 /* RPSTAT1 is in the GT power well */
1256                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1257                 if (ret)
1258                         goto out;
1259
1260                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1261
1262                 reqf = I915_READ(GEN6_RPNSWREQ);
1263                 if (IS_GEN9(dev))
1264                         reqf >>= 23;
1265                 else {
1266                         reqf &= ~GEN6_TURBO_DISABLE;
1267                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1268                                 reqf >>= 24;
1269                         else
1270                                 reqf >>= 25;
1271                 }
1272                 reqf = intel_gpu_freq(dev_priv, reqf);
1273
1274                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1275                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1276                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1277
1278                 rpstat = I915_READ(GEN6_RPSTAT1);
1279                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1280                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1281                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1282                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1283                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1284                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1285                 if (IS_GEN9(dev))
1286                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1287                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1288                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1289                 else
1290                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1291                 cagf = intel_gpu_freq(dev_priv, cagf);
1292
1293                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1294                 mutex_unlock(&dev->struct_mutex);
1295
1296                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1297                         pm_ier = I915_READ(GEN6_PMIER);
1298                         pm_imr = I915_READ(GEN6_PMIMR);
1299                         pm_isr = I915_READ(GEN6_PMISR);
1300                         pm_iir = I915_READ(GEN6_PMIIR);
1301                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1302                 } else {
1303                         pm_ier = I915_READ(GEN8_GT_IER(2));
1304                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1305                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1306                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1307                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1308                 }
1309                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1310                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1311                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1312                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1313                 seq_printf(m, "Render p-state ratio: %d\n",
1314                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1315                 seq_printf(m, "Render p-state VID: %d\n",
1316                            gt_perf_status & 0xff);
1317                 seq_printf(m, "Render p-state limit: %d\n",
1318                            rp_state_limits & 0xff);
1319                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1320                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1321                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1322                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1323                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1324                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1325                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1326                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1327                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1328                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1329                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1330                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1331                 seq_printf(m, "Up threshold: %d%%\n",
1332                            dev_priv->rps.up_threshold);
1333
1334                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1335                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1336                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1337                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1338                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1339                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1340                 seq_printf(m, "Down threshold: %d%%\n",
1341                            dev_priv->rps.down_threshold);
1342
1343                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1344                             rp_state_cap >> 16) & 0xff;
1345                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1346                              GEN9_FREQ_SCALER : 1);
1347                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1348                            intel_gpu_freq(dev_priv, max_freq));
1349
1350                 max_freq = (rp_state_cap & 0xff00) >> 8;
1351                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1352                              GEN9_FREQ_SCALER : 1);
1353                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1354                            intel_gpu_freq(dev_priv, max_freq));
1355
1356                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1357                             rp_state_cap >> 0) & 0xff;
1358                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1359                              GEN9_FREQ_SCALER : 1);
1360                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1361                            intel_gpu_freq(dev_priv, max_freq));
1362                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1363                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1364
1365                 seq_printf(m, "Current freq: %d MHz\n",
1366                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1367                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1368                 seq_printf(m, "Idle freq: %d MHz\n",
1369                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1370                 seq_printf(m, "Min freq: %d MHz\n",
1371                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1372                 seq_printf(m, "Max freq: %d MHz\n",
1373                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1374                 seq_printf(m,
1375                            "efficient (RPe) frequency: %d MHz\n",
1376                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1377         } else {
1378                 seq_puts(m, "no P-state info available\n");
1379         }
1380
1381         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1382         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1383         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1384
1385 out:
1386         intel_runtime_pm_put(dev_priv);
1387         return ret;
1388 }
1389
1390 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1391 {
1392         struct drm_info_node *node = m->private;
1393         struct drm_device *dev = node->minor->dev;
1394         struct drm_i915_private *dev_priv = dev->dev_private;
1395         struct intel_engine_cs *engine;
1396         u64 acthd[I915_NUM_ENGINES];
1397         u32 seqno[I915_NUM_ENGINES];
1398         u32 instdone[I915_NUM_INSTDONE_REG];
1399         enum intel_engine_id id;
1400         int j;
1401
1402         if (!i915.enable_hangcheck) {
1403                 seq_printf(m, "Hangcheck disabled\n");
1404                 return 0;
1405         }
1406
1407         intel_runtime_pm_get(dev_priv);
1408
1409         for_each_engine_id(engine, dev_priv, id) {
1410                 acthd[id] = intel_ring_get_active_head(engine);
1411                 seqno[id] = engine->get_seqno(engine);
1412         }
1413
1414         i915_get_extra_instdone(dev_priv, instdone);
1415
1416         intel_runtime_pm_put(dev_priv);
1417
1418         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1419                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1420                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1421                                             jiffies));
1422         } else
1423                 seq_printf(m, "Hangcheck inactive\n");
1424
1425         for_each_engine_id(engine, dev_priv, id) {
1426                 seq_printf(m, "%s:\n", engine->name);
1427                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1428                            engine->hangcheck.seqno,
1429                            seqno[id],
1430                            engine->last_submitted_seqno);
1431                 seq_printf(m, "\tuser interrupts = %x [current %x]\n",
1432                            engine->hangcheck.user_interrupts,
1433                            READ_ONCE(engine->user_interrupts));
1434                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1435                            (long long)engine->hangcheck.acthd,
1436                            (long long)acthd[id]);
1437                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1438                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1439
1440                 if (engine->id == RCS) {
1441                         seq_puts(m, "\tinstdone read =");
1442
1443                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1444                                 seq_printf(m, " 0x%08x", instdone[j]);
1445
1446                         seq_puts(m, "\n\tinstdone accu =");
1447
1448                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1449                                 seq_printf(m, " 0x%08x",
1450                                            engine->hangcheck.instdone[j]);
1451
1452                         seq_puts(m, "\n");
1453                 }
1454         }
1455
1456         return 0;
1457 }
1458
1459 static int ironlake_drpc_info(struct seq_file *m)
1460 {
1461         struct drm_info_node *node = m->private;
1462         struct drm_device *dev = node->minor->dev;
1463         struct drm_i915_private *dev_priv = dev->dev_private;
1464         u32 rgvmodectl, rstdbyctl;
1465         u16 crstandvid;
1466         int ret;
1467
1468         ret = mutex_lock_interruptible(&dev->struct_mutex);
1469         if (ret)
1470                 return ret;
1471         intel_runtime_pm_get(dev_priv);
1472
1473         rgvmodectl = I915_READ(MEMMODECTL);
1474         rstdbyctl = I915_READ(RSTDBYCTL);
1475         crstandvid = I915_READ16(CRSTANDVID);
1476
1477         intel_runtime_pm_put(dev_priv);
1478         mutex_unlock(&dev->struct_mutex);
1479
1480         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1481         seq_printf(m, "Boost freq: %d\n",
1482                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1483                    MEMMODE_BOOST_FREQ_SHIFT);
1484         seq_printf(m, "HW control enabled: %s\n",
1485                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1486         seq_printf(m, "SW control enabled: %s\n",
1487                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1488         seq_printf(m, "Gated voltage change: %s\n",
1489                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1490         seq_printf(m, "Starting frequency: P%d\n",
1491                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1492         seq_printf(m, "Max P-state: P%d\n",
1493                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1494         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1495         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1496         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1497         seq_printf(m, "Render standby enabled: %s\n",
1498                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1499         seq_puts(m, "Current RS state: ");
1500         switch (rstdbyctl & RSX_STATUS_MASK) {
1501         case RSX_STATUS_ON:
1502                 seq_puts(m, "on\n");
1503                 break;
1504         case RSX_STATUS_RC1:
1505                 seq_puts(m, "RC1\n");
1506                 break;
1507         case RSX_STATUS_RC1E:
1508                 seq_puts(m, "RC1E\n");
1509                 break;
1510         case RSX_STATUS_RS1:
1511                 seq_puts(m, "RS1\n");
1512                 break;
1513         case RSX_STATUS_RS2:
1514                 seq_puts(m, "RS2 (RC6)\n");
1515                 break;
1516         case RSX_STATUS_RS3:
1517                 seq_puts(m, "RC3 (RC6+)\n");
1518                 break;
1519         default:
1520                 seq_puts(m, "unknown\n");
1521                 break;
1522         }
1523
1524         return 0;
1525 }
1526
1527 static int i915_forcewake_domains(struct seq_file *m, void *data)
1528 {
1529         struct drm_info_node *node = m->private;
1530         struct drm_device *dev = node->minor->dev;
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         struct intel_uncore_forcewake_domain *fw_domain;
1533
1534         spin_lock_irq(&dev_priv->uncore.lock);
1535         for_each_fw_domain(fw_domain, dev_priv) {
1536                 seq_printf(m, "%s.wake_count = %u\n",
1537                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1538                            fw_domain->wake_count);
1539         }
1540         spin_unlock_irq(&dev_priv->uncore.lock);
1541
1542         return 0;
1543 }
1544
1545 static int vlv_drpc_info(struct seq_file *m)
1546 {
1547         struct drm_info_node *node = m->private;
1548         struct drm_device *dev = node->minor->dev;
1549         struct drm_i915_private *dev_priv = dev->dev_private;
1550         u32 rpmodectl1, rcctl1, pw_status;
1551
1552         intel_runtime_pm_get(dev_priv);
1553
1554         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1555         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1556         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1557
1558         intel_runtime_pm_put(dev_priv);
1559
1560         seq_printf(m, "Video Turbo Mode: %s\n",
1561                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1562         seq_printf(m, "Turbo enabled: %s\n",
1563                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1564         seq_printf(m, "HW control enabled: %s\n",
1565                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1566         seq_printf(m, "SW control enabled: %s\n",
1567                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1568                           GEN6_RP_MEDIA_SW_MODE));
1569         seq_printf(m, "RC6 Enabled: %s\n",
1570                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1571                                         GEN6_RC_CTL_EI_MODE(1))));
1572         seq_printf(m, "Render Power Well: %s\n",
1573                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1574         seq_printf(m, "Media Power Well: %s\n",
1575                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1576
1577         seq_printf(m, "Render RC6 residency since boot: %u\n",
1578                    I915_READ(VLV_GT_RENDER_RC6));
1579         seq_printf(m, "Media RC6 residency since boot: %u\n",
1580                    I915_READ(VLV_GT_MEDIA_RC6));
1581
1582         return i915_forcewake_domains(m, NULL);
1583 }
1584
1585 static int gen6_drpc_info(struct seq_file *m)
1586 {
1587         struct drm_info_node *node = m->private;
1588         struct drm_device *dev = node->minor->dev;
1589         struct drm_i915_private *dev_priv = dev->dev_private;
1590         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1591         unsigned forcewake_count;
1592         int count = 0, ret;
1593
1594         ret = mutex_lock_interruptible(&dev->struct_mutex);
1595         if (ret)
1596                 return ret;
1597         intel_runtime_pm_get(dev_priv);
1598
1599         spin_lock_irq(&dev_priv->uncore.lock);
1600         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1601         spin_unlock_irq(&dev_priv->uncore.lock);
1602
1603         if (forcewake_count) {
1604                 seq_puts(m, "RC information inaccurate because somebody "
1605                             "holds a forcewake reference \n");
1606         } else {
1607                 /* NB: we cannot use forcewake, else we read the wrong values */
1608                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1609                         udelay(10);
1610                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1611         }
1612
1613         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1614         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1615
1616         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1617         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1618         mutex_unlock(&dev->struct_mutex);
1619         mutex_lock(&dev_priv->rps.hw_lock);
1620         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1621         mutex_unlock(&dev_priv->rps.hw_lock);
1622
1623         intel_runtime_pm_put(dev_priv);
1624
1625         seq_printf(m, "Video Turbo Mode: %s\n",
1626                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1627         seq_printf(m, "HW control enabled: %s\n",
1628                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1629         seq_printf(m, "SW control enabled: %s\n",
1630                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1631                           GEN6_RP_MEDIA_SW_MODE));
1632         seq_printf(m, "RC1e Enabled: %s\n",
1633                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1634         seq_printf(m, "RC6 Enabled: %s\n",
1635                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1636         seq_printf(m, "Deep RC6 Enabled: %s\n",
1637                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1638         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1639                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1640         seq_puts(m, "Current RC state: ");
1641         switch (gt_core_status & GEN6_RCn_MASK) {
1642         case GEN6_RC0:
1643                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1644                         seq_puts(m, "Core Power Down\n");
1645                 else
1646                         seq_puts(m, "on\n");
1647                 break;
1648         case GEN6_RC3:
1649                 seq_puts(m, "RC3\n");
1650                 break;
1651         case GEN6_RC6:
1652                 seq_puts(m, "RC6\n");
1653                 break;
1654         case GEN6_RC7:
1655                 seq_puts(m, "RC7\n");
1656                 break;
1657         default:
1658                 seq_puts(m, "Unknown\n");
1659                 break;
1660         }
1661
1662         seq_printf(m, "Core Power Down: %s\n",
1663                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1664
1665         /* Not exactly sure what this is */
1666         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1667                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1668         seq_printf(m, "RC6 residency since boot: %u\n",
1669                    I915_READ(GEN6_GT_GFX_RC6));
1670         seq_printf(m, "RC6+ residency since boot: %u\n",
1671                    I915_READ(GEN6_GT_GFX_RC6p));
1672         seq_printf(m, "RC6++ residency since boot: %u\n",
1673                    I915_READ(GEN6_GT_GFX_RC6pp));
1674
1675         seq_printf(m, "RC6   voltage: %dmV\n",
1676                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1677         seq_printf(m, "RC6+  voltage: %dmV\n",
1678                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1679         seq_printf(m, "RC6++ voltage: %dmV\n",
1680                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1681         return 0;
1682 }
1683
1684 static int i915_drpc_info(struct seq_file *m, void *unused)
1685 {
1686         struct drm_info_node *node = m->private;
1687         struct drm_device *dev = node->minor->dev;
1688
1689         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1690                 return vlv_drpc_info(m);
1691         else if (INTEL_INFO(dev)->gen >= 6)
1692                 return gen6_drpc_info(m);
1693         else
1694                 return ironlake_drpc_info(m);
1695 }
1696
1697 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1698 {
1699         struct drm_info_node *node = m->private;
1700         struct drm_device *dev = node->minor->dev;
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702
1703         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1704                    dev_priv->fb_tracking.busy_bits);
1705
1706         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1707                    dev_priv->fb_tracking.flip_bits);
1708
1709         return 0;
1710 }
1711
1712 static int i915_fbc_status(struct seq_file *m, void *unused)
1713 {
1714         struct drm_info_node *node = m->private;
1715         struct drm_device *dev = node->minor->dev;
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717
1718         if (!HAS_FBC(dev)) {
1719                 seq_puts(m, "FBC unsupported on this chipset\n");
1720                 return 0;
1721         }
1722
1723         intel_runtime_pm_get(dev_priv);
1724         mutex_lock(&dev_priv->fbc.lock);
1725
1726         if (intel_fbc_is_active(dev_priv))
1727                 seq_puts(m, "FBC enabled\n");
1728         else
1729                 seq_printf(m, "FBC disabled: %s\n",
1730                            dev_priv->fbc.no_fbc_reason);
1731
1732         if (INTEL_INFO(dev_priv)->gen >= 7)
1733                 seq_printf(m, "Compressing: %s\n",
1734                            yesno(I915_READ(FBC_STATUS2) &
1735                                  FBC_COMPRESSION_MASK));
1736
1737         mutex_unlock(&dev_priv->fbc.lock);
1738         intel_runtime_pm_put(dev_priv);
1739
1740         return 0;
1741 }
1742
1743 static int i915_fbc_fc_get(void *data, u64 *val)
1744 {
1745         struct drm_device *dev = data;
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747
1748         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1749                 return -ENODEV;
1750
1751         *val = dev_priv->fbc.false_color;
1752
1753         return 0;
1754 }
1755
1756 static int i915_fbc_fc_set(void *data, u64 val)
1757 {
1758         struct drm_device *dev = data;
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         u32 reg;
1761
1762         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1763                 return -ENODEV;
1764
1765         mutex_lock(&dev_priv->fbc.lock);
1766
1767         reg = I915_READ(ILK_DPFC_CONTROL);
1768         dev_priv->fbc.false_color = val;
1769
1770         I915_WRITE(ILK_DPFC_CONTROL, val ?
1771                    (reg | FBC_CTL_FALSE_COLOR) :
1772                    (reg & ~FBC_CTL_FALSE_COLOR));
1773
1774         mutex_unlock(&dev_priv->fbc.lock);
1775         return 0;
1776 }
1777
1778 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1779                         i915_fbc_fc_get, i915_fbc_fc_set,
1780                         "%llu\n");
1781
1782 static int i915_ips_status(struct seq_file *m, void *unused)
1783 {
1784         struct drm_info_node *node = m->private;
1785         struct drm_device *dev = node->minor->dev;
1786         struct drm_i915_private *dev_priv = dev->dev_private;
1787
1788         if (!HAS_IPS(dev)) {
1789                 seq_puts(m, "not supported\n");
1790                 return 0;
1791         }
1792
1793         intel_runtime_pm_get(dev_priv);
1794
1795         seq_printf(m, "Enabled by kernel parameter: %s\n",
1796                    yesno(i915.enable_ips));
1797
1798         if (INTEL_INFO(dev)->gen >= 8) {
1799                 seq_puts(m, "Currently: unknown\n");
1800         } else {
1801                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1802                         seq_puts(m, "Currently: enabled\n");
1803                 else
1804                         seq_puts(m, "Currently: disabled\n");
1805         }
1806
1807         intel_runtime_pm_put(dev_priv);
1808
1809         return 0;
1810 }
1811
1812 static int i915_sr_status(struct seq_file *m, void *unused)
1813 {
1814         struct drm_info_node *node = m->private;
1815         struct drm_device *dev = node->minor->dev;
1816         struct drm_i915_private *dev_priv = dev->dev_private;
1817         bool sr_enabled = false;
1818
1819         intel_runtime_pm_get(dev_priv);
1820
1821         if (HAS_PCH_SPLIT(dev))
1822                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1823         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1824                  IS_I945G(dev) || IS_I945GM(dev))
1825                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1826         else if (IS_I915GM(dev))
1827                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1828         else if (IS_PINEVIEW(dev))
1829                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1830         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1831                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1832
1833         intel_runtime_pm_put(dev_priv);
1834
1835         seq_printf(m, "self-refresh: %s\n",
1836                    sr_enabled ? "enabled" : "disabled");
1837
1838         return 0;
1839 }
1840
1841 static int i915_emon_status(struct seq_file *m, void *unused)
1842 {
1843         struct drm_info_node *node = m->private;
1844         struct drm_device *dev = node->minor->dev;
1845         struct drm_i915_private *dev_priv = dev->dev_private;
1846         unsigned long temp, chipset, gfx;
1847         int ret;
1848
1849         if (!IS_GEN5(dev))
1850                 return -ENODEV;
1851
1852         ret = mutex_lock_interruptible(&dev->struct_mutex);
1853         if (ret)
1854                 return ret;
1855
1856         temp = i915_mch_val(dev_priv);
1857         chipset = i915_chipset_val(dev_priv);
1858         gfx = i915_gfx_val(dev_priv);
1859         mutex_unlock(&dev->struct_mutex);
1860
1861         seq_printf(m, "GMCH temp: %ld\n", temp);
1862         seq_printf(m, "Chipset power: %ld\n", chipset);
1863         seq_printf(m, "GFX power: %ld\n", gfx);
1864         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1865
1866         return 0;
1867 }
1868
1869 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1870 {
1871         struct drm_info_node *node = m->private;
1872         struct drm_device *dev = node->minor->dev;
1873         struct drm_i915_private *dev_priv = dev->dev_private;
1874         int ret = 0;
1875         int gpu_freq, ia_freq;
1876         unsigned int max_gpu_freq, min_gpu_freq;
1877
1878         if (!HAS_CORE_RING_FREQ(dev)) {
1879                 seq_puts(m, "unsupported on this chipset\n");
1880                 return 0;
1881         }
1882
1883         intel_runtime_pm_get(dev_priv);
1884
1885         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1886
1887         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1888         if (ret)
1889                 goto out;
1890
1891         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1892                 /* Convert GT frequency to 50 HZ units */
1893                 min_gpu_freq =
1894                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1895                 max_gpu_freq =
1896                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1897         } else {
1898                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1899                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1900         }
1901
1902         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1903
1904         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1905                 ia_freq = gpu_freq;
1906                 sandybridge_pcode_read(dev_priv,
1907                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1908                                        &ia_freq);
1909                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1910                            intel_gpu_freq(dev_priv, (gpu_freq *
1911                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1912                                  GEN9_FREQ_SCALER : 1))),
1913                            ((ia_freq >> 0) & 0xff) * 100,
1914                            ((ia_freq >> 8) & 0xff) * 100);
1915         }
1916
1917         mutex_unlock(&dev_priv->rps.hw_lock);
1918
1919 out:
1920         intel_runtime_pm_put(dev_priv);
1921         return ret;
1922 }
1923
1924 static int i915_opregion(struct seq_file *m, void *unused)
1925 {
1926         struct drm_info_node *node = m->private;
1927         struct drm_device *dev = node->minor->dev;
1928         struct drm_i915_private *dev_priv = dev->dev_private;
1929         struct intel_opregion *opregion = &dev_priv->opregion;
1930         int ret;
1931
1932         ret = mutex_lock_interruptible(&dev->struct_mutex);
1933         if (ret)
1934                 goto out;
1935
1936         if (opregion->header)
1937                 seq_write(m, opregion->header, OPREGION_SIZE);
1938
1939         mutex_unlock(&dev->struct_mutex);
1940
1941 out:
1942         return 0;
1943 }
1944
1945 static int i915_vbt(struct seq_file *m, void *unused)
1946 {
1947         struct drm_info_node *node = m->private;
1948         struct drm_device *dev = node->minor->dev;
1949         struct drm_i915_private *dev_priv = dev->dev_private;
1950         struct intel_opregion *opregion = &dev_priv->opregion;
1951
1952         if (opregion->vbt)
1953                 seq_write(m, opregion->vbt, opregion->vbt_size);
1954
1955         return 0;
1956 }
1957
1958 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1959 {
1960         struct drm_info_node *node = m->private;
1961         struct drm_device *dev = node->minor->dev;
1962         struct intel_framebuffer *fbdev_fb = NULL;
1963         struct drm_framebuffer *drm_fb;
1964         int ret;
1965
1966         ret = mutex_lock_interruptible(&dev->struct_mutex);
1967         if (ret)
1968                 return ret;
1969
1970 #ifdef CONFIG_DRM_FBDEV_EMULATION
1971        if (to_i915(dev)->fbdev) {
1972                fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1973
1974                seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1975                          fbdev_fb->base.width,
1976                          fbdev_fb->base.height,
1977                          fbdev_fb->base.depth,
1978                          fbdev_fb->base.bits_per_pixel,
1979                          fbdev_fb->base.modifier[0],
1980                          drm_framebuffer_read_refcount(&fbdev_fb->base));
1981                describe_obj(m, fbdev_fb->obj);
1982                seq_putc(m, '\n');
1983        }
1984 #endif
1985
1986         mutex_lock(&dev->mode_config.fb_lock);
1987         drm_for_each_fb(drm_fb, dev) {
1988                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1989                 if (fb == fbdev_fb)
1990                         continue;
1991
1992                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1993                            fb->base.width,
1994                            fb->base.height,
1995                            fb->base.depth,
1996                            fb->base.bits_per_pixel,
1997                            fb->base.modifier[0],
1998                            drm_framebuffer_read_refcount(&fb->base));
1999                 describe_obj(m, fb->obj);
2000                 seq_putc(m, '\n');
2001         }
2002         mutex_unlock(&dev->mode_config.fb_lock);
2003         mutex_unlock(&dev->struct_mutex);
2004
2005         return 0;
2006 }
2007
2008 static void describe_ctx_ringbuf(struct seq_file *m,
2009                                  struct intel_ringbuffer *ringbuf)
2010 {
2011         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2012                    ringbuf->space, ringbuf->head, ringbuf->tail,
2013                    ringbuf->last_retired_head);
2014 }
2015
2016 static int i915_context_status(struct seq_file *m, void *unused)
2017 {
2018         struct drm_info_node *node = m->private;
2019         struct drm_device *dev = node->minor->dev;
2020         struct drm_i915_private *dev_priv = dev->dev_private;
2021         struct intel_engine_cs *engine;
2022         struct i915_gem_context *ctx;
2023         int ret;
2024
2025         ret = mutex_lock_interruptible(&dev->struct_mutex);
2026         if (ret)
2027                 return ret;
2028
2029         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2030                 seq_printf(m, "HW context %u ", ctx->hw_id);
2031                 if (IS_ERR(ctx->file_priv)) {
2032                         seq_puts(m, "(deleted) ");
2033                 } else if (ctx->file_priv) {
2034                         struct pid *pid = ctx->file_priv->file->pid;
2035                         struct task_struct *task;
2036
2037                         task = get_pid_task(pid, PIDTYPE_PID);
2038                         if (task) {
2039                                 seq_printf(m, "(%s [%d]) ",
2040                                            task->comm, task->pid);
2041                                 put_task_struct(task);
2042                         }
2043                 } else {
2044                         seq_puts(m, "(kernel) ");
2045                 }
2046
2047                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2048                 seq_putc(m, '\n');
2049
2050                 for_each_engine(engine, dev_priv) {
2051                         struct intel_context *ce = &ctx->engine[engine->id];
2052
2053                         seq_printf(m, "%s: ", engine->name);
2054                         seq_putc(m, ce->initialised ? 'I' : 'i');
2055                         if (ce->state)
2056                                 describe_obj(m, ce->state);
2057                         if (ce->ringbuf)
2058                                 describe_ctx_ringbuf(m, ce->ringbuf);
2059                         seq_putc(m, '\n');
2060                 }
2061
2062                 seq_putc(m, '\n');
2063         }
2064
2065         mutex_unlock(&dev->struct_mutex);
2066
2067         return 0;
2068 }
2069
2070 static void i915_dump_lrc_obj(struct seq_file *m,
2071                               struct i915_gem_context *ctx,
2072                               struct intel_engine_cs *engine)
2073 {
2074         struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2075         struct page *page;
2076         uint32_t *reg_state;
2077         int j;
2078         unsigned long ggtt_offset = 0;
2079
2080         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2081
2082         if (ctx_obj == NULL) {
2083                 seq_puts(m, "\tNot allocated\n");
2084                 return;
2085         }
2086
2087         if (!i915_gem_obj_ggtt_bound(ctx_obj))
2088                 seq_puts(m, "\tNot bound in GGTT\n");
2089         else
2090                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2091
2092         if (i915_gem_object_get_pages(ctx_obj)) {
2093                 seq_puts(m, "\tFailed to get pages for context object\n");
2094                 return;
2095         }
2096
2097         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2098         if (!WARN_ON(page == NULL)) {
2099                 reg_state = kmap_atomic(page);
2100
2101                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2102                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2103                                    ggtt_offset + 4096 + (j * 4),
2104                                    reg_state[j], reg_state[j + 1],
2105                                    reg_state[j + 2], reg_state[j + 3]);
2106                 }
2107                 kunmap_atomic(reg_state);
2108         }
2109
2110         seq_putc(m, '\n');
2111 }
2112
2113 static int i915_dump_lrc(struct seq_file *m, void *unused)
2114 {
2115         struct drm_info_node *node = (struct drm_info_node *) m->private;
2116         struct drm_device *dev = node->minor->dev;
2117         struct drm_i915_private *dev_priv = dev->dev_private;
2118         struct intel_engine_cs *engine;
2119         struct i915_gem_context *ctx;
2120         int ret;
2121
2122         if (!i915.enable_execlists) {
2123                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2124                 return 0;
2125         }
2126
2127         ret = mutex_lock_interruptible(&dev->struct_mutex);
2128         if (ret)
2129                 return ret;
2130
2131         list_for_each_entry(ctx, &dev_priv->context_list, link)
2132                 for_each_engine(engine, dev_priv)
2133                         i915_dump_lrc_obj(m, ctx, engine);
2134
2135         mutex_unlock(&dev->struct_mutex);
2136
2137         return 0;
2138 }
2139
2140 static int i915_execlists(struct seq_file *m, void *data)
2141 {
2142         struct drm_info_node *node = (struct drm_info_node *)m->private;
2143         struct drm_device *dev = node->minor->dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145         struct intel_engine_cs *engine;
2146         u32 status_pointer;
2147         u8 read_pointer;
2148         u8 write_pointer;
2149         u32 status;
2150         u32 ctx_id;
2151         struct list_head *cursor;
2152         int i, ret;
2153
2154         if (!i915.enable_execlists) {
2155                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2156                 return 0;
2157         }
2158
2159         ret = mutex_lock_interruptible(&dev->struct_mutex);
2160         if (ret)
2161                 return ret;
2162
2163         intel_runtime_pm_get(dev_priv);
2164
2165         for_each_engine(engine, dev_priv) {
2166                 struct drm_i915_gem_request *head_req = NULL;
2167                 int count = 0;
2168
2169                 seq_printf(m, "%s\n", engine->name);
2170
2171                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2172                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2173                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2174                            status, ctx_id);
2175
2176                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2177                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2178
2179                 read_pointer = engine->next_context_status_buffer;
2180                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2181                 if (read_pointer > write_pointer)
2182                         write_pointer += GEN8_CSB_ENTRIES;
2183                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2184                            read_pointer, write_pointer);
2185
2186                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2187                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2188                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2189
2190                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2191                                    i, status, ctx_id);
2192                 }
2193
2194                 spin_lock_bh(&engine->execlist_lock);
2195                 list_for_each(cursor, &engine->execlist_queue)
2196                         count++;
2197                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2198                                                     struct drm_i915_gem_request,
2199                                                     execlist_link);
2200                 spin_unlock_bh(&engine->execlist_lock);
2201
2202                 seq_printf(m, "\t%d requests in queue\n", count);
2203                 if (head_req) {
2204                         seq_printf(m, "\tHead request context: %u\n",
2205                                    head_req->ctx->hw_id);
2206                         seq_printf(m, "\tHead request tail: %u\n",
2207                                    head_req->tail);
2208                 }
2209
2210                 seq_putc(m, '\n');
2211         }
2212
2213         intel_runtime_pm_put(dev_priv);
2214         mutex_unlock(&dev->struct_mutex);
2215
2216         return 0;
2217 }
2218
2219 static const char *swizzle_string(unsigned swizzle)
2220 {
2221         switch (swizzle) {
2222         case I915_BIT_6_SWIZZLE_NONE:
2223                 return "none";
2224         case I915_BIT_6_SWIZZLE_9:
2225                 return "bit9";
2226         case I915_BIT_6_SWIZZLE_9_10:
2227                 return "bit9/bit10";
2228         case I915_BIT_6_SWIZZLE_9_11:
2229                 return "bit9/bit11";
2230         case I915_BIT_6_SWIZZLE_9_10_11:
2231                 return "bit9/bit10/bit11";
2232         case I915_BIT_6_SWIZZLE_9_17:
2233                 return "bit9/bit17";
2234         case I915_BIT_6_SWIZZLE_9_10_17:
2235                 return "bit9/bit10/bit17";
2236         case I915_BIT_6_SWIZZLE_UNKNOWN:
2237                 return "unknown";
2238         }
2239
2240         return "bug";
2241 }
2242
2243 static int i915_swizzle_info(struct seq_file *m, void *data)
2244 {
2245         struct drm_info_node *node = m->private;
2246         struct drm_device *dev = node->minor->dev;
2247         struct drm_i915_private *dev_priv = dev->dev_private;
2248         int ret;
2249
2250         ret = mutex_lock_interruptible(&dev->struct_mutex);
2251         if (ret)
2252                 return ret;
2253         intel_runtime_pm_get(dev_priv);
2254
2255         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2256                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2257         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2258                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2259
2260         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2261                 seq_printf(m, "DDC = 0x%08x\n",
2262                            I915_READ(DCC));
2263                 seq_printf(m, "DDC2 = 0x%08x\n",
2264                            I915_READ(DCC2));
2265                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2266                            I915_READ16(C0DRB3));
2267                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2268                            I915_READ16(C1DRB3));
2269         } else if (INTEL_INFO(dev)->gen >= 6) {
2270                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2271                            I915_READ(MAD_DIMM_C0));
2272                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2273                            I915_READ(MAD_DIMM_C1));
2274                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2275                            I915_READ(MAD_DIMM_C2));
2276                 seq_printf(m, "TILECTL = 0x%08x\n",
2277                            I915_READ(TILECTL));
2278                 if (INTEL_INFO(dev)->gen >= 8)
2279                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2280                                    I915_READ(GAMTARBMODE));
2281                 else
2282                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2283                                    I915_READ(ARB_MODE));
2284                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2285                            I915_READ(DISP_ARB_CTL));
2286         }
2287
2288         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2289                 seq_puts(m, "L-shaped memory detected\n");
2290
2291         intel_runtime_pm_put(dev_priv);
2292         mutex_unlock(&dev->struct_mutex);
2293
2294         return 0;
2295 }
2296
2297 static int per_file_ctx(int id, void *ptr, void *data)
2298 {
2299         struct i915_gem_context *ctx = ptr;
2300         struct seq_file *m = data;
2301         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2302
2303         if (!ppgtt) {
2304                 seq_printf(m, "  no ppgtt for context %d\n",
2305                            ctx->user_handle);
2306                 return 0;
2307         }
2308
2309         if (i915_gem_context_is_default(ctx))
2310                 seq_puts(m, "  default context:\n");
2311         else
2312                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2313         ppgtt->debug_dump(ppgtt, m);
2314
2315         return 0;
2316 }
2317
2318 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2319 {
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         struct intel_engine_cs *engine;
2322         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2323         int i;
2324
2325         if (!ppgtt)
2326                 return;
2327
2328         for_each_engine(engine, dev_priv) {
2329                 seq_printf(m, "%s\n", engine->name);
2330                 for (i = 0; i < 4; i++) {
2331                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2332                         pdp <<= 32;
2333                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2334                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2335                 }
2336         }
2337 }
2338
2339 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2340 {
2341         struct drm_i915_private *dev_priv = dev->dev_private;
2342         struct intel_engine_cs *engine;
2343
2344         if (IS_GEN6(dev_priv))
2345                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2346
2347         for_each_engine(engine, dev_priv) {
2348                 seq_printf(m, "%s\n", engine->name);
2349                 if (IS_GEN7(dev_priv))
2350                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2351                                    I915_READ(RING_MODE_GEN7(engine)));
2352                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2353                            I915_READ(RING_PP_DIR_BASE(engine)));
2354                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2355                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2356                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2357                            I915_READ(RING_PP_DIR_DCLV(engine)));
2358         }
2359         if (dev_priv->mm.aliasing_ppgtt) {
2360                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2361
2362                 seq_puts(m, "aliasing PPGTT:\n");
2363                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2364
2365                 ppgtt->debug_dump(ppgtt, m);
2366         }
2367
2368         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2369 }
2370
2371 static int i915_ppgtt_info(struct seq_file *m, void *data)
2372 {
2373         struct drm_info_node *node = m->private;
2374         struct drm_device *dev = node->minor->dev;
2375         struct drm_i915_private *dev_priv = dev->dev_private;
2376         struct drm_file *file;
2377
2378         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2379         if (ret)
2380                 return ret;
2381         intel_runtime_pm_get(dev_priv);
2382
2383         if (INTEL_INFO(dev)->gen >= 8)
2384                 gen8_ppgtt_info(m, dev);
2385         else if (INTEL_INFO(dev)->gen >= 6)
2386                 gen6_ppgtt_info(m, dev);
2387
2388         mutex_lock(&dev->filelist_mutex);
2389         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2390                 struct drm_i915_file_private *file_priv = file->driver_priv;
2391                 struct task_struct *task;
2392
2393                 task = get_pid_task(file->pid, PIDTYPE_PID);
2394                 if (!task) {
2395                         ret = -ESRCH;
2396                         goto out_unlock;
2397                 }
2398                 seq_printf(m, "\nproc: %s\n", task->comm);
2399                 put_task_struct(task);
2400                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2401                              (void *)(unsigned long)m);
2402         }
2403 out_unlock:
2404         mutex_unlock(&dev->filelist_mutex);
2405
2406         intel_runtime_pm_put(dev_priv);
2407         mutex_unlock(&dev->struct_mutex);
2408
2409         return ret;
2410 }
2411
2412 static int count_irq_waiters(struct drm_i915_private *i915)
2413 {
2414         struct intel_engine_cs *engine;
2415         int count = 0;
2416
2417         for_each_engine(engine, i915)
2418                 count += engine->irq_refcount;
2419
2420         return count;
2421 }
2422
2423 static int i915_rps_boost_info(struct seq_file *m, void *data)
2424 {
2425         struct drm_info_node *node = m->private;
2426         struct drm_device *dev = node->minor->dev;
2427         struct drm_i915_private *dev_priv = dev->dev_private;
2428         struct drm_file *file;
2429
2430         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2431         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2432         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2433         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2434                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2435                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2436                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2437                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2438                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2439
2440         mutex_lock(&dev->filelist_mutex);
2441         spin_lock(&dev_priv->rps.client_lock);
2442         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2443                 struct drm_i915_file_private *file_priv = file->driver_priv;
2444                 struct task_struct *task;
2445
2446                 rcu_read_lock();
2447                 task = pid_task(file->pid, PIDTYPE_PID);
2448                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2449                            task ? task->comm : "<unknown>",
2450                            task ? task->pid : -1,
2451                            file_priv->rps.boosts,
2452                            list_empty(&file_priv->rps.link) ? "" : ", active");
2453                 rcu_read_unlock();
2454         }
2455         seq_printf(m, "Semaphore boosts: %d%s\n",
2456                    dev_priv->rps.semaphores.boosts,
2457                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2458         seq_printf(m, "MMIO flip boosts: %d%s\n",
2459                    dev_priv->rps.mmioflips.boosts,
2460                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2461         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2462         spin_unlock(&dev_priv->rps.client_lock);
2463         mutex_unlock(&dev->filelist_mutex);
2464
2465         return 0;
2466 }
2467
2468 static int i915_llc(struct seq_file *m, void *data)
2469 {
2470         struct drm_info_node *node = m->private;
2471         struct drm_device *dev = node->minor->dev;
2472         struct drm_i915_private *dev_priv = dev->dev_private;
2473         const bool edram = INTEL_GEN(dev_priv) > 8;
2474
2475         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2476         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2477                    intel_uncore_edram_size(dev_priv)/1024/1024);
2478
2479         return 0;
2480 }
2481
2482 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2483 {
2484         struct drm_info_node *node = m->private;
2485         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2486         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2487         u32 tmp, i;
2488
2489         if (!HAS_GUC_UCODE(dev_priv))
2490                 return 0;
2491
2492         seq_printf(m, "GuC firmware status:\n");
2493         seq_printf(m, "\tpath: %s\n",
2494                 guc_fw->guc_fw_path);
2495         seq_printf(m, "\tfetch: %s\n",
2496                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2497         seq_printf(m, "\tload: %s\n",
2498                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2499         seq_printf(m, "\tversion wanted: %d.%d\n",
2500                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2501         seq_printf(m, "\tversion found: %d.%d\n",
2502                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2503         seq_printf(m, "\theader: offset is %d; size = %d\n",
2504                 guc_fw->header_offset, guc_fw->header_size);
2505         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2506                 guc_fw->ucode_offset, guc_fw->ucode_size);
2507         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2508                 guc_fw->rsa_offset, guc_fw->rsa_size);
2509
2510         tmp = I915_READ(GUC_STATUS);
2511
2512         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2513         seq_printf(m, "\tBootrom status = 0x%x\n",
2514                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2515         seq_printf(m, "\tuKernel status = 0x%x\n",
2516                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2517         seq_printf(m, "\tMIA Core status = 0x%x\n",
2518                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2519         seq_puts(m, "\nScratch registers:\n");
2520         for (i = 0; i < 16; i++)
2521                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2522
2523         return 0;
2524 }
2525
2526 static void i915_guc_client_info(struct seq_file *m,
2527                                  struct drm_i915_private *dev_priv,
2528                                  struct i915_guc_client *client)
2529 {
2530         struct intel_engine_cs *engine;
2531         uint64_t tot = 0;
2532
2533         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2534                 client->priority, client->ctx_index, client->proc_desc_offset);
2535         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2536                 client->doorbell_id, client->doorbell_offset, client->cookie);
2537         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2538                 client->wq_size, client->wq_offset, client->wq_tail);
2539
2540         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2541         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2542         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2543         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2544
2545         for_each_engine(engine, dev_priv) {
2546                 seq_printf(m, "\tSubmissions: %llu %s\n",
2547                                 client->submissions[engine->id],
2548                                 engine->name);
2549                 tot += client->submissions[engine->id];
2550         }
2551         seq_printf(m, "\tTotal: %llu\n", tot);
2552 }
2553
2554 static int i915_guc_info(struct seq_file *m, void *data)
2555 {
2556         struct drm_info_node *node = m->private;
2557         struct drm_device *dev = node->minor->dev;
2558         struct drm_i915_private *dev_priv = dev->dev_private;
2559         struct intel_guc guc;
2560         struct i915_guc_client client = {};
2561         struct intel_engine_cs *engine;
2562         u64 total = 0;
2563
2564         if (!HAS_GUC_SCHED(dev_priv))
2565                 return 0;
2566
2567         if (mutex_lock_interruptible(&dev->struct_mutex))
2568                 return 0;
2569
2570         /* Take a local copy of the GuC data, so we can dump it at leisure */
2571         guc = dev_priv->guc;
2572         if (guc.execbuf_client)
2573                 client = *guc.execbuf_client;
2574
2575         mutex_unlock(&dev->struct_mutex);
2576
2577         seq_printf(m, "Doorbell map:\n");
2578         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2579         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2580
2581         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2582         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2583         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2584         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2585         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2586
2587         seq_printf(m, "\nGuC submissions:\n");
2588         for_each_engine(engine, dev_priv) {
2589                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2590                         engine->name, guc.submissions[engine->id],
2591                         guc.last_seqno[engine->id]);
2592                 total += guc.submissions[engine->id];
2593         }
2594         seq_printf(m, "\t%s: %llu\n", "Total", total);
2595
2596         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2597         i915_guc_client_info(m, dev_priv, &client);
2598
2599         /* Add more as required ... */
2600
2601         return 0;
2602 }
2603
2604 static int i915_guc_log_dump(struct seq_file *m, void *data)
2605 {
2606         struct drm_info_node *node = m->private;
2607         struct drm_device *dev = node->minor->dev;
2608         struct drm_i915_private *dev_priv = dev->dev_private;
2609         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2610         u32 *log;
2611         int i = 0, pg;
2612
2613         if (!log_obj)
2614                 return 0;
2615
2616         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2617                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2618
2619                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2620                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2621                                    *(log + i), *(log + i + 1),
2622                                    *(log + i + 2), *(log + i + 3));
2623
2624                 kunmap_atomic(log);
2625         }
2626
2627         seq_putc(m, '\n');
2628
2629         return 0;
2630 }
2631
2632 static int i915_edp_psr_status(struct seq_file *m, void *data)
2633 {
2634         struct drm_info_node *node = m->private;
2635         struct drm_device *dev = node->minor->dev;
2636         struct drm_i915_private *dev_priv = dev->dev_private;
2637         u32 psrperf = 0;
2638         u32 stat[3];
2639         enum pipe pipe;
2640         bool enabled = false;
2641
2642         if (!HAS_PSR(dev)) {
2643                 seq_puts(m, "PSR not supported\n");
2644                 return 0;
2645         }
2646
2647         intel_runtime_pm_get(dev_priv);
2648
2649         mutex_lock(&dev_priv->psr.lock);
2650         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2651         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2652         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2653         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2654         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2655                    dev_priv->psr.busy_frontbuffer_bits);
2656         seq_printf(m, "Re-enable work scheduled: %s\n",
2657                    yesno(work_busy(&dev_priv->psr.work.work)));
2658
2659         if (HAS_DDI(dev))
2660                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2661         else {
2662                 for_each_pipe(dev_priv, pipe) {
2663                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2664                                 VLV_EDP_PSR_CURR_STATE_MASK;
2665                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2666                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2667                                 enabled = true;
2668                 }
2669         }
2670
2671         seq_printf(m, "Main link in standby mode: %s\n",
2672                    yesno(dev_priv->psr.link_standby));
2673
2674         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2675
2676         if (!HAS_DDI(dev))
2677                 for_each_pipe(dev_priv, pipe) {
2678                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2679                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2680                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2681                 }
2682         seq_puts(m, "\n");
2683
2684         /*
2685          * VLV/CHV PSR has no kind of performance counter
2686          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2687          */
2688         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2689                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2690                         EDP_PSR_PERF_CNT_MASK;
2691
2692                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2693         }
2694         mutex_unlock(&dev_priv->psr.lock);
2695
2696         intel_runtime_pm_put(dev_priv);
2697         return 0;
2698 }
2699
2700 static int i915_sink_crc(struct seq_file *m, void *data)
2701 {
2702         struct drm_info_node *node = m->private;
2703         struct drm_device *dev = node->minor->dev;
2704         struct intel_encoder *encoder;
2705         struct intel_connector *connector;
2706         struct intel_dp *intel_dp = NULL;
2707         int ret;
2708         u8 crc[6];
2709
2710         drm_modeset_lock_all(dev);
2711         for_each_intel_connector(dev, connector) {
2712
2713                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2714                         continue;
2715
2716                 if (!connector->base.encoder)
2717                         continue;
2718
2719                 encoder = to_intel_encoder(connector->base.encoder);
2720                 if (encoder->type != INTEL_OUTPUT_EDP)
2721                         continue;
2722
2723                 intel_dp = enc_to_intel_dp(&encoder->base);
2724
2725                 ret = intel_dp_sink_crc(intel_dp, crc);
2726                 if (ret)
2727                         goto out;
2728
2729                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2730                            crc[0], crc[1], crc[2],
2731                            crc[3], crc[4], crc[5]);
2732                 goto out;
2733         }
2734         ret = -ENODEV;
2735 out:
2736         drm_modeset_unlock_all(dev);
2737         return ret;
2738 }
2739
2740 static int i915_energy_uJ(struct seq_file *m, void *data)
2741 {
2742         struct drm_info_node *node = m->private;
2743         struct drm_device *dev = node->minor->dev;
2744         struct drm_i915_private *dev_priv = dev->dev_private;
2745         u64 power;
2746         u32 units;
2747
2748         if (INTEL_INFO(dev)->gen < 6)
2749                 return -ENODEV;
2750
2751         intel_runtime_pm_get(dev_priv);
2752
2753         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2754         power = (power & 0x1f00) >> 8;
2755         units = 1000000 / (1 << power); /* convert to uJ */
2756         power = I915_READ(MCH_SECP_NRG_STTS);
2757         power *= units;
2758
2759         intel_runtime_pm_put(dev_priv);
2760
2761         seq_printf(m, "%llu", (long long unsigned)power);
2762
2763         return 0;
2764 }
2765
2766 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2767 {
2768         struct drm_info_node *node = m->private;
2769         struct drm_device *dev = node->minor->dev;
2770         struct drm_i915_private *dev_priv = dev->dev_private;
2771
2772         if (!HAS_RUNTIME_PM(dev_priv))
2773                 seq_puts(m, "Runtime power management not supported\n");
2774
2775         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2776         seq_printf(m, "IRQs disabled: %s\n",
2777                    yesno(!intel_irqs_enabled(dev_priv)));
2778 #ifdef CONFIG_PM
2779         seq_printf(m, "Usage count: %d\n",
2780                    atomic_read(&dev->dev->power.usage_count));
2781 #else
2782         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2783 #endif
2784         seq_printf(m, "PCI device power state: %s [%d]\n",
2785                    pci_power_name(dev_priv->dev->pdev->current_state),
2786                    dev_priv->dev->pdev->current_state);
2787
2788         return 0;
2789 }
2790
2791 static int i915_power_domain_info(struct seq_file *m, void *unused)
2792 {
2793         struct drm_info_node *node = m->private;
2794         struct drm_device *dev = node->minor->dev;
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2797         int i;
2798
2799         mutex_lock(&power_domains->lock);
2800
2801         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2802         for (i = 0; i < power_domains->power_well_count; i++) {
2803                 struct i915_power_well *power_well;
2804                 enum intel_display_power_domain power_domain;
2805
2806                 power_well = &power_domains->power_wells[i];
2807                 seq_printf(m, "%-25s %d\n", power_well->name,
2808                            power_well->count);
2809
2810                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2811                      power_domain++) {
2812                         if (!(BIT(power_domain) & power_well->domains))
2813                                 continue;
2814
2815                         seq_printf(m, "  %-23s %d\n",
2816                                  intel_display_power_domain_str(power_domain),
2817                                  power_domains->domain_use_count[power_domain]);
2818                 }
2819         }
2820
2821         mutex_unlock(&power_domains->lock);
2822
2823         return 0;
2824 }
2825
2826 static int i915_dmc_info(struct seq_file *m, void *unused)
2827 {
2828         struct drm_info_node *node = m->private;
2829         struct drm_device *dev = node->minor->dev;
2830         struct drm_i915_private *dev_priv = dev->dev_private;
2831         struct intel_csr *csr;
2832
2833         if (!HAS_CSR(dev)) {
2834                 seq_puts(m, "not supported\n");
2835                 return 0;
2836         }
2837
2838         csr = &dev_priv->csr;
2839
2840         intel_runtime_pm_get(dev_priv);
2841
2842         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2843         seq_printf(m, "path: %s\n", csr->fw_path);
2844
2845         if (!csr->dmc_payload)
2846                 goto out;
2847
2848         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2849                    CSR_VERSION_MINOR(csr->version));
2850
2851         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2852                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2853                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2854                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2855                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2856         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2857                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2858                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2859         }
2860
2861 out:
2862         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2863         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2864         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2865
2866         intel_runtime_pm_put(dev_priv);
2867
2868         return 0;
2869 }
2870
2871 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2872                                  struct drm_display_mode *mode)
2873 {
2874         int i;
2875
2876         for (i = 0; i < tabs; i++)
2877                 seq_putc(m, '\t');
2878
2879         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2880                    mode->base.id, mode->name,
2881                    mode->vrefresh, mode->clock,
2882                    mode->hdisplay, mode->hsync_start,
2883                    mode->hsync_end, mode->htotal,
2884                    mode->vdisplay, mode->vsync_start,
2885                    mode->vsync_end, mode->vtotal,
2886                    mode->type, mode->flags);
2887 }
2888
2889 static void intel_encoder_info(struct seq_file *m,
2890                                struct intel_crtc *intel_crtc,
2891                                struct intel_encoder *intel_encoder)
2892 {
2893         struct drm_info_node *node = m->private;
2894         struct drm_device *dev = node->minor->dev;
2895         struct drm_crtc *crtc = &intel_crtc->base;
2896         struct intel_connector *intel_connector;
2897         struct drm_encoder *encoder;
2898
2899         encoder = &intel_encoder->base;
2900         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2901                    encoder->base.id, encoder->name);
2902         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2903                 struct drm_connector *connector = &intel_connector->base;
2904                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2905                            connector->base.id,
2906                            connector->name,
2907                            drm_get_connector_status_name(connector->status));
2908                 if (connector->status == connector_status_connected) {
2909                         struct drm_display_mode *mode = &crtc->mode;
2910                         seq_printf(m, ", mode:\n");
2911                         intel_seq_print_mode(m, 2, mode);
2912                 } else {
2913                         seq_putc(m, '\n');
2914                 }
2915         }
2916 }
2917
2918 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2919 {
2920         struct drm_info_node *node = m->private;
2921         struct drm_device *dev = node->minor->dev;
2922         struct drm_crtc *crtc = &intel_crtc->base;
2923         struct intel_encoder *intel_encoder;
2924         struct drm_plane_state *plane_state = crtc->primary->state;
2925         struct drm_framebuffer *fb = plane_state->fb;
2926
2927         if (fb)
2928                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2929                            fb->base.id, plane_state->src_x >> 16,
2930                            plane_state->src_y >> 16, fb->width, fb->height);
2931         else
2932                 seq_puts(m, "\tprimary plane disabled\n");
2933         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2934                 intel_encoder_info(m, intel_crtc, intel_encoder);
2935 }
2936
2937 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2938 {
2939         struct drm_display_mode *mode = panel->fixed_mode;
2940
2941         seq_printf(m, "\tfixed mode:\n");
2942         intel_seq_print_mode(m, 2, mode);
2943 }
2944
2945 static void intel_dp_info(struct seq_file *m,
2946                           struct intel_connector *intel_connector)
2947 {
2948         struct intel_encoder *intel_encoder = intel_connector->encoder;
2949         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2950
2951         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2952         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2953         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2954                 intel_panel_info(m, &intel_connector->panel);
2955 }
2956
2957 static void intel_hdmi_info(struct seq_file *m,
2958                             struct intel_connector *intel_connector)
2959 {
2960         struct intel_encoder *intel_encoder = intel_connector->encoder;
2961         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2962
2963         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2964 }
2965
2966 static void intel_lvds_info(struct seq_file *m,
2967                             struct intel_connector *intel_connector)
2968 {
2969         intel_panel_info(m, &intel_connector->panel);
2970 }
2971
2972 static void intel_connector_info(struct seq_file *m,
2973                                  struct drm_connector *connector)
2974 {
2975         struct intel_connector *intel_connector = to_intel_connector(connector);
2976         struct intel_encoder *intel_encoder = intel_connector->encoder;
2977         struct drm_display_mode *mode;
2978
2979         seq_printf(m, "connector %d: type %s, status: %s\n",
2980                    connector->base.id, connector->name,
2981                    drm_get_connector_status_name(connector->status));
2982         if (connector->status == connector_status_connected) {
2983                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2984                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2985                            connector->display_info.width_mm,
2986                            connector->display_info.height_mm);
2987                 seq_printf(m, "\tsubpixel order: %s\n",
2988                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2989                 seq_printf(m, "\tCEA rev: %d\n",
2990                            connector->display_info.cea_rev);
2991         }
2992         if (intel_encoder) {
2993                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2994                     intel_encoder->type == INTEL_OUTPUT_EDP)
2995                         intel_dp_info(m, intel_connector);
2996                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2997                         intel_hdmi_info(m, intel_connector);
2998                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2999                         intel_lvds_info(m, intel_connector);
3000         }
3001
3002         seq_printf(m, "\tmodes:\n");
3003         list_for_each_entry(mode, &connector->modes, head)
3004                 intel_seq_print_mode(m, 2, mode);
3005 }
3006
3007 static bool cursor_active(struct drm_device *dev, int pipe)
3008 {
3009         struct drm_i915_private *dev_priv = dev->dev_private;
3010         u32 state;
3011
3012         if (IS_845G(dev) || IS_I865G(dev))
3013                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3014         else
3015                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3016
3017         return state;
3018 }
3019
3020 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3021 {
3022         struct drm_i915_private *dev_priv = dev->dev_private;
3023         u32 pos;
3024
3025         pos = I915_READ(CURPOS(pipe));
3026
3027         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3028         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3029                 *x = -*x;
3030
3031         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3032         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3033                 *y = -*y;
3034
3035         return cursor_active(dev, pipe);
3036 }
3037
3038 static const char *plane_type(enum drm_plane_type type)
3039 {
3040         switch (type) {
3041         case DRM_PLANE_TYPE_OVERLAY:
3042                 return "OVL";
3043         case DRM_PLANE_TYPE_PRIMARY:
3044                 return "PRI";
3045         case DRM_PLANE_TYPE_CURSOR:
3046                 return "CUR";
3047         /*
3048          * Deliberately omitting default: to generate compiler warnings
3049          * when a new drm_plane_type gets added.
3050          */
3051         }
3052
3053         return "unknown";
3054 }
3055
3056 static const char *plane_rotation(unsigned int rotation)
3057 {
3058         static char buf[48];
3059         /*
3060          * According to doc only one DRM_ROTATE_ is allowed but this
3061          * will print them all to visualize if the values are misused
3062          */
3063         snprintf(buf, sizeof(buf),
3064                  "%s%s%s%s%s%s(0x%08x)",
3065                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3066                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3067                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3068                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3069                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3070                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3071                  rotation);
3072
3073         return buf;
3074 }
3075
3076 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3077 {
3078         struct drm_info_node *node = m->private;
3079         struct drm_device *dev = node->minor->dev;
3080         struct intel_plane *intel_plane;
3081
3082         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3083                 struct drm_plane_state *state;
3084                 struct drm_plane *plane = &intel_plane->base;
3085
3086                 if (!plane->state) {
3087                         seq_puts(m, "plane->state is NULL!\n");
3088                         continue;
3089                 }
3090
3091                 state = plane->state;
3092
3093                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3094                            plane->base.id,
3095                            plane_type(intel_plane->base.type),
3096                            state->crtc_x, state->crtc_y,
3097                            state->crtc_w, state->crtc_h,
3098                            (state->src_x >> 16),
3099                            ((state->src_x & 0xffff) * 15625) >> 10,
3100                            (state->src_y >> 16),
3101                            ((state->src_y & 0xffff) * 15625) >> 10,
3102                            (state->src_w >> 16),
3103                            ((state->src_w & 0xffff) * 15625) >> 10,
3104                            (state->src_h >> 16),
3105                            ((state->src_h & 0xffff) * 15625) >> 10,
3106                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3107                            plane_rotation(state->rotation));
3108         }
3109 }
3110
3111 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3112 {
3113         struct intel_crtc_state *pipe_config;
3114         int num_scalers = intel_crtc->num_scalers;
3115         int i;
3116
3117         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3118
3119         /* Not all platformas have a scaler */
3120         if (num_scalers) {
3121                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3122                            num_scalers,
3123                            pipe_config->scaler_state.scaler_users,
3124                            pipe_config->scaler_state.scaler_id);
3125
3126                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3127                         struct intel_scaler *sc =
3128                                         &pipe_config->scaler_state.scalers[i];
3129
3130                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3131                                    i, yesno(sc->in_use), sc->mode);
3132                 }
3133                 seq_puts(m, "\n");
3134         } else {
3135                 seq_puts(m, "\tNo scalers available on this platform\n");
3136         }
3137 }
3138
3139 static int i915_display_info(struct seq_file *m, void *unused)
3140 {
3141         struct drm_info_node *node = m->private;
3142         struct drm_device *dev = node->minor->dev;
3143         struct drm_i915_private *dev_priv = dev->dev_private;
3144         struct intel_crtc *crtc;
3145         struct drm_connector *connector;
3146
3147         intel_runtime_pm_get(dev_priv);
3148         drm_modeset_lock_all(dev);
3149         seq_printf(m, "CRTC info\n");
3150         seq_printf(m, "---------\n");
3151         for_each_intel_crtc(dev, crtc) {
3152                 bool active;
3153                 struct intel_crtc_state *pipe_config;
3154                 int x, y;
3155
3156                 pipe_config = to_intel_crtc_state(crtc->base.state);
3157
3158                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3159                            crtc->base.base.id, pipe_name(crtc->pipe),
3160                            yesno(pipe_config->base.active),
3161                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3162                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3163
3164                 if (pipe_config->base.active) {
3165                         intel_crtc_info(m, crtc);
3166
3167                         active = cursor_position(dev, crtc->pipe, &x, &y);
3168                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3169                                    yesno(crtc->cursor_base),
3170                                    x, y, crtc->base.cursor->state->crtc_w,
3171                                    crtc->base.cursor->state->crtc_h,
3172                                    crtc->cursor_addr, yesno(active));
3173                         intel_scaler_info(m, crtc);
3174                         intel_plane_info(m, crtc);
3175                 }
3176
3177                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3178                            yesno(!crtc->cpu_fifo_underrun_disabled),
3179                            yesno(!crtc->pch_fifo_underrun_disabled));
3180         }
3181
3182         seq_printf(m, "\n");
3183         seq_printf(m, "Connector info\n");
3184         seq_printf(m, "--------------\n");
3185         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3186                 intel_connector_info(m, connector);
3187         }
3188         drm_modeset_unlock_all(dev);
3189         intel_runtime_pm_put(dev_priv);
3190
3191         return 0;
3192 }
3193
3194 static int i915_semaphore_status(struct seq_file *m, void *unused)
3195 {
3196         struct drm_info_node *node = (struct drm_info_node *) m->private;
3197         struct drm_device *dev = node->minor->dev;
3198         struct drm_i915_private *dev_priv = dev->dev_private;
3199         struct intel_engine_cs *engine;
3200         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3201         enum intel_engine_id id;
3202         int j, ret;
3203
3204         if (!i915_semaphore_is_enabled(dev_priv)) {
3205                 seq_puts(m, "Semaphores are disabled\n");
3206                 return 0;
3207         }
3208
3209         ret = mutex_lock_interruptible(&dev->struct_mutex);
3210         if (ret)
3211                 return ret;
3212         intel_runtime_pm_get(dev_priv);
3213
3214         if (IS_BROADWELL(dev)) {
3215                 struct page *page;
3216                 uint64_t *seqno;
3217
3218                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3219
3220                 seqno = (uint64_t *)kmap_atomic(page);
3221                 for_each_engine_id(engine, dev_priv, id) {
3222                         uint64_t offset;
3223
3224                         seq_printf(m, "%s\n", engine->name);
3225
3226                         seq_puts(m, "  Last signal:");
3227                         for (j = 0; j < num_rings; j++) {
3228                                 offset = id * I915_NUM_ENGINES + j;
3229                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3230                                            seqno[offset], offset * 8);
3231                         }
3232                         seq_putc(m, '\n');
3233
3234                         seq_puts(m, "  Last wait:  ");
3235                         for (j = 0; j < num_rings; j++) {
3236                                 offset = id + (j * I915_NUM_ENGINES);
3237                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3238                                            seqno[offset], offset * 8);
3239                         }
3240                         seq_putc(m, '\n');
3241
3242                 }
3243                 kunmap_atomic(seqno);
3244         } else {
3245                 seq_puts(m, "  Last signal:");
3246                 for_each_engine(engine, dev_priv)
3247                         for (j = 0; j < num_rings; j++)
3248                                 seq_printf(m, "0x%08x\n",
3249                                            I915_READ(engine->semaphore.mbox.signal[j]));
3250                 seq_putc(m, '\n');
3251         }
3252
3253         seq_puts(m, "\nSync seqno:\n");
3254         for_each_engine(engine, dev_priv) {
3255                 for (j = 0; j < num_rings; j++)
3256                         seq_printf(m, "  0x%08x ",
3257                                    engine->semaphore.sync_seqno[j]);
3258                 seq_putc(m, '\n');
3259         }
3260         seq_putc(m, '\n');
3261
3262         intel_runtime_pm_put(dev_priv);
3263         mutex_unlock(&dev->struct_mutex);
3264         return 0;
3265 }
3266
3267 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3268 {
3269         struct drm_info_node *node = (struct drm_info_node *) m->private;
3270         struct drm_device *dev = node->minor->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         int i;
3273
3274         drm_modeset_lock_all(dev);
3275         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3276                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3277
3278                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3279                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3280                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3281                 seq_printf(m, " tracked hardware state:\n");
3282                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3283                 seq_printf(m, " dpll_md: 0x%08x\n",
3284                            pll->config.hw_state.dpll_md);
3285                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3286                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3287                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3288         }
3289         drm_modeset_unlock_all(dev);
3290
3291         return 0;
3292 }
3293
3294 static int i915_wa_registers(struct seq_file *m, void *unused)
3295 {
3296         int i;
3297         int ret;
3298         struct intel_engine_cs *engine;
3299         struct drm_info_node *node = (struct drm_info_node *) m->private;
3300         struct drm_device *dev = node->minor->dev;
3301         struct drm_i915_private *dev_priv = dev->dev_private;
3302         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3303         enum intel_engine_id id;
3304
3305         ret = mutex_lock_interruptible(&dev->struct_mutex);
3306         if (ret)
3307                 return ret;
3308
3309         intel_runtime_pm_get(dev_priv);
3310
3311         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3312         for_each_engine_id(engine, dev_priv, id)
3313                 seq_printf(m, "HW whitelist count for %s: %d\n",
3314                            engine->name, workarounds->hw_whitelist_count[id]);
3315         for (i = 0; i < workarounds->count; ++i) {
3316                 i915_reg_t addr;
3317                 u32 mask, value, read;
3318                 bool ok;
3319
3320                 addr = workarounds->reg[i].addr;
3321                 mask = workarounds->reg[i].mask;
3322                 value = workarounds->reg[i].value;
3323                 read = I915_READ(addr);
3324                 ok = (value & mask) == (read & mask);
3325                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3326                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3327         }
3328
3329         intel_runtime_pm_put(dev_priv);
3330         mutex_unlock(&dev->struct_mutex);
3331
3332         return 0;
3333 }
3334
3335 static int i915_ddb_info(struct seq_file *m, void *unused)
3336 {
3337         struct drm_info_node *node = m->private;
3338         struct drm_device *dev = node->minor->dev;
3339         struct drm_i915_private *dev_priv = dev->dev_private;
3340         struct skl_ddb_allocation *ddb;
3341         struct skl_ddb_entry *entry;
3342         enum pipe pipe;
3343         int plane;
3344
3345         if (INTEL_INFO(dev)->gen < 9)
3346                 return 0;
3347
3348         drm_modeset_lock_all(dev);
3349
3350         ddb = &dev_priv->wm.skl_hw.ddb;
3351
3352         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3353
3354         for_each_pipe(dev_priv, pipe) {
3355                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3356
3357                 for_each_plane(dev_priv, pipe, plane) {
3358                         entry = &ddb->plane[pipe][plane];
3359                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3360                                    entry->start, entry->end,
3361                                    skl_ddb_entry_size(entry));
3362                 }
3363
3364                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3365                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3366                            entry->end, skl_ddb_entry_size(entry));
3367         }
3368
3369         drm_modeset_unlock_all(dev);
3370
3371         return 0;
3372 }
3373
3374 static void drrs_status_per_crtc(struct seq_file *m,
3375                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3376 {
3377         struct intel_encoder *intel_encoder;
3378         struct drm_i915_private *dev_priv = dev->dev_private;
3379         struct i915_drrs *drrs = &dev_priv->drrs;
3380         int vrefresh = 0;
3381
3382         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3383                 /* Encoder connected on this CRTC */
3384                 switch (intel_encoder->type) {
3385                 case INTEL_OUTPUT_EDP:
3386                         seq_puts(m, "eDP:\n");
3387                         break;
3388                 case INTEL_OUTPUT_DSI:
3389                         seq_puts(m, "DSI:\n");
3390                         break;
3391                 case INTEL_OUTPUT_HDMI:
3392                         seq_puts(m, "HDMI:\n");
3393                         break;
3394                 case INTEL_OUTPUT_DISPLAYPORT:
3395                         seq_puts(m, "DP:\n");
3396                         break;
3397                 default:
3398                         seq_printf(m, "Other encoder (id=%d).\n",
3399                                                 intel_encoder->type);
3400                         return;
3401                 }
3402         }
3403
3404         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3405                 seq_puts(m, "\tVBT: DRRS_type: Static");
3406         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3407                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3408         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3409                 seq_puts(m, "\tVBT: DRRS_type: None");
3410         else
3411                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3412
3413         seq_puts(m, "\n\n");
3414
3415         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3416                 struct intel_panel *panel;
3417
3418                 mutex_lock(&drrs->mutex);
3419                 /* DRRS Supported */
3420                 seq_puts(m, "\tDRRS Supported: Yes\n");
3421
3422                 /* disable_drrs() will make drrs->dp NULL */
3423                 if (!drrs->dp) {
3424                         seq_puts(m, "Idleness DRRS: Disabled");
3425                         mutex_unlock(&drrs->mutex);
3426                         return;
3427                 }
3428
3429                 panel = &drrs->dp->attached_connector->panel;
3430                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3431                                         drrs->busy_frontbuffer_bits);
3432
3433                 seq_puts(m, "\n\t\t");
3434                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3435                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3436                         vrefresh = panel->fixed_mode->vrefresh;
3437                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3438                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3439                         vrefresh = panel->downclock_mode->vrefresh;
3440                 } else {
3441                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3442                                                 drrs->refresh_rate_type);
3443                         mutex_unlock(&drrs->mutex);
3444                         return;
3445                 }
3446                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3447
3448                 seq_puts(m, "\n\t\t");
3449                 mutex_unlock(&drrs->mutex);
3450         } else {
3451                 /* DRRS not supported. Print the VBT parameter*/
3452                 seq_puts(m, "\tDRRS Supported : No");
3453         }
3454         seq_puts(m, "\n");
3455 }
3456
3457 static int i915_drrs_status(struct seq_file *m, void *unused)
3458 {
3459         struct drm_info_node *node = m->private;
3460         struct drm_device *dev = node->minor->dev;
3461         struct intel_crtc *intel_crtc;
3462         int active_crtc_cnt = 0;
3463
3464         for_each_intel_crtc(dev, intel_crtc) {
3465                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3466
3467                 if (intel_crtc->base.state->active) {
3468                         active_crtc_cnt++;
3469                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3470
3471                         drrs_status_per_crtc(m, dev, intel_crtc);
3472                 }
3473
3474                 drm_modeset_unlock(&intel_crtc->base.mutex);
3475         }
3476
3477         if (!active_crtc_cnt)
3478                 seq_puts(m, "No active crtc found\n");
3479
3480         return 0;
3481 }
3482
3483 struct pipe_crc_info {
3484         const char *name;
3485         struct drm_device *dev;
3486         enum pipe pipe;
3487 };
3488
3489 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3490 {
3491         struct drm_info_node *node = (struct drm_info_node *) m->private;
3492         struct drm_device *dev = node->minor->dev;
3493         struct drm_encoder *encoder;
3494         struct intel_encoder *intel_encoder;
3495         struct intel_digital_port *intel_dig_port;
3496         drm_modeset_lock_all(dev);
3497         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3498                 intel_encoder = to_intel_encoder(encoder);
3499                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3500                         continue;
3501                 intel_dig_port = enc_to_dig_port(encoder);
3502                 if (!intel_dig_port->dp.can_mst)
3503                         continue;
3504                 seq_printf(m, "MST Source Port %c\n",
3505                            port_name(intel_dig_port->port));
3506                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3507         }
3508         drm_modeset_unlock_all(dev);
3509         return 0;
3510 }
3511
3512 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3513 {
3514         struct pipe_crc_info *info = inode->i_private;
3515         struct drm_i915_private *dev_priv = info->dev->dev_private;
3516         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3517
3518         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3519                 return -ENODEV;
3520
3521         spin_lock_irq(&pipe_crc->lock);
3522
3523         if (pipe_crc->opened) {
3524                 spin_unlock_irq(&pipe_crc->lock);
3525                 return -EBUSY; /* already open */
3526         }
3527
3528         pipe_crc->opened = true;
3529         filep->private_data = inode->i_private;
3530
3531         spin_unlock_irq(&pipe_crc->lock);
3532
3533         return 0;
3534 }
3535
3536 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3537 {
3538         struct pipe_crc_info *info = inode->i_private;
3539         struct drm_i915_private *dev_priv = info->dev->dev_private;
3540         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3541
3542         spin_lock_irq(&pipe_crc->lock);
3543         pipe_crc->opened = false;
3544         spin_unlock_irq(&pipe_crc->lock);
3545
3546         return 0;
3547 }
3548
3549 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3550 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3551 /* account for \'0' */
3552 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3553
3554 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3555 {
3556         assert_spin_locked(&pipe_crc->lock);
3557         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3558                         INTEL_PIPE_CRC_ENTRIES_NR);
3559 }
3560
3561 static ssize_t
3562 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3563                    loff_t *pos)
3564 {
3565         struct pipe_crc_info *info = filep->private_data;
3566         struct drm_device *dev = info->dev;
3567         struct drm_i915_private *dev_priv = dev->dev_private;
3568         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3569         char buf[PIPE_CRC_BUFFER_LEN];
3570         int n_entries;
3571         ssize_t bytes_read;
3572
3573         /*
3574          * Don't allow user space to provide buffers not big enough to hold
3575          * a line of data.
3576          */
3577         if (count < PIPE_CRC_LINE_LEN)
3578                 return -EINVAL;
3579
3580         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3581                 return 0;
3582
3583         /* nothing to read */
3584         spin_lock_irq(&pipe_crc->lock);
3585         while (pipe_crc_data_count(pipe_crc) == 0) {
3586                 int ret;
3587
3588                 if (filep->f_flags & O_NONBLOCK) {
3589                         spin_unlock_irq(&pipe_crc->lock);
3590                         return -EAGAIN;
3591                 }
3592
3593                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3594                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3595                 if (ret) {
3596                         spin_unlock_irq(&pipe_crc->lock);
3597                         return ret;
3598                 }
3599         }
3600
3601         /* We now have one or more entries to read */
3602         n_entries = count / PIPE_CRC_LINE_LEN;
3603
3604         bytes_read = 0;
3605         while (n_entries > 0) {
3606                 struct intel_pipe_crc_entry *entry =
3607                         &pipe_crc->entries[pipe_crc->tail];
3608                 int ret;
3609
3610                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3611                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3612                         break;
3613
3614                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3615                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3616
3617                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3618                                        "%8u %8x %8x %8x %8x %8x\n",
3619                                        entry->frame, entry->crc[0],
3620                                        entry->crc[1], entry->crc[2],
3621                                        entry->crc[3], entry->crc[4]);
3622
3623                 spin_unlock_irq(&pipe_crc->lock);
3624
3625                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3626                 if (ret == PIPE_CRC_LINE_LEN)
3627                         return -EFAULT;
3628
3629                 user_buf += PIPE_CRC_LINE_LEN;
3630                 n_entries--;
3631
3632                 spin_lock_irq(&pipe_crc->lock);
3633         }
3634
3635         spin_unlock_irq(&pipe_crc->lock);
3636
3637         return bytes_read;
3638 }
3639
3640 static const struct file_operations i915_pipe_crc_fops = {
3641         .owner = THIS_MODULE,
3642         .open = i915_pipe_crc_open,
3643         .read = i915_pipe_crc_read,
3644         .release = i915_pipe_crc_release,
3645 };
3646
3647 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3648         {
3649                 .name = "i915_pipe_A_crc",
3650                 .pipe = PIPE_A,
3651         },
3652         {
3653                 .name = "i915_pipe_B_crc",
3654                 .pipe = PIPE_B,
3655         },
3656         {
3657                 .name = "i915_pipe_C_crc",
3658                 .pipe = PIPE_C,
3659         },
3660 };
3661
3662 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3663                                 enum pipe pipe)
3664 {
3665         struct drm_device *dev = minor->dev;
3666         struct dentry *ent;
3667         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3668
3669         info->dev = dev;
3670         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3671                                   &i915_pipe_crc_fops);
3672         if (!ent)
3673                 return -ENOMEM;
3674
3675         return drm_add_fake_info_node(minor, ent, info);
3676 }
3677
3678 static const char * const pipe_crc_sources[] = {
3679         "none",
3680         "plane1",
3681         "plane2",
3682         "pf",
3683         "pipe",
3684         "TV",
3685         "DP-B",
3686         "DP-C",
3687         "DP-D",
3688         "auto",
3689 };
3690
3691 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3692 {
3693         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3694         return pipe_crc_sources[source];
3695 }
3696
3697 static int display_crc_ctl_show(struct seq_file *m, void *data)
3698 {
3699         struct drm_device *dev = m->private;
3700         struct drm_i915_private *dev_priv = dev->dev_private;
3701         int i;
3702
3703         for (i = 0; i < I915_MAX_PIPES; i++)
3704                 seq_printf(m, "%c %s\n", pipe_name(i),
3705                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3706
3707         return 0;
3708 }
3709
3710 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3711 {
3712         struct drm_device *dev = inode->i_private;
3713
3714         return single_open(file, display_crc_ctl_show, dev);
3715 }
3716
3717 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3718                                  uint32_t *val)
3719 {
3720         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3721                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3722
3723         switch (*source) {
3724         case INTEL_PIPE_CRC_SOURCE_PIPE:
3725                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3726                 break;
3727         case INTEL_PIPE_CRC_SOURCE_NONE:
3728                 *val = 0;
3729                 break;
3730         default:
3731                 return -EINVAL;
3732         }
3733
3734         return 0;
3735 }
3736
3737 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3738                                      enum intel_pipe_crc_source *source)
3739 {
3740         struct intel_encoder *encoder;
3741         struct intel_crtc *crtc;
3742         struct intel_digital_port *dig_port;
3743         int ret = 0;
3744
3745         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3746
3747         drm_modeset_lock_all(dev);
3748         for_each_intel_encoder(dev, encoder) {
3749                 if (!encoder->base.crtc)
3750                         continue;
3751
3752                 crtc = to_intel_crtc(encoder->base.crtc);
3753
3754                 if (crtc->pipe != pipe)
3755                         continue;
3756
3757                 switch (encoder->type) {
3758                 case INTEL_OUTPUT_TVOUT:
3759                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3760                         break;
3761                 case INTEL_OUTPUT_DISPLAYPORT:
3762                 case INTEL_OUTPUT_EDP:
3763                         dig_port = enc_to_dig_port(&encoder->base);
3764                         switch (dig_port->port) {
3765                         case PORT_B:
3766                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3767                                 break;
3768                         case PORT_C:
3769                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3770                                 break;
3771                         case PORT_D:
3772                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3773                                 break;
3774                         default:
3775                                 WARN(1, "nonexisting DP port %c\n",
3776                                      port_name(dig_port->port));
3777                                 break;
3778                         }
3779                         break;
3780                 default:
3781                         break;
3782                 }
3783         }
3784         drm_modeset_unlock_all(dev);
3785
3786         return ret;
3787 }
3788
3789 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3790                                 enum pipe pipe,
3791                                 enum intel_pipe_crc_source *source,
3792                                 uint32_t *val)
3793 {
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         bool need_stable_symbols = false;
3796
3797         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3798                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3799                 if (ret)
3800                         return ret;
3801         }
3802
3803         switch (*source) {
3804         case INTEL_PIPE_CRC_SOURCE_PIPE:
3805                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3806                 break;
3807         case INTEL_PIPE_CRC_SOURCE_DP_B:
3808                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3809                 need_stable_symbols = true;
3810                 break;
3811         case INTEL_PIPE_CRC_SOURCE_DP_C:
3812                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3813                 need_stable_symbols = true;
3814                 break;
3815         case INTEL_PIPE_CRC_SOURCE_DP_D:
3816                 if (!IS_CHERRYVIEW(dev))
3817                         return -EINVAL;
3818                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3819                 need_stable_symbols = true;
3820                 break;
3821         case INTEL_PIPE_CRC_SOURCE_NONE:
3822                 *val = 0;
3823                 break;
3824         default:
3825                 return -EINVAL;
3826         }
3827
3828         /*
3829          * When the pipe CRC tap point is after the transcoders we need
3830          * to tweak symbol-level features to produce a deterministic series of
3831          * symbols for a given frame. We need to reset those features only once
3832          * a frame (instead of every nth symbol):
3833          *   - DC-balance: used to ensure a better clock recovery from the data
3834          *     link (SDVO)
3835          *   - DisplayPort scrambling: used for EMI reduction
3836          */
3837         if (need_stable_symbols) {
3838                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3839
3840                 tmp |= DC_BALANCE_RESET_VLV;
3841                 switch (pipe) {
3842                 case PIPE_A:
3843                         tmp |= PIPE_A_SCRAMBLE_RESET;
3844                         break;
3845                 case PIPE_B:
3846                         tmp |= PIPE_B_SCRAMBLE_RESET;
3847                         break;
3848                 case PIPE_C:
3849                         tmp |= PIPE_C_SCRAMBLE_RESET;
3850                         break;
3851                 default:
3852                         return -EINVAL;
3853                 }
3854                 I915_WRITE(PORT_DFT2_G4X, tmp);
3855         }
3856
3857         return 0;
3858 }
3859
3860 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3861                                  enum pipe pipe,
3862                                  enum intel_pipe_crc_source *source,
3863                                  uint32_t *val)
3864 {
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866         bool need_stable_symbols = false;
3867
3868         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3869                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3870                 if (ret)
3871                         return ret;
3872         }
3873
3874         switch (*source) {
3875         case INTEL_PIPE_CRC_SOURCE_PIPE:
3876                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3877                 break;
3878         case INTEL_PIPE_CRC_SOURCE_TV:
3879                 if (!SUPPORTS_TV(dev))
3880                         return -EINVAL;
3881                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3882                 break;
3883         case INTEL_PIPE_CRC_SOURCE_DP_B:
3884                 if (!IS_G4X(dev))
3885                         return -EINVAL;
3886                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3887                 need_stable_symbols = true;
3888                 break;
3889         case INTEL_PIPE_CRC_SOURCE_DP_C:
3890                 if (!IS_G4X(dev))
3891                         return -EINVAL;
3892                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3893                 need_stable_symbols = true;
3894                 break;
3895         case INTEL_PIPE_CRC_SOURCE_DP_D:
3896                 if (!IS_G4X(dev))
3897                         return -EINVAL;
3898                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3899                 need_stable_symbols = true;
3900                 break;
3901         case INTEL_PIPE_CRC_SOURCE_NONE:
3902                 *val = 0;
3903                 break;
3904         default:
3905                 return -EINVAL;
3906         }
3907
3908         /*
3909          * When the pipe CRC tap point is after the transcoders we need
3910          * to tweak symbol-level features to produce a deterministic series of
3911          * symbols for a given frame. We need to reset those features only once
3912          * a frame (instead of every nth symbol):
3913          *   - DC-balance: used to ensure a better clock recovery from the data
3914          *     link (SDVO)
3915          *   - DisplayPort scrambling: used for EMI reduction
3916          */
3917         if (need_stable_symbols) {
3918                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3919
3920                 WARN_ON(!IS_G4X(dev));
3921
3922                 I915_WRITE(PORT_DFT_I9XX,
3923                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3924
3925                 if (pipe == PIPE_A)
3926                         tmp |= PIPE_A_SCRAMBLE_RESET;
3927                 else
3928                         tmp |= PIPE_B_SCRAMBLE_RESET;
3929
3930                 I915_WRITE(PORT_DFT2_G4X, tmp);
3931         }
3932
3933         return 0;
3934 }
3935
3936 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3937                                          enum pipe pipe)
3938 {
3939         struct drm_i915_private *dev_priv = dev->dev_private;
3940         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3941
3942         switch (pipe) {
3943         case PIPE_A:
3944                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3945                 break;
3946         case PIPE_B:
3947                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3948                 break;
3949         case PIPE_C:
3950                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3951                 break;
3952         default:
3953                 return;
3954         }
3955         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3956                 tmp &= ~DC_BALANCE_RESET_VLV;
3957         I915_WRITE(PORT_DFT2_G4X, tmp);
3958
3959 }
3960
3961 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3962                                          enum pipe pipe)
3963 {
3964         struct drm_i915_private *dev_priv = dev->dev_private;
3965         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3966
3967         if (pipe == PIPE_A)
3968                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3969         else
3970                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3971         I915_WRITE(PORT_DFT2_G4X, tmp);
3972
3973         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3974                 I915_WRITE(PORT_DFT_I9XX,
3975                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3976         }
3977 }
3978
3979 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3980                                 uint32_t *val)
3981 {
3982         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3983                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3984
3985         switch (*source) {
3986         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3987                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3988                 break;
3989         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3990                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3991                 break;
3992         case INTEL_PIPE_CRC_SOURCE_PIPE:
3993                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3994                 break;
3995         case INTEL_PIPE_CRC_SOURCE_NONE:
3996                 *val = 0;
3997                 break;
3998         default:
3999                 return -EINVAL;
4000         }
4001
4002         return 0;
4003 }
4004
4005 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4006 {
4007         struct drm_i915_private *dev_priv = dev->dev_private;
4008         struct intel_crtc *crtc =
4009                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4010         struct intel_crtc_state *pipe_config;
4011         struct drm_atomic_state *state;
4012         int ret = 0;
4013
4014         drm_modeset_lock_all(dev);
4015         state = drm_atomic_state_alloc(dev);
4016         if (!state) {
4017                 ret = -ENOMEM;
4018                 goto out;
4019         }
4020
4021         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4022         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4023         if (IS_ERR(pipe_config)) {
4024                 ret = PTR_ERR(pipe_config);
4025                 goto out;
4026         }
4027
4028         pipe_config->pch_pfit.force_thru = enable;
4029         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4030             pipe_config->pch_pfit.enabled != enable)
4031                 pipe_config->base.connectors_changed = true;
4032
4033         ret = drm_atomic_commit(state);
4034 out:
4035         drm_modeset_unlock_all(dev);
4036         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4037         if (ret)
4038                 drm_atomic_state_free(state);
4039 }
4040
4041 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4042                                 enum pipe pipe,
4043                                 enum intel_pipe_crc_source *source,
4044                                 uint32_t *val)
4045 {
4046         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4047                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4048
4049         switch (*source) {
4050         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4051                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4052                 break;
4053         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4054                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4055                 break;
4056         case INTEL_PIPE_CRC_SOURCE_PF:
4057                 if (IS_HASWELL(dev) && pipe == PIPE_A)
4058                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
4059
4060                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4061                 break;
4062         case INTEL_PIPE_CRC_SOURCE_NONE:
4063                 *val = 0;
4064                 break;
4065         default:
4066                 return -EINVAL;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4073                                enum intel_pipe_crc_source source)
4074 {
4075         struct drm_i915_private *dev_priv = dev->dev_private;
4076         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4077         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4078                                                                         pipe));
4079         enum intel_display_power_domain power_domain;
4080         u32 val = 0; /* shut up gcc */
4081         int ret;
4082
4083         if (pipe_crc->source == source)
4084                 return 0;
4085
4086         /* forbid changing the source without going back to 'none' */
4087         if (pipe_crc->source && source)
4088                 return -EINVAL;
4089
4090         power_domain = POWER_DOMAIN_PIPE(pipe);
4091         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4092                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4093                 return -EIO;
4094         }
4095
4096         if (IS_GEN2(dev))
4097                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4098         else if (INTEL_INFO(dev)->gen < 5)
4099                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4100         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4101                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4102         else if (IS_GEN5(dev) || IS_GEN6(dev))
4103                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4104         else
4105                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4106
4107         if (ret != 0)
4108                 goto out;
4109
4110         /* none -> real source transition */
4111         if (source) {
4112                 struct intel_pipe_crc_entry *entries;
4113
4114                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4115                                  pipe_name(pipe), pipe_crc_source_name(source));
4116
4117                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4118                                   sizeof(pipe_crc->entries[0]),
4119                                   GFP_KERNEL);
4120                 if (!entries) {
4121                         ret = -ENOMEM;
4122                         goto out;
4123                 }
4124
4125                 /*
4126                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4127                  * enabled and disabled dynamically based on package C states,
4128                  * user space can't make reliable use of the CRCs, so let's just
4129                  * completely disable it.
4130                  */
4131                 hsw_disable_ips(crtc);
4132
4133                 spin_lock_irq(&pipe_crc->lock);
4134                 kfree(pipe_crc->entries);
4135                 pipe_crc->entries = entries;
4136                 pipe_crc->head = 0;
4137                 pipe_crc->tail = 0;
4138                 spin_unlock_irq(&pipe_crc->lock);
4139         }
4140
4141         pipe_crc->source = source;
4142
4143         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4144         POSTING_READ(PIPE_CRC_CTL(pipe));
4145
4146         /* real source -> none transition */
4147         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4148                 struct intel_pipe_crc_entry *entries;
4149                 struct intel_crtc *crtc =
4150                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4151
4152                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4153                                  pipe_name(pipe));
4154
4155                 drm_modeset_lock(&crtc->base.mutex, NULL);
4156                 if (crtc->base.state->active)
4157                         intel_wait_for_vblank(dev, pipe);
4158                 drm_modeset_unlock(&crtc->base.mutex);
4159
4160                 spin_lock_irq(&pipe_crc->lock);
4161                 entries = pipe_crc->entries;
4162                 pipe_crc->entries = NULL;
4163                 pipe_crc->head = 0;
4164                 pipe_crc->tail = 0;
4165                 spin_unlock_irq(&pipe_crc->lock);
4166
4167                 kfree(entries);
4168
4169                 if (IS_G4X(dev))
4170                         g4x_undo_pipe_scramble_reset(dev, pipe);
4171                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4172                         vlv_undo_pipe_scramble_reset(dev, pipe);
4173                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4174                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4175
4176                 hsw_enable_ips(crtc);
4177         }
4178
4179         ret = 0;
4180
4181 out:
4182         intel_display_power_put(dev_priv, power_domain);
4183
4184         return ret;
4185 }
4186
4187 /*
4188  * Parse pipe CRC command strings:
4189  *   command: wsp* object wsp+ name wsp+ source wsp*
4190  *   object: 'pipe'
4191  *   name: (A | B | C)
4192  *   source: (none | plane1 | plane2 | pf)
4193  *   wsp: (#0x20 | #0x9 | #0xA)+
4194  *
4195  * eg.:
4196  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4197  *  "pipe A none"    ->  Stop CRC
4198  */
4199 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4200 {
4201         int n_words = 0;
4202
4203         while (*buf) {
4204                 char *end;
4205
4206                 /* skip leading white space */
4207                 buf = skip_spaces(buf);
4208                 if (!*buf)
4209                         break;  /* end of buffer */
4210
4211                 /* find end of word */
4212                 for (end = buf; *end && !isspace(*end); end++)
4213                         ;
4214
4215                 if (n_words == max_words) {
4216                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4217                                          max_words);
4218                         return -EINVAL; /* ran out of words[] before bytes */
4219                 }
4220
4221                 if (*end)
4222                         *end++ = '\0';
4223                 words[n_words++] = buf;
4224                 buf = end;
4225         }
4226
4227         return n_words;
4228 }
4229
4230 enum intel_pipe_crc_object {
4231         PIPE_CRC_OBJECT_PIPE,
4232 };
4233
4234 static const char * const pipe_crc_objects[] = {
4235         "pipe",
4236 };
4237
4238 static int
4239 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4240 {
4241         int i;
4242
4243         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4244                 if (!strcmp(buf, pipe_crc_objects[i])) {
4245                         *o = i;
4246                         return 0;
4247                     }
4248
4249         return -EINVAL;
4250 }
4251
4252 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4253 {
4254         const char name = buf[0];
4255
4256         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4257                 return -EINVAL;
4258
4259         *pipe = name - 'A';
4260
4261         return 0;
4262 }
4263
4264 static int
4265 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4266 {
4267         int i;
4268
4269         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4270                 if (!strcmp(buf, pipe_crc_sources[i])) {
4271                         *s = i;
4272                         return 0;
4273                     }
4274
4275         return -EINVAL;
4276 }
4277
4278 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4279 {
4280 #define N_WORDS 3
4281         int n_words;
4282         char *words[N_WORDS];
4283         enum pipe pipe;
4284         enum intel_pipe_crc_object object;
4285         enum intel_pipe_crc_source source;
4286
4287         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4288         if (n_words != N_WORDS) {
4289                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4290                                  N_WORDS);
4291                 return -EINVAL;
4292         }
4293
4294         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4295                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4296                 return -EINVAL;
4297         }
4298
4299         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4300                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4301                 return -EINVAL;
4302         }
4303
4304         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4305                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4306                 return -EINVAL;
4307         }
4308
4309         return pipe_crc_set_source(dev, pipe, source);
4310 }
4311
4312 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4313                                      size_t len, loff_t *offp)
4314 {
4315         struct seq_file *m = file->private_data;
4316         struct drm_device *dev = m->private;
4317         char *tmpbuf;
4318         int ret;
4319
4320         if (len == 0)
4321                 return 0;
4322
4323         if (len > PAGE_SIZE - 1) {
4324                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4325                                  PAGE_SIZE);
4326                 return -E2BIG;
4327         }
4328
4329         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4330         if (!tmpbuf)
4331                 return -ENOMEM;
4332
4333         if (copy_from_user(tmpbuf, ubuf, len)) {
4334                 ret = -EFAULT;
4335                 goto out;
4336         }
4337         tmpbuf[len] = '\0';
4338
4339         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4340
4341 out:
4342         kfree(tmpbuf);
4343         if (ret < 0)
4344                 return ret;
4345
4346         *offp += len;
4347         return len;
4348 }
4349
4350 static const struct file_operations i915_display_crc_ctl_fops = {
4351         .owner = THIS_MODULE,
4352         .open = display_crc_ctl_open,
4353         .read = seq_read,
4354         .llseek = seq_lseek,
4355         .release = single_release,
4356         .write = display_crc_ctl_write
4357 };
4358
4359 static ssize_t i915_displayport_test_active_write(struct file *file,
4360                                             const char __user *ubuf,
4361                                             size_t len, loff_t *offp)
4362 {
4363         char *input_buffer;
4364         int status = 0;
4365         struct drm_device *dev;
4366         struct drm_connector *connector;
4367         struct list_head *connector_list;
4368         struct intel_dp *intel_dp;
4369         int val = 0;
4370
4371         dev = ((struct seq_file *)file->private_data)->private;
4372
4373         connector_list = &dev->mode_config.connector_list;
4374
4375         if (len == 0)
4376                 return 0;
4377
4378         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4379         if (!input_buffer)
4380                 return -ENOMEM;
4381
4382         if (copy_from_user(input_buffer, ubuf, len)) {
4383                 status = -EFAULT;
4384                 goto out;
4385         }
4386
4387         input_buffer[len] = '\0';
4388         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4389
4390         list_for_each_entry(connector, connector_list, head) {
4391
4392                 if (connector->connector_type !=
4393                     DRM_MODE_CONNECTOR_DisplayPort)
4394                         continue;
4395
4396                 if (connector->status == connector_status_connected &&
4397                     connector->encoder != NULL) {
4398                         intel_dp = enc_to_intel_dp(connector->encoder);
4399                         status = kstrtoint(input_buffer, 10, &val);
4400                         if (status < 0)
4401                                 goto out;
4402                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4403                         /* To prevent erroneous activation of the compliance
4404                          * testing code, only accept an actual value of 1 here
4405                          */
4406                         if (val == 1)
4407                                 intel_dp->compliance_test_active = 1;
4408                         else
4409                                 intel_dp->compliance_test_active = 0;
4410                 }
4411         }
4412 out:
4413         kfree(input_buffer);
4414         if (status < 0)
4415                 return status;
4416
4417         *offp += len;
4418         return len;
4419 }
4420
4421 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4422 {
4423         struct drm_device *dev = m->private;
4424         struct drm_connector *connector;
4425         struct list_head *connector_list = &dev->mode_config.connector_list;
4426         struct intel_dp *intel_dp;
4427
4428         list_for_each_entry(connector, connector_list, head) {
4429
4430                 if (connector->connector_type !=
4431                     DRM_MODE_CONNECTOR_DisplayPort)
4432                         continue;
4433
4434                 if (connector->status == connector_status_connected &&
4435                     connector->encoder != NULL) {
4436                         intel_dp = enc_to_intel_dp(connector->encoder);
4437                         if (intel_dp->compliance_test_active)
4438                                 seq_puts(m, "1");
4439                         else
4440                                 seq_puts(m, "0");
4441                 } else
4442                         seq_puts(m, "0");
4443         }
4444
4445         return 0;
4446 }
4447
4448 static int i915_displayport_test_active_open(struct inode *inode,
4449                                        struct file *file)
4450 {
4451         struct drm_device *dev = inode->i_private;
4452
4453         return single_open(file, i915_displayport_test_active_show, dev);
4454 }
4455
4456 static const struct file_operations i915_displayport_test_active_fops = {
4457         .owner = THIS_MODULE,
4458         .open = i915_displayport_test_active_open,
4459         .read = seq_read,
4460         .llseek = seq_lseek,
4461         .release = single_release,
4462         .write = i915_displayport_test_active_write
4463 };
4464
4465 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4466 {
4467         struct drm_device *dev = m->private;
4468         struct drm_connector *connector;
4469         struct list_head *connector_list = &dev->mode_config.connector_list;
4470         struct intel_dp *intel_dp;
4471
4472         list_for_each_entry(connector, connector_list, head) {
4473
4474                 if (connector->connector_type !=
4475                     DRM_MODE_CONNECTOR_DisplayPort)
4476                         continue;
4477
4478                 if (connector->status == connector_status_connected &&
4479                     connector->encoder != NULL) {
4480                         intel_dp = enc_to_intel_dp(connector->encoder);
4481                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4482                 } else
4483                         seq_puts(m, "0");
4484         }
4485
4486         return 0;
4487 }
4488 static int i915_displayport_test_data_open(struct inode *inode,
4489                                        struct file *file)
4490 {
4491         struct drm_device *dev = inode->i_private;
4492
4493         return single_open(file, i915_displayport_test_data_show, dev);
4494 }
4495
4496 static const struct file_operations i915_displayport_test_data_fops = {
4497         .owner = THIS_MODULE,
4498         .open = i915_displayport_test_data_open,
4499         .read = seq_read,
4500         .llseek = seq_lseek,
4501         .release = single_release
4502 };
4503
4504 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4505 {
4506         struct drm_device *dev = m->private;
4507         struct drm_connector *connector;
4508         struct list_head *connector_list = &dev->mode_config.connector_list;
4509         struct intel_dp *intel_dp;
4510
4511         list_for_each_entry(connector, connector_list, head) {
4512
4513                 if (connector->connector_type !=
4514                     DRM_MODE_CONNECTOR_DisplayPort)
4515                         continue;
4516
4517                 if (connector->status == connector_status_connected &&
4518                     connector->encoder != NULL) {
4519                         intel_dp = enc_to_intel_dp(connector->encoder);
4520                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4521                 } else
4522                         seq_puts(m, "0");
4523         }
4524
4525         return 0;
4526 }
4527
4528 static int i915_displayport_test_type_open(struct inode *inode,
4529                                        struct file *file)
4530 {
4531         struct drm_device *dev = inode->i_private;
4532
4533         return single_open(file, i915_displayport_test_type_show, dev);
4534 }
4535
4536 static const struct file_operations i915_displayport_test_type_fops = {
4537         .owner = THIS_MODULE,
4538         .open = i915_displayport_test_type_open,
4539         .read = seq_read,
4540         .llseek = seq_lseek,
4541         .release = single_release
4542 };
4543
4544 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4545 {
4546         struct drm_device *dev = m->private;
4547         int level;
4548         int num_levels;
4549
4550         if (IS_CHERRYVIEW(dev))
4551                 num_levels = 3;
4552         else if (IS_VALLEYVIEW(dev))
4553                 num_levels = 1;
4554         else
4555                 num_levels = ilk_wm_max_level(dev) + 1;
4556
4557         drm_modeset_lock_all(dev);
4558
4559         for (level = 0; level < num_levels; level++) {
4560                 unsigned int latency = wm[level];
4561
4562                 /*
4563                  * - WM1+ latency values in 0.5us units
4564                  * - latencies are in us on gen9/vlv/chv
4565                  */
4566                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4567                     IS_CHERRYVIEW(dev))
4568                         latency *= 10;
4569                 else if (level > 0)
4570                         latency *= 5;
4571
4572                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4573                            level, wm[level], latency / 10, latency % 10);
4574         }
4575
4576         drm_modeset_unlock_all(dev);
4577 }
4578
4579 static int pri_wm_latency_show(struct seq_file *m, void *data)
4580 {
4581         struct drm_device *dev = m->private;
4582         struct drm_i915_private *dev_priv = dev->dev_private;
4583         const uint16_t *latencies;
4584
4585         if (INTEL_INFO(dev)->gen >= 9)
4586                 latencies = dev_priv->wm.skl_latency;
4587         else
4588                 latencies = to_i915(dev)->wm.pri_latency;
4589
4590         wm_latency_show(m, latencies);
4591
4592         return 0;
4593 }
4594
4595 static int spr_wm_latency_show(struct seq_file *m, void *data)
4596 {
4597         struct drm_device *dev = m->private;
4598         struct drm_i915_private *dev_priv = dev->dev_private;
4599         const uint16_t *latencies;
4600
4601         if (INTEL_INFO(dev)->gen >= 9)
4602                 latencies = dev_priv->wm.skl_latency;
4603         else
4604                 latencies = to_i915(dev)->wm.spr_latency;
4605
4606         wm_latency_show(m, latencies);
4607
4608         return 0;
4609 }
4610
4611 static int cur_wm_latency_show(struct seq_file *m, void *data)
4612 {
4613         struct drm_device *dev = m->private;
4614         struct drm_i915_private *dev_priv = dev->dev_private;
4615         const uint16_t *latencies;
4616
4617         if (INTEL_INFO(dev)->gen >= 9)
4618                 latencies = dev_priv->wm.skl_latency;
4619         else
4620                 latencies = to_i915(dev)->wm.cur_latency;
4621
4622         wm_latency_show(m, latencies);
4623
4624         return 0;
4625 }
4626
4627 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4628 {
4629         struct drm_device *dev = inode->i_private;
4630
4631         if (INTEL_INFO(dev)->gen < 5)
4632                 return -ENODEV;
4633
4634         return single_open(file, pri_wm_latency_show, dev);
4635 }
4636
4637 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4638 {
4639         struct drm_device *dev = inode->i_private;
4640
4641         if (HAS_GMCH_DISPLAY(dev))
4642                 return -ENODEV;
4643
4644         return single_open(file, spr_wm_latency_show, dev);
4645 }
4646
4647 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4648 {
4649         struct drm_device *dev = inode->i_private;
4650
4651         if (HAS_GMCH_DISPLAY(dev))
4652                 return -ENODEV;
4653
4654         return single_open(file, cur_wm_latency_show, dev);
4655 }
4656
4657 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4658                                 size_t len, loff_t *offp, uint16_t wm[8])
4659 {
4660         struct seq_file *m = file->private_data;
4661         struct drm_device *dev = m->private;
4662         uint16_t new[8] = { 0 };
4663         int num_levels;
4664         int level;
4665         int ret;
4666         char tmp[32];
4667
4668         if (IS_CHERRYVIEW(dev))
4669                 num_levels = 3;
4670         else if (IS_VALLEYVIEW(dev))
4671                 num_levels = 1;
4672         else
4673                 num_levels = ilk_wm_max_level(dev) + 1;
4674
4675         if (len >= sizeof(tmp))
4676                 return -EINVAL;
4677
4678         if (copy_from_user(tmp, ubuf, len))
4679                 return -EFAULT;
4680
4681         tmp[len] = '\0';
4682
4683         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4684                      &new[0], &new[1], &new[2], &new[3],
4685                      &new[4], &new[5], &new[6], &new[7]);
4686         if (ret != num_levels)
4687                 return -EINVAL;
4688
4689         drm_modeset_lock_all(dev);
4690
4691         for (level = 0; level < num_levels; level++)
4692                 wm[level] = new[level];
4693
4694         drm_modeset_unlock_all(dev);
4695
4696         return len;
4697 }
4698
4699
4700 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4701                                     size_t len, loff_t *offp)
4702 {
4703         struct seq_file *m = file->private_data;
4704         struct drm_device *dev = m->private;
4705         struct drm_i915_private *dev_priv = dev->dev_private;
4706         uint16_t *latencies;
4707
4708         if (INTEL_INFO(dev)->gen >= 9)
4709                 latencies = dev_priv->wm.skl_latency;
4710         else
4711                 latencies = to_i915(dev)->wm.pri_latency;
4712
4713         return wm_latency_write(file, ubuf, len, offp, latencies);
4714 }
4715
4716 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4717                                     size_t len, loff_t *offp)
4718 {
4719         struct seq_file *m = file->private_data;
4720         struct drm_device *dev = m->private;
4721         struct drm_i915_private *dev_priv = dev->dev_private;
4722         uint16_t *latencies;
4723
4724         if (INTEL_INFO(dev)->gen >= 9)
4725                 latencies = dev_priv->wm.skl_latency;
4726         else
4727                 latencies = to_i915(dev)->wm.spr_latency;
4728
4729         return wm_latency_write(file, ubuf, len, offp, latencies);
4730 }
4731
4732 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4733                                     size_t len, loff_t *offp)
4734 {
4735         struct seq_file *m = file->private_data;
4736         struct drm_device *dev = m->private;
4737         struct drm_i915_private *dev_priv = dev->dev_private;
4738         uint16_t *latencies;
4739
4740         if (INTEL_INFO(dev)->gen >= 9)
4741                 latencies = dev_priv->wm.skl_latency;
4742         else
4743                 latencies = to_i915(dev)->wm.cur_latency;
4744
4745         return wm_latency_write(file, ubuf, len, offp, latencies);
4746 }
4747
4748 static const struct file_operations i915_pri_wm_latency_fops = {
4749         .owner = THIS_MODULE,
4750         .open = pri_wm_latency_open,
4751         .read = seq_read,
4752         .llseek = seq_lseek,
4753         .release = single_release,
4754         .write = pri_wm_latency_write
4755 };
4756
4757 static const struct file_operations i915_spr_wm_latency_fops = {
4758         .owner = THIS_MODULE,
4759         .open = spr_wm_latency_open,
4760         .read = seq_read,
4761         .llseek = seq_lseek,
4762         .release = single_release,
4763         .write = spr_wm_latency_write
4764 };
4765
4766 static const struct file_operations i915_cur_wm_latency_fops = {
4767         .owner = THIS_MODULE,
4768         .open = cur_wm_latency_open,
4769         .read = seq_read,
4770         .llseek = seq_lseek,
4771         .release = single_release,
4772         .write = cur_wm_latency_write
4773 };
4774
4775 static int
4776 i915_wedged_get(void *data, u64 *val)
4777 {
4778         struct drm_device *dev = data;
4779         struct drm_i915_private *dev_priv = dev->dev_private;
4780
4781         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4782
4783         return 0;
4784 }
4785
4786 static int
4787 i915_wedged_set(void *data, u64 val)
4788 {
4789         struct drm_device *dev = data;
4790         struct drm_i915_private *dev_priv = dev->dev_private;
4791
4792         /*
4793          * There is no safeguard against this debugfs entry colliding
4794          * with the hangcheck calling same i915_handle_error() in
4795          * parallel, causing an explosion. For now we assume that the
4796          * test harness is responsible enough not to inject gpu hangs
4797          * while it is writing to 'i915_wedged'
4798          */
4799
4800         if (i915_reset_in_progress(&dev_priv->gpu_error))
4801                 return -EAGAIN;
4802
4803         intel_runtime_pm_get(dev_priv);
4804
4805         i915_handle_error(dev_priv, val,
4806                           "Manually setting wedged to %llu", val);
4807
4808         intel_runtime_pm_put(dev_priv);
4809
4810         return 0;
4811 }
4812
4813 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4814                         i915_wedged_get, i915_wedged_set,
4815                         "%llu\n");
4816
4817 static int
4818 i915_ring_stop_get(void *data, u64 *val)
4819 {
4820         struct drm_device *dev = data;
4821         struct drm_i915_private *dev_priv = dev->dev_private;
4822
4823         *val = dev_priv->gpu_error.stop_rings;
4824
4825         return 0;
4826 }
4827
4828 static int
4829 i915_ring_stop_set(void *data, u64 val)
4830 {
4831         struct drm_device *dev = data;
4832         struct drm_i915_private *dev_priv = dev->dev_private;
4833         int ret;
4834
4835         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4836
4837         ret = mutex_lock_interruptible(&dev->struct_mutex);
4838         if (ret)
4839                 return ret;
4840
4841         dev_priv->gpu_error.stop_rings = val;
4842         mutex_unlock(&dev->struct_mutex);
4843
4844         return 0;
4845 }
4846
4847 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4848                         i915_ring_stop_get, i915_ring_stop_set,
4849                         "0x%08llx\n");
4850
4851 static int
4852 i915_ring_missed_irq_get(void *data, u64 *val)
4853 {
4854         struct drm_device *dev = data;
4855         struct drm_i915_private *dev_priv = dev->dev_private;
4856
4857         *val = dev_priv->gpu_error.missed_irq_rings;
4858         return 0;
4859 }
4860
4861 static int
4862 i915_ring_missed_irq_set(void *data, u64 val)
4863 {
4864         struct drm_device *dev = data;
4865         struct drm_i915_private *dev_priv = dev->dev_private;
4866         int ret;
4867
4868         /* Lock against concurrent debugfs callers */
4869         ret = mutex_lock_interruptible(&dev->struct_mutex);
4870         if (ret)
4871                 return ret;
4872         dev_priv->gpu_error.missed_irq_rings = val;
4873         mutex_unlock(&dev->struct_mutex);
4874
4875         return 0;
4876 }
4877
4878 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4879                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4880                         "0x%08llx\n");
4881
4882 static int
4883 i915_ring_test_irq_get(void *data, u64 *val)
4884 {
4885         struct drm_device *dev = data;
4886         struct drm_i915_private *dev_priv = dev->dev_private;
4887
4888         *val = dev_priv->gpu_error.test_irq_rings;
4889
4890         return 0;
4891 }
4892
4893 static int
4894 i915_ring_test_irq_set(void *data, u64 val)
4895 {
4896         struct drm_device *dev = data;
4897         struct drm_i915_private *dev_priv = dev->dev_private;
4898         int ret;
4899
4900         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4901
4902         /* Lock against concurrent debugfs callers */
4903         ret = mutex_lock_interruptible(&dev->struct_mutex);
4904         if (ret)
4905                 return ret;
4906
4907         dev_priv->gpu_error.test_irq_rings = val;
4908         mutex_unlock(&dev->struct_mutex);
4909
4910         return 0;
4911 }
4912
4913 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4914                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4915                         "0x%08llx\n");
4916
4917 #define DROP_UNBOUND 0x1
4918 #define DROP_BOUND 0x2
4919 #define DROP_RETIRE 0x4
4920 #define DROP_ACTIVE 0x8
4921 #define DROP_ALL (DROP_UNBOUND | \
4922                   DROP_BOUND | \
4923                   DROP_RETIRE | \
4924                   DROP_ACTIVE)
4925 static int
4926 i915_drop_caches_get(void *data, u64 *val)
4927 {
4928         *val = DROP_ALL;
4929
4930         return 0;
4931 }
4932
4933 static int
4934 i915_drop_caches_set(void *data, u64 val)
4935 {
4936         struct drm_device *dev = data;
4937         struct drm_i915_private *dev_priv = dev->dev_private;
4938         int ret;
4939
4940         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4941
4942         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4943          * on ioctls on -EAGAIN. */
4944         ret = mutex_lock_interruptible(&dev->struct_mutex);
4945         if (ret)
4946                 return ret;
4947
4948         if (val & DROP_ACTIVE) {
4949                 ret = i915_gpu_idle(dev);
4950                 if (ret)
4951                         goto unlock;
4952         }
4953
4954         if (val & (DROP_RETIRE | DROP_ACTIVE))
4955                 i915_gem_retire_requests(dev_priv);
4956
4957         if (val & DROP_BOUND)
4958                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4959
4960         if (val & DROP_UNBOUND)
4961                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4962
4963 unlock:
4964         mutex_unlock(&dev->struct_mutex);
4965
4966         return ret;
4967 }
4968
4969 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4970                         i915_drop_caches_get, i915_drop_caches_set,
4971                         "0x%08llx\n");
4972
4973 static int
4974 i915_max_freq_get(void *data, u64 *val)
4975 {
4976         struct drm_device *dev = data;
4977         struct drm_i915_private *dev_priv = dev->dev_private;
4978         int ret;
4979
4980         if (INTEL_INFO(dev)->gen < 6)
4981                 return -ENODEV;
4982
4983         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4984
4985         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4986         if (ret)
4987                 return ret;
4988
4989         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4990         mutex_unlock(&dev_priv->rps.hw_lock);
4991
4992         return 0;
4993 }
4994
4995 static int
4996 i915_max_freq_set(void *data, u64 val)
4997 {
4998         struct drm_device *dev = data;
4999         struct drm_i915_private *dev_priv = dev->dev_private;
5000         u32 hw_max, hw_min;
5001         int ret;
5002
5003         if (INTEL_INFO(dev)->gen < 6)
5004                 return -ENODEV;
5005
5006         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5007
5008         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5009
5010         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5011         if (ret)
5012                 return ret;
5013
5014         /*
5015          * Turbo will still be enabled, but won't go above the set value.
5016          */
5017         val = intel_freq_opcode(dev_priv, val);
5018
5019         hw_max = dev_priv->rps.max_freq;
5020         hw_min = dev_priv->rps.min_freq;
5021
5022         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5023                 mutex_unlock(&dev_priv->rps.hw_lock);
5024                 return -EINVAL;
5025         }
5026
5027         dev_priv->rps.max_freq_softlimit = val;
5028
5029         intel_set_rps(dev_priv, val);
5030
5031         mutex_unlock(&dev_priv->rps.hw_lock);
5032
5033         return 0;
5034 }
5035
5036 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5037                         i915_max_freq_get, i915_max_freq_set,
5038                         "%llu\n");
5039
5040 static int
5041 i915_min_freq_get(void *data, u64 *val)
5042 {
5043         struct drm_device *dev = data;
5044         struct drm_i915_private *dev_priv = dev->dev_private;
5045         int ret;
5046
5047         if (INTEL_INFO(dev)->gen < 6)
5048                 return -ENODEV;
5049
5050         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5051
5052         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5053         if (ret)
5054                 return ret;
5055
5056         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5057         mutex_unlock(&dev_priv->rps.hw_lock);
5058
5059         return 0;
5060 }
5061
5062 static int
5063 i915_min_freq_set(void *data, u64 val)
5064 {
5065         struct drm_device *dev = data;
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067         u32 hw_max, hw_min;
5068         int ret;
5069
5070         if (INTEL_INFO(dev)->gen < 6)
5071                 return -ENODEV;
5072
5073         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5074
5075         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5076
5077         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5078         if (ret)
5079                 return ret;
5080
5081         /*
5082          * Turbo will still be enabled, but won't go below the set value.
5083          */
5084         val = intel_freq_opcode(dev_priv, val);
5085
5086         hw_max = dev_priv->rps.max_freq;
5087         hw_min = dev_priv->rps.min_freq;
5088
5089         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5090                 mutex_unlock(&dev_priv->rps.hw_lock);
5091                 return -EINVAL;
5092         }
5093
5094         dev_priv->rps.min_freq_softlimit = val;
5095
5096         intel_set_rps(dev_priv, val);
5097
5098         mutex_unlock(&dev_priv->rps.hw_lock);
5099
5100         return 0;
5101 }
5102
5103 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5104                         i915_min_freq_get, i915_min_freq_set,
5105                         "%llu\n");
5106
5107 static int
5108 i915_cache_sharing_get(void *data, u64 *val)
5109 {
5110         struct drm_device *dev = data;
5111         struct drm_i915_private *dev_priv = dev->dev_private;
5112         u32 snpcr;
5113         int ret;
5114
5115         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5116                 return -ENODEV;
5117
5118         ret = mutex_lock_interruptible(&dev->struct_mutex);
5119         if (ret)
5120                 return ret;
5121         intel_runtime_pm_get(dev_priv);
5122
5123         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5124
5125         intel_runtime_pm_put(dev_priv);
5126         mutex_unlock(&dev_priv->dev->struct_mutex);
5127
5128         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5129
5130         return 0;
5131 }
5132
5133 static int
5134 i915_cache_sharing_set(void *data, u64 val)
5135 {
5136         struct drm_device *dev = data;
5137         struct drm_i915_private *dev_priv = dev->dev_private;
5138         u32 snpcr;
5139
5140         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5141                 return -ENODEV;
5142
5143         if (val > 3)
5144                 return -EINVAL;
5145
5146         intel_runtime_pm_get(dev_priv);
5147         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5148
5149         /* Update the cache sharing policy here as well */
5150         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5151         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5152         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5153         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5154
5155         intel_runtime_pm_put(dev_priv);
5156         return 0;
5157 }
5158
5159 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5160                         i915_cache_sharing_get, i915_cache_sharing_set,
5161                         "%llu\n");
5162
5163 struct sseu_dev_status {
5164         unsigned int slice_total;
5165         unsigned int subslice_total;
5166         unsigned int subslice_per_slice;
5167         unsigned int eu_total;
5168         unsigned int eu_per_subslice;
5169 };
5170
5171 static void cherryview_sseu_device_status(struct drm_device *dev,
5172                                           struct sseu_dev_status *stat)
5173 {
5174         struct drm_i915_private *dev_priv = dev->dev_private;
5175         int ss_max = 2;
5176         int ss;
5177         u32 sig1[ss_max], sig2[ss_max];
5178
5179         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5180         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5181         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5182         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5183
5184         for (ss = 0; ss < ss_max; ss++) {
5185                 unsigned int eu_cnt;
5186
5187                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5188                         /* skip disabled subslice */
5189                         continue;
5190
5191                 stat->slice_total = 1;
5192                 stat->subslice_per_slice++;
5193                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5194                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5195                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5196                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5197                 stat->eu_total += eu_cnt;
5198                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5199         }
5200         stat->subslice_total = stat->subslice_per_slice;
5201 }
5202
5203 static void gen9_sseu_device_status(struct drm_device *dev,
5204                                     struct sseu_dev_status *stat)
5205 {
5206         struct drm_i915_private *dev_priv = dev->dev_private;
5207         int s_max = 3, ss_max = 4;
5208         int s, ss;
5209         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5210
5211         /* BXT has a single slice and at most 3 subslices. */
5212         if (IS_BROXTON(dev)) {
5213                 s_max = 1;
5214                 ss_max = 3;
5215         }
5216
5217         for (s = 0; s < s_max; s++) {
5218                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5219                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5220                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5221         }
5222
5223         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5224                      GEN9_PGCTL_SSA_EU19_ACK |
5225                      GEN9_PGCTL_SSA_EU210_ACK |
5226                      GEN9_PGCTL_SSA_EU311_ACK;
5227         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5228                      GEN9_PGCTL_SSB_EU19_ACK |
5229                      GEN9_PGCTL_SSB_EU210_ACK |
5230                      GEN9_PGCTL_SSB_EU311_ACK;
5231
5232         for (s = 0; s < s_max; s++) {
5233                 unsigned int ss_cnt = 0;
5234
5235                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5236                         /* skip disabled slice */
5237                         continue;
5238
5239                 stat->slice_total++;
5240
5241                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5242                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5243
5244                 for (ss = 0; ss < ss_max; ss++) {
5245                         unsigned int eu_cnt;
5246
5247                         if (IS_BROXTON(dev) &&
5248                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5249                                 /* skip disabled subslice */
5250                                 continue;
5251
5252                         if (IS_BROXTON(dev))
5253                                 ss_cnt++;
5254
5255                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5256                                                eu_mask[ss%2]);
5257                         stat->eu_total += eu_cnt;
5258                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5259                                                     eu_cnt);
5260                 }
5261
5262                 stat->subslice_total += ss_cnt;
5263                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5264                                                ss_cnt);
5265         }
5266 }
5267
5268 static void broadwell_sseu_device_status(struct drm_device *dev,
5269                                          struct sseu_dev_status *stat)
5270 {
5271         struct drm_i915_private *dev_priv = dev->dev_private;
5272         int s;
5273         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5274
5275         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5276
5277         if (stat->slice_total) {
5278                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5279                 stat->subslice_total = stat->slice_total *
5280                                        stat->subslice_per_slice;
5281                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5282                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5283
5284                 /* subtract fused off EU(s) from enabled slice(s) */
5285                 for (s = 0; s < stat->slice_total; s++) {
5286                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5287
5288                         stat->eu_total -= hweight8(subslice_7eu);
5289                 }
5290         }
5291 }
5292
5293 static int i915_sseu_status(struct seq_file *m, void *unused)
5294 {
5295         struct drm_info_node *node = (struct drm_info_node *) m->private;
5296         struct drm_device *dev = node->minor->dev;
5297         struct sseu_dev_status stat;
5298
5299         if (INTEL_INFO(dev)->gen < 8)
5300                 return -ENODEV;
5301
5302         seq_puts(m, "SSEU Device Info\n");
5303         seq_printf(m, "  Available Slice Total: %u\n",
5304                    INTEL_INFO(dev)->slice_total);
5305         seq_printf(m, "  Available Subslice Total: %u\n",
5306                    INTEL_INFO(dev)->subslice_total);
5307         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5308                    INTEL_INFO(dev)->subslice_per_slice);
5309         seq_printf(m, "  Available EU Total: %u\n",
5310                    INTEL_INFO(dev)->eu_total);
5311         seq_printf(m, "  Available EU Per Subslice: %u\n",
5312                    INTEL_INFO(dev)->eu_per_subslice);
5313         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5314         if (HAS_POOLED_EU(dev))
5315                 seq_printf(m, "  Min EU in pool: %u\n",
5316                            INTEL_INFO(dev)->min_eu_in_pool);
5317         seq_printf(m, "  Has Slice Power Gating: %s\n",
5318                    yesno(INTEL_INFO(dev)->has_slice_pg));
5319         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5320                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5321         seq_printf(m, "  Has EU Power Gating: %s\n",
5322                    yesno(INTEL_INFO(dev)->has_eu_pg));
5323
5324         seq_puts(m, "SSEU Device Status\n");
5325         memset(&stat, 0, sizeof(stat));
5326         if (IS_CHERRYVIEW(dev)) {
5327                 cherryview_sseu_device_status(dev, &stat);
5328         } else if (IS_BROADWELL(dev)) {
5329                 broadwell_sseu_device_status(dev, &stat);
5330         } else if (INTEL_INFO(dev)->gen >= 9) {
5331                 gen9_sseu_device_status(dev, &stat);
5332         }
5333         seq_printf(m, "  Enabled Slice Total: %u\n",
5334                    stat.slice_total);
5335         seq_printf(m, "  Enabled Subslice Total: %u\n",
5336                    stat.subslice_total);
5337         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5338                    stat.subslice_per_slice);
5339         seq_printf(m, "  Enabled EU Total: %u\n",
5340                    stat.eu_total);
5341         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5342                    stat.eu_per_subslice);
5343
5344         return 0;
5345 }
5346
5347 static int i915_forcewake_open(struct inode *inode, struct file *file)
5348 {
5349         struct drm_device *dev = inode->i_private;
5350         struct drm_i915_private *dev_priv = dev->dev_private;
5351
5352         if (INTEL_INFO(dev)->gen < 6)
5353                 return 0;
5354
5355         intel_runtime_pm_get(dev_priv);
5356         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5357
5358         return 0;
5359 }
5360
5361 static int i915_forcewake_release(struct inode *inode, struct file *file)
5362 {
5363         struct drm_device *dev = inode->i_private;
5364         struct drm_i915_private *dev_priv = dev->dev_private;
5365
5366         if (INTEL_INFO(dev)->gen < 6)
5367                 return 0;
5368
5369         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5370         intel_runtime_pm_put(dev_priv);
5371
5372         return 0;
5373 }
5374
5375 static const struct file_operations i915_forcewake_fops = {
5376         .owner = THIS_MODULE,
5377         .open = i915_forcewake_open,
5378         .release = i915_forcewake_release,
5379 };
5380
5381 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5382 {
5383         struct drm_device *dev = minor->dev;
5384         struct dentry *ent;
5385
5386         ent = debugfs_create_file("i915_forcewake_user",
5387                                   S_IRUSR,
5388                                   root, dev,
5389                                   &i915_forcewake_fops);
5390         if (!ent)
5391                 return -ENOMEM;
5392
5393         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5394 }
5395
5396 static int i915_debugfs_create(struct dentry *root,
5397                                struct drm_minor *minor,
5398                                const char *name,
5399                                const struct file_operations *fops)
5400 {
5401         struct drm_device *dev = minor->dev;
5402         struct dentry *ent;
5403
5404         ent = debugfs_create_file(name,
5405                                   S_IRUGO | S_IWUSR,
5406                                   root, dev,
5407                                   fops);
5408         if (!ent)
5409                 return -ENOMEM;
5410
5411         return drm_add_fake_info_node(minor, ent, fops);
5412 }
5413
5414 static const struct drm_info_list i915_debugfs_list[] = {
5415         {"i915_capabilities", i915_capabilities, 0},
5416         {"i915_gem_objects", i915_gem_object_info, 0},
5417         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5418         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5419         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5420         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5421         {"i915_gem_stolen", i915_gem_stolen_list_info },
5422         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5423         {"i915_gem_request", i915_gem_request_info, 0},
5424         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5425         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5426         {"i915_gem_interrupt", i915_interrupt_info, 0},
5427         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5428         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5429         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5430         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5431         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5432         {"i915_guc_info", i915_guc_info, 0},
5433         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5434         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5435         {"i915_frequency_info", i915_frequency_info, 0},
5436         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5437         {"i915_drpc_info", i915_drpc_info, 0},
5438         {"i915_emon_status", i915_emon_status, 0},
5439         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5440         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5441         {"i915_fbc_status", i915_fbc_status, 0},
5442         {"i915_ips_status", i915_ips_status, 0},
5443         {"i915_sr_status", i915_sr_status, 0},
5444         {"i915_opregion", i915_opregion, 0},
5445         {"i915_vbt", i915_vbt, 0},
5446         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5447         {"i915_context_status", i915_context_status, 0},
5448         {"i915_dump_lrc", i915_dump_lrc, 0},
5449         {"i915_execlists", i915_execlists, 0},
5450         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5451         {"i915_swizzle_info", i915_swizzle_info, 0},
5452         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5453         {"i915_llc", i915_llc, 0},
5454         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5455         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5456         {"i915_energy_uJ", i915_energy_uJ, 0},
5457         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5458         {"i915_power_domain_info", i915_power_domain_info, 0},
5459         {"i915_dmc_info", i915_dmc_info, 0},
5460         {"i915_display_info", i915_display_info, 0},
5461         {"i915_semaphore_status", i915_semaphore_status, 0},
5462         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5463         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5464         {"i915_wa_registers", i915_wa_registers, 0},
5465         {"i915_ddb_info", i915_ddb_info, 0},
5466         {"i915_sseu_status", i915_sseu_status, 0},
5467         {"i915_drrs_status", i915_drrs_status, 0},
5468         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5469 };
5470 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5471
5472 static const struct i915_debugfs_files {
5473         const char *name;
5474         const struct file_operations *fops;
5475 } i915_debugfs_files[] = {
5476         {"i915_wedged", &i915_wedged_fops},
5477         {"i915_max_freq", &i915_max_freq_fops},
5478         {"i915_min_freq", &i915_min_freq_fops},
5479         {"i915_cache_sharing", &i915_cache_sharing_fops},
5480         {"i915_ring_stop", &i915_ring_stop_fops},
5481         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5482         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5483         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5484         {"i915_error_state", &i915_error_state_fops},
5485         {"i915_next_seqno", &i915_next_seqno_fops},
5486         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5487         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5488         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5489         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5490         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5491         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5492         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5493         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5494 };
5495
5496 void intel_display_crc_init(struct drm_device *dev)
5497 {
5498         struct drm_i915_private *dev_priv = dev->dev_private;
5499         enum pipe pipe;
5500
5501         for_each_pipe(dev_priv, pipe) {
5502                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5503
5504                 pipe_crc->opened = false;
5505                 spin_lock_init(&pipe_crc->lock);
5506                 init_waitqueue_head(&pipe_crc->wq);
5507         }
5508 }
5509
5510 int i915_debugfs_init(struct drm_minor *minor)
5511 {
5512         int ret, i;
5513
5514         ret = i915_forcewake_create(minor->debugfs_root, minor);
5515         if (ret)
5516                 return ret;
5517
5518         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5519                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5520                 if (ret)
5521                         return ret;
5522         }
5523
5524         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5525                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5526                                           i915_debugfs_files[i].name,
5527                                           i915_debugfs_files[i].fops);
5528                 if (ret)
5529                         return ret;
5530         }
5531
5532         return drm_debugfs_create_files(i915_debugfs_list,
5533                                         I915_DEBUGFS_ENTRIES,
5534                                         minor->debugfs_root, minor);
5535 }
5536
5537 void i915_debugfs_cleanup(struct drm_minor *minor)
5538 {
5539         int i;
5540
5541         drm_debugfs_remove_files(i915_debugfs_list,
5542                                  I915_DEBUGFS_ENTRIES, minor);
5543
5544         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5545                                  1, minor);
5546
5547         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5548                 struct drm_info_list *info_list =
5549                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5550
5551                 drm_debugfs_remove_files(info_list, 1, minor);
5552         }
5553
5554         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5555                 struct drm_info_list *info_list =
5556                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5557
5558                 drm_debugfs_remove_files(info_list, 1, minor);
5559         }
5560 }
5561
5562 struct dpcd_block {
5563         /* DPCD dump start address. */
5564         unsigned int offset;
5565         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5566         unsigned int end;
5567         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5568         size_t size;
5569         /* Only valid for eDP. */
5570         bool edp;
5571 };
5572
5573 static const struct dpcd_block i915_dpcd_debug[] = {
5574         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5575         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5576         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5577         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5578         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5579         { .offset = DP_SET_POWER },
5580         { .offset = DP_EDP_DPCD_REV },
5581         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5582         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5583         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5584 };
5585
5586 static int i915_dpcd_show(struct seq_file *m, void *data)
5587 {
5588         struct drm_connector *connector = m->private;
5589         struct intel_dp *intel_dp =
5590                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5591         uint8_t buf[16];
5592         ssize_t err;
5593         int i;
5594
5595         if (connector->status != connector_status_connected)
5596                 return -ENODEV;
5597
5598         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5599                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5600                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5601
5602                 if (b->edp &&
5603                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5604                         continue;
5605
5606                 /* low tech for now */
5607                 if (WARN_ON(size > sizeof(buf)))
5608                         continue;
5609
5610                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5611                 if (err <= 0) {
5612                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5613                                   size, b->offset, err);
5614                         continue;
5615                 }
5616
5617                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5618         }
5619
5620         return 0;
5621 }
5622
5623 static int i915_dpcd_open(struct inode *inode, struct file *file)
5624 {
5625         return single_open(file, i915_dpcd_show, inode->i_private);
5626 }
5627
5628 static const struct file_operations i915_dpcd_fops = {
5629         .owner = THIS_MODULE,
5630         .open = i915_dpcd_open,
5631         .read = seq_read,
5632         .llseek = seq_lseek,
5633         .release = single_release,
5634 };
5635
5636 /**
5637  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5638  * @connector: pointer to a registered drm_connector
5639  *
5640  * Cleanup will be done by drm_connector_unregister() through a call to
5641  * drm_debugfs_connector_remove().
5642  *
5643  * Returns 0 on success, negative error codes on error.
5644  */
5645 int i915_debugfs_connector_add(struct drm_connector *connector)
5646 {
5647         struct dentry *root = connector->debugfs_entry;
5648
5649         /* The connector must have been registered beforehands. */
5650         if (!root)
5651                 return -ENODEV;
5652
5653         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5654             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5655                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5656                                     &i915_dpcd_fops);
5657
5658         return 0;
5659 }