drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->pin_display)
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static void
 121 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 122 {
 123         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 124         struct intel_engine_cs *ring;
 125         struct i915_vma *vma;
 126         int pin_count = 0;
 127         int i;
 128
 129         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 130                    &obj->base,
 131                    obj->active ? "*" : " ",
 132                    get_pin_flag(obj),
 133                    get_tiling_flag(obj),
 134                    get_global_flag(obj),
 135                    obj->base.size / 1024,
 136                    obj->base.read_domains,
 137                    obj->base.write_domain);
 138         for_each_ring(ring, dev_priv, i)
 139                 seq_printf(m, "%x ",
 140                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 141         seq_printf(m, "] %x %x%s%s%s",
 142                    i915_gem_request_get_seqno(obj->last_write_req),
 143                    i915_gem_request_get_seqno(obj->last_fenced_req),
 144                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 145                    obj->dirty ? " dirty" : "",
 146                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 147         if (obj->base.name)
 148                 seq_printf(m, " (name: %d)", obj->base.name);
 149         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 150                 if (vma->pin_count > 0)
 151                         pin_count++;
 152         }
 153         seq_printf(m, " (pinned x %d)", pin_count);
 154         if (obj->pin_display)
 155                 seq_printf(m, " (display)");
 156         if (obj->fence_reg != I915_FENCE_REG_NONE)
 157                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (!i915_is_ggtt(vma->vm))
 160                         seq_puts(m, " (pp");
 161                 else
 162                         seq_puts(m, " (g");
 163                 seq_printf(m, "gtt offset: %08llx, size: %08llx, type: %u)",
 164                            vma->node.start, vma->node.size,
 165                            vma->ggtt_view.type);
 166         }
 167         if (obj->stolen)
 168                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 169         if (obj->pin_display || obj->fault_mappable) {
 170                 char s[3], *t = s;
 171                 if (obj->pin_display)
 172                         *t++ = 'p';
 173                 if (obj->fault_mappable)
 174                         *t++ = 'f';
 175                 *t = '\0';
 176                 seq_printf(m, " (%s mappable)", s);
 177         }
 178         if (obj->last_write_req != NULL)
 179                 seq_printf(m, " (%s)",
 180                            i915_gem_request_get_ring(obj->last_write_req)->name);
 181         if (obj->frontbuffer_bits)
 182                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 183 }
 184
 185 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 186 {
 187         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 188         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 189         seq_putc(m, ' ');
 190 }
 191
 192 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 193 {
 194         struct drm_info_node *node = m->private;
 195         uintptr_t list = (uintptr_t) node->info_ent->data;
 196         struct list_head *head;
 197         struct drm_device *dev = node->minor->dev;
 198         struct drm_i915_private *dev_priv = dev->dev_private;
 199         struct i915_address_space *vm = &dev_priv->gtt.base;
 200         struct i915_vma *vma;
 201         size_t total_obj_size, total_gtt_size;
 202         int count, ret;
 203
 204         ret = mutex_lock_interruptible(&dev->struct_mutex);
 205         if (ret)
 206                 return ret;
 207
 208         /* FIXME: the user of this interface might want more than just GGTT */
 209         switch (list) {
 210         case ACTIVE_LIST:
 211                 seq_puts(m, "Active:\n");
 212                 head = &vm->active_list;
 213                 break;
 214         case INACTIVE_LIST:
 215                 seq_puts(m, "Inactive:\n");
 216                 head = &vm->inactive_list;
 217                 break;
 218         default:
 219                 mutex_unlock(&dev->struct_mutex);
 220                 return -EINVAL;
 221         }
 222
 223         total_obj_size = total_gtt_size = count = 0;
 224         list_for_each_entry(vma, head, mm_list) {
 225                 seq_printf(m, "   ");
 226                 describe_obj(m, vma->obj);
 227                 seq_printf(m, "\n");
 228                 total_obj_size += vma->obj->base.size;
 229                 total_gtt_size += vma->node.size;
 230                 count++;
 231         }
 232         mutex_unlock(&dev->struct_mutex);
 233
 234         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 235                    count, total_obj_size, total_gtt_size);
 236         return 0;
 237 }
 238
 239 static int obj_rank_by_stolen(void *priv,
 240                               struct list_head *A, struct list_head *B)
 241 {
 242         struct drm_i915_gem_object *a =
 243                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 244         struct drm_i915_gem_object *b =
 245                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 246
 247         return a->stolen->start - b->stolen->start;
 248 }
 249
 250 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 251 {
 252         struct drm_info_node *node = m->private;
 253         struct drm_device *dev = node->minor->dev;
 254         struct drm_i915_private *dev_priv = dev->dev_private;
 255         struct drm_i915_gem_object *obj;
 256         size_t total_obj_size, total_gtt_size;
 257         LIST_HEAD(stolen);
 258         int count, ret;
 259
 260         ret = mutex_lock_interruptible(&dev->struct_mutex);
 261         if (ret)
 262                 return ret;
 263
 264         total_obj_size = total_gtt_size = count = 0;
 265         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 266                 if (obj->stolen == NULL)
 267                         continue;
 268
 269                 list_add(&obj->obj_exec_link, &stolen);
 270
 271                 total_obj_size += obj->base.size;
 272                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 273                 count++;
 274         }
 275         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 276                 if (obj->stolen == NULL)
 277                         continue;
 278
 279                 list_add(&obj->obj_exec_link, &stolen);
 280
 281                 total_obj_size += obj->base.size;
 282                 count++;
 283         }
 284         list_sort(NULL, &stolen, obj_rank_by_stolen);
 285         seq_puts(m, "Stolen:\n");
 286         while (!list_empty(&stolen)) {
 287                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 288                 seq_puts(m, "   ");
 289                 describe_obj(m, obj);
 290                 seq_putc(m, '\n');
 291                 list_del_init(&obj->obj_exec_link);
 292         }
 293         mutex_unlock(&dev->struct_mutex);
 294
 295         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 296                    count, total_obj_size, total_gtt_size);
 297         return 0;
 298 }
 299
 300 #define count_objects(list, member) do { \
 301         list_for_each_entry(obj, list, member) { \
 302                 size += i915_gem_obj_ggtt_size(obj); \
 303                 ++count; \
 304                 if (obj->map_and_fenceable) { \
 305                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 306                         ++mappable_count; \
 307                 } \
 308         } \
 309 } while (0)
 310
 311 struct file_stats {
 312         struct drm_i915_file_private *file_priv;
 313         int count;
 314         size_t total, unbound;
 315         size_t global, shared;
 316         size_t active, inactive;
 317 };
 318
 319 static int per_file_stats(int id, void *ptr, void *data)
 320 {
 321         struct drm_i915_gem_object *obj = ptr;
 322         struct file_stats *stats = data;
 323         struct i915_vma *vma;
 324
 325         stats->count++;
 326         stats->total += obj->base.size;
 327
 328         if (obj->base.name || obj->base.dma_buf)
 329                 stats->shared += obj->base.size;
 330
 331         if (USES_FULL_PPGTT(obj->base.dev)) {
 332                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 333                         struct i915_hw_ppgtt *ppgtt;
 334
 335                         if (!drm_mm_node_allocated(&vma->node))
 336                                 continue;
 337
 338                         if (i915_is_ggtt(vma->vm)) {
 339                                 stats->global += obj->base.size;
 340                                 continue;
 341                         }
 342
 343                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 344                         if (ppgtt->file_priv != stats->file_priv)
 345                                 continue;
 346
 347                         if (obj->active) /* XXX per-vma statistic */
 348                                 stats->active += obj->base.size;
 349                         else
 350                                 stats->inactive += obj->base.size;
 351
 352                         return 0;
 353                 }
 354         } else {
 355                 if (i915_gem_obj_ggtt_bound(obj)) {
 356                         stats->global += obj->base.size;
 357                         if (obj->active)
 358                                 stats->active += obj->base.size;
 359                         else
 360                                 stats->inactive += obj->base.size;
 361                         return 0;
 362                 }
 363         }
 364
 365         if (!list_empty(&obj->global_list))
 366                 stats->unbound += obj->base.size;
 367
 368         return 0;
 369 }
 370
 371 #define print_file_stats(m, name, stats) do { \
 372         if (stats.count) \
 373                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound)\n", \
 374                            name, \
 375                            stats.count, \
 376                            stats.total, \
 377                            stats.active, \
 378                            stats.inactive, \
 379                            stats.global, \
 380                            stats.shared, \
 381                            stats.unbound); \
 382 } while (0)
 383
 384 static void print_batch_pool_stats(struct seq_file *m,
 385                                    struct drm_i915_private *dev_priv)
 386 {
 387         struct drm_i915_gem_object *obj;
 388         struct file_stats stats;
 389         struct intel_engine_cs *ring;
 390         int i, j;
 391
 392         memset(&stats, 0, sizeof(stats));
 393
 394         for_each_ring(ring, dev_priv, i) {
 395                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 396                         list_for_each_entry(obj,
 397                                             &ring->batch_pool.cache_list[j],
 398                                             batch_pool_link)
 399                                 per_file_stats(0, obj, &stats);
 400                 }
 401         }
 402
 403         print_file_stats(m, "[k]batch pool", stats);
 404 }
 405
 406 #define count_vmas(list, member) do { \
 407         list_for_each_entry(vma, list, member) { \
 408                 size += i915_gem_obj_ggtt_size(vma->obj); \
 409                 ++count; \
 410                 if (vma->obj->map_and_fenceable) { \
 411                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 412                         ++mappable_count; \
 413                 } \
 414         } \
 415 } while (0)
 416
 417 static int i915_gem_object_info(struct seq_file *m, void* data)
 418 {
 419         struct drm_info_node *node = m->private;
 420         struct drm_device *dev = node->minor->dev;
 421         struct drm_i915_private *dev_priv = dev->dev_private;
 422         u32 count, mappable_count, purgeable_count;
 423         size_t size, mappable_size, purgeable_size;
 424         struct drm_i915_gem_object *obj;
 425         struct i915_address_space *vm = &dev_priv->gtt.base;
 426         struct drm_file *file;
 427         struct i915_vma *vma;
 428         int ret;
 429
 430         ret = mutex_lock_interruptible(&dev->struct_mutex);
 431         if (ret)
 432                 return ret;
 433
 434         seq_printf(m, "%u objects, %zu bytes\n",
 435                    dev_priv->mm.object_count,
 436                    dev_priv->mm.object_memory);
 437
 438         size = count = mappable_size = mappable_count = 0;
 439         count_objects(&dev_priv->mm.bound_list, global_list);
 440         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 441                    count, mappable_count, size, mappable_size);
 442
 443         size = count = mappable_size = mappable_count = 0;
 444         count_vmas(&vm->active_list, mm_list);
 445         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 446                    count, mappable_count, size, mappable_size);
 447
 448         size = count = mappable_size = mappable_count = 0;
 449         count_vmas(&vm->inactive_list, mm_list);
 450         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 451                    count, mappable_count, size, mappable_size);
 452
 453         size = count = purgeable_size = purgeable_count = 0;
 454         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 455                 size += obj->base.size, ++count;
 456                 if (obj->madv == I915_MADV_DONTNEED)
 457                         purgeable_size += obj->base.size, ++purgeable_count;
 458         }
 459         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 460
 461         size = count = mappable_size = mappable_count = 0;
 462         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 463                 if (obj->fault_mappable) {
 464                         size += i915_gem_obj_ggtt_size(obj);
 465                         ++count;
 466                 }
 467                 if (obj->pin_display) {
 468                         mappable_size += i915_gem_obj_ggtt_size(obj);
 469                         ++mappable_count;
 470                 }
 471                 if (obj->madv == I915_MADV_DONTNEED) {
 472                         purgeable_size += obj->base.size;
 473                         ++purgeable_count;
 474                 }
 475         }
 476         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 477                    purgeable_count, purgeable_size);
 478         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 479                    mappable_count, mappable_size);
 480         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 481                    count, size);
 482
 483         seq_printf(m, "%zu [%lu] gtt total\n",
 484                    dev_priv->gtt.base.total,
 485                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 486
 487         seq_putc(m, '\n');
 488         print_batch_pool_stats(m, dev_priv);
 489         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 490                 struct file_stats stats;
 491                 struct task_struct *task;
 492
 493                 memset(&stats, 0, sizeof(stats));
 494                 stats.file_priv = file->driver_priv;
 495                 spin_lock(&file->table_lock);
 496                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 497                 spin_unlock(&file->table_lock);
 498                 /*
 499                  * Although we have a valid reference on file->pid, that does
 500                  * not guarantee that the task_struct who called get_pid() is
 501                  * still alive (e.g. get_pid(current) => fork() => exit()).
 502                  * Therefore, we need to protect this ->comm access using RCU.
 503                  */
 504                 rcu_read_lock();
 505                 task = pid_task(file->pid, PIDTYPE_PID);
 506                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 507                 rcu_read_unlock();
 508         }
 509
 510         mutex_unlock(&dev->struct_mutex);
 511
 512         return 0;
 513 }
 514
 515 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 516 {
 517         struct drm_info_node *node = m->private;
 518         struct drm_device *dev = node->minor->dev;
 519         uintptr_t list = (uintptr_t) node->info_ent->data;
 520         struct drm_i915_private *dev_priv = dev->dev_private;
 521         struct drm_i915_gem_object *obj;
 522         size_t total_obj_size, total_gtt_size;
 523         int count, ret;
 524
 525         ret = mutex_lock_interruptible(&dev->struct_mutex);
 526         if (ret)
 527                 return ret;
 528
 529         total_obj_size = total_gtt_size = count = 0;
 530         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 531                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 532                         continue;
 533
 534                 seq_puts(m, "   ");
 535                 describe_obj(m, obj);
 536                 seq_putc(m, '\n');
 537                 total_obj_size += obj->base.size;
 538                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 539                 count++;
 540         }
 541
 542         mutex_unlock(&dev->struct_mutex);
 543
 544         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 545                    count, total_obj_size, total_gtt_size);
 546
 547         return 0;
 548 }
 549
 550 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 551 {
 552         struct drm_info_node *node = m->private;
 553         struct drm_device *dev = node->minor->dev;
 554         struct drm_i915_private *dev_priv = dev->dev_private;
 555         struct intel_crtc *crtc;
 556         int ret;
 557
 558         ret = mutex_lock_interruptible(&dev->struct_mutex);
 559         if (ret)
 560                 return ret;
 561
 562         for_each_intel_crtc(dev, crtc) {
 563                 const char pipe = pipe_name(crtc->pipe);
 564                 const char plane = plane_name(crtc->plane);
 565                 struct intel_unpin_work *work;
 566
 567                 spin_lock_irq(&dev->event_lock);
 568                 work = crtc->unpin_work;
 569                 if (work == NULL) {
 570                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 571                                    pipe, plane);
 572                 } else {
 573                         u32 addr;
 574
 575                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 576                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 577                                            pipe, plane);
 578                         } else {
 579                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 580                                            pipe, plane);
 581                         }
 582                         if (work->flip_queued_req) {
 583                                 struct intel_engine_cs *ring =
 584                                         i915_gem_request_get_ring(work->flip_queued_req);
 585
 586                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 587                                            ring->name,
 588                                            i915_gem_request_get_seqno(work->flip_queued_req),
 589                                            dev_priv->next_seqno,
 590                                            ring->get_seqno(ring, true),
 591                                            i915_gem_request_completed(work->flip_queued_req, true));
 592                         } else
 593                                 seq_printf(m, "Flip not associated with any ring\n");
 594                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 595                                    work->flip_queued_vblank,
 596                                    work->flip_ready_vblank,
 597                                    drm_crtc_vblank_count(&crtc->base));
 598                         if (work->enable_stall_check)
 599                                 seq_puts(m, "Stall check enabled, ");
 600                         else
 601                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 602                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 603
 604                         if (INTEL_INFO(dev)->gen >= 4)
 605                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 606                         else
 607                                 addr = I915_READ(DSPADDR(crtc->plane));
 608                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 609
 610                         if (work->pending_flip_obj) {
 611                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 612                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 613                         }
 614                 }
 615                 spin_unlock_irq(&dev->event_lock);
 616         }
 617
 618         mutex_unlock(&dev->struct_mutex);
 619
 620         return 0;
 621 }
 622
 623 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 624 {
 625         struct drm_info_node *node = m->private;
 626         struct drm_device *dev = node->minor->dev;
 627         struct drm_i915_private *dev_priv = dev->dev_private;
 628         struct drm_i915_gem_object *obj;
 629         struct intel_engine_cs *ring;
 630         int total = 0;
 631         int ret, i, j;
 632
 633         ret = mutex_lock_interruptible(&dev->struct_mutex);
 634         if (ret)
 635                 return ret;
 636
 637         for_each_ring(ring, dev_priv, i) {
 638                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 639                         int count;
 640
 641                         count = 0;
 642                         list_for_each_entry(obj,
 643                                             &ring->batch_pool.cache_list[j],
 644                                             batch_pool_link)
 645                                 count++;
 646                         seq_printf(m, "%s cache[%d]: %d objects\n",
 647                                    ring->name, j, count);
 648
 649                         list_for_each_entry(obj,
 650                                             &ring->batch_pool.cache_list[j],
 651                                             batch_pool_link) {
 652                                 seq_puts(m, "   ");
 653                                 describe_obj(m, obj);
 654                                 seq_putc(m, '\n');
 655                         }
 656
 657                         total += count;
 658                 }
 659         }
 660
 661         seq_printf(m, "total: %d\n", total);
 662
 663         mutex_unlock(&dev->struct_mutex);
 664
 665         return 0;
 666 }
 667
 668 static int i915_gem_request_info(struct seq_file *m, void *data)
 669 {
 670         struct drm_info_node *node = m->private;
 671         struct drm_device *dev = node->minor->dev;
 672         struct drm_i915_private *dev_priv = dev->dev_private;
 673         struct intel_engine_cs *ring;
 674         struct drm_i915_gem_request *req;
 675         int ret, any, i;
 676
 677         ret = mutex_lock_interruptible(&dev->struct_mutex);
 678         if (ret)
 679                 return ret;
 680
 681         any = 0;
 682         for_each_ring(ring, dev_priv, i) {
 683                 int count;
 684
 685                 count = 0;
 686                 list_for_each_entry(req, &ring->request_list, list)
 687                         count++;
 688                 if (count == 0)
 689                         continue;
 690
 691                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 692                 list_for_each_entry(req, &ring->request_list, list) {
 693                         struct task_struct *task;
 694
 695                         rcu_read_lock();
 696                         task = NULL;
 697                         if (req->pid)
 698                                 task = pid_task(req->pid, PIDTYPE_PID);
 699                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 700                                    req->seqno,
 701                                    (int) (jiffies - req->emitted_jiffies),
 702                                    task ? task->comm : "<unknown>",
 703                                    task ? task->pid : -1);
 704                         rcu_read_unlock();
 705                 }
 706
 707                 any++;
 708         }
 709         mutex_unlock(&dev->struct_mutex);
 710
 711         if (any == 0)
 712                 seq_puts(m, "No requests\n");
 713
 714         return 0;
 715 }
 716
 717 static void i915_ring_seqno_info(struct seq_file *m,
 718                                  struct intel_engine_cs *ring)
 719 {
 720         if (ring->get_seqno) {
 721                 seq_printf(m, "Current sequence (%s): %x\n",
 722                            ring->name, ring->get_seqno(ring, false));
 723         }
 724 }
 725
 726 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 727 {
 728         struct drm_info_node *node = m->private;
 729         struct drm_device *dev = node->minor->dev;
 730         struct drm_i915_private *dev_priv = dev->dev_private;
 731         struct intel_engine_cs *ring;
 732         int ret, i;
 733
 734         ret = mutex_lock_interruptible(&dev->struct_mutex);
 735         if (ret)
 736                 return ret;
 737         intel_runtime_pm_get(dev_priv);
 738
 739         for_each_ring(ring, dev_priv, i)
 740                 i915_ring_seqno_info(m, ring);
 741
 742         intel_runtime_pm_put(dev_priv);
 743         mutex_unlock(&dev->struct_mutex);
 744
 745         return 0;
 746 }
 747
 748
 749 static int i915_interrupt_info(struct seq_file *m, void *data)
 750 {
 751         struct drm_info_node *node = m->private;
 752         struct drm_device *dev = node->minor->dev;
 753         struct drm_i915_private *dev_priv = dev->dev_private;
 754         struct intel_engine_cs *ring;
 755         int ret, i, pipe;
 756
 757         ret = mutex_lock_interruptible(&dev->struct_mutex);
 758         if (ret)
 759                 return ret;
 760         intel_runtime_pm_get(dev_priv);
 761
 762         if (IS_CHERRYVIEW(dev)) {
 763                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 764                            I915_READ(GEN8_MASTER_IRQ));
 765
 766                 seq_printf(m, "Display IER:\t%08x\n",
 767                            I915_READ(VLV_IER));
 768                 seq_printf(m, "Display IIR:\t%08x\n",
 769                            I915_READ(VLV_IIR));
 770                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 771                            I915_READ(VLV_IIR_RW));
 772                 seq_printf(m, "Display IMR:\t%08x\n",
 773                            I915_READ(VLV_IMR));
 774                 for_each_pipe(dev_priv, pipe)
 775                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 776                                    pipe_name(pipe),
 777                                    I915_READ(PIPESTAT(pipe)));
 778
 779                 seq_printf(m, "Port hotplug:\t%08x\n",
 780                            I915_READ(PORT_HOTPLUG_EN));
 781                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 782                            I915_READ(VLV_DPFLIPSTAT));
 783                 seq_printf(m, "DPINVGTT:\t%08x\n",
 784                            I915_READ(DPINVGTT));
 785
 786                 for (i = 0; i < 4; i++) {
 787                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 788                                    i, I915_READ(GEN8_GT_IMR(i)));
 789                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 790                                    i, I915_READ(GEN8_GT_IIR(i)));
 791                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 792                                    i, I915_READ(GEN8_GT_IER(i)));
 793                 }
 794
 795                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 796                            I915_READ(GEN8_PCU_IMR));
 797                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 798                            I915_READ(GEN8_PCU_IIR));
 799                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 800                            I915_READ(GEN8_PCU_IER));
 801         } else if (INTEL_INFO(dev)->gen >= 8) {
 802                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 803                            I915_READ(GEN8_MASTER_IRQ));
 804
 805                 for (i = 0; i < 4; i++) {
 806                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 807                                    i, I915_READ(GEN8_GT_IMR(i)));
 808                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 809                                    i, I915_READ(GEN8_GT_IIR(i)));
 810                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 811                                    i, I915_READ(GEN8_GT_IER(i)));
 812                 }
 813
 814                 for_each_pipe(dev_priv, pipe) {
 815                         if (!intel_display_power_is_enabled(dev_priv,
 816                                                 POWER_DOMAIN_PIPE(pipe))) {
 817                                 seq_printf(m, "Pipe %c power disabled\n",
 818                                            pipe_name(pipe));
 819                                 continue;
 820                         }
 821                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 822                                    pipe_name(pipe),
 823                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 824                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 825                                    pipe_name(pipe),
 826                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 827                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 828                                    pipe_name(pipe),
 829                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 830                 }
 831
 832                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 833                            I915_READ(GEN8_DE_PORT_IMR));
 834                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 835                            I915_READ(GEN8_DE_PORT_IIR));
 836                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 837                            I915_READ(GEN8_DE_PORT_IER));
 838
 839                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 840                            I915_READ(GEN8_DE_MISC_IMR));
 841                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 842                            I915_READ(GEN8_DE_MISC_IIR));
 843                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 844                            I915_READ(GEN8_DE_MISC_IER));
 845
 846                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 847                            I915_READ(GEN8_PCU_IMR));
 848                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 849                            I915_READ(GEN8_PCU_IIR));
 850                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 851                            I915_READ(GEN8_PCU_IER));
 852         } else if (IS_VALLEYVIEW(dev)) {
 853                 seq_printf(m, "Display IER:\t%08x\n",
 854                            I915_READ(VLV_IER));
 855                 seq_printf(m, "Display IIR:\t%08x\n",
 856                            I915_READ(VLV_IIR));
 857                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 858                            I915_READ(VLV_IIR_RW));
 859                 seq_printf(m, "Display IMR:\t%08x\n",
 860                            I915_READ(VLV_IMR));
 861                 for_each_pipe(dev_priv, pipe)
 862                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 863                                    pipe_name(pipe),
 864                                    I915_READ(PIPESTAT(pipe)));
 865
 866                 seq_printf(m, "Master IER:\t%08x\n",
 867                            I915_READ(VLV_MASTER_IER));
 868
 869                 seq_printf(m, "Render IER:\t%08x\n",
 870                            I915_READ(GTIER));
 871                 seq_printf(m, "Render IIR:\t%08x\n",
 872                            I915_READ(GTIIR));
 873                 seq_printf(m, "Render IMR:\t%08x\n",
 874                            I915_READ(GTIMR));
 875
 876                 seq_printf(m, "PM IER:\t\t%08x\n",
 877                            I915_READ(GEN6_PMIER));
 878                 seq_printf(m, "PM IIR:\t\t%08x\n",
 879                            I915_READ(GEN6_PMIIR));
 880                 seq_printf(m, "PM IMR:\t\t%08x\n",
 881                            I915_READ(GEN6_PMIMR));
 882
 883                 seq_printf(m, "Port hotplug:\t%08x\n",
 884                            I915_READ(PORT_HOTPLUG_EN));
 885                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 886                            I915_READ(VLV_DPFLIPSTAT));
 887                 seq_printf(m, "DPINVGTT:\t%08x\n",
 888                            I915_READ(DPINVGTT));
 889
 890         } else if (!HAS_PCH_SPLIT(dev)) {
 891                 seq_printf(m, "Interrupt enable:    %08x\n",
 892                            I915_READ(IER));
 893                 seq_printf(m, "Interrupt identity:  %08x\n",
 894                            I915_READ(IIR));
 895                 seq_printf(m, "Interrupt mask:      %08x\n",
 896                            I915_READ(IMR));
 897                 for_each_pipe(dev_priv, pipe)
 898                         seq_printf(m, "Pipe %c stat:         %08x\n",
 899                                    pipe_name(pipe),
 900                                    I915_READ(PIPESTAT(pipe)));
 901         } else {
 902                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 903                            I915_READ(DEIER));
 904                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 905                            I915_READ(DEIIR));
 906                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 907                            I915_READ(DEIMR));
 908                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 909                            I915_READ(SDEIER));
 910                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 911                            I915_READ(SDEIIR));
 912                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 913                            I915_READ(SDEIMR));
 914                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 915                            I915_READ(GTIER));
 916                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 917                            I915_READ(GTIIR));
 918                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 919                            I915_READ(GTIMR));
 920         }
 921         for_each_ring(ring, dev_priv, i) {
 922                 if (INTEL_INFO(dev)->gen >= 6) {
 923                         seq_printf(m,
 924                                    "Graphics Interrupt mask (%s):       %08x\n",
 925                                    ring->name, I915_READ_IMR(ring));
 926                 }
 927                 i915_ring_seqno_info(m, ring);
 928         }
 929         intel_runtime_pm_put(dev_priv);
 930         mutex_unlock(&dev->struct_mutex);
 931
 932         return 0;
 933 }
 934
 935 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 936 {
 937         struct drm_info_node *node = m->private;
 938         struct drm_device *dev = node->minor->dev;
 939         struct drm_i915_private *dev_priv = dev->dev_private;
 940         int i, ret;
 941
 942         ret = mutex_lock_interruptible(&dev->struct_mutex);
 943         if (ret)
 944                 return ret;
 945
 946         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 947         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 948         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 949                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 950
 951                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 952                            i, dev_priv->fence_regs[i].pin_count);
 953                 if (obj == NULL)
 954                         seq_puts(m, "unused");
 955                 else
 956                         describe_obj(m, obj);
 957                 seq_putc(m, '\n');
 958         }
 959
 960         mutex_unlock(&dev->struct_mutex);
 961         return 0;
 962 }
 963
 964 static int i915_hws_info(struct seq_file *m, void *data)
 965 {
 966         struct drm_info_node *node = m->private;
 967         struct drm_device *dev = node->minor->dev;
 968         struct drm_i915_private *dev_priv = dev->dev_private;
 969         struct intel_engine_cs *ring;
 970         const u32 *hws;
 971         int i;
 972
 973         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 974         hws = ring->status_page.page_addr;
 975         if (hws == NULL)
 976                 return 0;
 977
 978         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 979                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 980                            i * 4,
 981                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 982         }
 983         return 0;
 984 }
 985
 986 static ssize_t
 987 i915_error_state_write(struct file *filp,
 988                        const char __user *ubuf,
 989                        size_t cnt,
 990                        loff_t *ppos)
 991 {
 992         struct i915_error_state_file_priv *error_priv = filp->private_data;
 993         struct drm_device *dev = error_priv->dev;
 994         int ret;
 995
 996         DRM_DEBUG_DRIVER("Resetting error state\n");
 997
 998         ret = mutex_lock_interruptible(&dev->struct_mutex);
 999         if (ret)
1000                 return ret;
1001
1002         i915_destroy_error_state(dev);
1003         mutex_unlock(&dev->struct_mutex);
1004
1005         return cnt;
1006 }
1007
1008 static int i915_error_state_open(struct inode *inode, struct file *file)
1009 {
1010         struct drm_device *dev = inode->i_private;
1011         struct i915_error_state_file_priv *error_priv;
1012
1013         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1014         if (!error_priv)
1015                 return -ENOMEM;
1016
1017         error_priv->dev = dev;
1018
1019         i915_error_state_get(dev, error_priv);
1020
1021         file->private_data = error_priv;
1022
1023         return 0;
1024 }
1025
1026 static int i915_error_state_release(struct inode *inode, struct file *file)
1027 {
1028         struct i915_error_state_file_priv *error_priv = file->private_data;
1029
1030         i915_error_state_put(error_priv);
1031         kfree(error_priv);
1032
1033         return 0;
1034 }
1035
1036 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1037                                      size_t count, loff_t *pos)
1038 {
1039         struct i915_error_state_file_priv *error_priv = file->private_data;
1040         struct drm_i915_error_state_buf error_str;
1041         loff_t tmp_pos = 0;
1042         ssize_t ret_count = 0;
1043         int ret;
1044
1045         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1046         if (ret)
1047                 return ret;
1048
1049         ret = i915_error_state_to_str(&error_str, error_priv);
1050         if (ret)
1051                 goto out;
1052
1053         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1054                                             error_str.buf,
1055                                             error_str.bytes);
1056
1057         if (ret_count < 0)
1058                 ret = ret_count;
1059         else
1060                 *pos = error_str.start + ret_count;
1061 out:
1062         i915_error_state_buf_release(&error_str);
1063         return ret ?: ret_count;
1064 }
1065
1066 static const struct file_operations i915_error_state_fops = {
1067         .owner = THIS_MODULE,
1068         .open = i915_error_state_open,
1069         .read = i915_error_state_read,
1070         .write = i915_error_state_write,
1071         .llseek = default_llseek,
1072         .release = i915_error_state_release,
1073 };
1074
1075 static int
1076 i915_next_seqno_get(void *data, u64 *val)
1077 {
1078         struct drm_device *dev = data;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         int ret;
1081
1082         ret = mutex_lock_interruptible(&dev->struct_mutex);
1083         if (ret)
1084                 return ret;
1085
1086         *val = dev_priv->next_seqno;
1087         mutex_unlock(&dev->struct_mutex);
1088
1089         return 0;
1090 }
1091
1092 static int
1093 i915_next_seqno_set(void *data, u64 val)
1094 {
1095         struct drm_device *dev = data;
1096         int ret;
1097
1098         ret = mutex_lock_interruptible(&dev->struct_mutex);
1099         if (ret)
1100                 return ret;
1101
1102         ret = i915_gem_set_seqno(dev, val);
1103         mutex_unlock(&dev->struct_mutex);
1104
1105         return ret;
1106 }
1107
1108 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1109                         i915_next_seqno_get, i915_next_seqno_set,
1110                         "0x%llx\n");
1111
1112 static int i915_frequency_info(struct seq_file *m, void *unused)
1113 {
1114         struct drm_info_node *node = m->private;
1115         struct drm_device *dev = node->minor->dev;
1116         struct drm_i915_private *dev_priv = dev->dev_private;
1117         int ret = 0;
1118
1119         intel_runtime_pm_get(dev_priv);
1120
1121         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1122
1123         if (IS_GEN5(dev)) {
1124                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1125                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1126
1127                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1128                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1129                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1130                            MEMSTAT_VID_SHIFT);
1131                 seq_printf(m, "Current P-state: %d\n",
1132                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1133         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1134                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1135                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1136                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1137                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1138                 u32 rpmodectl, rpinclimit, rpdeclimit;
1139                 u32 rpstat, cagf, reqf;
1140                 u32 rpupei, rpcurup, rpprevup;
1141                 u32 rpdownei, rpcurdown, rpprevdown;
1142                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1143                 int max_freq;
1144
1145                 /* RPSTAT1 is in the GT power well */
1146                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1147                 if (ret)
1148                         goto out;
1149
1150                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1151
1152                 reqf = I915_READ(GEN6_RPNSWREQ);
1153                 if (IS_GEN9(dev))
1154                         reqf >>= 23;
1155                 else {
1156                         reqf &= ~GEN6_TURBO_DISABLE;
1157                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1158                                 reqf >>= 24;
1159                         else
1160                                 reqf >>= 25;
1161                 }
1162                 reqf = intel_gpu_freq(dev_priv, reqf);
1163
1164                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1165                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1166                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1167
1168                 rpstat = I915_READ(GEN6_RPSTAT1);
1169                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1170                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1171                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1172                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1173                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1174                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1175                 if (IS_GEN9(dev))
1176                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1177                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1178                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1179                 else
1180                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1181                 cagf = intel_gpu_freq(dev_priv, cagf);
1182
1183                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1184                 mutex_unlock(&dev->struct_mutex);
1185
1186                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1187                         pm_ier = I915_READ(GEN6_PMIER);
1188                         pm_imr = I915_READ(GEN6_PMIMR);
1189                         pm_isr = I915_READ(GEN6_PMISR);
1190                         pm_iir = I915_READ(GEN6_PMIIR);
1191                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1192                 } else {
1193                         pm_ier = I915_READ(GEN8_GT_IER(2));
1194                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1195                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1196                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1197                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1198                 }
1199                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1200                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1201                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1202                 seq_printf(m, "Render p-state ratio: %d\n",
1203                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1204                 seq_printf(m, "Render p-state VID: %d\n",
1205                            gt_perf_status & 0xff);
1206                 seq_printf(m, "Render p-state limit: %d\n",
1207                            rp_state_limits & 0xff);
1208                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1209                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1210                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1211                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1212                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1213                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1214                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1215                            GEN6_CURICONT_MASK);
1216                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1217                            GEN6_CURBSYTAVG_MASK);
1218                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1219                            GEN6_CURBSYTAVG_MASK);
1220                 seq_printf(m, "Up threshold: %d%%\n",
1221                            dev_priv->rps.up_threshold);
1222
1223                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1224                            GEN6_CURIAVG_MASK);
1225                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1226                            GEN6_CURBSYTAVG_MASK);
1227                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1228                            GEN6_CURBSYTAVG_MASK);
1229                 seq_printf(m, "Down threshold: %d%%\n",
1230                            dev_priv->rps.down_threshold);
1231
1232                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1233                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1234                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1235                            intel_gpu_freq(dev_priv, max_freq));
1236
1237                 max_freq = (rp_state_cap & 0xff00) >> 8;
1238                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1239                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1240                            intel_gpu_freq(dev_priv, max_freq));
1241
1242                 max_freq = rp_state_cap & 0xff;
1243                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1244                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1245                            intel_gpu_freq(dev_priv, max_freq));
1246                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1247                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1248
1249                 seq_printf(m, "Current freq: %d MHz\n",
1250                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1251                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1252                 seq_printf(m, "Idle freq: %d MHz\n",
1253                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1254                 seq_printf(m, "Min freq: %d MHz\n",
1255                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1256                 seq_printf(m, "Max freq: %d MHz\n",
1257                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1258                 seq_printf(m,
1259                            "efficient (RPe) frequency: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1261         } else if (IS_VALLEYVIEW(dev)) {
1262                 u32 freq_sts;
1263
1264                 mutex_lock(&dev_priv->rps.hw_lock);
1265                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1266                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1267                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1268
1269                 seq_printf(m, "actual GPU freq: %d MHz\n",
1270                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1271
1272                 seq_printf(m, "current GPU freq: %d MHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274
1275                 seq_printf(m, "max GPU freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1277
1278                 seq_printf(m, "min GPU freq: %d MHz\n",
1279                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1280
1281                 seq_printf(m, "idle GPU freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1283
1284                 seq_printf(m,
1285                            "efficient (RPe) frequency: %d MHz\n",
1286                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1287                 mutex_unlock(&dev_priv->rps.hw_lock);
1288         } else {
1289                 seq_puts(m, "no P-state info available\n");
1290         }
1291
1292 out:
1293         intel_runtime_pm_put(dev_priv);
1294         return ret;
1295 }
1296
1297 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1298 {
1299         struct drm_info_node *node = m->private;
1300         struct drm_device *dev = node->minor->dev;
1301         struct drm_i915_private *dev_priv = dev->dev_private;
1302         struct intel_engine_cs *ring;
1303         u64 acthd[I915_NUM_RINGS];
1304         u32 seqno[I915_NUM_RINGS];
1305         int i;
1306
1307         if (!i915.enable_hangcheck) {
1308                 seq_printf(m, "Hangcheck disabled\n");
1309                 return 0;
1310         }
1311
1312         intel_runtime_pm_get(dev_priv);
1313
1314         for_each_ring(ring, dev_priv, i) {
1315                 seqno[i] = ring->get_seqno(ring, false);
1316                 acthd[i] = intel_ring_get_active_head(ring);
1317         }
1318
1319         intel_runtime_pm_put(dev_priv);
1320
1321         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1322                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1323                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1324                                             jiffies));
1325         } else
1326                 seq_printf(m, "Hangcheck inactive\n");
1327
1328         for_each_ring(ring, dev_priv, i) {
1329                 seq_printf(m, "%s:\n", ring->name);
1330                 seq_printf(m, "\tseqno = %x [current %x]\n",
1331                            ring->hangcheck.seqno, seqno[i]);
1332                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1333                            (long long)ring->hangcheck.acthd,
1334                            (long long)acthd[i]);
1335                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1336                            (long long)ring->hangcheck.max_acthd);
1337                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1338                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int ironlake_drpc_info(struct seq_file *m)
1345 {
1346         struct drm_info_node *node = m->private;
1347         struct drm_device *dev = node->minor->dev;
1348         struct drm_i915_private *dev_priv = dev->dev_private;
1349         u32 rgvmodectl, rstdbyctl;
1350         u16 crstandvid;
1351         int ret;
1352
1353         ret = mutex_lock_interruptible(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356         intel_runtime_pm_get(dev_priv);
1357
1358         rgvmodectl = I915_READ(MEMMODECTL);
1359         rstdbyctl = I915_READ(RSTDBYCTL);
1360         crstandvid = I915_READ16(CRSTANDVID);
1361
1362         intel_runtime_pm_put(dev_priv);
1363         mutex_unlock(&dev->struct_mutex);
1364
1365         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1366                    "yes" : "no");
1367         seq_printf(m, "Boost freq: %d\n",
1368                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1369                    MEMMODE_BOOST_FREQ_SHIFT);
1370         seq_printf(m, "HW control enabled: %s\n",
1371                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1372         seq_printf(m, "SW control enabled: %s\n",
1373                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1374         seq_printf(m, "Gated voltage change: %s\n",
1375                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1376         seq_printf(m, "Starting frequency: P%d\n",
1377                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1378         seq_printf(m, "Max P-state: P%d\n",
1379                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1380         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1381         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1382         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1383         seq_printf(m, "Render standby enabled: %s\n",
1384                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1385         seq_puts(m, "Current RS state: ");
1386         switch (rstdbyctl & RSX_STATUS_MASK) {
1387         case RSX_STATUS_ON:
1388                 seq_puts(m, "on\n");
1389                 break;
1390         case RSX_STATUS_RC1:
1391                 seq_puts(m, "RC1\n");
1392                 break;
1393         case RSX_STATUS_RC1E:
1394                 seq_puts(m, "RC1E\n");
1395                 break;
1396         case RSX_STATUS_RS1:
1397                 seq_puts(m, "RS1\n");
1398                 break;
1399         case RSX_STATUS_RS2:
1400                 seq_puts(m, "RS2 (RC6)\n");
1401                 break;
1402         case RSX_STATUS_RS3:
1403                 seq_puts(m, "RC3 (RC6+)\n");
1404                 break;
1405         default:
1406                 seq_puts(m, "unknown\n");
1407                 break;
1408         }
1409
1410         return 0;
1411 }
1412
1413 static int i915_forcewake_domains(struct seq_file *m, void *data)
1414 {
1415         struct drm_info_node *node = m->private;
1416         struct drm_device *dev = node->minor->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct intel_uncore_forcewake_domain *fw_domain;
1419         int i;
1420
1421         spin_lock_irq(&dev_priv->uncore.lock);
1422         for_each_fw_domain(fw_domain, dev_priv, i) {
1423                 seq_printf(m, "%s.wake_count = %u\n",
1424                            intel_uncore_forcewake_domain_to_str(i),
1425                            fw_domain->wake_count);
1426         }
1427         spin_unlock_irq(&dev_priv->uncore.lock);
1428
1429         return 0;
1430 }
1431
1432 static int vlv_drpc_info(struct seq_file *m)
1433 {
1434         struct drm_info_node *node = m->private;
1435         struct drm_device *dev = node->minor->dev;
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         u32 rpmodectl1, rcctl1, pw_status;
1438
1439         intel_runtime_pm_get(dev_priv);
1440
1441         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1442         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1443         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1444
1445         intel_runtime_pm_put(dev_priv);
1446
1447         seq_printf(m, "Video Turbo Mode: %s\n",
1448                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1449         seq_printf(m, "Turbo enabled: %s\n",
1450                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1451         seq_printf(m, "HW control enabled: %s\n",
1452                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1453         seq_printf(m, "SW control enabled: %s\n",
1454                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1455                           GEN6_RP_MEDIA_SW_MODE));
1456         seq_printf(m, "RC6 Enabled: %s\n",
1457                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1458                                         GEN6_RC_CTL_EI_MODE(1))));
1459         seq_printf(m, "Render Power Well: %s\n",
1460                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1461         seq_printf(m, "Media Power Well: %s\n",
1462                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1463
1464         seq_printf(m, "Render RC6 residency since boot: %u\n",
1465                    I915_READ(VLV_GT_RENDER_RC6));
1466         seq_printf(m, "Media RC6 residency since boot: %u\n",
1467                    I915_READ(VLV_GT_MEDIA_RC6));
1468
1469         return i915_forcewake_domains(m, NULL);
1470 }
1471
1472 static int gen6_drpc_info(struct seq_file *m)
1473 {
1474         struct drm_info_node *node = m->private;
1475         struct drm_device *dev = node->minor->dev;
1476         struct drm_i915_private *dev_priv = dev->dev_private;
1477         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1478         unsigned forcewake_count;
1479         int count = 0, ret;
1480
1481         ret = mutex_lock_interruptible(&dev->struct_mutex);
1482         if (ret)
1483                 return ret;
1484         intel_runtime_pm_get(dev_priv);
1485
1486         spin_lock_irq(&dev_priv->uncore.lock);
1487         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1488         spin_unlock_irq(&dev_priv->uncore.lock);
1489
1490         if (forcewake_count) {
1491                 seq_puts(m, "RC information inaccurate because somebody "
1492                             "holds a forcewake reference \n");
1493         } else {
1494                 /* NB: we cannot use forcewake, else we read the wrong values */
1495                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1496                         udelay(10);
1497                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1498         }
1499
1500         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1501         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1502
1503         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1504         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1505         mutex_unlock(&dev->struct_mutex);
1506         mutex_lock(&dev_priv->rps.hw_lock);
1507         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1508         mutex_unlock(&dev_priv->rps.hw_lock);
1509
1510         intel_runtime_pm_put(dev_priv);
1511
1512         seq_printf(m, "Video Turbo Mode: %s\n",
1513                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1514         seq_printf(m, "HW control enabled: %s\n",
1515                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1516         seq_printf(m, "SW control enabled: %s\n",
1517                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1518                           GEN6_RP_MEDIA_SW_MODE));
1519         seq_printf(m, "RC1e Enabled: %s\n",
1520                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1521         seq_printf(m, "RC6 Enabled: %s\n",
1522                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1523         seq_printf(m, "Deep RC6 Enabled: %s\n",
1524                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1525         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1526                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1527         seq_puts(m, "Current RC state: ");
1528         switch (gt_core_status & GEN6_RCn_MASK) {
1529         case GEN6_RC0:
1530                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1531                         seq_puts(m, "Core Power Down\n");
1532                 else
1533                         seq_puts(m, "on\n");
1534                 break;
1535         case GEN6_RC3:
1536                 seq_puts(m, "RC3\n");
1537                 break;
1538         case GEN6_RC6:
1539                 seq_puts(m, "RC6\n");
1540                 break;
1541         case GEN6_RC7:
1542                 seq_puts(m, "RC7\n");
1543                 break;
1544         default:
1545                 seq_puts(m, "Unknown\n");
1546                 break;
1547         }
1548
1549         seq_printf(m, "Core Power Down: %s\n",
1550                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1551
1552         /* Not exactly sure what this is */
1553         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1554                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1555         seq_printf(m, "RC6 residency since boot: %u\n",
1556                    I915_READ(GEN6_GT_GFX_RC6));
1557         seq_printf(m, "RC6+ residency since boot: %u\n",
1558                    I915_READ(GEN6_GT_GFX_RC6p));
1559         seq_printf(m, "RC6++ residency since boot: %u\n",
1560                    I915_READ(GEN6_GT_GFX_RC6pp));
1561
1562         seq_printf(m, "RC6   voltage: %dmV\n",
1563                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1564         seq_printf(m, "RC6+  voltage: %dmV\n",
1565                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1566         seq_printf(m, "RC6++ voltage: %dmV\n",
1567                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1568         return 0;
1569 }
1570
1571 static int i915_drpc_info(struct seq_file *m, void *unused)
1572 {
1573         struct drm_info_node *node = m->private;
1574         struct drm_device *dev = node->minor->dev;
1575
1576         if (IS_VALLEYVIEW(dev))
1577                 return vlv_drpc_info(m);
1578         else if (INTEL_INFO(dev)->gen >= 6)
1579                 return gen6_drpc_info(m);
1580         else
1581                 return ironlake_drpc_info(m);
1582 }
1583
1584 static int i915_fbc_status(struct seq_file *m, void *unused)
1585 {
1586         struct drm_info_node *node = m->private;
1587         struct drm_device *dev = node->minor->dev;
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589
1590         if (!HAS_FBC(dev)) {
1591                 seq_puts(m, "FBC unsupported on this chipset\n");
1592                 return 0;
1593         }
1594
1595         intel_runtime_pm_get(dev_priv);
1596
1597         if (intel_fbc_enabled(dev)) {
1598                 seq_puts(m, "FBC enabled\n");
1599         } else {
1600                 seq_puts(m, "FBC disabled: ");
1601                 switch (dev_priv->fbc.no_fbc_reason) {
1602                 case FBC_OK:
1603                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1604                         break;
1605                 case FBC_UNSUPPORTED:
1606                         seq_puts(m, "unsupported by this chipset");
1607                         break;
1608                 case FBC_NO_OUTPUT:
1609                         seq_puts(m, "no outputs");
1610                         break;
1611                 case FBC_STOLEN_TOO_SMALL:
1612                         seq_puts(m, "not enough stolen memory");
1613                         break;
1614                 case FBC_UNSUPPORTED_MODE:
1615                         seq_puts(m, "mode not supported");
1616                         break;
1617                 case FBC_MODE_TOO_LARGE:
1618                         seq_puts(m, "mode too large");
1619                         break;
1620                 case FBC_BAD_PLANE:
1621                         seq_puts(m, "FBC unsupported on plane");
1622                         break;
1623                 case FBC_NOT_TILED:
1624                         seq_puts(m, "scanout buffer not tiled");
1625                         break;
1626                 case FBC_MULTIPLE_PIPES:
1627                         seq_puts(m, "multiple pipes are enabled");
1628                         break;
1629                 case FBC_MODULE_PARAM:
1630                         seq_puts(m, "disabled per module param (default off)");
1631                         break;
1632                 case FBC_CHIP_DEFAULT:
1633                         seq_puts(m, "disabled per chip default");
1634                         break;
1635                 default:
1636                         seq_puts(m, "unknown reason");
1637                 }
1638                 seq_putc(m, '\n');
1639         }
1640
1641         intel_runtime_pm_put(dev_priv);
1642
1643         return 0;
1644 }
1645
1646 static int i915_fbc_fc_get(void *data, u64 *val)
1647 {
1648         struct drm_device *dev = data;
1649         struct drm_i915_private *dev_priv = dev->dev_private;
1650
1651         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1652                 return -ENODEV;
1653
1654         drm_modeset_lock_all(dev);
1655         *val = dev_priv->fbc.false_color;
1656         drm_modeset_unlock_all(dev);
1657
1658         return 0;
1659 }
1660
1661 static int i915_fbc_fc_set(void *data, u64 val)
1662 {
1663         struct drm_device *dev = data;
1664         struct drm_i915_private *dev_priv = dev->dev_private;
1665         u32 reg;
1666
1667         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1668                 return -ENODEV;
1669
1670         drm_modeset_lock_all(dev);
1671
1672         reg = I915_READ(ILK_DPFC_CONTROL);
1673         dev_priv->fbc.false_color = val;
1674
1675         I915_WRITE(ILK_DPFC_CONTROL, val ?
1676                    (reg | FBC_CTL_FALSE_COLOR) :
1677                    (reg & ~FBC_CTL_FALSE_COLOR));
1678
1679         drm_modeset_unlock_all(dev);
1680         return 0;
1681 }
1682
1683 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1684                         i915_fbc_fc_get, i915_fbc_fc_set,
1685                         "%llu\n");
1686
1687 static int i915_ips_status(struct seq_file *m, void *unused)
1688 {
1689         struct drm_info_node *node = m->private;
1690         struct drm_device *dev = node->minor->dev;
1691         struct drm_i915_private *dev_priv = dev->dev_private;
1692
1693         if (!HAS_IPS(dev)) {
1694                 seq_puts(m, "not supported\n");
1695                 return 0;
1696         }
1697
1698         intel_runtime_pm_get(dev_priv);
1699
1700         seq_printf(m, "Enabled by kernel parameter: %s\n",
1701                    yesno(i915.enable_ips));
1702
1703         if (INTEL_INFO(dev)->gen >= 8) {
1704                 seq_puts(m, "Currently: unknown\n");
1705         } else {
1706                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1707                         seq_puts(m, "Currently: enabled\n");
1708                 else
1709                         seq_puts(m, "Currently: disabled\n");
1710         }
1711
1712         intel_runtime_pm_put(dev_priv);
1713
1714         return 0;
1715 }
1716
1717 static int i915_sr_status(struct seq_file *m, void *unused)
1718 {
1719         struct drm_info_node *node = m->private;
1720         struct drm_device *dev = node->minor->dev;
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722         bool sr_enabled = false;
1723
1724         intel_runtime_pm_get(dev_priv);
1725
1726         if (HAS_PCH_SPLIT(dev))
1727                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1728         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1729                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1730         else if (IS_I915GM(dev))
1731                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1732         else if (IS_PINEVIEW(dev))
1733                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1734
1735         intel_runtime_pm_put(dev_priv);
1736
1737         seq_printf(m, "self-refresh: %s\n",
1738                    sr_enabled ? "enabled" : "disabled");
1739
1740         return 0;
1741 }
1742
1743 static int i915_emon_status(struct seq_file *m, void *unused)
1744 {
1745         struct drm_info_node *node = m->private;
1746         struct drm_device *dev = node->minor->dev;
1747         struct drm_i915_private *dev_priv = dev->dev_private;
1748         unsigned long temp, chipset, gfx;
1749         int ret;
1750
1751         if (!IS_GEN5(dev))
1752                 return -ENODEV;
1753
1754         ret = mutex_lock_interruptible(&dev->struct_mutex);
1755         if (ret)
1756                 return ret;
1757
1758         temp = i915_mch_val(dev_priv);
1759         chipset = i915_chipset_val(dev_priv);
1760         gfx = i915_gfx_val(dev_priv);
1761         mutex_unlock(&dev->struct_mutex);
1762
1763         seq_printf(m, "GMCH temp: %ld\n", temp);
1764         seq_printf(m, "Chipset power: %ld\n", chipset);
1765         seq_printf(m, "GFX power: %ld\n", gfx);
1766         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1767
1768         return 0;
1769 }
1770
1771 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1772 {
1773         struct drm_info_node *node = m->private;
1774         struct drm_device *dev = node->minor->dev;
1775         struct drm_i915_private *dev_priv = dev->dev_private;
1776         int ret = 0;
1777         int gpu_freq, ia_freq;
1778
1779         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1780                 seq_puts(m, "unsupported on this chipset\n");
1781                 return 0;
1782         }
1783
1784         intel_runtime_pm_get(dev_priv);
1785
1786         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1787
1788         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1789         if (ret)
1790                 goto out;
1791
1792         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1793
1794         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1795              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1796              gpu_freq++) {
1797                 ia_freq = gpu_freq;
1798                 sandybridge_pcode_read(dev_priv,
1799                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1800                                        &ia_freq);
1801                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1802                            intel_gpu_freq(dev_priv, gpu_freq),
1803                            ((ia_freq >> 0) & 0xff) * 100,
1804                            ((ia_freq >> 8) & 0xff) * 100);
1805         }
1806
1807         mutex_unlock(&dev_priv->rps.hw_lock);
1808
1809 out:
1810         intel_runtime_pm_put(dev_priv);
1811         return ret;
1812 }
1813
1814 static int i915_opregion(struct seq_file *m, void *unused)
1815 {
1816         struct drm_info_node *node = m->private;
1817         struct drm_device *dev = node->minor->dev;
1818         struct drm_i915_private *dev_priv = dev->dev_private;
1819         struct intel_opregion *opregion = &dev_priv->opregion;
1820         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1821         int ret;
1822
1823         if (data == NULL)
1824                 return -ENOMEM;
1825
1826         ret = mutex_lock_interruptible(&dev->struct_mutex);
1827         if (ret)
1828                 goto out;
1829
1830         if (opregion->header) {
1831                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1832                 seq_write(m, data, OPREGION_SIZE);
1833         }
1834
1835         mutex_unlock(&dev->struct_mutex);
1836
1837 out:
1838         kfree(data);
1839         return 0;
1840 }
1841
1842 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1843 {
1844         struct drm_info_node *node = m->private;
1845         struct drm_device *dev = node->minor->dev;
1846         struct intel_fbdev *ifbdev = NULL;
1847         struct intel_framebuffer *fb;
1848
1849 #ifdef CONFIG_DRM_I915_FBDEV
1850         struct drm_i915_private *dev_priv = dev->dev_private;
1851
1852         ifbdev = dev_priv->fbdev;
1853         fb = to_intel_framebuffer(ifbdev->helper.fb);
1854
1855         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1856                    fb->base.width,
1857                    fb->base.height,
1858                    fb->base.depth,
1859                    fb->base.bits_per_pixel,
1860                    fb->base.modifier[0],
1861                    atomic_read(&fb->base.refcount.refcount));
1862         describe_obj(m, fb->obj);
1863         seq_putc(m, '\n');
1864 #endif
1865
1866         mutex_lock(&dev->mode_config.fb_lock);
1867         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1868                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1869                         continue;
1870
1871                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1872                            fb->base.width,
1873                            fb->base.height,
1874                            fb->base.depth,
1875                            fb->base.bits_per_pixel,
1876                            fb->base.modifier[0],
1877                            atomic_read(&fb->base.refcount.refcount));
1878                 describe_obj(m, fb->obj);
1879                 seq_putc(m, '\n');
1880         }
1881         mutex_unlock(&dev->mode_config.fb_lock);
1882
1883         return 0;
1884 }
1885
1886 static void describe_ctx_ringbuf(struct seq_file *m,
1887                                  struct intel_ringbuffer *ringbuf)
1888 {
1889         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1890                    ringbuf->space, ringbuf->head, ringbuf->tail,
1891                    ringbuf->last_retired_head);
1892 }
1893
1894 static int i915_context_status(struct seq_file *m, void *unused)
1895 {
1896         struct drm_info_node *node = m->private;
1897         struct drm_device *dev = node->minor->dev;
1898         struct drm_i915_private *dev_priv = dev->dev_private;
1899         struct intel_engine_cs *ring;
1900         struct intel_context *ctx;
1901         int ret, i;
1902
1903         ret = mutex_lock_interruptible(&dev->struct_mutex);
1904         if (ret)
1905                 return ret;
1906
1907         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1908                 if (!i915.enable_execlists &&
1909                     ctx->legacy_hw_ctx.rcs_state == NULL)
1910                         continue;
1911
1912                 seq_puts(m, "HW context ");
1913                 describe_ctx(m, ctx);
1914                 for_each_ring(ring, dev_priv, i) {
1915                         if (ring->default_context == ctx)
1916                                 seq_printf(m, "(default context %s) ",
1917                                            ring->name);
1918                 }
1919
1920                 if (i915.enable_execlists) {
1921                         seq_putc(m, '\n');
1922                         for_each_ring(ring, dev_priv, i) {
1923                                 struct drm_i915_gem_object *ctx_obj =
1924                                         ctx->engine[i].state;
1925                                 struct intel_ringbuffer *ringbuf =
1926                                         ctx->engine[i].ringbuf;
1927
1928                                 seq_printf(m, "%s: ", ring->name);
1929                                 if (ctx_obj)
1930                                         describe_obj(m, ctx_obj);
1931                                 if (ringbuf)
1932                                         describe_ctx_ringbuf(m, ringbuf);
1933                                 seq_putc(m, '\n');
1934                         }
1935                 } else {
1936                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1937                 }
1938
1939                 seq_putc(m, '\n');
1940         }
1941
1942         mutex_unlock(&dev->struct_mutex);
1943
1944         return 0;
1945 }
1946
1947 static void i915_dump_lrc_obj(struct seq_file *m,
1948                               struct intel_engine_cs *ring,
1949                               struct drm_i915_gem_object *ctx_obj)
1950 {
1951         struct page *page;
1952         uint32_t *reg_state;
1953         int j;
1954         unsigned long ggtt_offset = 0;
1955
1956         if (ctx_obj == NULL) {
1957                 seq_printf(m, "Context on %s with no gem object\n",
1958                            ring->name);
1959                 return;
1960         }
1961
1962         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1963                    intel_execlists_ctx_id(ctx_obj));
1964
1965         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1966                 seq_puts(m, "\tNot bound in GGTT\n");
1967         else
1968                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1969
1970         if (i915_gem_object_get_pages(ctx_obj)) {
1971                 seq_puts(m, "\tFailed to get pages for context object\n");
1972                 return;
1973         }
1974
1975         page = i915_gem_object_get_page(ctx_obj, 1);
1976         if (!WARN_ON(page == NULL)) {
1977                 reg_state = kmap_atomic(page);
1978
1979                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1980                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1981                                    ggtt_offset + 4096 + (j * 4),
1982                                    reg_state[j], reg_state[j + 1],
1983                                    reg_state[j + 2], reg_state[j + 3]);
1984                 }
1985                 kunmap_atomic(reg_state);
1986         }
1987
1988         seq_putc(m, '\n');
1989 }
1990
1991 static int i915_dump_lrc(struct seq_file *m, void *unused)
1992 {
1993         struct drm_info_node *node = (struct drm_info_node *) m->private;
1994         struct drm_device *dev = node->minor->dev;
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996         struct intel_engine_cs *ring;
1997         struct intel_context *ctx;
1998         int ret, i;
1999
2000         if (!i915.enable_execlists) {
2001                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2002                 return 0;
2003         }
2004
2005         ret = mutex_lock_interruptible(&dev->struct_mutex);
2006         if (ret)
2007                 return ret;
2008
2009         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2010                 for_each_ring(ring, dev_priv, i) {
2011                         if (ring->default_context != ctx)
2012                                 i915_dump_lrc_obj(m, ring,
2013                                                   ctx->engine[i].state);
2014                 }
2015         }
2016
2017         mutex_unlock(&dev->struct_mutex);
2018
2019         return 0;
2020 }
2021
2022 static int i915_execlists(struct seq_file *m, void *data)
2023 {
2024         struct drm_info_node *node = (struct drm_info_node *)m->private;
2025         struct drm_device *dev = node->minor->dev;
2026         struct drm_i915_private *dev_priv = dev->dev_private;
2027         struct intel_engine_cs *ring;
2028         u32 status_pointer;
2029         u8 read_pointer;
2030         u8 write_pointer;
2031         u32 status;
2032         u32 ctx_id;
2033         struct list_head *cursor;
2034         int ring_id, i;
2035         int ret;
2036
2037         if (!i915.enable_execlists) {
2038                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2039                 return 0;
2040         }
2041
2042         ret = mutex_lock_interruptible(&dev->struct_mutex);
2043         if (ret)
2044                 return ret;
2045
2046         intel_runtime_pm_get(dev_priv);
2047
2048         for_each_ring(ring, dev_priv, ring_id) {
2049                 struct drm_i915_gem_request *head_req = NULL;
2050                 int count = 0;
2051                 unsigned long flags;
2052
2053                 seq_printf(m, "%s\n", ring->name);
2054
2055                 status = I915_READ(RING_EXECLIST_STATUS(ring));
2056                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2057                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2058                            status, ctx_id);
2059
2060                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2061                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2062
2063                 read_pointer = ring->next_context_status_buffer;
2064                 write_pointer = status_pointer & 0x07;
2065                 if (read_pointer > write_pointer)
2066                         write_pointer += 6;
2067                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2068                            read_pointer, write_pointer);
2069
2070                 for (i = 0; i < 6; i++) {
2071                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2072                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2073
2074                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2075                                    i, status, ctx_id);
2076                 }
2077
2078                 spin_lock_irqsave(&ring->execlist_lock, flags);
2079                 list_for_each(cursor, &ring->execlist_queue)
2080                         count++;
2081                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2082                                 struct drm_i915_gem_request, execlist_link);
2083                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2084
2085                 seq_printf(m, "\t%d requests in queue\n", count);
2086                 if (head_req) {
2087                         struct drm_i915_gem_object *ctx_obj;
2088
2089                         ctx_obj = head_req->ctx->engine[ring_id].state;
2090                         seq_printf(m, "\tHead request id: %u\n",
2091                                    intel_execlists_ctx_id(ctx_obj));
2092                         seq_printf(m, "\tHead request tail: %u\n",
2093                                    head_req->tail);
2094                 }
2095
2096                 seq_putc(m, '\n');
2097         }
2098
2099         intel_runtime_pm_put(dev_priv);
2100         mutex_unlock(&dev->struct_mutex);
2101
2102         return 0;
2103 }
2104
2105 static const char *swizzle_string(unsigned swizzle)
2106 {
2107         switch (swizzle) {
2108         case I915_BIT_6_SWIZZLE_NONE:
2109                 return "none";
2110         case I915_BIT_6_SWIZZLE_9:
2111                 return "bit9";
2112         case I915_BIT_6_SWIZZLE_9_10:
2113                 return "bit9/bit10";
2114         case I915_BIT_6_SWIZZLE_9_11:
2115                 return "bit9/bit11";
2116         case I915_BIT_6_SWIZZLE_9_10_11:
2117                 return "bit9/bit10/bit11";
2118         case I915_BIT_6_SWIZZLE_9_17:
2119                 return "bit9/bit17";
2120         case I915_BIT_6_SWIZZLE_9_10_17:
2121                 return "bit9/bit10/bit17";
2122         case I915_BIT_6_SWIZZLE_UNKNOWN:
2123                 return "unknown";
2124         }
2125
2126         return "bug";
2127 }
2128
2129 static int i915_swizzle_info(struct seq_file *m, void *data)
2130 {
2131         struct drm_info_node *node = m->private;
2132         struct drm_device *dev = node->minor->dev;
2133         struct drm_i915_private *dev_priv = dev->dev_private;
2134         int ret;
2135
2136         ret = mutex_lock_interruptible(&dev->struct_mutex);
2137         if (ret)
2138                 return ret;
2139         intel_runtime_pm_get(dev_priv);
2140
2141         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2142                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2143         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2144                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2145
2146         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2147                 seq_printf(m, "DDC = 0x%08x\n",
2148                            I915_READ(DCC));
2149                 seq_printf(m, "DDC2 = 0x%08x\n",
2150                            I915_READ(DCC2));
2151                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2152                            I915_READ16(C0DRB3));
2153                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2154                            I915_READ16(C1DRB3));
2155         } else if (INTEL_INFO(dev)->gen >= 6) {
2156                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2157                            I915_READ(MAD_DIMM_C0));
2158                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2159                            I915_READ(MAD_DIMM_C1));
2160                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2161                            I915_READ(MAD_DIMM_C2));
2162                 seq_printf(m, "TILECTL = 0x%08x\n",
2163                            I915_READ(TILECTL));
2164                 if (INTEL_INFO(dev)->gen >= 8)
2165                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2166                                    I915_READ(GAMTARBMODE));
2167                 else
2168                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2169                                    I915_READ(ARB_MODE));
2170                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2171                            I915_READ(DISP_ARB_CTL));
2172         }
2173
2174         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2175                 seq_puts(m, "L-shaped memory detected\n");
2176
2177         intel_runtime_pm_put(dev_priv);
2178         mutex_unlock(&dev->struct_mutex);
2179
2180         return 0;
2181 }
2182
2183 static int per_file_ctx(int id, void *ptr, void *data)
2184 {
2185         struct intel_context *ctx = ptr;
2186         struct seq_file *m = data;
2187         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2188
2189         if (!ppgtt) {
2190                 seq_printf(m, "  no ppgtt for context %d\n",
2191                            ctx->user_handle);
2192                 return 0;
2193         }
2194
2195         if (i915_gem_context_is_default(ctx))
2196                 seq_puts(m, "  default context:\n");
2197         else
2198                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2199         ppgtt->debug_dump(ppgtt, m);
2200
2201         return 0;
2202 }
2203
2204 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2205 {
2206         struct drm_i915_private *dev_priv = dev->dev_private;
2207         struct intel_engine_cs *ring;
2208         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2209         int unused, i;
2210
2211         if (!ppgtt)
2212                 return;
2213
2214         for_each_ring(ring, dev_priv, unused) {
2215                 seq_printf(m, "%s\n", ring->name);
2216                 for (i = 0; i < 4; i++) {
2217                         u32 offset = 0x270 + i * 8;
2218                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2219                         pdp <<= 32;
2220                         pdp |= I915_READ(ring->mmio_base + offset);
2221                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2222                 }
2223         }
2224 }
2225
2226 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2227 {
2228         struct drm_i915_private *dev_priv = dev->dev_private;
2229         struct intel_engine_cs *ring;
2230         struct drm_file *file;
2231         int i;
2232
2233         if (INTEL_INFO(dev)->gen == 6)
2234                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2235
2236         for_each_ring(ring, dev_priv, i) {
2237                 seq_printf(m, "%s\n", ring->name);
2238                 if (INTEL_INFO(dev)->gen == 7)
2239                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2240                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2241                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2242                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2243         }
2244         if (dev_priv->mm.aliasing_ppgtt) {
2245                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2246
2247                 seq_puts(m, "aliasing PPGTT:\n");
2248                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.pd_offset);
2249
2250                 ppgtt->debug_dump(ppgtt, m);
2251         }
2252
2253         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2254                 struct drm_i915_file_private *file_priv = file->driver_priv;
2255
2256                 seq_printf(m, "proc: %s\n",
2257                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2258                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2259         }
2260         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2261 }
2262
2263 static int i915_ppgtt_info(struct seq_file *m, void *data)
2264 {
2265         struct drm_info_node *node = m->private;
2266         struct drm_device *dev = node->minor->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268
2269         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2270         if (ret)
2271                 return ret;
2272         intel_runtime_pm_get(dev_priv);
2273
2274         if (INTEL_INFO(dev)->gen >= 8)
2275                 gen8_ppgtt_info(m, dev);
2276         else if (INTEL_INFO(dev)->gen >= 6)
2277                 gen6_ppgtt_info(m, dev);
2278
2279         intel_runtime_pm_put(dev_priv);
2280         mutex_unlock(&dev->struct_mutex);
2281
2282         return 0;
2283 }
2284
2285 static int count_irq_waiters(struct drm_i915_private *i915)
2286 {
2287         struct intel_engine_cs *ring;
2288         int count = 0;
2289         int i;
2290
2291         for_each_ring(ring, i915, i)
2292                 count += ring->irq_refcount;
2293
2294         return count;
2295 }
2296
2297 static int i915_rps_boost_info(struct seq_file *m, void *data)
2298 {
2299         struct drm_info_node *node = m->private;
2300         struct drm_device *dev = node->minor->dev;
2301         struct drm_i915_private *dev_priv = dev->dev_private;
2302         struct drm_file *file;
2303         int ret;
2304
2305         ret = mutex_lock_interruptible(&dev->struct_mutex);
2306         if (ret)
2307                 return ret;
2308
2309         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
2310         if (ret)
2311                 goto unlock;
2312
2313         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2314         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2315         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2316         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2317                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2318                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2319                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2320                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2321                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2322         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2323                 struct drm_i915_file_private *file_priv = file->driver_priv;
2324                 struct task_struct *task;
2325
2326                 rcu_read_lock();
2327                 task = pid_task(file->pid, PIDTYPE_PID);
2328                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2329                            task ? task->comm : "<unknown>",
2330                            task ? task->pid : -1,
2331                            file_priv->rps.boosts,
2332                            list_empty(&file_priv->rps.link) ? "" : ", active");
2333                 rcu_read_unlock();
2334         }
2335         seq_printf(m, "Semaphore boosts: %d%s\n",
2336                    dev_priv->rps.semaphores.boosts,
2337                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2338         seq_printf(m, "MMIO flip boosts: %d%s\n",
2339                    dev_priv->rps.mmioflips.boosts,
2340                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2341         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2342
2343         mutex_unlock(&dev_priv->rps.hw_lock);
2344 unlock:
2345         mutex_unlock(&dev->struct_mutex);
2346
2347         return ret;
2348 }
2349
2350 static int i915_llc(struct seq_file *m, void *data)
2351 {
2352         struct drm_info_node *node = m->private;
2353         struct drm_device *dev = node->minor->dev;
2354         struct drm_i915_private *dev_priv = dev->dev_private;
2355
2356         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2357         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2358         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2359
2360         return 0;
2361 }
2362
2363 static int i915_edp_psr_status(struct seq_file *m, void *data)
2364 {
2365         struct drm_info_node *node = m->private;
2366         struct drm_device *dev = node->minor->dev;
2367         struct drm_i915_private *dev_priv = dev->dev_private;
2368         u32 psrperf = 0;
2369         u32 stat[3];
2370         enum pipe pipe;
2371         bool enabled = false;
2372
2373         if (!HAS_PSR(dev)) {
2374                 seq_puts(m, "PSR not supported\n");
2375                 return 0;
2376         }
2377
2378         intel_runtime_pm_get(dev_priv);
2379
2380         mutex_lock(&dev_priv->psr.lock);
2381         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2382         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2383         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2384         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2385         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2386                    dev_priv->psr.busy_frontbuffer_bits);
2387         seq_printf(m, "Re-enable work scheduled: %s\n",
2388                    yesno(work_busy(&dev_priv->psr.work.work)));
2389
2390         if (HAS_DDI(dev))
2391                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2392         else {
2393                 for_each_pipe(dev_priv, pipe) {
2394                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2395                                 VLV_EDP_PSR_CURR_STATE_MASK;
2396                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2397                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2398                                 enabled = true;
2399                 }
2400         }
2401         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2402
2403         if (!HAS_DDI(dev))
2404                 for_each_pipe(dev_priv, pipe) {
2405                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2406                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2407                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2408                 }
2409         seq_puts(m, "\n");
2410
2411         /* CHV PSR has no kind of performance counter */
2412         if (HAS_DDI(dev)) {
2413                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2414                         EDP_PSR_PERF_CNT_MASK;
2415
2416                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2417         }
2418         mutex_unlock(&dev_priv->psr.lock);
2419
2420         intel_runtime_pm_put(dev_priv);
2421         return 0;
2422 }
2423
2424 static int i915_sink_crc(struct seq_file *m, void *data)
2425 {
2426         struct drm_info_node *node = m->private;
2427         struct drm_device *dev = node->minor->dev;
2428         struct intel_encoder *encoder;
2429         struct intel_connector *connector;
2430         struct intel_dp *intel_dp = NULL;
2431         int ret;
2432         u8 crc[6];
2433
2434         drm_modeset_lock_all(dev);
2435         for_each_intel_connector(dev, connector) {
2436
2437                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2438                         continue;
2439
2440                 if (!connector->base.encoder)
2441                         continue;
2442
2443                 encoder = to_intel_encoder(connector->base.encoder);
2444                 if (encoder->type != INTEL_OUTPUT_EDP)
2445                         continue;
2446
2447                 intel_dp = enc_to_intel_dp(&encoder->base);
2448
2449                 ret = intel_dp_sink_crc(intel_dp, crc);
2450                 if (ret)
2451                         goto out;
2452
2453                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2454                            crc[0], crc[1], crc[2],
2455                            crc[3], crc[4], crc[5]);
2456                 goto out;
2457         }
2458         ret = -ENODEV;
2459 out:
2460         drm_modeset_unlock_all(dev);
2461         return ret;
2462 }
2463
2464 static int i915_energy_uJ(struct seq_file *m, void *data)
2465 {
2466         struct drm_info_node *node = m->private;
2467         struct drm_device *dev = node->minor->dev;
2468         struct drm_i915_private *dev_priv = dev->dev_private;
2469         u64 power;
2470         u32 units;
2471
2472         if (INTEL_INFO(dev)->gen < 6)
2473                 return -ENODEV;
2474
2475         intel_runtime_pm_get(dev_priv);
2476
2477         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2478         power = (power & 0x1f00) >> 8;
2479         units = 1000000 / (1 << power); /* convert to uJ */
2480         power = I915_READ(MCH_SECP_NRG_STTS);
2481         power *= units;
2482
2483         intel_runtime_pm_put(dev_priv);
2484
2485         seq_printf(m, "%llu", (long long unsigned)power);
2486
2487         return 0;
2488 }
2489
2490 static int i915_pc8_status(struct seq_file *m, void *unused)
2491 {
2492         struct drm_info_node *node = m->private;
2493         struct drm_device *dev = node->minor->dev;
2494         struct drm_i915_private *dev_priv = dev->dev_private;
2495
2496         if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2497                 seq_puts(m, "not supported\n");
2498                 return 0;
2499         }
2500
2501         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2502         seq_printf(m, "IRQs disabled: %s\n",
2503                    yesno(!intel_irqs_enabled(dev_priv)));
2504
2505         return 0;
2506 }
2507
2508 static const char *power_domain_str(enum intel_display_power_domain domain)
2509 {
2510         switch (domain) {
2511         case POWER_DOMAIN_PIPE_A:
2512                 return "PIPE_A";
2513         case POWER_DOMAIN_PIPE_B:
2514                 return "PIPE_B";
2515         case POWER_DOMAIN_PIPE_C:
2516                 return "PIPE_C";
2517         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2518                 return "PIPE_A_PANEL_FITTER";
2519         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2520                 return "PIPE_B_PANEL_FITTER";
2521         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2522                 return "PIPE_C_PANEL_FITTER";
2523         case POWER_DOMAIN_TRANSCODER_A:
2524                 return "TRANSCODER_A";
2525         case POWER_DOMAIN_TRANSCODER_B:
2526                 return "TRANSCODER_B";
2527         case POWER_DOMAIN_TRANSCODER_C:
2528                 return "TRANSCODER_C";
2529         case POWER_DOMAIN_TRANSCODER_EDP:
2530                 return "TRANSCODER_EDP";
2531         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2532                 return "PORT_DDI_A_2_LANES";
2533         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2534                 return "PORT_DDI_A_4_LANES";
2535         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2536                 return "PORT_DDI_B_2_LANES";
2537         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2538                 return "PORT_DDI_B_4_LANES";
2539         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2540                 return "PORT_DDI_C_2_LANES";
2541         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2542                 return "PORT_DDI_C_4_LANES";
2543         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2544                 return "PORT_DDI_D_2_LANES";
2545         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2546                 return "PORT_DDI_D_4_LANES";
2547         case POWER_DOMAIN_PORT_DSI:
2548                 return "PORT_DSI";
2549         case POWER_DOMAIN_PORT_CRT:
2550                 return "PORT_CRT";
2551         case POWER_DOMAIN_PORT_OTHER:
2552                 return "PORT_OTHER";
2553         case POWER_DOMAIN_VGA:
2554                 return "VGA";
2555         case POWER_DOMAIN_AUDIO:
2556                 return "AUDIO";
2557         case POWER_DOMAIN_PLLS:
2558                 return "PLLS";
2559         case POWER_DOMAIN_AUX_A:
2560                 return "AUX_A";
2561         case POWER_DOMAIN_AUX_B:
2562                 return "AUX_B";
2563         case POWER_DOMAIN_AUX_C:
2564                 return "AUX_C";
2565         case POWER_DOMAIN_AUX_D:
2566                 return "AUX_D";
2567         case POWER_DOMAIN_INIT:
2568                 return "INIT";
2569         default:
2570                 MISSING_CASE(domain);
2571                 return "?";
2572         }
2573 }
2574
2575 static int i915_power_domain_info(struct seq_file *m, void *unused)
2576 {
2577         struct drm_info_node *node = m->private;
2578         struct drm_device *dev = node->minor->dev;
2579         struct drm_i915_private *dev_priv = dev->dev_private;
2580         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2581         int i;
2582
2583         mutex_lock(&power_domains->lock);
2584
2585         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2586         for (i = 0; i < power_domains->power_well_count; i++) {
2587                 struct i915_power_well *power_well;
2588                 enum intel_display_power_domain power_domain;
2589
2590                 power_well = &power_domains->power_wells[i];
2591                 seq_printf(m, "%-25s %d\n", power_well->name,
2592                            power_well->count);
2593
2594                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2595                      power_domain++) {
2596                         if (!(BIT(power_domain) & power_well->domains))
2597                                 continue;
2598
2599                         seq_printf(m, "  %-23s %d\n",
2600                                  power_domain_str(power_domain),
2601                                  power_domains->domain_use_count[power_domain]);
2602                 }
2603         }
2604
2605         mutex_unlock(&power_domains->lock);
2606
2607         return 0;
2608 }
2609
2610 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2611                                  struct drm_display_mode *mode)
2612 {
2613         int i;
2614
2615         for (i = 0; i < tabs; i++)
2616                 seq_putc(m, '\t');
2617
2618         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2619                    mode->base.id, mode->name,
2620                    mode->vrefresh, mode->clock,
2621                    mode->hdisplay, mode->hsync_start,
2622                    mode->hsync_end, mode->htotal,
2623                    mode->vdisplay, mode->vsync_start,
2624                    mode->vsync_end, mode->vtotal,
2625                    mode->type, mode->flags);
2626 }
2627
2628 static void intel_encoder_info(struct seq_file *m,
2629                                struct intel_crtc *intel_crtc,
2630                                struct intel_encoder *intel_encoder)
2631 {
2632         struct drm_info_node *node = m->private;
2633         struct drm_device *dev = node->minor->dev;
2634         struct drm_crtc *crtc = &intel_crtc->base;
2635         struct intel_connector *intel_connector;
2636         struct drm_encoder *encoder;
2637
2638         encoder = &intel_encoder->base;
2639         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2640                    encoder->base.id, encoder->name);
2641         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2642                 struct drm_connector *connector = &intel_connector->base;
2643                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2644                            connector->base.id,
2645                            connector->name,
2646                            drm_get_connector_status_name(connector->status));
2647                 if (connector->status == connector_status_connected) {
2648                         struct drm_display_mode *mode = &crtc->mode;
2649                         seq_printf(m, ", mode:\n");
2650                         intel_seq_print_mode(m, 2, mode);
2651                 } else {
2652                         seq_putc(m, '\n');
2653                 }
2654         }
2655 }
2656
2657 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2658 {
2659         struct drm_info_node *node = m->private;
2660         struct drm_device *dev = node->minor->dev;
2661         struct drm_crtc *crtc = &intel_crtc->base;
2662         struct intel_encoder *intel_encoder;
2663
2664         if (crtc->primary->fb)
2665                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2666                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2667                            crtc->primary->fb->width, crtc->primary->fb->height);
2668         else
2669                 seq_puts(m, "\tprimary plane disabled\n");
2670         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2671                 intel_encoder_info(m, intel_crtc, intel_encoder);
2672 }
2673
2674 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2675 {
2676         struct drm_display_mode *mode = panel->fixed_mode;
2677
2678         seq_printf(m, "\tfixed mode:\n");
2679         intel_seq_print_mode(m, 2, mode);
2680 }
2681
2682 static void intel_dp_info(struct seq_file *m,
2683                           struct intel_connector *intel_connector)
2684 {
2685         struct intel_encoder *intel_encoder = intel_connector->encoder;
2686         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2687
2688         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2689         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2690                    "no");
2691         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2692                 intel_panel_info(m, &intel_connector->panel);
2693 }
2694
2695 static void intel_hdmi_info(struct seq_file *m,
2696                             struct intel_connector *intel_connector)
2697 {
2698         struct intel_encoder *intel_encoder = intel_connector->encoder;
2699         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2700
2701         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2702                    "no");
2703 }
2704
2705 static void intel_lvds_info(struct seq_file *m,
2706                             struct intel_connector *intel_connector)
2707 {
2708         intel_panel_info(m, &intel_connector->panel);
2709 }
2710
2711 static void intel_connector_info(struct seq_file *m,
2712                                  struct drm_connector *connector)
2713 {
2714         struct intel_connector *intel_connector = to_intel_connector(connector);
2715         struct intel_encoder *intel_encoder = intel_connector->encoder;
2716         struct drm_display_mode *mode;
2717
2718         seq_printf(m, "connector %d: type %s, status: %s\n",
2719                    connector->base.id, connector->name,
2720                    drm_get_connector_status_name(connector->status));
2721         if (connector->status == connector_status_connected) {
2722                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2723                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2724                            connector->display_info.width_mm,
2725                            connector->display_info.height_mm);
2726                 seq_printf(m, "\tsubpixel order: %s\n",
2727                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2728                 seq_printf(m, "\tCEA rev: %d\n",
2729                            connector->display_info.cea_rev);
2730         }
2731         if (intel_encoder) {
2732                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2733                     intel_encoder->type == INTEL_OUTPUT_EDP)
2734                         intel_dp_info(m, intel_connector);
2735                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2736                         intel_hdmi_info(m, intel_connector);
2737                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2738                         intel_lvds_info(m, intel_connector);
2739         }
2740
2741         seq_printf(m, "\tmodes:\n");
2742         list_for_each_entry(mode, &connector->modes, head)
2743                 intel_seq_print_mode(m, 2, mode);
2744 }
2745
2746 static bool cursor_active(struct drm_device *dev, int pipe)
2747 {
2748         struct drm_i915_private *dev_priv = dev->dev_private;
2749         u32 state;
2750
2751         if (IS_845G(dev) || IS_I865G(dev))
2752                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2753         else
2754                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2755
2756         return state;
2757 }
2758
2759 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2760 {
2761         struct drm_i915_private *dev_priv = dev->dev_private;
2762         u32 pos;
2763
2764         pos = I915_READ(CURPOS(pipe));
2765
2766         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2767         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2768                 *x = -*x;
2769
2770         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2771         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2772                 *y = -*y;
2773
2774         return cursor_active(dev, pipe);
2775 }
2776
2777 static int i915_display_info(struct seq_file *m, void *unused)
2778 {
2779         struct drm_info_node *node = m->private;
2780         struct drm_device *dev = node->minor->dev;
2781         struct drm_i915_private *dev_priv = dev->dev_private;
2782         struct intel_crtc *crtc;
2783         struct drm_connector *connector;
2784
2785         intel_runtime_pm_get(dev_priv);
2786         drm_modeset_lock_all(dev);
2787         seq_printf(m, "CRTC info\n");
2788         seq_printf(m, "---------\n");
2789         for_each_intel_crtc(dev, crtc) {
2790                 bool active;
2791                 int x, y;
2792
2793                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2794                            crtc->base.base.id, pipe_name(crtc->pipe),
2795                            yesno(crtc->active), crtc->config->pipe_src_w,
2796                            crtc->config->pipe_src_h);
2797                 if (crtc->active) {
2798                         intel_crtc_info(m, crtc);
2799
2800                         active = cursor_position(dev, crtc->pipe, &x, &y);
2801                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2802                                    yesno(crtc->cursor_base),
2803                                    x, y, crtc->base.cursor->state->crtc_w,
2804                                    crtc->base.cursor->state->crtc_h,
2805                                    crtc->cursor_addr, yesno(active));
2806                 }
2807
2808                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2809                            yesno(!crtc->cpu_fifo_underrun_disabled),
2810                            yesno(!crtc->pch_fifo_underrun_disabled));
2811         }
2812
2813         seq_printf(m, "\n");
2814         seq_printf(m, "Connector info\n");
2815         seq_printf(m, "--------------\n");
2816         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2817                 intel_connector_info(m, connector);
2818         }
2819         drm_modeset_unlock_all(dev);
2820         intel_runtime_pm_put(dev_priv);
2821
2822         return 0;
2823 }
2824
2825 static int i915_semaphore_status(struct seq_file *m, void *unused)
2826 {
2827         struct drm_info_node *node = (struct drm_info_node *) m->private;
2828         struct drm_device *dev = node->minor->dev;
2829         struct drm_i915_private *dev_priv = dev->dev_private;
2830         struct intel_engine_cs *ring;
2831         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2832         int i, j, ret;
2833
2834         if (!i915_semaphore_is_enabled(dev)) {
2835                 seq_puts(m, "Semaphores are disabled\n");
2836                 return 0;
2837         }
2838
2839         ret = mutex_lock_interruptible(&dev->struct_mutex);
2840         if (ret)
2841                 return ret;
2842         intel_runtime_pm_get(dev_priv);
2843
2844         if (IS_BROADWELL(dev)) {
2845                 struct page *page;
2846                 uint64_t *seqno;
2847
2848                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2849
2850                 seqno = (uint64_t *)kmap_atomic(page);
2851                 for_each_ring(ring, dev_priv, i) {
2852                         uint64_t offset;
2853
2854                         seq_printf(m, "%s\n", ring->name);
2855
2856                         seq_puts(m, "  Last signal:");
2857                         for (j = 0; j < num_rings; j++) {
2858                                 offset = i * I915_NUM_RINGS + j;
2859                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2860                                            seqno[offset], offset * 8);
2861                         }
2862                         seq_putc(m, '\n');
2863
2864                         seq_puts(m, "  Last wait:  ");
2865                         for (j = 0; j < num_rings; j++) {
2866                                 offset = i + (j * I915_NUM_RINGS);
2867                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2868                                            seqno[offset], offset * 8);
2869                         }
2870                         seq_putc(m, '\n');
2871
2872                 }
2873                 kunmap_atomic(seqno);
2874         } else {
2875                 seq_puts(m, "  Last signal:");
2876                 for_each_ring(ring, dev_priv, i)
2877                         for (j = 0; j < num_rings; j++)
2878                                 seq_printf(m, "0x%08x\n",
2879                                            I915_READ(ring->semaphore.mbox.signal[j]));
2880                 seq_putc(m, '\n');
2881         }
2882
2883         seq_puts(m, "\nSync seqno:\n");
2884         for_each_ring(ring, dev_priv, i) {
2885                 for (j = 0; j < num_rings; j++) {
2886                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2887                 }
2888                 seq_putc(m, '\n');
2889         }
2890         seq_putc(m, '\n');
2891
2892         intel_runtime_pm_put(dev_priv);
2893         mutex_unlock(&dev->struct_mutex);
2894         return 0;
2895 }
2896
2897 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2898 {
2899         struct drm_info_node *node = (struct drm_info_node *) m->private;
2900         struct drm_device *dev = node->minor->dev;
2901         struct drm_i915_private *dev_priv = dev->dev_private;
2902         int i;
2903
2904         drm_modeset_lock_all(dev);
2905         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2906                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2907
2908                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2909                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2910                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2911                 seq_printf(m, " tracked hardware state:\n");
2912                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2913                 seq_printf(m, " dpll_md: 0x%08x\n",
2914                            pll->config.hw_state.dpll_md);
2915                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2916                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2917                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2918         }
2919         drm_modeset_unlock_all(dev);
2920
2921         return 0;
2922 }
2923
2924 static int i915_wa_registers(struct seq_file *m, void *unused)
2925 {
2926         int i;
2927         int ret;
2928         struct drm_info_node *node = (struct drm_info_node *) m->private;
2929         struct drm_device *dev = node->minor->dev;
2930         struct drm_i915_private *dev_priv = dev->dev_private;
2931
2932         ret = mutex_lock_interruptible(&dev->struct_mutex);
2933         if (ret)
2934                 return ret;
2935
2936         intel_runtime_pm_get(dev_priv);
2937
2938         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2939         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2940                 u32 addr, mask, value, read;
2941                 bool ok;
2942
2943                 addr = dev_priv->workarounds.reg[i].addr;
2944                 mask = dev_priv->workarounds.reg[i].mask;
2945                 value = dev_priv->workarounds.reg[i].value;
2946                 read = I915_READ(addr);
2947                 ok = (value & mask) == (read & mask);
2948                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2949                            addr, value, mask, read, ok ? "OK" : "FAIL");
2950         }
2951
2952         intel_runtime_pm_put(dev_priv);
2953         mutex_unlock(&dev->struct_mutex);
2954
2955         return 0;
2956 }
2957
2958 static int i915_ddb_info(struct seq_file *m, void *unused)
2959 {
2960         struct drm_info_node *node = m->private;
2961         struct drm_device *dev = node->minor->dev;
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         struct skl_ddb_allocation *ddb;
2964         struct skl_ddb_entry *entry;
2965         enum pipe pipe;
2966         int plane;
2967
2968         if (INTEL_INFO(dev)->gen < 9)
2969                 return 0;
2970
2971         drm_modeset_lock_all(dev);
2972
2973         ddb = &dev_priv->wm.skl_hw.ddb;
2974
2975         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2976
2977         for_each_pipe(dev_priv, pipe) {
2978                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2979
2980                 for_each_plane(dev_priv, pipe, plane) {
2981                         entry = &ddb->plane[pipe][plane];
2982                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2983                                    entry->start, entry->end,
2984                                    skl_ddb_entry_size(entry));
2985                 }
2986
2987                 entry = &ddb->cursor[pipe];
2988                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2989                            entry->end, skl_ddb_entry_size(entry));
2990         }
2991
2992         drm_modeset_unlock_all(dev);
2993
2994         return 0;
2995 }
2996
2997 static void drrs_status_per_crtc(struct seq_file *m,
2998                 struct drm_device *dev, struct intel_crtc *intel_crtc)
2999 {
3000         struct intel_encoder *intel_encoder;
3001         struct drm_i915_private *dev_priv = dev->dev_private;
3002         struct i915_drrs *drrs = &dev_priv->drrs;
3003         int vrefresh = 0;
3004
3005         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3006                 /* Encoder connected on this CRTC */
3007                 switch (intel_encoder->type) {
3008                 case INTEL_OUTPUT_EDP:
3009                         seq_puts(m, "eDP:\n");
3010                         break;
3011                 case INTEL_OUTPUT_DSI:
3012                         seq_puts(m, "DSI:\n");
3013                         break;
3014                 case INTEL_OUTPUT_HDMI:
3015                         seq_puts(m, "HDMI:\n");
3016                         break;
3017                 case INTEL_OUTPUT_DISPLAYPORT:
3018                         seq_puts(m, "DP:\n");
3019                         break;
3020                 default:
3021                         seq_printf(m, "Other encoder (id=%d).\n",
3022                                                 intel_encoder->type);
3023                         return;
3024                 }
3025         }
3026
3027         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3028                 seq_puts(m, "\tVBT: DRRS_type: Static");
3029         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3030                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3031         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3032                 seq_puts(m, "\tVBT: DRRS_type: None");
3033         else
3034                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3035
3036         seq_puts(m, "\n\n");
3037
3038         if (intel_crtc->config->has_drrs) {
3039                 struct intel_panel *panel;
3040
3041                 mutex_lock(&drrs->mutex);
3042                 /* DRRS Supported */
3043                 seq_puts(m, "\tDRRS Supported: Yes\n");
3044
3045                 /* disable_drrs() will make drrs->dp NULL */
3046                 if (!drrs->dp) {
3047                         seq_puts(m, "Idleness DRRS: Disabled");
3048                         mutex_unlock(&drrs->mutex);
3049                         return;
3050                 }
3051
3052                 panel = &drrs->dp->attached_connector->panel;
3053                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3054                                         drrs->busy_frontbuffer_bits);
3055
3056                 seq_puts(m, "\n\t\t");
3057                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3058                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3059                         vrefresh = panel->fixed_mode->vrefresh;
3060                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3061                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3062                         vrefresh = panel->downclock_mode->vrefresh;
3063                 } else {
3064                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3065                                                 drrs->refresh_rate_type);
3066                         mutex_unlock(&drrs->mutex);
3067                         return;
3068                 }
3069                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3070
3071                 seq_puts(m, "\n\t\t");
3072                 mutex_unlock(&drrs->mutex);
3073         } else {
3074                 /* DRRS not supported. Print the VBT parameter*/
3075                 seq_puts(m, "\tDRRS Supported : No");
3076         }
3077         seq_puts(m, "\n");
3078 }
3079
3080 static int i915_drrs_status(struct seq_file *m, void *unused)
3081 {
3082         struct drm_info_node *node = m->private;
3083         struct drm_device *dev = node->minor->dev;
3084         struct intel_crtc *intel_crtc;
3085         int active_crtc_cnt = 0;
3086
3087         for_each_intel_crtc(dev, intel_crtc) {
3088                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3089
3090                 if (intel_crtc->active) {
3091                         active_crtc_cnt++;
3092                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3093
3094                         drrs_status_per_crtc(m, dev, intel_crtc);
3095                 }
3096
3097                 drm_modeset_unlock(&intel_crtc->base.mutex);
3098         }
3099
3100         if (!active_crtc_cnt)
3101                 seq_puts(m, "No active crtc found\n");
3102
3103         return 0;
3104 }
3105
3106 struct pipe_crc_info {
3107         const char *name;
3108         struct drm_device *dev;
3109         enum pipe pipe;
3110 };
3111
3112 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3113 {
3114         struct drm_info_node *node = (struct drm_info_node *) m->private;
3115         struct drm_device *dev = node->minor->dev;
3116         struct drm_encoder *encoder;
3117         struct intel_encoder *intel_encoder;
3118         struct intel_digital_port *intel_dig_port;
3119         drm_modeset_lock_all(dev);
3120         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3121                 intel_encoder = to_intel_encoder(encoder);
3122                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3123                         continue;
3124                 intel_dig_port = enc_to_dig_port(encoder);
3125                 if (!intel_dig_port->dp.can_mst)
3126                         continue;
3127
3128                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3129         }
3130         drm_modeset_unlock_all(dev);
3131         return 0;
3132 }
3133
3134 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3135 {
3136         struct pipe_crc_info *info = inode->i_private;
3137         struct drm_i915_private *dev_priv = info->dev->dev_private;
3138         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3139
3140         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3141                 return -ENODEV;
3142
3143         spin_lock_irq(&pipe_crc->lock);
3144
3145         if (pipe_crc->opened) {
3146                 spin_unlock_irq(&pipe_crc->lock);
3147                 return -EBUSY; /* already open */
3148         }
3149
3150         pipe_crc->opened = true;
3151         filep->private_data = inode->i_private;
3152
3153         spin_unlock_irq(&pipe_crc->lock);
3154
3155         return 0;
3156 }
3157
3158 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3159 {
3160         struct pipe_crc_info *info = inode->i_private;
3161         struct drm_i915_private *dev_priv = info->dev->dev_private;
3162         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3163
3164         spin_lock_irq(&pipe_crc->lock);
3165         pipe_crc->opened = false;
3166         spin_unlock_irq(&pipe_crc->lock);
3167
3168         return 0;
3169 }
3170
3171 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3172 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3173 /* account for \'0' */
3174 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3175
3176 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3177 {
3178         assert_spin_locked(&pipe_crc->lock);
3179         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3180                         INTEL_PIPE_CRC_ENTRIES_NR);
3181 }
3182
3183 static ssize_t
3184 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3185                    loff_t *pos)
3186 {
3187         struct pipe_crc_info *info = filep->private_data;
3188         struct drm_device *dev = info->dev;
3189         struct drm_i915_private *dev_priv = dev->dev_private;
3190         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3191         char buf[PIPE_CRC_BUFFER_LEN];
3192         int n_entries;
3193         ssize_t bytes_read;
3194
3195         /*
3196          * Don't allow user space to provide buffers not big enough to hold
3197          * a line of data.
3198          */
3199         if (count < PIPE_CRC_LINE_LEN)
3200                 return -EINVAL;
3201
3202         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3203                 return 0;
3204
3205         /* nothing to read */
3206         spin_lock_irq(&pipe_crc->lock);
3207         while (pipe_crc_data_count(pipe_crc) == 0) {
3208                 int ret;
3209
3210                 if (filep->f_flags & O_NONBLOCK) {
3211                         spin_unlock_irq(&pipe_crc->lock);
3212                         return -EAGAIN;
3213                 }
3214
3215                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3216                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3217                 if (ret) {
3218                         spin_unlock_irq(&pipe_crc->lock);
3219                         return ret;
3220                 }
3221         }
3222
3223         /* We now have one or more entries to read */
3224         n_entries = count / PIPE_CRC_LINE_LEN;
3225
3226         bytes_read = 0;
3227         while (n_entries > 0) {
3228                 struct intel_pipe_crc_entry *entry =
3229                         &pipe_crc->entries[pipe_crc->tail];
3230                 int ret;
3231
3232                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3233                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3234                         break;
3235
3236                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3237                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3238
3239                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3240                                        "%8u %8x %8x %8x %8x %8x\n",
3241                                        entry->frame, entry->crc[0],
3242                                        entry->crc[1], entry->crc[2],
3243                                        entry->crc[3], entry->crc[4]);
3244
3245                 spin_unlock_irq(&pipe_crc->lock);
3246
3247                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3248                 if (ret == PIPE_CRC_LINE_LEN)
3249                         return -EFAULT;
3250
3251                 user_buf += PIPE_CRC_LINE_LEN;
3252                 n_entries--;
3253
3254                 spin_lock_irq(&pipe_crc->lock);
3255         }
3256
3257         spin_unlock_irq(&pipe_crc->lock);
3258
3259         return bytes_read;
3260 }
3261
3262 static const struct file_operations i915_pipe_crc_fops = {
3263         .owner = THIS_MODULE,
3264         .open = i915_pipe_crc_open,
3265         .read = i915_pipe_crc_read,
3266         .release = i915_pipe_crc_release,
3267 };
3268
3269 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3270         {
3271                 .name = "i915_pipe_A_crc",
3272                 .pipe = PIPE_A,
3273         },
3274         {
3275                 .name = "i915_pipe_B_crc",
3276                 .pipe = PIPE_B,
3277         },
3278         {
3279                 .name = "i915_pipe_C_crc",
3280                 .pipe = PIPE_C,
3281         },
3282 };
3283
3284 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3285                                 enum pipe pipe)
3286 {
3287         struct drm_device *dev = minor->dev;
3288         struct dentry *ent;
3289         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3290
3291         info->dev = dev;
3292         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3293                                   &i915_pipe_crc_fops);
3294         if (!ent)
3295                 return -ENOMEM;
3296
3297         return drm_add_fake_info_node(minor, ent, info);
3298 }
3299
3300 static const char * const pipe_crc_sources[] = {
3301         "none",
3302         "plane1",
3303         "plane2",
3304         "pf",
3305         "pipe",
3306         "TV",
3307         "DP-B",
3308         "DP-C",
3309         "DP-D",
3310         "auto",
3311 };
3312
3313 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3314 {
3315         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3316         return pipe_crc_sources[source];
3317 }
3318
3319 static int display_crc_ctl_show(struct seq_file *m, void *data)
3320 {
3321         struct drm_device *dev = m->private;
3322         struct drm_i915_private *dev_priv = dev->dev_private;
3323         int i;
3324
3325         for (i = 0; i < I915_MAX_PIPES; i++)
3326                 seq_printf(m, "%c %s\n", pipe_name(i),
3327                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3328
3329         return 0;
3330 }
3331
3332 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3333 {
3334         struct drm_device *dev = inode->i_private;
3335
3336         return single_open(file, display_crc_ctl_show, dev);
3337 }
3338
3339 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3340                                  uint32_t *val)
3341 {
3342         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3343                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3344
3345         switch (*source) {
3346         case INTEL_PIPE_CRC_SOURCE_PIPE:
3347                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3348                 break;
3349         case INTEL_PIPE_CRC_SOURCE_NONE:
3350                 *val = 0;
3351                 break;
3352         default:
3353                 return -EINVAL;
3354         }
3355
3356         return 0;
3357 }
3358
3359 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3360                                      enum intel_pipe_crc_source *source)
3361 {
3362         struct intel_encoder *encoder;
3363         struct intel_crtc *crtc;
3364         struct intel_digital_port *dig_port;
3365         int ret = 0;
3366
3367         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3368
3369         drm_modeset_lock_all(dev);
3370         for_each_intel_encoder(dev, encoder) {
3371                 if (!encoder->base.crtc)
3372                         continue;
3373
3374                 crtc = to_intel_crtc(encoder->base.crtc);
3375
3376                 if (crtc->pipe != pipe)
3377                         continue;
3378
3379                 switch (encoder->type) {
3380                 case INTEL_OUTPUT_TVOUT:
3381                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3382                         break;
3383                 case INTEL_OUTPUT_DISPLAYPORT:
3384                 case INTEL_OUTPUT_EDP:
3385                         dig_port = enc_to_dig_port(&encoder->base);
3386                         switch (dig_port->port) {
3387                         case PORT_B:
3388                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3389                                 break;
3390                         case PORT_C:
3391                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3392                                 break;
3393                         case PORT_D:
3394                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3395                                 break;
3396                         default:
3397                                 WARN(1, "nonexisting DP port %c\n",
3398                                      port_name(dig_port->port));
3399                                 break;
3400                         }
3401                         break;
3402                 default:
3403                         break;
3404                 }
3405         }
3406         drm_modeset_unlock_all(dev);
3407
3408         return ret;
3409 }
3410
3411 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3412                                 enum pipe pipe,
3413                                 enum intel_pipe_crc_source *source,
3414                                 uint32_t *val)
3415 {
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417         bool need_stable_symbols = false;
3418
3419         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3420                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3421                 if (ret)
3422                         return ret;
3423         }
3424
3425         switch (*source) {
3426         case INTEL_PIPE_CRC_SOURCE_PIPE:
3427                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3428                 break;
3429         case INTEL_PIPE_CRC_SOURCE_DP_B:
3430                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3431                 need_stable_symbols = true;
3432                 break;
3433         case INTEL_PIPE_CRC_SOURCE_DP_C:
3434                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3435                 need_stable_symbols = true;
3436                 break;
3437         case INTEL_PIPE_CRC_SOURCE_DP_D:
3438                 if (!IS_CHERRYVIEW(dev))
3439                         return -EINVAL;
3440                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3441                 need_stable_symbols = true;
3442                 break;
3443         case INTEL_PIPE_CRC_SOURCE_NONE:
3444                 *val = 0;
3445                 break;
3446         default:
3447                 return -EINVAL;
3448         }
3449
3450         /*
3451          * When the pipe CRC tap point is after the transcoders we need
3452          * to tweak symbol-level features to produce a deterministic series of
3453          * symbols for a given frame. We need to reset those features only once
3454          * a frame (instead of every nth symbol):
3455          *   - DC-balance: used to ensure a better clock recovery from the data
3456          *     link (SDVO)
3457          *   - DisplayPort scrambling: used for EMI reduction
3458          */
3459         if (need_stable_symbols) {
3460                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3461
3462                 tmp |= DC_BALANCE_RESET_VLV;
3463                 switch (pipe) {
3464                 case PIPE_A:
3465                         tmp |= PIPE_A_SCRAMBLE_RESET;
3466                         break;
3467                 case PIPE_B:
3468                         tmp |= PIPE_B_SCRAMBLE_RESET;
3469                         break;
3470                 case PIPE_C:
3471                         tmp |= PIPE_C_SCRAMBLE_RESET;
3472                         break;
3473                 default:
3474                         return -EINVAL;
3475                 }
3476                 I915_WRITE(PORT_DFT2_G4X, tmp);
3477         }
3478
3479         return 0;
3480 }
3481
3482 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3483                                  enum pipe pipe,
3484                                  enum intel_pipe_crc_source *source,
3485                                  uint32_t *val)
3486 {
3487         struct drm_i915_private *dev_priv = dev->dev_private;
3488         bool need_stable_symbols = false;
3489
3490         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3491                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3492                 if (ret)
3493                         return ret;
3494         }
3495
3496         switch (*source) {
3497         case INTEL_PIPE_CRC_SOURCE_PIPE:
3498                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3499                 break;
3500         case INTEL_PIPE_CRC_SOURCE_TV:
3501                 if (!SUPPORTS_TV(dev))
3502                         return -EINVAL;
3503                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3504                 break;
3505         case INTEL_PIPE_CRC_SOURCE_DP_B:
3506                 if (!IS_G4X(dev))
3507                         return -EINVAL;
3508                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3509                 need_stable_symbols = true;
3510                 break;
3511         case INTEL_PIPE_CRC_SOURCE_DP_C:
3512                 if (!IS_G4X(dev))
3513                         return -EINVAL;
3514                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3515                 need_stable_symbols = true;
3516                 break;
3517         case INTEL_PIPE_CRC_SOURCE_DP_D:
3518                 if (!IS_G4X(dev))
3519                         return -EINVAL;
3520                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3521                 need_stable_symbols = true;
3522                 break;
3523         case INTEL_PIPE_CRC_SOURCE_NONE:
3524                 *val = 0;
3525                 break;
3526         default:
3527                 return -EINVAL;
3528         }
3529
3530         /*
3531          * When the pipe CRC tap point is after the transcoders we need
3532          * to tweak symbol-level features to produce a deterministic series of
3533          * symbols for a given frame. We need to reset those features only once
3534          * a frame (instead of every nth symbol):
3535          *   - DC-balance: used to ensure a better clock recovery from the data
3536          *     link (SDVO)
3537          *   - DisplayPort scrambling: used for EMI reduction
3538          */
3539         if (need_stable_symbols) {
3540                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3541
3542                 WARN_ON(!IS_G4X(dev));
3543
3544                 I915_WRITE(PORT_DFT_I9XX,
3545                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3546
3547                 if (pipe == PIPE_A)
3548                         tmp |= PIPE_A_SCRAMBLE_RESET;
3549                 else
3550                         tmp |= PIPE_B_SCRAMBLE_RESET;
3551
3552                 I915_WRITE(PORT_DFT2_G4X, tmp);
3553         }
3554
3555         return 0;
3556 }
3557
3558 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3559                                          enum pipe pipe)
3560 {
3561         struct drm_i915_private *dev_priv = dev->dev_private;
3562         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3563
3564         switch (pipe) {
3565         case PIPE_A:
3566                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3567                 break;
3568         case PIPE_B:
3569                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3570                 break;
3571         case PIPE_C:
3572                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3573                 break;
3574         default:
3575                 return;
3576         }
3577         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3578                 tmp &= ~DC_BALANCE_RESET_VLV;
3579         I915_WRITE(PORT_DFT2_G4X, tmp);
3580
3581 }
3582
3583 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3584                                          enum pipe pipe)
3585 {
3586         struct drm_i915_private *dev_priv = dev->dev_private;
3587         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3588
3589         if (pipe == PIPE_A)
3590                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3591         else
3592                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3593         I915_WRITE(PORT_DFT2_G4X, tmp);
3594
3595         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3596                 I915_WRITE(PORT_DFT_I9XX,
3597                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3598         }
3599 }
3600
3601 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3602                                 uint32_t *val)
3603 {
3604         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3605                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3606
3607         switch (*source) {
3608         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3609                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3610                 break;
3611         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3612                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3613                 break;
3614         case INTEL_PIPE_CRC_SOURCE_PIPE:
3615                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3616                 break;
3617         case INTEL_PIPE_CRC_SOURCE_NONE:
3618                 *val = 0;
3619                 break;
3620         default:
3621                 return -EINVAL;
3622         }
3623
3624         return 0;
3625 }
3626
3627 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3628 {
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         struct intel_crtc *crtc =
3631                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3632
3633         drm_modeset_lock_all(dev);
3634         /*
3635          * If we use the eDP transcoder we need to make sure that we don't
3636          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3637          * relevant on hsw with pipe A when using the always-on power well
3638          * routing.
3639          */
3640         if (crtc->config->cpu_transcoder == TRANSCODER_EDP &&
3641             !crtc->config->pch_pfit.enabled) {
3642                 crtc->config->pch_pfit.force_thru = true;
3643
3644                 intel_display_power_get(dev_priv,
3645                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3646
3647                 intel_crtc_reset(crtc);
3648         }
3649         drm_modeset_unlock_all(dev);
3650 }
3651
3652 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3653 {
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_crtc *crtc =
3656                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3657
3658         drm_modeset_lock_all(dev);
3659         /*
3660          * If we use the eDP transcoder we need to make sure that we don't
3661          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3662          * relevant on hsw with pipe A when using the always-on power well
3663          * routing.
3664          */
3665         if (crtc->config->pch_pfit.force_thru) {
3666                 crtc->config->pch_pfit.force_thru = false;
3667
3668                 intel_crtc_reset(crtc);
3669
3670                 intel_display_power_put(dev_priv,
3671                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3672         }
3673         drm_modeset_unlock_all(dev);
3674 }
3675
3676 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3677                                 enum pipe pipe,
3678                                 enum intel_pipe_crc_source *source,
3679                                 uint32_t *val)
3680 {
3681         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3682                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3683
3684         switch (*source) {
3685         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3686                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3687                 break;
3688         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3689                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3690                 break;
3691         case INTEL_PIPE_CRC_SOURCE_PF:
3692                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3693                         hsw_trans_edp_pipe_A_crc_wa(dev);
3694
3695                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3696                 break;
3697         case INTEL_PIPE_CRC_SOURCE_NONE:
3698                 *val = 0;
3699                 break;
3700         default:
3701                 return -EINVAL;
3702         }
3703
3704         return 0;
3705 }
3706
3707 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3708                                enum intel_pipe_crc_source source)
3709 {
3710         struct drm_i915_private *dev_priv = dev->dev_private;
3711         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3712         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3713                                                                         pipe));
3714         u32 val = 0; /* shut up gcc */
3715         int ret;
3716
3717         if (pipe_crc->source == source)
3718                 return 0;
3719
3720         /* forbid changing the source without going back to 'none' */
3721         if (pipe_crc->source && source)
3722                 return -EINVAL;
3723
3724         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3725                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3726                 return -EIO;
3727         }
3728
3729         if (IS_GEN2(dev))
3730                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3731         else if (INTEL_INFO(dev)->gen < 5)
3732                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3733         else if (IS_VALLEYVIEW(dev))
3734                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3735         else if (IS_GEN5(dev) || IS_GEN6(dev))
3736                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3737         else
3738                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3739
3740         if (ret != 0)
3741                 return ret;
3742
3743         /* none -> real source transition */
3744         if (source) {
3745                 struct intel_pipe_crc_entry *entries;
3746
3747                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3748                                  pipe_name(pipe), pipe_crc_source_name(source));
3749
3750                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3751                                   sizeof(pipe_crc->entries[0]),
3752                                   GFP_KERNEL);
3753                 if (!entries)
3754                         return -ENOMEM;
3755
3756                 /*
3757                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3758                  * enabled and disabled dynamically based on package C states,
3759                  * user space can't make reliable use of the CRCs, so let's just
3760                  * completely disable it.
3761                  */
3762                 hsw_disable_ips(crtc);
3763
3764                 spin_lock_irq(&pipe_crc->lock);
3765                 kfree(pipe_crc->entries);
3766                 pipe_crc->entries = entries;
3767                 pipe_crc->head = 0;
3768                 pipe_crc->tail = 0;
3769                 spin_unlock_irq(&pipe_crc->lock);
3770         }
3771
3772         pipe_crc->source = source;
3773
3774         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3775         POSTING_READ(PIPE_CRC_CTL(pipe));
3776
3777         /* real source -> none transition */
3778         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3779                 struct intel_pipe_crc_entry *entries;
3780                 struct intel_crtc *crtc =
3781                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3782
3783                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3784                                  pipe_name(pipe));
3785
3786                 drm_modeset_lock(&crtc->base.mutex, NULL);
3787                 if (crtc->active)
3788                         intel_wait_for_vblank(dev, pipe);
3789                 drm_modeset_unlock(&crtc->base.mutex);
3790
3791                 spin_lock_irq(&pipe_crc->lock);
3792                 entries = pipe_crc->entries;
3793                 pipe_crc->entries = NULL;
3794                 pipe_crc->head = 0;
3795                 pipe_crc->tail = 0;
3796                 spin_unlock_irq(&pipe_crc->lock);
3797
3798                 kfree(entries);
3799
3800                 if (IS_G4X(dev))
3801                         g4x_undo_pipe_scramble_reset(dev, pipe);
3802                 else if (IS_VALLEYVIEW(dev))
3803                         vlv_undo_pipe_scramble_reset(dev, pipe);
3804                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3805                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3806
3807                 hsw_enable_ips(crtc);
3808         }
3809
3810         return 0;
3811 }
3812
3813 /*
3814  * Parse pipe CRC command strings:
3815  *   command: wsp* object wsp+ name wsp+ source wsp*
3816  *   object: 'pipe'
3817  *   name: (A | B | C)
3818  *   source: (none | plane1 | plane2 | pf)
3819  *   wsp: (#0x20 | #0x9 | #0xA)+
3820  *
3821  * eg.:
3822  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3823  *  "pipe A none"    ->  Stop CRC
3824  */
3825 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3826 {
3827         int n_words = 0;
3828
3829         while (*buf) {
3830                 char *end;
3831
3832                 /* skip leading white space */
3833                 buf = skip_spaces(buf);
3834                 if (!*buf)
3835                         break;  /* end of buffer */
3836
3837                 /* find end of word */
3838                 for (end = buf; *end && !isspace(*end); end++)
3839                         ;
3840
3841                 if (n_words == max_words) {
3842                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3843                                          max_words);
3844                         return -EINVAL; /* ran out of words[] before bytes */
3845                 }
3846
3847                 if (*end)
3848                         *end++ = '\0';
3849                 words[n_words++] = buf;
3850                 buf = end;
3851         }
3852
3853         return n_words;
3854 }
3855
3856 enum intel_pipe_crc_object {
3857         PIPE_CRC_OBJECT_PIPE,
3858 };
3859
3860 static const char * const pipe_crc_objects[] = {
3861         "pipe",
3862 };
3863
3864 static int
3865 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3866 {
3867         int i;
3868
3869         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3870                 if (!strcmp(buf, pipe_crc_objects[i])) {
3871                         *o = i;
3872                         return 0;
3873                     }
3874
3875         return -EINVAL;
3876 }
3877
3878 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3879 {
3880         const char name = buf[0];
3881
3882         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3883                 return -EINVAL;
3884
3885         *pipe = name - 'A';
3886
3887         return 0;
3888 }
3889
3890 static int
3891 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3892 {
3893         int i;
3894
3895         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3896                 if (!strcmp(buf, pipe_crc_sources[i])) {
3897                         *s = i;
3898                         return 0;
3899                     }
3900
3901         return -EINVAL;
3902 }
3903
3904 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3905 {
3906 #define N_WORDS 3
3907         int n_words;
3908         char *words[N_WORDS];
3909         enum pipe pipe;
3910         enum intel_pipe_crc_object object;
3911         enum intel_pipe_crc_source source;
3912
3913         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3914         if (n_words != N_WORDS) {
3915                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3916                                  N_WORDS);
3917                 return -EINVAL;
3918         }
3919
3920         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3921                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3922                 return -EINVAL;
3923         }
3924
3925         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3926                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3927                 return -EINVAL;
3928         }
3929
3930         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3931                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3932                 return -EINVAL;
3933         }
3934
3935         return pipe_crc_set_source(dev, pipe, source);
3936 }
3937
3938 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3939                                      size_t len, loff_t *offp)
3940 {
3941         struct seq_file *m = file->private_data;
3942         struct drm_device *dev = m->private;
3943         char *tmpbuf;
3944         int ret;
3945
3946         if (len == 0)
3947                 return 0;
3948
3949         if (len > PAGE_SIZE - 1) {
3950                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3951                                  PAGE_SIZE);
3952                 return -E2BIG;
3953         }
3954
3955         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3956         if (!tmpbuf)
3957                 return -ENOMEM;
3958
3959         if (copy_from_user(tmpbuf, ubuf, len)) {
3960                 ret = -EFAULT;
3961                 goto out;
3962         }
3963         tmpbuf[len] = '\0';
3964
3965         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3966
3967 out:
3968         kfree(tmpbuf);
3969         if (ret < 0)
3970                 return ret;
3971
3972         *offp += len;
3973         return len;
3974 }
3975
3976 static const struct file_operations i915_display_crc_ctl_fops = {
3977         .owner = THIS_MODULE,
3978         .open = display_crc_ctl_open,
3979         .read = seq_read,
3980         .llseek = seq_lseek,
3981         .release = single_release,
3982         .write = display_crc_ctl_write
3983 };
3984
3985 static ssize_t i915_displayport_test_active_write(struct file *file,
3986                                             const char __user *ubuf,
3987                                             size_t len, loff_t *offp)
3988 {
3989         char *input_buffer;
3990         int status = 0;
3991         struct seq_file *m;
3992         struct drm_device *dev;
3993         struct drm_connector *connector;
3994         struct list_head *connector_list;
3995         struct intel_dp *intel_dp;
3996         int val = 0;
3997
3998         m = file->private_data;
3999         if (!m) {
4000                 status = -ENODEV;
4001                 return status;
4002         }
4003         dev = m->private;
4004
4005         if (!dev) {
4006                 status = -ENODEV;
4007                 return status;
4008         }
4009         connector_list = &dev->mode_config.connector_list;
4010
4011         if (len == 0)
4012                 return 0;
4013
4014         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4015         if (!input_buffer)
4016                 return -ENOMEM;
4017
4018         if (copy_from_user(input_buffer, ubuf, len)) {
4019                 status = -EFAULT;
4020                 goto out;
4021         }
4022
4023         input_buffer[len] = '\0';
4024         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4025
4026         list_for_each_entry(connector, connector_list, head) {
4027
4028                 if (connector->connector_type !=
4029                     DRM_MODE_CONNECTOR_DisplayPort)
4030                         continue;
4031
4032                 if (connector->connector_type ==
4033                     DRM_MODE_CONNECTOR_DisplayPort &&
4034                     connector->status == connector_status_connected &&
4035                     connector->encoder != NULL) {
4036                         intel_dp = enc_to_intel_dp(connector->encoder);
4037                         status = kstrtoint(input_buffer, 10, &val);
4038                         if (status < 0)
4039                                 goto out;
4040                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4041                         /* To prevent erroneous activation of the compliance
4042                          * testing code, only accept an actual value of 1 here
4043                          */
4044                         if (val == 1)
4045                                 intel_dp->compliance_test_active = 1;
4046                         else
4047                                 intel_dp->compliance_test_active = 0;
4048                 }
4049         }
4050 out:
4051         kfree(input_buffer);
4052         if (status < 0)
4053                 return status;
4054
4055         *offp += len;
4056         return len;
4057 }
4058
4059 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4060 {
4061         struct drm_device *dev = m->private;
4062         struct drm_connector *connector;
4063         struct list_head *connector_list = &dev->mode_config.connector_list;
4064         struct intel_dp *intel_dp;
4065
4066         if (!dev)
4067                 return -ENODEV;
4068
4069         list_for_each_entry(connector, connector_list, head) {
4070
4071                 if (connector->connector_type !=
4072                     DRM_MODE_CONNECTOR_DisplayPort)
4073                         continue;
4074
4075                 if (connector->status == connector_status_connected &&
4076                     connector->encoder != NULL) {
4077                         intel_dp = enc_to_intel_dp(connector->encoder);
4078                         if (intel_dp->compliance_test_active)
4079                                 seq_puts(m, "1");
4080                         else
4081                                 seq_puts(m, "0");
4082                 } else
4083                         seq_puts(m, "0");
4084         }
4085
4086         return 0;
4087 }
4088
4089 static int i915_displayport_test_active_open(struct inode *inode,
4090                                        struct file *file)
4091 {
4092         struct drm_device *dev = inode->i_private;
4093
4094         return single_open(file, i915_displayport_test_active_show, dev);
4095 }
4096
4097 static const struct file_operations i915_displayport_test_active_fops = {
4098         .owner = THIS_MODULE,
4099         .open = i915_displayport_test_active_open,
4100         .read = seq_read,
4101         .llseek = seq_lseek,
4102         .release = single_release,
4103         .write = i915_displayport_test_active_write
4104 };
4105
4106 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4107 {
4108         struct drm_device *dev = m->private;
4109         struct drm_connector *connector;
4110         struct list_head *connector_list = &dev->mode_config.connector_list;
4111         struct intel_dp *intel_dp;
4112
4113         if (!dev)
4114                 return -ENODEV;
4115
4116         list_for_each_entry(connector, connector_list, head) {
4117
4118                 if (connector->connector_type !=
4119                     DRM_MODE_CONNECTOR_DisplayPort)
4120                         continue;
4121
4122                 if (connector->status == connector_status_connected &&
4123                     connector->encoder != NULL) {
4124                         intel_dp = enc_to_intel_dp(connector->encoder);
4125                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4126                 } else
4127                         seq_puts(m, "0");
4128         }
4129
4130         return 0;
4131 }
4132 static int i915_displayport_test_data_open(struct inode *inode,
4133                                        struct file *file)
4134 {
4135         struct drm_device *dev = inode->i_private;
4136
4137         return single_open(file, i915_displayport_test_data_show, dev);
4138 }
4139
4140 static const struct file_operations i915_displayport_test_data_fops = {
4141         .owner = THIS_MODULE,
4142         .open = i915_displayport_test_data_open,
4143         .read = seq_read,
4144         .llseek = seq_lseek,
4145         .release = single_release
4146 };
4147
4148 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4149 {
4150         struct drm_device *dev = m->private;
4151         struct drm_connector *connector;
4152         struct list_head *connector_list = &dev->mode_config.connector_list;
4153         struct intel_dp *intel_dp;
4154
4155         if (!dev)
4156                 return -ENODEV;
4157
4158         list_for_each_entry(connector, connector_list, head) {
4159
4160                 if (connector->connector_type !=
4161                     DRM_MODE_CONNECTOR_DisplayPort)
4162                         continue;
4163
4164                 if (connector->status == connector_status_connected &&
4165                     connector->encoder != NULL) {
4166                         intel_dp = enc_to_intel_dp(connector->encoder);
4167                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4168                 } else
4169                         seq_puts(m, "0");
4170         }
4171
4172         return 0;
4173 }
4174
4175 static int i915_displayport_test_type_open(struct inode *inode,
4176                                        struct file *file)
4177 {
4178         struct drm_device *dev = inode->i_private;
4179
4180         return single_open(file, i915_displayport_test_type_show, dev);
4181 }
4182
4183 static const struct file_operations i915_displayport_test_type_fops = {
4184         .owner = THIS_MODULE,
4185         .open = i915_displayport_test_type_open,
4186         .read = seq_read,
4187         .llseek = seq_lseek,
4188         .release = single_release
4189 };
4190
4191 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4192 {
4193         struct drm_device *dev = m->private;
4194         int num_levels = ilk_wm_max_level(dev) + 1;
4195         int level;
4196
4197         drm_modeset_lock_all(dev);
4198
4199         for (level = 0; level < num_levels; level++) {
4200                 unsigned int latency = wm[level];
4201
4202                 /*
4203                  * - WM1+ latency values in 0.5us units
4204                  * - latencies are in us on gen9
4205                  */
4206                 if (INTEL_INFO(dev)->gen >= 9)
4207                         latency *= 10;
4208                 else if (level > 0)
4209                         latency *= 5;
4210
4211                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4212                            level, wm[level], latency / 10, latency % 10);
4213         }
4214
4215         drm_modeset_unlock_all(dev);
4216 }
4217
4218 static int pri_wm_latency_show(struct seq_file *m, void *data)
4219 {
4220         struct drm_device *dev = m->private;
4221         struct drm_i915_private *dev_priv = dev->dev_private;
4222         const uint16_t *latencies;
4223
4224         if (INTEL_INFO(dev)->gen >= 9)
4225                 latencies = dev_priv->wm.skl_latency;
4226         else
4227                 latencies = to_i915(dev)->wm.pri_latency;
4228
4229         wm_latency_show(m, latencies);
4230
4231         return 0;
4232 }
4233
4234 static int spr_wm_latency_show(struct seq_file *m, void *data)
4235 {
4236         struct drm_device *dev = m->private;
4237         struct drm_i915_private *dev_priv = dev->dev_private;
4238         const uint16_t *latencies;
4239
4240         if (INTEL_INFO(dev)->gen >= 9)
4241                 latencies = dev_priv->wm.skl_latency;
4242         else
4243                 latencies = to_i915(dev)->wm.spr_latency;
4244
4245         wm_latency_show(m, latencies);
4246
4247         return 0;
4248 }
4249
4250 static int cur_wm_latency_show(struct seq_file *m, void *data)
4251 {
4252         struct drm_device *dev = m->private;
4253         struct drm_i915_private *dev_priv = dev->dev_private;
4254         const uint16_t *latencies;
4255
4256         if (INTEL_INFO(dev)->gen >= 9)
4257                 latencies = dev_priv->wm.skl_latency;
4258         else
4259                 latencies = to_i915(dev)->wm.cur_latency;
4260
4261         wm_latency_show(m, latencies);
4262
4263         return 0;
4264 }
4265
4266 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4267 {
4268         struct drm_device *dev = inode->i_private;
4269
4270         if (HAS_GMCH_DISPLAY(dev))
4271                 return -ENODEV;
4272
4273         return single_open(file, pri_wm_latency_show, dev);
4274 }
4275
4276 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4277 {
4278         struct drm_device *dev = inode->i_private;
4279
4280         if (HAS_GMCH_DISPLAY(dev))
4281                 return -ENODEV;
4282
4283         return single_open(file, spr_wm_latency_show, dev);
4284 }
4285
4286 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4287 {
4288         struct drm_device *dev = inode->i_private;
4289
4290         if (HAS_GMCH_DISPLAY(dev))
4291                 return -ENODEV;
4292
4293         return single_open(file, cur_wm_latency_show, dev);
4294 }
4295
4296 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4297                                 size_t len, loff_t *offp, uint16_t wm[8])
4298 {
4299         struct seq_file *m = file->private_data;
4300         struct drm_device *dev = m->private;
4301         uint16_t new[8] = { 0 };
4302         int num_levels = ilk_wm_max_level(dev) + 1;
4303         int level;
4304         int ret;
4305         char tmp[32];
4306
4307         if (len >= sizeof(tmp))
4308                 return -EINVAL;
4309
4310         if (copy_from_user(tmp, ubuf, len))
4311                 return -EFAULT;
4312
4313         tmp[len] = '\0';
4314
4315         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4316                      &new[0], &new[1], &new[2], &new[3],
4317                      &new[4], &new[5], &new[6], &new[7]);
4318         if (ret != num_levels)
4319                 return -EINVAL;
4320
4321         drm_modeset_lock_all(dev);
4322
4323         for (level = 0; level < num_levels; level++)
4324                 wm[level] = new[level];
4325
4326         drm_modeset_unlock_all(dev);
4327
4328         return len;
4329 }
4330
4331
4332 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4333                                     size_t len, loff_t *offp)
4334 {
4335         struct seq_file *m = file->private_data;
4336         struct drm_device *dev = m->private;
4337         struct drm_i915_private *dev_priv = dev->dev_private;
4338         uint16_t *latencies;
4339
4340         if (INTEL_INFO(dev)->gen >= 9)
4341                 latencies = dev_priv->wm.skl_latency;
4342         else
4343                 latencies = to_i915(dev)->wm.pri_latency;
4344
4345         return wm_latency_write(file, ubuf, len, offp, latencies);
4346 }
4347
4348 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4349                                     size_t len, loff_t *offp)
4350 {
4351         struct seq_file *m = file->private_data;
4352         struct drm_device *dev = m->private;
4353         struct drm_i915_private *dev_priv = dev->dev_private;
4354         uint16_t *latencies;
4355
4356         if (INTEL_INFO(dev)->gen >= 9)
4357                 latencies = dev_priv->wm.skl_latency;
4358         else
4359                 latencies = to_i915(dev)->wm.spr_latency;
4360
4361         return wm_latency_write(file, ubuf, len, offp, latencies);
4362 }
4363
4364 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4365                                     size_t len, loff_t *offp)
4366 {
4367         struct seq_file *m = file->private_data;
4368         struct drm_device *dev = m->private;
4369         struct drm_i915_private *dev_priv = dev->dev_private;
4370         uint16_t *latencies;
4371
4372         if (INTEL_INFO(dev)->gen >= 9)
4373                 latencies = dev_priv->wm.skl_latency;
4374         else
4375                 latencies = to_i915(dev)->wm.cur_latency;
4376
4377         return wm_latency_write(file, ubuf, len, offp, latencies);
4378 }
4379
4380 static const struct file_operations i915_pri_wm_latency_fops = {
4381         .owner = THIS_MODULE,
4382         .open = pri_wm_latency_open,
4383         .read = seq_read,
4384         .llseek = seq_lseek,
4385         .release = single_release,
4386         .write = pri_wm_latency_write
4387 };
4388
4389 static const struct file_operations i915_spr_wm_latency_fops = {
4390         .owner = THIS_MODULE,
4391         .open = spr_wm_latency_open,
4392         .read = seq_read,
4393         .llseek = seq_lseek,
4394         .release = single_release,
4395         .write = spr_wm_latency_write
4396 };
4397
4398 static const struct file_operations i915_cur_wm_latency_fops = {
4399         .owner = THIS_MODULE,
4400         .open = cur_wm_latency_open,
4401         .read = seq_read,
4402         .llseek = seq_lseek,
4403         .release = single_release,
4404         .write = cur_wm_latency_write
4405 };
4406
4407 static int
4408 i915_wedged_get(void *data, u64 *val)
4409 {
4410         struct drm_device *dev = data;
4411         struct drm_i915_private *dev_priv = dev->dev_private;
4412
4413         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4414
4415         return 0;
4416 }
4417
4418 static int
4419 i915_wedged_set(void *data, u64 val)
4420 {
4421         struct drm_device *dev = data;
4422         struct drm_i915_private *dev_priv = dev->dev_private;
4423
4424         /*
4425          * There is no safeguard against this debugfs entry colliding
4426          * with the hangcheck calling same i915_handle_error() in
4427          * parallel, causing an explosion. For now we assume that the
4428          * test harness is responsible enough not to inject gpu hangs
4429          * while it is writing to 'i915_wedged'
4430          */
4431
4432         if (i915_reset_in_progress(&dev_priv->gpu_error))
4433                 return -EAGAIN;
4434
4435         intel_runtime_pm_get(dev_priv);
4436
4437         i915_handle_error(dev, val,
4438                           "Manually setting wedged to %llu", val);
4439
4440         intel_runtime_pm_put(dev_priv);
4441
4442         return 0;
4443 }
4444
4445 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4446                         i915_wedged_get, i915_wedged_set,
4447                         "%llu\n");
4448
4449 static int
4450 i915_ring_stop_get(void *data, u64 *val)
4451 {
4452         struct drm_device *dev = data;
4453         struct drm_i915_private *dev_priv = dev->dev_private;
4454
4455         *val = dev_priv->gpu_error.stop_rings;
4456
4457         return 0;
4458 }
4459
4460 static int
4461 i915_ring_stop_set(void *data, u64 val)
4462 {
4463         struct drm_device *dev = data;
4464         struct drm_i915_private *dev_priv = dev->dev_private;
4465         int ret;
4466
4467         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4468
4469         ret = mutex_lock_interruptible(&dev->struct_mutex);
4470         if (ret)
4471                 return ret;
4472
4473         dev_priv->gpu_error.stop_rings = val;
4474         mutex_unlock(&dev->struct_mutex);
4475
4476         return 0;
4477 }
4478
4479 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4480                         i915_ring_stop_get, i915_ring_stop_set,
4481                         "0x%08llx\n");
4482
4483 static int
4484 i915_ring_missed_irq_get(void *data, u64 *val)
4485 {
4486         struct drm_device *dev = data;
4487         struct drm_i915_private *dev_priv = dev->dev_private;
4488
4489         *val = dev_priv->gpu_error.missed_irq_rings;
4490         return 0;
4491 }
4492
4493 static int
4494 i915_ring_missed_irq_set(void *data, u64 val)
4495 {
4496         struct drm_device *dev = data;
4497         struct drm_i915_private *dev_priv = dev->dev_private;
4498         int ret;
4499
4500         /* Lock against concurrent debugfs callers */
4501         ret = mutex_lock_interruptible(&dev->struct_mutex);
4502         if (ret)
4503                 return ret;
4504         dev_priv->gpu_error.missed_irq_rings = val;
4505         mutex_unlock(&dev->struct_mutex);
4506
4507         return 0;
4508 }
4509
4510 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4511                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4512                         "0x%08llx\n");
4513
4514 static int
4515 i915_ring_test_irq_get(void *data, u64 *val)
4516 {
4517         struct drm_device *dev = data;
4518         struct drm_i915_private *dev_priv = dev->dev_private;
4519
4520         *val = dev_priv->gpu_error.test_irq_rings;
4521
4522         return 0;
4523 }
4524
4525 static int
4526 i915_ring_test_irq_set(void *data, u64 val)
4527 {
4528         struct drm_device *dev = data;
4529         struct drm_i915_private *dev_priv = dev->dev_private;
4530         int ret;
4531
4532         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4533
4534         /* Lock against concurrent debugfs callers */
4535         ret = mutex_lock_interruptible(&dev->struct_mutex);
4536         if (ret)
4537                 return ret;
4538
4539         dev_priv->gpu_error.test_irq_rings = val;
4540         mutex_unlock(&dev->struct_mutex);
4541
4542         return 0;
4543 }
4544
4545 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4546                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4547                         "0x%08llx\n");
4548
4549 #define DROP_UNBOUND 0x1
4550 #define DROP_BOUND 0x2
4551 #define DROP_RETIRE 0x4
4552 #define DROP_ACTIVE 0x8
4553 #define DROP_ALL (DROP_UNBOUND | \
4554                   DROP_BOUND | \
4555                   DROP_RETIRE | \
4556                   DROP_ACTIVE)
4557 static int
4558 i915_drop_caches_get(void *data, u64 *val)
4559 {
4560         *val = DROP_ALL;
4561
4562         return 0;
4563 }
4564
4565 static int
4566 i915_drop_caches_set(void *data, u64 val)
4567 {
4568         struct drm_device *dev = data;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         int ret;
4571
4572         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4573
4574         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4575          * on ioctls on -EAGAIN. */
4576         ret = mutex_lock_interruptible(&dev->struct_mutex);
4577         if (ret)
4578                 return ret;
4579
4580         if (val & DROP_ACTIVE) {
4581                 ret = i915_gpu_idle(dev);
4582                 if (ret)
4583                         goto unlock;
4584         }
4585
4586         if (val & (DROP_RETIRE | DROP_ACTIVE))
4587                 i915_gem_retire_requests(dev);
4588
4589         if (val & DROP_BOUND)
4590                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4591
4592         if (val & DROP_UNBOUND)
4593                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4594
4595 unlock:
4596         mutex_unlock(&dev->struct_mutex);
4597
4598         return ret;
4599 }
4600
4601 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4602                         i915_drop_caches_get, i915_drop_caches_set,
4603                         "0x%08llx\n");
4604
4605 static int
4606 i915_max_freq_get(void *data, u64 *val)
4607 {
4608         struct drm_device *dev = data;
4609         struct drm_i915_private *dev_priv = dev->dev_private;
4610         int ret;
4611
4612         if (INTEL_INFO(dev)->gen < 6)
4613                 return -ENODEV;
4614
4615         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4616
4617         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4618         if (ret)
4619                 return ret;
4620
4621         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4622         mutex_unlock(&dev_priv->rps.hw_lock);
4623
4624         return 0;
4625 }
4626
4627 static int
4628 i915_max_freq_set(void *data, u64 val)
4629 {
4630         struct drm_device *dev = data;
4631         struct drm_i915_private *dev_priv = dev->dev_private;
4632         u32 hw_max, hw_min;
4633         int ret;
4634
4635         if (INTEL_INFO(dev)->gen < 6)
4636                 return -ENODEV;
4637
4638         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4639
4640         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4641
4642         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4643         if (ret)
4644                 return ret;
4645
4646         /*
4647          * Turbo will still be enabled, but won't go above the set value.
4648          */
4649         val = intel_freq_opcode(dev_priv, val);
4650
4651         hw_max = dev_priv->rps.max_freq;
4652         hw_min = dev_priv->rps.min_freq;
4653
4654         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4655                 mutex_unlock(&dev_priv->rps.hw_lock);
4656                 return -EINVAL;
4657         }
4658
4659         dev_priv->rps.max_freq_softlimit = val;
4660
4661         intel_set_rps(dev, val);
4662
4663         mutex_unlock(&dev_priv->rps.hw_lock);
4664
4665         return 0;
4666 }
4667
4668 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4669                         i915_max_freq_get, i915_max_freq_set,
4670                         "%llu\n");
4671
4672 static int
4673 i915_min_freq_get(void *data, u64 *val)
4674 {
4675         struct drm_device *dev = data;
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677         int ret;
4678
4679         if (INTEL_INFO(dev)->gen < 6)
4680                 return -ENODEV;
4681
4682         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4683
4684         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4685         if (ret)
4686                 return ret;
4687
4688         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4689         mutex_unlock(&dev_priv->rps.hw_lock);
4690
4691         return 0;
4692 }
4693
4694 static int
4695 i915_min_freq_set(void *data, u64 val)
4696 {
4697         struct drm_device *dev = data;
4698         struct drm_i915_private *dev_priv = dev->dev_private;
4699         u32 hw_max, hw_min;
4700         int ret;
4701
4702         if (INTEL_INFO(dev)->gen < 6)
4703                 return -ENODEV;
4704
4705         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4706
4707         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4708
4709         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4710         if (ret)
4711                 return ret;
4712
4713         /*
4714          * Turbo will still be enabled, but won't go below the set value.
4715          */
4716         val = intel_freq_opcode(dev_priv, val);
4717
4718         hw_max = dev_priv->rps.max_freq;
4719         hw_min = dev_priv->rps.min_freq;
4720
4721         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4722                 mutex_unlock(&dev_priv->rps.hw_lock);
4723                 return -EINVAL;
4724         }
4725
4726         dev_priv->rps.min_freq_softlimit = val;
4727
4728         intel_set_rps(dev, val);
4729
4730         mutex_unlock(&dev_priv->rps.hw_lock);
4731
4732         return 0;
4733 }
4734
4735 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4736                         i915_min_freq_get, i915_min_freq_set,
4737                         "%llu\n");
4738
4739 static int
4740 i915_cache_sharing_get(void *data, u64 *val)
4741 {
4742         struct drm_device *dev = data;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         u32 snpcr;
4745         int ret;
4746
4747         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4748                 return -ENODEV;
4749
4750         ret = mutex_lock_interruptible(&dev->struct_mutex);
4751         if (ret)
4752                 return ret;
4753         intel_runtime_pm_get(dev_priv);
4754
4755         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4756
4757         intel_runtime_pm_put(dev_priv);
4758         mutex_unlock(&dev_priv->dev->struct_mutex);
4759
4760         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4761
4762         return 0;
4763 }
4764
4765 static int
4766 i915_cache_sharing_set(void *data, u64 val)
4767 {
4768         struct drm_device *dev = data;
4769         struct drm_i915_private *dev_priv = dev->dev_private;
4770         u32 snpcr;
4771
4772         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4773                 return -ENODEV;
4774
4775         if (val > 3)
4776                 return -EINVAL;
4777
4778         intel_runtime_pm_get(dev_priv);
4779         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4780
4781         /* Update the cache sharing policy here as well */
4782         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4783         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4784         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4785         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4786
4787         intel_runtime_pm_put(dev_priv);
4788         return 0;
4789 }
4790
4791 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4792                         i915_cache_sharing_get, i915_cache_sharing_set,
4793                         "%llu\n");
4794
4795 struct sseu_dev_status {
4796         unsigned int slice_total;
4797         unsigned int subslice_total;
4798         unsigned int subslice_per_slice;
4799         unsigned int eu_total;
4800         unsigned int eu_per_subslice;
4801 };
4802
4803 static void cherryview_sseu_device_status(struct drm_device *dev,
4804                                           struct sseu_dev_status *stat)
4805 {
4806         struct drm_i915_private *dev_priv = dev->dev_private;
4807         const int ss_max = 2;
4808         int ss;
4809         u32 sig1[ss_max], sig2[ss_max];
4810
4811         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4812         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4813         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4814         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4815
4816         for (ss = 0; ss < ss_max; ss++) {
4817                 unsigned int eu_cnt;
4818
4819                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4820                         /* skip disabled subslice */
4821                         continue;
4822
4823                 stat->slice_total = 1;
4824                 stat->subslice_per_slice++;
4825                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4826                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4827                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4828                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4829                 stat->eu_total += eu_cnt;
4830                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4831         }
4832         stat->subslice_total = stat->subslice_per_slice;
4833 }
4834
4835 static void gen9_sseu_device_status(struct drm_device *dev,
4836                                     struct sseu_dev_status *stat)
4837 {
4838         struct drm_i915_private *dev_priv = dev->dev_private;
4839         int s_max = 3, ss_max = 4;
4840         int s, ss;
4841         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4842
4843         /* BXT has a single slice and at most 3 subslices. */
4844         if (IS_BROXTON(dev)) {
4845                 s_max = 1;
4846                 ss_max = 3;
4847         }
4848
4849         for (s = 0; s < s_max; s++) {
4850                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4851                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4852                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4853         }
4854
4855         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4856                      GEN9_PGCTL_SSA_EU19_ACK |
4857                      GEN9_PGCTL_SSA_EU210_ACK |
4858                      GEN9_PGCTL_SSA_EU311_ACK;
4859         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4860                      GEN9_PGCTL_SSB_EU19_ACK |
4861                      GEN9_PGCTL_SSB_EU210_ACK |
4862                      GEN9_PGCTL_SSB_EU311_ACK;
4863
4864         for (s = 0; s < s_max; s++) {
4865                 unsigned int ss_cnt = 0;
4866
4867                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4868                         /* skip disabled slice */
4869                         continue;
4870
4871                 stat->slice_total++;
4872
4873                 if (IS_SKYLAKE(dev))
4874                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4875
4876                 for (ss = 0; ss < ss_max; ss++) {
4877                         unsigned int eu_cnt;
4878
4879                         if (IS_BROXTON(dev) &&
4880                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4881                                 /* skip disabled subslice */
4882                                 continue;
4883
4884                         if (IS_BROXTON(dev))
4885                                 ss_cnt++;
4886
4887                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4888                                                eu_mask[ss%2]);
4889                         stat->eu_total += eu_cnt;
4890                         stat->eu_per_subslice = max(stat->eu_per_subslice,
4891                                                     eu_cnt);
4892                 }
4893
4894                 stat->subslice_total += ss_cnt;
4895                 stat->subslice_per_slice = max(stat->subslice_per_slice,
4896                                                ss_cnt);
4897         }
4898 }
4899
4900 static int i915_sseu_status(struct seq_file *m, void *unused)
4901 {
4902         struct drm_info_node *node = (struct drm_info_node *) m->private;
4903         struct drm_device *dev = node->minor->dev;
4904         struct sseu_dev_status stat;
4905
4906         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4907                 return -ENODEV;
4908
4909         seq_puts(m, "SSEU Device Info\n");
4910         seq_printf(m, "  Available Slice Total: %u\n",
4911                    INTEL_INFO(dev)->slice_total);
4912         seq_printf(m, "  Available Subslice Total: %u\n",
4913                    INTEL_INFO(dev)->subslice_total);
4914         seq_printf(m, "  Available Subslice Per Slice: %u\n",
4915                    INTEL_INFO(dev)->subslice_per_slice);
4916         seq_printf(m, "  Available EU Total: %u\n",
4917                    INTEL_INFO(dev)->eu_total);
4918         seq_printf(m, "  Available EU Per Subslice: %u\n",
4919                    INTEL_INFO(dev)->eu_per_subslice);
4920         seq_printf(m, "  Has Slice Power Gating: %s\n",
4921                    yesno(INTEL_INFO(dev)->has_slice_pg));
4922         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4923                    yesno(INTEL_INFO(dev)->has_subslice_pg));
4924         seq_printf(m, "  Has EU Power Gating: %s\n",
4925                    yesno(INTEL_INFO(dev)->has_eu_pg));
4926
4927         seq_puts(m, "SSEU Device Status\n");
4928         memset(&stat, 0, sizeof(stat));
4929         if (IS_CHERRYVIEW(dev)) {
4930                 cherryview_sseu_device_status(dev, &stat);
4931         } else if (INTEL_INFO(dev)->gen >= 9) {
4932                 gen9_sseu_device_status(dev, &stat);
4933         }
4934         seq_printf(m, "  Enabled Slice Total: %u\n",
4935                    stat.slice_total);
4936         seq_printf(m, "  Enabled Subslice Total: %u\n",
4937                    stat.subslice_total);
4938         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
4939                    stat.subslice_per_slice);
4940         seq_printf(m, "  Enabled EU Total: %u\n",
4941                    stat.eu_total);
4942         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
4943                    stat.eu_per_subslice);
4944
4945         return 0;
4946 }
4947
4948 static int i915_forcewake_open(struct inode *inode, struct file *file)
4949 {
4950         struct drm_device *dev = inode->i_private;
4951         struct drm_i915_private *dev_priv = dev->dev_private;
4952
4953         if (INTEL_INFO(dev)->gen < 6)
4954                 return 0;
4955
4956         intel_runtime_pm_get(dev_priv);
4957         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4958
4959         return 0;
4960 }
4961
4962 static int i915_forcewake_release(struct inode *inode, struct file *file)
4963 {
4964         struct drm_device *dev = inode->i_private;
4965         struct drm_i915_private *dev_priv = dev->dev_private;
4966
4967         if (INTEL_INFO(dev)->gen < 6)
4968                 return 0;
4969
4970         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4971         intel_runtime_pm_put(dev_priv);
4972
4973         return 0;
4974 }
4975
4976 static const struct file_operations i915_forcewake_fops = {
4977         .owner = THIS_MODULE,
4978         .open = i915_forcewake_open,
4979         .release = i915_forcewake_release,
4980 };
4981
4982 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
4983 {
4984         struct drm_device *dev = minor->dev;
4985         struct dentry *ent;
4986
4987         ent = debugfs_create_file("i915_forcewake_user",
4988                                   S_IRUSR,
4989                                   root, dev,
4990                                   &i915_forcewake_fops);
4991         if (!ent)
4992                 return -ENOMEM;
4993
4994         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
4995 }
4996
4997 static int i915_debugfs_create(struct dentry *root,
4998                                struct drm_minor *minor,
4999                                const char *name,
5000                                const struct file_operations *fops)
5001 {
5002         struct drm_device *dev = minor->dev;
5003         struct dentry *ent;
5004
5005         ent = debugfs_create_file(name,
5006                                   S_IRUGO | S_IWUSR,
5007                                   root, dev,
5008                                   fops);
5009         if (!ent)
5010                 return -ENOMEM;
5011
5012         return drm_add_fake_info_node(minor, ent, fops);
5013 }
5014
5015 static const struct drm_info_list i915_debugfs_list[] = {
5016         {"i915_capabilities", i915_capabilities, 0},
5017         {"i915_gem_objects", i915_gem_object_info, 0},
5018         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5019         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5020         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5021         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5022         {"i915_gem_stolen", i915_gem_stolen_list_info },
5023         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5024         {"i915_gem_request", i915_gem_request_info, 0},
5025         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5026         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5027         {"i915_gem_interrupt", i915_interrupt_info, 0},
5028         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5029         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5030         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5031         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5032         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5033         {"i915_frequency_info", i915_frequency_info, 0},
5034         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5035         {"i915_drpc_info", i915_drpc_info, 0},
5036         {"i915_emon_status", i915_emon_status, 0},
5037         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5038         {"i915_fbc_status", i915_fbc_status, 0},
5039         {"i915_ips_status", i915_ips_status, 0},
5040         {"i915_sr_status", i915_sr_status, 0},
5041         {"i915_opregion", i915_opregion, 0},
5042         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5043         {"i915_context_status", i915_context_status, 0},
5044         {"i915_dump_lrc", i915_dump_lrc, 0},
5045         {"i915_execlists", i915_execlists, 0},
5046         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5047         {"i915_swizzle_info", i915_swizzle_info, 0},
5048         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5049         {"i915_llc", i915_llc, 0},
5050         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5051         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5052         {"i915_energy_uJ", i915_energy_uJ, 0},
5053         {"i915_pc8_status", i915_pc8_status, 0},
5054         {"i915_power_domain_info", i915_power_domain_info, 0},
5055         {"i915_display_info", i915_display_info, 0},
5056         {"i915_semaphore_status", i915_semaphore_status, 0},
5057         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5058         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5059         {"i915_wa_registers", i915_wa_registers, 0},
5060         {"i915_ddb_info", i915_ddb_info, 0},
5061         {"i915_sseu_status", i915_sseu_status, 0},
5062         {"i915_drrs_status", i915_drrs_status, 0},
5063         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5064 };
5065 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5066
5067 static const struct i915_debugfs_files {
5068         const char *name;
5069         const struct file_operations *fops;
5070 } i915_debugfs_files[] = {
5071         {"i915_wedged", &i915_wedged_fops},
5072         {"i915_max_freq", &i915_max_freq_fops},
5073         {"i915_min_freq", &i915_min_freq_fops},
5074         {"i915_cache_sharing", &i915_cache_sharing_fops},
5075         {"i915_ring_stop", &i915_ring_stop_fops},
5076         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5077         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5078         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5079         {"i915_error_state", &i915_error_state_fops},
5080         {"i915_next_seqno", &i915_next_seqno_fops},
5081         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5082         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5083         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5084         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5085         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5086         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5087         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5088         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5089 };
5090
5091 void intel_display_crc_init(struct drm_device *dev)
5092 {
5093         struct drm_i915_private *dev_priv = dev->dev_private;
5094         enum pipe pipe;
5095
5096         for_each_pipe(dev_priv, pipe) {
5097                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5098
5099                 pipe_crc->opened = false;
5100                 spin_lock_init(&pipe_crc->lock);
5101                 init_waitqueue_head(&pipe_crc->wq);
5102         }
5103 }
5104
5105 int i915_debugfs_init(struct drm_minor *minor)
5106 {
5107         int ret, i;
5108
5109         ret = i915_forcewake_create(minor->debugfs_root, minor);
5110         if (ret)
5111                 return ret;
5112
5113         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5114                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5115                 if (ret)
5116                         return ret;
5117         }
5118
5119         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5120                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5121                                           i915_debugfs_files[i].name,
5122                                           i915_debugfs_files[i].fops);
5123                 if (ret)
5124                         return ret;
5125         }
5126
5127         return drm_debugfs_create_files(i915_debugfs_list,
5128                                         I915_DEBUGFS_ENTRIES,
5129                                         minor->debugfs_root, minor);
5130 }
5131
5132 void i915_debugfs_cleanup(struct drm_minor *minor)
5133 {
5134         int i;
5135
5136         drm_debugfs_remove_files(i915_debugfs_list,
5137                                  I915_DEBUGFS_ENTRIES, minor);
5138
5139         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5140                                  1, minor);
5141
5142         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5143                 struct drm_info_list *info_list =
5144                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5145
5146                 drm_debugfs_remove_files(info_list, 1, minor);
5147         }
5148
5149         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5150                 struct drm_info_list *info_list =
5151                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5152
5153                 drm_debugfs_remove_files(info_list, 1, minor);
5154         }
5155 }
5156
5157 struct dpcd_block {
5158         /* DPCD dump start address. */
5159         unsigned int offset;
5160         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5161         unsigned int end;
5162         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5163         size_t size;
5164         /* Only valid for eDP. */
5165         bool edp;
5166 };
5167
5168 static const struct dpcd_block i915_dpcd_debug[] = {
5169         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5170         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5171         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5172         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5173         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5174         { .offset = DP_SET_POWER },
5175         { .offset = DP_EDP_DPCD_REV },
5176         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5177         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5178         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5179 };
5180
5181 static int i915_dpcd_show(struct seq_file *m, void *data)
5182 {
5183         struct drm_connector *connector = m->private;
5184         struct intel_dp *intel_dp =
5185                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5186         uint8_t buf[16];
5187         ssize_t err;
5188         int i;
5189
5190         if (connector->status != connector_status_connected)
5191                 return -ENODEV;
5192
5193         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5194                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5195                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5196
5197                 if (b->edp &&
5198                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5199                         continue;
5200
5201                 /* low tech for now */
5202                 if (WARN_ON(size > sizeof(buf)))
5203                         continue;
5204
5205                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5206                 if (err <= 0) {
5207                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5208                                   size, b->offset, err);
5209                         continue;
5210                 }
5211
5212                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5213         }
5214
5215         return 0;
5216 }
5217
5218 static int i915_dpcd_open(struct inode *inode, struct file *file)
5219 {
5220         return single_open(file, i915_dpcd_show, inode->i_private);
5221 }
5222
5223 static const struct file_operations i915_dpcd_fops = {
5224         .owner = THIS_MODULE,
5225         .open = i915_dpcd_open,
5226         .read = seq_read,
5227         .llseek = seq_lseek,
5228         .release = single_release,
5229 };
5230
5231 /**
5232  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5233  * @connector: pointer to a registered drm_connector
5234  *
5235  * Cleanup will be done by drm_connector_unregister() through a call to
5236  * drm_debugfs_connector_remove().
5237  *
5238  * Returns 0 on success, negative error codes on error.
5239  */
5240 int i915_debugfs_connector_add(struct drm_connector *connector)
5241 {
5242         struct dentry *root = connector->debugfs_entry;
5243
5244         /* The connector must have been registered beforehands. */
5245         if (!root)
5246                 return -ENODEV;
5247
5248         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5249             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5250                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5251                                     &i915_dpcd_fops);
5252
5253         return 0;
5254 }