drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_legacy.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38 #include "i915_vgpu.h"
  39 #include "i915_trace.h"
  40 #include <linux/pci.h>
  41 #include <linux/console.h>
  42 #include <linux/vt.h>
  43 #include <linux/vgaarb.h>
  44 #include <linux/acpi.h>
  45 #include <linux/pnp.h>
  46 #include <linux/vga_switcheroo.h>
  47 #include <linux/slab.h>
  48 #include <acpi/video.h>
  49 #include <linux/pm.h>
  50 #include <linux/pm_runtime.h>
  51 #include <linux/oom.h>
  52
  53 static unsigned int i915_load_fail_count;
  54
  55 bool __i915_inject_load_failure(const char *func, int line)
  56 {
  57         if (i915_load_fail_count >= i915.inject_load_failure)
  58                 return false;
  59
  60         if (++i915_load_fail_count == i915.inject_load_failure) {
  61                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  62                          i915.inject_load_failure, func, line);
  63                 return true;
  64         }
  65
  66         return false;
  67 }
  68
  69 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  70 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  71                     "providing the dmesg log by booting with drm.debug=0xf"
  72
  73 void
  74 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  75               const char *fmt, ...)
  76 {
  77         static bool shown_bug_once;
  78         struct device *dev = dev_priv->dev->dev;
  79         bool is_error = level[1] <= KERN_ERR[1];
  80         bool is_debug = level[1] == KERN_DEBUG[1];
  81         struct va_format vaf;
  82         va_list args;
  83
  84         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  85                 return;
  86
  87         va_start(args, fmt);
  88
  89         vaf.fmt = fmt;
  90         vaf.va = &args;
  91
  92         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  93                    __builtin_return_address(0), &vaf);
  94
  95         if (is_error && !shown_bug_once) {
  96                 dev_notice(dev, "%s", FDO_BUG_MSG);
  97                 shown_bug_once = true;
  98         }
  99
 100         va_end(args);
 101 }
 102
 103 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 104 {
 105         return i915.inject_load_failure &&
 106                i915_load_fail_count == i915.inject_load_failure;
 107 }
 108
 109 #define i915_load_error(dev_priv, fmt, ...)                                  \
 110         __i915_printk(dev_priv,                                              \
 111                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 112                       fmt, ##__VA_ARGS__)
 113
 114 static int i915_getparam(struct drm_device *dev, void *data,
 115                          struct drm_file *file_priv)
 116 {
 117         struct drm_i915_private *dev_priv = dev->dev_private;
 118         drm_i915_getparam_t *param = data;
 119         int value;
 120
 121         switch (param->param) {
 122         case I915_PARAM_IRQ_ACTIVE:
 123         case I915_PARAM_ALLOW_BATCHBUFFER:
 124         case I915_PARAM_LAST_DISPATCH:
 125                 /* Reject all old ums/dri params. */
 126                 return -ENODEV;
 127         case I915_PARAM_CHIPSET_ID:
 128                 value = dev->pdev->device;
 129                 break;
 130         case I915_PARAM_REVISION:
 131                 value = dev->pdev->revision;
 132                 break;
 133         case I915_PARAM_HAS_GEM:
 134                 value = 1;
 135                 break;
 136         case I915_PARAM_NUM_FENCES_AVAIL:
 137                 value = dev_priv->num_fence_regs;
 138                 break;
 139         case I915_PARAM_HAS_OVERLAY:
 140                 value = dev_priv->overlay ? 1 : 0;
 141                 break;
 142         case I915_PARAM_HAS_PAGEFLIPPING:
 143                 value = 1;
 144                 break;
 145         case I915_PARAM_HAS_EXECBUF2:
 146                 /* depends on GEM */
 147                 value = 1;
 148                 break;
 149         case I915_PARAM_HAS_BSD:
 150                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 151                 break;
 152         case I915_PARAM_HAS_BLT:
 153                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 154                 break;
 155         case I915_PARAM_HAS_VEBOX:
 156                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 157                 break;
 158         case I915_PARAM_HAS_BSD2:
 159                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 160                 break;
 161         case I915_PARAM_HAS_RELAXED_FENCING:
 162                 value = 1;
 163                 break;
 164         case I915_PARAM_HAS_COHERENT_RINGS:
 165                 value = 1;
 166                 break;
 167         case I915_PARAM_HAS_EXEC_CONSTANTS:
 168                 value = INTEL_INFO(dev)->gen >= 4;
 169                 break;
 170         case I915_PARAM_HAS_RELAXED_DELTA:
 171                 value = 1;
 172                 break;
 173         case I915_PARAM_HAS_GEN7_SOL_RESET:
 174                 value = 1;
 175                 break;
 176         case I915_PARAM_HAS_LLC:
 177                 value = HAS_LLC(dev);
 178                 break;
 179         case I915_PARAM_HAS_WT:
 180                 value = HAS_WT(dev);
 181                 break;
 182         case I915_PARAM_HAS_ALIASING_PPGTT:
 183                 value = USES_PPGTT(dev);
 184                 break;
 185         case I915_PARAM_HAS_WAIT_TIMEOUT:
 186                 value = 1;
 187                 break;
 188         case I915_PARAM_HAS_SEMAPHORES:
 189                 value = i915_semaphore_is_enabled(dev_priv);
 190                 break;
 191         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 192                 value = 1;
 193                 break;
 194         case I915_PARAM_HAS_SECURE_BATCHES:
 195                 value = capable(CAP_SYS_ADMIN);
 196                 break;
 197         case I915_PARAM_HAS_PINNED_BATCHES:
 198                 value = 1;
 199                 break;
 200         case I915_PARAM_HAS_EXEC_NO_RELOC:
 201                 value = 1;
 202                 break;
 203         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 204                 value = 1;
 205                 break;
 206         case I915_PARAM_CMD_PARSER_VERSION:
 207                 value = i915_cmd_parser_get_version(dev_priv);
 208                 break;
 209         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 210                 value = 1;
 211                 break;
 212         case I915_PARAM_MMAP_VERSION:
 213                 value = 1;
 214                 break;
 215         case I915_PARAM_SUBSLICE_TOTAL:
 216                 value = INTEL_INFO(dev)->subslice_total;
 217                 if (!value)
 218                         return -ENODEV;
 219                 break;
 220         case I915_PARAM_EU_TOTAL:
 221                 value = INTEL_INFO(dev)->eu_total;
 222                 if (!value)
 223                         return -ENODEV;
 224                 break;
 225         case I915_PARAM_HAS_GPU_RESET:
 226                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 227                 break;
 228         case I915_PARAM_HAS_RESOURCE_STREAMER:
 229                 value = HAS_RESOURCE_STREAMER(dev);
 230                 break;
 231         case I915_PARAM_HAS_EXEC_SOFTPIN:
 232                 value = 1;
 233                 break;
 234         default:
 235                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 236                 return -EINVAL;
 237         }
 238
 239         if (copy_to_user(param->value, &value, sizeof(int))) {
 240                 DRM_ERROR("copy_to_user failed\n");
 241                 return -EFAULT;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static int i915_get_bridge_dev(struct drm_device *dev)
 248 {
 249         struct drm_i915_private *dev_priv = dev->dev_private;
 250
 251         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 252         if (!dev_priv->bridge_dev) {
 253                 DRM_ERROR("bridge device not found\n");
 254                 return -1;
 255         }
 256         return 0;
 257 }
 258
 259 /* Allocate space for the MCH regs if needed, return nonzero on error */
 260 static int
 261 intel_alloc_mchbar_resource(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 265         u32 temp_lo, temp_hi = 0;
 266         u64 mchbar_addr;
 267         int ret;
 268
 269         if (INTEL_INFO(dev)->gen >= 4)
 270                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 271         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 272         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 273
 274         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 275 #ifdef CONFIG_PNP
 276         if (mchbar_addr &&
 277             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 278                 return 0;
 279 #endif
 280
 281         /* Get some space for it */
 282         dev_priv->mch_res.name = "i915 MCHBAR";
 283         dev_priv->mch_res.flags = IORESOURCE_MEM;
 284         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 285                                      &dev_priv->mch_res,
 286                                      MCHBAR_SIZE, MCHBAR_SIZE,
 287                                      PCIBIOS_MIN_MEM,
 288                                      0, pcibios_align_resource,
 289                                      dev_priv->bridge_dev);
 290         if (ret) {
 291                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 292                 dev_priv->mch_res.start = 0;
 293                 return ret;
 294         }
 295
 296         if (INTEL_INFO(dev)->gen >= 4)
 297                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 298                                        upper_32_bits(dev_priv->mch_res.start));
 299
 300         pci_write_config_dword(dev_priv->bridge_dev, reg,
 301                                lower_32_bits(dev_priv->mch_res.start));
 302         return 0;
 303 }
 304
 305 /* Setup MCHBAR if possible, return true if we should disable it again */
 306 static void
 307 intel_setup_mchbar(struct drm_device *dev)
 308 {
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 311         u32 temp;
 312         bool enabled;
 313
 314         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 315                 return;
 316
 317         dev_priv->mchbar_need_disable = false;
 318
 319         if (IS_I915G(dev) || IS_I915GM(dev)) {
 320                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 321                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 322         } else {
 323                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 324                 enabled = temp & 1;
 325         }
 326
 327         /* If it's already enabled, don't have to do anything */
 328         if (enabled)
 329                 return;
 330
 331         if (intel_alloc_mchbar_resource(dev))
 332                 return;
 333
 334         dev_priv->mchbar_need_disable = true;
 335
 336         /* Space is allocated or reserved, so enable it. */
 337         if (IS_I915G(dev) || IS_I915GM(dev)) {
 338                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 339                                        temp | DEVEN_MCHBAR_EN);
 340         } else {
 341                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 342                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 343         }
 344 }
 345
 346 static void
 347 intel_teardown_mchbar(struct drm_device *dev)
 348 {
 349         struct drm_i915_private *dev_priv = dev->dev_private;
 350         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 351
 352         if (dev_priv->mchbar_need_disable) {
 353                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 354                         u32 deven_val;
 355
 356                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 357                                               &deven_val);
 358                         deven_val &= ~DEVEN_MCHBAR_EN;
 359                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 360                                                deven_val);
 361                 } else {
 362                         u32 mchbar_val;
 363
 364                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 365                                               &mchbar_val);
 366                         mchbar_val &= ~1;
 367                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 368                                                mchbar_val);
 369                 }
 370         }
 371
 372         if (dev_priv->mch_res.start)
 373                 release_resource(&dev_priv->mch_res);
 374 }
 375
 376 /* true = enable decode, false = disable decoder */
 377 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 378 {
 379         struct drm_device *dev = cookie;
 380
 381         intel_modeset_vga_set_state(dev, state);
 382         if (state)
 383                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 384                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 385         else
 386                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 387 }
 388
 389 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 390 {
 391         struct drm_device *dev = pci_get_drvdata(pdev);
 392         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 393
 394         if (state == VGA_SWITCHEROO_ON) {
 395                 pr_info("switched on\n");
 396                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 397                 /* i915 resume handler doesn't set to D0 */
 398                 pci_set_power_state(dev->pdev, PCI_D0);
 399                 i915_resume_switcheroo(dev);
 400                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 401         } else {
 402                 pr_info("switched off\n");
 403                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 404                 i915_suspend_switcheroo(dev, pmm);
 405                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 406         }
 407 }
 408
 409 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 410 {
 411         struct drm_device *dev = pci_get_drvdata(pdev);
 412
 413         /*
 414          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 415          * locking inversion with the driver load path. And the access here is
 416          * completely racy anyway. So don't bother with locking for now.
 417          */
 418         return dev->open_count == 0;
 419 }
 420
 421 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 422         .set_gpu_state = i915_switcheroo_set_state,
 423         .reprobe = NULL,
 424         .can_switch = i915_switcheroo_can_switch,
 425 };
 426
 427 static void i915_gem_fini(struct drm_device *dev)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(dev);
 430
 431         /*
 432          * Neither the BIOS, ourselves or any other kernel
 433          * expects the system to be in execlists mode on startup,
 434          * so we need to reset the GPU back to legacy mode. And the only
 435          * known way to disable logical contexts is through a GPU reset.
 436          *
 437          * So in order to leave the system in a known default configuration,
 438          * always reset the GPU upon unload. Afterwards we then clean up the
 439          * GEM state tracking, flushing off the requests and leaving the
 440          * system in a known idle state.
 441          *
 442          * Note that is of the upmost importance that the GPU is idle and
 443          * all stray writes are flushed *before* we dismantle the backing
 444          * storage for the pinned objects.
 445          *
 446          * However, since we are uncertain that reseting the GPU on older
 447          * machines is a good idea, we don't - just in case it leaves the
 448          * machine in an unusable condition.
 449          */
 450         if (HAS_HW_CONTEXTS(dev)) {
 451                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 452                 WARN_ON(reset && reset != -ENODEV);
 453         }
 454
 455         mutex_lock(&dev->struct_mutex);
 456         i915_gem_reset(dev);
 457         i915_gem_cleanup_engines(dev);
 458         i915_gem_context_fini(dev);
 459         mutex_unlock(&dev->struct_mutex);
 460
 461         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 462 }
 463
 464 static int i915_load_modeset_init(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467         int ret;
 468
 469         if (i915_inject_load_failure())
 470                 return -ENODEV;
 471
 472         ret = intel_bios_init(dev_priv);
 473         if (ret)
 474                 DRM_INFO("failed to find VBIOS tables\n");
 475
 476         /* If we have > 1 VGA cards, then we need to arbitrate access
 477          * to the common VGA resources.
 478          *
 479          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 480          * then we do not take part in VGA arbitration and the
 481          * vga_client_register() fails with -ENODEV.
 482          */
 483         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 484         if (ret && ret != -ENODEV)
 485                 goto out;
 486
 487         intel_register_dsm_handler();
 488
 489         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 490         if (ret)
 491                 goto cleanup_vga_client;
 492
 493         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 494         intel_update_rawclk(dev_priv);
 495
 496         intel_power_domains_init_hw(dev_priv, false);
 497
 498         intel_csr_ucode_init(dev_priv);
 499
 500         ret = intel_irq_install(dev_priv);
 501         if (ret)
 502                 goto cleanup_csr;
 503
 504         intel_setup_gmbus(dev);
 505
 506         /* Important: The output setup functions called by modeset_init need
 507          * working irqs for e.g. gmbus and dp aux transfers. */
 508         intel_modeset_init(dev);
 509
 510         intel_guc_init(dev);
 511
 512         ret = i915_gem_init(dev);
 513         if (ret)
 514                 goto cleanup_irq;
 515
 516         intel_modeset_gem_init(dev);
 517
 518         if (INTEL_INFO(dev)->num_pipes == 0)
 519                 return 0;
 520
 521         ret = intel_fbdev_init(dev);
 522         if (ret)
 523                 goto cleanup_gem;
 524
 525         /* Only enable hotplug handling once the fbdev is fully set up. */
 526         intel_hpd_init(dev_priv);
 527
 528         drm_kms_helper_poll_init(dev);
 529
 530         return 0;
 531
 532 cleanup_gem:
 533         i915_gem_fini(dev);
 534 cleanup_irq:
 535         intel_guc_fini(dev);
 536         drm_irq_uninstall(dev);
 537         intel_teardown_gmbus(dev);
 538 cleanup_csr:
 539         intel_csr_ucode_fini(dev_priv);
 540         intel_power_domains_fini(dev_priv);
 541         vga_switcheroo_unregister_client(dev->pdev);
 542 cleanup_vga_client:
 543         vga_client_register(dev->pdev, NULL, NULL, NULL);
 544 out:
 545         return ret;
 546 }
 547
 548 #if IS_ENABLED(CONFIG_FB)
 549 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 550 {
 551         struct apertures_struct *ap;
 552         struct pci_dev *pdev = dev_priv->dev->pdev;
 553         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 554         bool primary;
 555         int ret;
 556
 557         ap = alloc_apertures(1);
 558         if (!ap)
 559                 return -ENOMEM;
 560
 561         ap->ranges[0].base = ggtt->mappable_base;
 562         ap->ranges[0].size = ggtt->mappable_end;
 563
 564         primary =
 565                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 566
 567         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 568
 569         kfree(ap);
 570
 571         return ret;
 572 }
 573 #else
 574 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 575 {
 576         return 0;
 577 }
 578 #endif
 579
 580 #if !defined(CONFIG_VGA_CONSOLE)
 581 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 582 {
 583         return 0;
 584 }
 585 #elif !defined(CONFIG_DUMMY_CONSOLE)
 586 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 587 {
 588         return -ENODEV;
 589 }
 590 #else
 591 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 592 {
 593         int ret = 0;
 594
 595         DRM_INFO("Replacing VGA console driver\n");
 596
 597         console_lock();
 598         if (con_is_bound(&vga_con))
 599                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 600         if (ret == 0) {
 601                 ret = do_unregister_con_driver(&vga_con);
 602
 603                 /* Ignore "already unregistered". */
 604                 if (ret == -ENODEV)
 605                         ret = 0;
 606         }
 607         console_unlock();
 608
 609         return ret;
 610 }
 611 #endif
 612
 613 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 614 {
 615         const struct intel_device_info *info = &dev_priv->info;
 616
 617 #define PRINT_S(name) "%s"
 618 #define SEP_EMPTY
 619 #define PRINT_FLAG(name) info->name ? #name "," : ""
 620 #define SEP_COMMA ,
 621         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 622                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 623                          info->gen,
 624                          dev_priv->dev->pdev->device,
 625                          dev_priv->dev->pdev->revision,
 626                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 627 #undef PRINT_S
 628 #undef SEP_EMPTY
 629 #undef PRINT_FLAG
 630 #undef SEP_COMMA
 631 }
 632
 633 static void cherryview_sseu_info_init(struct drm_device *dev)
 634 {
 635         struct drm_i915_private *dev_priv = dev->dev_private;
 636         struct intel_device_info *info;
 637         u32 fuse, eu_dis;
 638
 639         info = (struct intel_device_info *)&dev_priv->info;
 640         fuse = I915_READ(CHV_FUSE_GT);
 641
 642         info->slice_total = 1;
 643
 644         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 645                 info->subslice_per_slice++;
 646                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 647                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 648                 info->eu_total += 8 - hweight32(eu_dis);
 649         }
 650
 651         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 652                 info->subslice_per_slice++;
 653                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 654                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 655                 info->eu_total += 8 - hweight32(eu_dis);
 656         }
 657
 658         info->subslice_total = info->subslice_per_slice;
 659         /*
 660          * CHV expected to always have a uniform distribution of EU
 661          * across subslices.
 662         */
 663         info->eu_per_subslice = info->subslice_total ?
 664                                 info->eu_total / info->subslice_total :
 665                                 0;
 666         /*
 667          * CHV supports subslice power gating on devices with more than
 668          * one subslice, and supports EU power gating on devices with
 669          * more than one EU pair per subslice.
 670         */
 671         info->has_slice_pg = 0;
 672         info->has_subslice_pg = (info->subslice_total > 1);
 673         info->has_eu_pg = (info->eu_per_subslice > 2);
 674 }
 675
 676 static void gen9_sseu_info_init(struct drm_device *dev)
 677 {
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         struct intel_device_info *info;
 680         int s_max = 3, ss_max = 4, eu_max = 8;
 681         int s, ss;
 682         u32 fuse2, s_enable, ss_disable, eu_disable;
 683         u8 eu_mask = 0xff;
 684
 685         info = (struct intel_device_info *)&dev_priv->info;
 686         fuse2 = I915_READ(GEN8_FUSE2);
 687         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 688                    GEN8_F2_S_ENA_SHIFT;
 689         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 690                      GEN9_F2_SS_DIS_SHIFT;
 691
 692         info->slice_total = hweight32(s_enable);
 693         /*
 694          * The subslice disable field is global, i.e. it applies
 695          * to each of the enabled slices.
 696         */
 697         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 698         info->subslice_total = info->slice_total *
 699                                info->subslice_per_slice;
 700
 701         /*
 702          * Iterate through enabled slices and subslices to
 703          * count the total enabled EU.
 704         */
 705         for (s = 0; s < s_max; s++) {
 706                 if (!(s_enable & (0x1 << s)))
 707                         /* skip disabled slice */
 708                         continue;
 709
 710                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 711                 for (ss = 0; ss < ss_max; ss++) {
 712                         int eu_per_ss;
 713
 714                         if (ss_disable & (0x1 << ss))
 715                                 /* skip disabled subslice */
 716                                 continue;
 717
 718                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 719                                                       eu_mask);
 720
 721                         /*
 722                          * Record which subslice(s) has(have) 7 EUs. we
 723                          * can tune the hash used to spread work among
 724                          * subslices if they are unbalanced.
 725                          */
 726                         if (eu_per_ss == 7)
 727                                 info->subslice_7eu[s] |= 1 << ss;
 728
 729                         info->eu_total += eu_per_ss;
 730                 }
 731         }
 732
 733         /*
 734          * SKL is expected to always have a uniform distribution
 735          * of EU across subslices with the exception that any one
 736          * EU in any one subslice may be fused off for die
 737          * recovery. BXT is expected to be perfectly uniform in EU
 738          * distribution.
 739         */
 740         info->eu_per_subslice = info->subslice_total ?
 741                                 DIV_ROUND_UP(info->eu_total,
 742                                              info->subslice_total) : 0;
 743         /*
 744          * SKL supports slice power gating on devices with more than
 745          * one slice, and supports EU power gating on devices with
 746          * more than one EU pair per subslice. BXT supports subslice
 747          * power gating on devices with more than one subslice, and
 748          * supports EU power gating on devices with more than one EU
 749          * pair per subslice.
 750         */
 751         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 752                                (info->slice_total > 1));
 753         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 754         info->has_eu_pg = (info->eu_per_subslice > 2);
 755
 756         if (IS_BROXTON(dev)) {
 757 #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
 758                 /*
 759                  * There is a HW issue in 2x6 fused down parts that requires
 760                  * Pooled EU to be enabled as a WA. The pool configuration
 761                  * changes depending upon which subslice is fused down. This
 762                  * doesn't affect if the device has all 3 subslices enabled.
 763                  */
 764                 /* WaEnablePooledEuFor2x6:bxt */
 765                 info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
 766                                        (info->subslice_per_slice == 2 &&
 767                                         INTEL_REVID(dev) < BXT_REVID_C0));
 768
 769                 info->min_eu_in_pool = 0;
 770                 if (info->has_pooled_eu) {
 771                         if (IS_SS_DISABLED(ss_disable, 0) ||
 772                             IS_SS_DISABLED(ss_disable, 2))
 773                                 info->min_eu_in_pool = 3;
 774                         else if (IS_SS_DISABLED(ss_disable, 1))
 775                                 info->min_eu_in_pool = 6;
 776                         else
 777                                 info->min_eu_in_pool = 9;
 778                 }
 779 #undef IS_SS_DISABLED
 780         }
 781 }
 782
 783 static void broadwell_sseu_info_init(struct drm_device *dev)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct intel_device_info *info;
 787         const int s_max = 3, ss_max = 3, eu_max = 8;
 788         int s, ss;
 789         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 790
 791         fuse2 = I915_READ(GEN8_FUSE2);
 792         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 793         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 794
 795         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 796         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 797                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 798                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 799         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 800                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 801                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 802
 803
 804         info = (struct intel_device_info *)&dev_priv->info;
 805         info->slice_total = hweight32(s_enable);
 806
 807         /*
 808          * The subslice disable field is global, i.e. it applies
 809          * to each of the enabled slices.
 810          */
 811         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 812         info->subslice_total = info->slice_total * info->subslice_per_slice;
 813
 814         /*
 815          * Iterate through enabled slices and subslices to
 816          * count the total enabled EU.
 817          */
 818         for (s = 0; s < s_max; s++) {
 819                 if (!(s_enable & (0x1 << s)))
 820                         /* skip disabled slice */
 821                         continue;
 822
 823                 for (ss = 0; ss < ss_max; ss++) {
 824                         u32 n_disabled;
 825
 826                         if (ss_disable & (0x1 << ss))
 827                                 /* skip disabled subslice */
 828                                 continue;
 829
 830                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 831
 832                         /*
 833                          * Record which subslices have 7 EUs.
 834                          */
 835                         if (eu_max - n_disabled == 7)
 836                                 info->subslice_7eu[s] |= 1 << ss;
 837
 838                         info->eu_total += eu_max - n_disabled;
 839                 }
 840         }
 841
 842         /*
 843          * BDW is expected to always have a uniform distribution of EU across
 844          * subslices with the exception that any one EU in any one subslice may
 845          * be fused off for die recovery.
 846          */
 847         info->eu_per_subslice = info->subslice_total ?
 848                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 849
 850         /*
 851          * BDW supports slice power gating on devices with more than
 852          * one slice.
 853          */
 854         info->has_slice_pg = (info->slice_total > 1);
 855         info->has_subslice_pg = 0;
 856         info->has_eu_pg = 0;
 857 }
 858
 859 /*
 860  * Determine various intel_device_info fields at runtime.
 861  *
 862  * Use it when either:
 863  *   - it's judged too laborious to fill n static structures with the limit
 864  *     when a simple if statement does the job,
 865  *   - run-time checks (eg read fuse/strap registers) are needed.
 866  *
 867  * This function needs to be called:
 868  *   - after the MMIO has been setup as we are reading registers,
 869  *   - after the PCH has been detected,
 870  *   - before the first usage of the fields it can tweak.
 871  */
 872 static void intel_device_info_runtime_init(struct drm_device *dev)
 873 {
 874         struct drm_i915_private *dev_priv = dev->dev_private;
 875         struct intel_device_info *info;
 876         enum pipe pipe;
 877
 878         info = (struct intel_device_info *)&dev_priv->info;
 879
 880         /*
 881          * Skylake and Broxton currently don't expose the topmost plane as its
 882          * use is exclusive with the legacy cursor and we only want to expose
 883          * one of those, not both. Until we can safely expose the topmost plane
 884          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 885          * we don't expose the topmost plane at all to prevent ABI breakage
 886          * down the line.
 887          */
 888         if (IS_BROXTON(dev)) {
 889                 info->num_sprites[PIPE_A] = 2;
 890                 info->num_sprites[PIPE_B] = 2;
 891                 info->num_sprites[PIPE_C] = 1;
 892         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 893                 for_each_pipe(dev_priv, pipe)
 894                         info->num_sprites[pipe] = 2;
 895         else
 896                 for_each_pipe(dev_priv, pipe)
 897                         info->num_sprites[pipe] = 1;
 898
 899         if (i915.disable_display) {
 900                 DRM_INFO("Display disabled (module parameter)\n");
 901                 info->num_pipes = 0;
 902         } else if (info->num_pipes > 0 &&
 903                    (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
 904                    HAS_PCH_SPLIT(dev)) {
 905                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 906                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 907
 908                 /*
 909                  * SFUSE_STRAP is supposed to have a bit signalling the display
 910                  * is fused off. Unfortunately it seems that, at least in
 911                  * certain cases, fused off display means that PCH display
 912                  * reads don't land anywhere. In that case, we read 0s.
 913                  *
 914                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 915                  * should be set when taking over after the firmware.
 916                  */
 917                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 918                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 919                     (dev_priv->pch_type == PCH_CPT &&
 920                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 921                         DRM_INFO("Display fused off, disabling\n");
 922                         info->num_pipes = 0;
 923                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 924                         DRM_INFO("PipeC fused off\n");
 925                         info->num_pipes -= 1;
 926                 }
 927         } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
 928                 u32 dfsm = I915_READ(SKL_DFSM);
 929                 u8 disabled_mask = 0;
 930                 bool invalid;
 931                 int num_bits;
 932
 933                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
 934                         disabled_mask |= BIT(PIPE_A);
 935                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
 936                         disabled_mask |= BIT(PIPE_B);
 937                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
 938                         disabled_mask |= BIT(PIPE_C);
 939
 940                 num_bits = hweight8(disabled_mask);
 941
 942                 switch (disabled_mask) {
 943                 case BIT(PIPE_A):
 944                 case BIT(PIPE_B):
 945                 case BIT(PIPE_A) | BIT(PIPE_B):
 946                 case BIT(PIPE_A) | BIT(PIPE_C):
 947                         invalid = true;
 948                         break;
 949                 default:
 950                         invalid = false;
 951                 }
 952
 953                 if (num_bits > info->num_pipes || invalid)
 954                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
 955                                   disabled_mask);
 956                 else
 957                         info->num_pipes -= num_bits;
 958         }
 959
 960         /* Initialize slice/subslice/EU info */
 961         if (IS_CHERRYVIEW(dev))
 962                 cherryview_sseu_info_init(dev);
 963         else if (IS_BROADWELL(dev))
 964                 broadwell_sseu_info_init(dev);
 965         else if (INTEL_INFO(dev)->gen >= 9)
 966                 gen9_sseu_info_init(dev);
 967
 968         info->has_snoop = !info->has_llc;
 969
 970         /* Snooping is broken on BXT A stepping. */
 971         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
 972                 info->has_snoop = false;
 973
 974         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 975         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 976         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 977         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 978         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 979         DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n");
 980         if (HAS_POOLED_EU(dev))
 981                 DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool);
 982         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 983                          info->has_slice_pg ? "y" : "n");
 984         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 985                          info->has_subslice_pg ? "y" : "n");
 986         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 987                          info->has_eu_pg ? "y" : "n");
 988
 989         i915.enable_execlists =
 990                 intel_sanitize_enable_execlists(dev_priv,
 991                                                 i915.enable_execlists);
 992
 993         /*
 994          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 995          * user's requested state against the hardware/driver capabilities.  We
 996          * do this now so that we can print out any log messages once rather
 997          * than every time we check intel_enable_ppgtt().
 998          */
 999         i915.enable_ppgtt =
1000                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1001         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1002 }
1003
1004 static void intel_init_dpio(struct drm_i915_private *dev_priv)
1005 {
1006         /*
1007          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1008          * CHV x1 PHY (DP/HDMI D)
1009          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1010          */
1011         if (IS_CHERRYVIEW(dev_priv)) {
1012                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1013                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1014         } else if (IS_VALLEYVIEW(dev_priv)) {
1015                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1016         }
1017 }
1018
1019 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
1020 {
1021         /*
1022          * The i915 workqueue is primarily used for batched retirement of
1023          * requests (and thus managing bo) once the task has been completed
1024          * by the GPU. i915_gem_retire_requests() is called directly when we
1025          * need high-priority retirement, such as waiting for an explicit
1026          * bo.
1027          *
1028          * It is also used for periodic low-priority events, such as
1029          * idle-timers and recording error state.
1030          *
1031          * All tasks on the workqueue are expected to acquire the dev mutex
1032          * so there is no point in running more than one instance of the
1033          * workqueue at any time.  Use an ordered one.
1034          */
1035         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1036         if (dev_priv->wq == NULL)
1037                 goto out_err;
1038
1039         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1040         if (dev_priv->hotplug.dp_wq == NULL)
1041                 goto out_free_wq;
1042
1043         dev_priv->gpu_error.hangcheck_wq =
1044                 alloc_ordered_workqueue("i915-hangcheck", 0);
1045         if (dev_priv->gpu_error.hangcheck_wq == NULL)
1046                 goto out_free_dp_wq;
1047
1048         return 0;
1049
1050 out_free_dp_wq:
1051         destroy_workqueue(dev_priv->hotplug.dp_wq);
1052 out_free_wq:
1053         destroy_workqueue(dev_priv->wq);
1054 out_err:
1055         DRM_ERROR("Failed to allocate workqueues.\n");
1056
1057         return -ENOMEM;
1058 }
1059
1060 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
1061 {
1062         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1063         destroy_workqueue(dev_priv->hotplug.dp_wq);
1064         destroy_workqueue(dev_priv->wq);
1065 }
1066
1067 /**
1068  * i915_driver_init_early - setup state not requiring device access
1069  * @dev_priv: device private
1070  *
1071  * Initialize everything that is a "SW-only" state, that is state not
1072  * requiring accessing the device or exposing the driver via kernel internal
1073  * or userspace interfaces. Example steps belonging here: lock initialization,
1074  * system memory allocation, setting up device specific attributes and
1075  * function hooks not requiring accessing the device.
1076  */
1077 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1078                                   struct drm_device *dev,
1079                                   struct intel_device_info *info)
1080 {
1081         struct intel_device_info *device_info;
1082         int ret = 0;
1083
1084         if (i915_inject_load_failure())
1085                 return -ENODEV;
1086
1087         /* Setup the write-once "constant" device info */
1088         device_info = (struct intel_device_info *)&dev_priv->info;
1089         memcpy(device_info, info, sizeof(dev_priv->info));
1090         device_info->device_id = dev->pdev->device;
1091
1092         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1093         device_info->gen_mask = BIT(device_info->gen - 1);
1094
1095         spin_lock_init(&dev_priv->irq_lock);
1096         spin_lock_init(&dev_priv->gpu_error.lock);
1097         mutex_init(&dev_priv->backlight_lock);
1098         spin_lock_init(&dev_priv->uncore.lock);
1099         spin_lock_init(&dev_priv->mm.object_stat_lock);
1100         spin_lock_init(&dev_priv->mmio_flip_lock);
1101         mutex_init(&dev_priv->sb_lock);
1102         mutex_init(&dev_priv->modeset_restore_lock);
1103         mutex_init(&dev_priv->av_mutex);
1104         mutex_init(&dev_priv->wm.wm_mutex);
1105         mutex_init(&dev_priv->pps_mutex);
1106
1107         ret = i915_workqueues_init(dev_priv);
1108         if (ret < 0)
1109                 return ret;
1110
1111         ret = intel_gvt_init(dev_priv);
1112         if (ret < 0)
1113                 goto err_workqueues;
1114
1115         /* This must be called before any calls to HAS_PCH_* */
1116         intel_detect_pch(dev);
1117
1118         intel_pm_setup(dev);
1119         intel_init_dpio(dev_priv);
1120         intel_power_domains_init(dev_priv);
1121         intel_irq_init(dev_priv);
1122         intel_init_display_hooks(dev_priv);
1123         intel_init_clock_gating_hooks(dev_priv);
1124         intel_init_audio_hooks(dev_priv);
1125         i915_gem_load_init(dev);
1126
1127         intel_display_crc_init(dev);
1128
1129         i915_dump_device_info(dev_priv);
1130
1131         /* Not all pre-production machines fall into this category, only the
1132          * very first ones. Almost everything should work, except for maybe
1133          * suspend/resume. And we don't implement workarounds that affect only
1134          * pre-production machines. */
1135         if (IS_HSW_EARLY_SDV(dev))
1136                 DRM_INFO("This is an early pre-production Haswell machine. "
1137                          "It may not be fully functional.\n");
1138
1139         return 0;
1140
1141 err_workqueues:
1142         i915_workqueues_cleanup(dev_priv);
1143         return ret;
1144 }
1145
1146 /**
1147  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1148  * @dev_priv: device private
1149  */
1150 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1151 {
1152         i915_gem_load_cleanup(dev_priv->dev);
1153         i915_workqueues_cleanup(dev_priv);
1154 }
1155
1156 static int i915_mmio_setup(struct drm_device *dev)
1157 {
1158         struct drm_i915_private *dev_priv = to_i915(dev);
1159         int mmio_bar;
1160         int mmio_size;
1161
1162         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1163         /*
1164          * Before gen4, the registers and the GTT are behind different BARs.
1165          * However, from gen4 onwards, the registers and the GTT are shared
1166          * in the same BAR, so we want to restrict this ioremap from
1167          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1168          * the register BAR remains the same size for all the earlier
1169          * generations up to Ironlake.
1170          */
1171         if (INTEL_INFO(dev)->gen < 5)
1172                 mmio_size = 512 * 1024;
1173         else
1174                 mmio_size = 2 * 1024 * 1024;
1175         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1176         if (dev_priv->regs == NULL) {
1177                 DRM_ERROR("failed to map registers\n");
1178
1179                 return -EIO;
1180         }
1181
1182         /* Try to make sure MCHBAR is enabled before poking at it */
1183         intel_setup_mchbar(dev);
1184
1185         return 0;
1186 }
1187
1188 static void i915_mmio_cleanup(struct drm_device *dev)
1189 {
1190         struct drm_i915_private *dev_priv = to_i915(dev);
1191
1192         intel_teardown_mchbar(dev);
1193         pci_iounmap(dev->pdev, dev_priv->regs);
1194 }
1195
1196 /**
1197  * i915_driver_init_mmio - setup device MMIO
1198  * @dev_priv: device private
1199  *
1200  * Setup minimal device state necessary for MMIO accesses later in the
1201  * initialization sequence. The setup here should avoid any other device-wide
1202  * side effects or exposing the driver via kernel internal or user space
1203  * interfaces.
1204  */
1205 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1206 {
1207         struct drm_device *dev = dev_priv->dev;
1208         int ret;
1209
1210         if (i915_inject_load_failure())
1211                 return -ENODEV;
1212
1213         if (i915_get_bridge_dev(dev))
1214                 return -EIO;
1215
1216         ret = i915_mmio_setup(dev);
1217         if (ret < 0)
1218                 goto put_bridge;
1219
1220         intel_uncore_init(dev_priv);
1221
1222         return 0;
1223
1224 put_bridge:
1225         pci_dev_put(dev_priv->bridge_dev);
1226
1227         return ret;
1228 }
1229
1230 /**
1231  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1232  * @dev_priv: device private
1233  */
1234 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1235 {
1236         struct drm_device *dev = dev_priv->dev;
1237
1238         intel_uncore_fini(dev_priv);
1239         i915_mmio_cleanup(dev);
1240         pci_dev_put(dev_priv->bridge_dev);
1241 }
1242
1243 /**
1244  * i915_driver_init_hw - setup state requiring device access
1245  * @dev_priv: device private
1246  *
1247  * Setup state that requires accessing the device, but doesn't require
1248  * exposing the driver via kernel internal or userspace interfaces.
1249  */
1250 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1251 {
1252         struct drm_device *dev = dev_priv->dev;
1253         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1254         uint32_t aperture_size;
1255         int ret;
1256
1257         if (i915_inject_load_failure())
1258                 return -ENODEV;
1259
1260         intel_device_info_runtime_init(dev);
1261
1262         ret = i915_ggtt_init_hw(dev);
1263         if (ret)
1264                 return ret;
1265
1266         ret = i915_ggtt_enable_hw(dev);
1267         if (ret) {
1268                 DRM_ERROR("failed to enable GGTT\n");
1269                 goto out_ggtt;
1270         }
1271
1272         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1273          * otherwise the vga fbdev driver falls over. */
1274         ret = i915_kick_out_firmware_fb(dev_priv);
1275         if (ret) {
1276                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1277                 goto out_ggtt;
1278         }
1279
1280         ret = i915_kick_out_vgacon(dev_priv);
1281         if (ret) {
1282                 DRM_ERROR("failed to remove conflicting VGA console\n");
1283                 goto out_ggtt;
1284         }
1285
1286         pci_set_master(dev->pdev);
1287
1288         /* overlay on gen2 is broken and can't address above 1G */
1289         if (IS_GEN2(dev)) {
1290                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1291                 if (ret) {
1292                         DRM_ERROR("failed to set DMA mask\n");
1293
1294                         goto out_ggtt;
1295                 }
1296         }
1297
1298
1299         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1300          * using 32bit addressing, overwriting memory if HWS is located
1301          * above 4GB.
1302          *
1303          * The documentation also mentions an issue with undefined
1304          * behaviour if any general state is accessed within a page above 4GB,
1305          * which also needs to be handled carefully.
1306          */
1307         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1308                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1309
1310                 if (ret) {
1311                         DRM_ERROR("failed to set DMA mask\n");
1312
1313                         goto out_ggtt;
1314                 }
1315         }
1316
1317         aperture_size = ggtt->mappable_end;
1318
1319         ggtt->mappable =
1320                 io_mapping_create_wc(ggtt->mappable_base,
1321                                      aperture_size);
1322         if (!ggtt->mappable) {
1323                 ret = -EIO;
1324                 goto out_ggtt;
1325         }
1326
1327         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1328                                               aperture_size);
1329
1330         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1331                            PM_QOS_DEFAULT_VALUE);
1332
1333         intel_uncore_sanitize(dev_priv);
1334
1335         intel_opregion_setup(dev_priv);
1336
1337         i915_gem_load_init_fences(dev_priv);
1338
1339         /* On the 945G/GM, the chipset reports the MSI capability on the
1340          * integrated graphics even though the support isn't actually there
1341          * according to the published specs.  It doesn't appear to function
1342          * correctly in testing on 945G.
1343          * This may be a side effect of MSI having been made available for PEG
1344          * and the registers being closely associated.
1345          *
1346          * According to chipset errata, on the 965GM, MSI interrupts may
1347          * be lost or delayed, but we use them anyways to avoid
1348          * stuck interrupts on some machines.
1349          */
1350         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1351                 if (pci_enable_msi(dev->pdev) < 0)
1352                         DRM_DEBUG_DRIVER("can't enable MSI");
1353         }
1354
1355         return 0;
1356
1357 out_ggtt:
1358         i915_ggtt_cleanup_hw(dev);
1359
1360         return ret;
1361 }
1362
1363 /**
1364  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1365  * @dev_priv: device private
1366  */
1367 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1368 {
1369         struct drm_device *dev = dev_priv->dev;
1370         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1371
1372         if (dev->pdev->msi_enabled)
1373                 pci_disable_msi(dev->pdev);
1374
1375         pm_qos_remove_request(&dev_priv->pm_qos);
1376         arch_phys_wc_del(ggtt->mtrr);
1377         io_mapping_free(ggtt->mappable);
1378         i915_ggtt_cleanup_hw(dev);
1379 }
1380
1381 /**
1382  * i915_driver_register - register the driver with the rest of the system
1383  * @dev_priv: device private
1384  *
1385  * Perform any steps necessary to make the driver available via kernel
1386  * internal or userspace interfaces.
1387  */
1388 static void i915_driver_register(struct drm_i915_private *dev_priv)
1389 {
1390         struct drm_device *dev = dev_priv->dev;
1391
1392         i915_gem_shrinker_init(dev_priv);
1393         /*
1394          * Notify a valid surface after modesetting,
1395          * when running inside a VM.
1396          */
1397         if (intel_vgpu_active(dev_priv))
1398                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1399
1400         i915_debugfs_register(dev_priv);
1401         i915_setup_sysfs(dev);
1402         intel_modeset_register(dev_priv);
1403
1404         if (INTEL_INFO(dev_priv)->num_pipes) {
1405                 /* Must be done after probing outputs */
1406                 intel_opregion_register(dev_priv);
1407                 acpi_video_register();
1408         }
1409
1410         if (IS_GEN5(dev_priv))
1411                 intel_gpu_ips_init(dev_priv);
1412
1413         i915_audio_component_init(dev_priv);
1414
1415         /*
1416          * Some ports require correctly set-up hpd registers for detection to
1417          * work properly (leading to ghost connected connector status), e.g. VGA
1418          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1419          * irqs are fully enabled. We do it last so that the async config
1420          * cannot run before the connectors are registered.
1421          */
1422         intel_fbdev_initial_config_async(dev);
1423 }
1424
1425 /**
1426  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1427  * @dev_priv: device private
1428  */
1429 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1430 {
1431         i915_audio_component_cleanup(dev_priv);
1432         intel_gpu_ips_teardown();
1433         acpi_video_unregister();
1434         intel_opregion_unregister(dev_priv);
1435         intel_modeset_unregister(dev_priv);
1436         i915_teardown_sysfs(dev_priv->dev);
1437         i915_debugfs_unregister(dev_priv);
1438         i915_gem_shrinker_cleanup(dev_priv);
1439 }
1440
1441 /**
1442  * i915_driver_load - setup chip and create an initial config
1443  * @dev: DRM device
1444  * @flags: startup flags
1445  *
1446  * The driver load routine has to do several things:
1447  *   - drive output discovery via intel_modeset_init()
1448  *   - initialize the memory manager
1449  *   - allocate initial config memory
1450  *   - setup the DRM framebuffer with the allocated memory
1451  */
1452 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1453 {
1454         struct drm_i915_private *dev_priv;
1455         int ret = 0;
1456
1457         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1458         if (dev_priv == NULL)
1459                 return -ENOMEM;
1460
1461         dev->dev_private = dev_priv;
1462         /* Must be set before calling __i915_printk */
1463         dev_priv->dev = dev;
1464
1465         ret = i915_driver_init_early(dev_priv, dev,
1466                                      (struct intel_device_info *)flags);
1467
1468         if (ret < 0)
1469                 goto out_free_priv;
1470
1471         intel_runtime_pm_get(dev_priv);
1472
1473         ret = i915_driver_init_mmio(dev_priv);
1474         if (ret < 0)
1475                 goto out_runtime_pm_put;
1476
1477         ret = i915_driver_init_hw(dev_priv);
1478         if (ret < 0)
1479                 goto out_cleanup_mmio;
1480
1481         /*
1482          * TODO: move the vblank init and parts of modeset init steps into one
1483          * of the i915_driver_init_/i915_driver_register functions according
1484          * to the role/effect of the given init step.
1485          */
1486         if (INTEL_INFO(dev)->num_pipes) {
1487                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1488                 if (ret)
1489                         goto out_cleanup_hw;
1490         }
1491
1492         ret = i915_load_modeset_init(dev);
1493         if (ret < 0)
1494                 goto out_cleanup_vblank;
1495
1496         i915_driver_register(dev_priv);
1497
1498         intel_runtime_pm_enable(dev_priv);
1499
1500         intel_runtime_pm_put(dev_priv);
1501
1502         return 0;
1503
1504 out_cleanup_vblank:
1505         drm_vblank_cleanup(dev);
1506 out_cleanup_hw:
1507         i915_driver_cleanup_hw(dev_priv);
1508 out_cleanup_mmio:
1509         i915_driver_cleanup_mmio(dev_priv);
1510 out_runtime_pm_put:
1511         intel_runtime_pm_put(dev_priv);
1512         i915_driver_cleanup_early(dev_priv);
1513 out_free_priv:
1514         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1515
1516         kfree(dev_priv);
1517
1518         return ret;
1519 }
1520
1521 int i915_driver_unload(struct drm_device *dev)
1522 {
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         int ret;
1525
1526         intel_fbdev_fini(dev);
1527
1528         intel_gvt_cleanup(dev_priv);
1529
1530         ret = i915_gem_suspend(dev);
1531         if (ret) {
1532                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1533                 return ret;
1534         }
1535
1536         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1537
1538         i915_driver_unregister(dev_priv);
1539
1540         drm_vblank_cleanup(dev);
1541
1542         intel_modeset_cleanup(dev);
1543
1544         /*
1545          * free the memory space allocated for the child device
1546          * config parsed from VBT
1547          */
1548         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1549                 kfree(dev_priv->vbt.child_dev);
1550                 dev_priv->vbt.child_dev = NULL;
1551                 dev_priv->vbt.child_dev_num = 0;
1552         }
1553         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1554         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1555         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1556         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1557
1558         vga_switcheroo_unregister_client(dev->pdev);
1559         vga_client_register(dev->pdev, NULL, NULL, NULL);
1560
1561         intel_csr_ucode_fini(dev_priv);
1562
1563         /* Free error state after interrupts are fully disabled. */
1564         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1565         i915_destroy_error_state(dev);
1566
1567         /* Flush any outstanding unpin_work. */
1568         flush_workqueue(dev_priv->wq);
1569
1570         intel_guc_fini(dev);
1571         i915_gem_fini(dev);
1572         intel_fbc_cleanup_cfb(dev_priv);
1573
1574         intel_power_domains_fini(dev_priv);
1575
1576         i915_driver_cleanup_hw(dev_priv);
1577         i915_driver_cleanup_mmio(dev_priv);
1578
1579         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1580
1581         i915_driver_cleanup_early(dev_priv);
1582         kfree(dev_priv);
1583
1584         return 0;
1585 }
1586
1587 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1588 {
1589         int ret;
1590
1591         ret = i915_gem_open(dev, file);
1592         if (ret)
1593                 return ret;
1594
1595         return 0;
1596 }
1597
1598 /**
1599  * i915_driver_lastclose - clean up after all DRM clients have exited
1600  * @dev: DRM device
1601  *
1602  * Take care of cleaning up after all DRM clients have exited.  In the
1603  * mode setting case, we want to restore the kernel's initial mode (just
1604  * in case the last client left us in a bad state).
1605  *
1606  * Additionally, in the non-mode setting case, we'll tear down the GTT
1607  * and DMA structures, since the kernel won't be using them, and clea
1608  * up any GEM state.
1609  */
1610 void i915_driver_lastclose(struct drm_device *dev)
1611 {
1612         intel_fbdev_restore_mode(dev);
1613         vga_switcheroo_process_delayed_switch();
1614 }
1615
1616 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1617 {
1618         mutex_lock(&dev->struct_mutex);
1619         i915_gem_context_close(dev, file);
1620         i915_gem_release(dev, file);
1621         mutex_unlock(&dev->struct_mutex);
1622 }
1623
1624 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1625 {
1626         struct drm_i915_file_private *file_priv = file->driver_priv;
1627
1628         kfree(file_priv);
1629 }
1630
1631 static int
1632 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1633                           struct drm_file *file)
1634 {
1635         return -ENODEV;
1636 }
1637
1638 const struct drm_ioctl_desc i915_ioctls[] = {
1639         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1640         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1641         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1642         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1643         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1644         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1645         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1646         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1647         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1648         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1649         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1650         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1651         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1652         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1653         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1654         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1655         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1656         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1657         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1658         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1659         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1660         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1661         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1662         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1663         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1664         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1665         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1666         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1667         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1668         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1669         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1670         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1671         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1672         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1673         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1674         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1675         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1676         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1677         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1678         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1679         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
1680         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
1681         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1682         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1683         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1684         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1685         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1686         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1687         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1688         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1689         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1690         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1691 };
1692
1693 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);