1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_fb_helper.h>
34 #include <drm/drm_legacy.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
38 #include "i915_vgpu.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
53 static unsigned int i915_load_fail_count;
55 bool __i915_inject_load_failure(const char *func, int line)
57 if (i915_load_fail_count >= i915.inject_load_failure)
60 if (++i915_load_fail_count == i915.inject_load_failure) {
61 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
62 i915.inject_load_failure, func, line);
69 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
70 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
71 "providing the dmesg log by booting with drm.debug=0xf"
74 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
77 static bool shown_bug_once;
78 struct device *dev = dev_priv->dev->dev;
79 bool is_error = level[1] <= KERN_ERR[1];
80 bool is_debug = level[1] == KERN_DEBUG[1];
84 if (is_debug && !(drm_debug & DRM_UT_DRIVER))
92 dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
93 __builtin_return_address(0), &vaf);
95 if (is_error && !shown_bug_once) {
96 dev_notice(dev, "%s", FDO_BUG_MSG);
97 shown_bug_once = true;
103 static bool i915_error_injected(struct drm_i915_private *dev_priv)
105 return i915.inject_load_failure &&
106 i915_load_fail_count == i915.inject_load_failure;
109 #define i915_load_error(dev_priv, fmt, ...) \
110 __i915_printk(dev_priv, \
111 i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
114 static int i915_getparam(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 drm_i915_getparam_t *param = data;
121 switch (param->param) {
122 case I915_PARAM_IRQ_ACTIVE:
123 case I915_PARAM_ALLOW_BATCHBUFFER:
124 case I915_PARAM_LAST_DISPATCH:
125 /* Reject all old ums/dri params. */
127 case I915_PARAM_CHIPSET_ID:
128 value = dev->pdev->device;
130 case I915_PARAM_REVISION:
131 value = dev->pdev->revision;
133 case I915_PARAM_HAS_GEM:
136 case I915_PARAM_NUM_FENCES_AVAIL:
137 value = dev_priv->num_fence_regs;
139 case I915_PARAM_HAS_OVERLAY:
140 value = dev_priv->overlay ? 1 : 0;
142 case I915_PARAM_HAS_PAGEFLIPPING:
145 case I915_PARAM_HAS_EXECBUF2:
149 case I915_PARAM_HAS_BSD:
150 value = intel_engine_initialized(&dev_priv->engine[VCS]);
152 case I915_PARAM_HAS_BLT:
153 value = intel_engine_initialized(&dev_priv->engine[BCS]);
155 case I915_PARAM_HAS_VEBOX:
156 value = intel_engine_initialized(&dev_priv->engine[VECS]);
158 case I915_PARAM_HAS_BSD2:
159 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
161 case I915_PARAM_HAS_RELAXED_FENCING:
164 case I915_PARAM_HAS_COHERENT_RINGS:
167 case I915_PARAM_HAS_EXEC_CONSTANTS:
168 value = INTEL_INFO(dev)->gen >= 4;
170 case I915_PARAM_HAS_RELAXED_DELTA:
173 case I915_PARAM_HAS_GEN7_SOL_RESET:
176 case I915_PARAM_HAS_LLC:
177 value = HAS_LLC(dev);
179 case I915_PARAM_HAS_WT:
182 case I915_PARAM_HAS_ALIASING_PPGTT:
183 value = USES_PPGTT(dev);
185 case I915_PARAM_HAS_WAIT_TIMEOUT:
188 case I915_PARAM_HAS_SEMAPHORES:
189 value = i915_semaphore_is_enabled(dev_priv);
191 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
194 case I915_PARAM_HAS_SECURE_BATCHES:
195 value = capable(CAP_SYS_ADMIN);
197 case I915_PARAM_HAS_PINNED_BATCHES:
200 case I915_PARAM_HAS_EXEC_NO_RELOC:
203 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
206 case I915_PARAM_CMD_PARSER_VERSION:
207 value = i915_cmd_parser_get_version(dev_priv);
209 case I915_PARAM_HAS_COHERENT_PHYS_GTT:
212 case I915_PARAM_MMAP_VERSION:
215 case I915_PARAM_SUBSLICE_TOTAL:
216 value = INTEL_INFO(dev)->subslice_total;
220 case I915_PARAM_EU_TOTAL:
221 value = INTEL_INFO(dev)->eu_total;
225 case I915_PARAM_HAS_GPU_RESET:
226 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
228 case I915_PARAM_HAS_RESOURCE_STREAMER:
229 value = HAS_RESOURCE_STREAMER(dev);
231 case I915_PARAM_HAS_EXEC_SOFTPIN:
235 DRM_DEBUG("Unknown parameter %d\n", param->param);
239 if (copy_to_user(param->value, &value, sizeof(int))) {
240 DRM_ERROR("copy_to_user failed\n");
247 static int i915_get_bridge_dev(struct drm_device *dev)
249 struct drm_i915_private *dev_priv = dev->dev_private;
251 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
252 if (!dev_priv->bridge_dev) {
253 DRM_ERROR("bridge device not found\n");
259 /* Allocate space for the MCH regs if needed, return nonzero on error */
261 intel_alloc_mchbar_resource(struct drm_device *dev)
263 struct drm_i915_private *dev_priv = dev->dev_private;
264 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
265 u32 temp_lo, temp_hi = 0;
269 if (INTEL_INFO(dev)->gen >= 4)
270 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
271 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
272 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
274 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
277 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
281 /* Get some space for it */
282 dev_priv->mch_res.name = "i915 MCHBAR";
283 dev_priv->mch_res.flags = IORESOURCE_MEM;
284 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
286 MCHBAR_SIZE, MCHBAR_SIZE,
288 0, pcibios_align_resource,
289 dev_priv->bridge_dev);
291 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
292 dev_priv->mch_res.start = 0;
296 if (INTEL_INFO(dev)->gen >= 4)
297 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
298 upper_32_bits(dev_priv->mch_res.start));
300 pci_write_config_dword(dev_priv->bridge_dev, reg,
301 lower_32_bits(dev_priv->mch_res.start));
305 /* Setup MCHBAR if possible, return true if we should disable it again */
307 intel_setup_mchbar(struct drm_device *dev)
309 struct drm_i915_private *dev_priv = dev->dev_private;
310 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
314 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
317 dev_priv->mchbar_need_disable = false;
319 if (IS_I915G(dev) || IS_I915GM(dev)) {
320 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
321 enabled = !!(temp & DEVEN_MCHBAR_EN);
323 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
327 /* If it's already enabled, don't have to do anything */
331 if (intel_alloc_mchbar_resource(dev))
334 dev_priv->mchbar_need_disable = true;
336 /* Space is allocated or reserved, so enable it. */
337 if (IS_I915G(dev) || IS_I915GM(dev)) {
338 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
339 temp | DEVEN_MCHBAR_EN);
341 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
342 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
347 intel_teardown_mchbar(struct drm_device *dev)
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
352 if (dev_priv->mchbar_need_disable) {
353 if (IS_I915G(dev) || IS_I915GM(dev)) {
356 pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
358 deven_val &= ~DEVEN_MCHBAR_EN;
359 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
364 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
367 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
372 if (dev_priv->mch_res.start)
373 release_resource(&dev_priv->mch_res);
376 /* true = enable decode, false = disable decoder */
377 static unsigned int i915_vga_set_decode(void *cookie, bool state)
379 struct drm_device *dev = cookie;
381 intel_modeset_vga_set_state(dev, state);
383 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
384 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
386 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
389 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
391 struct drm_device *dev = pci_get_drvdata(pdev);
392 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
394 if (state == VGA_SWITCHEROO_ON) {
395 pr_info("switched on\n");
396 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
397 /* i915 resume handler doesn't set to D0 */
398 pci_set_power_state(dev->pdev, PCI_D0);
399 i915_resume_switcheroo(dev);
400 dev->switch_power_state = DRM_SWITCH_POWER_ON;
402 pr_info("switched off\n");
403 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
404 i915_suspend_switcheroo(dev, pmm);
405 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
409 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
411 struct drm_device *dev = pci_get_drvdata(pdev);
414 * FIXME: open_count is protected by drm_global_mutex but that would lead to
415 * locking inversion with the driver load path. And the access here is
416 * completely racy anyway. So don't bother with locking for now.
418 return dev->open_count == 0;
421 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
422 .set_gpu_state = i915_switcheroo_set_state,
424 .can_switch = i915_switcheroo_can_switch,
427 static void i915_gem_fini(struct drm_device *dev)
429 struct drm_i915_private *dev_priv = to_i915(dev);
432 * Neither the BIOS, ourselves or any other kernel
433 * expects the system to be in execlists mode on startup,
434 * so we need to reset the GPU back to legacy mode. And the only
435 * known way to disable logical contexts is through a GPU reset.
437 * So in order to leave the system in a known default configuration,
438 * always reset the GPU upon unload. Afterwards we then clean up the
439 * GEM state tracking, flushing off the requests and leaving the
440 * system in a known idle state.
442 * Note that is of the upmost importance that the GPU is idle and
443 * all stray writes are flushed *before* we dismantle the backing
444 * storage for the pinned objects.
446 * However, since we are uncertain that reseting the GPU on older
447 * machines is a good idea, we don't - just in case it leaves the
448 * machine in an unusable condition.
450 if (HAS_HW_CONTEXTS(dev)) {
451 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
452 WARN_ON(reset && reset != -ENODEV);
455 mutex_lock(&dev->struct_mutex);
457 i915_gem_cleanup_engines(dev);
458 i915_gem_context_fini(dev);
459 mutex_unlock(&dev->struct_mutex);
461 WARN_ON(!list_empty(&to_i915(dev)->context_list));
464 static int i915_load_modeset_init(struct drm_device *dev)
466 struct drm_i915_private *dev_priv = dev->dev_private;
469 if (i915_inject_load_failure())
472 ret = intel_bios_init(dev_priv);
474 DRM_INFO("failed to find VBIOS tables\n");
476 /* If we have > 1 VGA cards, then we need to arbitrate access
477 * to the common VGA resources.
479 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
480 * then we do not take part in VGA arbitration and the
481 * vga_client_register() fails with -ENODEV.
483 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
484 if (ret && ret != -ENODEV)
487 intel_register_dsm_handler();
489 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
491 goto cleanup_vga_client;
493 /* must happen before intel_power_domains_init_hw() on VLV/CHV */
494 intel_update_rawclk(dev_priv);
496 intel_power_domains_init_hw(dev_priv, false);
498 intel_csr_ucode_init(dev_priv);
500 ret = intel_irq_install(dev_priv);
504 intel_setup_gmbus(dev);
506 /* Important: The output setup functions called by modeset_init need
507 * working irqs for e.g. gmbus and dp aux transfers. */
508 intel_modeset_init(dev);
512 ret = i915_gem_init(dev);
516 intel_modeset_gem_init(dev);
518 if (INTEL_INFO(dev)->num_pipes == 0)
521 ret = intel_fbdev_init(dev);
525 /* Only enable hotplug handling once the fbdev is fully set up. */
526 intel_hpd_init(dev_priv);
528 drm_kms_helper_poll_init(dev);
536 drm_irq_uninstall(dev);
537 intel_teardown_gmbus(dev);
539 intel_csr_ucode_fini(dev_priv);
540 intel_power_domains_fini(dev_priv);
541 vga_switcheroo_unregister_client(dev->pdev);
543 vga_client_register(dev->pdev, NULL, NULL, NULL);
548 #if IS_ENABLED(CONFIG_FB)
549 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
551 struct apertures_struct *ap;
552 struct pci_dev *pdev = dev_priv->dev->pdev;
553 struct i915_ggtt *ggtt = &dev_priv->ggtt;
557 ap = alloc_apertures(1);
561 ap->ranges[0].base = ggtt->mappable_base;
562 ap->ranges[0].size = ggtt->mappable_end;
565 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
567 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
574 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
580 #if !defined(CONFIG_VGA_CONSOLE)
581 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
585 #elif !defined(CONFIG_DUMMY_CONSOLE)
586 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
591 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
595 DRM_INFO("Replacing VGA console driver\n");
598 if (con_is_bound(&vga_con))
599 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
601 ret = do_unregister_con_driver(&vga_con);
603 /* Ignore "already unregistered". */
613 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
615 const struct intel_device_info *info = &dev_priv->info;
617 #define PRINT_S(name) "%s"
619 #define PRINT_FLAG(name) info->name ? #name "," : ""
621 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
622 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
624 dev_priv->dev->pdev->device,
625 dev_priv->dev->pdev->revision,
626 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
633 static void cherryview_sseu_info_init(struct drm_device *dev)
635 struct drm_i915_private *dev_priv = dev->dev_private;
636 struct intel_device_info *info;
639 info = (struct intel_device_info *)&dev_priv->info;
640 fuse = I915_READ(CHV_FUSE_GT);
642 info->slice_total = 1;
644 if (!(fuse & CHV_FGT_DISABLE_SS0)) {
645 info->subslice_per_slice++;
646 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
647 CHV_FGT_EU_DIS_SS0_R1_MASK);
648 info->eu_total += 8 - hweight32(eu_dis);
651 if (!(fuse & CHV_FGT_DISABLE_SS1)) {
652 info->subslice_per_slice++;
653 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
654 CHV_FGT_EU_DIS_SS1_R1_MASK);
655 info->eu_total += 8 - hweight32(eu_dis);
658 info->subslice_total = info->subslice_per_slice;
660 * CHV expected to always have a uniform distribution of EU
663 info->eu_per_subslice = info->subslice_total ?
664 info->eu_total / info->subslice_total :
667 * CHV supports subslice power gating on devices with more than
668 * one subslice, and supports EU power gating on devices with
669 * more than one EU pair per subslice.
671 info->has_slice_pg = 0;
672 info->has_subslice_pg = (info->subslice_total > 1);
673 info->has_eu_pg = (info->eu_per_subslice > 2);
676 static void gen9_sseu_info_init(struct drm_device *dev)
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 struct intel_device_info *info;
680 int s_max = 3, ss_max = 4, eu_max = 8;
682 u32 fuse2, s_enable, ss_disable, eu_disable;
685 info = (struct intel_device_info *)&dev_priv->info;
686 fuse2 = I915_READ(GEN8_FUSE2);
687 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
689 ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
690 GEN9_F2_SS_DIS_SHIFT;
692 info->slice_total = hweight32(s_enable);
694 * The subslice disable field is global, i.e. it applies
695 * to each of the enabled slices.
697 info->subslice_per_slice = ss_max - hweight32(ss_disable);
698 info->subslice_total = info->slice_total *
699 info->subslice_per_slice;
702 * Iterate through enabled slices and subslices to
703 * count the total enabled EU.
705 for (s = 0; s < s_max; s++) {
706 if (!(s_enable & (0x1 << s)))
707 /* skip disabled slice */
710 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
711 for (ss = 0; ss < ss_max; ss++) {
714 if (ss_disable & (0x1 << ss))
715 /* skip disabled subslice */
718 eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
722 * Record which subslice(s) has(have) 7 EUs. we
723 * can tune the hash used to spread work among
724 * subslices if they are unbalanced.
727 info->subslice_7eu[s] |= 1 << ss;
729 info->eu_total += eu_per_ss;
734 * SKL is expected to always have a uniform distribution
735 * of EU across subslices with the exception that any one
736 * EU in any one subslice may be fused off for die
737 * recovery. BXT is expected to be perfectly uniform in EU
740 info->eu_per_subslice = info->subslice_total ?
741 DIV_ROUND_UP(info->eu_total,
742 info->subslice_total) : 0;
744 * SKL supports slice power gating on devices with more than
745 * one slice, and supports EU power gating on devices with
746 * more than one EU pair per subslice. BXT supports subslice
747 * power gating on devices with more than one subslice, and
748 * supports EU power gating on devices with more than one EU
751 info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
752 (info->slice_total > 1));
753 info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
754 info->has_eu_pg = (info->eu_per_subslice > 2);
756 if (IS_BROXTON(dev)) {
757 #define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & (0x1 << ss))
759 * There is a HW issue in 2x6 fused down parts that requires
760 * Pooled EU to be enabled as a WA. The pool configuration
761 * changes depending upon which subslice is fused down. This
762 * doesn't affect if the device has all 3 subslices enabled.
764 /* WaEnablePooledEuFor2x6:bxt */
765 info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
766 (info->subslice_per_slice == 2 &&
767 INTEL_REVID(dev) < BXT_REVID_C0));
769 info->min_eu_in_pool = 0;
770 if (info->has_pooled_eu) {
771 if (IS_SS_DISABLED(ss_disable, 0) ||
772 IS_SS_DISABLED(ss_disable, 2))
773 info->min_eu_in_pool = 3;
774 else if (IS_SS_DISABLED(ss_disable, 1))
775 info->min_eu_in_pool = 6;
777 info->min_eu_in_pool = 9;
779 #undef IS_SS_DISABLED
783 static void broadwell_sseu_info_init(struct drm_device *dev)
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 struct intel_device_info *info;
787 const int s_max = 3, ss_max = 3, eu_max = 8;
789 u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
791 fuse2 = I915_READ(GEN8_FUSE2);
792 s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
793 ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
795 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
796 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
797 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
798 (32 - GEN8_EU_DIS0_S1_SHIFT));
799 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
800 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
801 (32 - GEN8_EU_DIS1_S2_SHIFT));
804 info = (struct intel_device_info *)&dev_priv->info;
805 info->slice_total = hweight32(s_enable);
808 * The subslice disable field is global, i.e. it applies
809 * to each of the enabled slices.
811 info->subslice_per_slice = ss_max - hweight32(ss_disable);
812 info->subslice_total = info->slice_total * info->subslice_per_slice;
815 * Iterate through enabled slices and subslices to
816 * count the total enabled EU.
818 for (s = 0; s < s_max; s++) {
819 if (!(s_enable & (0x1 << s)))
820 /* skip disabled slice */
823 for (ss = 0; ss < ss_max; ss++) {
826 if (ss_disable & (0x1 << ss))
827 /* skip disabled subslice */
830 n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
833 * Record which subslices have 7 EUs.
835 if (eu_max - n_disabled == 7)
836 info->subslice_7eu[s] |= 1 << ss;
838 info->eu_total += eu_max - n_disabled;
843 * BDW is expected to always have a uniform distribution of EU across
844 * subslices with the exception that any one EU in any one subslice may
845 * be fused off for die recovery.
847 info->eu_per_subslice = info->subslice_total ?
848 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
851 * BDW supports slice power gating on devices with more than
854 info->has_slice_pg = (info->slice_total > 1);
855 info->has_subslice_pg = 0;
860 * Determine various intel_device_info fields at runtime.
862 * Use it when either:
863 * - it's judged too laborious to fill n static structures with the limit
864 * when a simple if statement does the job,
865 * - run-time checks (eg read fuse/strap registers) are needed.
867 * This function needs to be called:
868 * - after the MMIO has been setup as we are reading registers,
869 * - after the PCH has been detected,
870 * - before the first usage of the fields it can tweak.
872 static void intel_device_info_runtime_init(struct drm_device *dev)
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 struct intel_device_info *info;
878 info = (struct intel_device_info *)&dev_priv->info;
881 * Skylake and Broxton currently don't expose the topmost plane as its
882 * use is exclusive with the legacy cursor and we only want to expose
883 * one of those, not both. Until we can safely expose the topmost plane
884 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
885 * we don't expose the topmost plane at all to prevent ABI breakage
888 if (IS_BROXTON(dev)) {
889 info->num_sprites[PIPE_A] = 2;
890 info->num_sprites[PIPE_B] = 2;
891 info->num_sprites[PIPE_C] = 1;
892 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
893 for_each_pipe(dev_priv, pipe)
894 info->num_sprites[pipe] = 2;
896 for_each_pipe(dev_priv, pipe)
897 info->num_sprites[pipe] = 1;
899 if (i915.disable_display) {
900 DRM_INFO("Display disabled (module parameter)\n");
902 } else if (info->num_pipes > 0 &&
903 (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
904 HAS_PCH_SPLIT(dev)) {
905 u32 fuse_strap = I915_READ(FUSE_STRAP);
906 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
909 * SFUSE_STRAP is supposed to have a bit signalling the display
910 * is fused off. Unfortunately it seems that, at least in
911 * certain cases, fused off display means that PCH display
912 * reads don't land anywhere. In that case, we read 0s.
914 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
915 * should be set when taking over after the firmware.
917 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
918 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
919 (dev_priv->pch_type == PCH_CPT &&
920 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
921 DRM_INFO("Display fused off, disabling\n");
923 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
924 DRM_INFO("PipeC fused off\n");
925 info->num_pipes -= 1;
927 } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
928 u32 dfsm = I915_READ(SKL_DFSM);
929 u8 disabled_mask = 0;
933 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
934 disabled_mask |= BIT(PIPE_A);
935 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
936 disabled_mask |= BIT(PIPE_B);
937 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
938 disabled_mask |= BIT(PIPE_C);
940 num_bits = hweight8(disabled_mask);
942 switch (disabled_mask) {
945 case BIT(PIPE_A) | BIT(PIPE_B):
946 case BIT(PIPE_A) | BIT(PIPE_C):
953 if (num_bits > info->num_pipes || invalid)
954 DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
957 info->num_pipes -= num_bits;
960 /* Initialize slice/subslice/EU info */
961 if (IS_CHERRYVIEW(dev))
962 cherryview_sseu_info_init(dev);
963 else if (IS_BROADWELL(dev))
964 broadwell_sseu_info_init(dev);
965 else if (INTEL_INFO(dev)->gen >= 9)
966 gen9_sseu_info_init(dev);
968 info->has_snoop = !info->has_llc;
970 /* Snooping is broken on BXT A stepping. */
971 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
972 info->has_snoop = false;
974 DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
975 DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
976 DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
977 DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
978 DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
979 DRM_DEBUG_DRIVER("Has Pooled EU: %s\n", HAS_POOLED_EU(dev) ? "y" : "n");
980 if (HAS_POOLED_EU(dev))
981 DRM_DEBUG_DRIVER("Min EU in pool: %u\n", info->min_eu_in_pool);
982 DRM_DEBUG_DRIVER("has slice power gating: %s\n",
983 info->has_slice_pg ? "y" : "n");
984 DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
985 info->has_subslice_pg ? "y" : "n");
986 DRM_DEBUG_DRIVER("has EU power gating: %s\n",
987 info->has_eu_pg ? "y" : "n");
989 i915.enable_execlists =
990 intel_sanitize_enable_execlists(dev_priv,
991 i915.enable_execlists);
994 * i915.enable_ppgtt is read-only, so do an early pass to validate the
995 * user's requested state against the hardware/driver capabilities. We
996 * do this now so that we can print out any log messages once rather
997 * than every time we check intel_enable_ppgtt().
1000 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1001 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1004 static void intel_init_dpio(struct drm_i915_private *dev_priv)
1007 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1008 * CHV x1 PHY (DP/HDMI D)
1009 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1011 if (IS_CHERRYVIEW(dev_priv)) {
1012 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1013 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1014 } else if (IS_VALLEYVIEW(dev_priv)) {
1015 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1019 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
1022 * The i915 workqueue is primarily used for batched retirement of
1023 * requests (and thus managing bo) once the task has been completed
1024 * by the GPU. i915_gem_retire_requests() is called directly when we
1025 * need high-priority retirement, such as waiting for an explicit
1028 * It is also used for periodic low-priority events, such as
1029 * idle-timers and recording error state.
1031 * All tasks on the workqueue are expected to acquire the dev mutex
1032 * so there is no point in running more than one instance of the
1033 * workqueue at any time. Use an ordered one.
1035 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1036 if (dev_priv->wq == NULL)
1039 dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1040 if (dev_priv->hotplug.dp_wq == NULL)
1043 dev_priv->gpu_error.hangcheck_wq =
1044 alloc_ordered_workqueue("i915-hangcheck", 0);
1045 if (dev_priv->gpu_error.hangcheck_wq == NULL)
1046 goto out_free_dp_wq;
1051 destroy_workqueue(dev_priv->hotplug.dp_wq);
1053 destroy_workqueue(dev_priv->wq);
1055 DRM_ERROR("Failed to allocate workqueues.\n");
1060 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
1062 destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1063 destroy_workqueue(dev_priv->hotplug.dp_wq);
1064 destroy_workqueue(dev_priv->wq);
1068 * i915_driver_init_early - setup state not requiring device access
1069 * @dev_priv: device private
1071 * Initialize everything that is a "SW-only" state, that is state not
1072 * requiring accessing the device or exposing the driver via kernel internal
1073 * or userspace interfaces. Example steps belonging here: lock initialization,
1074 * system memory allocation, setting up device specific attributes and
1075 * function hooks not requiring accessing the device.
1077 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1078 struct drm_device *dev,
1079 struct intel_device_info *info)
1081 struct intel_device_info *device_info;
1084 if (i915_inject_load_failure())
1087 /* Setup the write-once "constant" device info */
1088 device_info = (struct intel_device_info *)&dev_priv->info;
1089 memcpy(device_info, info, sizeof(dev_priv->info));
1090 device_info->device_id = dev->pdev->device;
1092 BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1093 device_info->gen_mask = BIT(device_info->gen - 1);
1095 spin_lock_init(&dev_priv->irq_lock);
1096 spin_lock_init(&dev_priv->gpu_error.lock);
1097 mutex_init(&dev_priv->backlight_lock);
1098 spin_lock_init(&dev_priv->uncore.lock);
1099 spin_lock_init(&dev_priv->mm.object_stat_lock);
1100 spin_lock_init(&dev_priv->mmio_flip_lock);
1101 mutex_init(&dev_priv->sb_lock);
1102 mutex_init(&dev_priv->modeset_restore_lock);
1103 mutex_init(&dev_priv->av_mutex);
1104 mutex_init(&dev_priv->wm.wm_mutex);
1105 mutex_init(&dev_priv->pps_mutex);
1107 ret = i915_workqueues_init(dev_priv);
1111 ret = intel_gvt_init(dev_priv);
1113 goto err_workqueues;
1115 /* This must be called before any calls to HAS_PCH_* */
1116 intel_detect_pch(dev);
1118 intel_pm_setup(dev);
1119 intel_init_dpio(dev_priv);
1120 intel_power_domains_init(dev_priv);
1121 intel_irq_init(dev_priv);
1122 intel_init_display_hooks(dev_priv);
1123 intel_init_clock_gating_hooks(dev_priv);
1124 intel_init_audio_hooks(dev_priv);
1125 i915_gem_load_init(dev);
1127 intel_display_crc_init(dev);
1129 i915_dump_device_info(dev_priv);
1131 /* Not all pre-production machines fall into this category, only the
1132 * very first ones. Almost everything should work, except for maybe
1133 * suspend/resume. And we don't implement workarounds that affect only
1134 * pre-production machines. */
1135 if (IS_HSW_EARLY_SDV(dev))
1136 DRM_INFO("This is an early pre-production Haswell machine. "
1137 "It may not be fully functional.\n");
1142 i915_workqueues_cleanup(dev_priv);
1147 * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1148 * @dev_priv: device private
1150 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1152 i915_gem_load_cleanup(dev_priv->dev);
1153 i915_workqueues_cleanup(dev_priv);
1156 static int i915_mmio_setup(struct drm_device *dev)
1158 struct drm_i915_private *dev_priv = to_i915(dev);
1162 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1164 * Before gen4, the registers and the GTT are behind different BARs.
1165 * However, from gen4 onwards, the registers and the GTT are shared
1166 * in the same BAR, so we want to restrict this ioremap from
1167 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1168 * the register BAR remains the same size for all the earlier
1169 * generations up to Ironlake.
1171 if (INTEL_INFO(dev)->gen < 5)
1172 mmio_size = 512 * 1024;
1174 mmio_size = 2 * 1024 * 1024;
1175 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1176 if (dev_priv->regs == NULL) {
1177 DRM_ERROR("failed to map registers\n");
1182 /* Try to make sure MCHBAR is enabled before poking at it */
1183 intel_setup_mchbar(dev);
1188 static void i915_mmio_cleanup(struct drm_device *dev)
1190 struct drm_i915_private *dev_priv = to_i915(dev);
1192 intel_teardown_mchbar(dev);
1193 pci_iounmap(dev->pdev, dev_priv->regs);
1197 * i915_driver_init_mmio - setup device MMIO
1198 * @dev_priv: device private
1200 * Setup minimal device state necessary for MMIO accesses later in the
1201 * initialization sequence. The setup here should avoid any other device-wide
1202 * side effects or exposing the driver via kernel internal or user space
1205 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1207 struct drm_device *dev = dev_priv->dev;
1210 if (i915_inject_load_failure())
1213 if (i915_get_bridge_dev(dev))
1216 ret = i915_mmio_setup(dev);
1220 intel_uncore_init(dev_priv);
1225 pci_dev_put(dev_priv->bridge_dev);
1231 * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1232 * @dev_priv: device private
1234 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1236 struct drm_device *dev = dev_priv->dev;
1238 intel_uncore_fini(dev_priv);
1239 i915_mmio_cleanup(dev);
1240 pci_dev_put(dev_priv->bridge_dev);
1244 * i915_driver_init_hw - setup state requiring device access
1245 * @dev_priv: device private
1247 * Setup state that requires accessing the device, but doesn't require
1248 * exposing the driver via kernel internal or userspace interfaces.
1250 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1252 struct drm_device *dev = dev_priv->dev;
1253 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1254 uint32_t aperture_size;
1257 if (i915_inject_load_failure())
1260 intel_device_info_runtime_init(dev);
1262 ret = i915_ggtt_init_hw(dev);
1266 ret = i915_ggtt_enable_hw(dev);
1268 DRM_ERROR("failed to enable GGTT\n");
1272 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1273 * otherwise the vga fbdev driver falls over. */
1274 ret = i915_kick_out_firmware_fb(dev_priv);
1276 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1280 ret = i915_kick_out_vgacon(dev_priv);
1282 DRM_ERROR("failed to remove conflicting VGA console\n");
1286 pci_set_master(dev->pdev);
1288 /* overlay on gen2 is broken and can't address above 1G */
1290 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1292 DRM_ERROR("failed to set DMA mask\n");
1299 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1300 * using 32bit addressing, overwriting memory if HWS is located
1303 * The documentation also mentions an issue with undefined
1304 * behaviour if any general state is accessed within a page above 4GB,
1305 * which also needs to be handled carefully.
1307 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1308 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1311 DRM_ERROR("failed to set DMA mask\n");
1317 aperture_size = ggtt->mappable_end;
1320 io_mapping_create_wc(ggtt->mappable_base,
1322 if (!ggtt->mappable) {
1327 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1330 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1331 PM_QOS_DEFAULT_VALUE);
1333 intel_uncore_sanitize(dev_priv);
1335 intel_opregion_setup(dev_priv);
1337 i915_gem_load_init_fences(dev_priv);
1339 /* On the 945G/GM, the chipset reports the MSI capability on the
1340 * integrated graphics even though the support isn't actually there
1341 * according to the published specs. It doesn't appear to function
1342 * correctly in testing on 945G.
1343 * This may be a side effect of MSI having been made available for PEG
1344 * and the registers being closely associated.
1346 * According to chipset errata, on the 965GM, MSI interrupts may
1347 * be lost or delayed, but we use them anyways to avoid
1348 * stuck interrupts on some machines.
1350 if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1351 if (pci_enable_msi(dev->pdev) < 0)
1352 DRM_DEBUG_DRIVER("can't enable MSI");
1358 i915_ggtt_cleanup_hw(dev);
1364 * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1365 * @dev_priv: device private
1367 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1369 struct drm_device *dev = dev_priv->dev;
1370 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1372 if (dev->pdev->msi_enabled)
1373 pci_disable_msi(dev->pdev);
1375 pm_qos_remove_request(&dev_priv->pm_qos);
1376 arch_phys_wc_del(ggtt->mtrr);
1377 io_mapping_free(ggtt->mappable);
1378 i915_ggtt_cleanup_hw(dev);
1382 * i915_driver_register - register the driver with the rest of the system
1383 * @dev_priv: device private
1385 * Perform any steps necessary to make the driver available via kernel
1386 * internal or userspace interfaces.
1388 static void i915_driver_register(struct drm_i915_private *dev_priv)
1390 struct drm_device *dev = dev_priv->dev;
1392 i915_gem_shrinker_init(dev_priv);
1394 * Notify a valid surface after modesetting,
1395 * when running inside a VM.
1397 if (intel_vgpu_active(dev_priv))
1398 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1400 i915_debugfs_register(dev_priv);
1401 i915_setup_sysfs(dev);
1402 intel_modeset_register(dev_priv);
1404 if (INTEL_INFO(dev_priv)->num_pipes) {
1405 /* Must be done after probing outputs */
1406 intel_opregion_register(dev_priv);
1407 acpi_video_register();
1410 if (IS_GEN5(dev_priv))
1411 intel_gpu_ips_init(dev_priv);
1413 i915_audio_component_init(dev_priv);
1416 * Some ports require correctly set-up hpd registers for detection to
1417 * work properly (leading to ghost connected connector status), e.g. VGA
1418 * on gm45. Hence we can only set up the initial fbdev config after hpd
1419 * irqs are fully enabled. We do it last so that the async config
1420 * cannot run before the connectors are registered.
1422 intel_fbdev_initial_config_async(dev);
1426 * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1427 * @dev_priv: device private
1429 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1431 i915_audio_component_cleanup(dev_priv);
1432 intel_gpu_ips_teardown();
1433 acpi_video_unregister();
1434 intel_opregion_unregister(dev_priv);
1435 intel_modeset_unregister(dev_priv);
1436 i915_teardown_sysfs(dev_priv->dev);
1437 i915_debugfs_unregister(dev_priv);
1438 i915_gem_shrinker_cleanup(dev_priv);
1442 * i915_driver_load - setup chip and create an initial config
1444 * @flags: startup flags
1446 * The driver load routine has to do several things:
1447 * - drive output discovery via intel_modeset_init()
1448 * - initialize the memory manager
1449 * - allocate initial config memory
1450 * - setup the DRM framebuffer with the allocated memory
1452 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1454 struct drm_i915_private *dev_priv;
1457 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1458 if (dev_priv == NULL)
1461 dev->dev_private = dev_priv;
1462 /* Must be set before calling __i915_printk */
1463 dev_priv->dev = dev;
1465 ret = i915_driver_init_early(dev_priv, dev,
1466 (struct intel_device_info *)flags);
1471 intel_runtime_pm_get(dev_priv);
1473 ret = i915_driver_init_mmio(dev_priv);
1475 goto out_runtime_pm_put;
1477 ret = i915_driver_init_hw(dev_priv);
1479 goto out_cleanup_mmio;
1482 * TODO: move the vblank init and parts of modeset init steps into one
1483 * of the i915_driver_init_/i915_driver_register functions according
1484 * to the role/effect of the given init step.
1486 if (INTEL_INFO(dev)->num_pipes) {
1487 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1489 goto out_cleanup_hw;
1492 ret = i915_load_modeset_init(dev);
1494 goto out_cleanup_vblank;
1496 i915_driver_register(dev_priv);
1498 intel_runtime_pm_enable(dev_priv);
1500 intel_runtime_pm_put(dev_priv);
1505 drm_vblank_cleanup(dev);
1507 i915_driver_cleanup_hw(dev_priv);
1509 i915_driver_cleanup_mmio(dev_priv);
1511 intel_runtime_pm_put(dev_priv);
1512 i915_driver_cleanup_early(dev_priv);
1514 i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1521 int i915_driver_unload(struct drm_device *dev)
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1526 intel_fbdev_fini(dev);
1528 intel_gvt_cleanup(dev_priv);
1530 ret = i915_gem_suspend(dev);
1532 DRM_ERROR("failed to idle hardware: %d\n", ret);
1536 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1538 i915_driver_unregister(dev_priv);
1540 drm_vblank_cleanup(dev);
1542 intel_modeset_cleanup(dev);
1545 * free the memory space allocated for the child device
1546 * config parsed from VBT
1548 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1549 kfree(dev_priv->vbt.child_dev);
1550 dev_priv->vbt.child_dev = NULL;
1551 dev_priv->vbt.child_dev_num = 0;
1553 kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1554 dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1555 kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1556 dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1558 vga_switcheroo_unregister_client(dev->pdev);
1559 vga_client_register(dev->pdev, NULL, NULL, NULL);
1561 intel_csr_ucode_fini(dev_priv);
1563 /* Free error state after interrupts are fully disabled. */
1564 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1565 i915_destroy_error_state(dev);
1567 /* Flush any outstanding unpin_work. */
1568 flush_workqueue(dev_priv->wq);
1570 intel_guc_fini(dev);
1572 intel_fbc_cleanup_cfb(dev_priv);
1574 intel_power_domains_fini(dev_priv);
1576 i915_driver_cleanup_hw(dev_priv);
1577 i915_driver_cleanup_mmio(dev_priv);
1579 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1581 i915_driver_cleanup_early(dev_priv);
1587 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1591 ret = i915_gem_open(dev, file);
1599 * i915_driver_lastclose - clean up after all DRM clients have exited
1602 * Take care of cleaning up after all DRM clients have exited. In the
1603 * mode setting case, we want to restore the kernel's initial mode (just
1604 * in case the last client left us in a bad state).
1606 * Additionally, in the non-mode setting case, we'll tear down the GTT
1607 * and DMA structures, since the kernel won't be using them, and clea
1610 void i915_driver_lastclose(struct drm_device *dev)
1612 intel_fbdev_restore_mode(dev);
1613 vga_switcheroo_process_delayed_switch();
1616 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1618 mutex_lock(&dev->struct_mutex);
1619 i915_gem_context_close(dev, file);
1620 i915_gem_release(dev, file);
1621 mutex_unlock(&dev->struct_mutex);
1624 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1626 struct drm_i915_file_private *file_priv = file->driver_priv;
1632 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1633 struct drm_file *file)
1638 const struct drm_ioctl_desc i915_ioctls[] = {
1639 DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1640 DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1641 DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1642 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1643 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1644 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1645 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1646 DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1647 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1648 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1649 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1650 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1651 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1652 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1653 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, drm_noop, DRM_AUTH),
1654 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1655 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1656 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1657 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1658 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
1659 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1660 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1661 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1662 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1663 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1664 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1665 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1666 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1667 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1668 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1669 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1670 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1671 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
1672 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1673 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1674 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
1675 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
1676 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1677 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
1678 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1679 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
1680 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
1681 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
1682 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
1683 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1684 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1685 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1686 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1687 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1688 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1689 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1690 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1693 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);