drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include <linux/acpi.h>
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34 #include "i915_drv.h"
  35 #include "i915_trace.h"
  36 #include "intel_drv.h"
  37
  38 #include <linux/apple-gmux.h>
  39 #include <linux/console.h>
  40 #include <linux/module.h>
  41 #include <linux/pm_runtime.h>
  42 #include <linux/vgaarb.h>
  43 #include <linux/vga_switcheroo.h>
  44 #include <drm/drm_crtc_helper.h>
  45
  46 static struct drm_driver driver;
  47
  48 #define GEN_DEFAULT_PIPEOFFSETS \
  49         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  50                           PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
  51         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  52                            TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
  53         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
  54
  55 #define GEN_CHV_PIPEOFFSETS \
  56         .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
  57                           CHV_PIPE_C_OFFSET }, \
  58         .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
  59                            CHV_TRANSCODER_C_OFFSET, }, \
  60         .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
  61                              CHV_PALETTE_C_OFFSET }
  62
  63 #define CURSOR_OFFSETS \
  64         .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
  65
  66 #define IVB_CURSOR_OFFSETS \
  67         .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
  68
  69 #define BDW_COLORS \
  70         .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
  71 #define CHV_COLORS \
  72         .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
  73
  74 static const struct intel_device_info intel_i830_info = {
  75         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
  76         .has_overlay = 1, .overlay_needs_physical = 1,
  77         .ring_mask = RENDER_RING,
  78         GEN_DEFAULT_PIPEOFFSETS,
  79         CURSOR_OFFSETS,
  80 };
  81
  82 static const struct intel_device_info intel_845g_info = {
  83         .gen = 2, .num_pipes = 1,
  84         .has_overlay = 1, .overlay_needs_physical = 1,
  85         .ring_mask = RENDER_RING,
  86         GEN_DEFAULT_PIPEOFFSETS,
  87         CURSOR_OFFSETS,
  88 };
  89
  90 static const struct intel_device_info intel_i85x_info = {
  91         .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
  92         .cursor_needs_physical = 1,
  93         .has_overlay = 1, .overlay_needs_physical = 1,
  94         .has_fbc = 1,
  95         .ring_mask = RENDER_RING,
  96         GEN_DEFAULT_PIPEOFFSETS,
  97         CURSOR_OFFSETS,
  98 };
  99
 100 static const struct intel_device_info intel_i865g_info = {
 101         .gen = 2, .num_pipes = 1,
 102         .has_overlay = 1, .overlay_needs_physical = 1,
 103         .ring_mask = RENDER_RING,
 104         GEN_DEFAULT_PIPEOFFSETS,
 105         CURSOR_OFFSETS,
 106 };
 107
 108 static const struct intel_device_info intel_i915g_info = {
 109         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 110         .has_overlay = 1, .overlay_needs_physical = 1,
 111         .ring_mask = RENDER_RING,
 112         GEN_DEFAULT_PIPEOFFSETS,
 113         CURSOR_OFFSETS,
 114 };
 115 static const struct intel_device_info intel_i915gm_info = {
 116         .gen = 3, .is_mobile = 1, .num_pipes = 2,
 117         .cursor_needs_physical = 1,
 118         .has_overlay = 1, .overlay_needs_physical = 1,
 119         .supports_tv = 1,
 120         .has_fbc = 1,
 121         .ring_mask = RENDER_RING,
 122         GEN_DEFAULT_PIPEOFFSETS,
 123         CURSOR_OFFSETS,
 124 };
 125 static const struct intel_device_info intel_i945g_info = {
 126         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
 127         .has_overlay = 1, .overlay_needs_physical = 1,
 128         .ring_mask = RENDER_RING,
 129         GEN_DEFAULT_PIPEOFFSETS,
 130         CURSOR_OFFSETS,
 131 };
 132 static const struct intel_device_info intel_i945gm_info = {
 133         .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
 134         .has_hotplug = 1, .cursor_needs_physical = 1,
 135         .has_overlay = 1, .overlay_needs_physical = 1,
 136         .supports_tv = 1,
 137         .has_fbc = 1,
 138         .ring_mask = RENDER_RING,
 139         GEN_DEFAULT_PIPEOFFSETS,
 140         CURSOR_OFFSETS,
 141 };
 142
 143 static const struct intel_device_info intel_i965g_info = {
 144         .gen = 4, .is_broadwater = 1, .num_pipes = 2,
 145         .has_hotplug = 1,
 146         .has_overlay = 1,
 147         .ring_mask = RENDER_RING,
 148         GEN_DEFAULT_PIPEOFFSETS,
 149         CURSOR_OFFSETS,
 150 };
 151
 152 static const struct intel_device_info intel_i965gm_info = {
 153         .gen = 4, .is_crestline = 1, .num_pipes = 2,
 154         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 155         .has_overlay = 1,
 156         .supports_tv = 1,
 157         .ring_mask = RENDER_RING,
 158         GEN_DEFAULT_PIPEOFFSETS,
 159         CURSOR_OFFSETS,
 160 };
 161
 162 static const struct intel_device_info intel_g33_info = {
 163         .gen = 3, .is_g33 = 1, .num_pipes = 2,
 164         .need_gfx_hws = 1, .has_hotplug = 1,
 165         .has_overlay = 1,
 166         .ring_mask = RENDER_RING,
 167         GEN_DEFAULT_PIPEOFFSETS,
 168         CURSOR_OFFSETS,
 169 };
 170
 171 static const struct intel_device_info intel_g45_info = {
 172         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
 173         .has_pipe_cxsr = 1, .has_hotplug = 1,
 174         .ring_mask = RENDER_RING | BSD_RING,
 175         GEN_DEFAULT_PIPEOFFSETS,
 176         CURSOR_OFFSETS,
 177 };
 178
 179 static const struct intel_device_info intel_gm45_info = {
 180         .gen = 4, .is_g4x = 1, .num_pipes = 2,
 181         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 182         .has_pipe_cxsr = 1, .has_hotplug = 1,
 183         .supports_tv = 1,
 184         .ring_mask = RENDER_RING | BSD_RING,
 185         GEN_DEFAULT_PIPEOFFSETS,
 186         CURSOR_OFFSETS,
 187 };
 188
 189 static const struct intel_device_info intel_pineview_info = {
 190         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
 191         .need_gfx_hws = 1, .has_hotplug = 1,
 192         .has_overlay = 1,
 193         GEN_DEFAULT_PIPEOFFSETS,
 194         CURSOR_OFFSETS,
 195 };
 196
 197 static const struct intel_device_info intel_ironlake_d_info = {
 198         .gen = 5, .num_pipes = 2,
 199         .need_gfx_hws = 1, .has_hotplug = 1,
 200         .ring_mask = RENDER_RING | BSD_RING,
 201         GEN_DEFAULT_PIPEOFFSETS,
 202         CURSOR_OFFSETS,
 203 };
 204
 205 static const struct intel_device_info intel_ironlake_m_info = {
 206         .gen = 5, .is_mobile = 1, .num_pipes = 2,
 207         .need_gfx_hws = 1, .has_hotplug = 1,
 208         .has_fbc = 1,
 209         .ring_mask = RENDER_RING | BSD_RING,
 210         GEN_DEFAULT_PIPEOFFSETS,
 211         CURSOR_OFFSETS,
 212 };
 213
 214 static const struct intel_device_info intel_sandybridge_d_info = {
 215         .gen = 6, .num_pipes = 2,
 216         .need_gfx_hws = 1, .has_hotplug = 1,
 217         .has_fbc = 1,
 218         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 219         .has_llc = 1,
 220         GEN_DEFAULT_PIPEOFFSETS,
 221         CURSOR_OFFSETS,
 222 };
 223
 224 static const struct intel_device_info intel_sandybridge_m_info = {
 225         .gen = 6, .is_mobile = 1, .num_pipes = 2,
 226         .need_gfx_hws = 1, .has_hotplug = 1,
 227         .has_fbc = 1,
 228         .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
 229         .has_llc = 1,
 230         GEN_DEFAULT_PIPEOFFSETS,
 231         CURSOR_OFFSETS,
 232 };
 233
 234 #define GEN7_FEATURES  \
 235         .gen = 7, .num_pipes = 3, \
 236         .need_gfx_hws = 1, .has_hotplug = 1, \
 237         .has_fbc = 1, \
 238         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 239         .has_llc = 1, \
 240         GEN_DEFAULT_PIPEOFFSETS, \
 241         IVB_CURSOR_OFFSETS
 242
 243 static const struct intel_device_info intel_ivybridge_d_info = {
 244         GEN7_FEATURES,
 245         .is_ivybridge = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_m_info = {
 249         GEN7_FEATURES,
 250         .is_ivybridge = 1,
 251         .is_mobile = 1,
 252 };
 253
 254 static const struct intel_device_info intel_ivybridge_q_info = {
 255         GEN7_FEATURES,
 256         .is_ivybridge = 1,
 257         .num_pipes = 0, /* legal, last one wins */
 258 };
 259
 260 #define VLV_FEATURES  \
 261         .gen = 7, .num_pipes = 2, \
 262         .need_gfx_hws = 1, .has_hotplug = 1, \
 263         .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
 264         .display_mmio_offset = VLV_DISPLAY_BASE, \
 265         GEN_DEFAULT_PIPEOFFSETS, \
 266         CURSOR_OFFSETS
 267
 268 static const struct intel_device_info intel_valleyview_m_info = {
 269         VLV_FEATURES,
 270         .is_valleyview = 1,
 271         .is_mobile = 1,
 272 };
 273
 274 static const struct intel_device_info intel_valleyview_d_info = {
 275         VLV_FEATURES,
 276         .is_valleyview = 1,
 277 };
 278
 279 #define HSW_FEATURES  \
 280         GEN7_FEATURES, \
 281         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
 282         .has_ddi = 1, \
 283         .has_fpga_dbg = 1
 284
 285 static const struct intel_device_info intel_haswell_d_info = {
 286         HSW_FEATURES,
 287         .is_haswell = 1,
 288 };
 289
 290 static const struct intel_device_info intel_haswell_m_info = {
 291         HSW_FEATURES,
 292         .is_haswell = 1,
 293         .is_mobile = 1,
 294 };
 295
 296 #define BDW_FEATURES \
 297         HSW_FEATURES, \
 298         BDW_COLORS
 299
 300 static const struct intel_device_info intel_broadwell_d_info = {
 301         BDW_FEATURES,
 302         .gen = 8,
 303 };
 304
 305 static const struct intel_device_info intel_broadwell_m_info = {
 306         BDW_FEATURES,
 307         .gen = 8, .is_mobile = 1,
 308 };
 309
 310 static const struct intel_device_info intel_broadwell_gt3d_info = {
 311         BDW_FEATURES,
 312         .gen = 8,
 313         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 314 };
 315
 316 static const struct intel_device_info intel_broadwell_gt3m_info = {
 317         BDW_FEATURES,
 318         .gen = 8, .is_mobile = 1,
 319         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 320 };
 321
 322 static const struct intel_device_info intel_cherryview_info = {
 323         .gen = 8, .num_pipes = 3,
 324         .need_gfx_hws = 1, .has_hotplug = 1,
 325         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 326         .is_cherryview = 1,
 327         .display_mmio_offset = VLV_DISPLAY_BASE,
 328         GEN_CHV_PIPEOFFSETS,
 329         CURSOR_OFFSETS,
 330         CHV_COLORS,
 331 };
 332
 333 static const struct intel_device_info intel_skylake_info = {
 334         BDW_FEATURES,
 335         .is_skylake = 1,
 336         .gen = 9,
 337 };
 338
 339 static const struct intel_device_info intel_skylake_gt3_info = {
 340         BDW_FEATURES,
 341         .is_skylake = 1,
 342         .gen = 9,
 343         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 344 };
 345
 346 static const struct intel_device_info intel_broxton_info = {
 347         .is_preliminary = 1,
 348         .is_broxton = 1,
 349         .gen = 9,
 350         .need_gfx_hws = 1, .has_hotplug = 1,
 351         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
 352         .num_pipes = 3,
 353         .has_ddi = 1,
 354         .has_fpga_dbg = 1,
 355         .has_fbc = 1,
 356         GEN_DEFAULT_PIPEOFFSETS,
 357         IVB_CURSOR_OFFSETS,
 358         BDW_COLORS,
 359 };
 360
 361 static const struct intel_device_info intel_kabylake_info = {
 362         BDW_FEATURES,
 363         .is_kabylake = 1,
 364         .gen = 9,
 365 };
 366
 367 static const struct intel_device_info intel_kabylake_gt3_info = {
 368         BDW_FEATURES,
 369         .is_kabylake = 1,
 370         .gen = 9,
 371         .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
 372 };
 373
 374 /*
 375  * Make sure any device matches here are from most specific to most
 376  * general.  For example, since the Quanta match is based on the subsystem
 377  * and subvendor IDs, we need it to come before the more general IVB
 378  * PCI ID matches, otherwise we'll use the wrong info struct above.
 379  */
 380 static const struct pci_device_id pciidlist[] = {
 381         INTEL_I830_IDS(&intel_i830_info),
 382         INTEL_I845G_IDS(&intel_845g_info),
 383         INTEL_I85X_IDS(&intel_i85x_info),
 384         INTEL_I865G_IDS(&intel_i865g_info),
 385         INTEL_I915G_IDS(&intel_i915g_info),
 386         INTEL_I915GM_IDS(&intel_i915gm_info),
 387         INTEL_I945G_IDS(&intel_i945g_info),
 388         INTEL_I945GM_IDS(&intel_i945gm_info),
 389         INTEL_I965G_IDS(&intel_i965g_info),
 390         INTEL_G33_IDS(&intel_g33_info),
 391         INTEL_I965GM_IDS(&intel_i965gm_info),
 392         INTEL_GM45_IDS(&intel_gm45_info),
 393         INTEL_G45_IDS(&intel_g45_info),
 394         INTEL_PINEVIEW_IDS(&intel_pineview_info),
 395         INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
 396         INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
 397         INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
 398         INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
 399         INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
 400         INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
 401         INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
 402         INTEL_HSW_D_IDS(&intel_haswell_d_info),
 403         INTEL_HSW_M_IDS(&intel_haswell_m_info),
 404         INTEL_VLV_M_IDS(&intel_valleyview_m_info),
 405         INTEL_VLV_D_IDS(&intel_valleyview_d_info),
 406         INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
 407         INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
 408         INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
 409         INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
 410         INTEL_CHV_IDS(&intel_cherryview_info),
 411         INTEL_SKL_GT1_IDS(&intel_skylake_info),
 412         INTEL_SKL_GT2_IDS(&intel_skylake_info),
 413         INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
 414         INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
 415         INTEL_BXT_IDS(&intel_broxton_info),
 416         INTEL_KBL_GT1_IDS(&intel_kabylake_info),
 417         INTEL_KBL_GT2_IDS(&intel_kabylake_info),
 418         INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
 419         INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
 420         {0, 0, 0}
 421 };
 422
 423 MODULE_DEVICE_TABLE(pci, pciidlist);
 424
 425 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 426 {
 427         enum intel_pch ret = PCH_NOP;
 428
 429         /*
 430          * In a virtualized passthrough environment we can be in a
 431          * setup where the ISA bridge is not able to be passed through.
 432          * In this case, a south bridge can be emulated and we have to
 433          * make an educated guess as to which PCH is really there.
 434          */
 435
 436         if (IS_GEN5(dev)) {
 437                 ret = PCH_IBX;
 438                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 439         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 440                 ret = PCH_CPT;
 441                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 442         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 443                 ret = PCH_LPT;
 444                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 445         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 446                 ret = PCH_SPT;
 447                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 448         }
 449
 450         return ret;
 451 }
 452
 453 void intel_detect_pch(struct drm_device *dev)
 454 {
 455         struct drm_i915_private *dev_priv = dev->dev_private;
 456         struct pci_dev *pch = NULL;
 457
 458         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 459          * (which really amounts to a PCH but no South Display).
 460          */
 461         if (INTEL_INFO(dev)->num_pipes == 0) {
 462                 dev_priv->pch_type = PCH_NOP;
 463                 return;
 464         }
 465
 466         /*
 467          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 468          * make graphics device passthrough work easy for VMM, that only
 469          * need to expose ISA bridge to let driver know the real hardware
 470          * underneath. This is a requirement from virtualization team.
 471          *
 472          * In some virtualized environments (e.g. XEN), there is irrelevant
 473          * ISA bridge in the system. To work reliably, we should scan trhough
 474          * all the ISA bridge devices and check for the first match, instead
 475          * of only checking the first one.
 476          */
 477         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 478                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 479                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 480                         dev_priv->pch_id = id;
 481
 482                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 483                                 dev_priv->pch_type = PCH_IBX;
 484                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 485                                 WARN_ON(!IS_GEN5(dev));
 486                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 487                                 dev_priv->pch_type = PCH_CPT;
 488                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 489                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 490                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 491                                 /* PantherPoint is CPT compatible */
 492                                 dev_priv->pch_type = PCH_CPT;
 493                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 494                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 495                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 496                                 dev_priv->pch_type = PCH_LPT;
 497                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 498                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 499                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 500                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 501                                 dev_priv->pch_type = PCH_LPT;
 502                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 503                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 504                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 505                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 506                                 dev_priv->pch_type = PCH_SPT;
 507                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 508                                 WARN_ON(!IS_SKYLAKE(dev) &&
 509                                         !IS_KABYLAKE(dev));
 510                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 511                                 dev_priv->pch_type = PCH_SPT;
 512                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 513                                 WARN_ON(!IS_SKYLAKE(dev) &&
 514                                         !IS_KABYLAKE(dev));
 515                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 516                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 517                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 518                                     pch->subsystem_vendor == 0x1af4 &&
 519                                     pch->subsystem_device == 0x1100)) {
 520                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 521                         } else
 522                                 continue;
 523
 524                         break;
 525                 }
 526         }
 527         if (!pch)
 528                 DRM_DEBUG_KMS("No PCH found.\n");
 529
 530         pci_dev_put(pch);
 531 }
 532
 533 bool i915_semaphore_is_enabled(struct drm_device *dev)
 534 {
 535         if (INTEL_INFO(dev)->gen < 6)
 536                 return false;
 537
 538         if (i915.semaphores >= 0)
 539                 return i915.semaphores;
 540
 541         /* TODO: make semaphores and Execlists play nicely together */
 542         if (i915.enable_execlists)
 543                 return false;
 544
 545         /* Until we get further testing... */
 546         if (IS_GEN8(dev))
 547                 return false;
 548
 549 #ifdef CONFIG_INTEL_IOMMU
 550         /* Enable semaphores on SNB when IO remapping is off */
 551         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
 552                 return false;
 553 #endif
 554
 555         return true;
 556 }
 557
 558 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 559 {
 560         struct drm_device *dev = dev_priv->dev;
 561         struct intel_encoder *encoder;
 562
 563         drm_modeset_lock_all(dev);
 564         for_each_intel_encoder(dev, encoder)
 565                 if (encoder->suspend)
 566                         encoder->suspend(encoder);
 567         drm_modeset_unlock_all(dev);
 568 }
 569
 570 static int intel_suspend_complete(struct drm_i915_private *dev_priv);
 571 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
 572                               bool rpm_resume);
 573 static int bxt_resume_prepare(struct drm_i915_private *dev_priv);
 574
 575 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
 576 {
 577 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
 578         if (acpi_target_system_state() < ACPI_STATE_S3)
 579                 return true;
 580 #endif
 581         return false;
 582 }
 583
 584 static int i915_drm_suspend(struct drm_device *dev)
 585 {
 586         struct drm_i915_private *dev_priv = dev->dev_private;
 587         pci_power_t opregion_target_state;
 588         int error;
 589
 590         /* ignore lid events during suspend */
 591         mutex_lock(&dev_priv->modeset_restore_lock);
 592         dev_priv->modeset_restore = MODESET_SUSPENDED;
 593         mutex_unlock(&dev_priv->modeset_restore_lock);
 594
 595         disable_rpm_wakeref_asserts(dev_priv);
 596
 597         /* We do a lot of poking in a lot of registers, make sure they work
 598          * properly. */
 599         intel_display_set_init_power(dev_priv, true);
 600
 601         drm_kms_helper_poll_disable(dev);
 602
 603         pci_save_state(dev->pdev);
 604
 605         error = i915_gem_suspend(dev);
 606         if (error) {
 607                 dev_err(&dev->pdev->dev,
 608                         "GEM idle failed, resume might fail\n");
 609                 goto out;
 610         }
 611
 612         intel_guc_suspend(dev);
 613
 614         intel_suspend_gt_powersave(dev);
 615
 616         intel_display_suspend(dev);
 617
 618         intel_dp_mst_suspend(dev);
 619
 620         intel_runtime_pm_disable_interrupts(dev_priv);
 621         intel_hpd_cancel_work(dev_priv);
 622
 623         intel_suspend_encoders(dev_priv);
 624
 625         intel_suspend_hw(dev);
 626
 627         i915_gem_suspend_gtt_mappings(dev);
 628
 629         i915_save_state(dev);
 630
 631         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
 632         intel_opregion_notify_adapter(dev, opregion_target_state);
 633
 634         intel_uncore_forcewake_reset(dev, false);
 635         intel_opregion_fini(dev);
 636
 637         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
 638
 639         dev_priv->suspend_count++;
 640
 641         intel_display_set_init_power(dev_priv, false);
 642
 643         intel_csr_ucode_suspend(dev_priv);
 644
 645 out:
 646         enable_rpm_wakeref_asserts(dev_priv);
 647
 648         return error;
 649 }
 650
 651 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
 652 {
 653         struct drm_i915_private *dev_priv = drm_dev->dev_private;
 654         bool fw_csr;
 655         int ret;
 656
 657         disable_rpm_wakeref_asserts(dev_priv);
 658
 659         fw_csr = !IS_BROXTON(dev_priv) &&
 660                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
 661         /*
 662          * In case of firmware assisted context save/restore don't manually
 663          * deinit the power domains. This also means the CSR/DMC firmware will
 664          * stay active, it will power down any HW resources as required and
 665          * also enable deeper system power states that would be blocked if the
 666          * firmware was inactive.
 667          */
 668         if (!fw_csr)
 669                 intel_power_domains_suspend(dev_priv);
 670
 671         ret = intel_suspend_complete(dev_priv);
 672
 673         if (ret) {
 674                 DRM_ERROR("Suspend complete failed: %d\n", ret);
 675                 if (!fw_csr)
 676                         intel_power_domains_init_hw(dev_priv, true);
 677
 678                 goto out;
 679         }
 680
 681         pci_disable_device(drm_dev->pdev);
 682         /*
 683          * During hibernation on some platforms the BIOS may try to access
 684          * the device even though it's already in D3 and hang the machine. So
 685          * leave the device in D0 on those platforms and hope the BIOS will
 686          * power down the device properly. The issue was seen on multiple old
 687          * GENs with different BIOS vendors, so having an explicit blacklist
 688          * is inpractical; apply the workaround on everything pre GEN6. The
 689          * platforms where the issue was seen:
 690          * Lenovo Thinkpad X301, X61s, X60, T60, X41
 691          * Fujitsu FSC S7110
 692          * Acer Aspire 1830T
 693          */
 694         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
 695                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
 696
 697         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
 698
 699 out:
 700         enable_rpm_wakeref_asserts(dev_priv);
 701
 702         return ret;
 703 }
 704
 705 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
 706 {
 707         int error;
 708
 709         if (!dev || !dev->dev_private) {
 710                 DRM_ERROR("dev: %p\n", dev);
 711                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 712                 return -ENODEV;
 713         }
 714
 715         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
 716                          state.event != PM_EVENT_FREEZE))
 717                 return -EINVAL;
 718
 719         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 720                 return 0;
 721
 722         error = i915_drm_suspend(dev);
 723         if (error)
 724                 return error;
 725
 726         return i915_drm_suspend_late(dev, false);
 727 }
 728
 729 static int i915_drm_resume(struct drm_device *dev)
 730 {
 731         struct drm_i915_private *dev_priv = dev->dev_private;
 732
 733         disable_rpm_wakeref_asserts(dev_priv);
 734
 735         intel_csr_ucode_resume(dev_priv);
 736
 737         mutex_lock(&dev->struct_mutex);
 738         i915_gem_restore_gtt_mappings(dev);
 739         mutex_unlock(&dev->struct_mutex);
 740
 741         i915_restore_state(dev);
 742         intel_opregion_setup(dev);
 743
 744         intel_init_pch_refclk(dev);
 745         drm_mode_config_reset(dev);
 746
 747         /*
 748          * Interrupts have to be enabled before any batches are run. If not the
 749          * GPU will hang. i915_gem_init_hw() will initiate batches to
 750          * update/restore the context.
 751          *
 752          * Modeset enabling in intel_modeset_init_hw() also needs working
 753          * interrupts.
 754          */
 755         intel_runtime_pm_enable_interrupts(dev_priv);
 756
 757         mutex_lock(&dev->struct_mutex);
 758         if (i915_gem_init_hw(dev)) {
 759                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
 760                         atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
 761         }
 762         mutex_unlock(&dev->struct_mutex);
 763
 764         intel_guc_resume(dev);
 765
 766         intel_modeset_init_hw(dev);
 767
 768         spin_lock_irq(&dev_priv->irq_lock);
 769         if (dev_priv->display.hpd_irq_setup)
 770                 dev_priv->display.hpd_irq_setup(dev);
 771         spin_unlock_irq(&dev_priv->irq_lock);
 772
 773         intel_dp_mst_resume(dev);
 774
 775         intel_display_resume(dev);
 776
 777         /*
 778          * ... but also need to make sure that hotplug processing
 779          * doesn't cause havoc. Like in the driver load code we don't
 780          * bother with the tiny race here where we might loose hotplug
 781          * notifications.
 782          * */
 783         intel_hpd_init(dev_priv);
 784         /* Config may have changed between suspend and resume */
 785         drm_helper_hpd_irq_event(dev);
 786
 787         intel_opregion_init(dev);
 788
 789         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
 790
 791         mutex_lock(&dev_priv->modeset_restore_lock);
 792         dev_priv->modeset_restore = MODESET_DONE;
 793         mutex_unlock(&dev_priv->modeset_restore_lock);
 794
 795         intel_opregion_notify_adapter(dev, PCI_D0);
 796
 797         drm_kms_helper_poll_enable(dev);
 798
 799         enable_rpm_wakeref_asserts(dev_priv);
 800
 801         return 0;
 802 }
 803
 804 static int i915_drm_resume_early(struct drm_device *dev)
 805 {
 806         struct drm_i915_private *dev_priv = dev->dev_private;
 807         int ret;
 808
 809         /*
 810          * We have a resume ordering issue with the snd-hda driver also
 811          * requiring our device to be power up. Due to the lack of a
 812          * parent/child relationship we currently solve this with an early
 813          * resume hook.
 814          *
 815          * FIXME: This should be solved with a special hdmi sink device or
 816          * similar so that power domains can be employed.
 817          */
 818
 819         /*
 820          * Note that we need to set the power state explicitly, since we
 821          * powered off the device during freeze and the PCI core won't power
 822          * it back up for us during thaw. Powering off the device during
 823          * freeze is not a hard requirement though, and during the
 824          * suspend/resume phases the PCI core makes sure we get here with the
 825          * device powered on. So in case we change our freeze logic and keep
 826          * the device powered we can also remove the following set power state
 827          * call.
 828          */
 829         ret = pci_set_power_state(dev->pdev, PCI_D0);
 830         if (ret) {
 831                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
 832                 goto out;
 833         }
 834
 835         /*
 836          * Note that pci_enable_device() first enables any parent bridge
 837          * device and only then sets the power state for this device. The
 838          * bridge enabling is a nop though, since bridge devices are resumed
 839          * first. The order of enabling power and enabling the device is
 840          * imposed by the PCI core as described above, so here we preserve the
 841          * same order for the freeze/thaw phases.
 842          *
 843          * TODO: eventually we should remove pci_disable_device() /
 844          * pci_enable_enable_device() from suspend/resume. Due to how they
 845          * depend on the device enable refcount we can't anyway depend on them
 846          * disabling/enabling the device.
 847          */
 848         if (pci_enable_device(dev->pdev)) {
 849                 ret = -EIO;
 850                 goto out;
 851         }
 852
 853         pci_set_master(dev->pdev);
 854
 855         disable_rpm_wakeref_asserts(dev_priv);
 856
 857         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 858                 ret = vlv_resume_prepare(dev_priv, false);
 859         if (ret)
 860                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
 861                           ret);
 862
 863         intel_uncore_early_sanitize(dev, true);
 864
 865         if (IS_BROXTON(dev))
 866                 ret = bxt_resume_prepare(dev_priv);
 867         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 868                 hsw_disable_pc8(dev_priv);
 869
 870         intel_uncore_sanitize(dev);
 871
 872         if (IS_BROXTON(dev_priv) ||
 873             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
 874                 intel_power_domains_init_hw(dev_priv, true);
 875
 876         enable_rpm_wakeref_asserts(dev_priv);
 877
 878 out:
 879         dev_priv->suspended_to_idle = false;
 880
 881         return ret;
 882 }
 883
 884 int i915_resume_switcheroo(struct drm_device *dev)
 885 {
 886         int ret;
 887
 888         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 889                 return 0;
 890
 891         ret = i915_drm_resume_early(dev);
 892         if (ret)
 893                 return ret;
 894
 895         return i915_drm_resume(dev);
 896 }
 897
 898 /**
 899  * i915_reset - reset chip after a hang
 900  * @dev: drm device to reset
 901  *
 902  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 903  * reset or otherwise an error code.
 904  *
 905  * Procedure is fairly simple:
 906  *   - reset the chip using the reset reg
 907  *   - re-init context state
 908  *   - re-init hardware status page
 909  *   - re-init ring buffer
 910  *   - re-init interrupt state
 911  *   - re-init display
 912  */
 913 int i915_reset(struct drm_device *dev)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         struct i915_gpu_error *error = &dev_priv->gpu_error;
 917         unsigned reset_counter;
 918         int ret;
 919
 920         intel_reset_gt_powersave(dev);
 921
 922         mutex_lock(&dev->struct_mutex);
 923
 924         /* Clear any previous failed attempts at recovery. Time to try again. */
 925         atomic_andnot(I915_WEDGED, &error->reset_counter);
 926
 927         /* Clear the reset-in-progress flag and increment the reset epoch. */
 928         reset_counter = atomic_inc_return(&error->reset_counter);
 929         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
 930                 ret = -EIO;
 931                 goto error;
 932         }
 933
 934         i915_gem_reset(dev);
 935
 936         ret = intel_gpu_reset(dev, ALL_ENGINES);
 937
 938         /* Also reset the gpu hangman. */
 939         if (error->stop_rings != 0) {
 940                 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
 941                 error->stop_rings = 0;
 942                 if (ret == -ENODEV) {
 943                         DRM_INFO("Reset not implemented, but ignoring "
 944                                  "error for simulated gpu hangs\n");
 945                         ret = 0;
 946                 }
 947         }
 948
 949         if (i915_stop_ring_allow_warn(dev_priv))
 950                 pr_notice("drm/i915: Resetting chip after gpu hang\n");
 951
 952         if (ret) {
 953                 if (ret != -ENODEV)
 954                         DRM_ERROR("Failed to reset chip: %i\n", ret);
 955                 else
 956                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
 957                 goto error;
 958         }
 959
 960         intel_overlay_reset(dev_priv);
 961
 962         /* Ok, now get things going again... */
 963
 964         /*
 965          * Everything depends on having the GTT running, so we need to start
 966          * there.  Fortunately we don't need to do this unless we reset the
 967          * chip at a PCI level.
 968          *
 969          * Next we need to restore the context, but we don't use those
 970          * yet either...
 971          *
 972          * Ring buffer needs to be re-initialized in the KMS case, or if X
 973          * was running at the time of the reset (i.e. we weren't VT
 974          * switched away).
 975          */
 976         ret = i915_gem_init_hw(dev);
 977         if (ret) {
 978                 DRM_ERROR("Failed hw init on reset %d\n", ret);
 979                 goto error;
 980         }
 981
 982         mutex_unlock(&dev->struct_mutex);
 983
 984         /*
 985          * rps/rc6 re-init is necessary to restore state lost after the
 986          * reset and the re-install of gt irqs. Skip for ironlake per
 987          * previous concerns that it doesn't respond well to some forms
 988          * of re-init after reset.
 989          */
 990         if (INTEL_INFO(dev)->gen > 5)
 991                 intel_enable_gt_powersave(dev);
 992
 993         return 0;
 994
 995 error:
 996         atomic_or(I915_WEDGED, &error->reset_counter);
 997         mutex_unlock(&dev->struct_mutex);
 998         return ret;
 999 }
1000
1001 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1002 {
1003         struct intel_device_info *intel_info =
1004                 (struct intel_device_info *) ent->driver_data;
1005
1006         if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
1007                 DRM_INFO("This hardware requires preliminary hardware support.\n"
1008                          "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1009                 return -ENODEV;
1010         }
1011
1012         /* Only bind to function 0 of the device. Early generations
1013          * used function 1 as a placeholder for multi-head. This causes
1014          * us confusion instead, especially on the systems where both
1015          * functions have the same PCI-ID!
1016          */
1017         if (PCI_FUNC(pdev->devfn))
1018                 return -ENODEV;
1019
1020         /*
1021          * apple-gmux is needed on dual GPU MacBook Pro
1022          * to probe the panel if we're the inactive GPU.
1023          */
1024         if (IS_ENABLED(CONFIG_VGA_ARB) && IS_ENABLED(CONFIG_VGA_SWITCHEROO) &&
1025             apple_gmux_present() && pdev != vga_default_device() &&
1026             !vga_switcheroo_handler_flags())
1027                 return -EPROBE_DEFER;
1028
1029         return drm_get_pci_dev(pdev, ent, &driver);
1030 }
1031
1032 static void
1033 i915_pci_remove(struct pci_dev *pdev)
1034 {
1035         struct drm_device *dev = pci_get_drvdata(pdev);
1036
1037         drm_put_dev(dev);
1038 }
1039
1040 static int i915_pm_suspend(struct device *dev)
1041 {
1042         struct pci_dev *pdev = to_pci_dev(dev);
1043         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1044
1045         if (!drm_dev || !drm_dev->dev_private) {
1046                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1047                 return -ENODEV;
1048         }
1049
1050         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1051                 return 0;
1052
1053         return i915_drm_suspend(drm_dev);
1054 }
1055
1056 static int i915_pm_suspend_late(struct device *dev)
1057 {
1058         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1059
1060         /*
1061          * We have a suspend ordering issue with the snd-hda driver also
1062          * requiring our device to be power up. Due to the lack of a
1063          * parent/child relationship we currently solve this with an late
1064          * suspend hook.
1065          *
1066          * FIXME: This should be solved with a special hdmi sink device or
1067          * similar so that power domains can be employed.
1068          */
1069         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1070                 return 0;
1071
1072         return i915_drm_suspend_late(drm_dev, false);
1073 }
1074
1075 static int i915_pm_poweroff_late(struct device *dev)
1076 {
1077         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1078
1079         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1080                 return 0;
1081
1082         return i915_drm_suspend_late(drm_dev, true);
1083 }
1084
1085 static int i915_pm_resume_early(struct device *dev)
1086 {
1087         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1088
1089         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1090                 return 0;
1091
1092         return i915_drm_resume_early(drm_dev);
1093 }
1094
1095 static int i915_pm_resume(struct device *dev)
1096 {
1097         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1098
1099         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1100                 return 0;
1101
1102         return i915_drm_resume(drm_dev);
1103 }
1104
1105 static int hsw_suspend_complete(struct drm_i915_private *dev_priv)
1106 {
1107         hsw_enable_pc8(dev_priv);
1108
1109         return 0;
1110 }
1111
1112 static int bxt_suspend_complete(struct drm_i915_private *dev_priv)
1113 {
1114         bxt_display_core_uninit(dev_priv);
1115         bxt_enable_dc9(dev_priv);
1116
1117         return 0;
1118 }
1119
1120 static int bxt_resume_prepare(struct drm_i915_private *dev_priv)
1121 {
1122         bxt_disable_dc9(dev_priv);
1123         bxt_display_core_init(dev_priv, true);
1124
1125         return 0;
1126 }
1127
1128 /*
1129  * Save all Gunit registers that may be lost after a D3 and a subsequent
1130  * S0i[R123] transition. The list of registers needing a save/restore is
1131  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1132  * registers in the following way:
1133  * - Driver: saved/restored by the driver
1134  * - Punit : saved/restored by the Punit firmware
1135  * - No, w/o marking: no need to save/restore, since the register is R/O or
1136  *                    used internally by the HW in a way that doesn't depend
1137  *                    keeping the content across a suspend/resume.
1138  * - Debug : used for debugging
1139  *
1140  * We save/restore all registers marked with 'Driver', with the following
1141  * exceptions:
1142  * - Registers out of use, including also registers marked with 'Debug'.
1143  *   These have no effect on the driver's operation, so we don't save/restore
1144  *   them to reduce the overhead.
1145  * - Registers that are fully setup by an initialization function called from
1146  *   the resume path. For example many clock gating and RPS/RC6 registers.
1147  * - Registers that provide the right functionality with their reset defaults.
1148  *
1149  * TODO: Except for registers that based on the above 3 criteria can be safely
1150  * ignored, we save/restore all others, practically treating the HW context as
1151  * a black-box for the driver. Further investigation is needed to reduce the
1152  * saved/restored registers even further, by following the same 3 criteria.
1153  */
1154 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1155 {
1156         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1157         int i;
1158
1159         /* GAM 0x4000-0x4770 */
1160         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1161         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1162         s->arb_mode             = I915_READ(ARB_MODE);
1163         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1164         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1165
1166         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1167                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1168
1169         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1170         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1171
1172         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1173         s->ecochk               = I915_READ(GAM_ECOCHK);
1174         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
1175         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
1176
1177         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
1178
1179         /* MBC 0x9024-0x91D0, 0x8500 */
1180         s->g3dctl               = I915_READ(VLV_G3DCTL);
1181         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
1182         s->mbctl                = I915_READ(GEN6_MBCTL);
1183
1184         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1185         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
1186         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
1187         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
1188         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
1189         s->rstctl               = I915_READ(GEN6_RSTCTL);
1190         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
1191
1192         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1193         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
1194         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
1195         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
1196         s->ecobus               = I915_READ(ECOBUS);
1197         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
1198         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1199         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
1200         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
1201         s->rcedata              = I915_READ(VLV_RCEDATA);
1202         s->spare2gh             = I915_READ(VLV_SPAREG2H);
1203
1204         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1205         s->gt_imr               = I915_READ(GTIMR);
1206         s->gt_ier               = I915_READ(GTIER);
1207         s->pm_imr               = I915_READ(GEN6_PMIMR);
1208         s->pm_ier               = I915_READ(GEN6_PMIER);
1209
1210         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1211                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1212
1213         /* GT SA CZ domain, 0x100000-0x138124 */
1214         s->tilectl              = I915_READ(TILECTL);
1215         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
1216         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
1217         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1218         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
1219
1220         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1221         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
1222         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
1223         s->pcbr                 = I915_READ(VLV_PCBR);
1224         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1225
1226         /*
1227          * Not saving any of:
1228          * DFT,         0x9800-0x9EC0
1229          * SARB,        0xB000-0xB1FC
1230          * GAC,         0x5208-0x524C, 0x14000-0x14C000
1231          * PCI CFG
1232          */
1233 }
1234
1235 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1236 {
1237         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1238         u32 val;
1239         int i;
1240
1241         /* GAM 0x4000-0x4770 */
1242         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
1243         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
1244         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
1245         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
1246         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
1247
1248         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1249                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1250
1251         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1252         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1253
1254         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1255         I915_WRITE(GAM_ECOCHK,          s->ecochk);
1256         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
1257         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
1258
1259         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
1260
1261         /* MBC 0x9024-0x91D0, 0x8500 */
1262         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
1263         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
1264         I915_WRITE(GEN6_MBCTL,          s->mbctl);
1265
1266         /* GCP 0x9400-0x9424, 0x8100-0x810C */
1267         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
1268         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
1269         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
1270         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
1271         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
1272         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
1273
1274         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1275         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
1276         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
1277         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
1278         I915_WRITE(ECOBUS,              s->ecobus);
1279         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
1280         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1281         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
1282         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
1283         I915_WRITE(VLV_RCEDATA,         s->rcedata);
1284         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
1285
1286         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1287         I915_WRITE(GTIMR,               s->gt_imr);
1288         I915_WRITE(GTIER,               s->gt_ier);
1289         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
1290         I915_WRITE(GEN6_PMIER,          s->pm_ier);
1291
1292         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1293                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1294
1295         /* GT SA CZ domain, 0x100000-0x138124 */
1296         I915_WRITE(TILECTL,                     s->tilectl);
1297         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
1298         /*
1299          * Preserve the GT allow wake and GFX force clock bit, they are not
1300          * be restored, as they are used to control the s0ix suspend/resume
1301          * sequence by the caller.
1302          */
1303         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1304         val &= VLV_GTLC_ALLOWWAKEREQ;
1305         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1306         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1307
1308         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1309         val &= VLV_GFX_CLK_FORCE_ON_BIT;
1310         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1311         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1312
1313         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
1314
1315         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1316         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
1317         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
1318         I915_WRITE(VLV_PCBR,                    s->pcbr);
1319         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
1320 }
1321
1322 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1323 {
1324         u32 val;
1325         int err;
1326
1327 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1328
1329         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1330         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1331         if (force_on)
1332                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1333         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1334
1335         if (!force_on)
1336                 return 0;
1337
1338         err = wait_for(COND, 20);
1339         if (err)
1340                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1341                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1342
1343         return err;
1344 #undef COND
1345 }
1346
1347 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1348 {
1349         u32 val;
1350         int err = 0;
1351
1352         val = I915_READ(VLV_GTLC_WAKE_CTRL);
1353         val &= ~VLV_GTLC_ALLOWWAKEREQ;
1354         if (allow)
1355                 val |= VLV_GTLC_ALLOWWAKEREQ;
1356         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1357         POSTING_READ(VLV_GTLC_WAKE_CTRL);
1358
1359 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1360               allow)
1361         err = wait_for(COND, 1);
1362         if (err)
1363                 DRM_ERROR("timeout disabling GT waking\n");
1364         return err;
1365 #undef COND
1366 }
1367
1368 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1369                                  bool wait_for_on)
1370 {
1371         u32 mask;
1372         u32 val;
1373         int err;
1374
1375         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1376         val = wait_for_on ? mask : 0;
1377 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1378         if (COND)
1379                 return 0;
1380
1381         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1382                       onoff(wait_for_on),
1383                       I915_READ(VLV_GTLC_PW_STATUS));
1384
1385         /*
1386          * RC6 transitioning can be delayed up to 2 msec (see
1387          * valleyview_enable_rps), use 3 msec for safety.
1388          */
1389         err = wait_for(COND, 3);
1390         if (err)
1391                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1392                           onoff(wait_for_on));
1393
1394         return err;
1395 #undef COND
1396 }
1397
1398 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1399 {
1400         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1401                 return;
1402
1403         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1404         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1405 }
1406
1407 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1408 {
1409         u32 mask;
1410         int err;
1411
1412         /*
1413          * Bspec defines the following GT well on flags as debug only, so
1414          * don't treat them as hard failures.
1415          */
1416         (void)vlv_wait_for_gt_wells(dev_priv, false);
1417
1418         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1419         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1420
1421         vlv_check_no_gt_access(dev_priv);
1422
1423         err = vlv_force_gfx_clock(dev_priv, true);
1424         if (err)
1425                 goto err1;
1426
1427         err = vlv_allow_gt_wake(dev_priv, false);
1428         if (err)
1429                 goto err2;
1430
1431         if (!IS_CHERRYVIEW(dev_priv))
1432                 vlv_save_gunit_s0ix_state(dev_priv);
1433
1434         err = vlv_force_gfx_clock(dev_priv, false);
1435         if (err)
1436                 goto err2;
1437
1438         return 0;
1439
1440 err2:
1441         /* For safety always re-enable waking and disable gfx clock forcing */
1442         vlv_allow_gt_wake(dev_priv, true);
1443 err1:
1444         vlv_force_gfx_clock(dev_priv, false);
1445
1446         return err;
1447 }
1448
1449 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1450                                 bool rpm_resume)
1451 {
1452         struct drm_device *dev = dev_priv->dev;
1453         int err;
1454         int ret;
1455
1456         /*
1457          * If any of the steps fail just try to continue, that's the best we
1458          * can do at this point. Return the first error code (which will also
1459          * leave RPM permanently disabled).
1460          */
1461         ret = vlv_force_gfx_clock(dev_priv, true);
1462
1463         if (!IS_CHERRYVIEW(dev_priv))
1464                 vlv_restore_gunit_s0ix_state(dev_priv);
1465
1466         err = vlv_allow_gt_wake(dev_priv, true);
1467         if (!ret)
1468                 ret = err;
1469
1470         err = vlv_force_gfx_clock(dev_priv, false);
1471         if (!ret)
1472                 ret = err;
1473
1474         vlv_check_no_gt_access(dev_priv);
1475
1476         if (rpm_resume) {
1477                 intel_init_clock_gating(dev);
1478                 i915_gem_restore_fences(dev);
1479         }
1480
1481         return ret;
1482 }
1483
1484 static int intel_runtime_suspend(struct device *device)
1485 {
1486         struct pci_dev *pdev = to_pci_dev(device);
1487         struct drm_device *dev = pci_get_drvdata(pdev);
1488         struct drm_i915_private *dev_priv = dev->dev_private;
1489         int ret;
1490
1491         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev))))
1492                 return -ENODEV;
1493
1494         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1495                 return -ENODEV;
1496
1497         DRM_DEBUG_KMS("Suspending device\n");
1498
1499         /*
1500          * We could deadlock here in case another thread holding struct_mutex
1501          * calls RPM suspend concurrently, since the RPM suspend will wait
1502          * first for this RPM suspend to finish. In this case the concurrent
1503          * RPM resume will be followed by its RPM suspend counterpart. Still
1504          * for consistency return -EAGAIN, which will reschedule this suspend.
1505          */
1506         if (!mutex_trylock(&dev->struct_mutex)) {
1507                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1508                 /*
1509                  * Bump the expiration timestamp, otherwise the suspend won't
1510                  * be rescheduled.
1511                  */
1512                 pm_runtime_mark_last_busy(device);
1513
1514                 return -EAGAIN;
1515         }
1516
1517         disable_rpm_wakeref_asserts(dev_priv);
1518
1519         /*
1520          * We are safe here against re-faults, since the fault handler takes
1521          * an RPM reference.
1522          */
1523         i915_gem_release_all_mmaps(dev_priv);
1524         mutex_unlock(&dev->struct_mutex);
1525
1526         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1527
1528         intel_guc_suspend(dev);
1529
1530         intel_suspend_gt_powersave(dev);
1531         intel_runtime_pm_disable_interrupts(dev_priv);
1532
1533         ret = intel_suspend_complete(dev_priv);
1534         if (ret) {
1535                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1536                 intel_runtime_pm_enable_interrupts(dev_priv);
1537
1538                 enable_rpm_wakeref_asserts(dev_priv);
1539
1540                 return ret;
1541         }
1542
1543         intel_uncore_forcewake_reset(dev, false);
1544
1545         enable_rpm_wakeref_asserts(dev_priv);
1546         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1547
1548         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1549                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1550
1551         dev_priv->pm.suspended = true;
1552
1553         /*
1554          * FIXME: We really should find a document that references the arguments
1555          * used below!
1556          */
1557         if (IS_BROADWELL(dev)) {
1558                 /*
1559                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1560                  * being detected, and the call we do at intel_runtime_resume()
1561                  * won't be able to restore them. Since PCI_D3hot matches the
1562                  * actual specification and appears to be working, use it.
1563                  */
1564                 intel_opregion_notify_adapter(dev, PCI_D3hot);
1565         } else {
1566                 /*
1567                  * current versions of firmware which depend on this opregion
1568                  * notification have repurposed the D1 definition to mean
1569                  * "runtime suspended" vs. what you would normally expect (D3)
1570                  * to distinguish it from notifications that might be sent via
1571                  * the suspend path.
1572                  */
1573                 intel_opregion_notify_adapter(dev, PCI_D1);
1574         }
1575
1576         assert_forcewakes_inactive(dev_priv);
1577
1578         DRM_DEBUG_KMS("Device suspended\n");
1579         return 0;
1580 }
1581
1582 static int intel_runtime_resume(struct device *device)
1583 {
1584         struct pci_dev *pdev = to_pci_dev(device);
1585         struct drm_device *dev = pci_get_drvdata(pdev);
1586         struct drm_i915_private *dev_priv = dev->dev_private;
1587         int ret = 0;
1588
1589         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1590                 return -ENODEV;
1591
1592         DRM_DEBUG_KMS("Resuming device\n");
1593
1594         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1595         disable_rpm_wakeref_asserts(dev_priv);
1596
1597         intel_opregion_notify_adapter(dev, PCI_D0);
1598         dev_priv->pm.suspended = false;
1599         if (intel_uncore_unclaimed_mmio(dev_priv))
1600                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1601
1602         intel_guc_resume(dev);
1603
1604         if (IS_GEN6(dev_priv))
1605                 intel_init_pch_refclk(dev);
1606
1607         if (IS_BROXTON(dev))
1608                 ret = bxt_resume_prepare(dev_priv);
1609         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1610                 hsw_disable_pc8(dev_priv);
1611         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1612                 ret = vlv_resume_prepare(dev_priv, true);
1613
1614         /*
1615          * No point of rolling back things in case of an error, as the best
1616          * we can do is to hope that things will still work (and disable RPM).
1617          */
1618         i915_gem_init_swizzling(dev);
1619         gen6_update_ring_freq(dev);
1620
1621         intel_runtime_pm_enable_interrupts(dev_priv);
1622
1623         /*
1624          * On VLV/CHV display interrupts are part of the display
1625          * power well, so hpd is reinitialized from there. For
1626          * everyone else do it here.
1627          */
1628         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1629                 intel_hpd_init(dev_priv);
1630
1631         intel_enable_gt_powersave(dev);
1632
1633         enable_rpm_wakeref_asserts(dev_priv);
1634
1635         if (ret)
1636                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1637         else
1638                 DRM_DEBUG_KMS("Device resumed\n");
1639
1640         return ret;
1641 }
1642
1643 /*
1644  * This function implements common functionality of runtime and system
1645  * suspend sequence.
1646  */
1647 static int intel_suspend_complete(struct drm_i915_private *dev_priv)
1648 {
1649         int ret;
1650
1651         if (IS_BROXTON(dev_priv))
1652                 ret = bxt_suspend_complete(dev_priv);
1653         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1654                 ret = hsw_suspend_complete(dev_priv);
1655         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1656                 ret = vlv_suspend_complete(dev_priv);
1657         else
1658                 ret = 0;
1659
1660         return ret;
1661 }
1662
1663 static const struct dev_pm_ops i915_pm_ops = {
1664         /*
1665          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1666          * PMSG_RESUME]
1667          */
1668         .suspend = i915_pm_suspend,
1669         .suspend_late = i915_pm_suspend_late,
1670         .resume_early = i915_pm_resume_early,
1671         .resume = i915_pm_resume,
1672
1673         /*
1674          * S4 event handlers
1675          * @freeze, @freeze_late    : called (1) before creating the
1676          *                            hibernation image [PMSG_FREEZE] and
1677          *                            (2) after rebooting, before restoring
1678          *                            the image [PMSG_QUIESCE]
1679          * @thaw, @thaw_early       : called (1) after creating the hibernation
1680          *                            image, before writing it [PMSG_THAW]
1681          *                            and (2) after failing to create or
1682          *                            restore the image [PMSG_RECOVER]
1683          * @poweroff, @poweroff_late: called after writing the hibernation
1684          *                            image, before rebooting [PMSG_HIBERNATE]
1685          * @restore, @restore_early : called after rebooting and restoring the
1686          *                            hibernation image [PMSG_RESTORE]
1687          */
1688         .freeze = i915_pm_suspend,
1689         .freeze_late = i915_pm_suspend_late,
1690         .thaw_early = i915_pm_resume_early,
1691         .thaw = i915_pm_resume,
1692         .poweroff = i915_pm_suspend,
1693         .poweroff_late = i915_pm_poweroff_late,
1694         .restore_early = i915_pm_resume_early,
1695         .restore = i915_pm_resume,
1696
1697         /* S0ix (via runtime suspend) event handlers */
1698         .runtime_suspend = intel_runtime_suspend,
1699         .runtime_resume = intel_runtime_resume,
1700 };
1701
1702 static const struct vm_operations_struct i915_gem_vm_ops = {
1703         .fault = i915_gem_fault,
1704         .open = drm_gem_vm_open,
1705         .close = drm_gem_vm_close,
1706 };
1707
1708 static const struct file_operations i915_driver_fops = {
1709         .owner = THIS_MODULE,
1710         .open = drm_open,
1711         .release = drm_release,
1712         .unlocked_ioctl = drm_ioctl,
1713         .mmap = drm_gem_mmap,
1714         .poll = drm_poll,
1715         .read = drm_read,
1716 #ifdef CONFIG_COMPAT
1717         .compat_ioctl = i915_compat_ioctl,
1718 #endif
1719         .llseek = noop_llseek,
1720 };
1721
1722 static struct drm_driver driver = {
1723         /* Don't use MTRRs here; the Xserver or userspace app should
1724          * deal with them for Intel hardware.
1725          */
1726         .driver_features =
1727             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1728             DRIVER_RENDER | DRIVER_MODESET,
1729         .load = i915_driver_load,
1730         .unload = i915_driver_unload,
1731         .open = i915_driver_open,
1732         .lastclose = i915_driver_lastclose,
1733         .preclose = i915_driver_preclose,
1734         .postclose = i915_driver_postclose,
1735         .set_busid = drm_pci_set_busid,
1736
1737 #if defined(CONFIG_DEBUG_FS)
1738         .debugfs_init = i915_debugfs_init,
1739         .debugfs_cleanup = i915_debugfs_cleanup,
1740 #endif
1741         .gem_free_object = i915_gem_free_object,
1742         .gem_vm_ops = &i915_gem_vm_ops,
1743
1744         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1745         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1746         .gem_prime_export = i915_gem_prime_export,
1747         .gem_prime_import = i915_gem_prime_import,
1748
1749         .dumb_create = i915_gem_dumb_create,
1750         .dumb_map_offset = i915_gem_mmap_gtt,
1751         .dumb_destroy = drm_gem_dumb_destroy,
1752         .ioctls = i915_ioctls,
1753         .fops = &i915_driver_fops,
1754         .name = DRIVER_NAME,
1755         .desc = DRIVER_DESC,
1756         .date = DRIVER_DATE,
1757         .major = DRIVER_MAJOR,
1758         .minor = DRIVER_MINOR,
1759         .patchlevel = DRIVER_PATCHLEVEL,
1760 };
1761
1762 static struct pci_driver i915_pci_driver = {
1763         .name = DRIVER_NAME,
1764         .id_table = pciidlist,
1765         .probe = i915_pci_probe,
1766         .remove = i915_pci_remove,
1767         .driver.pm = &i915_pm_ops,
1768 };
1769
1770 static int __init i915_init(void)
1771 {
1772         driver.num_ioctls = i915_max_ioctl;
1773
1774         /*
1775          * Enable KMS by default, unless explicitly overriden by
1776          * either the i915.modeset prarameter or by the
1777          * vga_text_mode_force boot option.
1778          */
1779
1780         if (i915.modeset == 0)
1781                 driver.driver_features &= ~DRIVER_MODESET;
1782
1783 #ifdef CONFIG_VGA_CONSOLE
1784         if (vgacon_text_force() && i915.modeset == -1)
1785                 driver.driver_features &= ~DRIVER_MODESET;
1786 #endif
1787
1788         if (!(driver.driver_features & DRIVER_MODESET)) {
1789                 /* Silently fail loading to not upset userspace. */
1790                 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1791                 return 0;
1792         }
1793
1794         if (i915.nuclear_pageflip)
1795                 driver.driver_features |= DRIVER_ATOMIC;
1796
1797         return drm_pci_init(&driver, &i915_pci_driver);
1798 }
1799
1800 static void __exit i915_exit(void)
1801 {
1802         if (!(driver.driver_features & DRIVER_MODESET))
1803                 return; /* Never loaded a driver. */
1804
1805         drm_pci_exit(&driver, &i915_pci_driver);
1806 }
1807
1808 module_init(i915_init);
1809 module_exit(i915_exit);
1810
1811 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1812 MODULE_AUTHOR("Intel Corporation");
1813
1814 MODULE_DESCRIPTION(DRIVER_DESC);
1815 MODULE_LICENSE("GPL and additional rights");