drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *dev = dev_priv->dev->dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(dev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = dev->dev_private;
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 208                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 209                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 210                                     pch->subsystem_vendor ==
 211                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 212                                     pch->subsystem_device ==
 213                                             PCI_SUBDEVICE_ID_QEMU)) {
 214                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 215                         } else
 216                                 continue;
 217
 218                         break;
 219                 }
 220         }
 221         if (!pch)
 222                 DRM_DEBUG_KMS("No PCH found.\n");
 223
 224         pci_dev_put(pch);
 225 }
 226
 227 bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
 228 {
 229         if (INTEL_GEN(dev_priv) < 6)
 230                 return false;
 231
 232         if (i915.semaphores >= 0)
 233                 return i915.semaphores;
 234
 235         /* TODO: make semaphores and Execlists play nicely together */
 236         if (i915.enable_execlists)
 237                 return false;
 238
 239 #ifdef CONFIG_INTEL_IOMMU
 240         /* Enable semaphores on SNB when IO remapping is off */
 241         if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
 242                 return false;
 243 #endif
 244
 245         return true;
 246 }
 247
 248 static int i915_getparam(struct drm_device *dev, void *data,
 249                          struct drm_file *file_priv)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252         drm_i915_getparam_t *param = data;
 253         int value;
 254
 255         switch (param->param) {
 256         case I915_PARAM_IRQ_ACTIVE:
 257         case I915_PARAM_ALLOW_BATCHBUFFER:
 258         case I915_PARAM_LAST_DISPATCH:
 259                 /* Reject all old ums/dri params. */
 260                 return -ENODEV;
 261         case I915_PARAM_CHIPSET_ID:
 262                 value = dev->pdev->device;
 263                 break;
 264         case I915_PARAM_REVISION:
 265                 value = dev->pdev->revision;
 266                 break;
 267         case I915_PARAM_HAS_GEM:
 268                 value = 1;
 269                 break;
 270         case I915_PARAM_NUM_FENCES_AVAIL:
 271                 value = dev_priv->num_fence_regs;
 272                 break;
 273         case I915_PARAM_HAS_OVERLAY:
 274                 value = dev_priv->overlay ? 1 : 0;
 275                 break;
 276         case I915_PARAM_HAS_PAGEFLIPPING:
 277                 value = 1;
 278                 break;
 279         case I915_PARAM_HAS_EXECBUF2:
 280                 /* depends on GEM */
 281                 value = 1;
 282                 break;
 283         case I915_PARAM_HAS_BSD:
 284                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 285                 break;
 286         case I915_PARAM_HAS_BLT:
 287                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 288                 break;
 289         case I915_PARAM_HAS_VEBOX:
 290                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 291                 break;
 292         case I915_PARAM_HAS_BSD2:
 293                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 294                 break;
 295         case I915_PARAM_HAS_RELAXED_FENCING:
 296                 value = 1;
 297                 break;
 298         case I915_PARAM_HAS_COHERENT_RINGS:
 299                 value = 1;
 300                 break;
 301         case I915_PARAM_HAS_EXEC_CONSTANTS:
 302                 value = INTEL_INFO(dev)->gen >= 4;
 303                 break;
 304         case I915_PARAM_HAS_RELAXED_DELTA:
 305                 value = 1;
 306                 break;
 307         case I915_PARAM_HAS_GEN7_SOL_RESET:
 308                 value = 1;
 309                 break;
 310         case I915_PARAM_HAS_LLC:
 311                 value = HAS_LLC(dev);
 312                 break;
 313         case I915_PARAM_HAS_WT:
 314                 value = HAS_WT(dev);
 315                 break;
 316         case I915_PARAM_HAS_ALIASING_PPGTT:
 317                 value = USES_PPGTT(dev);
 318                 break;
 319         case I915_PARAM_HAS_WAIT_TIMEOUT:
 320                 value = 1;
 321                 break;
 322         case I915_PARAM_HAS_SEMAPHORES:
 323                 value = i915_semaphore_is_enabled(dev_priv);
 324                 break;
 325         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 326                 value = 1;
 327                 break;
 328         case I915_PARAM_HAS_SECURE_BATCHES:
 329                 value = capable(CAP_SYS_ADMIN);
 330                 break;
 331         case I915_PARAM_HAS_PINNED_BATCHES:
 332                 value = 1;
 333                 break;
 334         case I915_PARAM_HAS_EXEC_NO_RELOC:
 335                 value = 1;
 336                 break;
 337         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 338                 value = 1;
 339                 break;
 340         case I915_PARAM_CMD_PARSER_VERSION:
 341                 value = i915_cmd_parser_get_version(dev_priv);
 342                 break;
 343         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 344                 value = 1;
 345                 break;
 346         case I915_PARAM_MMAP_VERSION:
 347                 value = 1;
 348                 break;
 349         case I915_PARAM_SUBSLICE_TOTAL:
 350                 value = INTEL_INFO(dev)->subslice_total;
 351                 if (!value)
 352                         return -ENODEV;
 353                 break;
 354         case I915_PARAM_EU_TOTAL:
 355                 value = INTEL_INFO(dev)->eu_total;
 356                 if (!value)
 357                         return -ENODEV;
 358                 break;
 359         case I915_PARAM_HAS_GPU_RESET:
 360                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 361                 break;
 362         case I915_PARAM_HAS_RESOURCE_STREAMER:
 363                 value = HAS_RESOURCE_STREAMER(dev);
 364                 break;
 365         case I915_PARAM_HAS_EXEC_SOFTPIN:
 366                 value = 1;
 367                 break;
 368         case I915_PARAM_HAS_POOLED_EU:
 369                 value = HAS_POOLED_EU(dev);
 370                 break;
 371         case I915_PARAM_MIN_EU_IN_POOL:
 372                 value = INTEL_INFO(dev)->min_eu_in_pool;
 373                 break;
 374         default:
 375                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 376                 return -EINVAL;
 377         }
 378
 379         if (put_user(value, param->value))
 380                 return -EFAULT;
 381
 382         return 0;
 383 }
 384
 385 static int i915_get_bridge_dev(struct drm_device *dev)
 386 {
 387         struct drm_i915_private *dev_priv = dev->dev_private;
 388
 389         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 390         if (!dev_priv->bridge_dev) {
 391                 DRM_ERROR("bridge device not found\n");
 392                 return -1;
 393         }
 394         return 0;
 395 }
 396
 397 /* Allocate space for the MCH regs if needed, return nonzero on error */
 398 static int
 399 intel_alloc_mchbar_resource(struct drm_device *dev)
 400 {
 401         struct drm_i915_private *dev_priv = dev->dev_private;
 402         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 403         u32 temp_lo, temp_hi = 0;
 404         u64 mchbar_addr;
 405         int ret;
 406
 407         if (INTEL_INFO(dev)->gen >= 4)
 408                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 409         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 410         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 411
 412         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 413 #ifdef CONFIG_PNP
 414         if (mchbar_addr &&
 415             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 416                 return 0;
 417 #endif
 418
 419         /* Get some space for it */
 420         dev_priv->mch_res.name = "i915 MCHBAR";
 421         dev_priv->mch_res.flags = IORESOURCE_MEM;
 422         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 423                                      &dev_priv->mch_res,
 424                                      MCHBAR_SIZE, MCHBAR_SIZE,
 425                                      PCIBIOS_MIN_MEM,
 426                                      0, pcibios_align_resource,
 427                                      dev_priv->bridge_dev);
 428         if (ret) {
 429                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 430                 dev_priv->mch_res.start = 0;
 431                 return ret;
 432         }
 433
 434         if (INTEL_INFO(dev)->gen >= 4)
 435                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 436                                        upper_32_bits(dev_priv->mch_res.start));
 437
 438         pci_write_config_dword(dev_priv->bridge_dev, reg,
 439                                lower_32_bits(dev_priv->mch_res.start));
 440         return 0;
 441 }
 442
 443 /* Setup MCHBAR if possible, return true if we should disable it again */
 444 static void
 445 intel_setup_mchbar(struct drm_device *dev)
 446 {
 447         struct drm_i915_private *dev_priv = dev->dev_private;
 448         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 449         u32 temp;
 450         bool enabled;
 451
 452         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 453                 return;
 454
 455         dev_priv->mchbar_need_disable = false;
 456
 457         if (IS_I915G(dev) || IS_I915GM(dev)) {
 458                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 459                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 460         } else {
 461                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 462                 enabled = temp & 1;
 463         }
 464
 465         /* If it's already enabled, don't have to do anything */
 466         if (enabled)
 467                 return;
 468
 469         if (intel_alloc_mchbar_resource(dev))
 470                 return;
 471
 472         dev_priv->mchbar_need_disable = true;
 473
 474         /* Space is allocated or reserved, so enable it. */
 475         if (IS_I915G(dev) || IS_I915GM(dev)) {
 476                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 477                                        temp | DEVEN_MCHBAR_EN);
 478         } else {
 479                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 480                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 481         }
 482 }
 483
 484 static void
 485 intel_teardown_mchbar(struct drm_device *dev)
 486 {
 487         struct drm_i915_private *dev_priv = dev->dev_private;
 488         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 489
 490         if (dev_priv->mchbar_need_disable) {
 491                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 492                         u32 deven_val;
 493
 494                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 495                                               &deven_val);
 496                         deven_val &= ~DEVEN_MCHBAR_EN;
 497                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 498                                                deven_val);
 499                 } else {
 500                         u32 mchbar_val;
 501
 502                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 503                                               &mchbar_val);
 504                         mchbar_val &= ~1;
 505                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 506                                                mchbar_val);
 507                 }
 508         }
 509
 510         if (dev_priv->mch_res.start)
 511                 release_resource(&dev_priv->mch_res);
 512 }
 513
 514 /* true = enable decode, false = disable decoder */
 515 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 516 {
 517         struct drm_device *dev = cookie;
 518
 519         intel_modeset_vga_set_state(dev, state);
 520         if (state)
 521                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 522                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 523         else
 524                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 525 }
 526
 527 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 528 {
 529         struct drm_device *dev = pci_get_drvdata(pdev);
 530         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 531
 532         if (state == VGA_SWITCHEROO_ON) {
 533                 pr_info("switched on\n");
 534                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 535                 /* i915 resume handler doesn't set to D0 */
 536                 pci_set_power_state(dev->pdev, PCI_D0);
 537                 i915_resume_switcheroo(dev);
 538                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 539         } else {
 540                 pr_info("switched off\n");
 541                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 542                 i915_suspend_switcheroo(dev, pmm);
 543                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 544         }
 545 }
 546
 547 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 548 {
 549         struct drm_device *dev = pci_get_drvdata(pdev);
 550
 551         /*
 552          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 553          * locking inversion with the driver load path. And the access here is
 554          * completely racy anyway. So don't bother with locking for now.
 555          */
 556         return dev->open_count == 0;
 557 }
 558
 559 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 560         .set_gpu_state = i915_switcheroo_set_state,
 561         .reprobe = NULL,
 562         .can_switch = i915_switcheroo_can_switch,
 563 };
 564
 565 static void i915_gem_fini(struct drm_device *dev)
 566 {
 567         struct drm_i915_private *dev_priv = to_i915(dev);
 568
 569         /*
 570          * Neither the BIOS, ourselves or any other kernel
 571          * expects the system to be in execlists mode on startup,
 572          * so we need to reset the GPU back to legacy mode. And the only
 573          * known way to disable logical contexts is through a GPU reset.
 574          *
 575          * So in order to leave the system in a known default configuration,
 576          * always reset the GPU upon unload. Afterwards we then clean up the
 577          * GEM state tracking, flushing off the requests and leaving the
 578          * system in a known idle state.
 579          *
 580          * Note that is of the upmost importance that the GPU is idle and
 581          * all stray writes are flushed *before* we dismantle the backing
 582          * storage for the pinned objects.
 583          *
 584          * However, since we are uncertain that reseting the GPU on older
 585          * machines is a good idea, we don't - just in case it leaves the
 586          * machine in an unusable condition.
 587          */
 588         if (HAS_HW_CONTEXTS(dev)) {
 589                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 590                 WARN_ON(reset && reset != -ENODEV);
 591         }
 592
 593         mutex_lock(&dev->struct_mutex);
 594         i915_gem_reset(dev);
 595         i915_gem_cleanup_engines(dev);
 596         i915_gem_context_fini(dev);
 597         mutex_unlock(&dev->struct_mutex);
 598
 599         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 600 }
 601
 602 static int i915_load_modeset_init(struct drm_device *dev)
 603 {
 604         struct drm_i915_private *dev_priv = dev->dev_private;
 605         int ret;
 606
 607         if (i915_inject_load_failure())
 608                 return -ENODEV;
 609
 610         ret = intel_bios_init(dev_priv);
 611         if (ret)
 612                 DRM_INFO("failed to find VBIOS tables\n");
 613
 614         /* If we have > 1 VGA cards, then we need to arbitrate access
 615          * to the common VGA resources.
 616          *
 617          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 618          * then we do not take part in VGA arbitration and the
 619          * vga_client_register() fails with -ENODEV.
 620          */
 621         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 622         if (ret && ret != -ENODEV)
 623                 goto out;
 624
 625         intel_register_dsm_handler();
 626
 627         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 628         if (ret)
 629                 goto cleanup_vga_client;
 630
 631         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 632         intel_update_rawclk(dev_priv);
 633
 634         intel_power_domains_init_hw(dev_priv, false);
 635
 636         intel_csr_ucode_init(dev_priv);
 637
 638         ret = intel_irq_install(dev_priv);
 639         if (ret)
 640                 goto cleanup_csr;
 641
 642         intel_setup_gmbus(dev);
 643
 644         /* Important: The output setup functions called by modeset_init need
 645          * working irqs for e.g. gmbus and dp aux transfers. */
 646         intel_modeset_init(dev);
 647
 648         intel_guc_init(dev);
 649
 650         ret = i915_gem_init(dev);
 651         if (ret)
 652                 goto cleanup_irq;
 653
 654         intel_modeset_gem_init(dev);
 655
 656         if (INTEL_INFO(dev)->num_pipes == 0)
 657                 return 0;
 658
 659         ret = intel_fbdev_init(dev);
 660         if (ret)
 661                 goto cleanup_gem;
 662
 663         /* Only enable hotplug handling once the fbdev is fully set up. */
 664         intel_hpd_init(dev_priv);
 665
 666         drm_kms_helper_poll_init(dev);
 667
 668         return 0;
 669
 670 cleanup_gem:
 671         i915_gem_fini(dev);
 672 cleanup_irq:
 673         intel_guc_fini(dev);
 674         drm_irq_uninstall(dev);
 675         intel_teardown_gmbus(dev);
 676 cleanup_csr:
 677         intel_csr_ucode_fini(dev_priv);
 678         intel_power_domains_fini(dev_priv);
 679         vga_switcheroo_unregister_client(dev->pdev);
 680 cleanup_vga_client:
 681         vga_client_register(dev->pdev, NULL, NULL, NULL);
 682 out:
 683         return ret;
 684 }
 685
 686 #if IS_ENABLED(CONFIG_FB)
 687 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 688 {
 689         struct apertures_struct *ap;
 690         struct pci_dev *pdev = dev_priv->dev->pdev;
 691         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 692         bool primary;
 693         int ret;
 694
 695         ap = alloc_apertures(1);
 696         if (!ap)
 697                 return -ENOMEM;
 698
 699         ap->ranges[0].base = ggtt->mappable_base;
 700         ap->ranges[0].size = ggtt->mappable_end;
 701
 702         primary =
 703                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 704
 705         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 706
 707         kfree(ap);
 708
 709         return ret;
 710 }
 711 #else
 712 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 713 {
 714         return 0;
 715 }
 716 #endif
 717
 718 #if !defined(CONFIG_VGA_CONSOLE)
 719 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 720 {
 721         return 0;
 722 }
 723 #elif !defined(CONFIG_DUMMY_CONSOLE)
 724 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 725 {
 726         return -ENODEV;
 727 }
 728 #else
 729 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 730 {
 731         int ret = 0;
 732
 733         DRM_INFO("Replacing VGA console driver\n");
 734
 735         console_lock();
 736         if (con_is_bound(&vga_con))
 737                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 738         if (ret == 0) {
 739                 ret = do_unregister_con_driver(&vga_con);
 740
 741                 /* Ignore "already unregistered". */
 742                 if (ret == -ENODEV)
 743                         ret = 0;
 744         }
 745         console_unlock();
 746
 747         return ret;
 748 }
 749 #endif
 750
 751 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 752 {
 753         const struct intel_device_info *info = &dev_priv->info;
 754
 755 #define PRINT_S(name) "%s"
 756 #define SEP_EMPTY
 757 #define PRINT_FLAG(name) info->name ? #name "," : ""
 758 #define SEP_COMMA ,
 759         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 760                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 761                          info->gen,
 762                          dev_priv->dev->pdev->device,
 763                          dev_priv->dev->pdev->revision,
 764                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 765 #undef PRINT_S
 766 #undef SEP_EMPTY
 767 #undef PRINT_FLAG
 768 #undef SEP_COMMA
 769 }
 770
 771 static void cherryview_sseu_info_init(struct drm_device *dev)
 772 {
 773         struct drm_i915_private *dev_priv = dev->dev_private;
 774         struct intel_device_info *info;
 775         u32 fuse, eu_dis;
 776
 777         info = (struct intel_device_info *)&dev_priv->info;
 778         fuse = I915_READ(CHV_FUSE_GT);
 779
 780         info->slice_total = 1;
 781
 782         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 783                 info->subslice_per_slice++;
 784                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 785                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 786                 info->eu_total += 8 - hweight32(eu_dis);
 787         }
 788
 789         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 790                 info->subslice_per_slice++;
 791                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 792                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 793                 info->eu_total += 8 - hweight32(eu_dis);
 794         }
 795
 796         info->subslice_total = info->subslice_per_slice;
 797         /*
 798          * CHV expected to always have a uniform distribution of EU
 799          * across subslices.
 800         */
 801         info->eu_per_subslice = info->subslice_total ?
 802                                 info->eu_total / info->subslice_total :
 803                                 0;
 804         /*
 805          * CHV supports subslice power gating on devices with more than
 806          * one subslice, and supports EU power gating on devices with
 807          * more than one EU pair per subslice.
 808         */
 809         info->has_slice_pg = 0;
 810         info->has_subslice_pg = (info->subslice_total > 1);
 811         info->has_eu_pg = (info->eu_per_subslice > 2);
 812 }
 813
 814 static void gen9_sseu_info_init(struct drm_device *dev)
 815 {
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         struct intel_device_info *info;
 818         int s_max = 3, ss_max = 4, eu_max = 8;
 819         int s, ss;
 820         u32 fuse2, s_enable, ss_disable, eu_disable;
 821         u8 eu_mask = 0xff;
 822
 823         info = (struct intel_device_info *)&dev_priv->info;
 824         fuse2 = I915_READ(GEN8_FUSE2);
 825         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 826                    GEN8_F2_S_ENA_SHIFT;
 827         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 828                      GEN9_F2_SS_DIS_SHIFT;
 829
 830         info->slice_total = hweight32(s_enable);
 831         /*
 832          * The subslice disable field is global, i.e. it applies
 833          * to each of the enabled slices.
 834         */
 835         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 836         info->subslice_total = info->slice_total *
 837                                info->subslice_per_slice;
 838
 839         /*
 840          * Iterate through enabled slices and subslices to
 841          * count the total enabled EU.
 842         */
 843         for (s = 0; s < s_max; s++) {
 844                 if (!(s_enable & (0x1 << s)))
 845                         /* skip disabled slice */
 846                         continue;
 847
 848                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 849                 for (ss = 0; ss < ss_max; ss++) {
 850                         int eu_per_ss;
 851
 852                         if (ss_disable & (0x1 << ss))
 853                                 /* skip disabled subslice */
 854                                 continue;
 855
 856                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 857                                                       eu_mask);
 858
 859                         /*
 860                          * Record which subslice(s) has(have) 7 EUs. we
 861                          * can tune the hash used to spread work among
 862                          * subslices if they are unbalanced.
 863                          */
 864                         if (eu_per_ss == 7)
 865                                 info->subslice_7eu[s] |= 1 << ss;
 866
 867                         info->eu_total += eu_per_ss;
 868                 }
 869         }
 870
 871         /*
 872          * SKL is expected to always have a uniform distribution
 873          * of EU across subslices with the exception that any one
 874          * EU in any one subslice may be fused off for die
 875          * recovery. BXT is expected to be perfectly uniform in EU
 876          * distribution.
 877         */
 878         info->eu_per_subslice = info->subslice_total ?
 879                                 DIV_ROUND_UP(info->eu_total,
 880                                              info->subslice_total) : 0;
 881         /*
 882          * SKL supports slice power gating on devices with more than
 883          * one slice, and supports EU power gating on devices with
 884          * more than one EU pair per subslice. BXT supports subslice
 885          * power gating on devices with more than one subslice, and
 886          * supports EU power gating on devices with more than one EU
 887          * pair per subslice.
 888         */
 889         info->has_slice_pg = ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
 890                                (info->slice_total > 1));
 891         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 892         info->has_eu_pg = (info->eu_per_subslice > 2);
 893
 894         if (IS_BROXTON(dev)) {
 895 #define IS_SS_DISABLED(_ss_disable, ss)    (_ss_disable & (0x1 << ss))
 896                 /*
 897                  * There is a HW issue in 2x6 fused down parts that requires
 898                  * Pooled EU to be enabled as a WA. The pool configuration
 899                  * changes depending upon which subslice is fused down. This
 900                  * doesn't affect if the device has all 3 subslices enabled.
 901                  */
 902                 /* WaEnablePooledEuFor2x6:bxt */
 903                 info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
 904                                        (info->subslice_per_slice == 2 &&
 905                                         INTEL_REVID(dev) < BXT_REVID_C0));
 906
 907                 info->min_eu_in_pool = 0;
 908                 if (info->has_pooled_eu) {
 909                         if (IS_SS_DISABLED(ss_disable, 0) ||
 910                             IS_SS_DISABLED(ss_disable, 2))
 911                                 info->min_eu_in_pool = 3;
 912                         else if (IS_SS_DISABLED(ss_disable, 1))
 913                                 info->min_eu_in_pool = 6;
 914                         else
 915                                 info->min_eu_in_pool = 9;
 916                 }
 917 #undef IS_SS_DISABLED
 918         }
 919 }
 920
 921 static void broadwell_sseu_info_init(struct drm_device *dev)
 922 {
 923         struct drm_i915_private *dev_priv = dev->dev_private;
 924         struct intel_device_info *info;
 925         const int s_max = 3, ss_max = 3, eu_max = 8;
 926         int s, ss;
 927         u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
 928
 929         fuse2 = I915_READ(GEN8_FUSE2);
 930         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
 931         ss_disable = (fuse2 & GEN8_F2_SS_DIS_MASK) >> GEN8_F2_SS_DIS_SHIFT;
 932
 933         eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK;
 934         eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) |
 935                         ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) <<
 936                          (32 - GEN8_EU_DIS0_S1_SHIFT));
 937         eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) |
 938                         ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
 939                          (32 - GEN8_EU_DIS1_S2_SHIFT));
 940
 941
 942         info = (struct intel_device_info *)&dev_priv->info;
 943         info->slice_total = hweight32(s_enable);
 944
 945         /*
 946          * The subslice disable field is global, i.e. it applies
 947          * to each of the enabled slices.
 948          */
 949         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 950         info->subslice_total = info->slice_total * info->subslice_per_slice;
 951
 952         /*
 953          * Iterate through enabled slices and subslices to
 954          * count the total enabled EU.
 955          */
 956         for (s = 0; s < s_max; s++) {
 957                 if (!(s_enable & (0x1 << s)))
 958                         /* skip disabled slice */
 959                         continue;
 960
 961                 for (ss = 0; ss < ss_max; ss++) {
 962                         u32 n_disabled;
 963
 964                         if (ss_disable & (0x1 << ss))
 965                                 /* skip disabled subslice */
 966                                 continue;
 967
 968                         n_disabled = hweight8(eu_disable[s] >> (ss * eu_max));
 969
 970                         /*
 971                          * Record which subslices have 7 EUs.
 972                          */
 973                         if (eu_max - n_disabled == 7)
 974                                 info->subslice_7eu[s] |= 1 << ss;
 975
 976                         info->eu_total += eu_max - n_disabled;
 977                 }
 978         }
 979
 980         /*
 981          * BDW is expected to always have a uniform distribution of EU across
 982          * subslices with the exception that any one EU in any one subslice may
 983          * be fused off for die recovery.
 984          */
 985         info->eu_per_subslice = info->subslice_total ?
 986                 DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
 987
 988         /*
 989          * BDW supports slice power gating on devices with more than
 990          * one slice.
 991          */
 992         info->has_slice_pg = (info->slice_total > 1);
 993         info->has_subslice_pg = 0;
 994         info->has_eu_pg = 0;
 995 }
 996
 997 /*
 998  * Determine various intel_device_info fields at runtime.
 999  *
1000  * Use it when either:
1001  *   - it's judged too laborious to fill n static structures with the limit
1002  *     when a simple if statement does the job,
1003  *   - run-time checks (eg read fuse/strap registers) are needed.
1004  *
1005  * This function needs to be called:
1006  *   - after the MMIO has been setup as we are reading registers,
1007  *   - after the PCH has been detected,
1008  *   - before the first usage of the fields it can tweak.
1009  */
1010 static void intel_device_info_runtime_init(struct drm_device *dev)
1011 {
1012         struct drm_i915_private *dev_priv = dev->dev_private;
1013         struct intel_device_info *info;
1014         enum pipe pipe;
1015
1016         info = (struct intel_device_info *)&dev_priv->info;
1017
1018         /*
1019          * Skylake and Broxton currently don't expose the topmost plane as its
1020          * use is exclusive with the legacy cursor and we only want to expose
1021          * one of those, not both. Until we can safely expose the topmost plane
1022          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
1023          * we don't expose the topmost plane at all to prevent ABI breakage
1024          * down the line.
1025          */
1026         if (IS_BROXTON(dev)) {
1027                 info->num_sprites[PIPE_A] = 2;
1028                 info->num_sprites[PIPE_B] = 2;
1029                 info->num_sprites[PIPE_C] = 1;
1030         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1031                 for_each_pipe(dev_priv, pipe)
1032                         info->num_sprites[pipe] = 2;
1033         else
1034                 for_each_pipe(dev_priv, pipe)
1035                         info->num_sprites[pipe] = 1;
1036
1037         if (i915.disable_display) {
1038                 DRM_INFO("Display disabled (module parameter)\n");
1039                 info->num_pipes = 0;
1040         } else if (info->num_pipes > 0 &&
1041                    (IS_GEN7(dev_priv) || IS_GEN8(dev_priv)) &&
1042                    HAS_PCH_SPLIT(dev)) {
1043                 u32 fuse_strap = I915_READ(FUSE_STRAP);
1044                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1045
1046                 /*
1047                  * SFUSE_STRAP is supposed to have a bit signalling the display
1048                  * is fused off. Unfortunately it seems that, at least in
1049                  * certain cases, fused off display means that PCH display
1050                  * reads don't land anywhere. In that case, we read 0s.
1051                  *
1052                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1053                  * should be set when taking over after the firmware.
1054                  */
1055                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1056                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1057                     (dev_priv->pch_type == PCH_CPT &&
1058                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1059                         DRM_INFO("Display fused off, disabling\n");
1060                         info->num_pipes = 0;
1061                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1062                         DRM_INFO("PipeC fused off\n");
1063                         info->num_pipes -= 1;
1064                 }
1065         } else if (info->num_pipes > 0 && IS_GEN9(dev_priv)) {
1066                 u32 dfsm = I915_READ(SKL_DFSM);
1067                 u8 disabled_mask = 0;
1068                 bool invalid;
1069                 int num_bits;
1070
1071                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE)
1072                         disabled_mask |= BIT(PIPE_A);
1073                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE)
1074                         disabled_mask |= BIT(PIPE_B);
1075                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE)
1076                         disabled_mask |= BIT(PIPE_C);
1077
1078                 num_bits = hweight8(disabled_mask);
1079
1080                 switch (disabled_mask) {
1081                 case BIT(PIPE_A):
1082                 case BIT(PIPE_B):
1083                 case BIT(PIPE_A) | BIT(PIPE_B):
1084                 case BIT(PIPE_A) | BIT(PIPE_C):
1085                         invalid = true;
1086                         break;
1087                 default:
1088                         invalid = false;
1089                 }
1090
1091                 if (num_bits > info->num_pipes || invalid)
1092                         DRM_ERROR("invalid pipe fuse configuration: 0x%x\n",
1093                                   disabled_mask);
1094                 else
1095                         info->num_pipes -= num_bits;
1096         }
1097
1098         /* Initialize slice/subslice/EU info */
1099         if (IS_CHERRYVIEW(dev))
1100                 cherryview_sseu_info_init(dev);
1101         else if (IS_BROADWELL(dev))
1102                 broadwell_sseu_info_init(dev);
1103         else if (INTEL_INFO(dev)->gen >= 9)
1104                 gen9_sseu_info_init(dev);
1105
1106         info->has_snoop = !info->has_llc;
1107
1108         /* Snooping is broken on BXT A stepping. */
1109         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
1110                 info->has_snoop = false;
1111
1112         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
1113         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
1114         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
1115         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
1116         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
1117         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
1118                          info->has_slice_pg ? "y" : "n");
1119         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
1120                          info->has_subslice_pg ? "y" : "n");
1121         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
1122                          info->has_eu_pg ? "y" : "n");
1123
1124         i915.enable_execlists =
1125                 intel_sanitize_enable_execlists(dev_priv,
1126                                                 i915.enable_execlists);
1127
1128         /*
1129          * i915.enable_ppgtt is read-only, so do an early pass to validate the
1130          * user's requested state against the hardware/driver capabilities.  We
1131          * do this now so that we can print out any log messages once rather
1132          * than every time we check intel_enable_ppgtt().
1133          */
1134         i915.enable_ppgtt =
1135                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
1136         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
1137 }
1138
1139 static void intel_init_dpio(struct drm_i915_private *dev_priv)
1140 {
1141         /*
1142          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1143          * CHV x1 PHY (DP/HDMI D)
1144          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1145          */
1146         if (IS_CHERRYVIEW(dev_priv)) {
1147                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1148                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1149         } else if (IS_VALLEYVIEW(dev_priv)) {
1150                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1151         }
1152 }
1153
1154 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
1155 {
1156         /*
1157          * The i915 workqueue is primarily used for batched retirement of
1158          * requests (and thus managing bo) once the task has been completed
1159          * by the GPU. i915_gem_retire_requests() is called directly when we
1160          * need high-priority retirement, such as waiting for an explicit
1161          * bo.
1162          *
1163          * It is also used for periodic low-priority events, such as
1164          * idle-timers and recording error state.
1165          *
1166          * All tasks on the workqueue are expected to acquire the dev mutex
1167          * so there is no point in running more than one instance of the
1168          * workqueue at any time.  Use an ordered one.
1169          */
1170         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1171         if (dev_priv->wq == NULL)
1172                 goto out_err;
1173
1174         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1175         if (dev_priv->hotplug.dp_wq == NULL)
1176                 goto out_free_wq;
1177
1178         return 0;
1179
1180 out_free_wq:
1181         destroy_workqueue(dev_priv->wq);
1182 out_err:
1183         DRM_ERROR("Failed to allocate workqueues.\n");
1184
1185         return -ENOMEM;
1186 }
1187
1188 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
1189 {
1190         destroy_workqueue(dev_priv->hotplug.dp_wq);
1191         destroy_workqueue(dev_priv->wq);
1192 }
1193
1194 /**
1195  * i915_driver_init_early - setup state not requiring device access
1196  * @dev_priv: device private
1197  *
1198  * Initialize everything that is a "SW-only" state, that is state not
1199  * requiring accessing the device or exposing the driver via kernel internal
1200  * or userspace interfaces. Example steps belonging here: lock initialization,
1201  * system memory allocation, setting up device specific attributes and
1202  * function hooks not requiring accessing the device.
1203  */
1204 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
1205                                   const struct pci_device_id *ent)
1206 {
1207         const struct intel_device_info *match_info =
1208                 (struct intel_device_info *)ent->driver_data;
1209         struct intel_device_info *device_info;
1210         int ret = 0;
1211
1212         if (i915_inject_load_failure())
1213                 return -ENODEV;
1214
1215         /* Setup the write-once "constant" device info */
1216         device_info = (struct intel_device_info *)&dev_priv->info;
1217         memcpy(device_info, match_info, sizeof(*device_info));
1218         device_info->device_id = dev_priv->drm.pdev->device;
1219
1220         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
1221         device_info->gen_mask = BIT(device_info->gen - 1);
1222
1223         spin_lock_init(&dev_priv->irq_lock);
1224         spin_lock_init(&dev_priv->gpu_error.lock);
1225         mutex_init(&dev_priv->backlight_lock);
1226         spin_lock_init(&dev_priv->uncore.lock);
1227         spin_lock_init(&dev_priv->mm.object_stat_lock);
1228         spin_lock_init(&dev_priv->mmio_flip_lock);
1229         mutex_init(&dev_priv->sb_lock);
1230         mutex_init(&dev_priv->modeset_restore_lock);
1231         mutex_init(&dev_priv->av_mutex);
1232         mutex_init(&dev_priv->wm.wm_mutex);
1233         mutex_init(&dev_priv->pps_mutex);
1234
1235         ret = i915_workqueues_init(dev_priv);
1236         if (ret < 0)
1237                 return ret;
1238
1239         ret = intel_gvt_init(dev_priv);
1240         if (ret < 0)
1241                 goto err_workqueues;
1242
1243         /* This must be called before any calls to HAS_PCH_* */
1244         intel_detect_pch(&dev_priv->drm);
1245
1246         intel_pm_setup(&dev_priv->drm);
1247         intel_init_dpio(dev_priv);
1248         intel_power_domains_init(dev_priv);
1249         intel_irq_init(dev_priv);
1250         intel_init_display_hooks(dev_priv);
1251         intel_init_clock_gating_hooks(dev_priv);
1252         intel_init_audio_hooks(dev_priv);
1253         i915_gem_load_init(&dev_priv->drm);
1254
1255         intel_display_crc_init(&dev_priv->drm);
1256
1257         i915_dump_device_info(dev_priv);
1258
1259         /* Not all pre-production machines fall into this category, only the
1260          * very first ones. Almost everything should work, except for maybe
1261          * suspend/resume. And we don't implement workarounds that affect only
1262          * pre-production machines. */
1263         if (IS_HSW_EARLY_SDV(dev_priv))
1264                 DRM_INFO("This is an early pre-production Haswell machine. "
1265                          "It may not be fully functional.\n");
1266
1267         return 0;
1268
1269 err_workqueues:
1270         i915_workqueues_cleanup(dev_priv);
1271         return ret;
1272 }
1273
1274 /**
1275  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
1276  * @dev_priv: device private
1277  */
1278 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
1279 {
1280         i915_gem_load_cleanup(dev_priv->dev);
1281         i915_workqueues_cleanup(dev_priv);
1282 }
1283
1284 static int i915_mmio_setup(struct drm_device *dev)
1285 {
1286         struct drm_i915_private *dev_priv = to_i915(dev);
1287         int mmio_bar;
1288         int mmio_size;
1289
1290         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1291         /*
1292          * Before gen4, the registers and the GTT are behind different BARs.
1293          * However, from gen4 onwards, the registers and the GTT are shared
1294          * in the same BAR, so we want to restrict this ioremap from
1295          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1296          * the register BAR remains the same size for all the earlier
1297          * generations up to Ironlake.
1298          */
1299         if (INTEL_INFO(dev)->gen < 5)
1300                 mmio_size = 512 * 1024;
1301         else
1302                 mmio_size = 2 * 1024 * 1024;
1303         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1304         if (dev_priv->regs == NULL) {
1305                 DRM_ERROR("failed to map registers\n");
1306
1307                 return -EIO;
1308         }
1309
1310         /* Try to make sure MCHBAR is enabled before poking at it */
1311         intel_setup_mchbar(dev);
1312
1313         return 0;
1314 }
1315
1316 static void i915_mmio_cleanup(struct drm_device *dev)
1317 {
1318         struct drm_i915_private *dev_priv = to_i915(dev);
1319
1320         intel_teardown_mchbar(dev);
1321         pci_iounmap(dev->pdev, dev_priv->regs);
1322 }
1323
1324 /**
1325  * i915_driver_init_mmio - setup device MMIO
1326  * @dev_priv: device private
1327  *
1328  * Setup minimal device state necessary for MMIO accesses later in the
1329  * initialization sequence. The setup here should avoid any other device-wide
1330  * side effects or exposing the driver via kernel internal or user space
1331  * interfaces.
1332  */
1333 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
1334 {
1335         struct drm_device *dev = dev_priv->dev;
1336         int ret;
1337
1338         if (i915_inject_load_failure())
1339                 return -ENODEV;
1340
1341         if (i915_get_bridge_dev(dev))
1342                 return -EIO;
1343
1344         ret = i915_mmio_setup(dev);
1345         if (ret < 0)
1346                 goto put_bridge;
1347
1348         intel_uncore_init(dev_priv);
1349
1350         return 0;
1351
1352 put_bridge:
1353         pci_dev_put(dev_priv->bridge_dev);
1354
1355         return ret;
1356 }
1357
1358 /**
1359  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
1360  * @dev_priv: device private
1361  */
1362 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
1363 {
1364         struct drm_device *dev = dev_priv->dev;
1365
1366         intel_uncore_fini(dev_priv);
1367         i915_mmio_cleanup(dev);
1368         pci_dev_put(dev_priv->bridge_dev);
1369 }
1370
1371 /**
1372  * i915_driver_init_hw - setup state requiring device access
1373  * @dev_priv: device private
1374  *
1375  * Setup state that requires accessing the device, but doesn't require
1376  * exposing the driver via kernel internal or userspace interfaces.
1377  */
1378 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1379 {
1380         struct drm_device *dev = dev_priv->dev;
1381         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1382         uint32_t aperture_size;
1383         int ret;
1384
1385         if (i915_inject_load_failure())
1386                 return -ENODEV;
1387
1388         intel_device_info_runtime_init(dev);
1389
1390         ret = i915_ggtt_init_hw(dev);
1391         if (ret)
1392                 return ret;
1393
1394         ret = i915_ggtt_enable_hw(dev);
1395         if (ret) {
1396                 DRM_ERROR("failed to enable GGTT\n");
1397                 goto out_ggtt;
1398         }
1399
1400         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1401          * otherwise the vga fbdev driver falls over. */
1402         ret = i915_kick_out_firmware_fb(dev_priv);
1403         if (ret) {
1404                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1405                 goto out_ggtt;
1406         }
1407
1408         ret = i915_kick_out_vgacon(dev_priv);
1409         if (ret) {
1410                 DRM_ERROR("failed to remove conflicting VGA console\n");
1411                 goto out_ggtt;
1412         }
1413
1414         pci_set_master(dev->pdev);
1415
1416         /* overlay on gen2 is broken and can't address above 1G */
1417         if (IS_GEN2(dev)) {
1418                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1419                 if (ret) {
1420                         DRM_ERROR("failed to set DMA mask\n");
1421
1422                         goto out_ggtt;
1423                 }
1424         }
1425
1426
1427         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1428          * using 32bit addressing, overwriting memory if HWS is located
1429          * above 4GB.
1430          *
1431          * The documentation also mentions an issue with undefined
1432          * behaviour if any general state is accessed within a page above 4GB,
1433          * which also needs to be handled carefully.
1434          */
1435         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1436                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1437
1438                 if (ret) {
1439                         DRM_ERROR("failed to set DMA mask\n");
1440
1441                         goto out_ggtt;
1442                 }
1443         }
1444
1445         aperture_size = ggtt->mappable_end;
1446
1447         ggtt->mappable =
1448                 io_mapping_create_wc(ggtt->mappable_base,
1449                                      aperture_size);
1450         if (!ggtt->mappable) {
1451                 ret = -EIO;
1452                 goto out_ggtt;
1453         }
1454
1455         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1456                                               aperture_size);
1457
1458         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1459                            PM_QOS_DEFAULT_VALUE);
1460
1461         intel_uncore_sanitize(dev_priv);
1462
1463         intel_opregion_setup(dev_priv);
1464
1465         i915_gem_load_init_fences(dev_priv);
1466
1467         /* On the 945G/GM, the chipset reports the MSI capability on the
1468          * integrated graphics even though the support isn't actually there
1469          * according to the published specs.  It doesn't appear to function
1470          * correctly in testing on 945G.
1471          * This may be a side effect of MSI having been made available for PEG
1472          * and the registers being closely associated.
1473          *
1474          * According to chipset errata, on the 965GM, MSI interrupts may
1475          * be lost or delayed, but we use them anyways to avoid
1476          * stuck interrupts on some machines.
1477          */
1478         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1479                 if (pci_enable_msi(dev->pdev) < 0)
1480                         DRM_DEBUG_DRIVER("can't enable MSI");
1481         }
1482
1483         return 0;
1484
1485 out_ggtt:
1486         i915_ggtt_cleanup_hw(dev);
1487
1488         return ret;
1489 }
1490
1491 /**
1492  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1493  * @dev_priv: device private
1494  */
1495 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1496 {
1497         struct drm_device *dev = dev_priv->dev;
1498         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1499
1500         if (dev->pdev->msi_enabled)
1501                 pci_disable_msi(dev->pdev);
1502
1503         pm_qos_remove_request(&dev_priv->pm_qos);
1504         arch_phys_wc_del(ggtt->mtrr);
1505         io_mapping_free(ggtt->mappable);
1506         i915_ggtt_cleanup_hw(dev);
1507 }
1508
1509 /**
1510  * i915_driver_register - register the driver with the rest of the system
1511  * @dev_priv: device private
1512  *
1513  * Perform any steps necessary to make the driver available via kernel
1514  * internal or userspace interfaces.
1515  */
1516 static void i915_driver_register(struct drm_i915_private *dev_priv)
1517 {
1518         struct drm_device *dev = dev_priv->dev;
1519
1520         i915_gem_shrinker_init(dev_priv);
1521
1522         /*
1523          * Notify a valid surface after modesetting,
1524          * when running inside a VM.
1525          */
1526         if (intel_vgpu_active(dev_priv))
1527                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1528
1529         /* Reveal our presence to userspace */
1530         if (drm_dev_register(dev, 0) == 0) {
1531                 i915_debugfs_register(dev_priv);
1532                 i915_setup_sysfs(dev);
1533         } else
1534                 DRM_ERROR("Failed to register driver for userspace access!\n");
1535
1536         if (INTEL_INFO(dev_priv)->num_pipes) {
1537                 /* Must be done after probing outputs */
1538                 intel_opregion_register(dev_priv);
1539                 acpi_video_register();
1540         }
1541
1542         if (IS_GEN5(dev_priv))
1543                 intel_gpu_ips_init(dev_priv);
1544
1545         i915_audio_component_init(dev_priv);
1546
1547         /*
1548          * Some ports require correctly set-up hpd registers for detection to
1549          * work properly (leading to ghost connected connector status), e.g. VGA
1550          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1551          * irqs are fully enabled. We do it last so that the async config
1552          * cannot run before the connectors are registered.
1553          */
1554         intel_fbdev_initial_config_async(dev);
1555 }
1556
1557 /**
1558  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1559  * @dev_priv: device private
1560  */
1561 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1562 {
1563         i915_audio_component_cleanup(dev_priv);
1564
1565         intel_gpu_ips_teardown();
1566         acpi_video_unregister();
1567         intel_opregion_unregister(dev_priv);
1568
1569         i915_teardown_sysfs(dev_priv->dev);
1570         i915_debugfs_unregister(dev_priv);
1571         drm_dev_unregister(dev_priv->dev);
1572
1573         i915_gem_shrinker_cleanup(dev_priv);
1574 }
1575
1576 /**
1577  * i915_driver_load - setup chip and create an initial config
1578  * @dev: DRM device
1579  * @flags: startup flags
1580  *
1581  * The driver load routine has to do several things:
1582  *   - drive output discovery via intel_modeset_init()
1583  *   - initialize the memory manager
1584  *   - allocate initial config memory
1585  *   - setup the DRM framebuffer with the allocated memory
1586  */
1587 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1588 {
1589         struct drm_i915_private *dev_priv;
1590         int ret;
1591
1592         if (i915.nuclear_pageflip)
1593                 driver.driver_features |= DRIVER_ATOMIC;
1594
1595         ret = -ENOMEM;
1596         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1597         if (dev_priv)
1598                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1599         if (ret) {
1600                 dev_printk(KERN_ERR, &pdev->dev,
1601                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1602                 kfree(dev_priv);
1603                 return ret;
1604         }
1605
1606         /* Must be set before calling __i915_printk */
1607         dev_priv->drm.pdev = pdev;
1608         dev_priv->drm.dev_private = dev_priv;
1609         dev_priv->dev = &dev_priv->drm;
1610
1611         ret = pci_enable_device(pdev);
1612         if (ret)
1613                 goto out_free_priv;
1614
1615         pci_set_drvdata(pdev, &dev_priv->drm);
1616
1617         ret = i915_driver_init_early(dev_priv, ent);
1618         if (ret < 0)
1619                 goto out_pci_disable;
1620
1621         intel_runtime_pm_get(dev_priv);
1622
1623         ret = i915_driver_init_mmio(dev_priv);
1624         if (ret < 0)
1625                 goto out_runtime_pm_put;
1626
1627         ret = i915_driver_init_hw(dev_priv);
1628         if (ret < 0)
1629                 goto out_cleanup_mmio;
1630
1631         /*
1632          * TODO: move the vblank init and parts of modeset init steps into one
1633          * of the i915_driver_init_/i915_driver_register functions according
1634          * to the role/effect of the given init step.
1635          */
1636         if (INTEL_INFO(dev_priv)->num_pipes) {
1637                 ret = drm_vblank_init(dev_priv->dev,
1638                                       INTEL_INFO(dev_priv)->num_pipes);
1639                 if (ret)
1640                         goto out_cleanup_hw;
1641         }
1642
1643         ret = i915_load_modeset_init(dev_priv->dev);
1644         if (ret < 0)
1645                 goto out_cleanup_vblank;
1646
1647         i915_driver_register(dev_priv);
1648
1649         intel_runtime_pm_enable(dev_priv);
1650
1651         intel_runtime_pm_put(dev_priv);
1652
1653         return 0;
1654
1655 out_cleanup_vblank:
1656         drm_vblank_cleanup(dev_priv->dev);
1657 out_cleanup_hw:
1658         i915_driver_cleanup_hw(dev_priv);
1659 out_cleanup_mmio:
1660         i915_driver_cleanup_mmio(dev_priv);
1661 out_runtime_pm_put:
1662         intel_runtime_pm_put(dev_priv);
1663         i915_driver_cleanup_early(dev_priv);
1664 out_pci_disable:
1665         pci_disable_device(pdev);
1666 out_free_priv:
1667         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1668         drm_dev_unref(&dev_priv->drm);
1669         return ret;
1670 }
1671
1672 void i915_driver_unload(struct drm_device *dev)
1673 {
1674         struct drm_i915_private *dev_priv = dev->dev_private;
1675
1676         intel_fbdev_fini(dev);
1677
1678         if (i915_gem_suspend(dev))
1679                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1680
1681         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1682
1683         i915_driver_unregister(dev_priv);
1684
1685         drm_vblank_cleanup(dev);
1686
1687         intel_modeset_cleanup(dev);
1688
1689         /*
1690          * free the memory space allocated for the child device
1691          * config parsed from VBT
1692          */
1693         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1694                 kfree(dev_priv->vbt.child_dev);
1695                 dev_priv->vbt.child_dev = NULL;
1696                 dev_priv->vbt.child_dev_num = 0;
1697         }
1698         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1699         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1700         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1701         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1702
1703         vga_switcheroo_unregister_client(dev->pdev);
1704         vga_client_register(dev->pdev, NULL, NULL, NULL);
1705
1706         intel_csr_ucode_fini(dev_priv);
1707
1708         /* Free error state after interrupts are fully disabled. */
1709         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1710         i915_destroy_error_state(dev);
1711
1712         /* Flush any outstanding unpin_work. */
1713         flush_workqueue(dev_priv->wq);
1714
1715         intel_guc_fini(dev);
1716         i915_gem_fini(dev);
1717         intel_fbc_cleanup_cfb(dev_priv);
1718
1719         intel_power_domains_fini(dev_priv);
1720
1721         i915_driver_cleanup_hw(dev_priv);
1722         i915_driver_cleanup_mmio(dev_priv);
1723
1724         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1725
1726         i915_driver_cleanup_early(dev_priv);
1727 }
1728
1729 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1730 {
1731         int ret;
1732
1733         ret = i915_gem_open(dev, file);
1734         if (ret)
1735                 return ret;
1736
1737         return 0;
1738 }
1739
1740 /**
1741  * i915_driver_lastclose - clean up after all DRM clients have exited
1742  * @dev: DRM device
1743  *
1744  * Take care of cleaning up after all DRM clients have exited.  In the
1745  * mode setting case, we want to restore the kernel's initial mode (just
1746  * in case the last client left us in a bad state).
1747  *
1748  * Additionally, in the non-mode setting case, we'll tear down the GTT
1749  * and DMA structures, since the kernel won't be using them, and clea
1750  * up any GEM state.
1751  */
1752 static void i915_driver_lastclose(struct drm_device *dev)
1753 {
1754         intel_fbdev_restore_mode(dev);
1755         vga_switcheroo_process_delayed_switch();
1756 }
1757
1758 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1759 {
1760         mutex_lock(&dev->struct_mutex);
1761         i915_gem_context_close(dev, file);
1762         i915_gem_release(dev, file);
1763         mutex_unlock(&dev->struct_mutex);
1764 }
1765
1766 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1767 {
1768         struct drm_i915_file_private *file_priv = file->driver_priv;
1769
1770         kfree(file_priv);
1771 }
1772
1773 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1774 {
1775         struct drm_device *dev = dev_priv->dev;
1776         struct intel_encoder *encoder;
1777
1778         drm_modeset_lock_all(dev);
1779         for_each_intel_encoder(dev, encoder)
1780                 if (encoder->suspend)
1781                         encoder->suspend(encoder);
1782         drm_modeset_unlock_all(dev);
1783 }
1784
1785 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1786                               bool rpm_resume);
1787 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1788
1789 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1790 {
1791 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1792         if (acpi_target_system_state() < ACPI_STATE_S3)
1793                 return true;
1794 #endif
1795         return false;
1796 }
1797
1798 static int i915_drm_suspend(struct drm_device *dev)
1799 {
1800         struct drm_i915_private *dev_priv = dev->dev_private;
1801         pci_power_t opregion_target_state;
1802         int error;
1803
1804         /* ignore lid events during suspend */
1805         mutex_lock(&dev_priv->modeset_restore_lock);
1806         dev_priv->modeset_restore = MODESET_SUSPENDED;
1807         mutex_unlock(&dev_priv->modeset_restore_lock);
1808
1809         disable_rpm_wakeref_asserts(dev_priv);
1810
1811         /* We do a lot of poking in a lot of registers, make sure they work
1812          * properly. */
1813         intel_display_set_init_power(dev_priv, true);
1814
1815         drm_kms_helper_poll_disable(dev);
1816
1817         pci_save_state(dev->pdev);
1818
1819         error = i915_gem_suspend(dev);
1820         if (error) {
1821                 dev_err(&dev->pdev->dev,
1822                         "GEM idle failed, resume might fail\n");
1823                 goto out;
1824         }
1825
1826         intel_guc_suspend(dev);
1827
1828         intel_suspend_gt_powersave(dev_priv);
1829
1830         intel_display_suspend(dev);
1831
1832         intel_dp_mst_suspend(dev);
1833
1834         intel_runtime_pm_disable_interrupts(dev_priv);
1835         intel_hpd_cancel_work(dev_priv);
1836
1837         intel_suspend_encoders(dev_priv);
1838
1839         intel_suspend_hw(dev);
1840
1841         i915_gem_suspend_gtt_mappings(dev);
1842
1843         i915_save_state(dev);
1844
1845         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1846         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1847
1848         intel_uncore_forcewake_reset(dev_priv, false);
1849         intel_opregion_unregister(dev_priv);
1850
1851         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1852
1853         dev_priv->suspend_count++;
1854
1855         intel_display_set_init_power(dev_priv, false);
1856
1857         intel_csr_ucode_suspend(dev_priv);
1858
1859 out:
1860         enable_rpm_wakeref_asserts(dev_priv);
1861
1862         return error;
1863 }
1864
1865 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
1866 {
1867         struct drm_i915_private *dev_priv = drm_dev->dev_private;
1868         bool fw_csr;
1869         int ret;
1870
1871         disable_rpm_wakeref_asserts(dev_priv);
1872
1873         fw_csr = !IS_BROXTON(dev_priv) &&
1874                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1875         /*
1876          * In case of firmware assisted context save/restore don't manually
1877          * deinit the power domains. This also means the CSR/DMC firmware will
1878          * stay active, it will power down any HW resources as required and
1879          * also enable deeper system power states that would be blocked if the
1880          * firmware was inactive.
1881          */
1882         if (!fw_csr)
1883                 intel_power_domains_suspend(dev_priv);
1884
1885         ret = 0;
1886         if (IS_BROXTON(dev_priv))
1887                 bxt_enable_dc9(dev_priv);
1888         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1889                 hsw_enable_pc8(dev_priv);
1890         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1891                 ret = vlv_suspend_complete(dev_priv);
1892
1893         if (ret) {
1894                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1895                 if (!fw_csr)
1896                         intel_power_domains_init_hw(dev_priv, true);
1897
1898                 goto out;
1899         }
1900
1901         pci_disable_device(drm_dev->pdev);
1902         /*
1903          * During hibernation on some platforms the BIOS may try to access
1904          * the device even though it's already in D3 and hang the machine. So
1905          * leave the device in D0 on those platforms and hope the BIOS will
1906          * power down the device properly. The issue was seen on multiple old
1907          * GENs with different BIOS vendors, so having an explicit blacklist
1908          * is inpractical; apply the workaround on everything pre GEN6. The
1909          * platforms where the issue was seen:
1910          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1911          * Fujitsu FSC S7110
1912          * Acer Aspire 1830T
1913          */
1914         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1915                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
1916
1917         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1918
1919 out:
1920         enable_rpm_wakeref_asserts(dev_priv);
1921
1922         return ret;
1923 }
1924
1925 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1926 {
1927         int error;
1928
1929         if (!dev || !dev->dev_private) {
1930                 DRM_ERROR("dev: %p\n", dev);
1931                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1932                 return -ENODEV;
1933         }
1934
1935         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1936                          state.event != PM_EVENT_FREEZE))
1937                 return -EINVAL;
1938
1939         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1940                 return 0;
1941
1942         error = i915_drm_suspend(dev);
1943         if (error)
1944                 return error;
1945
1946         return i915_drm_suspend_late(dev, false);
1947 }
1948
1949 static int i915_drm_resume(struct drm_device *dev)
1950 {
1951         struct drm_i915_private *dev_priv = dev->dev_private;
1952         int ret;
1953
1954         disable_rpm_wakeref_asserts(dev_priv);
1955
1956         ret = i915_ggtt_enable_hw(dev);
1957         if (ret)
1958                 DRM_ERROR("failed to re-enable GGTT\n");
1959
1960         intel_csr_ucode_resume(dev_priv);
1961
1962         mutex_lock(&dev->struct_mutex);
1963         i915_gem_restore_gtt_mappings(dev);
1964         mutex_unlock(&dev->struct_mutex);
1965
1966         i915_restore_state(dev);
1967         intel_opregion_setup(dev_priv);
1968
1969         intel_init_pch_refclk(dev);
1970         drm_mode_config_reset(dev);
1971
1972         /*
1973          * Interrupts have to be enabled before any batches are run. If not the
1974          * GPU will hang. i915_gem_init_hw() will initiate batches to
1975          * update/restore the context.
1976          *
1977          * Modeset enabling in intel_modeset_init_hw() also needs working
1978          * interrupts.
1979          */
1980         intel_runtime_pm_enable_interrupts(dev_priv);
1981
1982         mutex_lock(&dev->struct_mutex);
1983         if (i915_gem_init_hw(dev)) {
1984                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1985                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
1986         }
1987         mutex_unlock(&dev->struct_mutex);
1988
1989         intel_guc_resume(dev);
1990
1991         intel_modeset_init_hw(dev);
1992
1993         spin_lock_irq(&dev_priv->irq_lock);
1994         if (dev_priv->display.hpd_irq_setup)
1995                 dev_priv->display.hpd_irq_setup(dev_priv);
1996         spin_unlock_irq(&dev_priv->irq_lock);
1997
1998         intel_dp_mst_resume(dev);
1999
2000         intel_display_resume(dev);
2001
2002         /*
2003          * ... but also need to make sure that hotplug processing
2004          * doesn't cause havoc. Like in the driver load code we don't
2005          * bother with the tiny race here where we might loose hotplug
2006          * notifications.
2007          * */
2008         intel_hpd_init(dev_priv);
2009         /* Config may have changed between suspend and resume */
2010         drm_helper_hpd_irq_event(dev);
2011
2012         intel_opregion_register(dev_priv);
2013
2014         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
2015
2016         mutex_lock(&dev_priv->modeset_restore_lock);
2017         dev_priv->modeset_restore = MODESET_DONE;
2018         mutex_unlock(&dev_priv->modeset_restore_lock);
2019
2020         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2021
2022         drm_kms_helper_poll_enable(dev);
2023
2024         enable_rpm_wakeref_asserts(dev_priv);
2025
2026         return 0;
2027 }
2028
2029 static int i915_drm_resume_early(struct drm_device *dev)
2030 {
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         int ret;
2033
2034         /*
2035          * We have a resume ordering issue with the snd-hda driver also
2036          * requiring our device to be power up. Due to the lack of a
2037          * parent/child relationship we currently solve this with an early
2038          * resume hook.
2039          *
2040          * FIXME: This should be solved with a special hdmi sink device or
2041          * similar so that power domains can be employed.
2042          */
2043
2044         /*
2045          * Note that we need to set the power state explicitly, since we
2046          * powered off the device during freeze and the PCI core won't power
2047          * it back up for us during thaw. Powering off the device during
2048          * freeze is not a hard requirement though, and during the
2049          * suspend/resume phases the PCI core makes sure we get here with the
2050          * device powered on. So in case we change our freeze logic and keep
2051          * the device powered we can also remove the following set power state
2052          * call.
2053          */
2054         ret = pci_set_power_state(dev->pdev, PCI_D0);
2055         if (ret) {
2056                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
2057                 goto out;
2058         }
2059
2060         /*
2061          * Note that pci_enable_device() first enables any parent bridge
2062          * device and only then sets the power state for this device. The
2063          * bridge enabling is a nop though, since bridge devices are resumed
2064          * first. The order of enabling power and enabling the device is
2065          * imposed by the PCI core as described above, so here we preserve the
2066          * same order for the freeze/thaw phases.
2067          *
2068          * TODO: eventually we should remove pci_disable_device() /
2069          * pci_enable_enable_device() from suspend/resume. Due to how they
2070          * depend on the device enable refcount we can't anyway depend on them
2071          * disabling/enabling the device.
2072          */
2073         if (pci_enable_device(dev->pdev)) {
2074                 ret = -EIO;
2075                 goto out;
2076         }
2077
2078         pci_set_master(dev->pdev);
2079
2080         disable_rpm_wakeref_asserts(dev_priv);
2081
2082         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2083                 ret = vlv_resume_prepare(dev_priv, false);
2084         if (ret)
2085                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
2086                           ret);
2087
2088         intel_uncore_early_sanitize(dev_priv, true);
2089
2090         if (IS_BROXTON(dev_priv)) {
2091                 if (!dev_priv->suspended_to_idle)
2092                         gen9_sanitize_dc_state(dev_priv);
2093                 bxt_disable_dc9(dev_priv);
2094         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2095                 hsw_disable_pc8(dev_priv);
2096         }
2097
2098         intel_uncore_sanitize(dev_priv);
2099
2100         if (IS_BROXTON(dev_priv) ||
2101             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
2102                 intel_power_domains_init_hw(dev_priv, true);
2103
2104         enable_rpm_wakeref_asserts(dev_priv);
2105
2106 out:
2107         dev_priv->suspended_to_idle = false;
2108
2109         return ret;
2110 }
2111
2112 int i915_resume_switcheroo(struct drm_device *dev)
2113 {
2114         int ret;
2115
2116         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2117                 return 0;
2118
2119         ret = i915_drm_resume_early(dev);
2120         if (ret)
2121                 return ret;
2122
2123         return i915_drm_resume(dev);
2124 }
2125
2126 /**
2127  * i915_reset - reset chip after a hang
2128  * @dev: drm device to reset
2129  *
2130  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
2131  * reset or otherwise an error code.
2132  *
2133  * Procedure is fairly simple:
2134  *   - reset the chip using the reset reg
2135  *   - re-init context state
2136  *   - re-init hardware status page
2137  *   - re-init ring buffer
2138  *   - re-init interrupt state
2139  *   - re-init display
2140  */
2141 int i915_reset(struct drm_i915_private *dev_priv)
2142 {
2143         struct drm_device *dev = dev_priv->dev;
2144         struct i915_gpu_error *error = &dev_priv->gpu_error;
2145         unsigned reset_counter;
2146         int ret;
2147
2148         intel_reset_gt_powersave(dev_priv);
2149
2150         mutex_lock(&dev->struct_mutex);
2151
2152         /* Clear any previous failed attempts at recovery. Time to try again. */
2153         atomic_andnot(I915_WEDGED, &error->reset_counter);
2154
2155         /* Clear the reset-in-progress flag and increment the reset epoch. */
2156         reset_counter = atomic_inc_return(&error->reset_counter);
2157         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
2158                 ret = -EIO;
2159                 goto error;
2160         }
2161
2162         pr_notice("drm/i915: Resetting chip after gpu hang\n");
2163
2164         i915_gem_reset(dev);
2165
2166         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
2167         if (ret) {
2168                 if (ret != -ENODEV)
2169                         DRM_ERROR("Failed to reset chip: %i\n", ret);
2170                 else
2171                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
2172                 goto error;
2173         }
2174
2175         intel_overlay_reset(dev_priv);
2176
2177         /* Ok, now get things going again... */
2178
2179         /*
2180          * Everything depends on having the GTT running, so we need to start
2181          * there.  Fortunately we don't need to do this unless we reset the
2182          * chip at a PCI level.
2183          *
2184          * Next we need to restore the context, but we don't use those
2185          * yet either...
2186          *
2187          * Ring buffer needs to be re-initialized in the KMS case, or if X
2188          * was running at the time of the reset (i.e. we weren't VT
2189          * switched away).
2190          */
2191         ret = i915_gem_init_hw(dev);
2192         if (ret) {
2193                 DRM_ERROR("Failed hw init on reset %d\n", ret);
2194                 goto error;
2195         }
2196
2197         mutex_unlock(&dev->struct_mutex);
2198
2199         /*
2200          * rps/rc6 re-init is necessary to restore state lost after the
2201          * reset and the re-install of gt irqs. Skip for ironlake per
2202          * previous concerns that it doesn't respond well to some forms
2203          * of re-init after reset.
2204          */
2205         if (INTEL_INFO(dev)->gen > 5)
2206                 intel_enable_gt_powersave(dev_priv);
2207
2208         return 0;
2209
2210 error:
2211         atomic_or(I915_WEDGED, &error->reset_counter);
2212         mutex_unlock(&dev->struct_mutex);
2213         return ret;
2214 }
2215
2216 static int i915_pm_suspend(struct device *dev)
2217 {
2218         struct pci_dev *pdev = to_pci_dev(dev);
2219         struct drm_device *drm_dev = pci_get_drvdata(pdev);
2220
2221         if (!drm_dev || !drm_dev->dev_private) {
2222                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
2223                 return -ENODEV;
2224         }
2225
2226         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2227                 return 0;
2228
2229         return i915_drm_suspend(drm_dev);
2230 }
2231
2232 static int i915_pm_suspend_late(struct device *dev)
2233 {
2234         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
2235
2236         /*
2237          * We have a suspend ordering issue with the snd-hda driver also
2238          * requiring our device to be power up. Due to the lack of a
2239          * parent/child relationship we currently solve this with an late
2240          * suspend hook.
2241          *
2242          * FIXME: This should be solved with a special hdmi sink device or
2243          * similar so that power domains can be employed.
2244          */
2245         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2246                 return 0;
2247
2248         return i915_drm_suspend_late(drm_dev, false);
2249 }
2250
2251 static int i915_pm_poweroff_late(struct device *dev)
2252 {
2253         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
2254
2255         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2256                 return 0;
2257
2258         return i915_drm_suspend_late(drm_dev, true);
2259 }
2260
2261 static int i915_pm_resume_early(struct device *dev)
2262 {
2263         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
2264
2265         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2266                 return 0;
2267
2268         return i915_drm_resume_early(drm_dev);
2269 }
2270
2271 static int i915_pm_resume(struct device *dev)
2272 {
2273         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
2274
2275         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2276                 return 0;
2277
2278         return i915_drm_resume(drm_dev);
2279 }
2280
2281 /* freeze: before creating the hibernation_image */
2282 static int i915_pm_freeze(struct device *dev)
2283 {
2284         return i915_pm_suspend(dev);
2285 }
2286
2287 static int i915_pm_freeze_late(struct device *dev)
2288 {
2289         int ret;
2290
2291         ret = i915_pm_suspend_late(dev);
2292         if (ret)
2293                 return ret;
2294
2295         ret = i915_gem_freeze_late(dev_to_i915(dev));
2296         if (ret)
2297                 return ret;
2298
2299         return 0;
2300 }
2301
2302 /* thaw: called after creating the hibernation image, but before turning off. */
2303 static int i915_pm_thaw_early(struct device *dev)
2304 {
2305         return i915_pm_resume_early(dev);
2306 }
2307
2308 static int i915_pm_thaw(struct device *dev)
2309 {
2310         return i915_pm_resume(dev);
2311 }
2312
2313 /* restore: called after loading the hibernation image. */
2314 static int i915_pm_restore_early(struct device *dev)
2315 {
2316         return i915_pm_resume_early(dev);
2317 }
2318
2319 static int i915_pm_restore(struct device *dev)
2320 {
2321         return i915_pm_resume(dev);
2322 }
2323
2324 /*
2325  * Save all Gunit registers that may be lost after a D3 and a subsequent
2326  * S0i[R123] transition. The list of registers needing a save/restore is
2327  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
2328  * registers in the following way:
2329  * - Driver: saved/restored by the driver
2330  * - Punit : saved/restored by the Punit firmware
2331  * - No, w/o marking: no need to save/restore, since the register is R/O or
2332  *                    used internally by the HW in a way that doesn't depend
2333  *                    keeping the content across a suspend/resume.
2334  * - Debug : used for debugging
2335  *
2336  * We save/restore all registers marked with 'Driver', with the following
2337  * exceptions:
2338  * - Registers out of use, including also registers marked with 'Debug'.
2339  *   These have no effect on the driver's operation, so we don't save/restore
2340  *   them to reduce the overhead.
2341  * - Registers that are fully setup by an initialization function called from
2342  *   the resume path. For example many clock gating and RPS/RC6 registers.
2343  * - Registers that provide the right functionality with their reset defaults.
2344  *
2345  * TODO: Except for registers that based on the above 3 criteria can be safely
2346  * ignored, we save/restore all others, practically treating the HW context as
2347  * a black-box for the driver. Further investigation is needed to reduce the
2348  * saved/restored registers even further, by following the same 3 criteria.
2349  */
2350 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2351 {
2352         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2353         int i;
2354
2355         /* GAM 0x4000-0x4770 */
2356         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
2357         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
2358         s->arb_mode             = I915_READ(ARB_MODE);
2359         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
2360         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
2361
2362         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2363                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
2364
2365         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
2366         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
2367
2368         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
2369         s->ecochk               = I915_READ(GAM_ECOCHK);
2370         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2371         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2372
2373         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2374
2375         /* MBC 0x9024-0x91D0, 0x8500 */
2376         s->g3dctl               = I915_READ(VLV_G3DCTL);
2377         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2378         s->mbctl                = I915_READ(GEN6_MBCTL);
2379
2380         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2381         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2382         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2383         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2384         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2385         s->rstctl               = I915_READ(GEN6_RSTCTL);
2386         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2387
2388         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2389         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2390         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2391         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2392         s->ecobus               = I915_READ(ECOBUS);
2393         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2394         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2395         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2396         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2397         s->rcedata              = I915_READ(VLV_RCEDATA);
2398         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2399
2400         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2401         s->gt_imr               = I915_READ(GTIMR);
2402         s->gt_ier               = I915_READ(GTIER);
2403         s->pm_imr               = I915_READ(GEN6_PMIMR);
2404         s->pm_ier               = I915_READ(GEN6_PMIER);
2405
2406         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2407                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2408
2409         /* GT SA CZ domain, 0x100000-0x138124 */
2410         s->tilectl              = I915_READ(TILECTL);
2411         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2412         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2413         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2414         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2415
2416         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2417         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2418         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2419         s->pcbr                 = I915_READ(VLV_PCBR);
2420         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2421
2422         /*
2423          * Not saving any of:
2424          * DFT,         0x9800-0x9EC0
2425          * SARB,        0xB000-0xB1FC
2426          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2427          * PCI CFG
2428          */
2429 }
2430
2431 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2432 {
2433         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2434         u32 val;
2435         int i;
2436
2437         /* GAM 0x4000-0x4770 */
2438         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2439         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2440         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2441         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2442         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2443
2444         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2445                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2446
2447         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2448         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2449
2450         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2451         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2452         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2453         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2454
2455         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2456
2457         /* MBC 0x9024-0x91D0, 0x8500 */
2458         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2459         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2460         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2461
2462         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2463         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2464         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2465         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2466         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2467         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2468         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2469
2470         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2471         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2472         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2473         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2474         I915_WRITE(ECOBUS,              s->ecobus);
2475         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2476         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2477         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2478         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2479         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2480         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2481
2482         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2483         I915_WRITE(GTIMR,               s->gt_imr);
2484         I915_WRITE(GTIER,               s->gt_ier);
2485         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2486         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2487
2488         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2489                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2490
2491         /* GT SA CZ domain, 0x100000-0x138124 */
2492         I915_WRITE(TILECTL,                     s->tilectl);
2493         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2494         /*
2495          * Preserve the GT allow wake and GFX force clock bit, they are not
2496          * be restored, as they are used to control the s0ix suspend/resume
2497          * sequence by the caller.
2498          */
2499         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2500         val &= VLV_GTLC_ALLOWWAKEREQ;
2501         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2502         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2503
2504         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2505         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2506         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2507         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2508
2509         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2510
2511         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2512         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2513         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2514         I915_WRITE(VLV_PCBR,                    s->pcbr);
2515         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2516 }
2517
2518 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2519 {
2520         u32 val;
2521         int err;
2522
2523         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2524         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2525         if (force_on)
2526                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2527         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2528
2529         if (!force_on)
2530                 return 0;
2531
2532         err = intel_wait_for_register(dev_priv,
2533                                       VLV_GTLC_SURVIVABILITY_REG,
2534                                       VLV_GFX_CLK_STATUS_BIT,
2535                                       VLV_GFX_CLK_STATUS_BIT,
2536                                       20);
2537         if (err)
2538                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2539                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2540
2541         return err;
2542 }
2543
2544 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2545 {
2546         u32 val;
2547         int err = 0;
2548
2549         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2550         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2551         if (allow)
2552                 val |= VLV_GTLC_ALLOWWAKEREQ;
2553         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2554         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2555
2556         err = intel_wait_for_register(dev_priv,
2557                                       VLV_GTLC_PW_STATUS,
2558                                       VLV_GTLC_ALLOWWAKEACK,
2559                                       allow,
2560                                       1);
2561         if (err)
2562                 DRM_ERROR("timeout disabling GT waking\n");
2563
2564         return err;
2565 }
2566
2567 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2568                                  bool wait_for_on)
2569 {
2570         u32 mask;
2571         u32 val;
2572         int err;
2573
2574         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2575         val = wait_for_on ? mask : 0;
2576         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2577                 return 0;
2578
2579         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2580                       onoff(wait_for_on),
2581                       I915_READ(VLV_GTLC_PW_STATUS));
2582
2583         /*
2584          * RC6 transitioning can be delayed up to 2 msec (see
2585          * valleyview_enable_rps), use 3 msec for safety.
2586          */
2587         err = intel_wait_for_register(dev_priv,
2588                                       VLV_GTLC_PW_STATUS, mask, val,
2589                                       3);
2590         if (err)
2591                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2592                           onoff(wait_for_on));
2593
2594         return err;
2595 }
2596
2597 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2598 {
2599         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2600                 return;
2601
2602         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2603         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2604 }
2605
2606 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2607 {
2608         u32 mask;
2609         int err;
2610
2611         /*
2612          * Bspec defines the following GT well on flags as debug only, so
2613          * don't treat them as hard failures.
2614          */
2615         (void)vlv_wait_for_gt_wells(dev_priv, false);
2616
2617         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2618         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2619
2620         vlv_check_no_gt_access(dev_priv);
2621
2622         err = vlv_force_gfx_clock(dev_priv, true);
2623         if (err)
2624                 goto err1;
2625
2626         err = vlv_allow_gt_wake(dev_priv, false);
2627         if (err)
2628                 goto err2;
2629
2630         if (!IS_CHERRYVIEW(dev_priv))
2631                 vlv_save_gunit_s0ix_state(dev_priv);
2632
2633         err = vlv_force_gfx_clock(dev_priv, false);
2634         if (err)
2635                 goto err2;
2636
2637         return 0;
2638
2639 err2:
2640         /* For safety always re-enable waking and disable gfx clock forcing */
2641         vlv_allow_gt_wake(dev_priv, true);
2642 err1:
2643         vlv_force_gfx_clock(dev_priv, false);
2644
2645         return err;
2646 }
2647
2648 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2649                                 bool rpm_resume)
2650 {
2651         struct drm_device *dev = dev_priv->dev;
2652         int err;
2653         int ret;
2654
2655         /*
2656          * If any of the steps fail just try to continue, that's the best we
2657          * can do at this point. Return the first error code (which will also
2658          * leave RPM permanently disabled).
2659          */
2660         ret = vlv_force_gfx_clock(dev_priv, true);
2661
2662         if (!IS_CHERRYVIEW(dev_priv))
2663                 vlv_restore_gunit_s0ix_state(dev_priv);
2664
2665         err = vlv_allow_gt_wake(dev_priv, true);
2666         if (!ret)
2667                 ret = err;
2668
2669         err = vlv_force_gfx_clock(dev_priv, false);
2670         if (!ret)
2671                 ret = err;
2672
2673         vlv_check_no_gt_access(dev_priv);
2674
2675         if (rpm_resume) {
2676                 intel_init_clock_gating(dev);
2677                 i915_gem_restore_fences(dev);
2678         }
2679
2680         return ret;
2681 }
2682
2683 static int intel_runtime_suspend(struct device *device)
2684 {
2685         struct pci_dev *pdev = to_pci_dev(device);
2686         struct drm_device *dev = pci_get_drvdata(pdev);
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688         int ret;
2689
2690         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2691                 return -ENODEV;
2692
2693         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2694                 return -ENODEV;
2695
2696         DRM_DEBUG_KMS("Suspending device\n");
2697
2698         /*
2699          * We could deadlock here in case another thread holding struct_mutex
2700          * calls RPM suspend concurrently, since the RPM suspend will wait
2701          * first for this RPM suspend to finish. In this case the concurrent
2702          * RPM resume will be followed by its RPM suspend counterpart. Still
2703          * for consistency return -EAGAIN, which will reschedule this suspend.
2704          */
2705         if (!mutex_trylock(&dev->struct_mutex)) {
2706                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2707                 /*
2708                  * Bump the expiration timestamp, otherwise the suspend won't
2709                  * be rescheduled.
2710                  */
2711                 pm_runtime_mark_last_busy(device);
2712
2713                 return -EAGAIN;
2714         }
2715
2716         disable_rpm_wakeref_asserts(dev_priv);
2717
2718         /*
2719          * We are safe here against re-faults, since the fault handler takes
2720          * an RPM reference.
2721          */
2722         i915_gem_release_all_mmaps(dev_priv);
2723         mutex_unlock(&dev->struct_mutex);
2724
2725         intel_guc_suspend(dev);
2726
2727         intel_runtime_pm_disable_interrupts(dev_priv);
2728
2729         ret = 0;
2730         if (IS_BROXTON(dev_priv)) {
2731                 bxt_display_core_uninit(dev_priv);
2732                 bxt_enable_dc9(dev_priv);
2733         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2734                 hsw_enable_pc8(dev_priv);
2735         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2736                 ret = vlv_suspend_complete(dev_priv);
2737         }
2738
2739         if (ret) {
2740                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2741                 intel_runtime_pm_enable_interrupts(dev_priv);
2742
2743                 enable_rpm_wakeref_asserts(dev_priv);
2744
2745                 return ret;
2746         }
2747
2748         intel_uncore_forcewake_reset(dev_priv, false);
2749
2750         enable_rpm_wakeref_asserts(dev_priv);
2751         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2752
2753         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2754                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2755
2756         dev_priv->pm.suspended = true;
2757
2758         /*
2759          * FIXME: We really should find a document that references the arguments
2760          * used below!
2761          */
2762         if (IS_BROADWELL(dev_priv)) {
2763                 /*
2764                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2765                  * being detected, and the call we do at intel_runtime_resume()
2766                  * won't be able to restore them. Since PCI_D3hot matches the
2767                  * actual specification and appears to be working, use it.
2768                  */
2769                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2770         } else {
2771                 /*
2772                  * current versions of firmware which depend on this opregion
2773                  * notification have repurposed the D1 definition to mean
2774                  * "runtime suspended" vs. what you would normally expect (D3)
2775                  * to distinguish it from notifications that might be sent via
2776                  * the suspend path.
2777                  */
2778                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2779         }
2780
2781         assert_forcewakes_inactive(dev_priv);
2782
2783         DRM_DEBUG_KMS("Device suspended\n");
2784         return 0;
2785 }
2786
2787 static int intel_runtime_resume(struct device *device)
2788 {
2789         struct pci_dev *pdev = to_pci_dev(device);
2790         struct drm_device *dev = pci_get_drvdata(pdev);
2791         struct drm_i915_private *dev_priv = dev->dev_private;
2792         int ret = 0;
2793
2794         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2795                 return -ENODEV;
2796
2797         DRM_DEBUG_KMS("Resuming device\n");
2798
2799         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2800         disable_rpm_wakeref_asserts(dev_priv);
2801
2802         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2803         dev_priv->pm.suspended = false;
2804         if (intel_uncore_unclaimed_mmio(dev_priv))
2805                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2806
2807         intel_guc_resume(dev);
2808
2809         if (IS_GEN6(dev_priv))
2810                 intel_init_pch_refclk(dev);
2811
2812         if (IS_BROXTON(dev)) {
2813                 bxt_disable_dc9(dev_priv);
2814                 bxt_display_core_init(dev_priv, true);
2815                 if (dev_priv->csr.dmc_payload &&
2816                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2817                         gen9_enable_dc5(dev_priv);
2818         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2819                 hsw_disable_pc8(dev_priv);
2820         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2821                 ret = vlv_resume_prepare(dev_priv, true);
2822         }
2823
2824         /*
2825          * No point of rolling back things in case of an error, as the best
2826          * we can do is to hope that things will still work (and disable RPM).
2827          */
2828         i915_gem_init_swizzling(dev);
2829         gen6_update_ring_freq(dev_priv);
2830
2831         intel_runtime_pm_enable_interrupts(dev_priv);
2832
2833         /*
2834          * On VLV/CHV display interrupts are part of the display
2835          * power well, so hpd is reinitialized from there. For
2836          * everyone else do it here.
2837          */
2838         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2839                 intel_hpd_init(dev_priv);
2840
2841         enable_rpm_wakeref_asserts(dev_priv);
2842
2843         if (ret)
2844                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2845         else
2846                 DRM_DEBUG_KMS("Device resumed\n");
2847
2848         return ret;
2849 }
2850
2851 const struct dev_pm_ops i915_pm_ops = {
2852         /*
2853          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2854          * PMSG_RESUME]
2855          */
2856         .suspend = i915_pm_suspend,
2857         .suspend_late = i915_pm_suspend_late,
2858         .resume_early = i915_pm_resume_early,
2859         .resume = i915_pm_resume,
2860
2861         /*
2862          * S4 event handlers
2863          * @freeze, @freeze_late    : called (1) before creating the
2864          *                            hibernation image [PMSG_FREEZE] and
2865          *                            (2) after rebooting, before restoring
2866          *                            the image [PMSG_QUIESCE]
2867          * @thaw, @thaw_early       : called (1) after creating the hibernation
2868          *                            image, before writing it [PMSG_THAW]
2869          *                            and (2) after failing to create or
2870          *                            restore the image [PMSG_RECOVER]
2871          * @poweroff, @poweroff_late: called after writing the hibernation
2872          *                            image, before rebooting [PMSG_HIBERNATE]
2873          * @restore, @restore_early : called after rebooting and restoring the
2874          *                            hibernation image [PMSG_RESTORE]
2875          */
2876         .freeze = i915_pm_freeze,
2877         .freeze_late = i915_pm_freeze_late,
2878         .thaw_early = i915_pm_thaw_early,
2879         .thaw = i915_pm_thaw,
2880         .poweroff = i915_pm_suspend,
2881         .poweroff_late = i915_pm_poweroff_late,
2882         .restore_early = i915_pm_restore_early,
2883         .restore = i915_pm_restore,
2884
2885         /* S0ix (via runtime suspend) event handlers */
2886         .runtime_suspend = intel_runtime_suspend,
2887         .runtime_resume = intel_runtime_resume,
2888 };
2889
2890 static const struct vm_operations_struct i915_gem_vm_ops = {
2891         .fault = i915_gem_fault,
2892         .open = drm_gem_vm_open,
2893         .close = drm_gem_vm_close,
2894 };
2895
2896 static const struct file_operations i915_driver_fops = {
2897         .owner = THIS_MODULE,
2898         .open = drm_open,
2899         .release = drm_release,
2900         .unlocked_ioctl = drm_ioctl,
2901         .mmap = drm_gem_mmap,
2902         .poll = drm_poll,
2903         .read = drm_read,
2904 #ifdef CONFIG_COMPAT
2905         .compat_ioctl = i915_compat_ioctl,
2906 #endif
2907         .llseek = noop_llseek,
2908 };
2909
2910 static int
2911 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2912                           struct drm_file *file)
2913 {
2914         return -ENODEV;
2915 }
2916
2917 static const struct drm_ioctl_desc i915_ioctls[] = {
2918         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2919         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2920         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2921         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2922         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2923         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2924         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2925         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2926         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2927         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2928         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2929         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2930         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2931         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2932         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2933         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2934         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2935         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2936         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2937         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2938         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2939         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2940         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2941         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2942         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2943         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2944         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2945         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2946         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2947         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2948         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2949         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2950         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2951         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2952         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2953         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2954         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2955         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2956         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2957         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2958         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2959         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2960         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2961         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2962         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2963         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2964         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2965         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2966         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2967         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2968         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2969         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2970 };
2971
2972 static struct drm_driver driver = {
2973         /* Don't use MTRRs here; the Xserver or userspace app should
2974          * deal with them for Intel hardware.
2975          */
2976         .driver_features =
2977             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2978             DRIVER_RENDER | DRIVER_MODESET,
2979         .open = i915_driver_open,
2980         .lastclose = i915_driver_lastclose,
2981         .preclose = i915_driver_preclose,
2982         .postclose = i915_driver_postclose,
2983         .set_busid = drm_pci_set_busid,
2984
2985         .gem_free_object = i915_gem_free_object,
2986         .gem_vm_ops = &i915_gem_vm_ops,
2987
2988         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2989         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2990         .gem_prime_export = i915_gem_prime_export,
2991         .gem_prime_import = i915_gem_prime_import,
2992
2993         .dumb_create = i915_gem_dumb_create,
2994         .dumb_map_offset = i915_gem_mmap_gtt,
2995         .dumb_destroy = drm_gem_dumb_destroy,
2996         .ioctls = i915_ioctls,
2997         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2998         .fops = &i915_driver_fops,
2999         .name = DRIVER_NAME,
3000         .desc = DRIVER_DESC,
3001         .date = DRIVER_DATE,
3002         .major = DRIVER_MAJOR,
3003         .minor = DRIVER_MINOR,
3004         .patchlevel = DRIVER_PATCHLEVEL,
3005 };