drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/oom.h>
  33 #include <linux/module.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/pnp.h>
  38 #include <linux/slab.h>
  39 #include <linux/vgaarb.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/vt.h>
  42 #include <acpi/video.h>
  43
  44 #include <drm/drmP.h>
  45 #include <drm/drm_crtc_helper.h>
  46 #include <drm/i915_drm.h>
  47
  48 #include "i915_drv.h"
  49 #include "i915_trace.h"
  50 #include "i915_vgpu.h"
  51 #include "intel_drv.h"
  52
  53 static struct drm_driver driver;
  54
  55 static unsigned int i915_load_fail_count;
  56
  57 bool __i915_inject_load_failure(const char *func, int line)
  58 {
  59         if (i915_load_fail_count >= i915.inject_load_failure)
  60                 return false;
  61
  62         if (++i915_load_fail_count == i915.inject_load_failure) {
  63                 DRM_INFO("Injecting failure at checkpoint %u [%s:%d]\n",
  64                          i915.inject_load_failure, func, line);
  65                 return true;
  66         }
  67
  68         return false;
  69 }
  70
  71 #define FDO_BUG_URL "https://bugs.freedesktop.org/enter_bug.cgi?product=DRI"
  72 #define FDO_BUG_MSG "Please file a bug at " FDO_BUG_URL " against DRM/Intel " \
  73                     "providing the dmesg log by booting with drm.debug=0xf"
  74
  75 void
  76 __i915_printk(struct drm_i915_private *dev_priv, const char *level,
  77               const char *fmt, ...)
  78 {
  79         static bool shown_bug_once;
  80         struct device *dev = dev_priv->drm.dev;
  81         bool is_error = level[1] <= KERN_ERR[1];
  82         bool is_debug = level[1] == KERN_DEBUG[1];
  83         struct va_format vaf;
  84         va_list args;
  85
  86         if (is_debug && !(drm_debug & DRM_UT_DRIVER))
  87                 return;
  88
  89         va_start(args, fmt);
  90
  91         vaf.fmt = fmt;
  92         vaf.va = &args;
  93
  94         dev_printk(level, dev, "[" DRM_NAME ":%ps] %pV",
  95                    __builtin_return_address(0), &vaf);
  96
  97         if (is_error && !shown_bug_once) {
  98                 dev_notice(dev, "%s", FDO_BUG_MSG);
  99                 shown_bug_once = true;
 100         }
 101
 102         va_end(args);
 103 }
 104
 105 static bool i915_error_injected(struct drm_i915_private *dev_priv)
 106 {
 107         return i915.inject_load_failure &&
 108                i915_load_fail_count == i915.inject_load_failure;
 109 }
 110
 111 #define i915_load_error(dev_priv, fmt, ...)                                  \
 112         __i915_printk(dev_priv,                                              \
 113                       i915_error_injected(dev_priv) ? KERN_DEBUG : KERN_ERR, \
 114                       fmt, ##__VA_ARGS__)
 115
 116
 117 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
 118 {
 119         enum intel_pch ret = PCH_NOP;
 120
 121         /*
 122          * In a virtualized passthrough environment we can be in a
 123          * setup where the ISA bridge is not able to be passed through.
 124          * In this case, a south bridge can be emulated and we have to
 125          * make an educated guess as to which PCH is really there.
 126          */
 127
 128         if (IS_GEN5(dev)) {
 129                 ret = PCH_IBX;
 130                 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
 131         } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
 132                 ret = PCH_CPT;
 133                 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
 134         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 135                 ret = PCH_LPT;
 136                 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
 137         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
 138                 ret = PCH_SPT;
 139                 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
 140         }
 141
 142         return ret;
 143 }
 144
 145 static void intel_detect_pch(struct drm_device *dev)
 146 {
 147         struct drm_i915_private *dev_priv = to_i915(dev);
 148         struct pci_dev *pch = NULL;
 149
 150         /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
 151          * (which really amounts to a PCH but no South Display).
 152          */
 153         if (INTEL_INFO(dev)->num_pipes == 0) {
 154                 dev_priv->pch_type = PCH_NOP;
 155                 return;
 156         }
 157
 158         /*
 159          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 160          * make graphics device passthrough work easy for VMM, that only
 161          * need to expose ISA bridge to let driver know the real hardware
 162          * underneath. This is a requirement from virtualization team.
 163          *
 164          * In some virtualized environments (e.g. XEN), there is irrelevant
 165          * ISA bridge in the system. To work reliably, we should scan trhough
 166          * all the ISA bridge devices and check for the first match, instead
 167          * of only checking the first one.
 168          */
 169         while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
 170                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 171                         unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 172                         dev_priv->pch_id = id;
 173
 174                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 175                                 dev_priv->pch_type = PCH_IBX;
 176                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 177                                 WARN_ON(!IS_GEN5(dev));
 178                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 179                                 dev_priv->pch_type = PCH_CPT;
 180                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 181                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 182                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 183                                 /* PantherPoint is CPT compatible */
 184                                 dev_priv->pch_type = PCH_CPT;
 185                                 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
 186                                 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
 187                         } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
 188                                 dev_priv->pch_type = PCH_LPT;
 189                                 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
 190                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 191                                 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
 192                         } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
 193                                 dev_priv->pch_type = PCH_LPT;
 194                                 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
 195                                 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
 196                                 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
 197                         } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
 198                                 dev_priv->pch_type = PCH_SPT;
 199                                 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
 200                                 WARN_ON(!IS_SKYLAKE(dev) &&
 201                                         !IS_KABYLAKE(dev));
 202                         } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
 203                                 dev_priv->pch_type = PCH_SPT;
 204                                 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
 205                                 WARN_ON(!IS_SKYLAKE(dev) &&
 206                                         !IS_KABYLAKE(dev));
 207                         } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
 208                                    (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
 209                                    ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
 210                                     pch->subsystem_vendor ==
 211                                             PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
 212                                     pch->subsystem_device ==
 213                                             PCI_SUBDEVICE_ID_QEMU)) {
 214                                 dev_priv->pch_type = intel_virt_detect_pch(dev);
 215                         } else
 216                                 continue;
 217
 218                         break;
 219                 }
 220         }
 221         if (!pch)
 222                 DRM_DEBUG_KMS("No PCH found.\n");
 223
 224         pci_dev_put(pch);
 225 }
 226
 227 bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
 228 {
 229         if (INTEL_GEN(dev_priv) < 6)
 230                 return false;
 231
 232         if (i915.semaphores >= 0)
 233                 return i915.semaphores;
 234
 235         /* TODO: make semaphores and Execlists play nicely together */
 236         if (i915.enable_execlists)
 237                 return false;
 238
 239 #ifdef CONFIG_INTEL_IOMMU
 240         /* Enable semaphores on SNB when IO remapping is off */
 241         if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
 242                 return false;
 243 #endif
 244
 245         return true;
 246 }
 247
 248 static int i915_getparam(struct drm_device *dev, void *data,
 249                          struct drm_file *file_priv)
 250 {
 251         struct drm_i915_private *dev_priv = to_i915(dev);
 252         drm_i915_getparam_t *param = data;
 253         int value;
 254
 255         switch (param->param) {
 256         case I915_PARAM_IRQ_ACTIVE:
 257         case I915_PARAM_ALLOW_BATCHBUFFER:
 258         case I915_PARAM_LAST_DISPATCH:
 259                 /* Reject all old ums/dri params. */
 260                 return -ENODEV;
 261         case I915_PARAM_CHIPSET_ID:
 262                 value = dev->pdev->device;
 263                 break;
 264         case I915_PARAM_REVISION:
 265                 value = dev->pdev->revision;
 266                 break;
 267         case I915_PARAM_HAS_GEM:
 268                 value = 1;
 269                 break;
 270         case I915_PARAM_NUM_FENCES_AVAIL:
 271                 value = dev_priv->num_fence_regs;
 272                 break;
 273         case I915_PARAM_HAS_OVERLAY:
 274                 value = dev_priv->overlay ? 1 : 0;
 275                 break;
 276         case I915_PARAM_HAS_PAGEFLIPPING:
 277                 value = 1;
 278                 break;
 279         case I915_PARAM_HAS_EXECBUF2:
 280                 /* depends on GEM */
 281                 value = 1;
 282                 break;
 283         case I915_PARAM_HAS_BSD:
 284                 value = intel_engine_initialized(&dev_priv->engine[VCS]);
 285                 break;
 286         case I915_PARAM_HAS_BLT:
 287                 value = intel_engine_initialized(&dev_priv->engine[BCS]);
 288                 break;
 289         case I915_PARAM_HAS_VEBOX:
 290                 value = intel_engine_initialized(&dev_priv->engine[VECS]);
 291                 break;
 292         case I915_PARAM_HAS_BSD2:
 293                 value = intel_engine_initialized(&dev_priv->engine[VCS2]);
 294                 break;
 295         case I915_PARAM_HAS_RELAXED_FENCING:
 296                 value = 1;
 297                 break;
 298         case I915_PARAM_HAS_COHERENT_RINGS:
 299                 value = 1;
 300                 break;
 301         case I915_PARAM_HAS_EXEC_CONSTANTS:
 302                 value = INTEL_INFO(dev)->gen >= 4;
 303                 break;
 304         case I915_PARAM_HAS_RELAXED_DELTA:
 305                 value = 1;
 306                 break;
 307         case I915_PARAM_HAS_GEN7_SOL_RESET:
 308                 value = 1;
 309                 break;
 310         case I915_PARAM_HAS_LLC:
 311                 value = HAS_LLC(dev);
 312                 break;
 313         case I915_PARAM_HAS_WT:
 314                 value = HAS_WT(dev);
 315                 break;
 316         case I915_PARAM_HAS_ALIASING_PPGTT:
 317                 value = USES_PPGTT(dev);
 318                 break;
 319         case I915_PARAM_HAS_WAIT_TIMEOUT:
 320                 value = 1;
 321                 break;
 322         case I915_PARAM_HAS_SEMAPHORES:
 323                 value = i915_semaphore_is_enabled(dev_priv);
 324                 break;
 325         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
 326                 value = 1;
 327                 break;
 328         case I915_PARAM_HAS_SECURE_BATCHES:
 329                 value = capable(CAP_SYS_ADMIN);
 330                 break;
 331         case I915_PARAM_HAS_PINNED_BATCHES:
 332                 value = 1;
 333                 break;
 334         case I915_PARAM_HAS_EXEC_NO_RELOC:
 335                 value = 1;
 336                 break;
 337         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 338                 value = 1;
 339                 break;
 340         case I915_PARAM_CMD_PARSER_VERSION:
 341                 value = i915_cmd_parser_get_version(dev_priv);
 342                 break;
 343         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 344                 value = 1;
 345                 break;
 346         case I915_PARAM_MMAP_VERSION:
 347                 value = 1;
 348                 break;
 349         case I915_PARAM_SUBSLICE_TOTAL:
 350                 value = INTEL_INFO(dev)->subslice_total;
 351                 if (!value)
 352                         return -ENODEV;
 353                 break;
 354         case I915_PARAM_EU_TOTAL:
 355                 value = INTEL_INFO(dev)->eu_total;
 356                 if (!value)
 357                         return -ENODEV;
 358                 break;
 359         case I915_PARAM_HAS_GPU_RESET:
 360                 value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
 361                 break;
 362         case I915_PARAM_HAS_RESOURCE_STREAMER:
 363                 value = HAS_RESOURCE_STREAMER(dev);
 364                 break;
 365         case I915_PARAM_HAS_EXEC_SOFTPIN:
 366                 value = 1;
 367                 break;
 368         case I915_PARAM_HAS_POOLED_EU:
 369                 value = HAS_POOLED_EU(dev);
 370                 break;
 371         case I915_PARAM_MIN_EU_IN_POOL:
 372                 value = INTEL_INFO(dev)->min_eu_in_pool;
 373                 break;
 374         default:
 375                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 376                 return -EINVAL;
 377         }
 378
 379         if (put_user(value, param->value))
 380                 return -EFAULT;
 381
 382         return 0;
 383 }
 384
 385 static int i915_get_bridge_dev(struct drm_device *dev)
 386 {
 387         struct drm_i915_private *dev_priv = to_i915(dev);
 388
 389         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
 390         if (!dev_priv->bridge_dev) {
 391                 DRM_ERROR("bridge device not found\n");
 392                 return -1;
 393         }
 394         return 0;
 395 }
 396
 397 /* Allocate space for the MCH regs if needed, return nonzero on error */
 398 static int
 399 intel_alloc_mchbar_resource(struct drm_device *dev)
 400 {
 401         struct drm_i915_private *dev_priv = to_i915(dev);
 402         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 403         u32 temp_lo, temp_hi = 0;
 404         u64 mchbar_addr;
 405         int ret;
 406
 407         if (INTEL_INFO(dev)->gen >= 4)
 408                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 409         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 410         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 411
 412         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 413 #ifdef CONFIG_PNP
 414         if (mchbar_addr &&
 415             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 416                 return 0;
 417 #endif
 418
 419         /* Get some space for it */
 420         dev_priv->mch_res.name = "i915 MCHBAR";
 421         dev_priv->mch_res.flags = IORESOURCE_MEM;
 422         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 423                                      &dev_priv->mch_res,
 424                                      MCHBAR_SIZE, MCHBAR_SIZE,
 425                                      PCIBIOS_MIN_MEM,
 426                                      0, pcibios_align_resource,
 427                                      dev_priv->bridge_dev);
 428         if (ret) {
 429                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 430                 dev_priv->mch_res.start = 0;
 431                 return ret;
 432         }
 433
 434         if (INTEL_INFO(dev)->gen >= 4)
 435                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 436                                        upper_32_bits(dev_priv->mch_res.start));
 437
 438         pci_write_config_dword(dev_priv->bridge_dev, reg,
 439                                lower_32_bits(dev_priv->mch_res.start));
 440         return 0;
 441 }
 442
 443 /* Setup MCHBAR if possible, return true if we should disable it again */
 444 static void
 445 intel_setup_mchbar(struct drm_device *dev)
 446 {
 447         struct drm_i915_private *dev_priv = to_i915(dev);
 448         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 449         u32 temp;
 450         bool enabled;
 451
 452         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
 453                 return;
 454
 455         dev_priv->mchbar_need_disable = false;
 456
 457         if (IS_I915G(dev) || IS_I915GM(dev)) {
 458                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN, &temp);
 459                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 460         } else {
 461                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 462                 enabled = temp & 1;
 463         }
 464
 465         /* If it's already enabled, don't have to do anything */
 466         if (enabled)
 467                 return;
 468
 469         if (intel_alloc_mchbar_resource(dev))
 470                 return;
 471
 472         dev_priv->mchbar_need_disable = true;
 473
 474         /* Space is allocated or reserved, so enable it. */
 475         if (IS_I915G(dev) || IS_I915GM(dev)) {
 476                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 477                                        temp | DEVEN_MCHBAR_EN);
 478         } else {
 479                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 480                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 481         }
 482 }
 483
 484 static void
 485 intel_teardown_mchbar(struct drm_device *dev)
 486 {
 487         struct drm_i915_private *dev_priv = to_i915(dev);
 488         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 489
 490         if (dev_priv->mchbar_need_disable) {
 491                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 492                         u32 deven_val;
 493
 494                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN,
 495                                               &deven_val);
 496                         deven_val &= ~DEVEN_MCHBAR_EN;
 497                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN,
 498                                                deven_val);
 499                 } else {
 500                         u32 mchbar_val;
 501
 502                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg,
 503                                               &mchbar_val);
 504                         mchbar_val &= ~1;
 505                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg,
 506                                                mchbar_val);
 507                 }
 508         }
 509
 510         if (dev_priv->mch_res.start)
 511                 release_resource(&dev_priv->mch_res);
 512 }
 513
 514 /* true = enable decode, false = disable decoder */
 515 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 516 {
 517         struct drm_device *dev = cookie;
 518
 519         intel_modeset_vga_set_state(dev, state);
 520         if (state)
 521                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 522                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 523         else
 524                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 525 }
 526
 527 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 528 {
 529         struct drm_device *dev = pci_get_drvdata(pdev);
 530         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 531
 532         if (state == VGA_SWITCHEROO_ON) {
 533                 pr_info("switched on\n");
 534                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 535                 /* i915 resume handler doesn't set to D0 */
 536                 pci_set_power_state(dev->pdev, PCI_D0);
 537                 i915_resume_switcheroo(dev);
 538                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 539         } else {
 540                 pr_info("switched off\n");
 541                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 542                 i915_suspend_switcheroo(dev, pmm);
 543                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 544         }
 545 }
 546
 547 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 548 {
 549         struct drm_device *dev = pci_get_drvdata(pdev);
 550
 551         /*
 552          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 553          * locking inversion with the driver load path. And the access here is
 554          * completely racy anyway. So don't bother with locking for now.
 555          */
 556         return dev->open_count == 0;
 557 }
 558
 559 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 560         .set_gpu_state = i915_switcheroo_set_state,
 561         .reprobe = NULL,
 562         .can_switch = i915_switcheroo_can_switch,
 563 };
 564
 565 static void i915_gem_fini(struct drm_device *dev)
 566 {
 567         struct drm_i915_private *dev_priv = to_i915(dev);
 568
 569         /*
 570          * Neither the BIOS, ourselves or any other kernel
 571          * expects the system to be in execlists mode on startup,
 572          * so we need to reset the GPU back to legacy mode. And the only
 573          * known way to disable logical contexts is through a GPU reset.
 574          *
 575          * So in order to leave the system in a known default configuration,
 576          * always reset the GPU upon unload. Afterwards we then clean up the
 577          * GEM state tracking, flushing off the requests and leaving the
 578          * system in a known idle state.
 579          *
 580          * Note that is of the upmost importance that the GPU is idle and
 581          * all stray writes are flushed *before* we dismantle the backing
 582          * storage for the pinned objects.
 583          *
 584          * However, since we are uncertain that reseting the GPU on older
 585          * machines is a good idea, we don't - just in case it leaves the
 586          * machine in an unusable condition.
 587          */
 588         if (HAS_HW_CONTEXTS(dev)) {
 589                 int reset = intel_gpu_reset(dev_priv, ALL_ENGINES);
 590                 WARN_ON(reset && reset != -ENODEV);
 591         }
 592
 593         mutex_lock(&dev->struct_mutex);
 594         i915_gem_reset(dev);
 595         i915_gem_cleanup_engines(dev);
 596         i915_gem_context_fini(dev);
 597         mutex_unlock(&dev->struct_mutex);
 598
 599         WARN_ON(!list_empty(&to_i915(dev)->context_list));
 600 }
 601
 602 static int i915_load_modeset_init(struct drm_device *dev)
 603 {
 604         struct drm_i915_private *dev_priv = to_i915(dev);
 605         int ret;
 606
 607         if (i915_inject_load_failure())
 608                 return -ENODEV;
 609
 610         ret = intel_bios_init(dev_priv);
 611         if (ret)
 612                 DRM_INFO("failed to find VBIOS tables\n");
 613
 614         /* If we have > 1 VGA cards, then we need to arbitrate access
 615          * to the common VGA resources.
 616          *
 617          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 618          * then we do not take part in VGA arbitration and the
 619          * vga_client_register() fails with -ENODEV.
 620          */
 621         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 622         if (ret && ret != -ENODEV)
 623                 goto out;
 624
 625         intel_register_dsm_handler();
 626
 627         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 628         if (ret)
 629                 goto cleanup_vga_client;
 630
 631         /* must happen before intel_power_domains_init_hw() on VLV/CHV */
 632         intel_update_rawclk(dev_priv);
 633
 634         intel_power_domains_init_hw(dev_priv, false);
 635
 636         intel_csr_ucode_init(dev_priv);
 637
 638         ret = intel_irq_install(dev_priv);
 639         if (ret)
 640                 goto cleanup_csr;
 641
 642         intel_setup_gmbus(dev);
 643
 644         /* Important: The output setup functions called by modeset_init need
 645          * working irqs for e.g. gmbus and dp aux transfers. */
 646         intel_modeset_init(dev);
 647
 648         intel_guc_init(dev);
 649
 650         ret = i915_gem_init(dev);
 651         if (ret)
 652                 goto cleanup_irq;
 653
 654         intel_modeset_gem_init(dev);
 655
 656         if (INTEL_INFO(dev)->num_pipes == 0)
 657                 return 0;
 658
 659         ret = intel_fbdev_init(dev);
 660         if (ret)
 661                 goto cleanup_gem;
 662
 663         /* Only enable hotplug handling once the fbdev is fully set up. */
 664         intel_hpd_init(dev_priv);
 665
 666         drm_kms_helper_poll_init(dev);
 667
 668         return 0;
 669
 670 cleanup_gem:
 671         i915_gem_fini(dev);
 672 cleanup_irq:
 673         intel_guc_fini(dev);
 674         drm_irq_uninstall(dev);
 675         intel_teardown_gmbus(dev);
 676 cleanup_csr:
 677         intel_csr_ucode_fini(dev_priv);
 678         intel_power_domains_fini(dev_priv);
 679         vga_switcheroo_unregister_client(dev->pdev);
 680 cleanup_vga_client:
 681         vga_client_register(dev->pdev, NULL, NULL, NULL);
 682 out:
 683         return ret;
 684 }
 685
 686 #if IS_ENABLED(CONFIG_FB)
 687 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 688 {
 689         struct apertures_struct *ap;
 690         struct pci_dev *pdev = dev_priv->dev->pdev;
 691         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 692         bool primary;
 693         int ret;
 694
 695         ap = alloc_apertures(1);
 696         if (!ap)
 697                 return -ENOMEM;
 698
 699         ap->ranges[0].base = ggtt->mappable_base;
 700         ap->ranges[0].size = ggtt->mappable_end;
 701
 702         primary =
 703                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 704
 705         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 706
 707         kfree(ap);
 708
 709         return ret;
 710 }
 711 #else
 712 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 713 {
 714         return 0;
 715 }
 716 #endif
 717
 718 #if !defined(CONFIG_VGA_CONSOLE)
 719 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 720 {
 721         return 0;
 722 }
 723 #elif !defined(CONFIG_DUMMY_CONSOLE)
 724 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 725 {
 726         return -ENODEV;
 727 }
 728 #else
 729 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 730 {
 731         int ret = 0;
 732
 733         DRM_INFO("Replacing VGA console driver\n");
 734
 735         console_lock();
 736         if (con_is_bound(&vga_con))
 737                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 738         if (ret == 0) {
 739                 ret = do_unregister_con_driver(&vga_con);
 740
 741                 /* Ignore "already unregistered". */
 742                 if (ret == -ENODEV)
 743                         ret = 0;
 744         }
 745         console_unlock();
 746
 747         return ret;
 748 }
 749 #endif
 750
 751 static void intel_init_dpio(struct drm_i915_private *dev_priv)
 752 {
 753         /*
 754          * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
 755          * CHV x1 PHY (DP/HDMI D)
 756          * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
 757          */
 758         if (IS_CHERRYVIEW(dev_priv)) {
 759                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
 760                 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
 761         } else if (IS_VALLEYVIEW(dev_priv)) {
 762                 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
 763         }
 764 }
 765
 766 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 767 {
 768         /*
 769          * The i915 workqueue is primarily used for batched retirement of
 770          * requests (and thus managing bo) once the task has been completed
 771          * by the GPU. i915_gem_retire_requests() is called directly when we
 772          * need high-priority retirement, such as waiting for an explicit
 773          * bo.
 774          *
 775          * It is also used for periodic low-priority events, such as
 776          * idle-timers and recording error state.
 777          *
 778          * All tasks on the workqueue are expected to acquire the dev mutex
 779          * so there is no point in running more than one instance of the
 780          * workqueue at any time.  Use an ordered one.
 781          */
 782         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 783         if (dev_priv->wq == NULL)
 784                 goto out_err;
 785
 786         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 787         if (dev_priv->hotplug.dp_wq == NULL)
 788                 goto out_free_wq;
 789
 790         return 0;
 791
 792 out_free_wq:
 793         destroy_workqueue(dev_priv->wq);
 794 out_err:
 795         DRM_ERROR("Failed to allocate workqueues.\n");
 796
 797         return -ENOMEM;
 798 }
 799
 800 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 801 {
 802         destroy_workqueue(dev_priv->hotplug.dp_wq);
 803         destroy_workqueue(dev_priv->wq);
 804 }
 805
 806 /**
 807  * i915_driver_init_early - setup state not requiring device access
 808  * @dev_priv: device private
 809  *
 810  * Initialize everything that is a "SW-only" state, that is state not
 811  * requiring accessing the device or exposing the driver via kernel internal
 812  * or userspace interfaces. Example steps belonging here: lock initialization,
 813  * system memory allocation, setting up device specific attributes and
 814  * function hooks not requiring accessing the device.
 815  */
 816 static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 817                                   const struct pci_device_id *ent)
 818 {
 819         const struct intel_device_info *match_info =
 820                 (struct intel_device_info *)ent->driver_data;
 821         struct intel_device_info *device_info;
 822         int ret = 0;
 823
 824         if (i915_inject_load_failure())
 825                 return -ENODEV;
 826
 827         /* Setup the write-once "constant" device info */
 828         device_info = mkwrite_device_info(dev_priv);
 829         memcpy(device_info, match_info, sizeof(*device_info));
 830         device_info->device_id = dev_priv->drm.pdev->device;
 831
 832         BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE);
 833         device_info->gen_mask = BIT(device_info->gen - 1);
 834
 835         spin_lock_init(&dev_priv->irq_lock);
 836         spin_lock_init(&dev_priv->gpu_error.lock);
 837         mutex_init(&dev_priv->backlight_lock);
 838         spin_lock_init(&dev_priv->uncore.lock);
 839         spin_lock_init(&dev_priv->mm.object_stat_lock);
 840         spin_lock_init(&dev_priv->mmio_flip_lock);
 841         mutex_init(&dev_priv->sb_lock);
 842         mutex_init(&dev_priv->modeset_restore_lock);
 843         mutex_init(&dev_priv->av_mutex);
 844         mutex_init(&dev_priv->wm.wm_mutex);
 845         mutex_init(&dev_priv->pps_mutex);
 846
 847         ret = i915_workqueues_init(dev_priv);
 848         if (ret < 0)
 849                 return ret;
 850
 851         ret = intel_gvt_init(dev_priv);
 852         if (ret < 0)
 853                 goto err_workqueues;
 854
 855         /* This must be called before any calls to HAS_PCH_* */
 856         intel_detect_pch(&dev_priv->drm);
 857
 858         intel_pm_setup(&dev_priv->drm);
 859         intel_init_dpio(dev_priv);
 860         intel_power_domains_init(dev_priv);
 861         intel_irq_init(dev_priv);
 862         intel_init_display_hooks(dev_priv);
 863         intel_init_clock_gating_hooks(dev_priv);
 864         intel_init_audio_hooks(dev_priv);
 865         i915_gem_load_init(&dev_priv->drm);
 866
 867         intel_display_crc_init(&dev_priv->drm);
 868
 869         intel_device_info_dump(dev_priv);
 870
 871         /* Not all pre-production machines fall into this category, only the
 872          * very first ones. Almost everything should work, except for maybe
 873          * suspend/resume. And we don't implement workarounds that affect only
 874          * pre-production machines. */
 875         if (IS_HSW_EARLY_SDV(dev_priv))
 876                 DRM_INFO("This is an early pre-production Haswell machine. "
 877                          "It may not be fully functional.\n");
 878
 879         return 0;
 880
 881 err_workqueues:
 882         i915_workqueues_cleanup(dev_priv);
 883         return ret;
 884 }
 885
 886 /**
 887  * i915_driver_cleanup_early - cleanup the setup done in i915_driver_init_early()
 888  * @dev_priv: device private
 889  */
 890 static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
 891 {
 892         i915_gem_load_cleanup(dev_priv->dev);
 893         i915_workqueues_cleanup(dev_priv);
 894 }
 895
 896 static int i915_mmio_setup(struct drm_device *dev)
 897 {
 898         struct drm_i915_private *dev_priv = to_i915(dev);
 899         int mmio_bar;
 900         int mmio_size;
 901
 902         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 903         /*
 904          * Before gen4, the registers and the GTT are behind different BARs.
 905          * However, from gen4 onwards, the registers and the GTT are shared
 906          * in the same BAR, so we want to restrict this ioremap from
 907          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 908          * the register BAR remains the same size for all the earlier
 909          * generations up to Ironlake.
 910          */
 911         if (INTEL_INFO(dev)->gen < 5)
 912                 mmio_size = 512 * 1024;
 913         else
 914                 mmio_size = 2 * 1024 * 1024;
 915         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 916         if (dev_priv->regs == NULL) {
 917                 DRM_ERROR("failed to map registers\n");
 918
 919                 return -EIO;
 920         }
 921
 922         /* Try to make sure MCHBAR is enabled before poking at it */
 923         intel_setup_mchbar(dev);
 924
 925         return 0;
 926 }
 927
 928 static void i915_mmio_cleanup(struct drm_device *dev)
 929 {
 930         struct drm_i915_private *dev_priv = to_i915(dev);
 931
 932         intel_teardown_mchbar(dev);
 933         pci_iounmap(dev->pdev, dev_priv->regs);
 934 }
 935
 936 /**
 937  * i915_driver_init_mmio - setup device MMIO
 938  * @dev_priv: device private
 939  *
 940  * Setup minimal device state necessary for MMIO accesses later in the
 941  * initialization sequence. The setup here should avoid any other device-wide
 942  * side effects or exposing the driver via kernel internal or user space
 943  * interfaces.
 944  */
 945 static int i915_driver_init_mmio(struct drm_i915_private *dev_priv)
 946 {
 947         struct drm_device *dev = dev_priv->dev;
 948         int ret;
 949
 950         if (i915_inject_load_failure())
 951                 return -ENODEV;
 952
 953         if (i915_get_bridge_dev(dev))
 954                 return -EIO;
 955
 956         ret = i915_mmio_setup(dev);
 957         if (ret < 0)
 958                 goto put_bridge;
 959
 960         intel_uncore_init(dev_priv);
 961
 962         return 0;
 963
 964 put_bridge:
 965         pci_dev_put(dev_priv->bridge_dev);
 966
 967         return ret;
 968 }
 969
 970 /**
 971  * i915_driver_cleanup_mmio - cleanup the setup done in i915_driver_init_mmio()
 972  * @dev_priv: device private
 973  */
 974 static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv)
 975 {
 976         struct drm_device *dev = dev_priv->dev;
 977
 978         intel_uncore_fini(dev_priv);
 979         i915_mmio_cleanup(dev);
 980         pci_dev_put(dev_priv->bridge_dev);
 981 }
 982
 983 static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 984 {
 985         i915.enable_execlists =
 986                 intel_sanitize_enable_execlists(dev_priv,
 987                                                 i915.enable_execlists);
 988
 989         /*
 990          * i915.enable_ppgtt is read-only, so do an early pass to validate the
 991          * user's requested state against the hardware/driver capabilities.  We
 992          * do this now so that we can print out any log messages once rather
 993          * than every time we check intel_enable_ppgtt().
 994          */
 995         i915.enable_ppgtt =
 996                 intel_sanitize_enable_ppgtt(dev_priv, i915.enable_ppgtt);
 997         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
 998 }
 999
1000 /**
1001  * i915_driver_init_hw - setup state requiring device access
1002  * @dev_priv: device private
1003  *
1004  * Setup state that requires accessing the device, but doesn't require
1005  * exposing the driver via kernel internal or userspace interfaces.
1006  */
1007 static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
1008 {
1009         struct drm_device *dev = dev_priv->dev;
1010         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1011         uint32_t aperture_size;
1012         int ret;
1013
1014         if (i915_inject_load_failure())
1015                 return -ENODEV;
1016
1017         intel_device_info_runtime_init(dev_priv);
1018
1019         intel_sanitize_options(dev_priv);
1020
1021         ret = i915_ggtt_init_hw(dev);
1022         if (ret)
1023                 return ret;
1024
1025         ret = i915_ggtt_enable_hw(dev);
1026         if (ret) {
1027                 DRM_ERROR("failed to enable GGTT\n");
1028                 goto out_ggtt;
1029         }
1030
1031         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1032          * otherwise the vga fbdev driver falls over. */
1033         ret = i915_kick_out_firmware_fb(dev_priv);
1034         if (ret) {
1035                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1036                 goto out_ggtt;
1037         }
1038
1039         ret = i915_kick_out_vgacon(dev_priv);
1040         if (ret) {
1041                 DRM_ERROR("failed to remove conflicting VGA console\n");
1042                 goto out_ggtt;
1043         }
1044
1045         pci_set_master(dev->pdev);
1046
1047         /* overlay on gen2 is broken and can't address above 1G */
1048         if (IS_GEN2(dev)) {
1049                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1050                 if (ret) {
1051                         DRM_ERROR("failed to set DMA mask\n");
1052
1053                         goto out_ggtt;
1054                 }
1055         }
1056
1057
1058         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1059          * using 32bit addressing, overwriting memory if HWS is located
1060          * above 4GB.
1061          *
1062          * The documentation also mentions an issue with undefined
1063          * behaviour if any general state is accessed within a page above 4GB,
1064          * which also needs to be handled carefully.
1065          */
1066         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
1067                 ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1068
1069                 if (ret) {
1070                         DRM_ERROR("failed to set DMA mask\n");
1071
1072                         goto out_ggtt;
1073                 }
1074         }
1075
1076         aperture_size = ggtt->mappable_end;
1077
1078         ggtt->mappable =
1079                 io_mapping_create_wc(ggtt->mappable_base,
1080                                      aperture_size);
1081         if (!ggtt->mappable) {
1082                 ret = -EIO;
1083                 goto out_ggtt;
1084         }
1085
1086         ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
1087                                               aperture_size);
1088
1089         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
1090                            PM_QOS_DEFAULT_VALUE);
1091
1092         intel_uncore_sanitize(dev_priv);
1093
1094         intel_opregion_setup(dev_priv);
1095
1096         i915_gem_load_init_fences(dev_priv);
1097
1098         /* On the 945G/GM, the chipset reports the MSI capability on the
1099          * integrated graphics even though the support isn't actually there
1100          * according to the published specs.  It doesn't appear to function
1101          * correctly in testing on 945G.
1102          * This may be a side effect of MSI having been made available for PEG
1103          * and the registers being closely associated.
1104          *
1105          * According to chipset errata, on the 965GM, MSI interrupts may
1106          * be lost or delayed, but we use them anyways to avoid
1107          * stuck interrupts on some machines.
1108          */
1109         if (!IS_I945G(dev) && !IS_I945GM(dev)) {
1110                 if (pci_enable_msi(dev->pdev) < 0)
1111                         DRM_DEBUG_DRIVER("can't enable MSI");
1112         }
1113
1114         return 0;
1115
1116 out_ggtt:
1117         i915_ggtt_cleanup_hw(dev);
1118
1119         return ret;
1120 }
1121
1122 /**
1123  * i915_driver_cleanup_hw - cleanup the setup done in i915_driver_init_hw()
1124  * @dev_priv: device private
1125  */
1126 static void i915_driver_cleanup_hw(struct drm_i915_private *dev_priv)
1127 {
1128         struct drm_device *dev = dev_priv->dev;
1129         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1130
1131         if (dev->pdev->msi_enabled)
1132                 pci_disable_msi(dev->pdev);
1133
1134         pm_qos_remove_request(&dev_priv->pm_qos);
1135         arch_phys_wc_del(ggtt->mtrr);
1136         io_mapping_free(ggtt->mappable);
1137         i915_ggtt_cleanup_hw(dev);
1138 }
1139
1140 /**
1141  * i915_driver_register - register the driver with the rest of the system
1142  * @dev_priv: device private
1143  *
1144  * Perform any steps necessary to make the driver available via kernel
1145  * internal or userspace interfaces.
1146  */
1147 static void i915_driver_register(struct drm_i915_private *dev_priv)
1148 {
1149         struct drm_device *dev = dev_priv->dev;
1150
1151         i915_gem_shrinker_init(dev_priv);
1152
1153         /*
1154          * Notify a valid surface after modesetting,
1155          * when running inside a VM.
1156          */
1157         if (intel_vgpu_active(dev_priv))
1158                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1159
1160         /* Reveal our presence to userspace */
1161         if (drm_dev_register(dev, 0) == 0) {
1162                 i915_debugfs_register(dev_priv);
1163                 i915_setup_sysfs(dev);
1164         } else
1165                 DRM_ERROR("Failed to register driver for userspace access!\n");
1166
1167         if (INTEL_INFO(dev_priv)->num_pipes) {
1168                 /* Must be done after probing outputs */
1169                 intel_opregion_register(dev_priv);
1170                 acpi_video_register();
1171         }
1172
1173         if (IS_GEN5(dev_priv))
1174                 intel_gpu_ips_init(dev_priv);
1175
1176         i915_audio_component_init(dev_priv);
1177
1178         /*
1179          * Some ports require correctly set-up hpd registers for detection to
1180          * work properly (leading to ghost connected connector status), e.g. VGA
1181          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1182          * irqs are fully enabled. We do it last so that the async config
1183          * cannot run before the connectors are registered.
1184          */
1185         intel_fbdev_initial_config_async(dev);
1186 }
1187
1188 /**
1189  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
1190  * @dev_priv: device private
1191  */
1192 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
1193 {
1194         i915_audio_component_cleanup(dev_priv);
1195
1196         intel_gpu_ips_teardown();
1197         acpi_video_unregister();
1198         intel_opregion_unregister(dev_priv);
1199
1200         i915_teardown_sysfs(dev_priv->dev);
1201         i915_debugfs_unregister(dev_priv);
1202         drm_dev_unregister(dev_priv->dev);
1203
1204         i915_gem_shrinker_cleanup(dev_priv);
1205 }
1206
1207 /**
1208  * i915_driver_load - setup chip and create an initial config
1209  * @dev: DRM device
1210  * @flags: startup flags
1211  *
1212  * The driver load routine has to do several things:
1213  *   - drive output discovery via intel_modeset_init()
1214  *   - initialize the memory manager
1215  *   - allocate initial config memory
1216  *   - setup the DRM framebuffer with the allocated memory
1217  */
1218 int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
1219 {
1220         struct drm_i915_private *dev_priv;
1221         int ret;
1222
1223         if (i915.nuclear_pageflip)
1224                 driver.driver_features |= DRIVER_ATOMIC;
1225
1226         ret = -ENOMEM;
1227         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1228         if (dev_priv)
1229                 ret = drm_dev_init(&dev_priv->drm, &driver, &pdev->dev);
1230         if (ret) {
1231                 dev_printk(KERN_ERR, &pdev->dev,
1232                            "[" DRM_NAME ":%s] allocation failed\n", __func__);
1233                 kfree(dev_priv);
1234                 return ret;
1235         }
1236
1237         dev_priv->drm.pdev = pdev;
1238         dev_priv->drm.dev_private = dev_priv;
1239         dev_priv->dev = &dev_priv->drm;
1240
1241         ret = pci_enable_device(pdev);
1242         if (ret)
1243                 goto out_free_priv;
1244
1245         pci_set_drvdata(pdev, &dev_priv->drm);
1246
1247         ret = i915_driver_init_early(dev_priv, ent);
1248         if (ret < 0)
1249                 goto out_pci_disable;
1250
1251         intel_runtime_pm_get(dev_priv);
1252
1253         ret = i915_driver_init_mmio(dev_priv);
1254         if (ret < 0)
1255                 goto out_runtime_pm_put;
1256
1257         ret = i915_driver_init_hw(dev_priv);
1258         if (ret < 0)
1259                 goto out_cleanup_mmio;
1260
1261         /*
1262          * TODO: move the vblank init and parts of modeset init steps into one
1263          * of the i915_driver_init_/i915_driver_register functions according
1264          * to the role/effect of the given init step.
1265          */
1266         if (INTEL_INFO(dev_priv)->num_pipes) {
1267                 ret = drm_vblank_init(dev_priv->dev,
1268                                       INTEL_INFO(dev_priv)->num_pipes);
1269                 if (ret)
1270                         goto out_cleanup_hw;
1271         }
1272
1273         ret = i915_load_modeset_init(dev_priv->dev);
1274         if (ret < 0)
1275                 goto out_cleanup_vblank;
1276
1277         i915_driver_register(dev_priv);
1278
1279         intel_runtime_pm_enable(dev_priv);
1280
1281         intel_runtime_pm_put(dev_priv);
1282
1283         return 0;
1284
1285 out_cleanup_vblank:
1286         drm_vblank_cleanup(dev_priv->dev);
1287 out_cleanup_hw:
1288         i915_driver_cleanup_hw(dev_priv);
1289 out_cleanup_mmio:
1290         i915_driver_cleanup_mmio(dev_priv);
1291 out_runtime_pm_put:
1292         intel_runtime_pm_put(dev_priv);
1293         i915_driver_cleanup_early(dev_priv);
1294 out_pci_disable:
1295         pci_disable_device(pdev);
1296 out_free_priv:
1297         i915_load_error(dev_priv, "Device initialization failed (%d)\n", ret);
1298         drm_dev_unref(&dev_priv->drm);
1299         return ret;
1300 }
1301
1302 void i915_driver_unload(struct drm_device *dev)
1303 {
1304         struct drm_i915_private *dev_priv = to_i915(dev);
1305
1306         intel_fbdev_fini(dev);
1307
1308         if (i915_gem_suspend(dev))
1309                 DRM_ERROR("failed to idle hardware; continuing to unload!\n");
1310
1311         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1312
1313         i915_driver_unregister(dev_priv);
1314
1315         drm_vblank_cleanup(dev);
1316
1317         intel_modeset_cleanup(dev);
1318
1319         /*
1320          * free the memory space allocated for the child device
1321          * config parsed from VBT
1322          */
1323         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1324                 kfree(dev_priv->vbt.child_dev);
1325                 dev_priv->vbt.child_dev = NULL;
1326                 dev_priv->vbt.child_dev_num = 0;
1327         }
1328         kfree(dev_priv->vbt.sdvo_lvds_vbt_mode);
1329         dev_priv->vbt.sdvo_lvds_vbt_mode = NULL;
1330         kfree(dev_priv->vbt.lfp_lvds_vbt_mode);
1331         dev_priv->vbt.lfp_lvds_vbt_mode = NULL;
1332
1333         vga_switcheroo_unregister_client(dev->pdev);
1334         vga_client_register(dev->pdev, NULL, NULL, NULL);
1335
1336         intel_csr_ucode_fini(dev_priv);
1337
1338         /* Free error state after interrupts are fully disabled. */
1339         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1340         i915_destroy_error_state(dev);
1341
1342         /* Flush any outstanding unpin_work. */
1343         flush_workqueue(dev_priv->wq);
1344
1345         intel_guc_fini(dev);
1346         i915_gem_fini(dev);
1347         intel_fbc_cleanup_cfb(dev_priv);
1348
1349         intel_power_domains_fini(dev_priv);
1350
1351         i915_driver_cleanup_hw(dev_priv);
1352         i915_driver_cleanup_mmio(dev_priv);
1353
1354         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1355
1356         i915_driver_cleanup_early(dev_priv);
1357 }
1358
1359 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1360 {
1361         int ret;
1362
1363         ret = i915_gem_open(dev, file);
1364         if (ret)
1365                 return ret;
1366
1367         return 0;
1368 }
1369
1370 /**
1371  * i915_driver_lastclose - clean up after all DRM clients have exited
1372  * @dev: DRM device
1373  *
1374  * Take care of cleaning up after all DRM clients have exited.  In the
1375  * mode setting case, we want to restore the kernel's initial mode (just
1376  * in case the last client left us in a bad state).
1377  *
1378  * Additionally, in the non-mode setting case, we'll tear down the GTT
1379  * and DMA structures, since the kernel won't be using them, and clea
1380  * up any GEM state.
1381  */
1382 static void i915_driver_lastclose(struct drm_device *dev)
1383 {
1384         intel_fbdev_restore_mode(dev);
1385         vga_switcheroo_process_delayed_switch();
1386 }
1387
1388 static void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1389 {
1390         mutex_lock(&dev->struct_mutex);
1391         i915_gem_context_close(dev, file);
1392         i915_gem_release(dev, file);
1393         mutex_unlock(&dev->struct_mutex);
1394 }
1395
1396 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1397 {
1398         struct drm_i915_file_private *file_priv = file->driver_priv;
1399
1400         kfree(file_priv);
1401 }
1402
1403 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
1404 {
1405         struct drm_device *dev = dev_priv->dev;
1406         struct intel_encoder *encoder;
1407
1408         drm_modeset_lock_all(dev);
1409         for_each_intel_encoder(dev, encoder)
1410                 if (encoder->suspend)
1411                         encoder->suspend(encoder);
1412         drm_modeset_unlock_all(dev);
1413 }
1414
1415 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1416                               bool rpm_resume);
1417 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
1418
1419 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1420 {
1421 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1422         if (acpi_target_system_state() < ACPI_STATE_S3)
1423                 return true;
1424 #endif
1425         return false;
1426 }
1427
1428 static int i915_drm_suspend(struct drm_device *dev)
1429 {
1430         struct drm_i915_private *dev_priv = to_i915(dev);
1431         pci_power_t opregion_target_state;
1432         int error;
1433
1434         /* ignore lid events during suspend */
1435         mutex_lock(&dev_priv->modeset_restore_lock);
1436         dev_priv->modeset_restore = MODESET_SUSPENDED;
1437         mutex_unlock(&dev_priv->modeset_restore_lock);
1438
1439         disable_rpm_wakeref_asserts(dev_priv);
1440
1441         /* We do a lot of poking in a lot of registers, make sure they work
1442          * properly. */
1443         intel_display_set_init_power(dev_priv, true);
1444
1445         drm_kms_helper_poll_disable(dev);
1446
1447         pci_save_state(dev->pdev);
1448
1449         error = i915_gem_suspend(dev);
1450         if (error) {
1451                 dev_err(&dev->pdev->dev,
1452                         "GEM idle failed, resume might fail\n");
1453                 goto out;
1454         }
1455
1456         intel_guc_suspend(dev);
1457
1458         intel_suspend_gt_powersave(dev_priv);
1459
1460         intel_display_suspend(dev);
1461
1462         intel_dp_mst_suspend(dev);
1463
1464         intel_runtime_pm_disable_interrupts(dev_priv);
1465         intel_hpd_cancel_work(dev_priv);
1466
1467         intel_suspend_encoders(dev_priv);
1468
1469         intel_suspend_hw(dev);
1470
1471         i915_gem_suspend_gtt_mappings(dev);
1472
1473         i915_save_state(dev);
1474
1475         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1476         intel_opregion_notify_adapter(dev_priv, opregion_target_state);
1477
1478         intel_uncore_forcewake_reset(dev_priv, false);
1479         intel_opregion_unregister(dev_priv);
1480
1481         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1482
1483         dev_priv->suspend_count++;
1484
1485         intel_display_set_init_power(dev_priv, false);
1486
1487         intel_csr_ucode_suspend(dev_priv);
1488
1489 out:
1490         enable_rpm_wakeref_asserts(dev_priv);
1491
1492         return error;
1493 }
1494
1495 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
1496 {
1497         struct drm_i915_private *dev_priv = to_i915(drm_dev);
1498         bool fw_csr;
1499         int ret;
1500
1501         disable_rpm_wakeref_asserts(dev_priv);
1502
1503         fw_csr = !IS_BROXTON(dev_priv) &&
1504                 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
1505         /*
1506          * In case of firmware assisted context save/restore don't manually
1507          * deinit the power domains. This also means the CSR/DMC firmware will
1508          * stay active, it will power down any HW resources as required and
1509          * also enable deeper system power states that would be blocked if the
1510          * firmware was inactive.
1511          */
1512         if (!fw_csr)
1513                 intel_power_domains_suspend(dev_priv);
1514
1515         ret = 0;
1516         if (IS_BROXTON(dev_priv))
1517                 bxt_enable_dc9(dev_priv);
1518         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1519                 hsw_enable_pc8(dev_priv);
1520         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1521                 ret = vlv_suspend_complete(dev_priv);
1522
1523         if (ret) {
1524                 DRM_ERROR("Suspend complete failed: %d\n", ret);
1525                 if (!fw_csr)
1526                         intel_power_domains_init_hw(dev_priv, true);
1527
1528                 goto out;
1529         }
1530
1531         pci_disable_device(drm_dev->pdev);
1532         /*
1533          * During hibernation on some platforms the BIOS may try to access
1534          * the device even though it's already in D3 and hang the machine. So
1535          * leave the device in D0 on those platforms and hope the BIOS will
1536          * power down the device properly. The issue was seen on multiple old
1537          * GENs with different BIOS vendors, so having an explicit blacklist
1538          * is inpractical; apply the workaround on everything pre GEN6. The
1539          * platforms where the issue was seen:
1540          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1541          * Fujitsu FSC S7110
1542          * Acer Aspire 1830T
1543          */
1544         if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
1545                 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
1546
1547         dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
1548
1549 out:
1550         enable_rpm_wakeref_asserts(dev_priv);
1551
1552         return ret;
1553 }
1554
1555 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
1556 {
1557         int error;
1558
1559         if (!dev || !dev->dev_private) {
1560                 DRM_ERROR("dev: %p\n", dev);
1561                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
1562                 return -ENODEV;
1563         }
1564
1565         if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
1566                          state.event != PM_EVENT_FREEZE))
1567                 return -EINVAL;
1568
1569         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1570                 return 0;
1571
1572         error = i915_drm_suspend(dev);
1573         if (error)
1574                 return error;
1575
1576         return i915_drm_suspend_late(dev, false);
1577 }
1578
1579 static int i915_drm_resume(struct drm_device *dev)
1580 {
1581         struct drm_i915_private *dev_priv = to_i915(dev);
1582         int ret;
1583
1584         disable_rpm_wakeref_asserts(dev_priv);
1585
1586         ret = i915_ggtt_enable_hw(dev);
1587         if (ret)
1588                 DRM_ERROR("failed to re-enable GGTT\n");
1589
1590         intel_csr_ucode_resume(dev_priv);
1591
1592         mutex_lock(&dev->struct_mutex);
1593         i915_gem_restore_gtt_mappings(dev);
1594         mutex_unlock(&dev->struct_mutex);
1595
1596         i915_restore_state(dev);
1597         intel_opregion_setup(dev_priv);
1598
1599         intel_init_pch_refclk(dev);
1600         drm_mode_config_reset(dev);
1601
1602         /*
1603          * Interrupts have to be enabled before any batches are run. If not the
1604          * GPU will hang. i915_gem_init_hw() will initiate batches to
1605          * update/restore the context.
1606          *
1607          * Modeset enabling in intel_modeset_init_hw() also needs working
1608          * interrupts.
1609          */
1610         intel_runtime_pm_enable_interrupts(dev_priv);
1611
1612         mutex_lock(&dev->struct_mutex);
1613         if (i915_gem_init_hw(dev)) {
1614                 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
1615                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
1616         }
1617         mutex_unlock(&dev->struct_mutex);
1618
1619         intel_guc_resume(dev);
1620
1621         intel_modeset_init_hw(dev);
1622
1623         spin_lock_irq(&dev_priv->irq_lock);
1624         if (dev_priv->display.hpd_irq_setup)
1625                 dev_priv->display.hpd_irq_setup(dev_priv);
1626         spin_unlock_irq(&dev_priv->irq_lock);
1627
1628         intel_dp_mst_resume(dev);
1629
1630         intel_display_resume(dev);
1631
1632         /*
1633          * ... but also need to make sure that hotplug processing
1634          * doesn't cause havoc. Like in the driver load code we don't
1635          * bother with the tiny race here where we might loose hotplug
1636          * notifications.
1637          * */
1638         intel_hpd_init(dev_priv);
1639         /* Config may have changed between suspend and resume */
1640         drm_helper_hpd_irq_event(dev);
1641
1642         intel_opregion_register(dev_priv);
1643
1644         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1645
1646         mutex_lock(&dev_priv->modeset_restore_lock);
1647         dev_priv->modeset_restore = MODESET_DONE;
1648         mutex_unlock(&dev_priv->modeset_restore_lock);
1649
1650         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1651
1652         drm_kms_helper_poll_enable(dev);
1653
1654         enable_rpm_wakeref_asserts(dev_priv);
1655
1656         return 0;
1657 }
1658
1659 static int i915_drm_resume_early(struct drm_device *dev)
1660 {
1661         struct drm_i915_private *dev_priv = to_i915(dev);
1662         int ret;
1663
1664         /*
1665          * We have a resume ordering issue with the snd-hda driver also
1666          * requiring our device to be power up. Due to the lack of a
1667          * parent/child relationship we currently solve this with an early
1668          * resume hook.
1669          *
1670          * FIXME: This should be solved with a special hdmi sink device or
1671          * similar so that power domains can be employed.
1672          */
1673
1674         /*
1675          * Note that we need to set the power state explicitly, since we
1676          * powered off the device during freeze and the PCI core won't power
1677          * it back up for us during thaw. Powering off the device during
1678          * freeze is not a hard requirement though, and during the
1679          * suspend/resume phases the PCI core makes sure we get here with the
1680          * device powered on. So in case we change our freeze logic and keep
1681          * the device powered we can also remove the following set power state
1682          * call.
1683          */
1684         ret = pci_set_power_state(dev->pdev, PCI_D0);
1685         if (ret) {
1686                 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
1687                 goto out;
1688         }
1689
1690         /*
1691          * Note that pci_enable_device() first enables any parent bridge
1692          * device and only then sets the power state for this device. The
1693          * bridge enabling is a nop though, since bridge devices are resumed
1694          * first. The order of enabling power and enabling the device is
1695          * imposed by the PCI core as described above, so here we preserve the
1696          * same order for the freeze/thaw phases.
1697          *
1698          * TODO: eventually we should remove pci_disable_device() /
1699          * pci_enable_enable_device() from suspend/resume. Due to how they
1700          * depend on the device enable refcount we can't anyway depend on them
1701          * disabling/enabling the device.
1702          */
1703         if (pci_enable_device(dev->pdev)) {
1704                 ret = -EIO;
1705                 goto out;
1706         }
1707
1708         pci_set_master(dev->pdev);
1709
1710         disable_rpm_wakeref_asserts(dev_priv);
1711
1712         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1713                 ret = vlv_resume_prepare(dev_priv, false);
1714         if (ret)
1715                 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
1716                           ret);
1717
1718         intel_uncore_early_sanitize(dev_priv, true);
1719
1720         if (IS_BROXTON(dev_priv)) {
1721                 if (!dev_priv->suspended_to_idle)
1722                         gen9_sanitize_dc_state(dev_priv);
1723                 bxt_disable_dc9(dev_priv);
1724         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1725                 hsw_disable_pc8(dev_priv);
1726         }
1727
1728         intel_uncore_sanitize(dev_priv);
1729
1730         if (IS_BROXTON(dev_priv) ||
1731             !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
1732                 intel_power_domains_init_hw(dev_priv, true);
1733
1734         enable_rpm_wakeref_asserts(dev_priv);
1735
1736 out:
1737         dev_priv->suspended_to_idle = false;
1738
1739         return ret;
1740 }
1741
1742 int i915_resume_switcheroo(struct drm_device *dev)
1743 {
1744         int ret;
1745
1746         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1747                 return 0;
1748
1749         ret = i915_drm_resume_early(dev);
1750         if (ret)
1751                 return ret;
1752
1753         return i915_drm_resume(dev);
1754 }
1755
1756 /**
1757  * i915_reset - reset chip after a hang
1758  * @dev: drm device to reset
1759  *
1760  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
1761  * reset or otherwise an error code.
1762  *
1763  * Procedure is fairly simple:
1764  *   - reset the chip using the reset reg
1765  *   - re-init context state
1766  *   - re-init hardware status page
1767  *   - re-init ring buffer
1768  *   - re-init interrupt state
1769  *   - re-init display
1770  */
1771 int i915_reset(struct drm_i915_private *dev_priv)
1772 {
1773         struct drm_device *dev = dev_priv->dev;
1774         struct i915_gpu_error *error = &dev_priv->gpu_error;
1775         unsigned reset_counter;
1776         int ret;
1777
1778         intel_reset_gt_powersave(dev_priv);
1779
1780         mutex_lock(&dev->struct_mutex);
1781
1782         /* Clear any previous failed attempts at recovery. Time to try again. */
1783         atomic_andnot(I915_WEDGED, &error->reset_counter);
1784
1785         /* Clear the reset-in-progress flag and increment the reset epoch. */
1786         reset_counter = atomic_inc_return(&error->reset_counter);
1787         if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
1788                 ret = -EIO;
1789                 goto error;
1790         }
1791
1792         pr_notice("drm/i915: Resetting chip after gpu hang\n");
1793
1794         i915_gem_reset(dev);
1795
1796         ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
1797         if (ret) {
1798                 if (ret != -ENODEV)
1799                         DRM_ERROR("Failed to reset chip: %i\n", ret);
1800                 else
1801                         DRM_DEBUG_DRIVER("GPU reset disabled\n");
1802                 goto error;
1803         }
1804
1805         intel_overlay_reset(dev_priv);
1806
1807         /* Ok, now get things going again... */
1808
1809         /*
1810          * Everything depends on having the GTT running, so we need to start
1811          * there.  Fortunately we don't need to do this unless we reset the
1812          * chip at a PCI level.
1813          *
1814          * Next we need to restore the context, but we don't use those
1815          * yet either...
1816          *
1817          * Ring buffer needs to be re-initialized in the KMS case, or if X
1818          * was running at the time of the reset (i.e. we weren't VT
1819          * switched away).
1820          */
1821         ret = i915_gem_init_hw(dev);
1822         if (ret) {
1823                 DRM_ERROR("Failed hw init on reset %d\n", ret);
1824                 goto error;
1825         }
1826
1827         mutex_unlock(&dev->struct_mutex);
1828
1829         /*
1830          * rps/rc6 re-init is necessary to restore state lost after the
1831          * reset and the re-install of gt irqs. Skip for ironlake per
1832          * previous concerns that it doesn't respond well to some forms
1833          * of re-init after reset.
1834          */
1835         if (INTEL_INFO(dev)->gen > 5)
1836                 intel_enable_gt_powersave(dev_priv);
1837
1838         return 0;
1839
1840 error:
1841         atomic_or(I915_WEDGED, &error->reset_counter);
1842         mutex_unlock(&dev->struct_mutex);
1843         return ret;
1844 }
1845
1846 static int i915_pm_suspend(struct device *dev)
1847 {
1848         struct pci_dev *pdev = to_pci_dev(dev);
1849         struct drm_device *drm_dev = pci_get_drvdata(pdev);
1850
1851         if (!drm_dev || !drm_dev->dev_private) {
1852                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1853                 return -ENODEV;
1854         }
1855
1856         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1857                 return 0;
1858
1859         return i915_drm_suspend(drm_dev);
1860 }
1861
1862 static int i915_pm_suspend_late(struct device *dev)
1863 {
1864         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1865
1866         /*
1867          * We have a suspend ordering issue with the snd-hda driver also
1868          * requiring our device to be power up. Due to the lack of a
1869          * parent/child relationship we currently solve this with an late
1870          * suspend hook.
1871          *
1872          * FIXME: This should be solved with a special hdmi sink device or
1873          * similar so that power domains can be employed.
1874          */
1875         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1876                 return 0;
1877
1878         return i915_drm_suspend_late(drm_dev, false);
1879 }
1880
1881 static int i915_pm_poweroff_late(struct device *dev)
1882 {
1883         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1884
1885         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1886                 return 0;
1887
1888         return i915_drm_suspend_late(drm_dev, true);
1889 }
1890
1891 static int i915_pm_resume_early(struct device *dev)
1892 {
1893         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1894
1895         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1896                 return 0;
1897
1898         return i915_drm_resume_early(drm_dev);
1899 }
1900
1901 static int i915_pm_resume(struct device *dev)
1902 {
1903         struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1904
1905         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1906                 return 0;
1907
1908         return i915_drm_resume(drm_dev);
1909 }
1910
1911 /* freeze: before creating the hibernation_image */
1912 static int i915_pm_freeze(struct device *dev)
1913 {
1914         return i915_pm_suspend(dev);
1915 }
1916
1917 static int i915_pm_freeze_late(struct device *dev)
1918 {
1919         int ret;
1920
1921         ret = i915_pm_suspend_late(dev);
1922         if (ret)
1923                 return ret;
1924
1925         ret = i915_gem_freeze_late(dev_to_i915(dev));
1926         if (ret)
1927                 return ret;
1928
1929         return 0;
1930 }
1931
1932 /* thaw: called after creating the hibernation image, but before turning off. */
1933 static int i915_pm_thaw_early(struct device *dev)
1934 {
1935         return i915_pm_resume_early(dev);
1936 }
1937
1938 static int i915_pm_thaw(struct device *dev)
1939 {
1940         return i915_pm_resume(dev);
1941 }
1942
1943 /* restore: called after loading the hibernation image. */
1944 static int i915_pm_restore_early(struct device *dev)
1945 {
1946         return i915_pm_resume_early(dev);
1947 }
1948
1949 static int i915_pm_restore(struct device *dev)
1950 {
1951         return i915_pm_resume(dev);
1952 }
1953
1954 /*
1955  * Save all Gunit registers that may be lost after a D3 and a subsequent
1956  * S0i[R123] transition. The list of registers needing a save/restore is
1957  * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1958  * registers in the following way:
1959  * - Driver: saved/restored by the driver
1960  * - Punit : saved/restored by the Punit firmware
1961  * - No, w/o marking: no need to save/restore, since the register is R/O or
1962  *                    used internally by the HW in a way that doesn't depend
1963  *                    keeping the content across a suspend/resume.
1964  * - Debug : used for debugging
1965  *
1966  * We save/restore all registers marked with 'Driver', with the following
1967  * exceptions:
1968  * - Registers out of use, including also registers marked with 'Debug'.
1969  *   These have no effect on the driver's operation, so we don't save/restore
1970  *   them to reduce the overhead.
1971  * - Registers that are fully setup by an initialization function called from
1972  *   the resume path. For example many clock gating and RPS/RC6 registers.
1973  * - Registers that provide the right functionality with their reset defaults.
1974  *
1975  * TODO: Except for registers that based on the above 3 criteria can be safely
1976  * ignored, we save/restore all others, practically treating the HW context as
1977  * a black-box for the driver. Further investigation is needed to reduce the
1978  * saved/restored registers even further, by following the same 3 criteria.
1979  */
1980 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1981 {
1982         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1983         int i;
1984
1985         /* GAM 0x4000-0x4770 */
1986         s->wr_watermark         = I915_READ(GEN7_WR_WATERMARK);
1987         s->gfx_prio_ctrl        = I915_READ(GEN7_GFX_PRIO_CTRL);
1988         s->arb_mode             = I915_READ(ARB_MODE);
1989         s->gfx_pend_tlb0        = I915_READ(GEN7_GFX_PEND_TLB0);
1990         s->gfx_pend_tlb1        = I915_READ(GEN7_GFX_PEND_TLB1);
1991
1992         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1993                 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1994
1995         s->media_max_req_count  = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1996         s->gfx_max_req_count    = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1997
1998         s->render_hwsp          = I915_READ(RENDER_HWS_PGA_GEN7);
1999         s->ecochk               = I915_READ(GAM_ECOCHK);
2000         s->bsd_hwsp             = I915_READ(BSD_HWS_PGA_GEN7);
2001         s->blt_hwsp             = I915_READ(BLT_HWS_PGA_GEN7);
2002
2003         s->tlb_rd_addr          = I915_READ(GEN7_TLB_RD_ADDR);
2004
2005         /* MBC 0x9024-0x91D0, 0x8500 */
2006         s->g3dctl               = I915_READ(VLV_G3DCTL);
2007         s->gsckgctl             = I915_READ(VLV_GSCKGCTL);
2008         s->mbctl                = I915_READ(GEN6_MBCTL);
2009
2010         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2011         s->ucgctl1              = I915_READ(GEN6_UCGCTL1);
2012         s->ucgctl3              = I915_READ(GEN6_UCGCTL3);
2013         s->rcgctl1              = I915_READ(GEN6_RCGCTL1);
2014         s->rcgctl2              = I915_READ(GEN6_RCGCTL2);
2015         s->rstctl               = I915_READ(GEN6_RSTCTL);
2016         s->misccpctl            = I915_READ(GEN7_MISCCPCTL);
2017
2018         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2019         s->gfxpause             = I915_READ(GEN6_GFXPAUSE);
2020         s->rpdeuhwtc            = I915_READ(GEN6_RPDEUHWTC);
2021         s->rpdeuc               = I915_READ(GEN6_RPDEUC);
2022         s->ecobus               = I915_READ(ECOBUS);
2023         s->pwrdwnupctl          = I915_READ(VLV_PWRDWNUPCTL);
2024         s->rp_down_timeout      = I915_READ(GEN6_RP_DOWN_TIMEOUT);
2025         s->rp_deucsw            = I915_READ(GEN6_RPDEUCSW);
2026         s->rcubmabdtmr          = I915_READ(GEN6_RCUBMABDTMR);
2027         s->rcedata              = I915_READ(VLV_RCEDATA);
2028         s->spare2gh             = I915_READ(VLV_SPAREG2H);
2029
2030         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2031         s->gt_imr               = I915_READ(GTIMR);
2032         s->gt_ier               = I915_READ(GTIER);
2033         s->pm_imr               = I915_READ(GEN6_PMIMR);
2034         s->pm_ier               = I915_READ(GEN6_PMIER);
2035
2036         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2037                 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
2038
2039         /* GT SA CZ domain, 0x100000-0x138124 */
2040         s->tilectl              = I915_READ(TILECTL);
2041         s->gt_fifoctl           = I915_READ(GTFIFOCTL);
2042         s->gtlc_wake_ctrl       = I915_READ(VLV_GTLC_WAKE_CTRL);
2043         s->gtlc_survive         = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2044         s->pmwgicz              = I915_READ(VLV_PMWGICZ);
2045
2046         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2047         s->gu_ctl0              = I915_READ(VLV_GU_CTL0);
2048         s->gu_ctl1              = I915_READ(VLV_GU_CTL1);
2049         s->pcbr                 = I915_READ(VLV_PCBR);
2050         s->clock_gate_dis2      = I915_READ(VLV_GUNIT_CLOCK_GATE2);
2051
2052         /*
2053          * Not saving any of:
2054          * DFT,         0x9800-0x9EC0
2055          * SARB,        0xB000-0xB1FC
2056          * GAC,         0x5208-0x524C, 0x14000-0x14C000
2057          * PCI CFG
2058          */
2059 }
2060
2061 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
2062 {
2063         struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
2064         u32 val;
2065         int i;
2066
2067         /* GAM 0x4000-0x4770 */
2068         I915_WRITE(GEN7_WR_WATERMARK,   s->wr_watermark);
2069         I915_WRITE(GEN7_GFX_PRIO_CTRL,  s->gfx_prio_ctrl);
2070         I915_WRITE(ARB_MODE,            s->arb_mode | (0xffff << 16));
2071         I915_WRITE(GEN7_GFX_PEND_TLB0,  s->gfx_pend_tlb0);
2072         I915_WRITE(GEN7_GFX_PEND_TLB1,  s->gfx_pend_tlb1);
2073
2074         for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
2075                 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
2076
2077         I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
2078         I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
2079
2080         I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
2081         I915_WRITE(GAM_ECOCHK,          s->ecochk);
2082         I915_WRITE(BSD_HWS_PGA_GEN7,    s->bsd_hwsp);
2083         I915_WRITE(BLT_HWS_PGA_GEN7,    s->blt_hwsp);
2084
2085         I915_WRITE(GEN7_TLB_RD_ADDR,    s->tlb_rd_addr);
2086
2087         /* MBC 0x9024-0x91D0, 0x8500 */
2088         I915_WRITE(VLV_G3DCTL,          s->g3dctl);
2089         I915_WRITE(VLV_GSCKGCTL,        s->gsckgctl);
2090         I915_WRITE(GEN6_MBCTL,          s->mbctl);
2091
2092         /* GCP 0x9400-0x9424, 0x8100-0x810C */
2093         I915_WRITE(GEN6_UCGCTL1,        s->ucgctl1);
2094         I915_WRITE(GEN6_UCGCTL3,        s->ucgctl3);
2095         I915_WRITE(GEN6_RCGCTL1,        s->rcgctl1);
2096         I915_WRITE(GEN6_RCGCTL2,        s->rcgctl2);
2097         I915_WRITE(GEN6_RSTCTL,         s->rstctl);
2098         I915_WRITE(GEN7_MISCCPCTL,      s->misccpctl);
2099
2100         /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
2101         I915_WRITE(GEN6_GFXPAUSE,       s->gfxpause);
2102         I915_WRITE(GEN6_RPDEUHWTC,      s->rpdeuhwtc);
2103         I915_WRITE(GEN6_RPDEUC,         s->rpdeuc);
2104         I915_WRITE(ECOBUS,              s->ecobus);
2105         I915_WRITE(VLV_PWRDWNUPCTL,     s->pwrdwnupctl);
2106         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
2107         I915_WRITE(GEN6_RPDEUCSW,       s->rp_deucsw);
2108         I915_WRITE(GEN6_RCUBMABDTMR,    s->rcubmabdtmr);
2109         I915_WRITE(VLV_RCEDATA,         s->rcedata);
2110         I915_WRITE(VLV_SPAREG2H,        s->spare2gh);
2111
2112         /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
2113         I915_WRITE(GTIMR,               s->gt_imr);
2114         I915_WRITE(GTIER,               s->gt_ier);
2115         I915_WRITE(GEN6_PMIMR,          s->pm_imr);
2116         I915_WRITE(GEN6_PMIER,          s->pm_ier);
2117
2118         for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
2119                 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
2120
2121         /* GT SA CZ domain, 0x100000-0x138124 */
2122         I915_WRITE(TILECTL,                     s->tilectl);
2123         I915_WRITE(GTFIFOCTL,                   s->gt_fifoctl);
2124         /*
2125          * Preserve the GT allow wake and GFX force clock bit, they are not
2126          * be restored, as they are used to control the s0ix suspend/resume
2127          * sequence by the caller.
2128          */
2129         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2130         val &= VLV_GTLC_ALLOWWAKEREQ;
2131         val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
2132         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2133
2134         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2135         val &= VLV_GFX_CLK_FORCE_ON_BIT;
2136         val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
2137         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2138
2139         I915_WRITE(VLV_PMWGICZ,                 s->pmwgicz);
2140
2141         /* Gunit-Display CZ domain, 0x182028-0x1821CF */
2142         I915_WRITE(VLV_GU_CTL0,                 s->gu_ctl0);
2143         I915_WRITE(VLV_GU_CTL1,                 s->gu_ctl1);
2144         I915_WRITE(VLV_PCBR,                    s->pcbr);
2145         I915_WRITE(VLV_GUNIT_CLOCK_GATE2,       s->clock_gate_dis2);
2146 }
2147
2148 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
2149 {
2150         u32 val;
2151         int err;
2152
2153         val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
2154         val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
2155         if (force_on)
2156                 val |= VLV_GFX_CLK_FORCE_ON_BIT;
2157         I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
2158
2159         if (!force_on)
2160                 return 0;
2161
2162         err = intel_wait_for_register(dev_priv,
2163                                       VLV_GTLC_SURVIVABILITY_REG,
2164                                       VLV_GFX_CLK_STATUS_BIT,
2165                                       VLV_GFX_CLK_STATUS_BIT,
2166                                       20);
2167         if (err)
2168                 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
2169                           I915_READ(VLV_GTLC_SURVIVABILITY_REG));
2170
2171         return err;
2172 }
2173
2174 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
2175 {
2176         u32 val;
2177         int err = 0;
2178
2179         val = I915_READ(VLV_GTLC_WAKE_CTRL);
2180         val &= ~VLV_GTLC_ALLOWWAKEREQ;
2181         if (allow)
2182                 val |= VLV_GTLC_ALLOWWAKEREQ;
2183         I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
2184         POSTING_READ(VLV_GTLC_WAKE_CTRL);
2185
2186         err = intel_wait_for_register(dev_priv,
2187                                       VLV_GTLC_PW_STATUS,
2188                                       VLV_GTLC_ALLOWWAKEACK,
2189                                       allow,
2190                                       1);
2191         if (err)
2192                 DRM_ERROR("timeout disabling GT waking\n");
2193
2194         return err;
2195 }
2196
2197 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
2198                                  bool wait_for_on)
2199 {
2200         u32 mask;
2201         u32 val;
2202         int err;
2203
2204         mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
2205         val = wait_for_on ? mask : 0;
2206         if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
2207                 return 0;
2208
2209         DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
2210                       onoff(wait_for_on),
2211                       I915_READ(VLV_GTLC_PW_STATUS));
2212
2213         /*
2214          * RC6 transitioning can be delayed up to 2 msec (see
2215          * valleyview_enable_rps), use 3 msec for safety.
2216          */
2217         err = intel_wait_for_register(dev_priv,
2218                                       VLV_GTLC_PW_STATUS, mask, val,
2219                                       3);
2220         if (err)
2221                 DRM_ERROR("timeout waiting for GT wells to go %s\n",
2222                           onoff(wait_for_on));
2223
2224         return err;
2225 }
2226
2227 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
2228 {
2229         if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
2230                 return;
2231
2232         DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
2233         I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
2234 }
2235
2236 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
2237 {
2238         u32 mask;
2239         int err;
2240
2241         /*
2242          * Bspec defines the following GT well on flags as debug only, so
2243          * don't treat them as hard failures.
2244          */
2245         (void)vlv_wait_for_gt_wells(dev_priv, false);
2246
2247         mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
2248         WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
2249
2250         vlv_check_no_gt_access(dev_priv);
2251
2252         err = vlv_force_gfx_clock(dev_priv, true);
2253         if (err)
2254                 goto err1;
2255
2256         err = vlv_allow_gt_wake(dev_priv, false);
2257         if (err)
2258                 goto err2;
2259
2260         if (!IS_CHERRYVIEW(dev_priv))
2261                 vlv_save_gunit_s0ix_state(dev_priv);
2262
2263         err = vlv_force_gfx_clock(dev_priv, false);
2264         if (err)
2265                 goto err2;
2266
2267         return 0;
2268
2269 err2:
2270         /* For safety always re-enable waking and disable gfx clock forcing */
2271         vlv_allow_gt_wake(dev_priv, true);
2272 err1:
2273         vlv_force_gfx_clock(dev_priv, false);
2274
2275         return err;
2276 }
2277
2278 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
2279                                 bool rpm_resume)
2280 {
2281         struct drm_device *dev = dev_priv->dev;
2282         int err;
2283         int ret;
2284
2285         /*
2286          * If any of the steps fail just try to continue, that's the best we
2287          * can do at this point. Return the first error code (which will also
2288          * leave RPM permanently disabled).
2289          */
2290         ret = vlv_force_gfx_clock(dev_priv, true);
2291
2292         if (!IS_CHERRYVIEW(dev_priv))
2293                 vlv_restore_gunit_s0ix_state(dev_priv);
2294
2295         err = vlv_allow_gt_wake(dev_priv, true);
2296         if (!ret)
2297                 ret = err;
2298
2299         err = vlv_force_gfx_clock(dev_priv, false);
2300         if (!ret)
2301                 ret = err;
2302
2303         vlv_check_no_gt_access(dev_priv);
2304
2305         if (rpm_resume) {
2306                 intel_init_clock_gating(dev);
2307                 i915_gem_restore_fences(dev);
2308         }
2309
2310         return ret;
2311 }
2312
2313 static int intel_runtime_suspend(struct device *device)
2314 {
2315         struct pci_dev *pdev = to_pci_dev(device);
2316         struct drm_device *dev = pci_get_drvdata(pdev);
2317         struct drm_i915_private *dev_priv = to_i915(dev);
2318         int ret;
2319
2320         if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
2321                 return -ENODEV;
2322
2323         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2324                 return -ENODEV;
2325
2326         DRM_DEBUG_KMS("Suspending device\n");
2327
2328         /*
2329          * We could deadlock here in case another thread holding struct_mutex
2330          * calls RPM suspend concurrently, since the RPM suspend will wait
2331          * first for this RPM suspend to finish. In this case the concurrent
2332          * RPM resume will be followed by its RPM suspend counterpart. Still
2333          * for consistency return -EAGAIN, which will reschedule this suspend.
2334          */
2335         if (!mutex_trylock(&dev->struct_mutex)) {
2336                 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
2337                 /*
2338                  * Bump the expiration timestamp, otherwise the suspend won't
2339                  * be rescheduled.
2340                  */
2341                 pm_runtime_mark_last_busy(device);
2342
2343                 return -EAGAIN;
2344         }
2345
2346         disable_rpm_wakeref_asserts(dev_priv);
2347
2348         /*
2349          * We are safe here against re-faults, since the fault handler takes
2350          * an RPM reference.
2351          */
2352         i915_gem_release_all_mmaps(dev_priv);
2353         mutex_unlock(&dev->struct_mutex);
2354
2355         intel_guc_suspend(dev);
2356
2357         intel_runtime_pm_disable_interrupts(dev_priv);
2358
2359         ret = 0;
2360         if (IS_BROXTON(dev_priv)) {
2361                 bxt_display_core_uninit(dev_priv);
2362                 bxt_enable_dc9(dev_priv);
2363         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2364                 hsw_enable_pc8(dev_priv);
2365         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2366                 ret = vlv_suspend_complete(dev_priv);
2367         }
2368
2369         if (ret) {
2370                 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
2371                 intel_runtime_pm_enable_interrupts(dev_priv);
2372
2373                 enable_rpm_wakeref_asserts(dev_priv);
2374
2375                 return ret;
2376         }
2377
2378         intel_uncore_forcewake_reset(dev_priv, false);
2379
2380         enable_rpm_wakeref_asserts(dev_priv);
2381         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2382
2383         if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
2384                 DRM_ERROR("Unclaimed access detected prior to suspending\n");
2385
2386         dev_priv->pm.suspended = true;
2387
2388         /*
2389          * FIXME: We really should find a document that references the arguments
2390          * used below!
2391          */
2392         if (IS_BROADWELL(dev_priv)) {
2393                 /*
2394                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
2395                  * being detected, and the call we do at intel_runtime_resume()
2396                  * won't be able to restore them. Since PCI_D3hot matches the
2397                  * actual specification and appears to be working, use it.
2398                  */
2399                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
2400         } else {
2401                 /*
2402                  * current versions of firmware which depend on this opregion
2403                  * notification have repurposed the D1 definition to mean
2404                  * "runtime suspended" vs. what you would normally expect (D3)
2405                  * to distinguish it from notifications that might be sent via
2406                  * the suspend path.
2407                  */
2408                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
2409         }
2410
2411         assert_forcewakes_inactive(dev_priv);
2412
2413         DRM_DEBUG_KMS("Device suspended\n");
2414         return 0;
2415 }
2416
2417 static int intel_runtime_resume(struct device *device)
2418 {
2419         struct pci_dev *pdev = to_pci_dev(device);
2420         struct drm_device *dev = pci_get_drvdata(pdev);
2421         struct drm_i915_private *dev_priv = to_i915(dev);
2422         int ret = 0;
2423
2424         if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
2425                 return -ENODEV;
2426
2427         DRM_DEBUG_KMS("Resuming device\n");
2428
2429         WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
2430         disable_rpm_wakeref_asserts(dev_priv);
2431
2432         intel_opregion_notify_adapter(dev_priv, PCI_D0);
2433         dev_priv->pm.suspended = false;
2434         if (intel_uncore_unclaimed_mmio(dev_priv))
2435                 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
2436
2437         intel_guc_resume(dev);
2438
2439         if (IS_GEN6(dev_priv))
2440                 intel_init_pch_refclk(dev);
2441
2442         if (IS_BROXTON(dev)) {
2443                 bxt_disable_dc9(dev_priv);
2444                 bxt_display_core_init(dev_priv, true);
2445                 if (dev_priv->csr.dmc_payload &&
2446                     (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
2447                         gen9_enable_dc5(dev_priv);
2448         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2449                 hsw_disable_pc8(dev_priv);
2450         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2451                 ret = vlv_resume_prepare(dev_priv, true);
2452         }
2453
2454         /*
2455          * No point of rolling back things in case of an error, as the best
2456          * we can do is to hope that things will still work (and disable RPM).
2457          */
2458         i915_gem_init_swizzling(dev);
2459         gen6_update_ring_freq(dev_priv);
2460
2461         intel_runtime_pm_enable_interrupts(dev_priv);
2462
2463         /*
2464          * On VLV/CHV display interrupts are part of the display
2465          * power well, so hpd is reinitialized from there. For
2466          * everyone else do it here.
2467          */
2468         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
2469                 intel_hpd_init(dev_priv);
2470
2471         enable_rpm_wakeref_asserts(dev_priv);
2472
2473         if (ret)
2474                 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
2475         else
2476                 DRM_DEBUG_KMS("Device resumed\n");
2477
2478         return ret;
2479 }
2480
2481 const struct dev_pm_ops i915_pm_ops = {
2482         /*
2483          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
2484          * PMSG_RESUME]
2485          */
2486         .suspend = i915_pm_suspend,
2487         .suspend_late = i915_pm_suspend_late,
2488         .resume_early = i915_pm_resume_early,
2489         .resume = i915_pm_resume,
2490
2491         /*
2492          * S4 event handlers
2493          * @freeze, @freeze_late    : called (1) before creating the
2494          *                            hibernation image [PMSG_FREEZE] and
2495          *                            (2) after rebooting, before restoring
2496          *                            the image [PMSG_QUIESCE]
2497          * @thaw, @thaw_early       : called (1) after creating the hibernation
2498          *                            image, before writing it [PMSG_THAW]
2499          *                            and (2) after failing to create or
2500          *                            restore the image [PMSG_RECOVER]
2501          * @poweroff, @poweroff_late: called after writing the hibernation
2502          *                            image, before rebooting [PMSG_HIBERNATE]
2503          * @restore, @restore_early : called after rebooting and restoring the
2504          *                            hibernation image [PMSG_RESTORE]
2505          */
2506         .freeze = i915_pm_freeze,
2507         .freeze_late = i915_pm_freeze_late,
2508         .thaw_early = i915_pm_thaw_early,
2509         .thaw = i915_pm_thaw,
2510         .poweroff = i915_pm_suspend,
2511         .poweroff_late = i915_pm_poweroff_late,
2512         .restore_early = i915_pm_restore_early,
2513         .restore = i915_pm_restore,
2514
2515         /* S0ix (via runtime suspend) event handlers */
2516         .runtime_suspend = intel_runtime_suspend,
2517         .runtime_resume = intel_runtime_resume,
2518 };
2519
2520 static const struct vm_operations_struct i915_gem_vm_ops = {
2521         .fault = i915_gem_fault,
2522         .open = drm_gem_vm_open,
2523         .close = drm_gem_vm_close,
2524 };
2525
2526 static const struct file_operations i915_driver_fops = {
2527         .owner = THIS_MODULE,
2528         .open = drm_open,
2529         .release = drm_release,
2530         .unlocked_ioctl = drm_ioctl,
2531         .mmap = drm_gem_mmap,
2532         .poll = drm_poll,
2533         .read = drm_read,
2534 #ifdef CONFIG_COMPAT
2535         .compat_ioctl = i915_compat_ioctl,
2536 #endif
2537         .llseek = noop_llseek,
2538 };
2539
2540 static int
2541 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
2542                           struct drm_file *file)
2543 {
2544         return -ENODEV;
2545 }
2546
2547 static const struct drm_ioctl_desc i915_ioctls[] = {
2548         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2549         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
2550         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
2551         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
2552         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
2553         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
2554         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2555         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2556         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2557         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2558         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2559         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
2560         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2561         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2562         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
2563         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
2564         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2565         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2566         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
2567         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_RENDER_ALLOW),
2568         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2569         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
2570         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2571         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
2572         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
2573         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2574         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2575         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2576         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
2577         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
2578         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
2579         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
2580         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_RENDER_ALLOW),
2581         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
2582         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
2583         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_RENDER_ALLOW),
2584         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_RENDER_ALLOW),
2585         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
2586         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, 0),
2587         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
2588         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2589         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW),
2590         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW),
2591         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW),
2592         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
2593         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
2594         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
2595         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
2596         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
2597         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
2598         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
2599         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
2600 };
2601
2602 static struct drm_driver driver = {
2603         /* Don't use MTRRs here; the Xserver or userspace app should
2604          * deal with them for Intel hardware.
2605          */
2606         .driver_features =
2607             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
2608             DRIVER_RENDER | DRIVER_MODESET,
2609         .open = i915_driver_open,
2610         .lastclose = i915_driver_lastclose,
2611         .preclose = i915_driver_preclose,
2612         .postclose = i915_driver_postclose,
2613         .set_busid = drm_pci_set_busid,
2614
2615         .gem_free_object = i915_gem_free_object,
2616         .gem_vm_ops = &i915_gem_vm_ops,
2617
2618         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
2619         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
2620         .gem_prime_export = i915_gem_prime_export,
2621         .gem_prime_import = i915_gem_prime_import,
2622
2623         .dumb_create = i915_gem_dumb_create,
2624         .dumb_map_offset = i915_gem_mmap_gtt,
2625         .dumb_destroy = drm_gem_dumb_destroy,
2626         .ioctls = i915_ioctls,
2627         .num_ioctls = ARRAY_SIZE(i915_ioctls),
2628         .fops = &i915_driver_fops,
2629         .name = DRIVER_NAME,
2630         .desc = DRIVER_DESC,
2631         .date = DRIVER_DATE,
2632         .major = DRIVER_MAJOR,
2633         .minor = DRIVER_MINOR,
2634         .patchlevel = DRIVER_PATCHLEVEL,
2635 };