drivers/gpu/drm/i915/i915_drv.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/device.h>
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "intel_drv.h"
  36
  37 #include <linux/console.h>
  38 #include <linux/module.h>
  39 #include "drm_crtc_helper.h"
  40
  41 static int i915_modeset __read_mostly = -1;
  42 module_param_named(modeset, i915_modeset, int, 0400);
  43 MODULE_PARM_DESC(modeset,
  44                 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
  45                 "1=on, -1=force vga console preference [default])");
  46
  47 unsigned int i915_fbpercrtc __always_unused = 0;
  48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
  49
  50 int i915_panel_ignore_lid __read_mostly = 0;
  51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
  52 MODULE_PARM_DESC(panel_ignore_lid,
  53                 "Override lid status (0=autodetect [default], 1=lid open, "
  54                 "-1=lid closed)");
  55
  56 unsigned int i915_powersave __read_mostly = 1;
  57 module_param_named(powersave, i915_powersave, int, 0600);
  58 MODULE_PARM_DESC(powersave,
  59                 "Enable powersavings, fbc, downclocking, etc. (default: true)");
  60
  61 int i915_semaphores __read_mostly = -1;
  62 module_param_named(semaphores, i915_semaphores, int, 0600);
  63 MODULE_PARM_DESC(semaphores,
  64                 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
  65
  66 int i915_enable_rc6 __read_mostly = -1;
  67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
  68 MODULE_PARM_DESC(i915_enable_rc6,
  69                 "Enable power-saving render C-state 6 (default: -1 (use per-chip default)");
  70
  71 int i915_enable_fbc __read_mostly = -1;
  72 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
  73 MODULE_PARM_DESC(i915_enable_fbc,
  74                 "Enable frame buffer compression for power savings "
  75                 "(default: -1 (use per-chip default))");
  76
  77 unsigned int i915_lvds_downclock __read_mostly = 0;
  78 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
  79 MODULE_PARM_DESC(lvds_downclock,
  80                 "Use panel (LVDS/eDP) downclocking for power savings "
  81                 "(default: false)");
  82
  83 int i915_lvds_channel_mode __read_mostly;
  84 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
  85 MODULE_PARM_DESC(lvds_channel_mode,
  86                  "Specify LVDS channel mode "
  87                  "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
  88
  89 int i915_panel_use_ssc __read_mostly = -1;
  90 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
  91 MODULE_PARM_DESC(lvds_use_ssc,
  92                 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
  93                 "(default: auto from VBT)");
  94
  95 int i915_vbt_sdvo_panel_type __read_mostly = -1;
  96 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
  97 MODULE_PARM_DESC(vbt_sdvo_panel_type,
  98                 "Override/Ignore selection of SDVO panel mode in the VBT "
  99                 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
 100
 101 static bool i915_try_reset __read_mostly = true;
 102 module_param_named(reset, i915_try_reset, bool, 0600);
 103 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
 104
 105 bool i915_enable_hangcheck __read_mostly = true;
 106 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
 107 MODULE_PARM_DESC(enable_hangcheck,
 108                 "Periodically check GPU activity for detecting hangs. "
 109                 "WARNING: Disabling this can cause system wide hangs. "
 110                 "(default: true)");
 111
 112 bool i915_enable_ppgtt __read_mostly = 1;
 113 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, bool, 0600);
 114 MODULE_PARM_DESC(i915_enable_ppgtt,
 115                 "Enable PPGTT (default: true)");
 116
 117 static struct drm_driver driver;
 118 extern int intel_agp_enabled;
 119
 120 #define INTEL_VGA_DEVICE(id, info) {            \
 121         .class = PCI_BASE_CLASS_DISPLAY << 16,  \
 122         .class_mask = 0xff0000,                 \
 123         .vendor = 0x8086,                       \
 124         .device = id,                           \
 125         .subvendor = PCI_ANY_ID,                \
 126         .subdevice = PCI_ANY_ID,                \
 127         .driver_data = (unsigned long) info }
 128
 129 static const struct intel_device_info intel_i830_info = {
 130         .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
 131         .has_overlay = 1, .overlay_needs_physical = 1,
 132 };
 133
 134 static const struct intel_device_info intel_845g_info = {
 135         .gen = 2,
 136         .has_overlay = 1, .overlay_needs_physical = 1,
 137 };
 138
 139 static const struct intel_device_info intel_i85x_info = {
 140         .gen = 2, .is_i85x = 1, .is_mobile = 1,
 141         .cursor_needs_physical = 1,
 142         .has_overlay = 1, .overlay_needs_physical = 1,
 143 };
 144
 145 static const struct intel_device_info intel_i865g_info = {
 146         .gen = 2,
 147         .has_overlay = 1, .overlay_needs_physical = 1,
 148 };
 149
 150 static const struct intel_device_info intel_i915g_info = {
 151         .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
 152         .has_overlay = 1, .overlay_needs_physical = 1,
 153 };
 154 static const struct intel_device_info intel_i915gm_info = {
 155         .gen = 3, .is_mobile = 1,
 156         .cursor_needs_physical = 1,
 157         .has_overlay = 1, .overlay_needs_physical = 1,
 158         .supports_tv = 1,
 159 };
 160 static const struct intel_device_info intel_i945g_info = {
 161         .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
 162         .has_overlay = 1, .overlay_needs_physical = 1,
 163 };
 164 static const struct intel_device_info intel_i945gm_info = {
 165         .gen = 3, .is_i945gm = 1, .is_mobile = 1,
 166         .has_hotplug = 1, .cursor_needs_physical = 1,
 167         .has_overlay = 1, .overlay_needs_physical = 1,
 168         .supports_tv = 1,
 169 };
 170
 171 static const struct intel_device_info intel_i965g_info = {
 172         .gen = 4, .is_broadwater = 1,
 173         .has_hotplug = 1,
 174         .has_overlay = 1,
 175 };
 176
 177 static const struct intel_device_info intel_i965gm_info = {
 178         .gen = 4, .is_crestline = 1,
 179         .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
 180         .has_overlay = 1,
 181         .supports_tv = 1,
 182 };
 183
 184 static const struct intel_device_info intel_g33_info = {
 185         .gen = 3, .is_g33 = 1,
 186         .need_gfx_hws = 1, .has_hotplug = 1,
 187         .has_overlay = 1,
 188 };
 189
 190 static const struct intel_device_info intel_g45_info = {
 191         .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
 192         .has_pipe_cxsr = 1, .has_hotplug = 1,
 193         .has_bsd_ring = 1,
 194 };
 195
 196 static const struct intel_device_info intel_gm45_info = {
 197         .gen = 4, .is_g4x = 1,
 198         .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
 199         .has_pipe_cxsr = 1, .has_hotplug = 1,
 200         .supports_tv = 1,
 201         .has_bsd_ring = 1,
 202 };
 203
 204 static const struct intel_device_info intel_pineview_info = {
 205         .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
 206         .need_gfx_hws = 1, .has_hotplug = 1,
 207         .has_overlay = 1,
 208 };
 209
 210 static const struct intel_device_info intel_ironlake_d_info = {
 211         .gen = 5,
 212         .need_gfx_hws = 1, .has_hotplug = 1,
 213         .has_bsd_ring = 1,
 214 };
 215
 216 static const struct intel_device_info intel_ironlake_m_info = {
 217         .gen = 5, .is_mobile = 1,
 218         .need_gfx_hws = 1, .has_hotplug = 1,
 219         .has_fbc = 1,
 220         .has_bsd_ring = 1,
 221 };
 222
 223 static const struct intel_device_info intel_sandybridge_d_info = {
 224         .gen = 6,
 225         .need_gfx_hws = 1, .has_hotplug = 1,
 226         .has_bsd_ring = 1,
 227         .has_blt_ring = 1,
 228         .has_llc = 1,
 229 };
 230
 231 static const struct intel_device_info intel_sandybridge_m_info = {
 232         .gen = 6, .is_mobile = 1,
 233         .need_gfx_hws = 1, .has_hotplug = 1,
 234         .has_fbc = 1,
 235         .has_bsd_ring = 1,
 236         .has_blt_ring = 1,
 237         .has_llc = 1,
 238 };
 239
 240 static const struct intel_device_info intel_ivybridge_d_info = {
 241         .is_ivybridge = 1, .gen = 7,
 242         .need_gfx_hws = 1, .has_hotplug = 1,
 243         .has_bsd_ring = 1,
 244         .has_blt_ring = 1,
 245         .has_llc = 1,
 246 };
 247
 248 static const struct intel_device_info intel_ivybridge_m_info = {
 249         .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
 250         .need_gfx_hws = 1, .has_hotplug = 1,
 251         .has_fbc = 0,   /* FBC is not enabled on Ivybridge mobile yet */
 252         .has_bsd_ring = 1,
 253         .has_blt_ring = 1,
 254         .has_llc = 1,
 255 };
 256
 257 static const struct pci_device_id pciidlist[] = {               /* aka */
 258         INTEL_VGA_DEVICE(0x3577, &intel_i830_info),             /* I830_M */
 259         INTEL_VGA_DEVICE(0x2562, &intel_845g_info),             /* 845_G */
 260         INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),             /* I855_GM */
 261         INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
 262         INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),            /* I865_G */
 263         INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),            /* I915_G */
 264         INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),            /* E7221_G */
 265         INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),           /* I915_GM */
 266         INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),            /* I945_G */
 267         INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),           /* I945_GM */
 268         INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),           /* I945_GME */
 269         INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),            /* I946_GZ */
 270         INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),            /* G35_G */
 271         INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),            /* I965_Q */
 272         INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),            /* I965_G */
 273         INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),              /* Q35_G */
 274         INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),              /* G33_G */
 275         INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),              /* Q33_G */
 276         INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),           /* I965_GM */
 277         INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),           /* I965_GME */
 278         INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),             /* GM45_G */
 279         INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),              /* IGD_E_G */
 280         INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),              /* Q45_G */
 281         INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),              /* G45_G */
 282         INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),              /* G41_G */
 283         INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),              /* B43_G */
 284         INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),              /* B43_G.1 */
 285         INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
 286         INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
 287         INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
 288         INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
 289         INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
 290         INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
 291         INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
 292         INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
 293         INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
 294         INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
 295         INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
 296         INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
 297         INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
 298         INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
 299         INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
 300         INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
 301         {0, 0, 0}
 302 };
 303
 304 #if defined(CONFIG_DRM_I915_KMS)
 305 MODULE_DEVICE_TABLE(pci, pciidlist);
 306 #endif
 307
 308 #define INTEL_PCH_DEVICE_ID_MASK        0xff00
 309 #define INTEL_PCH_IBX_DEVICE_ID_TYPE    0x3b00
 310 #define INTEL_PCH_CPT_DEVICE_ID_TYPE    0x1c00
 311 #define INTEL_PCH_PPT_DEVICE_ID_TYPE    0x1e00
 312
 313 void intel_detect_pch(struct drm_device *dev)
 314 {
 315         struct drm_i915_private *dev_priv = dev->dev_private;
 316         struct pci_dev *pch;
 317
 318         /*
 319          * The reason to probe ISA bridge instead of Dev31:Fun0 is to
 320          * make graphics device passthrough work easy for VMM, that only
 321          * need to expose ISA bridge to let driver know the real hardware
 322          * underneath. This is a requirement from virtualization team.
 323          */
 324         pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
 325         if (pch) {
 326                 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
 327                         int id;
 328                         id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
 329
 330                         if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
 331                                 dev_priv->pch_type = PCH_IBX;
 332                                 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
 333                         } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
 334                                 dev_priv->pch_type = PCH_CPT;
 335                                 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
 336                         } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
 337                                 /* PantherPoint is CPT compatible */
 338                                 dev_priv->pch_type = PCH_CPT;
 339                                 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
 340                         }
 341                 }
 342                 pci_dev_put(pch);
 343         }
 344 }
 345
 346 void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 347 {
 348         int count;
 349
 350         count = 0;
 351         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
 352                 udelay(10);
 353
 354         I915_WRITE_NOTRACE(FORCEWAKE, 1);
 355         POSTING_READ(FORCEWAKE);
 356
 357         count = 0;
 358         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
 359                 udelay(10);
 360 }
 361
 362 void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
 363 {
 364         int count;
 365
 366         count = 0;
 367         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
 368                 udelay(10);
 369
 370         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
 371         POSTING_READ(FORCEWAKE_MT);
 372
 373         count = 0;
 374         while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
 375                 udelay(10);
 376 }
 377
 378 /*
 379  * Generally this is called implicitly by the register read function. However,
 380  * if some sequence requires the GT to not power down then this function should
 381  * be called at the beginning of the sequence followed by a call to
 382  * gen6_gt_force_wake_put() at the end of the sequence.
 383  */
 384 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
 385 {
 386         unsigned long irqflags;
 387
 388         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 389         if (dev_priv->forcewake_count++ == 0)
 390                 dev_priv->display.force_wake_get(dev_priv);
 391         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 392 }
 393
 394 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
 395 {
 396         u32 gtfifodbg;
 397         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
 398         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
 399              "MMIO read or write has been dropped %x\n", gtfifodbg))
 400                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
 401 }
 402
 403 void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 404 {
 405         I915_WRITE_NOTRACE(FORCEWAKE, 0);
 406         /* The below doubles as a POSTING_READ */
 407         gen6_gt_check_fifodbg(dev_priv);
 408 }
 409
 410 void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
 411 {
 412         I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
 413         /* The below doubles as a POSTING_READ */
 414         gen6_gt_check_fifodbg(dev_priv);
 415 }
 416
 417 /*
 418  * see gen6_gt_force_wake_get()
 419  */
 420 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
 421 {
 422         unsigned long irqflags;
 423
 424         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 425         if (--dev_priv->forcewake_count == 0)
 426                 dev_priv->display.force_wake_put(dev_priv);
 427         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 428 }
 429
 430 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 431 {
 432         int ret = 0;
 433
 434         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
 435                 int loop = 500;
 436                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 437                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
 438                         udelay(10);
 439                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 440                 }
 441                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
 442                         ++ret;
 443                 dev_priv->gt_fifo_count = fifo;
 444         }
 445         dev_priv->gt_fifo_count--;
 446
 447         return ret;
 448 }
 449
 450 static int i915_drm_freeze(struct drm_device *dev)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453
 454         drm_kms_helper_poll_disable(dev);
 455
 456         pci_save_state(dev->pdev);
 457
 458         /* If KMS is active, we do the leavevt stuff here */
 459         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 460                 int error = i915_gem_idle(dev);
 461                 if (error) {
 462                         dev_err(&dev->pdev->dev,
 463                                 "GEM idle failed, resume might fail\n");
 464                         return error;
 465                 }
 466                 drm_irq_uninstall(dev);
 467         }
 468
 469         i915_save_state(dev);
 470
 471         intel_opregion_fini(dev);
 472
 473         /* Modeset on resume, not lid events */
 474         dev_priv->modeset_on_lid = 0;
 475
 476         return 0;
 477 }
 478
 479 int i915_suspend(struct drm_device *dev, pm_message_t state)
 480 {
 481         int error;
 482
 483         if (!dev || !dev->dev_private) {
 484                 DRM_ERROR("dev: %p\n", dev);
 485                 DRM_ERROR("DRM not initialized, aborting suspend.\n");
 486                 return -ENODEV;
 487         }
 488
 489         if (state.event == PM_EVENT_PRETHAW)
 490                 return 0;
 491
 492
 493         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 494                 return 0;
 495
 496         error = i915_drm_freeze(dev);
 497         if (error)
 498                 return error;
 499
 500         if (state.event == PM_EVENT_SUSPEND) {
 501                 /* Shut down the device */
 502                 pci_disable_device(dev->pdev);
 503                 pci_set_power_state(dev->pdev, PCI_D3hot);
 504         }
 505
 506         return 0;
 507 }
 508
 509 static int i915_drm_thaw(struct drm_device *dev)
 510 {
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512         int error = 0;
 513
 514         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 515                 mutex_lock(&dev->struct_mutex);
 516                 i915_gem_restore_gtt_mappings(dev);
 517                 mutex_unlock(&dev->struct_mutex);
 518         }
 519
 520         i915_restore_state(dev);
 521         intel_opregion_setup(dev);
 522
 523         /* KMS EnterVT equivalent */
 524         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 525                 mutex_lock(&dev->struct_mutex);
 526                 dev_priv->mm.suspended = 0;
 527
 528                 error = i915_gem_init_hw(dev);
 529                 mutex_unlock(&dev->struct_mutex);
 530
 531                 if (HAS_PCH_SPLIT(dev))
 532                         ironlake_init_pch_refclk(dev);
 533
 534                 drm_mode_config_reset(dev);
 535                 drm_irq_install(dev);
 536
 537                 /* Resume the modeset for every activated CRTC */
 538                 drm_helper_resume_force_mode(dev);
 539
 540                 if (IS_IRONLAKE_M(dev))
 541                         ironlake_enable_rc6(dev);
 542         }
 543
 544         intel_opregion_init(dev);
 545
 546         dev_priv->modeset_on_lid = 0;
 547
 548         return error;
 549 }
 550
 551 int i915_resume(struct drm_device *dev)
 552 {
 553         int ret;
 554
 555         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 556                 return 0;
 557
 558         if (pci_enable_device(dev->pdev))
 559                 return -EIO;
 560
 561         pci_set_master(dev->pdev);
 562
 563         ret = i915_drm_thaw(dev);
 564         if (ret)
 565                 return ret;
 566
 567         drm_kms_helper_poll_enable(dev);
 568         return 0;
 569 }
 570
 571 static int i8xx_do_reset(struct drm_device *dev, u8 flags)
 572 {
 573         struct drm_i915_private *dev_priv = dev->dev_private;
 574
 575         if (IS_I85X(dev))
 576                 return -ENODEV;
 577
 578         I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
 579         POSTING_READ(D_STATE);
 580
 581         if (IS_I830(dev) || IS_845G(dev)) {
 582                 I915_WRITE(DEBUG_RESET_I830,
 583                            DEBUG_RESET_DISPLAY |
 584                            DEBUG_RESET_RENDER |
 585                            DEBUG_RESET_FULL);
 586                 POSTING_READ(DEBUG_RESET_I830);
 587                 msleep(1);
 588
 589                 I915_WRITE(DEBUG_RESET_I830, 0);
 590                 POSTING_READ(DEBUG_RESET_I830);
 591         }
 592
 593         msleep(1);
 594
 595         I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
 596         POSTING_READ(D_STATE);
 597
 598         return 0;
 599 }
 600
 601 static int i965_reset_complete(struct drm_device *dev)
 602 {
 603         u8 gdrst;
 604         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 605         return gdrst & 0x1;
 606 }
 607
 608 static int i965_do_reset(struct drm_device *dev, u8 flags)
 609 {
 610         u8 gdrst;
 611
 612         /*
 613          * Set the domains we want to reset (GRDOM/bits 2 and 3) as
 614          * well as the reset bit (GR/bit 0).  Setting the GR bit
 615          * triggers the reset; when done, the hardware will clear it.
 616          */
 617         pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
 618         pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1);
 619
 620         return wait_for(i965_reset_complete(dev), 500);
 621 }
 622
 623 static int ironlake_do_reset(struct drm_device *dev, u8 flags)
 624 {
 625         struct drm_i915_private *dev_priv = dev->dev_private;
 626         u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
 627         I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
 628         return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
 629 }
 630
 631 static int gen6_do_reset(struct drm_device *dev, u8 flags)
 632 {
 633         struct drm_i915_private *dev_priv = dev->dev_private;
 634         int     ret;
 635         unsigned long irqflags;
 636
 637         /* Hold gt_lock across reset to prevent any register access
 638          * with forcewake not set correctly
 639          */
 640         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
 641
 642         /* Reset the chip */
 643
 644         /* GEN6_GDRST is not in the gt power well, no need to check
 645          * for fifo space for the write or forcewake the chip for
 646          * the read
 647          */
 648         I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
 649
 650         /* Spin waiting for the device to ack the reset request */
 651         ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
 652
 653         /* If reset with a user forcewake, try to restore, otherwise turn it off */
 654         if (dev_priv->forcewake_count)
 655                 dev_priv->display.force_wake_get(dev_priv);
 656         else
 657                 dev_priv->display.force_wake_put(dev_priv);
 658
 659         /* Restore fifo count */
 660         dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 661
 662         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
 663         return ret;
 664 }
 665
 666 /**
 667  * i915_reset - reset chip after a hang
 668  * @dev: drm device to reset
 669  * @flags: reset domains
 670  *
 671  * Reset the chip.  Useful if a hang is detected. Returns zero on successful
 672  * reset or otherwise an error code.
 673  *
 674  * Procedure is fairly simple:
 675  *   - reset the chip using the reset reg
 676  *   - re-init context state
 677  *   - re-init hardware status page
 678  *   - re-init ring buffer
 679  *   - re-init interrupt state
 680  *   - re-init display
 681  */
 682 int i915_reset(struct drm_device *dev, u8 flags)
 683 {
 684         drm_i915_private_t *dev_priv = dev->dev_private;
 685         /*
 686          * We really should only reset the display subsystem if we actually
 687          * need to
 688          */
 689         bool need_display = true;
 690         int ret;
 691
 692         if (!i915_try_reset)
 693                 return 0;
 694
 695         if (!mutex_trylock(&dev->struct_mutex))
 696                 return -EBUSY;
 697
 698         i915_gem_reset(dev);
 699
 700         ret = -ENODEV;
 701         if (get_seconds() - dev_priv->last_gpu_reset < 5) {
 702                 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
 703         } else switch (INTEL_INFO(dev)->gen) {
 704         case 7:
 705         case 6:
 706                 ret = gen6_do_reset(dev, flags);
 707                 break;
 708         case 5:
 709                 ret = ironlake_do_reset(dev, flags);
 710                 break;
 711         case 4:
 712                 ret = i965_do_reset(dev, flags);
 713                 break;
 714         case 2:
 715                 ret = i8xx_do_reset(dev, flags);
 716                 break;
 717         }
 718         dev_priv->last_gpu_reset = get_seconds();
 719         if (ret) {
 720                 DRM_ERROR("Failed to reset chip.\n");
 721                 mutex_unlock(&dev->struct_mutex);
 722                 return ret;
 723         }
 724
 725         /* Ok, now get things going again... */
 726
 727         /*
 728          * Everything depends on having the GTT running, so we need to start
 729          * there.  Fortunately we don't need to do this unless we reset the
 730          * chip at a PCI level.
 731          *
 732          * Next we need to restore the context, but we don't use those
 733          * yet either...
 734          *
 735          * Ring buffer needs to be re-initialized in the KMS case, or if X
 736          * was running at the time of the reset (i.e. we weren't VT
 737          * switched away).
 738          */
 739         if (drm_core_check_feature(dev, DRIVER_MODESET) ||
 740                         !dev_priv->mm.suspended) {
 741                 dev_priv->mm.suspended = 0;
 742
 743                 i915_gem_init_swizzling(dev);
 744
 745                 dev_priv->ring[RCS].init(&dev_priv->ring[RCS]);
 746                 if (HAS_BSD(dev))
 747                     dev_priv->ring[VCS].init(&dev_priv->ring[VCS]);
 748                 if (HAS_BLT(dev))
 749                     dev_priv->ring[BCS].init(&dev_priv->ring[BCS]);
 750
 751                 i915_gem_init_ppgtt(dev);
 752
 753                 mutex_unlock(&dev->struct_mutex);
 754                 drm_irq_uninstall(dev);
 755                 drm_mode_config_reset(dev);
 756                 drm_irq_install(dev);
 757                 mutex_lock(&dev->struct_mutex);
 758         }
 759
 760         mutex_unlock(&dev->struct_mutex);
 761
 762         /*
 763          * Perform a full modeset as on later generations, e.g. Ironlake, we may
 764          * need to retrain the display link and cannot just restore the register
 765          * values.
 766          */
 767         if (need_display) {
 768                 mutex_lock(&dev->mode_config.mutex);
 769                 drm_helper_resume_force_mode(dev);
 770                 mutex_unlock(&dev->mode_config.mutex);
 771         }
 772
 773         return 0;
 774 }
 775
 776
 777 static int __devinit
 778 i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 779 {
 780         /* Only bind to function 0 of the device. Early generations
 781          * used function 1 as a placeholder for multi-head. This causes
 782          * us confusion instead, especially on the systems where both
 783          * functions have the same PCI-ID!
 784          */
 785         if (PCI_FUNC(pdev->devfn))
 786                 return -ENODEV;
 787
 788         return drm_get_pci_dev(pdev, ent, &driver);
 789 }
 790
 791 static void
 792 i915_pci_remove(struct pci_dev *pdev)
 793 {
 794         struct drm_device *dev = pci_get_drvdata(pdev);
 795
 796         drm_put_dev(dev);
 797 }
 798
 799 static int i915_pm_suspend(struct device *dev)
 800 {
 801         struct pci_dev *pdev = to_pci_dev(dev);
 802         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 803         int error;
 804
 805         if (!drm_dev || !drm_dev->dev_private) {
 806                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 807                 return -ENODEV;
 808         }
 809
 810         if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
 811                 return 0;
 812
 813         error = i915_drm_freeze(drm_dev);
 814         if (error)
 815                 return error;
 816
 817         pci_disable_device(pdev);
 818         pci_set_power_state(pdev, PCI_D3hot);
 819
 820         return 0;
 821 }
 822
 823 static int i915_pm_resume(struct device *dev)
 824 {
 825         struct pci_dev *pdev = to_pci_dev(dev);
 826         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 827
 828         return i915_resume(drm_dev);
 829 }
 830
 831 static int i915_pm_freeze(struct device *dev)
 832 {
 833         struct pci_dev *pdev = to_pci_dev(dev);
 834         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 835
 836         if (!drm_dev || !drm_dev->dev_private) {
 837                 dev_err(dev, "DRM not initialized, aborting suspend.\n");
 838                 return -ENODEV;
 839         }
 840
 841         return i915_drm_freeze(drm_dev);
 842 }
 843
 844 static int i915_pm_thaw(struct device *dev)
 845 {
 846         struct pci_dev *pdev = to_pci_dev(dev);
 847         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 848
 849         return i915_drm_thaw(drm_dev);
 850 }
 851
 852 static int i915_pm_poweroff(struct device *dev)
 853 {
 854         struct pci_dev *pdev = to_pci_dev(dev);
 855         struct drm_device *drm_dev = pci_get_drvdata(pdev);
 856
 857         return i915_drm_freeze(drm_dev);
 858 }
 859
 860 static const struct dev_pm_ops i915_pm_ops = {
 861         .suspend = i915_pm_suspend,
 862         .resume = i915_pm_resume,
 863         .freeze = i915_pm_freeze,
 864         .thaw = i915_pm_thaw,
 865         .poweroff = i915_pm_poweroff,
 866         .restore = i915_pm_resume,
 867 };
 868
 869 static struct vm_operations_struct i915_gem_vm_ops = {
 870         .fault = i915_gem_fault,
 871         .open = drm_gem_vm_open,
 872         .close = drm_gem_vm_close,
 873 };
 874
 875 static const struct file_operations i915_driver_fops = {
 876         .owner = THIS_MODULE,
 877         .open = drm_open,
 878         .release = drm_release,
 879         .unlocked_ioctl = drm_ioctl,
 880         .mmap = drm_gem_mmap,
 881         .poll = drm_poll,
 882         .fasync = drm_fasync,
 883         .read = drm_read,
 884 #ifdef CONFIG_COMPAT
 885         .compat_ioctl = i915_compat_ioctl,
 886 #endif
 887         .llseek = noop_llseek,
 888 };
 889
 890 static struct drm_driver driver = {
 891         /* Don't use MTRRs here; the Xserver or userspace app should
 892          * deal with them for Intel hardware.
 893          */
 894         .driver_features =
 895             DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
 896             DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM,
 897         .load = i915_driver_load,
 898         .unload = i915_driver_unload,
 899         .open = i915_driver_open,
 900         .lastclose = i915_driver_lastclose,
 901         .preclose = i915_driver_preclose,
 902         .postclose = i915_driver_postclose,
 903
 904         /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
 905         .suspend = i915_suspend,
 906         .resume = i915_resume,
 907
 908         .device_is_agp = i915_driver_device_is_agp,
 909         .reclaim_buffers = drm_core_reclaim_buffers,
 910         .master_create = i915_master_create,
 911         .master_destroy = i915_master_destroy,
 912 #if defined(CONFIG_DEBUG_FS)
 913         .debugfs_init = i915_debugfs_init,
 914         .debugfs_cleanup = i915_debugfs_cleanup,
 915 #endif
 916         .gem_init_object = i915_gem_init_object,
 917         .gem_free_object = i915_gem_free_object,
 918         .gem_vm_ops = &i915_gem_vm_ops,
 919         .dumb_create = i915_gem_dumb_create,
 920         .dumb_map_offset = i915_gem_mmap_gtt,
 921         .dumb_destroy = i915_gem_dumb_destroy,
 922         .ioctls = i915_ioctls,
 923         .fops = &i915_driver_fops,
 924         .name = DRIVER_NAME,
 925         .desc = DRIVER_DESC,
 926         .date = DRIVER_DATE,
 927         .major = DRIVER_MAJOR,
 928         .minor = DRIVER_MINOR,
 929         .patchlevel = DRIVER_PATCHLEVEL,
 930 };
 931
 932 static struct pci_driver i915_pci_driver = {
 933         .name = DRIVER_NAME,
 934         .id_table = pciidlist,
 935         .probe = i915_pci_probe,
 936         .remove = i915_pci_remove,
 937         .driver.pm = &i915_pm_ops,
 938 };
 939
 940 static int __init i915_init(void)
 941 {
 942         if (!intel_agp_enabled) {
 943                 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
 944                 return -ENODEV;
 945         }
 946
 947         driver.num_ioctls = i915_max_ioctl;
 948
 949         /*
 950          * If CONFIG_DRM_I915_KMS is set, default to KMS unless
 951          * explicitly disabled with the module pararmeter.
 952          *
 953          * Otherwise, just follow the parameter (defaulting to off).
 954          *
 955          * Allow optional vga_text_mode_force boot option to override
 956          * the default behavior.
 957          */
 958 #if defined(CONFIG_DRM_I915_KMS)
 959         if (i915_modeset != 0)
 960                 driver.driver_features |= DRIVER_MODESET;
 961 #endif
 962         if (i915_modeset == 1)
 963                 driver.driver_features |= DRIVER_MODESET;
 964
 965 #ifdef CONFIG_VGA_CONSOLE
 966         if (vgacon_text_force() && i915_modeset == -1)
 967                 driver.driver_features &= ~DRIVER_MODESET;
 968 #endif
 969
 970         if (!(driver.driver_features & DRIVER_MODESET))
 971                 driver.get_vblank_timestamp = NULL;
 972
 973         return drm_pci_init(&driver, &i915_pci_driver);
 974 }
 975
 976 static void __exit i915_exit(void)
 977 {
 978         drm_pci_exit(&driver, &i915_pci_driver);
 979 }
 980
 981 module_init(i915_init);
 982 module_exit(i915_exit);
 983
 984 MODULE_AUTHOR(DRIVER_AUTHOR);
 985 MODULE_DESCRIPTION(DRIVER_DESC);
 986 MODULE_LICENSE("GPL and additional rights");
 987
 988 #define __i915_read(x, y) \
 989 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
 990         u##x val = 0; \
 991         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
 992                 unsigned long irqflags; \
 993                 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
 994                 if (dev_priv->forcewake_count == 0) \
 995                         dev_priv->display.force_wake_get(dev_priv); \
 996                 val = read##y(dev_priv->regs + reg); \
 997                 if (dev_priv->forcewake_count == 0) \
 998                         dev_priv->display.force_wake_put(dev_priv); \
 999                 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1000         } else { \
1001                 val = read##y(dev_priv->regs + reg); \
1002         } \
1003         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1004         return val; \
1005 }
1006
1007 __i915_read(8, b)
1008 __i915_read(16, w)
1009 __i915_read(32, l)
1010 __i915_read(64, q)
1011 #undef __i915_read
1012
1013 #define __i915_write(x, y) \
1014 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1015         u32 __fifo_ret = 0; \
1016         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1017         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1018                 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1019         } \
1020         write##y(val, dev_priv->regs + reg); \
1021         if (unlikely(__fifo_ret)) { \
1022                 gen6_gt_check_fifodbg(dev_priv); \
1023         } \
1024 }
1025 __i915_write(8, b)
1026 __i915_write(16, w)
1027 __i915_write(32, l)
1028 __i915_write(64, q)
1029 #undef __i915_write