1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include <drm/drm_crtc_helper.h>
44 static struct drm_driver driver;
46 #define GEN_DEFAULT_PIPEOFFSETS \
47 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
48 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
49 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
50 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
51 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
53 #define GEN_CHV_PIPEOFFSETS \
54 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
55 CHV_PIPE_C_OFFSET }, \
56 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
57 CHV_TRANSCODER_C_OFFSET, }, \
58 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
59 CHV_PALETTE_C_OFFSET }
61 #define CURSOR_OFFSETS \
62 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
64 #define IVB_CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
70 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
72 static const struct intel_device_info intel_i830_info = {
73 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
74 .has_overlay = 1, .overlay_needs_physical = 1,
75 .ring_mask = RENDER_RING,
76 GEN_DEFAULT_PIPEOFFSETS,
80 static const struct intel_device_info intel_845g_info = {
81 .gen = 2, .num_pipes = 1,
82 .has_overlay = 1, .overlay_needs_physical = 1,
83 .ring_mask = RENDER_RING,
84 GEN_DEFAULT_PIPEOFFSETS,
88 static const struct intel_device_info intel_i85x_info = {
89 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
90 .cursor_needs_physical = 1,
91 .has_overlay = 1, .overlay_needs_physical = 1,
93 .ring_mask = RENDER_RING,
94 GEN_DEFAULT_PIPEOFFSETS,
98 static const struct intel_device_info intel_i865g_info = {
99 .gen = 2, .num_pipes = 1,
100 .has_overlay = 1, .overlay_needs_physical = 1,
101 .ring_mask = RENDER_RING,
102 GEN_DEFAULT_PIPEOFFSETS,
106 static const struct intel_device_info intel_i915g_info = {
107 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
108 .has_overlay = 1, .overlay_needs_physical = 1,
109 .ring_mask = RENDER_RING,
110 GEN_DEFAULT_PIPEOFFSETS,
113 static const struct intel_device_info intel_i915gm_info = {
114 .gen = 3, .is_mobile = 1, .num_pipes = 2,
115 .cursor_needs_physical = 1,
116 .has_overlay = 1, .overlay_needs_physical = 1,
119 .ring_mask = RENDER_RING,
120 GEN_DEFAULT_PIPEOFFSETS,
123 static const struct intel_device_info intel_i945g_info = {
124 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
125 .has_overlay = 1, .overlay_needs_physical = 1,
126 .ring_mask = RENDER_RING,
127 GEN_DEFAULT_PIPEOFFSETS,
130 static const struct intel_device_info intel_i945gm_info = {
131 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
132 .has_hotplug = 1, .cursor_needs_physical = 1,
133 .has_overlay = 1, .overlay_needs_physical = 1,
136 .ring_mask = RENDER_RING,
137 GEN_DEFAULT_PIPEOFFSETS,
141 static const struct intel_device_info intel_i965g_info = {
142 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
145 .ring_mask = RENDER_RING,
146 GEN_DEFAULT_PIPEOFFSETS,
150 static const struct intel_device_info intel_i965gm_info = {
151 .gen = 4, .is_crestline = 1, .num_pipes = 2,
152 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
155 .ring_mask = RENDER_RING,
156 GEN_DEFAULT_PIPEOFFSETS,
160 static const struct intel_device_info intel_g33_info = {
161 .gen = 3, .is_g33 = 1, .num_pipes = 2,
162 .need_gfx_hws = 1, .has_hotplug = 1,
164 .ring_mask = RENDER_RING,
165 GEN_DEFAULT_PIPEOFFSETS,
169 static const struct intel_device_info intel_g45_info = {
170 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
171 .has_pipe_cxsr = 1, .has_hotplug = 1,
172 .ring_mask = RENDER_RING | BSD_RING,
173 GEN_DEFAULT_PIPEOFFSETS,
177 static const struct intel_device_info intel_gm45_info = {
178 .gen = 4, .is_g4x = 1, .num_pipes = 2,
179 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
180 .has_pipe_cxsr = 1, .has_hotplug = 1,
182 .ring_mask = RENDER_RING | BSD_RING,
183 GEN_DEFAULT_PIPEOFFSETS,
187 static const struct intel_device_info intel_pineview_info = {
188 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
189 .need_gfx_hws = 1, .has_hotplug = 1,
191 GEN_DEFAULT_PIPEOFFSETS,
195 static const struct intel_device_info intel_ironlake_d_info = {
196 .gen = 5, .num_pipes = 2,
197 .need_gfx_hws = 1, .has_hotplug = 1,
198 .ring_mask = RENDER_RING | BSD_RING,
199 GEN_DEFAULT_PIPEOFFSETS,
203 static const struct intel_device_info intel_ironlake_m_info = {
204 .gen = 5, .is_mobile = 1, .num_pipes = 2,
205 .need_gfx_hws = 1, .has_hotplug = 1,
207 .ring_mask = RENDER_RING | BSD_RING,
208 GEN_DEFAULT_PIPEOFFSETS,
212 static const struct intel_device_info intel_sandybridge_d_info = {
213 .gen = 6, .num_pipes = 2,
214 .need_gfx_hws = 1, .has_hotplug = 1,
216 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
218 GEN_DEFAULT_PIPEOFFSETS,
222 static const struct intel_device_info intel_sandybridge_m_info = {
223 .gen = 6, .is_mobile = 1, .num_pipes = 2,
224 .need_gfx_hws = 1, .has_hotplug = 1,
226 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
228 GEN_DEFAULT_PIPEOFFSETS,
232 #define GEN7_FEATURES \
233 .gen = 7, .num_pipes = 3, \
234 .need_gfx_hws = 1, .has_hotplug = 1, \
236 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
238 GEN_DEFAULT_PIPEOFFSETS, \
241 static const struct intel_device_info intel_ivybridge_d_info = {
246 static const struct intel_device_info intel_ivybridge_m_info = {
252 static const struct intel_device_info intel_ivybridge_q_info = {
255 .num_pipes = 0, /* legal, last one wins */
258 #define VLV_FEATURES \
259 .gen = 7, .num_pipes = 2, \
260 .need_gfx_hws = 1, .has_hotplug = 1, \
261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
262 .display_mmio_offset = VLV_DISPLAY_BASE, \
263 GEN_DEFAULT_PIPEOFFSETS, \
266 static const struct intel_device_info intel_valleyview_m_info = {
272 static const struct intel_device_info intel_valleyview_d_info = {
277 #define HSW_FEATURES \
279 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
283 static const struct intel_device_info intel_haswell_d_info = {
288 static const struct intel_device_info intel_haswell_m_info = {
294 #define BDW_FEATURES \
298 static const struct intel_device_info intel_broadwell_d_info = {
304 static const struct intel_device_info intel_broadwell_m_info = {
306 .gen = 8, .is_mobile = 1,
310 static const struct intel_device_info intel_broadwell_gt3d_info = {
314 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
317 static const struct intel_device_info intel_broadwell_gt3m_info = {
319 .gen = 8, .is_mobile = 1,
321 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
324 static const struct intel_device_info intel_cherryview_info = {
325 .gen = 8, .num_pipes = 3,
326 .need_gfx_hws = 1, .has_hotplug = 1,
327 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
329 .display_mmio_offset = VLV_DISPLAY_BASE,
335 static const struct intel_device_info intel_skylake_info = {
341 static const struct intel_device_info intel_skylake_gt3_info = {
345 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
348 static const struct intel_device_info intel_broxton_info = {
352 .need_gfx_hws = 1, .has_hotplug = 1,
353 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
358 GEN_DEFAULT_PIPEOFFSETS,
363 static const struct intel_device_info intel_kabylake_info = {
369 static const struct intel_device_info intel_kabylake_gt3_info = {
373 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
377 * Make sure any device matches here are from most specific to most
378 * general. For example, since the Quanta match is based on the subsystem
379 * and subvendor IDs, we need it to come before the more general IVB
380 * PCI ID matches, otherwise we'll use the wrong info struct above.
382 static const struct pci_device_id pciidlist[] = {
383 INTEL_I830_IDS(&intel_i830_info),
384 INTEL_I845G_IDS(&intel_845g_info),
385 INTEL_I85X_IDS(&intel_i85x_info),
386 INTEL_I865G_IDS(&intel_i865g_info),
387 INTEL_I915G_IDS(&intel_i915g_info),
388 INTEL_I915GM_IDS(&intel_i915gm_info),
389 INTEL_I945G_IDS(&intel_i945g_info),
390 INTEL_I945GM_IDS(&intel_i945gm_info),
391 INTEL_I965G_IDS(&intel_i965g_info),
392 INTEL_G33_IDS(&intel_g33_info),
393 INTEL_I965GM_IDS(&intel_i965gm_info),
394 INTEL_GM45_IDS(&intel_gm45_info),
395 INTEL_G45_IDS(&intel_g45_info),
396 INTEL_PINEVIEW_IDS(&intel_pineview_info),
397 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
398 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
399 INTEL_SNB_D_IDS(&intel_sandybridge_d_info),
400 INTEL_SNB_M_IDS(&intel_sandybridge_m_info),
401 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
402 INTEL_IVB_M_IDS(&intel_ivybridge_m_info),
403 INTEL_IVB_D_IDS(&intel_ivybridge_d_info),
404 INTEL_HSW_D_IDS(&intel_haswell_d_info),
405 INTEL_HSW_M_IDS(&intel_haswell_m_info),
406 INTEL_VLV_M_IDS(&intel_valleyview_m_info),
407 INTEL_VLV_D_IDS(&intel_valleyview_d_info),
408 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info),
409 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info),
410 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info),
411 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info),
412 INTEL_CHV_IDS(&intel_cherryview_info),
413 INTEL_SKL_GT1_IDS(&intel_skylake_info),
414 INTEL_SKL_GT2_IDS(&intel_skylake_info),
415 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
416 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info),
417 INTEL_BXT_IDS(&intel_broxton_info),
418 INTEL_KBL_GT1_IDS(&intel_kabylake_info),
419 INTEL_KBL_GT2_IDS(&intel_kabylake_info),
420 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
421 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
425 MODULE_DEVICE_TABLE(pci, pciidlist);
427 static enum intel_pch intel_virt_detect_pch(struct drm_device *dev)
429 enum intel_pch ret = PCH_NOP;
432 * In a virtualized passthrough environment we can be in a
433 * setup where the ISA bridge is not able to be passed through.
434 * In this case, a south bridge can be emulated and we have to
435 * make an educated guess as to which PCH is really there.
440 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
441 } else if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
443 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
444 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
446 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
447 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
449 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
455 void intel_detect_pch(struct drm_device *dev)
457 struct drm_i915_private *dev_priv = dev->dev_private;
458 struct pci_dev *pch = NULL;
460 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
461 * (which really amounts to a PCH but no South Display).
463 if (INTEL_INFO(dev)->num_pipes == 0) {
464 dev_priv->pch_type = PCH_NOP;
469 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
470 * make graphics device passthrough work easy for VMM, that only
471 * need to expose ISA bridge to let driver know the real hardware
472 * underneath. This is a requirement from virtualization team.
474 * In some virtualized environments (e.g. XEN), there is irrelevant
475 * ISA bridge in the system. To work reliably, we should scan trhough
476 * all the ISA bridge devices and check for the first match, instead
477 * of only checking the first one.
479 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
480 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
481 unsigned short id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
482 dev_priv->pch_id = id;
484 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
485 dev_priv->pch_type = PCH_IBX;
486 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
487 WARN_ON(!IS_GEN5(dev));
488 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
489 dev_priv->pch_type = PCH_CPT;
490 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
491 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
492 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
493 /* PantherPoint is CPT compatible */
494 dev_priv->pch_type = PCH_CPT;
495 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
496 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
497 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
498 dev_priv->pch_type = PCH_LPT;
499 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
500 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
501 WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev));
502 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
503 dev_priv->pch_type = PCH_LPT;
504 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
505 WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev));
506 WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev));
507 } else if (id == INTEL_PCH_SPT_DEVICE_ID_TYPE) {
508 dev_priv->pch_type = PCH_SPT;
509 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
510 WARN_ON(!IS_SKYLAKE(dev) &&
512 } else if (id == INTEL_PCH_SPT_LP_DEVICE_ID_TYPE) {
513 dev_priv->pch_type = PCH_SPT;
514 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
515 WARN_ON(!IS_SKYLAKE(dev) &&
517 } else if ((id == INTEL_PCH_P2X_DEVICE_ID_TYPE) ||
518 (id == INTEL_PCH_P3X_DEVICE_ID_TYPE) ||
519 ((id == INTEL_PCH_QEMU_DEVICE_ID_TYPE) &&
520 pch->subsystem_vendor == 0x1af4 &&
521 pch->subsystem_device == 0x1100)) {
522 dev_priv->pch_type = intel_virt_detect_pch(dev);
530 DRM_DEBUG_KMS("No PCH found.\n");
535 bool i915_semaphore_is_enabled(struct drm_i915_private *dev_priv)
537 if (INTEL_GEN(dev_priv) < 6)
540 if (i915.semaphores >= 0)
541 return i915.semaphores;
543 /* TODO: make semaphores and Execlists play nicely together */
544 if (i915.enable_execlists)
547 #ifdef CONFIG_INTEL_IOMMU
548 /* Enable semaphores on SNB when IO remapping is off */
549 if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped)
556 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
558 struct drm_device *dev = dev_priv->dev;
559 struct intel_encoder *encoder;
561 drm_modeset_lock_all(dev);
562 for_each_intel_encoder(dev, encoder)
563 if (encoder->suspend)
564 encoder->suspend(encoder);
565 drm_modeset_unlock_all(dev);
568 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
570 static int vlv_suspend_complete(struct drm_i915_private *dev_priv);
572 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
574 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
575 if (acpi_target_system_state() < ACPI_STATE_S3)
581 static int i915_drm_suspend(struct drm_device *dev)
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 pci_power_t opregion_target_state;
587 /* ignore lid events during suspend */
588 mutex_lock(&dev_priv->modeset_restore_lock);
589 dev_priv->modeset_restore = MODESET_SUSPENDED;
590 mutex_unlock(&dev_priv->modeset_restore_lock);
592 disable_rpm_wakeref_asserts(dev_priv);
594 /* We do a lot of poking in a lot of registers, make sure they work
596 intel_display_set_init_power(dev_priv, true);
598 drm_kms_helper_poll_disable(dev);
600 pci_save_state(dev->pdev);
602 error = i915_gem_suspend(dev);
604 dev_err(&dev->pdev->dev,
605 "GEM idle failed, resume might fail\n");
609 intel_guc_suspend(dev);
611 intel_suspend_gt_powersave(dev_priv);
613 intel_display_suspend(dev);
615 intel_dp_mst_suspend(dev);
617 intel_runtime_pm_disable_interrupts(dev_priv);
618 intel_hpd_cancel_work(dev_priv);
620 intel_suspend_encoders(dev_priv);
622 intel_suspend_hw(dev);
624 i915_gem_suspend_gtt_mappings(dev);
626 i915_save_state(dev);
628 opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
629 intel_opregion_notify_adapter(dev, opregion_target_state);
631 intel_uncore_forcewake_reset(dev_priv, false);
632 intel_opregion_fini(dev);
634 intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
636 dev_priv->suspend_count++;
638 intel_display_set_init_power(dev_priv, false);
640 intel_csr_ucode_suspend(dev_priv);
643 enable_rpm_wakeref_asserts(dev_priv);
648 static int i915_drm_suspend_late(struct drm_device *drm_dev, bool hibernation)
650 struct drm_i915_private *dev_priv = drm_dev->dev_private;
654 disable_rpm_wakeref_asserts(dev_priv);
656 fw_csr = !IS_BROXTON(dev_priv) &&
657 suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
659 * In case of firmware assisted context save/restore don't manually
660 * deinit the power domains. This also means the CSR/DMC firmware will
661 * stay active, it will power down any HW resources as required and
662 * also enable deeper system power states that would be blocked if the
663 * firmware was inactive.
666 intel_power_domains_suspend(dev_priv);
669 if (IS_BROXTON(dev_priv))
670 bxt_enable_dc9(dev_priv);
671 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
672 hsw_enable_pc8(dev_priv);
673 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
674 ret = vlv_suspend_complete(dev_priv);
677 DRM_ERROR("Suspend complete failed: %d\n", ret);
679 intel_power_domains_init_hw(dev_priv, true);
684 pci_disable_device(drm_dev->pdev);
686 * During hibernation on some platforms the BIOS may try to access
687 * the device even though it's already in D3 and hang the machine. So
688 * leave the device in D0 on those platforms and hope the BIOS will
689 * power down the device properly. The issue was seen on multiple old
690 * GENs with different BIOS vendors, so having an explicit blacklist
691 * is inpractical; apply the workaround on everything pre GEN6. The
692 * platforms where the issue was seen:
693 * Lenovo Thinkpad X301, X61s, X60, T60, X41
697 if (!(hibernation && INTEL_INFO(dev_priv)->gen < 6))
698 pci_set_power_state(drm_dev->pdev, PCI_D3hot);
700 dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
703 enable_rpm_wakeref_asserts(dev_priv);
708 int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state)
712 if (!dev || !dev->dev_private) {
713 DRM_ERROR("dev: %p\n", dev);
714 DRM_ERROR("DRM not initialized, aborting suspend.\n");
718 if (WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND &&
719 state.event != PM_EVENT_FREEZE))
722 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
725 error = i915_drm_suspend(dev);
729 return i915_drm_suspend_late(dev, false);
732 static int i915_drm_resume(struct drm_device *dev)
734 struct drm_i915_private *dev_priv = dev->dev_private;
737 disable_rpm_wakeref_asserts(dev_priv);
739 ret = i915_ggtt_enable_hw(dev);
741 DRM_ERROR("failed to re-enable GGTT\n");
743 intel_csr_ucode_resume(dev_priv);
745 mutex_lock(&dev->struct_mutex);
746 i915_gem_restore_gtt_mappings(dev);
747 mutex_unlock(&dev->struct_mutex);
749 i915_restore_state(dev);
750 intel_opregion_setup(dev);
752 intel_init_pch_refclk(dev);
753 drm_mode_config_reset(dev);
756 * Interrupts have to be enabled before any batches are run. If not the
757 * GPU will hang. i915_gem_init_hw() will initiate batches to
758 * update/restore the context.
760 * Modeset enabling in intel_modeset_init_hw() also needs working
763 intel_runtime_pm_enable_interrupts(dev_priv);
765 mutex_lock(&dev->struct_mutex);
766 if (i915_gem_init_hw(dev)) {
767 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
768 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
770 mutex_unlock(&dev->struct_mutex);
772 intel_guc_resume(dev);
774 intel_modeset_init_hw(dev);
776 spin_lock_irq(&dev_priv->irq_lock);
777 if (dev_priv->display.hpd_irq_setup)
778 dev_priv->display.hpd_irq_setup(dev_priv);
779 spin_unlock_irq(&dev_priv->irq_lock);
781 intel_dp_mst_resume(dev);
783 intel_display_resume(dev);
786 * ... but also need to make sure that hotplug processing
787 * doesn't cause havoc. Like in the driver load code we don't
788 * bother with the tiny race here where we might loose hotplug
791 intel_hpd_init(dev_priv);
792 /* Config may have changed between suspend and resume */
793 drm_helper_hpd_irq_event(dev);
795 intel_opregion_init(dev);
797 intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
799 mutex_lock(&dev_priv->modeset_restore_lock);
800 dev_priv->modeset_restore = MODESET_DONE;
801 mutex_unlock(&dev_priv->modeset_restore_lock);
803 intel_opregion_notify_adapter(dev, PCI_D0);
805 drm_kms_helper_poll_enable(dev);
807 enable_rpm_wakeref_asserts(dev_priv);
812 static int i915_drm_resume_early(struct drm_device *dev)
814 struct drm_i915_private *dev_priv = dev->dev_private;
818 * We have a resume ordering issue with the snd-hda driver also
819 * requiring our device to be power up. Due to the lack of a
820 * parent/child relationship we currently solve this with an early
823 * FIXME: This should be solved with a special hdmi sink device or
824 * similar so that power domains can be employed.
828 * Note that we need to set the power state explicitly, since we
829 * powered off the device during freeze and the PCI core won't power
830 * it back up for us during thaw. Powering off the device during
831 * freeze is not a hard requirement though, and during the
832 * suspend/resume phases the PCI core makes sure we get here with the
833 * device powered on. So in case we change our freeze logic and keep
834 * the device powered we can also remove the following set power state
837 ret = pci_set_power_state(dev->pdev, PCI_D0);
839 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret);
844 * Note that pci_enable_device() first enables any parent bridge
845 * device and only then sets the power state for this device. The
846 * bridge enabling is a nop though, since bridge devices are resumed
847 * first. The order of enabling power and enabling the device is
848 * imposed by the PCI core as described above, so here we preserve the
849 * same order for the freeze/thaw phases.
851 * TODO: eventually we should remove pci_disable_device() /
852 * pci_enable_enable_device() from suspend/resume. Due to how they
853 * depend on the device enable refcount we can't anyway depend on them
854 * disabling/enabling the device.
856 if (pci_enable_device(dev->pdev)) {
861 pci_set_master(dev->pdev);
863 disable_rpm_wakeref_asserts(dev_priv);
865 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
866 ret = vlv_resume_prepare(dev_priv, false);
868 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
871 intel_uncore_early_sanitize(dev_priv, true);
873 if (IS_BROXTON(dev_priv)) {
874 if (!dev_priv->suspended_to_idle)
875 gen9_sanitize_dc_state(dev_priv);
876 bxt_disable_dc9(dev_priv);
877 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
878 hsw_disable_pc8(dev_priv);
881 intel_uncore_sanitize(dev_priv);
883 if (IS_BROXTON(dev_priv) ||
884 !(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
885 intel_power_domains_init_hw(dev_priv, true);
887 enable_rpm_wakeref_asserts(dev_priv);
890 dev_priv->suspended_to_idle = false;
895 int i915_resume_switcheroo(struct drm_device *dev)
899 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
902 ret = i915_drm_resume_early(dev);
906 return i915_drm_resume(dev);
910 * i915_reset - reset chip after a hang
911 * @dev: drm device to reset
913 * Reset the chip. Useful if a hang is detected. Returns zero on successful
914 * reset or otherwise an error code.
916 * Procedure is fairly simple:
917 * - reset the chip using the reset reg
918 * - re-init context state
919 * - re-init hardware status page
920 * - re-init ring buffer
921 * - re-init interrupt state
924 int i915_reset(struct drm_i915_private *dev_priv)
926 struct drm_device *dev = dev_priv->dev;
927 struct i915_gpu_error *error = &dev_priv->gpu_error;
928 unsigned reset_counter;
931 intel_reset_gt_powersave(dev_priv);
933 mutex_lock(&dev->struct_mutex);
935 /* Clear any previous failed attempts at recovery. Time to try again. */
936 atomic_andnot(I915_WEDGED, &error->reset_counter);
938 /* Clear the reset-in-progress flag and increment the reset epoch. */
939 reset_counter = atomic_inc_return(&error->reset_counter);
940 if (WARN_ON(__i915_reset_in_progress(reset_counter))) {
947 ret = intel_gpu_reset(dev_priv, ALL_ENGINES);
949 /* Also reset the gpu hangman. */
950 if (error->stop_rings != 0) {
951 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
952 error->stop_rings = 0;
953 if (ret == -ENODEV) {
954 DRM_INFO("Reset not implemented, but ignoring "
955 "error for simulated gpu hangs\n");
960 if (i915_stop_ring_allow_warn(dev_priv))
961 pr_notice("drm/i915: Resetting chip after gpu hang\n");
965 DRM_ERROR("Failed to reset chip: %i\n", ret);
967 DRM_DEBUG_DRIVER("GPU reset disabled\n");
971 intel_overlay_reset(dev_priv);
973 /* Ok, now get things going again... */
976 * Everything depends on having the GTT running, so we need to start
977 * there. Fortunately we don't need to do this unless we reset the
978 * chip at a PCI level.
980 * Next we need to restore the context, but we don't use those
983 * Ring buffer needs to be re-initialized in the KMS case, or if X
984 * was running at the time of the reset (i.e. we weren't VT
987 ret = i915_gem_init_hw(dev);
989 DRM_ERROR("Failed hw init on reset %d\n", ret);
993 mutex_unlock(&dev->struct_mutex);
996 * rps/rc6 re-init is necessary to restore state lost after the
997 * reset and the re-install of gt irqs. Skip for ironlake per
998 * previous concerns that it doesn't respond well to some forms
999 * of re-init after reset.
1001 if (INTEL_INFO(dev)->gen > 5)
1002 intel_enable_gt_powersave(dev_priv);
1007 atomic_or(I915_WEDGED, &error->reset_counter);
1008 mutex_unlock(&dev->struct_mutex);
1012 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1014 struct intel_device_info *intel_info =
1015 (struct intel_device_info *) ent->driver_data;
1017 if (IS_PRELIMINARY_HW(intel_info) && !i915.preliminary_hw_support) {
1018 DRM_INFO("This hardware requires preliminary hardware support.\n"
1019 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1023 /* Only bind to function 0 of the device. Early generations
1024 * used function 1 as a placeholder for multi-head. This causes
1025 * us confusion instead, especially on the systems where both
1026 * functions have the same PCI-ID!
1028 if (PCI_FUNC(pdev->devfn))
1031 if (vga_switcheroo_client_probe_defer(pdev))
1032 return -EPROBE_DEFER;
1034 return drm_get_pci_dev(pdev, ent, &driver);
1038 i915_pci_remove(struct pci_dev *pdev)
1040 struct drm_device *dev = pci_get_drvdata(pdev);
1045 static int i915_pm_suspend(struct device *dev)
1047 struct pci_dev *pdev = to_pci_dev(dev);
1048 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1050 if (!drm_dev || !drm_dev->dev_private) {
1051 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1055 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1058 return i915_drm_suspend(drm_dev);
1061 static int i915_pm_suspend_late(struct device *dev)
1063 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1066 * We have a suspend ordering issue with the snd-hda driver also
1067 * requiring our device to be power up. Due to the lack of a
1068 * parent/child relationship we currently solve this with an late
1071 * FIXME: This should be solved with a special hdmi sink device or
1072 * similar so that power domains can be employed.
1074 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1077 return i915_drm_suspend_late(drm_dev, false);
1080 static int i915_pm_poweroff_late(struct device *dev)
1082 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1084 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1087 return i915_drm_suspend_late(drm_dev, true);
1090 static int i915_pm_resume_early(struct device *dev)
1092 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1094 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1097 return i915_drm_resume_early(drm_dev);
1100 static int i915_pm_resume(struct device *dev)
1102 struct drm_device *drm_dev = dev_to_i915(dev)->dev;
1104 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1107 return i915_drm_resume(drm_dev);
1110 /* freeze: before creating the hibernation_image */
1111 static int i915_pm_freeze(struct device *dev)
1113 return i915_pm_suspend(dev);
1116 static int i915_pm_freeze_late(struct device *dev)
1120 ret = i915_pm_suspend_late(dev);
1124 ret = i915_gem_freeze_late(dev_to_i915(dev));
1131 /* thaw: called after creating the hibernation image, but before turning off. */
1132 static int i915_pm_thaw_early(struct device *dev)
1134 return i915_pm_resume_early(dev);
1137 static int i915_pm_thaw(struct device *dev)
1139 return i915_pm_resume(dev);
1142 /* restore: called after loading the hibernation image. */
1143 static int i915_pm_restore_early(struct device *dev)
1145 return i915_pm_resume_early(dev);
1148 static int i915_pm_restore(struct device *dev)
1150 return i915_pm_resume(dev);
1154 * Save all Gunit registers that may be lost after a D3 and a subsequent
1155 * S0i[R123] transition. The list of registers needing a save/restore is
1156 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1157 * registers in the following way:
1158 * - Driver: saved/restored by the driver
1159 * - Punit : saved/restored by the Punit firmware
1160 * - No, w/o marking: no need to save/restore, since the register is R/O or
1161 * used internally by the HW in a way that doesn't depend
1162 * keeping the content across a suspend/resume.
1163 * - Debug : used for debugging
1165 * We save/restore all registers marked with 'Driver', with the following
1167 * - Registers out of use, including also registers marked with 'Debug'.
1168 * These have no effect on the driver's operation, so we don't save/restore
1169 * them to reduce the overhead.
1170 * - Registers that are fully setup by an initialization function called from
1171 * the resume path. For example many clock gating and RPS/RC6 registers.
1172 * - Registers that provide the right functionality with their reset defaults.
1174 * TODO: Except for registers that based on the above 3 criteria can be safely
1175 * ignored, we save/restore all others, practically treating the HW context as
1176 * a black-box for the driver. Further investigation is needed to reduce the
1177 * saved/restored registers even further, by following the same 3 criteria.
1179 static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1181 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1184 /* GAM 0x4000-0x4770 */
1185 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
1186 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
1187 s->arb_mode = I915_READ(ARB_MODE);
1188 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
1189 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
1191 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1192 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i));
1194 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
1195 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT);
1197 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
1198 s->ecochk = I915_READ(GAM_ECOCHK);
1199 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
1200 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
1202 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
1204 /* MBC 0x9024-0x91D0, 0x8500 */
1205 s->g3dctl = I915_READ(VLV_G3DCTL);
1206 s->gsckgctl = I915_READ(VLV_GSCKGCTL);
1207 s->mbctl = I915_READ(GEN6_MBCTL);
1209 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1210 s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1211 s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1212 s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1213 s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1214 s->rstctl = I915_READ(GEN6_RSTCTL);
1215 s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1217 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1218 s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1219 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1220 s->rpdeuc = I915_READ(GEN6_RPDEUC);
1221 s->ecobus = I915_READ(ECOBUS);
1222 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1223 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1224 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1225 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1226 s->rcedata = I915_READ(VLV_RCEDATA);
1227 s->spare2gh = I915_READ(VLV_SPAREG2H);
1229 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1230 s->gt_imr = I915_READ(GTIMR);
1231 s->gt_ier = I915_READ(GTIER);
1232 s->pm_imr = I915_READ(GEN6_PMIMR);
1233 s->pm_ier = I915_READ(GEN6_PMIER);
1235 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1236 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH(i));
1238 /* GT SA CZ domain, 0x100000-0x138124 */
1239 s->tilectl = I915_READ(TILECTL);
1240 s->gt_fifoctl = I915_READ(GTFIFOCTL);
1241 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1242 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1243 s->pmwgicz = I915_READ(VLV_PMWGICZ);
1245 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1246 s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1247 s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1248 s->pcbr = I915_READ(VLV_PCBR);
1249 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1252 * Not saving any of:
1253 * DFT, 0x9800-0x9EC0
1254 * SARB, 0xB000-0xB1FC
1255 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1260 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1262 struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1266 /* GAM 0x4000-0x4770 */
1267 I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1268 I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1269 I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1270 I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1271 I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1273 for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1274 I915_WRITE(GEN7_LRA_LIMITS(i), s->lra_limits[i]);
1276 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1277 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT, s->gfx_max_req_count);
1279 I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1280 I915_WRITE(GAM_ECOCHK, s->ecochk);
1281 I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1282 I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1284 I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1286 /* MBC 0x9024-0x91D0, 0x8500 */
1287 I915_WRITE(VLV_G3DCTL, s->g3dctl);
1288 I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1289 I915_WRITE(GEN6_MBCTL, s->mbctl);
1291 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1292 I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1293 I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1294 I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1295 I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1296 I915_WRITE(GEN6_RSTCTL, s->rstctl);
1297 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1299 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1300 I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1301 I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1302 I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1303 I915_WRITE(ECOBUS, s->ecobus);
1304 I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1305 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1306 I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1307 I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1308 I915_WRITE(VLV_RCEDATA, s->rcedata);
1309 I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1311 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1312 I915_WRITE(GTIMR, s->gt_imr);
1313 I915_WRITE(GTIER, s->gt_ier);
1314 I915_WRITE(GEN6_PMIMR, s->pm_imr);
1315 I915_WRITE(GEN6_PMIER, s->pm_ier);
1317 for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1318 I915_WRITE(GEN7_GT_SCRATCH(i), s->gt_scratch[i]);
1320 /* GT SA CZ domain, 0x100000-0x138124 */
1321 I915_WRITE(TILECTL, s->tilectl);
1322 I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1324 * Preserve the GT allow wake and GFX force clock bit, they are not
1325 * be restored, as they are used to control the s0ix suspend/resume
1326 * sequence by the caller.
1328 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1329 val &= VLV_GTLC_ALLOWWAKEREQ;
1330 val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1331 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1333 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1334 val &= VLV_GFX_CLK_FORCE_ON_BIT;
1335 val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1336 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1338 I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1340 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1341 I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1342 I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1343 I915_WRITE(VLV_PCBR, s->pcbr);
1344 I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1347 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
1352 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1354 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1355 val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
1357 val |= VLV_GFX_CLK_FORCE_ON_BIT;
1358 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1363 err = wait_for(COND, 20);
1365 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1366 I915_READ(VLV_GTLC_SURVIVABILITY_REG));
1372 static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1377 val = I915_READ(VLV_GTLC_WAKE_CTRL);
1378 val &= ~VLV_GTLC_ALLOWWAKEREQ;
1380 val |= VLV_GTLC_ALLOWWAKEREQ;
1381 I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1382 POSTING_READ(VLV_GTLC_WAKE_CTRL);
1384 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1386 err = wait_for(COND, 1);
1388 DRM_ERROR("timeout disabling GT waking\n");
1393 static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1400 mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1401 val = wait_for_on ? mask : 0;
1402 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1406 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1408 I915_READ(VLV_GTLC_PW_STATUS));
1411 * RC6 transitioning can be delayed up to 2 msec (see
1412 * valleyview_enable_rps), use 3 msec for safety.
1414 err = wait_for(COND, 3);
1416 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1417 onoff(wait_for_on));
1423 static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1425 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1428 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1429 I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1432 static int vlv_suspend_complete(struct drm_i915_private *dev_priv)
1438 * Bspec defines the following GT well on flags as debug only, so
1439 * don't treat them as hard failures.
1441 (void)vlv_wait_for_gt_wells(dev_priv, false);
1443 mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1444 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1446 vlv_check_no_gt_access(dev_priv);
1448 err = vlv_force_gfx_clock(dev_priv, true);
1452 err = vlv_allow_gt_wake(dev_priv, false);
1456 if (!IS_CHERRYVIEW(dev_priv))
1457 vlv_save_gunit_s0ix_state(dev_priv);
1459 err = vlv_force_gfx_clock(dev_priv, false);
1466 /* For safety always re-enable waking and disable gfx clock forcing */
1467 vlv_allow_gt_wake(dev_priv, true);
1469 vlv_force_gfx_clock(dev_priv, false);
1474 static int vlv_resume_prepare(struct drm_i915_private *dev_priv,
1477 struct drm_device *dev = dev_priv->dev;
1482 * If any of the steps fail just try to continue, that's the best we
1483 * can do at this point. Return the first error code (which will also
1484 * leave RPM permanently disabled).
1486 ret = vlv_force_gfx_clock(dev_priv, true);
1488 if (!IS_CHERRYVIEW(dev_priv))
1489 vlv_restore_gunit_s0ix_state(dev_priv);
1491 err = vlv_allow_gt_wake(dev_priv, true);
1495 err = vlv_force_gfx_clock(dev_priv, false);
1499 vlv_check_no_gt_access(dev_priv);
1502 intel_init_clock_gating(dev);
1503 i915_gem_restore_fences(dev);
1509 static int intel_runtime_suspend(struct device *device)
1511 struct pci_dev *pdev = to_pci_dev(device);
1512 struct drm_device *dev = pci_get_drvdata(pdev);
1513 struct drm_i915_private *dev_priv = dev->dev_private;
1516 if (WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6())))
1519 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1522 DRM_DEBUG_KMS("Suspending device\n");
1525 * We could deadlock here in case another thread holding struct_mutex
1526 * calls RPM suspend concurrently, since the RPM suspend will wait
1527 * first for this RPM suspend to finish. In this case the concurrent
1528 * RPM resume will be followed by its RPM suspend counterpart. Still
1529 * for consistency return -EAGAIN, which will reschedule this suspend.
1531 if (!mutex_trylock(&dev->struct_mutex)) {
1532 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1534 * Bump the expiration timestamp, otherwise the suspend won't
1537 pm_runtime_mark_last_busy(device);
1542 disable_rpm_wakeref_asserts(dev_priv);
1545 * We are safe here against re-faults, since the fault handler takes
1548 i915_gem_release_all_mmaps(dev_priv);
1549 mutex_unlock(&dev->struct_mutex);
1551 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1553 intel_guc_suspend(dev);
1555 intel_suspend_gt_powersave(dev_priv);
1556 intel_runtime_pm_disable_interrupts(dev_priv);
1559 if (IS_BROXTON(dev_priv)) {
1560 bxt_display_core_uninit(dev_priv);
1561 bxt_enable_dc9(dev_priv);
1562 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1563 hsw_enable_pc8(dev_priv);
1564 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1565 ret = vlv_suspend_complete(dev_priv);
1569 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret);
1570 intel_runtime_pm_enable_interrupts(dev_priv);
1572 enable_rpm_wakeref_asserts(dev_priv);
1577 intel_uncore_forcewake_reset(dev_priv, false);
1579 enable_rpm_wakeref_asserts(dev_priv);
1580 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1582 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv))
1583 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1585 dev_priv->pm.suspended = true;
1588 * FIXME: We really should find a document that references the arguments
1591 if (IS_BROADWELL(dev)) {
1593 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1594 * being detected, and the call we do at intel_runtime_resume()
1595 * won't be able to restore them. Since PCI_D3hot matches the
1596 * actual specification and appears to be working, use it.
1598 intel_opregion_notify_adapter(dev, PCI_D3hot);
1601 * current versions of firmware which depend on this opregion
1602 * notification have repurposed the D1 definition to mean
1603 * "runtime suspended" vs. what you would normally expect (D3)
1604 * to distinguish it from notifications that might be sent via
1607 intel_opregion_notify_adapter(dev, PCI_D1);
1610 assert_forcewakes_inactive(dev_priv);
1612 DRM_DEBUG_KMS("Device suspended\n");
1616 static int intel_runtime_resume(struct device *device)
1618 struct pci_dev *pdev = to_pci_dev(device);
1619 struct drm_device *dev = pci_get_drvdata(pdev);
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1623 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev)))
1626 DRM_DEBUG_KMS("Resuming device\n");
1628 WARN_ON_ONCE(atomic_read(&dev_priv->pm.wakeref_count));
1629 disable_rpm_wakeref_asserts(dev_priv);
1631 intel_opregion_notify_adapter(dev, PCI_D0);
1632 dev_priv->pm.suspended = false;
1633 if (intel_uncore_unclaimed_mmio(dev_priv))
1634 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1636 intel_guc_resume(dev);
1638 if (IS_GEN6(dev_priv))
1639 intel_init_pch_refclk(dev);
1641 if (IS_BROXTON(dev)) {
1642 bxt_disable_dc9(dev_priv);
1643 bxt_display_core_init(dev_priv, true);
1644 if (dev_priv->csr.dmc_payload &&
1645 (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
1646 gen9_enable_dc5(dev_priv);
1647 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1648 hsw_disable_pc8(dev_priv);
1649 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1650 ret = vlv_resume_prepare(dev_priv, true);
1654 * No point of rolling back things in case of an error, as the best
1655 * we can do is to hope that things will still work (and disable RPM).
1657 i915_gem_init_swizzling(dev);
1658 gen6_update_ring_freq(dev_priv);
1660 intel_runtime_pm_enable_interrupts(dev_priv);
1663 * On VLV/CHV display interrupts are part of the display
1664 * power well, so hpd is reinitialized from there. For
1665 * everyone else do it here.
1667 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1668 intel_hpd_init(dev_priv);
1670 intel_enable_gt_powersave(dev_priv);
1672 enable_rpm_wakeref_asserts(dev_priv);
1675 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret);
1677 DRM_DEBUG_KMS("Device resumed\n");
1682 static const struct dev_pm_ops i915_pm_ops = {
1684 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1687 .suspend = i915_pm_suspend,
1688 .suspend_late = i915_pm_suspend_late,
1689 .resume_early = i915_pm_resume_early,
1690 .resume = i915_pm_resume,
1694 * @freeze, @freeze_late : called (1) before creating the
1695 * hibernation image [PMSG_FREEZE] and
1696 * (2) after rebooting, before restoring
1697 * the image [PMSG_QUIESCE]
1698 * @thaw, @thaw_early : called (1) after creating the hibernation
1699 * image, before writing it [PMSG_THAW]
1700 * and (2) after failing to create or
1701 * restore the image [PMSG_RECOVER]
1702 * @poweroff, @poweroff_late: called after writing the hibernation
1703 * image, before rebooting [PMSG_HIBERNATE]
1704 * @restore, @restore_early : called after rebooting and restoring the
1705 * hibernation image [PMSG_RESTORE]
1707 .freeze = i915_pm_freeze,
1708 .freeze_late = i915_pm_freeze_late,
1709 .thaw_early = i915_pm_thaw_early,
1710 .thaw = i915_pm_thaw,
1711 .poweroff = i915_pm_suspend,
1712 .poweroff_late = i915_pm_poweroff_late,
1713 .restore_early = i915_pm_restore_early,
1714 .restore = i915_pm_restore,
1716 /* S0ix (via runtime suspend) event handlers */
1717 .runtime_suspend = intel_runtime_suspend,
1718 .runtime_resume = intel_runtime_resume,
1721 static const struct vm_operations_struct i915_gem_vm_ops = {
1722 .fault = i915_gem_fault,
1723 .open = drm_gem_vm_open,
1724 .close = drm_gem_vm_close,
1727 static const struct file_operations i915_driver_fops = {
1728 .owner = THIS_MODULE,
1730 .release = drm_release,
1731 .unlocked_ioctl = drm_ioctl,
1732 .mmap = drm_gem_mmap,
1735 #ifdef CONFIG_COMPAT
1736 .compat_ioctl = i915_compat_ioctl,
1738 .llseek = noop_llseek,
1741 static struct drm_driver driver = {
1742 /* Don't use MTRRs here; the Xserver or userspace app should
1743 * deal with them for Intel hardware.
1746 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME |
1747 DRIVER_RENDER | DRIVER_MODESET,
1748 .load = i915_driver_load,
1749 .unload = i915_driver_unload,
1750 .open = i915_driver_open,
1751 .lastclose = i915_driver_lastclose,
1752 .preclose = i915_driver_preclose,
1753 .postclose = i915_driver_postclose,
1754 .set_busid = drm_pci_set_busid,
1756 #if defined(CONFIG_DEBUG_FS)
1757 .debugfs_init = i915_debugfs_init,
1758 .debugfs_cleanup = i915_debugfs_cleanup,
1760 .gem_free_object = i915_gem_free_object,
1761 .gem_vm_ops = &i915_gem_vm_ops,
1763 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1764 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1765 .gem_prime_export = i915_gem_prime_export,
1766 .gem_prime_import = i915_gem_prime_import,
1768 .dumb_create = i915_gem_dumb_create,
1769 .dumb_map_offset = i915_gem_mmap_gtt,
1770 .dumb_destroy = drm_gem_dumb_destroy,
1771 .ioctls = i915_ioctls,
1772 .fops = &i915_driver_fops,
1773 .name = DRIVER_NAME,
1774 .desc = DRIVER_DESC,
1775 .date = DRIVER_DATE,
1776 .major = DRIVER_MAJOR,
1777 .minor = DRIVER_MINOR,
1778 .patchlevel = DRIVER_PATCHLEVEL,
1781 static struct pci_driver i915_pci_driver = {
1782 .name = DRIVER_NAME,
1783 .id_table = pciidlist,
1784 .probe = i915_pci_probe,
1785 .remove = i915_pci_remove,
1786 .driver.pm = &i915_pm_ops,
1789 static int __init i915_init(void)
1791 driver.num_ioctls = i915_max_ioctl;
1794 * Enable KMS by default, unless explicitly overriden by
1795 * either the i915.modeset prarameter or by the
1796 * vga_text_mode_force boot option.
1799 if (i915.modeset == 0)
1800 driver.driver_features &= ~DRIVER_MODESET;
1802 if (vgacon_text_force() && i915.modeset == -1)
1803 driver.driver_features &= ~DRIVER_MODESET;
1805 if (!(driver.driver_features & DRIVER_MODESET)) {
1806 /* Silently fail loading to not upset userspace. */
1807 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1811 if (i915.nuclear_pageflip)
1812 driver.driver_features |= DRIVER_ATOMIC;
1814 return drm_pci_init(&driver, &i915_pci_driver);
1817 static void __exit i915_exit(void)
1819 if (!(driver.driver_features & DRIVER_MODESET))
1820 return; /* Never loaded a driver. */
1822 drm_pci_exit(&driver, &i915_pci_driver);
1825 module_init(i915_init);
1826 module_exit(i915_exit);
1828 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1829 MODULE_AUTHOR("Intel Corporation");
1831 MODULE_DESCRIPTION(DRIVER_DESC);
1832 MODULE_LICENSE("GPL and additional rights");