1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150410"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES = _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain {
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
173 POWER_DOMAIN_TRANSCODER_A,
174 POWER_DOMAIN_TRANSCODER_B,
175 POWER_DOMAIN_TRANSCODER_C,
176 POWER_DOMAIN_TRANSCODER_EDP,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES,
185 POWER_DOMAIN_PORT_DSI,
186 POWER_DOMAIN_PORT_CRT,
187 POWER_DOMAIN_PORT_OTHER,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
210 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_crtc(dev, intel_crtc) \
242 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
244 #define for_each_intel_encoder(dev, intel_encoder) \
245 list_for_each_entry(intel_encoder, \
246 &(dev)->mode_config.encoder_list, \
249 #define for_each_intel_connector(dev, intel_connector) \
250 list_for_each_entry(intel_connector, \
251 &dev->mode_config.connector_list, \
255 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
256 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
257 if ((intel_encoder)->base.crtc == (__crtc))
259 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
260 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
261 if ((intel_connector)->base.encoder == (__encoder))
263 #define for_each_power_domain(domain, mask) \
264 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
265 if ((1 << (domain)) & (mask))
267 struct drm_i915_private;
268 struct i915_mm_struct;
269 struct i915_mmu_object;
272 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
273 /* real shared dpll ids must be >= 0 */
274 DPLL_ID_PCH_PLL_A = 0,
275 DPLL_ID_PCH_PLL_B = 1,
280 DPLL_ID_SKL_DPLL1 = 0,
281 DPLL_ID_SKL_DPLL2 = 1,
282 DPLL_ID_SKL_DPLL3 = 2,
284 #define I915_NUM_PLLS 3
286 struct intel_dpll_hw_state {
298 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
299 * lower part of crtl1 and they get shifted into position when writing
300 * the register. This allows us to easily compare the state to share
304 /* HDMI only, 0 when used for DP */
305 uint32_t cfgcr1, cfgcr2;
308 struct intel_shared_dpll_config {
309 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
310 struct intel_dpll_hw_state hw_state;
313 struct intel_shared_dpll {
314 struct intel_shared_dpll_config config;
315 struct intel_shared_dpll_config *new_config;
317 int active; /* count of number of active CRTCs (i.e. DPMS on) */
318 bool on; /* is the PLL actually active? Disabled during modeset */
320 /* should match the index in the dev_priv->shared_dplls array */
321 enum intel_dpll_id id;
322 /* The mode_set hook is optional and should be used together with the
323 * intel_prepare_shared_dpll function. */
324 void (*mode_set)(struct drm_i915_private *dev_priv,
325 struct intel_shared_dpll *pll);
326 void (*enable)(struct drm_i915_private *dev_priv,
327 struct intel_shared_dpll *pll);
328 void (*disable)(struct drm_i915_private *dev_priv,
329 struct intel_shared_dpll *pll);
330 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
331 struct intel_shared_dpll *pll,
332 struct intel_dpll_hw_state *hw_state);
340 /* Used by dp and fdi links */
341 struct intel_link_m_n {
349 void intel_link_compute_m_n(int bpp, int nlanes,
350 int pixel_clock, int link_clock,
351 struct intel_link_m_n *m_n);
353 /* Interface history:
356 * 1.2: Add Power Management
357 * 1.3: Add vblank support
358 * 1.4: Fix cmdbuffer path, add heap destroy
359 * 1.5: Add vblank pipe configuration
360 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
361 * - Support vertical blank on secondary display pipe
363 #define DRIVER_MAJOR 1
364 #define DRIVER_MINOR 6
365 #define DRIVER_PATCHLEVEL 0
367 #define WATCH_LISTS 0
369 struct opregion_header;
370 struct opregion_acpi;
371 struct opregion_swsci;
372 struct opregion_asle;
374 struct intel_opregion {
375 struct opregion_header __iomem *header;
376 struct opregion_acpi __iomem *acpi;
377 struct opregion_swsci __iomem *swsci;
378 u32 swsci_gbda_sub_functions;
379 u32 swsci_sbcb_sub_functions;
380 struct opregion_asle __iomem *asle;
382 u32 __iomem *lid_state;
383 struct work_struct asle_work;
385 #define OPREGION_SIZE (8*1024)
387 struct intel_overlay;
388 struct intel_overlay_error_state;
390 #define I915_FENCE_REG_NONE -1
391 #define I915_MAX_NUM_FENCES 32
392 /* 32 fences + sign bit for FENCE_REG_NONE */
393 #define I915_MAX_NUM_FENCE_BITS 6
395 struct drm_i915_fence_reg {
396 struct list_head lru_list;
397 struct drm_i915_gem_object *obj;
401 struct sdvo_device_mapping {
410 struct intel_display_error_state;
412 struct drm_i915_error_state {
420 /* Generic register state */
428 u32 error; /* gen6+ */
429 u32 err_int; /* gen7 */
430 u32 fault_data0; /* gen8, gen9 */
431 u32 fault_data1; /* gen8, gen9 */
437 u32 extra_instdone[I915_NUM_INSTDONE_REG];
438 u64 fence[I915_MAX_NUM_FENCES];
439 struct intel_overlay_error_state *overlay;
440 struct intel_display_error_state *display;
441 struct drm_i915_error_object *semaphore_obj;
443 struct drm_i915_error_ring {
445 /* Software tracked state */
448 enum intel_ring_hangcheck_action hangcheck_action;
451 /* our own tracking of ring head and tail */
455 u32 semaphore_seqno[I915_NUM_RINGS - 1];
474 u32 rc_psmi; /* sleep state */
475 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
477 struct drm_i915_error_object {
481 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
483 struct drm_i915_error_request {
498 char comm[TASK_COMM_LEN];
499 } ring[I915_NUM_RINGS];
501 struct drm_i915_error_buffer {
508 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
516 } **active_bo, **pinned_bo;
518 u32 *active_bo_count, *pinned_bo_count;
522 struct intel_connector;
523 struct intel_encoder;
524 struct intel_crtc_state;
525 struct intel_initial_plane_config;
530 struct drm_i915_display_funcs {
531 bool (*fbc_enabled)(struct drm_device *dev);
532 void (*enable_fbc)(struct drm_crtc *crtc);
533 void (*disable_fbc)(struct drm_device *dev);
534 int (*get_display_clock_speed)(struct drm_device *dev);
535 int (*get_fifo_size)(struct drm_device *dev, int plane);
537 * find_dpll() - Find the best values for the PLL
538 * @limit: limits for the PLL
539 * @crtc: current CRTC
540 * @target: target frequency in kHz
541 * @refclk: reference clock frequency in kHz
542 * @match_clock: if provided, @best_clock P divider must
543 * match the P divider from @match_clock
544 * used for LVDS downclocking
545 * @best_clock: best PLL values found
547 * Returns true on success, false on failure.
549 bool (*find_dpll)(const struct intel_limit *limit,
550 struct intel_crtc_state *crtc_state,
551 int target, int refclk,
552 struct dpll *match_clock,
553 struct dpll *best_clock);
554 void (*update_wm)(struct drm_crtc *crtc);
555 void (*update_sprite_wm)(struct drm_plane *plane,
556 struct drm_crtc *crtc,
557 uint32_t sprite_width, uint32_t sprite_height,
558 int pixel_size, bool enable, bool scaled);
559 void (*modeset_global_resources)(struct drm_atomic_state *state);
560 /* Returns the active state of the crtc, and if the crtc is active,
561 * fills out the pipe-config with the hw state. */
562 bool (*get_pipe_config)(struct intel_crtc *,
563 struct intel_crtc_state *);
564 void (*get_initial_plane_config)(struct intel_crtc *,
565 struct intel_initial_plane_config *);
566 int (*crtc_compute_clock)(struct intel_crtc *crtc,
567 struct intel_crtc_state *crtc_state);
568 void (*crtc_enable)(struct drm_crtc *crtc);
569 void (*crtc_disable)(struct drm_crtc *crtc);
570 void (*off)(struct drm_crtc *crtc);
571 void (*audio_codec_enable)(struct drm_connector *connector,
572 struct intel_encoder *encoder,
573 struct drm_display_mode *mode);
574 void (*audio_codec_disable)(struct intel_encoder *encoder);
575 void (*fdi_link_train)(struct drm_crtc *crtc);
576 void (*init_clock_gating)(struct drm_device *dev);
577 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
578 struct drm_framebuffer *fb,
579 struct drm_i915_gem_object *obj,
580 struct intel_engine_cs *ring,
582 void (*update_primary_plane)(struct drm_crtc *crtc,
583 struct drm_framebuffer *fb,
585 void (*hpd_irq_setup)(struct drm_device *dev);
586 /* clock updates for mode set */
588 /* render clock increase/decrease */
589 /* display clock increase/decrease */
590 /* pll clock increase/decrease */
592 int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
593 uint32_t (*get_backlight)(struct intel_connector *connector);
594 void (*set_backlight)(struct intel_connector *connector,
596 void (*disable_backlight)(struct intel_connector *connector);
597 void (*enable_backlight)(struct intel_connector *connector);
600 enum forcewake_domain_id {
601 FW_DOMAIN_ID_RENDER = 0,
602 FW_DOMAIN_ID_BLITTER,
608 enum forcewake_domains {
609 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
610 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
611 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
612 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
617 struct intel_uncore_funcs {
618 void (*force_wake_get)(struct drm_i915_private *dev_priv,
619 enum forcewake_domains domains);
620 void (*force_wake_put)(struct drm_i915_private *dev_priv,
621 enum forcewake_domains domains);
623 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
624 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
625 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
626 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
628 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
629 uint8_t val, bool trace);
630 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
631 uint16_t val, bool trace);
632 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
633 uint32_t val, bool trace);
634 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
635 uint64_t val, bool trace);
638 struct intel_uncore {
639 spinlock_t lock; /** lock is also taken in irq contexts. */
641 struct intel_uncore_funcs funcs;
644 enum forcewake_domains fw_domains;
646 struct intel_uncore_forcewake_domain {
647 struct drm_i915_private *i915;
648 enum forcewake_domain_id id;
650 struct timer_list timer;
657 } fw_domain[FW_DOMAIN_ID_COUNT];
660 /* Iterate over initialised fw domains */
661 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
662 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
663 (i__) < FW_DOMAIN_ID_COUNT; \
664 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
665 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
667 #define for_each_fw_domain(domain__, dev_priv__, i__) \
668 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
670 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
671 func(is_mobile) sep \
674 func(is_i945gm) sep \
676 func(need_gfx_hws) sep \
678 func(is_pineview) sep \
679 func(is_broadwater) sep \
680 func(is_crestline) sep \
681 func(is_ivybridge) sep \
682 func(is_valleyview) sep \
683 func(is_haswell) sep \
684 func(is_skylake) sep \
685 func(is_preliminary) sep \
687 func(has_pipe_cxsr) sep \
688 func(has_hotplug) sep \
689 func(cursor_needs_physical) sep \
690 func(has_overlay) sep \
691 func(overlay_needs_physical) sep \
692 func(supports_tv) sep \
697 #define DEFINE_FLAG(name) u8 name:1
698 #define SEP_SEMICOLON ;
700 struct intel_device_info {
701 u32 display_mmio_offset;
704 u8 num_sprites[I915_MAX_PIPES];
706 u8 ring_mask; /* Rings supported by the HW */
707 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
708 /* Register offsets for the various display pipes and transcoders */
709 int pipe_offsets[I915_MAX_TRANSCODERS];
710 int trans_offsets[I915_MAX_TRANSCODERS];
711 int palette_offsets[I915_MAX_PIPES];
712 int cursor_offsets[I915_MAX_PIPES];
714 /* Slice/subslice/EU info */
717 u8 subslice_per_slice;
720 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
723 u8 has_subslice_pg:1;
730 enum i915_cache_level {
732 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
733 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
734 caches, eg sampler/render caches, and the
735 large Last-Level-Cache. LLC is coherent with
736 the CPU, but L3 is only visible to the GPU. */
737 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
740 struct i915_ctx_hang_stats {
741 /* This context had batch pending when hang was declared */
742 unsigned batch_pending;
744 /* This context had batch active when hang was declared */
745 unsigned batch_active;
747 /* Time when this context was last blamed for a GPU reset */
748 unsigned long guilty_ts;
750 /* If the contexts causes a second GPU hang within this time,
751 * it is permanently banned from submitting any more work.
753 unsigned long ban_period_seconds;
755 /* This context is banned to submit more work */
759 /* This must match up with the value previously used for execbuf2.rsvd1. */
760 #define DEFAULT_CONTEXT_HANDLE 0
762 * struct intel_context - as the name implies, represents a context.
763 * @ref: reference count.
764 * @user_handle: userspace tracking identity for this context.
765 * @remap_slice: l3 row remapping information.
766 * @file_priv: filp associated with this context (NULL for global default
768 * @hang_stats: information about the role of this context in possible GPU
770 * @vm: virtual memory space used by this context.
771 * @legacy_hw_ctx: render context backing object and whether it is correctly
772 * initialized (legacy ring submission mechanism only).
773 * @link: link in the global list of contexts.
775 * Contexts are memory images used by the hardware to store copies of their
778 struct intel_context {
782 struct drm_i915_file_private *file_priv;
783 struct i915_ctx_hang_stats hang_stats;
784 struct i915_hw_ppgtt *ppgtt;
786 /* Legacy ring buffer submission */
788 struct drm_i915_gem_object *rcs_state;
793 bool rcs_initialized;
795 struct drm_i915_gem_object *state;
796 struct intel_ringbuffer *ringbuf;
798 } engine[I915_NUM_RINGS];
800 struct list_head link;
811 unsigned long uncompressed_size;
814 unsigned int possible_framebuffer_bits;
815 unsigned int busy_bits;
816 struct intel_crtc *crtc;
819 struct drm_mm_node compressed_fb;
820 struct drm_mm_node *compressed_llb;
824 /* Tracks whether the HW is actually enabled, not whether the feature is
828 struct intel_fbc_work {
829 struct delayed_work work;
830 struct drm_crtc *crtc;
831 struct drm_framebuffer *fb;
835 FBC_OK, /* FBC is enabled */
836 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
837 FBC_NO_OUTPUT, /* no outputs enabled to compress */
838 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
839 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
840 FBC_MODE_TOO_LARGE, /* mode too large for compression */
841 FBC_BAD_PLANE, /* fbc not supported on plane */
842 FBC_NOT_TILED, /* buffer not tiled */
843 FBC_MULTIPLE_PIPES, /* more than one pipe active */
845 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
850 * HIGH_RR is the highest eDP panel refresh rate read from EDID
851 * LOW_RR is the lowest eDP panel refresh rate found from EDID
852 * parsing for same resolution.
854 enum drrs_refresh_rate_type {
857 DRRS_MAX_RR, /* RR count */
860 enum drrs_support_type {
861 DRRS_NOT_SUPPORTED = 0,
862 STATIC_DRRS_SUPPORT = 1,
863 SEAMLESS_DRRS_SUPPORT = 2
869 struct delayed_work work;
871 unsigned busy_frontbuffer_bits;
872 enum drrs_refresh_rate_type refresh_rate_type;
873 enum drrs_support_type type;
880 struct intel_dp *enabled;
882 struct delayed_work work;
883 unsigned busy_frontbuffer_bits;
890 PCH_NONE = 0, /* No PCH present */
891 PCH_IBX, /* Ibexpeak PCH */
892 PCH_CPT, /* Cougarpoint PCH */
893 PCH_LPT, /* Lynxpoint PCH */
894 PCH_SPT, /* Sunrisepoint PCH */
898 enum intel_sbi_destination {
903 #define QUIRK_PIPEA_FORCE (1<<0)
904 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
905 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
906 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
907 #define QUIRK_PIPEB_FORCE (1<<4)
908 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
911 struct intel_fbc_work;
914 struct i2c_adapter adapter;
918 struct i2c_algo_bit_data bit_algo;
919 struct drm_i915_private *dev_priv;
922 struct i915_suspend_saved_registers {
925 u32 savePP_ON_DELAYS;
926 u32 savePP_OFF_DELAYS;
932 u32 saveCACHE_MODE_0;
933 u32 saveMI_ARB_STATE;
937 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
938 u32 savePCH_PORT_HOTPLUG;
942 struct vlv_s0ix_state {
949 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
950 u32 media_max_req_count;
951 u32 gfx_max_req_count;
983 /* Display 1 CZ domain */
988 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
990 /* GT SA CZ domain */
997 /* Display 2 CZ domain */
1000 u32 clock_gate_dis2;
1003 struct intel_rps_ei {
1009 struct intel_gen6_power_mgmt {
1011 * work, interrupts_enabled and pm_iir are protected by
1012 * dev_priv->irq_lock
1014 struct work_struct work;
1015 bool interrupts_enabled;
1018 /* Frequencies are stored in potentially platform dependent multiples.
1019 * In other words, *_freq needs to be multiplied by X to be interesting.
1020 * Soft limits are those which are used for the dynamic reclocking done
1021 * by the driver (raise frequencies under heavy loads, and lower for
1022 * lighter loads). Hard limits are those imposed by the hardware.
1024 * A distinction is made for overclocking, which is never enabled by
1025 * default, and is considered to be above the hard limit if it's
1028 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1029 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1030 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1031 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1032 u8 min_freq; /* AKA RPn. Minimum frequency */
1033 u8 idle_freq; /* Frequency to request when we are idle */
1034 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1035 u8 rp1_freq; /* "less than" RP0 power/freqency */
1036 u8 rp0_freq; /* Non-overclocked max frequency. */
1039 u8 up_threshold; /* Current %busy required to uplock */
1040 u8 down_threshold; /* Current %busy required to downclock */
1043 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1046 struct delayed_work delayed_resume_work;
1047 struct list_head clients;
1050 /* manual wa residency calculations */
1051 struct intel_rps_ei up_ei, down_ei;
1054 * Protects RPS/RC6 register access and PCU communication.
1055 * Must be taken after struct_mutex if nested.
1057 struct mutex hw_lock;
1060 /* defined intel_pm.c */
1061 extern spinlock_t mchdev_lock;
1063 struct intel_ilk_power_mgmt {
1071 unsigned long last_time1;
1072 unsigned long chipset_power;
1075 unsigned long gfx_power;
1082 struct drm_i915_private;
1083 struct i915_power_well;
1085 struct i915_power_well_ops {
1087 * Synchronize the well's hw state to match the current sw state, for
1088 * example enable/disable it based on the current refcount. Called
1089 * during driver init and resume time, possibly after first calling
1090 * the enable/disable handlers.
1092 void (*sync_hw)(struct drm_i915_private *dev_priv,
1093 struct i915_power_well *power_well);
1095 * Enable the well and resources that depend on it (for example
1096 * interrupts located on the well). Called after the 0->1 refcount
1099 void (*enable)(struct drm_i915_private *dev_priv,
1100 struct i915_power_well *power_well);
1102 * Disable the well and resources that depend on it. Called after
1103 * the 1->0 refcount transition.
1105 void (*disable)(struct drm_i915_private *dev_priv,
1106 struct i915_power_well *power_well);
1107 /* Returns the hw enabled state. */
1108 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1109 struct i915_power_well *power_well);
1112 /* Power well structure for haswell */
1113 struct i915_power_well {
1116 /* power well enable/disable usage count */
1118 /* cached hw enabled state */
1120 unsigned long domains;
1122 const struct i915_power_well_ops *ops;
1125 struct i915_power_domains {
1127 * Power wells needed for initialization at driver init and suspend
1128 * time are on. They are kept on until after the first modeset.
1132 int power_well_count;
1135 int domain_use_count[POWER_DOMAIN_NUM];
1136 struct i915_power_well *power_wells;
1139 #define MAX_L3_SLICES 2
1140 struct intel_l3_parity {
1141 u32 *remap_info[MAX_L3_SLICES];
1142 struct work_struct error_work;
1146 struct i915_gem_mm {
1147 /** Memory allocator for GTT stolen memory */
1148 struct drm_mm stolen;
1149 /** List of all objects in gtt_space. Used to restore gtt
1150 * mappings on resume */
1151 struct list_head bound_list;
1153 * List of objects which are not bound to the GTT (thus
1154 * are idle and not used by the GPU) but still have
1155 * (presumably uncached) pages still attached.
1157 struct list_head unbound_list;
1159 /** Usable portion of the GTT for GEM */
1160 unsigned long stolen_base; /* limited to low memory (32-bit) */
1162 /** PPGTT used for aliasing the PPGTT with the GTT */
1163 struct i915_hw_ppgtt *aliasing_ppgtt;
1165 struct notifier_block oom_notifier;
1166 struct shrinker shrinker;
1167 bool shrinker_no_lock_stealing;
1169 /** LRU list of objects with fence regs on them. */
1170 struct list_head fence_list;
1173 * We leave the user IRQ off as much as possible,
1174 * but this means that requests will finish and never
1175 * be retired once the system goes idle. Set a timer to
1176 * fire periodically while the ring is running. When it
1177 * fires, go retire requests.
1179 struct delayed_work retire_work;
1182 * When we detect an idle GPU, we want to turn on
1183 * powersaving features. So once we see that there
1184 * are no more requests outstanding and no more
1185 * arrive within a small period of time, we fire
1186 * off the idle_work.
1188 struct delayed_work idle_work;
1191 * Are we in a non-interruptible section of code like
1197 * Is the GPU currently considered idle, or busy executing userspace
1198 * requests? Whilst idle, we attempt to power down the hardware and
1199 * display clocks. In order to reduce the effect on performance, there
1200 * is a slight delay before we do so.
1204 /* the indicator for dispatch video commands on two BSD rings */
1205 int bsd_ring_dispatch_index;
1207 /** Bit 6 swizzling required for X tiling */
1208 uint32_t bit_6_swizzle_x;
1209 /** Bit 6 swizzling required for Y tiling */
1210 uint32_t bit_6_swizzle_y;
1212 /* accounting, useful for userland debugging */
1213 spinlock_t object_stat_lock;
1214 size_t object_memory;
1218 struct drm_i915_error_state_buf {
1219 struct drm_i915_private *i915;
1228 struct i915_error_state_file_priv {
1229 struct drm_device *dev;
1230 struct drm_i915_error_state *error;
1233 struct i915_gpu_error {
1234 /* For hangcheck timer */
1235 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1236 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1237 /* Hang gpu twice in this window and your context gets banned */
1238 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1240 struct workqueue_struct *hangcheck_wq;
1241 struct delayed_work hangcheck_work;
1243 /* For reset and error_state handling. */
1245 /* Protected by the above dev->gpu_error.lock. */
1246 struct drm_i915_error_state *first_error;
1248 unsigned long missed_irq_rings;
1251 * State variable controlling the reset flow and count
1253 * This is a counter which gets incremented when reset is triggered,
1254 * and again when reset has been handled. So odd values (lowest bit set)
1255 * means that reset is in progress and even values that
1256 * (reset_counter >> 1):th reset was successfully completed.
1258 * If reset is not completed succesfully, the I915_WEDGE bit is
1259 * set meaning that hardware is terminally sour and there is no
1260 * recovery. All waiters on the reset_queue will be woken when
1263 * This counter is used by the wait_seqno code to notice that reset
1264 * event happened and it needs to restart the entire ioctl (since most
1265 * likely the seqno it waited for won't ever signal anytime soon).
1267 * This is important for lock-free wait paths, where no contended lock
1268 * naturally enforces the correct ordering between the bail-out of the
1269 * waiter and the gpu reset work code.
1271 atomic_t reset_counter;
1273 #define I915_RESET_IN_PROGRESS_FLAG 1
1274 #define I915_WEDGED (1 << 31)
1277 * Waitqueue to signal when the reset has completed. Used by clients
1278 * that wait for dev_priv->mm.wedged to settle.
1280 wait_queue_head_t reset_queue;
1282 /* Userspace knobs for gpu hang simulation;
1283 * combines both a ring mask, and extra flags
1286 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1287 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1289 /* For missed irq/seqno simulation. */
1290 unsigned int test_irq_rings;
1292 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1293 bool reload_in_reset;
1296 enum modeset_restore {
1297 MODESET_ON_LID_OPEN,
1302 struct ddi_vbt_port_info {
1304 * This is an index in the HDMI/DVI DDI buffer translation table.
1305 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1306 * populate this field.
1308 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1309 uint8_t hdmi_level_shift;
1311 uint8_t supports_dvi:1;
1312 uint8_t supports_hdmi:1;
1313 uint8_t supports_dp:1;
1316 enum psr_lines_to_wait {
1317 PSR_0_LINES_TO_WAIT = 0,
1319 PSR_4_LINES_TO_WAIT,
1323 struct intel_vbt_data {
1324 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1325 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1328 unsigned int int_tv_support:1;
1329 unsigned int lvds_dither:1;
1330 unsigned int lvds_vbt:1;
1331 unsigned int int_crt_support:1;
1332 unsigned int lvds_use_ssc:1;
1333 unsigned int display_clock_mode:1;
1334 unsigned int fdi_rx_polarity_inverted:1;
1335 unsigned int has_mipi:1;
1337 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1339 enum drrs_support_type drrs_type;
1344 int edp_preemphasis;
1346 bool edp_initialized;
1349 bool edp_low_vswing;
1350 struct edp_power_seq edp_pps;
1354 bool require_aux_wakeup;
1356 enum psr_lines_to_wait lines_to_wait;
1357 int tp1_wakeup_time;
1358 int tp2_tp3_wakeup_time;
1364 bool active_low_pwm;
1365 u8 min_brightness; /* min_brightness/255 of max */
1372 struct mipi_config *config;
1373 struct mipi_pps_data *pps;
1377 u8 *sequence[MIPI_SEQ_MAX];
1383 union child_device_config *child_dev;
1385 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1388 enum intel_ddb_partitioning {
1390 INTEL_DDB_PART_5_6, /* IVB+ */
1393 struct intel_wm_level {
1401 struct ilk_wm_values {
1402 uint32_t wm_pipe[3];
1404 uint32_t wm_lp_spr[3];
1405 uint32_t wm_linetime[3];
1407 enum intel_ddb_partitioning partitioning;
1410 struct vlv_wm_values {
1429 struct skl_ddb_entry {
1430 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1433 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1435 return entry->end - entry->start;
1438 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1439 const struct skl_ddb_entry *e2)
1441 if (e1->start == e2->start && e1->end == e2->end)
1447 struct skl_ddb_allocation {
1448 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1449 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1450 struct skl_ddb_entry cursor[I915_MAX_PIPES];
1453 struct skl_wm_values {
1454 bool dirty[I915_MAX_PIPES];
1455 struct skl_ddb_allocation ddb;
1456 uint32_t wm_linetime[I915_MAX_PIPES];
1457 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1458 uint32_t cursor[I915_MAX_PIPES][8];
1459 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1460 uint32_t cursor_trans[I915_MAX_PIPES];
1463 struct skl_wm_level {
1464 bool plane_en[I915_MAX_PLANES];
1466 uint16_t plane_res_b[I915_MAX_PLANES];
1467 uint8_t plane_res_l[I915_MAX_PLANES];
1468 uint16_t cursor_res_b;
1469 uint8_t cursor_res_l;
1473 * This struct helps tracking the state needed for runtime PM, which puts the
1474 * device in PCI D3 state. Notice that when this happens, nothing on the
1475 * graphics device works, even register access, so we don't get interrupts nor
1478 * Every piece of our code that needs to actually touch the hardware needs to
1479 * either call intel_runtime_pm_get or call intel_display_power_get with the
1480 * appropriate power domain.
1482 * Our driver uses the autosuspend delay feature, which means we'll only really
1483 * suspend if we stay with zero refcount for a certain amount of time. The
1484 * default value is currently very conservative (see intel_runtime_pm_enable), but
1485 * it can be changed with the standard runtime PM files from sysfs.
1487 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1488 * goes back to false exactly before we reenable the IRQs. We use this variable
1489 * to check if someone is trying to enable/disable IRQs while they're supposed
1490 * to be disabled. This shouldn't happen and we'll print some error messages in
1493 * For more, read the Documentation/power/runtime_pm.txt.
1495 struct i915_runtime_pm {
1500 enum intel_pipe_crc_source {
1501 INTEL_PIPE_CRC_SOURCE_NONE,
1502 INTEL_PIPE_CRC_SOURCE_PLANE1,
1503 INTEL_PIPE_CRC_SOURCE_PLANE2,
1504 INTEL_PIPE_CRC_SOURCE_PF,
1505 INTEL_PIPE_CRC_SOURCE_PIPE,
1506 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1507 INTEL_PIPE_CRC_SOURCE_TV,
1508 INTEL_PIPE_CRC_SOURCE_DP_B,
1509 INTEL_PIPE_CRC_SOURCE_DP_C,
1510 INTEL_PIPE_CRC_SOURCE_DP_D,
1511 INTEL_PIPE_CRC_SOURCE_AUTO,
1512 INTEL_PIPE_CRC_SOURCE_MAX,
1515 struct intel_pipe_crc_entry {
1520 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1521 struct intel_pipe_crc {
1523 bool opened; /* exclusive access to the result file */
1524 struct intel_pipe_crc_entry *entries;
1525 enum intel_pipe_crc_source source;
1527 wait_queue_head_t wq;
1530 struct i915_frontbuffer_tracking {
1534 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1541 struct i915_wa_reg {
1544 /* bitmask representing WA bits */
1548 #define I915_MAX_WA_REGS 16
1550 struct i915_workarounds {
1551 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1555 struct i915_virtual_gpu {
1559 struct drm_i915_private {
1560 struct drm_device *dev;
1561 struct kmem_cache *objects;
1562 struct kmem_cache *vmas;
1563 struct kmem_cache *requests;
1565 const struct intel_device_info info;
1567 int relative_constants_mode;
1571 struct intel_uncore uncore;
1573 struct i915_virtual_gpu vgpu;
1575 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1577 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1578 * controller on different i2c buses. */
1579 struct mutex gmbus_mutex;
1582 * Base address of the gmbus and gpio block.
1584 uint32_t gpio_mmio_base;
1586 /* MMIO base address for MIPI regs */
1587 uint32_t mipi_mmio_base;
1589 wait_queue_head_t gmbus_wait_queue;
1591 struct pci_dev *bridge_dev;
1592 struct intel_engine_cs ring[I915_NUM_RINGS];
1593 struct drm_i915_gem_object *semaphore_obj;
1594 uint32_t last_seqno, next_seqno;
1596 struct drm_dma_handle *status_page_dmah;
1597 struct resource mch_res;
1599 /* protects the irq masks */
1600 spinlock_t irq_lock;
1602 /* protects the mmio flip data */
1603 spinlock_t mmio_flip_lock;
1605 bool display_irqs_enabled;
1607 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1608 struct pm_qos_request pm_qos;
1610 /* DPIO indirect register protection */
1611 struct mutex dpio_lock;
1613 /** Cached value of IMR to avoid reads in updating the bitfield */
1616 u32 de_irq_mask[I915_MAX_PIPES];
1621 u32 pipestat_irq_mask[I915_MAX_PIPES];
1623 struct work_struct hotplug_work;
1625 unsigned long hpd_last_jiffies;
1630 HPD_MARK_DISABLED = 2
1632 } hpd_stats[HPD_NUM_PINS];
1634 struct delayed_work hotplug_reenable_work;
1636 struct i915_fbc fbc;
1637 struct i915_drrs drrs;
1638 struct intel_opregion opregion;
1639 struct intel_vbt_data vbt;
1641 bool preserve_bios_swizzle;
1644 struct intel_overlay *overlay;
1646 /* backlight registers and fields in struct intel_panel */
1647 struct mutex backlight_lock;
1650 bool no_aux_handshake;
1652 /* protects panel power sequencer state */
1653 struct mutex pps_mutex;
1655 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1656 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1657 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1659 unsigned int fsb_freq, mem_freq, is_ddr3;
1660 unsigned int vlv_cdclk_freq;
1661 unsigned int hpll_freq;
1664 * wq - Driver workqueue for GEM.
1666 * NOTE: Work items scheduled here are not allowed to grab any modeset
1667 * locks, for otherwise the flushing done in the pageflip code will
1668 * result in deadlocks.
1670 struct workqueue_struct *wq;
1672 /* Display functions */
1673 struct drm_i915_display_funcs display;
1675 /* PCH chipset type */
1676 enum intel_pch pch_type;
1677 unsigned short pch_id;
1679 unsigned long quirks;
1681 enum modeset_restore modeset_restore;
1682 struct mutex modeset_restore_lock;
1684 struct list_head vm_list; /* Global list of all address spaces */
1685 struct i915_gtt gtt; /* VM representing the global address space */
1687 struct i915_gem_mm mm;
1688 DECLARE_HASHTABLE(mm_structs, 7);
1689 struct mutex mm_lock;
1691 /* Kernel Modesetting */
1693 struct sdvo_device_mapping sdvo_mappings[2];
1695 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1696 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1697 wait_queue_head_t pending_flip_queue;
1699 #ifdef CONFIG_DEBUG_FS
1700 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1703 int num_shared_dpll;
1704 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1705 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1707 struct i915_workarounds workarounds;
1709 /* Reclocking support */
1710 bool render_reclock_avail;
1711 bool lvds_downclock_avail;
1712 /* indicates the reduced downclock for LVDS*/
1715 struct i915_frontbuffer_tracking fb_tracking;
1719 bool mchbar_need_disable;
1721 struct intel_l3_parity l3_parity;
1723 /* Cannot be determined by PCIID. You must always read a register. */
1726 /* gen6+ rps state */
1727 struct intel_gen6_power_mgmt rps;
1729 /* ilk-only ips/rps state. Everything in here is protected by the global
1730 * mchdev_lock in intel_pm.c */
1731 struct intel_ilk_power_mgmt ips;
1733 struct i915_power_domains power_domains;
1735 struct i915_psr psr;
1737 struct i915_gpu_error gpu_error;
1739 struct drm_i915_gem_object *vlv_pctx;
1741 #ifdef CONFIG_DRM_I915_FBDEV
1742 /* list of fbdev register on this device */
1743 struct intel_fbdev *fbdev;
1744 struct work_struct fbdev_suspend_work;
1747 struct drm_property *broadcast_rgb_property;
1748 struct drm_property *force_audio_property;
1750 /* hda/i915 audio component */
1751 bool audio_component_registered;
1753 uint32_t hw_context_size;
1754 struct list_head context_list;
1759 struct i915_suspend_saved_registers regfile;
1760 struct vlv_s0ix_state vlv_s0ix_state;
1764 * Raw watermark latency values:
1765 * in 0.1us units for WM0,
1766 * in 0.5us units for WM1+.
1769 uint16_t pri_latency[5];
1771 uint16_t spr_latency[5];
1773 uint16_t cur_latency[5];
1775 * Raw watermark memory latency values
1776 * for SKL for all 8 levels
1779 uint16_t skl_latency[8];
1782 * The skl_wm_values structure is a bit too big for stack
1783 * allocation, so we keep the staging struct where we store
1784 * intermediate results here instead.
1786 struct skl_wm_values skl_results;
1788 /* current hardware state */
1790 struct ilk_wm_values hw;
1791 struct skl_wm_values skl_hw;
1792 struct vlv_wm_values vlv;
1796 struct i915_runtime_pm pm;
1798 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1799 u32 long_hpd_port_mask;
1800 u32 short_hpd_port_mask;
1801 struct work_struct dig_port_work;
1804 * if we get a HPD irq from DP and a HPD irq from non-DP
1805 * the non-DP HPD could block the workqueue on a mode config
1806 * mutex getting, that userspace may have taken. However
1807 * userspace is waiting on the DP workqueue to run which is
1808 * blocked behind the non-DP one.
1810 struct workqueue_struct *dp_wq;
1812 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1814 int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file,
1815 struct intel_engine_cs *ring,
1816 struct intel_context *ctx,
1817 struct drm_i915_gem_execbuffer2 *args,
1818 struct list_head *vmas,
1819 struct drm_i915_gem_object *batch_obj,
1820 u64 exec_start, u32 flags);
1821 int (*init_rings)(struct drm_device *dev);
1822 void (*cleanup_ring)(struct intel_engine_cs *ring);
1823 void (*stop_ring)(struct intel_engine_cs *ring);
1827 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1828 * will be rejected. Instead look for a better place.
1832 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1834 return dev->dev_private;
1837 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1839 return to_i915(dev_get_drvdata(dev));
1842 /* Iterate over initialised rings */
1843 #define for_each_ring(ring__, dev_priv__, i__) \
1844 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1845 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1847 enum hdmi_force_audio {
1848 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1849 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1850 HDMI_AUDIO_AUTO, /* trust EDID */
1851 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1854 #define I915_GTT_OFFSET_NONE ((u32)-1)
1856 struct drm_i915_gem_object_ops {
1857 /* Interface between the GEM object and its backing storage.
1858 * get_pages() is called once prior to the use of the associated set
1859 * of pages before to binding them into the GTT, and put_pages() is
1860 * called after we no longer need them. As we expect there to be
1861 * associated cost with migrating pages between the backing storage
1862 * and making them available for the GPU (e.g. clflush), we may hold
1863 * onto the pages after they are no longer referenced by the GPU
1864 * in case they may be used again shortly (for example migrating the
1865 * pages to a different memory domain within the GTT). put_pages()
1866 * will therefore most likely be called when the object itself is
1867 * being released or under memory pressure (where we attempt to
1868 * reap pages for the shrinker).
1870 int (*get_pages)(struct drm_i915_gem_object *);
1871 void (*put_pages)(struct drm_i915_gem_object *);
1872 int (*dmabuf_export)(struct drm_i915_gem_object *);
1873 void (*release)(struct drm_i915_gem_object *);
1877 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1878 * considered to be the frontbuffer for the given plane interface-vise. This
1879 * doesn't mean that the hw necessarily already scans it out, but that any
1880 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1882 * We have one bit per pipe and per scanout plane type.
1884 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1885 #define INTEL_FRONTBUFFER_BITS \
1886 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1887 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1888 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1889 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1890 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1891 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1892 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1893 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1894 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1895 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1896 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1898 struct drm_i915_gem_object {
1899 struct drm_gem_object base;
1901 const struct drm_i915_gem_object_ops *ops;
1903 /** List of VMAs backed by this object */
1904 struct list_head vma_list;
1906 /** Stolen memory for this object, instead of being backed by shmem. */
1907 struct drm_mm_node *stolen;
1908 struct list_head global_list;
1910 struct list_head ring_list;
1911 /** Used in execbuf to temporarily hold a ref */
1912 struct list_head obj_exec_link;
1914 struct list_head batch_pool_link;
1917 * This is set if the object is on the active lists (has pending
1918 * rendering and so a non-zero seqno), and is not set if it i s on
1919 * inactive (ready to be unbound) list.
1921 unsigned int active:1;
1924 * This is set if the object has been written to since last bound
1927 unsigned int dirty:1;
1930 * Fence register bits (if any) for this object. Will be set
1931 * as needed when mapped into the GTT.
1932 * Protected by dev->struct_mutex.
1934 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1937 * Advice: are the backing pages purgeable?
1939 unsigned int madv:2;
1942 * Current tiling mode for the object.
1944 unsigned int tiling_mode:2;
1946 * Whether the tiling parameters for the currently associated fence
1947 * register have changed. Note that for the purposes of tracking
1948 * tiling changes we also treat the unfenced register, the register
1949 * slot that the object occupies whilst it executes a fenced
1950 * command (such as BLT on gen2/3), as a "fence".
1952 unsigned int fence_dirty:1;
1955 * Is the object at the current location in the gtt mappable and
1956 * fenceable? Used to avoid costly recalculations.
1958 unsigned int map_and_fenceable:1;
1961 * Whether the current gtt mapping needs to be mappable (and isn't just
1962 * mappable by accident). Track pin and fault separate for a more
1963 * accurate mappable working set.
1965 unsigned int fault_mappable:1;
1966 unsigned int pin_display:1;
1969 * Is the object to be mapped as read-only to the GPU
1970 * Only honoured if hardware has relevant pte bit
1972 unsigned long gt_ro:1;
1973 unsigned int cache_level:3;
1974 unsigned int cache_dirty:1;
1976 unsigned int has_dma_mapping:1;
1978 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1980 struct sg_table *pages;
1981 int pages_pin_count;
1983 struct scatterlist *sg;
1987 /* prime dma-buf support */
1988 void *dma_buf_vmapping;
1991 /** Breadcrumb of last rendering to the buffer. */
1992 struct drm_i915_gem_request *last_read_req;
1993 struct drm_i915_gem_request *last_write_req;
1994 /** Breadcrumb of last fenced GPU access to the buffer. */
1995 struct drm_i915_gem_request *last_fenced_req;
1997 /** Current tiling stride for the object, if it's tiled. */
2000 /** References from framebuffers, locks out tiling changes. */
2001 unsigned long framebuffer_references;
2003 /** Record of address bit 17 of each page at last unbind. */
2004 unsigned long *bit_17;
2007 /** for phy allocated objects */
2008 struct drm_dma_handle *phys_handle;
2010 struct i915_gem_userptr {
2012 unsigned read_only :1;
2013 unsigned workers :4;
2014 #define I915_GEM_USERPTR_MAX_WORKERS 15
2016 struct i915_mm_struct *mm;
2017 struct i915_mmu_object *mmu_object;
2018 struct work_struct *work;
2022 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2024 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2025 struct drm_i915_gem_object *new,
2026 unsigned frontbuffer_bits);
2029 * Request queue structure.
2031 * The request queue allows us to note sequence numbers that have been emitted
2032 * and may be associated with active buffers to be retired.
2034 * By keeping this list, we can avoid having to do questionable sequence
2035 * number comparisons on buffer last_read|write_seqno. It also allows an
2036 * emission time to be associated with the request for tracking how far ahead
2037 * of the GPU the submission is.
2039 * The requests are reference counted, so upon creation they should have an
2040 * initial reference taken using kref_init
2042 struct drm_i915_gem_request {
2045 /** On Which ring this request was generated */
2046 struct drm_i915_private *i915;
2047 struct intel_engine_cs *ring;
2049 /** GEM sequence number associated with this request. */
2052 /** Position in the ringbuffer of the start of the request */
2056 * Position in the ringbuffer of the start of the postfix.
2057 * This is required to calculate the maximum available ringbuffer
2058 * space without overwriting the postfix.
2062 /** Position in the ringbuffer of the end of the whole request */
2066 * Context and ring buffer related to this request
2067 * Contexts are refcounted, so when this request is associated with a
2068 * context, we must increment the context's refcount, to guarantee that
2069 * it persists while any request is linked to it. Requests themselves
2070 * are also refcounted, so the request will only be freed when the last
2071 * reference to it is dismissed, and the code in
2072 * i915_gem_request_free() will then decrement the refcount on the
2075 struct intel_context *ctx;
2076 struct intel_ringbuffer *ringbuf;
2078 /** Batch buffer related to this request if any */
2079 struct drm_i915_gem_object *batch_obj;
2081 /** Time at which this request was emitted, in jiffies. */
2082 unsigned long emitted_jiffies;
2084 /** global list entry for this request */
2085 struct list_head list;
2087 struct drm_i915_file_private *file_priv;
2088 /** file_priv list entry for this request */
2089 struct list_head client_list;
2091 /** process identifier submitting this request */
2095 * The ELSP only accepts two elements at a time, so we queue
2096 * context/tail pairs on a given queue (ring->execlist_queue) until the
2097 * hardware is available. The queue serves a double purpose: we also use
2098 * it to keep track of the up to 2 contexts currently in the hardware
2099 * (usually one in execution and the other queued up by the GPU): We
2100 * only remove elements from the head of the queue when the hardware
2101 * informs us that an element has been completed.
2103 * All accesses to the queue are mediated by a spinlock
2104 * (ring->execlist_lock).
2107 /** Execlist link in the submission queue.*/
2108 struct list_head execlist_link;
2110 /** Execlists no. of times this request has been sent to the ELSP */
2115 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2116 struct intel_context *ctx);
2117 void i915_gem_request_free(struct kref *req_ref);
2119 static inline uint32_t
2120 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2122 return req ? req->seqno : 0;
2125 static inline struct intel_engine_cs *
2126 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2128 return req ? req->ring : NULL;
2132 i915_gem_request_reference(struct drm_i915_gem_request *req)
2134 kref_get(&req->ref);
2138 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2140 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2141 kref_put(&req->ref, i915_gem_request_free);
2145 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2147 struct drm_device *dev;
2152 dev = req->ring->dev;
2153 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2154 mutex_unlock(&dev->struct_mutex);
2157 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2158 struct drm_i915_gem_request *src)
2161 i915_gem_request_reference(src);
2164 i915_gem_request_unreference(*pdst);
2170 * XXX: i915_gem_request_completed should be here but currently needs the
2171 * definition of i915_seqno_passed() which is below. It will be moved in
2172 * a later patch when the call to i915_seqno_passed() is obsoleted...
2175 struct drm_i915_file_private {
2176 struct drm_i915_private *dev_priv;
2177 struct drm_file *file;
2181 struct list_head request_list;
2183 struct idr context_idr;
2185 struct list_head rps_boost;
2186 struct intel_engine_cs *bsd_ring;
2188 unsigned rps_boosts;
2192 * A command that requires special handling by the command parser.
2194 struct drm_i915_cmd_descriptor {
2196 * Flags describing how the command parser processes the command.
2198 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2199 * a length mask if not set
2200 * CMD_DESC_SKIP: The command is allowed but does not follow the
2201 * standard length encoding for the opcode range in
2203 * CMD_DESC_REJECT: The command is never allowed
2204 * CMD_DESC_REGISTER: The command should be checked against the
2205 * register whitelist for the appropriate ring
2206 * CMD_DESC_MASTER: The command is allowed if the submitting process
2210 #define CMD_DESC_FIXED (1<<0)
2211 #define CMD_DESC_SKIP (1<<1)
2212 #define CMD_DESC_REJECT (1<<2)
2213 #define CMD_DESC_REGISTER (1<<3)
2214 #define CMD_DESC_BITMASK (1<<4)
2215 #define CMD_DESC_MASTER (1<<5)
2218 * The command's unique identification bits and the bitmask to get them.
2219 * This isn't strictly the opcode field as defined in the spec and may
2220 * also include type, subtype, and/or subop fields.
2228 * The command's length. The command is either fixed length (i.e. does
2229 * not include a length field) or has a length field mask. The flag
2230 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2231 * a length mask. All command entries in a command table must include
2232 * length information.
2240 * Describes where to find a register address in the command to check
2241 * against the ring's register whitelist. Only valid if flags has the
2242 * CMD_DESC_REGISTER bit set.
2249 #define MAX_CMD_DESC_BITMASKS 3
2251 * Describes command checks where a particular dword is masked and
2252 * compared against an expected value. If the command does not match
2253 * the expected value, the parser rejects it. Only valid if flags has
2254 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2257 * If the check specifies a non-zero condition_mask then the parser
2258 * only performs the check when the bits specified by condition_mask
2265 u32 condition_offset;
2267 } bits[MAX_CMD_DESC_BITMASKS];
2271 * A table of commands requiring special handling by the command parser.
2273 * Each ring has an array of tables. Each table consists of an array of command
2274 * descriptors, which must be sorted with command opcodes in ascending order.
2276 struct drm_i915_cmd_table {
2277 const struct drm_i915_cmd_descriptor *table;
2281 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2282 #define __I915__(p) ({ \
2283 struct drm_i915_private *__p; \
2284 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2285 __p = (struct drm_i915_private *)p; \
2286 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2287 __p = to_i915((struct drm_device *)p); \
2292 #define INTEL_INFO(p) (&__I915__(p)->info)
2293 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2294 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2296 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2297 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2298 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2299 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2300 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2301 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2302 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2303 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2304 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2305 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2306 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2307 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2308 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2309 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2310 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2311 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2312 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2313 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2314 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2315 INTEL_DEVID(dev) == 0x0152 || \
2316 INTEL_DEVID(dev) == 0x015a)
2317 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2318 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2319 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2320 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2321 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2322 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2323 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2324 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2325 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2326 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2327 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2328 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2329 (INTEL_DEVID(dev) & 0xf) == 0xe))
2330 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2331 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2332 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2333 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2334 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2335 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2336 /* ULX machines are also considered ULT. */
2337 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2338 INTEL_DEVID(dev) == 0x0A1E)
2339 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2341 #define SKL_REVID_A0 (0x0)
2342 #define SKL_REVID_B0 (0x1)
2343 #define SKL_REVID_C0 (0x2)
2344 #define SKL_REVID_D0 (0x3)
2345 #define SKL_REVID_E0 (0x4)
2347 #define BXT_REVID_A0 (0x0)
2348 #define BXT_REVID_B0 (0x3)
2349 #define BXT_REVID_C0 (0x6)
2352 * The genX designation typically refers to the render engine, so render
2353 * capability related checks should use IS_GEN, while display and other checks
2354 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2357 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2358 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2359 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2360 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2361 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2362 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2363 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2364 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2366 #define RENDER_RING (1<<RCS)
2367 #define BSD_RING (1<<VCS)
2368 #define BLT_RING (1<<BCS)
2369 #define VEBOX_RING (1<<VECS)
2370 #define BSD2_RING (1<<VCS2)
2371 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2372 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2373 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2374 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2375 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2376 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2377 __I915__(dev)->ellc_size)
2378 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2380 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2381 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2382 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2383 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2385 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2386 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2388 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2389 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2391 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2392 * even when in MSI mode. This results in spurious interrupt warnings if the
2393 * legacy irq no. is shared with another device. The kernel then disables that
2394 * interrupt source and so prevents the other device from working properly.
2396 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2397 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2399 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2400 * rows, which changed the alignment requirements and fence programming.
2402 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2404 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2405 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2406 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2407 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2408 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2410 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2411 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2412 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2414 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2416 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2417 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2418 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2419 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2421 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2422 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2423 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2424 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2426 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2427 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2428 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2429 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2430 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2431 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2432 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2433 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2435 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2436 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2437 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2438 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2439 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2440 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2441 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2443 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2445 /* DPF == dynamic parity feature */
2446 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2447 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2449 #define GT_FREQUENCY_MULTIPLIER 50
2450 #define GEN9_FREQ_SCALER 3
2452 #include "i915_trace.h"
2454 extern const struct drm_ioctl_desc i915_ioctls[];
2455 extern int i915_max_ioctl;
2457 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2458 extern int i915_resume_legacy(struct drm_device *dev);
2461 struct i915_params {
2463 int panel_ignore_lid;
2465 unsigned int lvds_downclock;
2466 int lvds_channel_mode;
2468 int vbt_sdvo_panel_type;
2472 int enable_execlists;
2474 unsigned int preliminary_hw_support;
2475 int disable_power_well;
2477 int invert_brightness;
2478 int enable_cmd_parser;
2479 /* leave bools at the end to not create holes */
2480 bool enable_hangcheck;
2482 bool prefault_disable;
2483 bool load_detect_test;
2485 bool disable_display;
2486 bool disable_vtd_wa;
2489 bool verbose_state_checks;
2490 bool nuclear_pageflip;
2492 extern struct i915_params i915 __read_mostly;
2495 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2496 extern int i915_driver_unload(struct drm_device *);
2497 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2498 extern void i915_driver_lastclose(struct drm_device * dev);
2499 extern void i915_driver_preclose(struct drm_device *dev,
2500 struct drm_file *file);
2501 extern void i915_driver_postclose(struct drm_device *dev,
2502 struct drm_file *file);
2503 extern int i915_driver_device_is_agp(struct drm_device * dev);
2504 #ifdef CONFIG_COMPAT
2505 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2508 extern int intel_gpu_reset(struct drm_device *dev);
2509 extern int i915_reset(struct drm_device *dev);
2510 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2511 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2512 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2513 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2514 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2515 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2518 void i915_queue_hangcheck(struct drm_device *dev);
2520 void i915_handle_error(struct drm_device *dev, bool wedged,
2521 const char *fmt, ...);
2523 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2524 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2525 int intel_irq_install(struct drm_i915_private *dev_priv);
2526 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2528 extern void intel_uncore_sanitize(struct drm_device *dev);
2529 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2530 bool restore_forcewake);
2531 extern void intel_uncore_init(struct drm_device *dev);
2532 extern void intel_uncore_check_errors(struct drm_device *dev);
2533 extern void intel_uncore_fini(struct drm_device *dev);
2534 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2535 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2536 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2537 enum forcewake_domains domains);
2538 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2539 enum forcewake_domains domains);
2540 /* Like above but the caller must manage the uncore.lock itself.
2541 * Must be used with I915_READ_FW and friends.
2543 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2544 enum forcewake_domains domains);
2545 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2546 enum forcewake_domains domains);
2547 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2548 static inline bool intel_vgpu_active(struct drm_device *dev)
2550 return to_i915(dev)->vgpu.active;
2554 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2558 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2561 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2562 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2564 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2566 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2567 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2568 uint32_t interrupt_mask,
2569 uint32_t enabled_irq_mask);
2570 #define ibx_enable_display_interrupt(dev_priv, bits) \
2571 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2572 #define ibx_disable_display_interrupt(dev_priv, bits) \
2573 ibx_display_interrupt_update((dev_priv), (bits), 0)
2576 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2577 struct drm_file *file_priv);
2578 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2579 struct drm_file *file_priv);
2580 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2581 struct drm_file *file_priv);
2582 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2583 struct drm_file *file_priv);
2584 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2585 struct drm_file *file_priv);
2586 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2587 struct drm_file *file_priv);
2588 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2589 struct drm_file *file_priv);
2590 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2591 struct intel_engine_cs *ring);
2592 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2593 struct drm_file *file,
2594 struct intel_engine_cs *ring,
2595 struct drm_i915_gem_object *obj);
2596 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2597 struct drm_file *file,
2598 struct intel_engine_cs *ring,
2599 struct intel_context *ctx,
2600 struct drm_i915_gem_execbuffer2 *args,
2601 struct list_head *vmas,
2602 struct drm_i915_gem_object *batch_obj,
2603 u64 exec_start, u32 flags);
2604 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2605 struct drm_file *file_priv);
2606 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2607 struct drm_file *file_priv);
2608 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2609 struct drm_file *file_priv);
2610 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2611 struct drm_file *file);
2612 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2613 struct drm_file *file);
2614 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2615 struct drm_file *file_priv);
2616 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2617 struct drm_file *file_priv);
2618 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2619 struct drm_file *file_priv);
2620 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2621 struct drm_file *file_priv);
2622 int i915_gem_init_userptr(struct drm_device *dev);
2623 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2624 struct drm_file *file);
2625 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2626 struct drm_file *file_priv);
2627 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2628 struct drm_file *file_priv);
2629 void i915_gem_load(struct drm_device *dev);
2630 void *i915_gem_object_alloc(struct drm_device *dev);
2631 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2632 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2633 const struct drm_i915_gem_object_ops *ops);
2634 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2636 void i915_init_vm(struct drm_i915_private *dev_priv,
2637 struct i915_address_space *vm);
2638 void i915_gem_free_object(struct drm_gem_object *obj);
2639 void i915_gem_vma_destroy(struct i915_vma *vma);
2641 #define PIN_MAPPABLE 0x1
2642 #define PIN_NONBLOCK 0x2
2643 #define PIN_GLOBAL 0x4
2644 #define PIN_OFFSET_BIAS 0x8
2645 #define PIN_OFFSET_MASK (~4095)
2647 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2648 struct i915_address_space *vm,
2652 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2653 const struct i915_ggtt_view *view,
2657 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2659 int __must_check i915_vma_unbind(struct i915_vma *vma);
2660 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2661 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2662 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2664 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2665 int *needs_clflush);
2667 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2669 static inline int __sg_page_count(struct scatterlist *sg)
2671 return sg->length >> PAGE_SHIFT;
2674 static inline struct page *
2675 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2677 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2680 if (n < obj->get_page.last) {
2681 obj->get_page.sg = obj->pages->sgl;
2682 obj->get_page.last = 0;
2685 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2686 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2687 if (unlikely(sg_is_chain(obj->get_page.sg)))
2688 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2691 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2694 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2696 BUG_ON(obj->pages == NULL);
2697 obj->pages_pin_count++;
2699 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2701 BUG_ON(obj->pages_pin_count == 0);
2702 obj->pages_pin_count--;
2705 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2706 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2707 struct intel_engine_cs *to);
2708 void i915_vma_move_to_active(struct i915_vma *vma,
2709 struct intel_engine_cs *ring);
2710 int i915_gem_dumb_create(struct drm_file *file_priv,
2711 struct drm_device *dev,
2712 struct drm_mode_create_dumb *args);
2713 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2714 uint32_t handle, uint64_t *offset);
2716 * Returns true if seq1 is later than seq2.
2719 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2721 return (int32_t)(seq1 - seq2) >= 0;
2724 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2725 bool lazy_coherency)
2729 BUG_ON(req == NULL);
2731 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2733 return i915_seqno_passed(seqno, req->seqno);
2736 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2737 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2738 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2739 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2741 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2742 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2744 struct drm_i915_gem_request *
2745 i915_gem_find_active_request(struct intel_engine_cs *ring);
2747 bool i915_gem_retire_requests(struct drm_device *dev);
2748 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2749 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2750 bool interruptible);
2751 int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req);
2753 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2755 return unlikely(atomic_read(&error->reset_counter)
2756 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2759 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2761 return atomic_read(&error->reset_counter) & I915_WEDGED;
2764 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2766 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2769 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2771 return dev_priv->gpu_error.stop_rings == 0 ||
2772 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2775 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2777 return dev_priv->gpu_error.stop_rings == 0 ||
2778 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2781 void i915_gem_reset(struct drm_device *dev);
2782 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2783 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2784 int __must_check i915_gem_init(struct drm_device *dev);
2785 int i915_gem_init_rings(struct drm_device *dev);
2786 int __must_check i915_gem_init_hw(struct drm_device *dev);
2787 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2788 void i915_gem_init_swizzling(struct drm_device *dev);
2789 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2790 int __must_check i915_gpu_idle(struct drm_device *dev);
2791 int __must_check i915_gem_suspend(struct drm_device *dev);
2792 int __i915_add_request(struct intel_engine_cs *ring,
2793 struct drm_file *file,
2794 struct drm_i915_gem_object *batch_obj);
2795 #define i915_add_request(ring) \
2796 __i915_add_request(ring, NULL, NULL)
2797 int __i915_wait_request(struct drm_i915_gem_request *req,
2798 unsigned reset_counter,
2801 struct drm_i915_file_private *file_priv);
2802 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
2803 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2805 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2808 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2810 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2812 struct intel_engine_cs *pipelined,
2813 const struct i915_ggtt_view *view);
2814 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
2815 const struct i915_ggtt_view *view);
2816 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2818 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2819 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2822 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2824 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2825 int tiling_mode, bool fenced);
2827 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2828 enum i915_cache_level cache_level);
2830 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2831 struct dma_buf *dma_buf);
2833 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2834 struct drm_gem_object *gem_obj, int flags);
2836 void i915_gem_restore_fences(struct drm_device *dev);
2839 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
2840 const struct i915_ggtt_view *view);
2842 i915_gem_obj_offset(struct drm_i915_gem_object *o,
2843 struct i915_address_space *vm);
2844 static inline unsigned long
2845 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
2847 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
2850 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2851 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
2852 const struct i915_ggtt_view *view);
2853 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2854 struct i915_address_space *vm);
2856 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2857 struct i915_address_space *vm);
2859 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2860 struct i915_address_space *vm);
2862 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
2863 const struct i915_ggtt_view *view);
2866 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2867 struct i915_address_space *vm);
2869 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2870 const struct i915_ggtt_view *view);
2872 static inline struct i915_vma *
2873 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
2875 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
2877 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
2879 /* Some GGTT VM helpers */
2880 #define i915_obj_to_ggtt(obj) \
2881 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2882 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2884 struct i915_address_space *ggtt =
2885 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2889 static inline struct i915_hw_ppgtt *
2890 i915_vm_to_ppgtt(struct i915_address_space *vm)
2892 WARN_ON(i915_is_ggtt(vm));
2894 return container_of(vm, struct i915_hw_ppgtt, base);
2898 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2900 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
2903 static inline unsigned long
2904 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2906 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2909 static inline int __must_check
2910 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2914 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2915 alignment, flags | PIN_GLOBAL);
2919 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2921 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2924 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
2925 const struct i915_ggtt_view *view);
2927 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
2929 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
2932 /* i915_gem_context.c */
2933 int __must_check i915_gem_context_init(struct drm_device *dev);
2934 void i915_gem_context_fini(struct drm_device *dev);
2935 void i915_gem_context_reset(struct drm_device *dev);
2936 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2937 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2938 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2939 int i915_switch_context(struct intel_engine_cs *ring,
2940 struct intel_context *to);
2941 struct intel_context *
2942 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2943 void i915_gem_context_free(struct kref *ctx_ref);
2944 struct drm_i915_gem_object *
2945 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2946 static inline void i915_gem_context_reference(struct intel_context *ctx)
2948 kref_get(&ctx->ref);
2951 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2953 kref_put(&ctx->ref, i915_gem_context_free);
2956 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2958 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2961 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2962 struct drm_file *file);
2963 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2964 struct drm_file *file);
2965 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
2966 struct drm_file *file_priv);
2967 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
2968 struct drm_file *file_priv);
2970 /* i915_gem_evict.c */
2971 int __must_check i915_gem_evict_something(struct drm_device *dev,
2972 struct i915_address_space *vm,
2975 unsigned cache_level,
2976 unsigned long start,
2979 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2980 int i915_gem_evict_everything(struct drm_device *dev);
2982 /* belongs in i915_gem_gtt.h */
2983 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2985 if (INTEL_INFO(dev)->gen < 6)
2986 intel_gtt_chipset_flush();
2989 /* i915_gem_stolen.c */
2990 int i915_gem_init_stolen(struct drm_device *dev);
2991 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2992 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2993 void i915_gem_cleanup_stolen(struct drm_device *dev);
2994 struct drm_i915_gem_object *
2995 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2996 struct drm_i915_gem_object *
2997 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3002 /* i915_gem_shrinker.c */
3003 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3006 #define I915_SHRINK_PURGEABLE 0x1
3007 #define I915_SHRINK_UNBOUND 0x2
3008 #define I915_SHRINK_BOUND 0x4
3009 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3010 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3013 /* i915_gem_tiling.c */
3014 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3016 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3018 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3019 obj->tiling_mode != I915_TILING_NONE;
3022 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3023 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3024 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3026 /* i915_gem_debug.c */
3028 int i915_verify_lists(struct drm_device *dev);
3030 #define i915_verify_lists(dev) 0
3033 /* i915_debugfs.c */
3034 int i915_debugfs_init(struct drm_minor *minor);
3035 void i915_debugfs_cleanup(struct drm_minor *minor);
3036 #ifdef CONFIG_DEBUG_FS
3037 int i915_debugfs_connector_add(struct drm_connector *connector);
3038 void intel_display_crc_init(struct drm_device *dev);
3040 static inline int i915_debugfs_connector_add(struct drm_connector *connector) {}
3041 static inline void intel_display_crc_init(struct drm_device *dev) {}
3044 /* i915_gpu_error.c */
3046 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3047 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3048 const struct i915_error_state_file_priv *error);
3049 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3050 struct drm_i915_private *i915,
3051 size_t count, loff_t pos);
3052 static inline void i915_error_state_buf_release(
3053 struct drm_i915_error_state_buf *eb)
3057 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3058 const char *error_msg);
3059 void i915_error_state_get(struct drm_device *dev,
3060 struct i915_error_state_file_priv *error_priv);
3061 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3062 void i915_destroy_error_state(struct drm_device *dev);
3064 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3065 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3067 /* i915_cmd_parser.c */
3068 int i915_cmd_parser_get_version(void);
3069 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3070 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3071 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3072 int i915_parse_cmds(struct intel_engine_cs *ring,
3073 struct drm_i915_gem_object *batch_obj,
3074 struct drm_i915_gem_object *shadow_batch_obj,
3075 u32 batch_start_offset,
3079 /* i915_suspend.c */
3080 extern int i915_save_state(struct drm_device *dev);
3081 extern int i915_restore_state(struct drm_device *dev);
3084 void i915_setup_sysfs(struct drm_device *dev_priv);
3085 void i915_teardown_sysfs(struct drm_device *dev_priv);
3088 extern int intel_setup_gmbus(struct drm_device *dev);
3089 extern void intel_teardown_gmbus(struct drm_device *dev);
3090 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3093 extern struct i2c_adapter *
3094 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3095 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3096 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3097 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3099 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3101 extern void intel_i2c_reset(struct drm_device *dev);
3103 /* intel_opregion.c */
3105 extern int intel_opregion_setup(struct drm_device *dev);
3106 extern void intel_opregion_init(struct drm_device *dev);
3107 extern void intel_opregion_fini(struct drm_device *dev);
3108 extern void intel_opregion_asle_intr(struct drm_device *dev);
3109 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3111 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3114 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3115 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3116 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3117 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3119 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3124 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3132 extern void intel_register_dsm_handler(void);
3133 extern void intel_unregister_dsm_handler(void);
3135 static inline void intel_register_dsm_handler(void) { return; }
3136 static inline void intel_unregister_dsm_handler(void) { return; }
3137 #endif /* CONFIG_ACPI */
3140 extern void intel_modeset_init_hw(struct drm_device *dev);
3141 extern void intel_modeset_init(struct drm_device *dev);
3142 extern void intel_modeset_gem_init(struct drm_device *dev);
3143 extern void intel_modeset_cleanup(struct drm_device *dev);
3144 extern void intel_connector_unregister(struct intel_connector *);
3145 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3146 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
3147 bool force_restore);
3148 extern void i915_redisable_vga(struct drm_device *dev);
3149 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3150 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3151 extern void intel_init_pch_refclk(struct drm_device *dev);
3152 extern void intel_set_rps(struct drm_device *dev, u8 val);
3153 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3155 extern void intel_detect_pch(struct drm_device *dev);
3156 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
3157 extern int intel_enable_rc6(const struct drm_device *dev);
3159 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3160 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3161 struct drm_file *file);
3162 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3163 struct drm_file *file);
3166 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3167 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3168 struct intel_overlay_error_state *error);
3170 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3171 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3172 struct drm_device *dev,
3173 struct intel_display_error_state *error);
3175 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3176 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3178 /* intel_sideband.c */
3179 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3180 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3181 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3182 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3183 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3184 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3185 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3186 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3187 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3188 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3189 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3190 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3191 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3192 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3193 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3194 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3195 enum intel_sbi_destination destination);
3196 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3197 enum intel_sbi_destination destination);
3198 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3199 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3201 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3202 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3204 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3205 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3207 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3208 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3209 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3210 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3212 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3213 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3214 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3215 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3217 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3218 * will be implemented using 2 32-bit writes in an arbitrary order with
3219 * an arbitrary delay between them. This can cause the hardware to
3220 * act upon the intermediate value, possibly leading to corruption and
3221 * machine death. You have been warned.
3223 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3224 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3226 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3227 u32 upper = I915_READ(upper_reg); \
3228 u32 lower = I915_READ(lower_reg); \
3229 u32 tmp = I915_READ(upper_reg); \
3230 if (upper != tmp) { \
3232 lower = I915_READ(lower_reg); \
3233 WARN_ON(I915_READ(upper_reg) != upper); \
3235 (u64)upper << 32 | lower; })
3237 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3238 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3240 /* These are untraced mmio-accessors that are only valid to be used inside
3241 * criticial sections inside IRQ handlers where forcewake is explicitly
3243 * Think twice, and think again, before using these.
3244 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3245 * intel_uncore_forcewake_irqunlock().
3247 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3248 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3249 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3251 /* "Broadcast RGB" property */
3252 #define INTEL_BROADCAST_RGB_AUTO 0
3253 #define INTEL_BROADCAST_RGB_FULL 1
3254 #define INTEL_BROADCAST_RGB_LIMITED 2
3256 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3258 if (IS_VALLEYVIEW(dev))
3259 return VLV_VGACNTRL;
3260 else if (INTEL_INFO(dev)->gen >= 5)
3261 return CPU_VGACNTRL;
3266 static inline void __user *to_user_ptr(u64 address)
3268 return (void __user *)(uintptr_t)address;
3271 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3273 unsigned long j = msecs_to_jiffies(m);
3275 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3278 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3280 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3283 static inline unsigned long
3284 timespec_to_jiffies_timeout(const struct timespec *value)
3286 unsigned long j = timespec_to_jiffies(value);
3288 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3292 * If you need to wait X milliseconds between events A and B, but event B
3293 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3294 * when event A happened, then just before event B you call this function and
3295 * pass the timestamp as the first argument, and X as the second argument.
3298 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3300 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3303 * Don't re-read the value of "jiffies" every time since it may change
3304 * behind our back and break the math.
3306 tmp_jiffies = jiffies;
3307 target_jiffies = timestamp_jiffies +
3308 msecs_to_jiffies_timeout(to_wait_ms);
3310 if (time_after(target_jiffies, tmp_jiffies)) {
3311 remaining_jiffies = target_jiffies - tmp_jiffies;
3312 while (remaining_jiffies)
3314 schedule_timeout_uninterruptible(remaining_jiffies);
3318 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3319 struct drm_i915_gem_request *req)
3321 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3322 i915_gem_request_assign(&ring->trace_irq_req, req);