drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include "intel_mocs.h"
  36 #include <linux/shmem_fs.h>
  37 #include <linux/slab.h>
  38 #include <linux/swap.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-buf.h>
  41
  42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  44 static void
  45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
  46 static void
  47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
  48
  49 static bool cpu_cache_is_coherent(struct drm_device *dev,
  50                                   enum i915_cache_level level)
  51 {
  52         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  53 }
  54
  55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  56 {
  57         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
  58                 return false;
  59
  60         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  61                 return true;
  62
  63         return obj->pin_display;
  64 }
  65
  66 static int
  67 insert_mappable_node(struct drm_i915_private *i915,
  68                      struct drm_mm_node *node, u32 size)
  69 {
  70         memset(node, 0, sizeof(*node));
  71         return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node,
  72                                                    size, 0, 0, 0,
  73                                                    i915->ggtt.mappable_end,
  74                                                    DRM_MM_SEARCH_DEFAULT,
  75                                                    DRM_MM_CREATE_DEFAULT);
  76 }
  77
  78 static void
  79 remove_mappable_node(struct drm_mm_node *node)
  80 {
  81         drm_mm_remove_node(node);
  82 }
  83
  84 /* some bookkeeping */
  85 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  86                                   size_t size)
  87 {
  88         spin_lock(&dev_priv->mm.object_stat_lock);
  89         dev_priv->mm.object_count++;
  90         dev_priv->mm.object_memory += size;
  91         spin_unlock(&dev_priv->mm.object_stat_lock);
  92 }
  93
  94 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  95                                      size_t size)
  96 {
  97         spin_lock(&dev_priv->mm.object_stat_lock);
  98         dev_priv->mm.object_count--;
  99         dev_priv->mm.object_memory -= size;
 100         spin_unlock(&dev_priv->mm.object_stat_lock);
 101 }
 102
 103 static int
 104 i915_gem_wait_for_error(struct i915_gpu_error *error)
 105 {
 106         int ret;
 107
 108         if (!i915_reset_in_progress(error))
 109                 return 0;
 110
 111         /*
 112          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 113          * userspace. If it takes that long something really bad is going on and
 114          * we should simply try to bail out and fail as gracefully as possible.
 115          */
 116         ret = wait_event_interruptible_timeout(error->reset_queue,
 117                                                !i915_reset_in_progress(error),
 118                                                10*HZ);
 119         if (ret == 0) {
 120                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 121                 return -EIO;
 122         } else if (ret < 0) {
 123                 return ret;
 124         } else {
 125                 return 0;
 126         }
 127 }
 128
 129 int i915_mutex_lock_interruptible(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132         int ret;
 133
 134         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 135         if (ret)
 136                 return ret;
 137
 138         ret = mutex_lock_interruptible(&dev->struct_mutex);
 139         if (ret)
 140                 return ret;
 141
 142         WARN_ON(i915_verify_lists(dev));
 143         return 0;
 144 }
 145
 146 int
 147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 148                             struct drm_file *file)
 149 {
 150         struct drm_i915_private *dev_priv = to_i915(dev);
 151         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 152         struct drm_i915_gem_get_aperture *args = data;
 153         struct i915_vma *vma;
 154         size_t pinned;
 155
 156         pinned = 0;
 157         mutex_lock(&dev->struct_mutex);
 158         list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
 159                 if (vma->pin_count)
 160                         pinned += vma->node.size;
 161         list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
 162                 if (vma->pin_count)
 163                         pinned += vma->node.size;
 164         mutex_unlock(&dev->struct_mutex);
 165
 166         args->aper_size = ggtt->base.total;
 167         args->aper_available_size = args->aper_size - pinned;
 168
 169         return 0;
 170 }
 171
 172 static int
 173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 174 {
 175         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 176         char *vaddr = obj->phys_handle->vaddr;
 177         struct sg_table *st;
 178         struct scatterlist *sg;
 179         int i;
 180
 181         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 182                 return -EINVAL;
 183
 184         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 185                 struct page *page;
 186                 char *src;
 187
 188                 page = shmem_read_mapping_page(mapping, i);
 189                 if (IS_ERR(page))
 190                         return PTR_ERR(page);
 191
 192                 src = kmap_atomic(page);
 193                 memcpy(vaddr, src, PAGE_SIZE);
 194                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 195                 kunmap_atomic(src);
 196
 197                 put_page(page);
 198                 vaddr += PAGE_SIZE;
 199         }
 200
 201         i915_gem_chipset_flush(to_i915(obj->base.dev));
 202
 203         st = kmalloc(sizeof(*st), GFP_KERNEL);
 204         if (st == NULL)
 205                 return -ENOMEM;
 206
 207         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 208                 kfree(st);
 209                 return -ENOMEM;
 210         }
 211
 212         sg = st->sgl;
 213         sg->offset = 0;
 214         sg->length = obj->base.size;
 215
 216         sg_dma_address(sg) = obj->phys_handle->busaddr;
 217         sg_dma_len(sg) = obj->base.size;
 218
 219         obj->pages = st;
 220         return 0;
 221 }
 222
 223 static void
 224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 225 {
 226         int ret;
 227
 228         BUG_ON(obj->madv == __I915_MADV_PURGED);
 229
 230         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 231         if (WARN_ON(ret)) {
 232                 /* In the event of a disaster, abandon all caches and
 233                  * hope for the best.
 234                  */
 235                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 236         }
 237
 238         if (obj->madv == I915_MADV_DONTNEED)
 239                 obj->dirty = 0;
 240
 241         if (obj->dirty) {
 242                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 243                 char *vaddr = obj->phys_handle->vaddr;
 244                 int i;
 245
 246                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 247                         struct page *page;
 248                         char *dst;
 249
 250                         page = shmem_read_mapping_page(mapping, i);
 251                         if (IS_ERR(page))
 252                                 continue;
 253
 254                         dst = kmap_atomic(page);
 255                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 256                         memcpy(dst, vaddr, PAGE_SIZE);
 257                         kunmap_atomic(dst);
 258
 259                         set_page_dirty(page);
 260                         if (obj->madv == I915_MADV_WILLNEED)
 261                                 mark_page_accessed(page);
 262                         put_page(page);
 263                         vaddr += PAGE_SIZE;
 264                 }
 265                 obj->dirty = 0;
 266         }
 267
 268         sg_free_table(obj->pages);
 269         kfree(obj->pages);
 270 }
 271
 272 static void
 273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 274 {
 275         drm_pci_free(obj->base.dev, obj->phys_handle);
 276 }
 277
 278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 279         .get_pages = i915_gem_object_get_pages_phys,
 280         .put_pages = i915_gem_object_put_pages_phys,
 281         .release = i915_gem_object_release_phys,
 282 };
 283
 284 static int
 285 drop_pages(struct drm_i915_gem_object *obj)
 286 {
 287         struct i915_vma *vma, *next;
 288         int ret;
 289
 290         drm_gem_object_reference(&obj->base);
 291         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
 292                 if (i915_vma_unbind(vma))
 293                         break;
 294
 295         ret = i915_gem_object_put_pages(obj);
 296         drm_gem_object_unreference(&obj->base);
 297
 298         return ret;
 299 }
 300
 301 int
 302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 303                             int align)
 304 {
 305         drm_dma_handle_t *phys;
 306         int ret;
 307
 308         if (obj->phys_handle) {
 309                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 310                         return -EBUSY;
 311
 312                 return 0;
 313         }
 314
 315         if (obj->madv != I915_MADV_WILLNEED)
 316                 return -EFAULT;
 317
 318         if (obj->base.filp == NULL)
 319                 return -EINVAL;
 320
 321         ret = drop_pages(obj);
 322         if (ret)
 323                 return ret;
 324
 325         /* create a new object */
 326         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 327         if (!phys)
 328                 return -ENOMEM;
 329
 330         obj->phys_handle = phys;
 331         obj->ops = &i915_gem_phys_ops;
 332
 333         return i915_gem_object_get_pages(obj);
 334 }
 335
 336 static int
 337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 338                      struct drm_i915_gem_pwrite *args,
 339                      struct drm_file *file_priv)
 340 {
 341         struct drm_device *dev = obj->base.dev;
 342         void *vaddr = obj->phys_handle->vaddr + args->offset;
 343         char __user *user_data = u64_to_user_ptr(args->data_ptr);
 344         int ret = 0;
 345
 346         /* We manually control the domain here and pretend that it
 347          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 348          */
 349         ret = i915_gem_object_wait_rendering(obj, false);
 350         if (ret)
 351                 return ret;
 352
 353         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 354         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 355                 unsigned long unwritten;
 356
 357                 /* The physical object once assigned is fixed for the lifetime
 358                  * of the obj, so we can safely drop the lock and continue
 359                  * to access vaddr.
 360                  */
 361                 mutex_unlock(&dev->struct_mutex);
 362                 unwritten = copy_from_user(vaddr, user_data, args->size);
 363                 mutex_lock(&dev->struct_mutex);
 364                 if (unwritten) {
 365                         ret = -EFAULT;
 366                         goto out;
 367                 }
 368         }
 369
 370         drm_clflush_virt_range(vaddr, args->size);
 371         i915_gem_chipset_flush(to_i915(dev));
 372
 373 out:
 374         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
 375         return ret;
 376 }
 377
 378 void *i915_gem_object_alloc(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 382 }
 383
 384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 385 {
 386         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 387         kmem_cache_free(dev_priv->objects, obj);
 388 }
 389
 390 static int
 391 i915_gem_create(struct drm_file *file,
 392                 struct drm_device *dev,
 393                 uint64_t size,
 394                 uint32_t *handle_p)
 395 {
 396         struct drm_i915_gem_object *obj;
 397         int ret;
 398         u32 handle;
 399
 400         size = roundup(size, PAGE_SIZE);
 401         if (size == 0)
 402                 return -EINVAL;
 403
 404         /* Allocate the new object */
 405         obj = i915_gem_object_create(dev, size);
 406         if (IS_ERR(obj))
 407                 return PTR_ERR(obj);
 408
 409         ret = drm_gem_handle_create(file, &obj->base, &handle);
 410         /* drop reference from allocate - handle holds it now */
 411         drm_gem_object_unreference_unlocked(&obj->base);
 412         if (ret)
 413                 return ret;
 414
 415         *handle_p = handle;
 416         return 0;
 417 }
 418
 419 int
 420 i915_gem_dumb_create(struct drm_file *file,
 421                      struct drm_device *dev,
 422                      struct drm_mode_create_dumb *args)
 423 {
 424         /* have to work out size/pitch and return them */
 425         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 426         args->size = args->pitch * args->height;
 427         return i915_gem_create(file, dev,
 428                                args->size, &args->handle);
 429 }
 430
 431 /**
 432  * Creates a new mm object and returns a handle to it.
 433  * @dev: drm device pointer
 434  * @data: ioctl data blob
 435  * @file: drm file pointer
 436  */
 437 int
 438 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 439                       struct drm_file *file)
 440 {
 441         struct drm_i915_gem_create *args = data;
 442
 443         return i915_gem_create(file, dev,
 444                                args->size, &args->handle);
 445 }
 446
 447 static inline int
 448 __copy_to_user_swizzled(char __user *cpu_vaddr,
 449                         const char *gpu_vaddr, int gpu_offset,
 450                         int length)
 451 {
 452         int ret, cpu_offset = 0;
 453
 454         while (length > 0) {
 455                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 456                 int this_length = min(cacheline_end - gpu_offset, length);
 457                 int swizzled_gpu_offset = gpu_offset ^ 64;
 458
 459                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 460                                      gpu_vaddr + swizzled_gpu_offset,
 461                                      this_length);
 462                 if (ret)
 463                         return ret + length;
 464
 465                 cpu_offset += this_length;
 466                 gpu_offset += this_length;
 467                 length -= this_length;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static inline int
 474 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 475                           const char __user *cpu_vaddr,
 476                           int length)
 477 {
 478         int ret, cpu_offset = 0;
 479
 480         while (length > 0) {
 481                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 482                 int this_length = min(cacheline_end - gpu_offset, length);
 483                 int swizzled_gpu_offset = gpu_offset ^ 64;
 484
 485                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 486                                        cpu_vaddr + cpu_offset,
 487                                        this_length);
 488                 if (ret)
 489                         return ret + length;
 490
 491                 cpu_offset += this_length;
 492                 gpu_offset += this_length;
 493                 length -= this_length;
 494         }
 495
 496         return 0;
 497 }
 498
 499 /*
 500  * Pins the specified object's pages and synchronizes the object with
 501  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 502  * flush the object from the CPU cache.
 503  */
 504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 505                                     int *needs_clflush)
 506 {
 507         int ret;
 508
 509         *needs_clflush = 0;
 510
 511         if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
 512                 return -EINVAL;
 513
 514         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 515                 /* If we're not in the cpu read domain, set ourself into the gtt
 516                  * read domain and manually flush cachelines (if required). This
 517                  * optimizes for the case when the gpu will dirty the data
 518                  * anyway again before the next pread happens. */
 519                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 520                                                         obj->cache_level);
 521                 ret = i915_gem_object_wait_rendering(obj, true);
 522                 if (ret)
 523                         return ret;
 524         }
 525
 526         ret = i915_gem_object_get_pages(obj);
 527         if (ret)
 528                 return ret;
 529
 530         i915_gem_object_pin_pages(obj);
 531
 532         return ret;
 533 }
 534
 535 /* Per-page copy function for the shmem pread fastpath.
 536  * Flushes invalid cachelines before reading the target if
 537  * needs_clflush is set. */
 538 static int
 539 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 540                  char __user *user_data,
 541                  bool page_do_bit17_swizzling, bool needs_clflush)
 542 {
 543         char *vaddr;
 544         int ret;
 545
 546         if (unlikely(page_do_bit17_swizzling))
 547                 return -EINVAL;
 548
 549         vaddr = kmap_atomic(page);
 550         if (needs_clflush)
 551                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 552                                        page_length);
 553         ret = __copy_to_user_inatomic(user_data,
 554                                       vaddr + shmem_page_offset,
 555                                       page_length);
 556         kunmap_atomic(vaddr);
 557
 558         return ret ? -EFAULT : 0;
 559 }
 560
 561 static void
 562 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 563                              bool swizzled)
 564 {
 565         if (unlikely(swizzled)) {
 566                 unsigned long start = (unsigned long) addr;
 567                 unsigned long end = (unsigned long) addr + length;
 568
 569                 /* For swizzling simply ensure that we always flush both
 570                  * channels. Lame, but simple and it works. Swizzled
 571                  * pwrite/pread is far from a hotpath - current userspace
 572                  * doesn't use it at all. */
 573                 start = round_down(start, 128);
 574                 end = round_up(end, 128);
 575
 576                 drm_clflush_virt_range((void *)start, end - start);
 577         } else {
 578                 drm_clflush_virt_range(addr, length);
 579         }
 580
 581 }
 582
 583 /* Only difference to the fast-path function is that this can handle bit17
 584  * and uses non-atomic copy and kmap functions. */
 585 static int
 586 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 587                  char __user *user_data,
 588                  bool page_do_bit17_swizzling, bool needs_clflush)
 589 {
 590         char *vaddr;
 591         int ret;
 592
 593         vaddr = kmap(page);
 594         if (needs_clflush)
 595                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 596                                              page_length,
 597                                              page_do_bit17_swizzling);
 598
 599         if (page_do_bit17_swizzling)
 600                 ret = __copy_to_user_swizzled(user_data,
 601                                               vaddr, shmem_page_offset,
 602                                               page_length);
 603         else
 604                 ret = __copy_to_user(user_data,
 605                                      vaddr + shmem_page_offset,
 606                                      page_length);
 607         kunmap(page);
 608
 609         return ret ? - EFAULT : 0;
 610 }
 611
 612 static inline unsigned long
 613 slow_user_access(struct io_mapping *mapping,
 614                  uint64_t page_base, int page_offset,
 615                  char __user *user_data,
 616                  unsigned long length, bool pwrite)
 617 {
 618         void __iomem *ioaddr;
 619         void *vaddr;
 620         uint64_t unwritten;
 621
 622         ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE);
 623         /* We can use the cpu mem copy function because this is X86. */
 624         vaddr = (void __force *)ioaddr + page_offset;
 625         if (pwrite)
 626                 unwritten = __copy_from_user(vaddr, user_data, length);
 627         else
 628                 unwritten = __copy_to_user(user_data, vaddr, length);
 629
 630         io_mapping_unmap(ioaddr);
 631         return unwritten;
 632 }
 633
 634 static int
 635 i915_gem_gtt_pread(struct drm_device *dev,
 636                    struct drm_i915_gem_object *obj, uint64_t size,
 637                    uint64_t data_offset, uint64_t data_ptr)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 641         struct drm_mm_node node;
 642         char __user *user_data;
 643         uint64_t remain;
 644         uint64_t offset;
 645         int ret;
 646
 647         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
 648         if (ret) {
 649                 ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE);
 650                 if (ret)
 651                         goto out;
 652
 653                 ret = i915_gem_object_get_pages(obj);
 654                 if (ret) {
 655                         remove_mappable_node(&node);
 656                         goto out;
 657                 }
 658
 659                 i915_gem_object_pin_pages(obj);
 660         } else {
 661                 node.start = i915_gem_obj_ggtt_offset(obj);
 662                 node.allocated = false;
 663                 ret = i915_gem_object_put_fence(obj);
 664                 if (ret)
 665                         goto out_unpin;
 666         }
 667
 668         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 669         if (ret)
 670                 goto out_unpin;
 671
 672         user_data = u64_to_user_ptr(data_ptr);
 673         remain = size;
 674         offset = data_offset;
 675
 676         mutex_unlock(&dev->struct_mutex);
 677         if (likely(!i915.prefault_disable)) {
 678                 ret = fault_in_multipages_writeable(user_data, remain);
 679                 if (ret) {
 680                         mutex_lock(&dev->struct_mutex);
 681                         goto out_unpin;
 682                 }
 683         }
 684
 685         while (remain > 0) {
 686                 /* Operation in this page
 687                  *
 688                  * page_base = page offset within aperture
 689                  * page_offset = offset within page
 690                  * page_length = bytes to copy for this page
 691                  */
 692                 u32 page_base = node.start;
 693                 unsigned page_offset = offset_in_page(offset);
 694                 unsigned page_length = PAGE_SIZE - page_offset;
 695                 page_length = remain < page_length ? remain : page_length;
 696                 if (node.allocated) {
 697                         wmb();
 698                         ggtt->base.insert_page(&ggtt->base,
 699                                                i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
 700                                                node.start,
 701                                                I915_CACHE_NONE, 0);
 702                         wmb();
 703                 } else {
 704                         page_base += offset & PAGE_MASK;
 705                 }
 706                 /* This is a slow read/write as it tries to read from
 707                  * and write to user memory which may result into page
 708                  * faults, and so we cannot perform this under struct_mutex.
 709                  */
 710                 if (slow_user_access(ggtt->mappable, page_base,
 711                                      page_offset, user_data,
 712                                      page_length, false)) {
 713                         ret = -EFAULT;
 714                         break;
 715                 }
 716
 717                 remain -= page_length;
 718                 user_data += page_length;
 719                 offset += page_length;
 720         }
 721
 722         mutex_lock(&dev->struct_mutex);
 723         if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
 724                 /* The user has modified the object whilst we tried
 725                  * reading from it, and we now have no idea what domain
 726                  * the pages should be in. As we have just been touching
 727                  * them directly, flush everything back to the GTT
 728                  * domain.
 729                  */
 730                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
 731         }
 732
 733 out_unpin:
 734         if (node.allocated) {
 735                 wmb();
 736                 ggtt->base.clear_range(&ggtt->base,
 737                                        node.start, node.size,
 738                                        true);
 739                 i915_gem_object_unpin_pages(obj);
 740                 remove_mappable_node(&node);
 741         } else {
 742                 i915_gem_object_ggtt_unpin(obj);
 743         }
 744 out:
 745         return ret;
 746 }
 747
 748 static int
 749 i915_gem_shmem_pread(struct drm_device *dev,
 750                      struct drm_i915_gem_object *obj,
 751                      struct drm_i915_gem_pread *args,
 752                      struct drm_file *file)
 753 {
 754         char __user *user_data;
 755         ssize_t remain;
 756         loff_t offset;
 757         int shmem_page_offset, page_length, ret = 0;
 758         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 759         int prefaulted = 0;
 760         int needs_clflush = 0;
 761         struct sg_page_iter sg_iter;
 762
 763         if (!i915_gem_object_has_struct_page(obj))
 764                 return -ENODEV;
 765
 766         user_data = u64_to_user_ptr(args->data_ptr);
 767         remain = args->size;
 768
 769         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 770
 771         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 772         if (ret)
 773                 return ret;
 774
 775         offset = args->offset;
 776
 777         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 778                          offset >> PAGE_SHIFT) {
 779                 struct page *page = sg_page_iter_page(&sg_iter);
 780
 781                 if (remain <= 0)
 782                         break;
 783
 784                 /* Operation in this page
 785                  *
 786                  * shmem_page_offset = offset within page in shmem file
 787                  * page_length = bytes to copy for this page
 788                  */
 789                 shmem_page_offset = offset_in_page(offset);
 790                 page_length = remain;
 791                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 792                         page_length = PAGE_SIZE - shmem_page_offset;
 793
 794                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 795                         (page_to_phys(page) & (1 << 17)) != 0;
 796
 797                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 798                                        user_data, page_do_bit17_swizzling,
 799                                        needs_clflush);
 800                 if (ret == 0)
 801                         goto next_page;
 802
 803                 mutex_unlock(&dev->struct_mutex);
 804
 805                 if (likely(!i915.prefault_disable) && !prefaulted) {
 806                         ret = fault_in_multipages_writeable(user_data, remain);
 807                         /* Userspace is tricking us, but we've already clobbered
 808                          * its pages with the prefault and promised to write the
 809                          * data up to the first fault. Hence ignore any errors
 810                          * and just continue. */
 811                         (void)ret;
 812                         prefaulted = 1;
 813                 }
 814
 815                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 816                                        user_data, page_do_bit17_swizzling,
 817                                        needs_clflush);
 818
 819                 mutex_lock(&dev->struct_mutex);
 820
 821                 if (ret)
 822                         goto out;
 823
 824 next_page:
 825                 remain -= page_length;
 826                 user_data += page_length;
 827                 offset += page_length;
 828         }
 829
 830 out:
 831         i915_gem_object_unpin_pages(obj);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * Reads data from the object referenced by handle.
 838  * @dev: drm device pointer
 839  * @data: ioctl data blob
 840  * @file: drm file pointer
 841  *
 842  * On error, the contents of *data are undefined.
 843  */
 844 int
 845 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 846                      struct drm_file *file)
 847 {
 848         struct drm_i915_gem_pread *args = data;
 849         struct drm_i915_gem_object *obj;
 850         int ret = 0;
 851
 852         if (args->size == 0)
 853                 return 0;
 854
 855         if (!access_ok(VERIFY_WRITE,
 856                        u64_to_user_ptr(args->data_ptr),
 857                        args->size))
 858                 return -EFAULT;
 859
 860         ret = i915_mutex_lock_interruptible(dev);
 861         if (ret)
 862                 return ret;
 863
 864         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
 865         if (&obj->base == NULL) {
 866                 ret = -ENOENT;
 867                 goto unlock;
 868         }
 869
 870         /* Bounds check source.  */
 871         if (args->offset > obj->base.size ||
 872             args->size > obj->base.size - args->offset) {
 873                 ret = -EINVAL;
 874                 goto out;
 875         }
 876
 877         trace_i915_gem_object_pread(obj, args->offset, args->size);
 878
 879         ret = i915_gem_shmem_pread(dev, obj, args, file);
 880
 881         /* pread for non shmem backed objects */
 882         if (ret == -EFAULT || ret == -ENODEV)
 883                 ret = i915_gem_gtt_pread(dev, obj, args->size,
 884                                         args->offset, args->data_ptr);
 885
 886 out:
 887         drm_gem_object_unreference(&obj->base);
 888 unlock:
 889         mutex_unlock(&dev->struct_mutex);
 890         return ret;
 891 }
 892
 893 /* This is the fast write path which cannot handle
 894  * page faults in the source data
 895  */
 896
 897 static inline int
 898 fast_user_write(struct io_mapping *mapping,
 899                 loff_t page_base, int page_offset,
 900                 char __user *user_data,
 901                 int length)
 902 {
 903         void __iomem *vaddr_atomic;
 904         void *vaddr;
 905         unsigned long unwritten;
 906
 907         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 908         /* We can use the cpu mem copy function because this is X86. */
 909         vaddr = (void __force*)vaddr_atomic + page_offset;
 910         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 911                                                       user_data, length);
 912         io_mapping_unmap_atomic(vaddr_atomic);
 913         return unwritten;
 914 }
 915
 916 /**
 917  * This is the fast pwrite path, where we copy the data directly from the
 918  * user into the GTT, uncached.
 919  * @dev: drm device pointer
 920  * @obj: i915 gem object
 921  * @args: pwrite arguments structure
 922  * @file: drm file pointer
 923  */
 924 static int
 925 i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915,
 926                          struct drm_i915_gem_object *obj,
 927                          struct drm_i915_gem_pwrite *args,
 928                          struct drm_file *file)
 929 {
 930         struct i915_ggtt *ggtt = &i915->ggtt;
 931         struct drm_device *dev = obj->base.dev;
 932         struct drm_mm_node node;
 933         uint64_t remain, offset;
 934         char __user *user_data;
 935         int ret;
 936         bool hit_slow_path = false;
 937
 938         if (obj->tiling_mode != I915_TILING_NONE)
 939                 return -EFAULT;
 940
 941         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 942         if (ret) {
 943                 ret = insert_mappable_node(i915, &node, PAGE_SIZE);
 944                 if (ret)
 945                         goto out;
 946
 947                 ret = i915_gem_object_get_pages(obj);
 948                 if (ret) {
 949                         remove_mappable_node(&node);
 950                         goto out;
 951                 }
 952
 953                 i915_gem_object_pin_pages(obj);
 954         } else {
 955                 node.start = i915_gem_obj_ggtt_offset(obj);
 956                 node.allocated = false;
 957                 ret = i915_gem_object_put_fence(obj);
 958                 if (ret)
 959                         goto out_unpin;
 960         }
 961
 962         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 963         if (ret)
 964                 goto out_unpin;
 965
 966         intel_fb_obj_invalidate(obj, ORIGIN_GTT);
 967         obj->dirty = true;
 968
 969         user_data = u64_to_user_ptr(args->data_ptr);
 970         offset = args->offset;
 971         remain = args->size;
 972         while (remain) {
 973                 /* Operation in this page
 974                  *
 975                  * page_base = page offset within aperture
 976                  * page_offset = offset within page
 977                  * page_length = bytes to copy for this page
 978                  */
 979                 u32 page_base = node.start;
 980                 unsigned page_offset = offset_in_page(offset);
 981                 unsigned page_length = PAGE_SIZE - page_offset;
 982                 page_length = remain < page_length ? remain : page_length;
 983                 if (node.allocated) {
 984                         wmb(); /* flush the write before we modify the GGTT */
 985                         ggtt->base.insert_page(&ggtt->base,
 986                                                i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
 987                                                node.start, I915_CACHE_NONE, 0);
 988                         wmb(); /* flush modifications to the GGTT (insert_page) */
 989                 } else {
 990                         page_base += offset & PAGE_MASK;
 991                 }
 992                 /* If we get a fault while copying data, then (presumably) our
 993                  * source page isn't available.  Return the error and we'll
 994                  * retry in the slow path.
 995                  * If the object is non-shmem backed, we retry again with the
 996                  * path that handles page fault.
 997                  */
 998                 if (fast_user_write(ggtt->mappable, page_base,
 999                                     page_offset, user_data, page_length)) {
1000                         hit_slow_path = true;
1001                         mutex_unlock(&dev->struct_mutex);
1002                         if (slow_user_access(ggtt->mappable,
1003                                              page_base,
1004                                              page_offset, user_data,
1005                                              page_length, true)) {
1006                                 ret = -EFAULT;
1007                                 mutex_lock(&dev->struct_mutex);
1008                                 goto out_flush;
1009                         }
1010
1011                         mutex_lock(&dev->struct_mutex);
1012                 }
1013
1014                 remain -= page_length;
1015                 user_data += page_length;
1016                 offset += page_length;
1017         }
1018
1019 out_flush:
1020         if (hit_slow_path) {
1021                 if (ret == 0 &&
1022                     (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
1023                         /* The user has modified the object whilst we tried
1024                          * reading from it, and we now have no idea what domain
1025                          * the pages should be in. As we have just been touching
1026                          * them directly, flush everything back to the GTT
1027                          * domain.
1028                          */
1029                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
1030                 }
1031         }
1032
1033         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
1034 out_unpin:
1035         if (node.allocated) {
1036                 wmb();
1037                 ggtt->base.clear_range(&ggtt->base,
1038                                        node.start, node.size,
1039                                        true);
1040                 i915_gem_object_unpin_pages(obj);
1041                 remove_mappable_node(&node);
1042         } else {
1043                 i915_gem_object_ggtt_unpin(obj);
1044         }
1045 out:
1046         return ret;
1047 }
1048
1049 /* Per-page copy function for the shmem pwrite fastpath.
1050  * Flushes invalid cachelines before writing to the target if
1051  * needs_clflush_before is set and flushes out any written cachelines after
1052  * writing if needs_clflush is set. */
1053 static int
1054 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
1055                   char __user *user_data,
1056                   bool page_do_bit17_swizzling,
1057                   bool needs_clflush_before,
1058                   bool needs_clflush_after)
1059 {
1060         char *vaddr;
1061         int ret;
1062
1063         if (unlikely(page_do_bit17_swizzling))
1064                 return -EINVAL;
1065
1066         vaddr = kmap_atomic(page);
1067         if (needs_clflush_before)
1068                 drm_clflush_virt_range(vaddr + shmem_page_offset,
1069                                        page_length);
1070         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
1071                                         user_data, page_length);
1072         if (needs_clflush_after)
1073                 drm_clflush_virt_range(vaddr + shmem_page_offset,
1074                                        page_length);
1075         kunmap_atomic(vaddr);
1076
1077         return ret ? -EFAULT : 0;
1078 }
1079
1080 /* Only difference to the fast-path function is that this can handle bit17
1081  * and uses non-atomic copy and kmap functions. */
1082 static int
1083 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
1084                   char __user *user_data,
1085                   bool page_do_bit17_swizzling,
1086                   bool needs_clflush_before,
1087                   bool needs_clflush_after)
1088 {
1089         char *vaddr;
1090         int ret;
1091
1092         vaddr = kmap(page);
1093         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1094                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1095                                              page_length,
1096                                              page_do_bit17_swizzling);
1097         if (page_do_bit17_swizzling)
1098                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
1099                                                 user_data,
1100                                                 page_length);
1101         else
1102                 ret = __copy_from_user(vaddr + shmem_page_offset,
1103                                        user_data,
1104                                        page_length);
1105         if (needs_clflush_after)
1106                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1107                                              page_length,
1108                                              page_do_bit17_swizzling);
1109         kunmap(page);
1110
1111         return ret ? -EFAULT : 0;
1112 }
1113
1114 static int
1115 i915_gem_shmem_pwrite(struct drm_device *dev,
1116                       struct drm_i915_gem_object *obj,
1117                       struct drm_i915_gem_pwrite *args,
1118                       struct drm_file *file)
1119 {
1120         ssize_t remain;
1121         loff_t offset;
1122         char __user *user_data;
1123         int shmem_page_offset, page_length, ret = 0;
1124         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
1125         int hit_slowpath = 0;
1126         int needs_clflush_after = 0;
1127         int needs_clflush_before = 0;
1128         struct sg_page_iter sg_iter;
1129
1130         user_data = u64_to_user_ptr(args->data_ptr);
1131         remain = args->size;
1132
1133         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
1134
1135         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1136                 /* If we're not in the cpu write domain, set ourself into the gtt
1137                  * write domain and manually flush cachelines (if required). This
1138                  * optimizes for the case when the gpu will use the data
1139                  * right away and we therefore have to clflush anyway. */
1140                 needs_clflush_after = cpu_write_needs_clflush(obj);
1141                 ret = i915_gem_object_wait_rendering(obj, false);
1142                 if (ret)
1143                         return ret;
1144         }
1145         /* Same trick applies to invalidate partially written cachelines read
1146          * before writing. */
1147         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1148                 needs_clflush_before =
1149                         !cpu_cache_is_coherent(dev, obj->cache_level);
1150
1151         ret = i915_gem_object_get_pages(obj);
1152         if (ret)
1153                 return ret;
1154
1155         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1156
1157         i915_gem_object_pin_pages(obj);
1158
1159         offset = args->offset;
1160         obj->dirty = 1;
1161
1162         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
1163                          offset >> PAGE_SHIFT) {
1164                 struct page *page = sg_page_iter_page(&sg_iter);
1165                 int partial_cacheline_write;
1166
1167                 if (remain <= 0)
1168                         break;
1169
1170                 /* Operation in this page
1171                  *
1172                  * shmem_page_offset = offset within page in shmem file
1173                  * page_length = bytes to copy for this page
1174                  */
1175                 shmem_page_offset = offset_in_page(offset);
1176
1177                 page_length = remain;
1178                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1179                         page_length = PAGE_SIZE - shmem_page_offset;
1180
1181                 /* If we don't overwrite a cacheline completely we need to be
1182                  * careful to have up-to-date data by first clflushing. Don't
1183                  * overcomplicate things and flush the entire patch. */
1184                 partial_cacheline_write = needs_clflush_before &&
1185                         ((shmem_page_offset | page_length)
1186                                 & (boot_cpu_data.x86_clflush_size - 1));
1187
1188                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
1189                         (page_to_phys(page) & (1 << 17)) != 0;
1190
1191                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
1192                                         user_data, page_do_bit17_swizzling,
1193                                         partial_cacheline_write,
1194                                         needs_clflush_after);
1195                 if (ret == 0)
1196                         goto next_page;
1197
1198                 hit_slowpath = 1;
1199                 mutex_unlock(&dev->struct_mutex);
1200                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1201                                         user_data, page_do_bit17_swizzling,
1202                                         partial_cacheline_write,
1203                                         needs_clflush_after);
1204
1205                 mutex_lock(&dev->struct_mutex);
1206
1207                 if (ret)
1208                         goto out;
1209
1210 next_page:
1211                 remain -= page_length;
1212                 user_data += page_length;
1213                 offset += page_length;
1214         }
1215
1216 out:
1217         i915_gem_object_unpin_pages(obj);
1218
1219         if (hit_slowpath) {
1220                 /*
1221                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1222                  * cachelines in-line while writing and the object moved
1223                  * out of the cpu write domain while we've dropped the lock.
1224                  */
1225                 if (!needs_clflush_after &&
1226                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1227                         if (i915_gem_clflush_object(obj, obj->pin_display))
1228                                 needs_clflush_after = true;
1229                 }
1230         }
1231
1232         if (needs_clflush_after)
1233                 i915_gem_chipset_flush(to_i915(dev));
1234         else
1235                 obj->cache_dirty = true;
1236
1237         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1238         return ret;
1239 }
1240
1241 /**
1242  * Writes data to the object referenced by handle.
1243  * @dev: drm device
1244  * @data: ioctl data blob
1245  * @file: drm file
1246  *
1247  * On error, the contents of the buffer that were to be modified are undefined.
1248  */
1249 int
1250 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1251                       struct drm_file *file)
1252 {
1253         struct drm_i915_private *dev_priv = dev->dev_private;
1254         struct drm_i915_gem_pwrite *args = data;
1255         struct drm_i915_gem_object *obj;
1256         int ret;
1257
1258         if (args->size == 0)
1259                 return 0;
1260
1261         if (!access_ok(VERIFY_READ,
1262                        u64_to_user_ptr(args->data_ptr),
1263                        args->size))
1264                 return -EFAULT;
1265
1266         if (likely(!i915.prefault_disable)) {
1267                 ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr),
1268                                                    args->size);
1269                 if (ret)
1270                         return -EFAULT;
1271         }
1272
1273         intel_runtime_pm_get(dev_priv);
1274
1275         ret = i915_mutex_lock_interruptible(dev);
1276         if (ret)
1277                 goto put_rpm;
1278
1279         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1280         if (&obj->base == NULL) {
1281                 ret = -ENOENT;
1282                 goto unlock;
1283         }
1284
1285         /* Bounds check destination. */
1286         if (args->offset > obj->base.size ||
1287             args->size > obj->base.size - args->offset) {
1288                 ret = -EINVAL;
1289                 goto out;
1290         }
1291
1292         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1293
1294         ret = -EFAULT;
1295         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1296          * it would end up going through the fenced access, and we'll get
1297          * different detiling behavior between reading and writing.
1298          * pread/pwrite currently are reading and writing from the CPU
1299          * perspective, requiring manual detiling by the client.
1300          */
1301         if (!i915_gem_object_has_struct_page(obj) ||
1302             cpu_write_needs_clflush(obj)) {
1303                 ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file);
1304                 /* Note that the gtt paths might fail with non-page-backed user
1305                  * pointers (e.g. gtt mappings when moving data between
1306                  * textures). Fallback to the shmem path in that case. */
1307         }
1308
1309         if (ret == -EFAULT) {
1310                 if (obj->phys_handle)
1311                         ret = i915_gem_phys_pwrite(obj, args, file);
1312                 else if (i915_gem_object_has_struct_page(obj))
1313                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1314                 else
1315                         ret = -ENODEV;
1316         }
1317
1318 out:
1319         drm_gem_object_unreference(&obj->base);
1320 unlock:
1321         mutex_unlock(&dev->struct_mutex);
1322 put_rpm:
1323         intel_runtime_pm_put(dev_priv);
1324
1325         return ret;
1326 }
1327
1328 static int
1329 i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
1330 {
1331         if (__i915_terminally_wedged(reset_counter))
1332                 return -EIO;
1333
1334         if (__i915_reset_in_progress(reset_counter)) {
1335                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1336                  * -EIO unconditionally for these. */
1337                 if (!interruptible)
1338                         return -EIO;
1339
1340                 return -EAGAIN;
1341         }
1342
1343         return 0;
1344 }
1345
1346 static unsigned long local_clock_us(unsigned *cpu)
1347 {
1348         unsigned long t;
1349
1350         /* Cheaply and approximately convert from nanoseconds to microseconds.
1351          * The result and subsequent calculations are also defined in the same
1352          * approximate microseconds units. The principal source of timing
1353          * error here is from the simple truncation.
1354          *
1355          * Note that local_clock() is only defined wrt to the current CPU;
1356          * the comparisons are no longer valid if we switch CPUs. Instead of
1357          * blocking preemption for the entire busywait, we can detect the CPU
1358          * switch and use that as indicator of system load and a reason to
1359          * stop busywaiting, see busywait_stop().
1360          */
1361         *cpu = get_cpu();
1362         t = local_clock() >> 10;
1363         put_cpu();
1364
1365         return t;
1366 }
1367
1368 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1369 {
1370         unsigned this_cpu;
1371
1372         if (time_after(local_clock_us(&this_cpu), timeout))
1373                 return true;
1374
1375         return this_cpu != cpu;
1376 }
1377
1378 bool __i915_spin_request(const struct drm_i915_gem_request *req,
1379                          int state, unsigned long timeout_us)
1380 {
1381         unsigned cpu;
1382
1383         /* When waiting for high frequency requests, e.g. during synchronous
1384          * rendering split between the CPU and GPU, the finite amount of time
1385          * required to set up the irq and wait upon it limits the response
1386          * rate. By busywaiting on the request completion for a short while we
1387          * can service the high frequency waits as quick as possible. However,
1388          * if it is a slow request, we want to sleep as quickly as possible.
1389          * The tradeoff between waiting and sleeping is roughly the time it
1390          * takes to sleep on a request, on the order of a microsecond.
1391          */
1392
1393         timeout_us += local_clock_us(&cpu);
1394         do {
1395                 if (i915_gem_request_completed(req))
1396                         return true;
1397
1398                 if (signal_pending_state(state, current))
1399                         break;
1400
1401                 if (busywait_stop(timeout_us, cpu))
1402                         break;
1403
1404                 cpu_relax_lowlatency();
1405         } while (!need_resched());
1406
1407         return false;
1408 }
1409
1410 /**
1411  * __i915_wait_request - wait until execution of request has finished
1412  * @req: duh!
1413  * @interruptible: do an interruptible wait (normally yes)
1414  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1415  * @rps: RPS client
1416  *
1417  * Note: It is of utmost importance that the passed in seqno and reset_counter
1418  * values have been read by the caller in an smp safe manner. Where read-side
1419  * locks are involved, it is sufficient to read the reset_counter before
1420  * unlocking the lock that protects the seqno. For lockless tricks, the
1421  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1422  * inserted.
1423  *
1424  * Returns 0 if the request was found within the alloted time. Else returns the
1425  * errno with remaining time filled in timeout argument.
1426  */
1427 int __i915_wait_request(struct drm_i915_gem_request *req,
1428                         bool interruptible,
1429                         s64 *timeout,
1430                         struct intel_rps_client *rps)
1431 {
1432         int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1433         DEFINE_WAIT(reset);
1434         struct intel_wait wait;
1435         unsigned long timeout_remain;
1436         s64 before = 0; /* Only to silence a compiler warning. */
1437         int ret = 0;
1438
1439         might_sleep();
1440
1441         if (list_empty(&req->list))
1442                 return 0;
1443
1444         if (i915_gem_request_completed(req))
1445                 return 0;
1446
1447         timeout_remain = MAX_SCHEDULE_TIMEOUT;
1448         if (timeout) {
1449                 if (WARN_ON(*timeout < 0))
1450                         return -EINVAL;
1451
1452                 if (*timeout == 0)
1453                         return -ETIME;
1454
1455                 timeout_remain = nsecs_to_jiffies_timeout(*timeout);
1456
1457                 /*
1458                  * Record current time in case interrupted by signal, or wedged.
1459                  */
1460                 before = ktime_get_raw_ns();
1461         }
1462
1463         trace_i915_gem_request_wait_begin(req);
1464
1465         if (INTEL_INFO(req->i915)->gen >= 6)
1466                 gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
1467
1468         /* Optimistic spin for the next ~jiffie before touching IRQs */
1469         if (i915_spin_request(req, state, 5))
1470                 goto complete;
1471
1472         set_current_state(state);
1473         add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1474
1475         intel_wait_init(&wait, req->seqno);
1476         if (intel_engine_add_wait(req->engine, &wait))
1477                 /* In order to check that we haven't missed the interrupt
1478                  * as we enabled it, we need to kick ourselves to do a
1479                  * coherent check on the seqno before we sleep.
1480                  */
1481                 goto wakeup;
1482
1483         for (;;) {
1484                 if (signal_pending_state(state, current)) {
1485                         ret = -ERESTARTSYS;
1486                         break;
1487                 }
1488
1489                 /* Ensure that even if the GPU hangs, we get woken up.
1490                  *
1491                  * However, note that if no one is waiting, we never notice
1492                  * a gpu hang. Eventually, we will have to wait for a resource
1493                  * held by the GPU and so trigger a hangcheck. In the most
1494                  * pathological case, this will be upon memory starvation!
1495                  */
1496                 i915_queue_hangcheck(req->i915);
1497
1498                 timeout_remain = io_schedule_timeout(timeout_remain);
1499                 if (timeout_remain == 0) {
1500                         ret = -ETIME;
1501                         break;
1502                 }
1503
1504                 if (intel_wait_complete(&wait))
1505                         break;
1506
1507                 set_current_state(state);
1508
1509 wakeup:
1510                 /* Carefully check if the request is complete, giving time
1511                  * for the seqno to be visible following the interrupt.
1512                  * We also have to check in case we are kicked by the GPU
1513                  * reset in order to drop the struct_mutex.
1514                  */
1515                 if (__i915_request_irq_complete(req))
1516                         break;
1517
1518                 /* Only spin if we know the GPU is processing this request */
1519                 if (i915_spin_request(req, state, 2))
1520                         break;
1521         }
1522         remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1523
1524         intel_engine_remove_wait(req->engine, &wait);
1525         __set_current_state(TASK_RUNNING);
1526 complete:
1527         trace_i915_gem_request_wait_end(req);
1528
1529         if (timeout) {
1530                 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1531
1532                 *timeout = tres < 0 ? 0 : tres;
1533
1534                 /*
1535                  * Apparently ktime isn't accurate enough and occasionally has a
1536                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1537                  * things up to make the test happy. We allow up to 1 jiffy.
1538                  *
1539                  * This is a regrssion from the timespec->ktime conversion.
1540                  */
1541                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1542                         *timeout = 0;
1543         }
1544
1545         return ret;
1546 }
1547
1548 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1549                                    struct drm_file *file)
1550 {
1551         struct drm_i915_file_private *file_priv;
1552
1553         WARN_ON(!req || !file || req->file_priv);
1554
1555         if (!req || !file)
1556                 return -EINVAL;
1557
1558         if (req->file_priv)
1559                 return -EINVAL;
1560
1561         file_priv = file->driver_priv;
1562
1563         spin_lock(&file_priv->mm.lock);
1564         req->file_priv = file_priv;
1565         list_add_tail(&req->client_list, &file_priv->mm.request_list);
1566         spin_unlock(&file_priv->mm.lock);
1567
1568         req->pid = get_pid(task_pid(current));
1569
1570         return 0;
1571 }
1572
1573 static inline void
1574 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1575 {
1576         struct drm_i915_file_private *file_priv = request->file_priv;
1577
1578         if (!file_priv)
1579                 return;
1580
1581         spin_lock(&file_priv->mm.lock);
1582         list_del(&request->client_list);
1583         request->file_priv = NULL;
1584         spin_unlock(&file_priv->mm.lock);
1585
1586         put_pid(request->pid);
1587         request->pid = NULL;
1588 }
1589
1590 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1591 {
1592         trace_i915_gem_request_retire(request);
1593
1594         /* We know the GPU must have read the request to have
1595          * sent us the seqno + interrupt, so use the position
1596          * of tail of the request to update the last known position
1597          * of the GPU head.
1598          *
1599          * Note this requires that we are always called in request
1600          * completion order.
1601          */
1602         request->ringbuf->last_retired_head = request->postfix;
1603
1604         list_del_init(&request->list);
1605         i915_gem_request_remove_from_client(request);
1606
1607         if (request->previous_context) {
1608                 if (i915.enable_execlists)
1609                         intel_lr_context_unpin(request->previous_context,
1610                                                request->engine);
1611         }
1612
1613         i915_gem_context_unreference(request->ctx);
1614         i915_gem_request_unreference(request);
1615 }
1616
1617 static void
1618 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1619 {
1620         struct intel_engine_cs *engine = req->engine;
1621         struct drm_i915_gem_request *tmp;
1622
1623         lockdep_assert_held(&engine->i915->dev->struct_mutex);
1624
1625         if (list_empty(&req->list))
1626                 return;
1627
1628         do {
1629                 tmp = list_first_entry(&engine->request_list,
1630                                        typeof(*tmp), list);
1631
1632                 i915_gem_request_retire(tmp);
1633         } while (tmp != req);
1634
1635         WARN_ON(i915_verify_lists(engine->dev));
1636 }
1637
1638 /**
1639  * Waits for a request to be signaled, and cleans up the
1640  * request and object lists appropriately for that event.
1641  * @req: request to wait on
1642  */
1643 int
1644 i915_wait_request(struct drm_i915_gem_request *req)
1645 {
1646         struct drm_i915_private *dev_priv = req->i915;
1647         bool interruptible;
1648         int ret;
1649
1650         interruptible = dev_priv->mm.interruptible;
1651
1652         BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1653
1654         ret = __i915_wait_request(req, interruptible, NULL, NULL);
1655         if (ret)
1656                 return ret;
1657
1658         /* If the GPU hung, we want to keep the requests to find the guilty. */
1659         if (!i915_reset_in_progress(&dev_priv->gpu_error))
1660                 __i915_gem_request_retire__upto(req);
1661
1662         return 0;
1663 }
1664
1665 /**
1666  * Ensures that all rendering to the object has completed and the object is
1667  * safe to unbind from the GTT or access from the CPU.
1668  * @obj: i915 gem object
1669  * @readonly: waiting for read access or write
1670  */
1671 int
1672 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1673                                bool readonly)
1674 {
1675         int ret, i;
1676
1677         if (!obj->active)
1678                 return 0;
1679
1680         if (readonly) {
1681                 if (obj->last_write_req != NULL) {
1682                         ret = i915_wait_request(obj->last_write_req);
1683                         if (ret)
1684                                 return ret;
1685
1686                         i = obj->last_write_req->engine->id;
1687                         if (obj->last_read_req[i] == obj->last_write_req)
1688                                 i915_gem_object_retire__read(obj, i);
1689                         else
1690                                 i915_gem_object_retire__write(obj);
1691                 }
1692         } else {
1693                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1694                         if (obj->last_read_req[i] == NULL)
1695                                 continue;
1696
1697                         ret = i915_wait_request(obj->last_read_req[i]);
1698                         if (ret)
1699                                 return ret;
1700
1701                         i915_gem_object_retire__read(obj, i);
1702                 }
1703                 GEM_BUG_ON(obj->active);
1704         }
1705
1706         return 0;
1707 }
1708
1709 static void
1710 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1711                                struct drm_i915_gem_request *req)
1712 {
1713         int ring = req->engine->id;
1714
1715         if (obj->last_read_req[ring] == req)
1716                 i915_gem_object_retire__read(obj, ring);
1717         else if (obj->last_write_req == req)
1718                 i915_gem_object_retire__write(obj);
1719
1720         if (!i915_reset_in_progress(&req->i915->gpu_error))
1721                 __i915_gem_request_retire__upto(req);
1722 }
1723
1724 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1725  * as the object state may change during this call.
1726  */
1727 static __must_check int
1728 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1729                                             struct intel_rps_client *rps,
1730                                             bool readonly)
1731 {
1732         struct drm_device *dev = obj->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1735         int ret, i, n = 0;
1736
1737         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1738         BUG_ON(!dev_priv->mm.interruptible);
1739
1740         if (!obj->active)
1741                 return 0;
1742
1743         if (readonly) {
1744                 struct drm_i915_gem_request *req;
1745
1746                 req = obj->last_write_req;
1747                 if (req == NULL)
1748                         return 0;
1749
1750                 requests[n++] = i915_gem_request_reference(req);
1751         } else {
1752                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1753                         struct drm_i915_gem_request *req;
1754
1755                         req = obj->last_read_req[i];
1756                         if (req == NULL)
1757                                 continue;
1758
1759                         requests[n++] = i915_gem_request_reference(req);
1760                 }
1761         }
1762
1763         mutex_unlock(&dev->struct_mutex);
1764         ret = 0;
1765         for (i = 0; ret == 0 && i < n; i++)
1766                 ret = __i915_wait_request(requests[i], true, NULL, rps);
1767         mutex_lock(&dev->struct_mutex);
1768
1769         for (i = 0; i < n; i++) {
1770                 if (ret == 0)
1771                         i915_gem_object_retire_request(obj, requests[i]);
1772                 i915_gem_request_unreference(requests[i]);
1773         }
1774
1775         return ret;
1776 }
1777
1778 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1779 {
1780         struct drm_i915_file_private *fpriv = file->driver_priv;
1781         return &fpriv->rps;
1782 }
1783
1784 static enum fb_op_origin
1785 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1786 {
1787         return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ?
1788                ORIGIN_GTT : ORIGIN_CPU;
1789 }
1790
1791 /**
1792  * Called when user space prepares to use an object with the CPU, either
1793  * through the mmap ioctl's mapping or a GTT mapping.
1794  * @dev: drm device
1795  * @data: ioctl data blob
1796  * @file: drm file
1797  */
1798 int
1799 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1800                           struct drm_file *file)
1801 {
1802         struct drm_i915_gem_set_domain *args = data;
1803         struct drm_i915_gem_object *obj;
1804         uint32_t read_domains = args->read_domains;
1805         uint32_t write_domain = args->write_domain;
1806         int ret;
1807
1808         /* Only handle setting domains to types used by the CPU. */
1809         if (write_domain & I915_GEM_GPU_DOMAINS)
1810                 return -EINVAL;
1811
1812         if (read_domains & I915_GEM_GPU_DOMAINS)
1813                 return -EINVAL;
1814
1815         /* Having something in the write domain implies it's in the read
1816          * domain, and only that read domain.  Enforce that in the request.
1817          */
1818         if (write_domain != 0 && read_domains != write_domain)
1819                 return -EINVAL;
1820
1821         ret = i915_mutex_lock_interruptible(dev);
1822         if (ret)
1823                 return ret;
1824
1825         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1826         if (&obj->base == NULL) {
1827                 ret = -ENOENT;
1828                 goto unlock;
1829         }
1830
1831         /* Try to flush the object off the GPU without holding the lock.
1832          * We will repeat the flush holding the lock in the normal manner
1833          * to catch cases where we are gazumped.
1834          */
1835         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1836                                                           to_rps_client(file),
1837                                                           !write_domain);
1838         if (ret)
1839                 goto unref;
1840
1841         if (read_domains & I915_GEM_DOMAIN_GTT)
1842                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1843         else
1844                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1845
1846         if (write_domain != 0)
1847                 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1848
1849 unref:
1850         drm_gem_object_unreference(&obj->base);
1851 unlock:
1852         mutex_unlock(&dev->struct_mutex);
1853         return ret;
1854 }
1855
1856 /**
1857  * Called when user space has done writes to this buffer
1858  * @dev: drm device
1859  * @data: ioctl data blob
1860  * @file: drm file
1861  */
1862 int
1863 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1864                          struct drm_file *file)
1865 {
1866         struct drm_i915_gem_sw_finish *args = data;
1867         struct drm_i915_gem_object *obj;
1868         int ret = 0;
1869
1870         ret = i915_mutex_lock_interruptible(dev);
1871         if (ret)
1872                 return ret;
1873
1874         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1875         if (&obj->base == NULL) {
1876                 ret = -ENOENT;
1877                 goto unlock;
1878         }
1879
1880         /* Pinned buffers may be scanout, so flush the cache */
1881         if (obj->pin_display)
1882                 i915_gem_object_flush_cpu_write_domain(obj);
1883
1884         drm_gem_object_unreference(&obj->base);
1885 unlock:
1886         mutex_unlock(&dev->struct_mutex);
1887         return ret;
1888 }
1889
1890 /**
1891  * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1892  *                       it is mapped to.
1893  * @dev: drm device
1894  * @data: ioctl data blob
1895  * @file: drm file
1896  *
1897  * While the mapping holds a reference on the contents of the object, it doesn't
1898  * imply a ref on the object itself.
1899  *
1900  * IMPORTANT:
1901  *
1902  * DRM driver writers who look a this function as an example for how to do GEM
1903  * mmap support, please don't implement mmap support like here. The modern way
1904  * to implement DRM mmap support is with an mmap offset ioctl (like
1905  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1906  * That way debug tooling like valgrind will understand what's going on, hiding
1907  * the mmap call in a driver private ioctl will break that. The i915 driver only
1908  * does cpu mmaps this way because we didn't know better.
1909  */
1910 int
1911 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1912                     struct drm_file *file)
1913 {
1914         struct drm_i915_gem_mmap *args = data;
1915         struct drm_gem_object *obj;
1916         unsigned long addr;
1917
1918         if (args->flags & ~(I915_MMAP_WC))
1919                 return -EINVAL;
1920
1921         if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1922                 return -ENODEV;
1923
1924         obj = drm_gem_object_lookup(file, args->handle);
1925         if (obj == NULL)
1926                 return -ENOENT;
1927
1928         /* prime objects have no backing filp to GEM mmap
1929          * pages from.
1930          */
1931         if (!obj->filp) {
1932                 drm_gem_object_unreference_unlocked(obj);
1933                 return -EINVAL;
1934         }
1935
1936         addr = vm_mmap(obj->filp, 0, args->size,
1937                        PROT_READ | PROT_WRITE, MAP_SHARED,
1938                        args->offset);
1939         if (args->flags & I915_MMAP_WC) {
1940                 struct mm_struct *mm = current->mm;
1941                 struct vm_area_struct *vma;
1942
1943                 if (down_write_killable(&mm->mmap_sem)) {
1944                         drm_gem_object_unreference_unlocked(obj);
1945                         return -EINTR;
1946                 }
1947                 vma = find_vma(mm, addr);
1948                 if (vma)
1949                         vma->vm_page_prot =
1950                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1951                 else
1952                         addr = -ENOMEM;
1953                 up_write(&mm->mmap_sem);
1954
1955                 /* This may race, but that's ok, it only gets set */
1956                 WRITE_ONCE(to_intel_bo(obj)->has_wc_mmap, true);
1957         }
1958         drm_gem_object_unreference_unlocked(obj);
1959         if (IS_ERR((void *)addr))
1960                 return addr;
1961
1962         args->addr_ptr = (uint64_t) addr;
1963
1964         return 0;
1965 }
1966
1967 /**
1968  * i915_gem_fault - fault a page into the GTT
1969  * @vma: VMA in question
1970  * @vmf: fault info
1971  *
1972  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1973  * from userspace.  The fault handler takes care of binding the object to
1974  * the GTT (if needed), allocating and programming a fence register (again,
1975  * only if needed based on whether the old reg is still valid or the object
1976  * is tiled) and inserting a new PTE into the faulting process.
1977  *
1978  * Note that the faulting process may involve evicting existing objects
1979  * from the GTT and/or fence registers to make room.  So performance may
1980  * suffer if the GTT working set is large or there are few fence registers
1981  * left.
1982  */
1983 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1984 {
1985         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1986         struct drm_device *dev = obj->base.dev;
1987         struct drm_i915_private *dev_priv = to_i915(dev);
1988         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1989         struct i915_ggtt_view view = i915_ggtt_view_normal;
1990         pgoff_t page_offset;
1991         unsigned long pfn;
1992         int ret = 0;
1993         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1994
1995         intel_runtime_pm_get(dev_priv);
1996
1997         /* We don't use vmf->pgoff since that has the fake offset */
1998         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1999                 PAGE_SHIFT;
2000
2001         ret = i915_mutex_lock_interruptible(dev);
2002         if (ret)
2003                 goto out;
2004
2005         trace_i915_gem_object_fault(obj, page_offset, true, write);
2006
2007         /* Try to flush the object off the GPU first without holding the lock.
2008          * Upon reacquiring the lock, we will perform our sanity checks and then
2009          * repeat the flush holding the lock in the normal manner to catch cases
2010          * where we are gazumped.
2011          */
2012         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
2013         if (ret)
2014                 goto unlock;
2015
2016         /* Access to snoopable pages through the GTT is incoherent. */
2017         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
2018                 ret = -EFAULT;
2019                 goto unlock;
2020         }
2021
2022         /* Use a partial view if the object is bigger than the aperture. */
2023         if (obj->base.size >= ggtt->mappable_end &&
2024             obj->tiling_mode == I915_TILING_NONE) {
2025                 static const unsigned int chunk_size = 256; // 1 MiB
2026
2027                 memset(&view, 0, sizeof(view));
2028                 view.type = I915_GGTT_VIEW_PARTIAL;
2029                 view.params.partial.offset = rounddown(page_offset, chunk_size);
2030                 view.params.partial.size =
2031                         min_t(unsigned int,
2032                               chunk_size,
2033                               (vma->vm_end - vma->vm_start)/PAGE_SIZE -
2034                               view.params.partial.offset);
2035         }
2036
2037         /* Now pin it into the GTT if needed */
2038         ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
2039         if (ret)
2040                 goto unlock;
2041
2042         ret = i915_gem_object_set_to_gtt_domain(obj, write);
2043         if (ret)
2044                 goto unpin;
2045
2046         ret = i915_gem_object_get_fence(obj);
2047         if (ret)
2048                 goto unpin;
2049
2050         /* Finally, remap it using the new GTT offset */
2051         pfn = ggtt->mappable_base +
2052                 i915_gem_obj_ggtt_offset_view(obj, &view);
2053         pfn >>= PAGE_SHIFT;
2054
2055         if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
2056                 /* Overriding existing pages in partial view does not cause
2057                  * us any trouble as TLBs are still valid because the fault
2058                  * is due to userspace losing part of the mapping or never
2059                  * having accessed it before (at this partials' range).
2060                  */
2061                 unsigned long base = vma->vm_start +
2062                                      (view.params.partial.offset << PAGE_SHIFT);
2063                 unsigned int i;
2064
2065                 for (i = 0; i < view.params.partial.size; i++) {
2066                         ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
2067                         if (ret)
2068                                 break;
2069                 }
2070
2071                 obj->fault_mappable = true;
2072         } else {
2073                 if (!obj->fault_mappable) {
2074                         unsigned long size = min_t(unsigned long,
2075                                                    vma->vm_end - vma->vm_start,
2076                                                    obj->base.size);
2077                         int i;
2078
2079                         for (i = 0; i < size >> PAGE_SHIFT; i++) {
2080                                 ret = vm_insert_pfn(vma,
2081                                                     (unsigned long)vma->vm_start + i * PAGE_SIZE,
2082                                                     pfn + i);
2083                                 if (ret)
2084                                         break;
2085                         }
2086
2087                         obj->fault_mappable = true;
2088                 } else
2089                         ret = vm_insert_pfn(vma,
2090                                             (unsigned long)vmf->virtual_address,
2091                                             pfn + page_offset);
2092         }
2093 unpin:
2094         i915_gem_object_ggtt_unpin_view(obj, &view);
2095 unlock:
2096         mutex_unlock(&dev->struct_mutex);
2097 out:
2098         switch (ret) {
2099         case -EIO:
2100                 /*
2101                  * We eat errors when the gpu is terminally wedged to avoid
2102                  * userspace unduly crashing (gl has no provisions for mmaps to
2103                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
2104                  * and so needs to be reported.
2105                  */
2106                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
2107                         ret = VM_FAULT_SIGBUS;
2108                         break;
2109                 }
2110         case -EAGAIN:
2111                 /*
2112                  * EAGAIN means the gpu is hung and we'll wait for the error
2113                  * handler to reset everything when re-faulting in
2114                  * i915_mutex_lock_interruptible.
2115                  */
2116         case 0:
2117         case -ERESTARTSYS:
2118         case -EINTR:
2119         case -EBUSY:
2120                 /*
2121                  * EBUSY is ok: this just means that another thread
2122                  * already did the job.
2123                  */
2124                 ret = VM_FAULT_NOPAGE;
2125                 break;
2126         case -ENOMEM:
2127                 ret = VM_FAULT_OOM;
2128                 break;
2129         case -ENOSPC:
2130         case -EFAULT:
2131                 ret = VM_FAULT_SIGBUS;
2132                 break;
2133         default:
2134                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2135                 ret = VM_FAULT_SIGBUS;
2136                 break;
2137         }
2138
2139         intel_runtime_pm_put(dev_priv);
2140         return ret;
2141 }
2142
2143 /**
2144  * i915_gem_release_mmap - remove physical page mappings
2145  * @obj: obj in question
2146  *
2147  * Preserve the reservation of the mmapping with the DRM core code, but
2148  * relinquish ownership of the pages back to the system.
2149  *
2150  * It is vital that we remove the page mapping if we have mapped a tiled
2151  * object through the GTT and then lose the fence register due to
2152  * resource pressure. Similarly if the object has been moved out of the
2153  * aperture, than pages mapped into userspace must be revoked. Removing the
2154  * mapping will then trigger a page fault on the next user access, allowing
2155  * fixup by i915_gem_fault().
2156  */
2157 void
2158 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2159 {
2160         /* Serialisation between user GTT access and our code depends upon
2161          * revoking the CPU's PTE whilst the mutex is held. The next user
2162          * pagefault then has to wait until we release the mutex.
2163          */
2164         lockdep_assert_held(&obj->base.dev->struct_mutex);
2165
2166         if (!obj->fault_mappable)
2167                 return;
2168
2169         drm_vma_node_unmap(&obj->base.vma_node,
2170                            obj->base.dev->anon_inode->i_mapping);
2171
2172         /* Ensure that the CPU's PTE are revoked and there are not outstanding
2173          * memory transactions from userspace before we return. The TLB
2174          * flushing implied above by changing the PTE above *should* be
2175          * sufficient, an extra barrier here just provides us with a bit
2176          * of paranoid documentation about our requirement to serialise
2177          * memory writes before touching registers / GSM.
2178          */
2179         wmb();
2180
2181         obj->fault_mappable = false;
2182 }
2183
2184 void
2185 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
2186 {
2187         struct drm_i915_gem_object *obj;
2188
2189         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
2190                 i915_gem_release_mmap(obj);
2191 }
2192
2193 uint32_t
2194 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
2195 {
2196         uint32_t gtt_size;
2197
2198         if (INTEL_INFO(dev)->gen >= 4 ||
2199             tiling_mode == I915_TILING_NONE)
2200                 return size;
2201
2202         /* Previous chips need a power-of-two fence region when tiling */
2203         if (IS_GEN3(dev))
2204                 gtt_size = 1024*1024;
2205         else
2206                 gtt_size = 512*1024;
2207
2208         while (gtt_size < size)
2209                 gtt_size <<= 1;
2210
2211         return gtt_size;
2212 }
2213
2214 /**
2215  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2216  * @dev: drm device
2217  * @size: object size
2218  * @tiling_mode: tiling mode
2219  * @fenced: is fenced alignemned required or not
2220  *
2221  * Return the required GTT alignment for an object, taking into account
2222  * potential fence register mapping.
2223  */
2224 uint32_t
2225 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2226                            int tiling_mode, bool fenced)
2227 {
2228         /*
2229          * Minimum alignment is 4k (GTT page size), but might be greater
2230          * if a fence register is needed for the object.
2231          */
2232         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2233             tiling_mode == I915_TILING_NONE)
2234                 return 4096;
2235
2236         /*
2237          * Previous chips need to be aligned to the size of the smallest
2238          * fence register that can contain the object.
2239          */
2240         return i915_gem_get_gtt_size(dev, size, tiling_mode);
2241 }
2242
2243 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2244 {
2245         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246         int ret;
2247
2248         dev_priv->mm.shrinker_no_lock_stealing = true;
2249
2250         ret = drm_gem_create_mmap_offset(&obj->base);
2251         if (ret != -ENOSPC)
2252                 goto out;
2253
2254         /* Badly fragmented mmap space? The only way we can recover
2255          * space is by destroying unwanted objects. We can't randomly release
2256          * mmap_offsets as userspace expects them to be persistent for the
2257          * lifetime of the objects. The closest we can is to release the
2258          * offsets on purgeable objects by truncating it and marking it purged,
2259          * which prevents userspace from ever using that object again.
2260          */
2261         i915_gem_shrink(dev_priv,
2262                         obj->base.size >> PAGE_SHIFT,
2263                         I915_SHRINK_BOUND |
2264                         I915_SHRINK_UNBOUND |
2265                         I915_SHRINK_PURGEABLE);
2266         ret = drm_gem_create_mmap_offset(&obj->base);
2267         if (ret != -ENOSPC)
2268                 goto out;
2269
2270         i915_gem_shrink_all(dev_priv);
2271         ret = drm_gem_create_mmap_offset(&obj->base);
2272 out:
2273         dev_priv->mm.shrinker_no_lock_stealing = false;
2274
2275         return ret;
2276 }
2277
2278 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2279 {
2280         drm_gem_free_mmap_offset(&obj->base);
2281 }
2282
2283 int
2284 i915_gem_mmap_gtt(struct drm_file *file,
2285                   struct drm_device *dev,
2286                   uint32_t handle,
2287                   uint64_t *offset)
2288 {
2289         struct drm_i915_gem_object *obj;
2290         int ret;
2291
2292         ret = i915_mutex_lock_interruptible(dev);
2293         if (ret)
2294                 return ret;
2295
2296         obj = to_intel_bo(drm_gem_object_lookup(file, handle));
2297         if (&obj->base == NULL) {
2298                 ret = -ENOENT;
2299                 goto unlock;
2300         }
2301
2302         if (obj->madv != I915_MADV_WILLNEED) {
2303                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2304                 ret = -EFAULT;
2305                 goto out;
2306         }
2307
2308         ret = i915_gem_object_create_mmap_offset(obj);
2309         if (ret)
2310                 goto out;
2311
2312         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2313
2314 out:
2315         drm_gem_object_unreference(&obj->base);
2316 unlock:
2317         mutex_unlock(&dev->struct_mutex);
2318         return ret;
2319 }
2320
2321 /**
2322  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2323  * @dev: DRM device
2324  * @data: GTT mapping ioctl data
2325  * @file: GEM object info
2326  *
2327  * Simply returns the fake offset to userspace so it can mmap it.
2328  * The mmap call will end up in drm_gem_mmap(), which will set things
2329  * up so we can get faults in the handler above.
2330  *
2331  * The fault handler will take care of binding the object into the GTT
2332  * (since it may have been evicted to make room for something), allocating
2333  * a fence register, and mapping the appropriate aperture address into
2334  * userspace.
2335  */
2336 int
2337 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2338                         struct drm_file *file)
2339 {
2340         struct drm_i915_gem_mmap_gtt *args = data;
2341
2342         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2343 }
2344
2345 /* Immediately discard the backing storage */
2346 static void
2347 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2348 {
2349         i915_gem_object_free_mmap_offset(obj);
2350
2351         if (obj->base.filp == NULL)
2352                 return;
2353
2354         /* Our goal here is to return as much of the memory as
2355          * is possible back to the system as we are called from OOM.
2356          * To do this we must instruct the shmfs to drop all of its
2357          * backing pages, *now*.
2358          */
2359         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2360         obj->madv = __I915_MADV_PURGED;
2361 }
2362
2363 /* Try to discard unwanted pages */
2364 static void
2365 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2366 {
2367         struct address_space *mapping;
2368
2369         switch (obj->madv) {
2370         case I915_MADV_DONTNEED:
2371                 i915_gem_object_truncate(obj);
2372         case __I915_MADV_PURGED:
2373                 return;
2374         }
2375
2376         if (obj->base.filp == NULL)
2377                 return;
2378
2379         mapping = file_inode(obj->base.filp)->i_mapping,
2380         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2381 }
2382
2383 static void
2384 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2385 {
2386         struct sgt_iter sgt_iter;
2387         struct page *page;
2388         int ret;
2389
2390         BUG_ON(obj->madv == __I915_MADV_PURGED);
2391
2392         ret = i915_gem_object_set_to_cpu_domain(obj, true);
2393         if (WARN_ON(ret)) {
2394                 /* In the event of a disaster, abandon all caches and
2395                  * hope for the best.
2396                  */
2397                 i915_gem_clflush_object(obj, true);
2398                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2399         }
2400
2401         i915_gem_gtt_finish_object(obj);
2402
2403         if (i915_gem_object_needs_bit17_swizzle(obj))
2404                 i915_gem_object_save_bit_17_swizzle(obj);
2405
2406         if (obj->madv == I915_MADV_DONTNEED)
2407                 obj->dirty = 0;
2408
2409         for_each_sgt_page(page, sgt_iter, obj->pages) {
2410                 if (obj->dirty)
2411                         set_page_dirty(page);
2412
2413                 if (obj->madv == I915_MADV_WILLNEED)
2414                         mark_page_accessed(page);
2415
2416                 put_page(page);
2417         }
2418         obj->dirty = 0;
2419
2420         sg_free_table(obj->pages);
2421         kfree(obj->pages);
2422 }
2423
2424 int
2425 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2426 {
2427         const struct drm_i915_gem_object_ops *ops = obj->ops;
2428
2429         if (obj->pages == NULL)
2430                 return 0;
2431
2432         if (obj->pages_pin_count)
2433                 return -EBUSY;
2434
2435         BUG_ON(i915_gem_obj_bound_any(obj));
2436
2437         /* ->put_pages might need to allocate memory for the bit17 swizzle
2438          * array, hence protect them from being reaped by removing them from gtt
2439          * lists early. */
2440         list_del(&obj->global_list);
2441
2442         if (obj->mapping) {
2443                 if (is_vmalloc_addr(obj->mapping))
2444                         vunmap(obj->mapping);
2445                 else
2446                         kunmap(kmap_to_page(obj->mapping));
2447                 obj->mapping = NULL;
2448         }
2449
2450         ops->put_pages(obj);
2451         obj->pages = NULL;
2452
2453         i915_gem_object_invalidate(obj);
2454
2455         return 0;
2456 }
2457
2458 static int
2459 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2460 {
2461         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2462         int page_count, i;
2463         struct address_space *mapping;
2464         struct sg_table *st;
2465         struct scatterlist *sg;
2466         struct sgt_iter sgt_iter;
2467         struct page *page;
2468         unsigned long last_pfn = 0;     /* suppress gcc warning */
2469         int ret;
2470         gfp_t gfp;
2471
2472         /* Assert that the object is not currently in any GPU domain. As it
2473          * wasn't in the GTT, there shouldn't be any way it could have been in
2474          * a GPU cache
2475          */
2476         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2477         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2478
2479         st = kmalloc(sizeof(*st), GFP_KERNEL);
2480         if (st == NULL)
2481                 return -ENOMEM;
2482
2483         page_count = obj->base.size / PAGE_SIZE;
2484         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2485                 kfree(st);
2486                 return -ENOMEM;
2487         }
2488
2489         /* Get the list of pages out of our struct file.  They'll be pinned
2490          * at this point until we release them.
2491          *
2492          * Fail silently without starting the shrinker
2493          */
2494         mapping = file_inode(obj->base.filp)->i_mapping;
2495         gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2496         gfp |= __GFP_NORETRY | __GFP_NOWARN;
2497         sg = st->sgl;
2498         st->nents = 0;
2499         for (i = 0; i < page_count; i++) {
2500                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2501                 if (IS_ERR(page)) {
2502                         i915_gem_shrink(dev_priv,
2503                                         page_count,
2504                                         I915_SHRINK_BOUND |
2505                                         I915_SHRINK_UNBOUND |
2506                                         I915_SHRINK_PURGEABLE);
2507                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2508                 }
2509                 if (IS_ERR(page)) {
2510                         /* We've tried hard to allocate the memory by reaping
2511                          * our own buffer, now let the real VM do its job and
2512                          * go down in flames if truly OOM.
2513                          */
2514                         i915_gem_shrink_all(dev_priv);
2515                         page = shmem_read_mapping_page(mapping, i);
2516                         if (IS_ERR(page)) {
2517                                 ret = PTR_ERR(page);
2518                                 goto err_pages;
2519                         }
2520                 }
2521 #ifdef CONFIG_SWIOTLB
2522                 if (swiotlb_nr_tbl()) {
2523                         st->nents++;
2524                         sg_set_page(sg, page, PAGE_SIZE, 0);
2525                         sg = sg_next(sg);
2526                         continue;
2527                 }
2528 #endif
2529                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2530                         if (i)
2531                                 sg = sg_next(sg);
2532                         st->nents++;
2533                         sg_set_page(sg, page, PAGE_SIZE, 0);
2534                 } else {
2535                         sg->length += PAGE_SIZE;
2536                 }
2537                 last_pfn = page_to_pfn(page);
2538
2539                 /* Check that the i965g/gm workaround works. */
2540                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2541         }
2542 #ifdef CONFIG_SWIOTLB
2543         if (!swiotlb_nr_tbl())
2544 #endif
2545                 sg_mark_end(sg);
2546         obj->pages = st;
2547
2548         ret = i915_gem_gtt_prepare_object(obj);
2549         if (ret)
2550                 goto err_pages;
2551
2552         if (i915_gem_object_needs_bit17_swizzle(obj))
2553                 i915_gem_object_do_bit_17_swizzle(obj);
2554
2555         if (obj->tiling_mode != I915_TILING_NONE &&
2556             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2557                 i915_gem_object_pin_pages(obj);
2558
2559         return 0;
2560
2561 err_pages:
2562         sg_mark_end(sg);
2563         for_each_sgt_page(page, sgt_iter, st)
2564                 put_page(page);
2565         sg_free_table(st);
2566         kfree(st);
2567
2568         /* shmemfs first checks if there is enough memory to allocate the page
2569          * and reports ENOSPC should there be insufficient, along with the usual
2570          * ENOMEM for a genuine allocation failure.
2571          *
2572          * We use ENOSPC in our driver to mean that we have run out of aperture
2573          * space and so want to translate the error from shmemfs back to our
2574          * usual understanding of ENOMEM.
2575          */
2576         if (ret == -ENOSPC)
2577                 ret = -ENOMEM;
2578
2579         return ret;
2580 }
2581
2582 /* Ensure that the associated pages are gathered from the backing storage
2583  * and pinned into our object. i915_gem_object_get_pages() may be called
2584  * multiple times before they are released by a single call to
2585  * i915_gem_object_put_pages() - once the pages are no longer referenced
2586  * either as a result of memory pressure (reaping pages under the shrinker)
2587  * or as the object is itself released.
2588  */
2589 int
2590 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2591 {
2592         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2593         const struct drm_i915_gem_object_ops *ops = obj->ops;
2594         int ret;
2595
2596         if (obj->pages)
2597                 return 0;
2598
2599         if (obj->madv != I915_MADV_WILLNEED) {
2600                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2601                 return -EFAULT;
2602         }
2603
2604         BUG_ON(obj->pages_pin_count);
2605
2606         ret = ops->get_pages(obj);
2607         if (ret)
2608                 return ret;
2609
2610         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2611
2612         obj->get_page.sg = obj->pages->sgl;
2613         obj->get_page.last = 0;
2614
2615         return 0;
2616 }
2617
2618 /* The 'mapping' part of i915_gem_object_pin_map() below */
2619 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj)
2620 {
2621         unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2622         struct sg_table *sgt = obj->pages;
2623         struct sgt_iter sgt_iter;
2624         struct page *page;
2625         struct page *stack_pages[32];
2626         struct page **pages = stack_pages;
2627         unsigned long i = 0;
2628         void *addr;
2629
2630         /* A single page can always be kmapped */
2631         if (n_pages == 1)
2632                 return kmap(sg_page(sgt->sgl));
2633
2634         if (n_pages > ARRAY_SIZE(stack_pages)) {
2635                 /* Too big for stack -- allocate temporary array instead */
2636                 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2637                 if (!pages)
2638                         return NULL;
2639         }
2640
2641         for_each_sgt_page(page, sgt_iter, sgt)
2642                 pages[i++] = page;
2643
2644         /* Check that we have the expected number of pages */
2645         GEM_BUG_ON(i != n_pages);
2646
2647         addr = vmap(pages, n_pages, 0, PAGE_KERNEL);
2648
2649         if (pages != stack_pages)
2650                 drm_free_large(pages);
2651
2652         return addr;
2653 }
2654
2655 /* get, pin, and map the pages of the object into kernel space */
2656 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2657 {
2658         int ret;
2659
2660         lockdep_assert_held(&obj->base.dev->struct_mutex);
2661
2662         ret = i915_gem_object_get_pages(obj);
2663         if (ret)
2664                 return ERR_PTR(ret);
2665
2666         i915_gem_object_pin_pages(obj);
2667
2668         if (!obj->mapping) {
2669                 obj->mapping = i915_gem_object_map(obj);
2670                 if (!obj->mapping) {
2671                         i915_gem_object_unpin_pages(obj);
2672                         return ERR_PTR(-ENOMEM);
2673                 }
2674         }
2675
2676         return obj->mapping;
2677 }
2678
2679 void i915_vma_move_to_active(struct i915_vma *vma,
2680                              struct drm_i915_gem_request *req)
2681 {
2682         struct drm_i915_gem_object *obj = vma->obj;
2683         struct intel_engine_cs *engine;
2684
2685         engine = i915_gem_request_get_engine(req);
2686
2687         /* Add a reference if we're newly entering the active list. */
2688         if (obj->active == 0)
2689                 drm_gem_object_reference(&obj->base);
2690         obj->active |= intel_engine_flag(engine);
2691
2692         list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2693         i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2694
2695         list_move_tail(&vma->vm_link, &vma->vm->active_list);
2696 }
2697
2698 static void
2699 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2700 {
2701         GEM_BUG_ON(obj->last_write_req == NULL);
2702         GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2703
2704         i915_gem_request_assign(&obj->last_write_req, NULL);
2705         intel_fb_obj_flush(obj, true, ORIGIN_CS);
2706 }
2707
2708 static void
2709 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2710 {
2711         struct i915_vma *vma;
2712
2713         GEM_BUG_ON(obj->last_read_req[ring] == NULL);
2714         GEM_BUG_ON(!(obj->active & (1 << ring)));
2715
2716         list_del_init(&obj->engine_list[ring]);
2717         i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2718
2719         if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2720                 i915_gem_object_retire__write(obj);
2721
2722         obj->active &= ~(1 << ring);
2723         if (obj->active)
2724                 return;
2725
2726         /* Bump our place on the bound list to keep it roughly in LRU order
2727          * so that we don't steal from recently used but inactive objects
2728          * (unless we are forced to ofc!)
2729          */
2730         list_move_tail(&obj->global_list,
2731                        &to_i915(obj->base.dev)->mm.bound_list);
2732
2733         list_for_each_entry(vma, &obj->vma_list, obj_link) {
2734                 if (!list_empty(&vma->vm_link))
2735                         list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2736         }
2737
2738         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2739         drm_gem_object_unreference(&obj->base);
2740 }
2741
2742 static int
2743 i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
2744 {
2745         struct intel_engine_cs *engine;
2746         int ret;
2747
2748         /* Carefully retire all requests without writing to the rings */
2749         for_each_engine(engine, dev_priv) {
2750                 ret = intel_engine_idle(engine);
2751                 if (ret)
2752                         return ret;
2753         }
2754         i915_gem_retire_requests(dev_priv);
2755
2756         /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
2757         if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) {
2758                 while (intel_kick_waiters(dev_priv) ||
2759                        intel_kick_signalers(dev_priv))
2760                         yield();
2761         }
2762
2763         /* Finally reset hw state */
2764         for_each_engine(engine, dev_priv)
2765                 intel_ring_init_seqno(engine, seqno);
2766
2767         return 0;
2768 }
2769
2770 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2771 {
2772         struct drm_i915_private *dev_priv = dev->dev_private;
2773         int ret;
2774
2775         if (seqno == 0)
2776                 return -EINVAL;
2777
2778         /* HWS page needs to be set less than what we
2779          * will inject to ring
2780          */
2781         ret = i915_gem_init_seqno(dev_priv, seqno - 1);
2782         if (ret)
2783                 return ret;
2784
2785         /* Carefully set the last_seqno value so that wrap
2786          * detection still works
2787          */
2788         dev_priv->next_seqno = seqno;
2789         dev_priv->last_seqno = seqno - 1;
2790         if (dev_priv->last_seqno == 0)
2791                 dev_priv->last_seqno--;
2792
2793         return 0;
2794 }
2795
2796 int
2797 i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
2798 {
2799         /* reserve 0 for non-seqno */
2800         if (dev_priv->next_seqno == 0) {
2801                 int ret = i915_gem_init_seqno(dev_priv, 0);
2802                 if (ret)
2803                         return ret;
2804
2805                 dev_priv->next_seqno = 1;
2806         }
2807
2808         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2809         return 0;
2810 }
2811
2812 static void i915_gem_mark_busy(const struct intel_engine_cs *engine)
2813 {
2814         struct drm_i915_private *dev_priv = engine->i915;
2815
2816         dev_priv->gt.active_engines |= intel_engine_flag(engine);
2817         if (dev_priv->gt.awake)
2818                 return;
2819
2820         intel_runtime_pm_get_noresume(dev_priv);
2821         dev_priv->gt.awake = true;
2822
2823         i915_update_gfx_val(dev_priv);
2824         if (INTEL_GEN(dev_priv) >= 6)
2825                 gen6_rps_busy(dev_priv);
2826
2827         queue_delayed_work(dev_priv->wq,
2828                            &dev_priv->gt.retire_work,
2829                            round_jiffies_up_relative(HZ));
2830 }
2831
2832 /*
2833  * NB: This function is not allowed to fail. Doing so would mean the the
2834  * request is not being tracked for completion but the work itself is
2835  * going to happen on the hardware. This would be a Bad Thing(tm).
2836  */
2837 void __i915_add_request(struct drm_i915_gem_request *request,
2838                         struct drm_i915_gem_object *obj,
2839                         bool flush_caches)
2840 {
2841         struct intel_engine_cs *engine;
2842         struct intel_ringbuffer *ringbuf;
2843         u32 request_start;
2844         u32 reserved_tail;
2845         int ret;
2846
2847         if (WARN_ON(request == NULL))
2848                 return;
2849
2850         engine = request->engine;
2851         ringbuf = request->ringbuf;
2852
2853         /*
2854          * To ensure that this call will not fail, space for its emissions
2855          * should already have been reserved in the ring buffer. Let the ring
2856          * know that it is time to use that space up.
2857          */
2858         request_start = intel_ring_get_tail(ringbuf);
2859         reserved_tail = request->reserved_space;
2860         request->reserved_space = 0;
2861
2862         /*
2863          * Emit any outstanding flushes - execbuf can fail to emit the flush
2864          * after having emitted the batchbuffer command. Hence we need to fix
2865          * things up similar to emitting the lazy request. The difference here
2866          * is that the flush _must_ happen before the next request, no matter
2867          * what.
2868          */
2869         if (flush_caches) {
2870                 if (i915.enable_execlists)
2871                         ret = logical_ring_flush_all_caches(request);
2872                 else
2873                         ret = intel_ring_flush_all_caches(request);
2874                 /* Not allowed to fail! */
2875                 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2876         }
2877
2878         trace_i915_gem_request_add(request);
2879
2880         request->head = request_start;
2881
2882         /* Whilst this request exists, batch_obj will be on the
2883          * active_list, and so will hold the active reference. Only when this
2884          * request is retired will the the batch_obj be moved onto the
2885          * inactive_list and lose its active reference. Hence we do not need
2886          * to explicitly hold another reference here.
2887          */
2888         request->batch_obj = obj;
2889
2890         /* Seal the request and mark it as pending execution. Note that
2891          * we may inspect this state, without holding any locks, during
2892          * hangcheck. Hence we apply the barrier to ensure that we do not
2893          * see a more recent value in the hws than we are tracking.
2894          */
2895         request->emitted_jiffies = jiffies;
2896         request->previous_seqno = engine->last_submitted_seqno;
2897         smp_store_mb(engine->last_submitted_seqno, request->seqno);
2898         list_add_tail(&request->list, &engine->request_list);
2899
2900         /* Record the position of the start of the request so that
2901          * should we detect the updated seqno part-way through the
2902          * GPU processing the request, we never over-estimate the
2903          * position of the head.
2904          */
2905         request->postfix = intel_ring_get_tail(ringbuf);
2906
2907         if (i915.enable_execlists)
2908                 ret = engine->emit_request(request);
2909         else {
2910                 ret = engine->add_request(request);
2911
2912                 request->tail = intel_ring_get_tail(ringbuf);
2913         }
2914         /* Not allowed to fail! */
2915         WARN(ret, "emit|add_request failed: %d!\n", ret);
2916         /* Sanity check that the reserved size was large enough. */
2917         ret = intel_ring_get_tail(ringbuf) - request_start;
2918         if (ret < 0)
2919                 ret += ringbuf->size;
2920         WARN_ONCE(ret > reserved_tail,
2921                   "Not enough space reserved (%d bytes) "
2922                   "for adding the request (%d bytes)\n",
2923                   reserved_tail, ret);
2924
2925         i915_gem_mark_busy(engine);
2926 }
2927
2928 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2929                                    const struct i915_gem_context *ctx)
2930 {
2931         unsigned long elapsed;
2932
2933         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2934
2935         if (ctx->hang_stats.banned)
2936                 return true;
2937
2938         if (ctx->hang_stats.ban_period_seconds &&
2939             elapsed <= ctx->hang_stats.ban_period_seconds) {
2940                 if (!i915_gem_context_is_default(ctx)) {
2941                         DRM_DEBUG("context hanging too fast, banning!\n");
2942                         return true;
2943                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2944                         if (i915_stop_ring_allow_warn(dev_priv))
2945                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2946                         return true;
2947                 }
2948         }
2949
2950         return false;
2951 }
2952
2953 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2954                                   struct i915_gem_context *ctx,
2955                                   const bool guilty)
2956 {
2957         struct i915_ctx_hang_stats *hs;
2958
2959         if (WARN_ON(!ctx))
2960                 return;
2961
2962         hs = &ctx->hang_stats;
2963
2964         if (guilty) {
2965                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2966                 hs->batch_active++;
2967                 hs->guilty_ts = get_seconds();
2968         } else {
2969                 hs->batch_pending++;
2970         }
2971 }
2972
2973 void i915_gem_request_free(struct kref *req_ref)
2974 {
2975         struct drm_i915_gem_request *req = container_of(req_ref,
2976                                                  typeof(*req), ref);
2977         kmem_cache_free(req->i915->requests, req);
2978 }
2979
2980 static inline int
2981 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2982                          struct i915_gem_context *ctx,
2983                          struct drm_i915_gem_request **req_out)
2984 {
2985         struct drm_i915_private *dev_priv = engine->i915;
2986         unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
2987         struct drm_i915_gem_request *req;
2988         int ret;
2989
2990         if (!req_out)
2991                 return -EINVAL;
2992
2993         *req_out = NULL;
2994
2995         /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2996          * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2997          * and restart.
2998          */
2999         ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
3000         if (ret)
3001                 return ret;
3002
3003         req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
3004         if (req == NULL)
3005                 return -ENOMEM;
3006
3007         ret = i915_gem_get_seqno(engine->i915, &req->seqno);
3008         if (ret)
3009                 goto err;
3010
3011         kref_init(&req->ref);
3012         req->i915 = dev_priv;
3013         req->engine = engine;
3014         req->ctx  = ctx;
3015         i915_gem_context_reference(req->ctx);
3016
3017         /*
3018          * Reserve space in the ring buffer for all the commands required to
3019          * eventually emit this request. This is to guarantee that the
3020          * i915_add_request() call can't fail. Note that the reserve may need
3021          * to be redone if the request is not actually submitted straight
3022          * away, e.g. because a GPU scheduler has deferred it.
3023          */
3024         req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
3025
3026         if (i915.enable_execlists)
3027                 ret = intel_logical_ring_alloc_request_extras(req);
3028         else
3029                 ret = intel_ring_alloc_request_extras(req);
3030         if (ret)
3031                 goto err_ctx;
3032
3033         *req_out = req;
3034         return 0;
3035
3036 err_ctx:
3037         i915_gem_context_unreference(ctx);
3038 err:
3039         kmem_cache_free(dev_priv->requests, req);
3040         return ret;
3041 }
3042
3043 /**
3044  * i915_gem_request_alloc - allocate a request structure
3045  *
3046  * @engine: engine that we wish to issue the request on.
3047  * @ctx: context that the request will be associated with.
3048  *       This can be NULL if the request is not directly related to
3049  *       any specific user context, in which case this function will
3050  *       choose an appropriate context to use.
3051  *
3052  * Returns a pointer to the allocated request if successful,
3053  * or an error code if not.
3054  */
3055 struct drm_i915_gem_request *
3056 i915_gem_request_alloc(struct intel_engine_cs *engine,
3057                        struct i915_gem_context *ctx)
3058 {
3059         struct drm_i915_gem_request *req;
3060         int err;
3061
3062         if (ctx == NULL)
3063                 ctx = engine->i915->kernel_context;
3064         err = __i915_gem_request_alloc(engine, ctx, &req);
3065         return err ? ERR_PTR(err) : req;
3066 }
3067
3068 struct drm_i915_gem_request *
3069 i915_gem_find_active_request(struct intel_engine_cs *engine)
3070 {
3071         struct drm_i915_gem_request *request;
3072
3073         /* We are called by the error capture and reset at a random
3074          * point in time. In particular, note that neither is crucially
3075          * ordered with an interrupt. After a hang, the GPU is dead and we
3076          * assume that no more writes can happen (we waited long enough for
3077          * all writes that were in transaction to be flushed) - adding an
3078          * extra delay for a recent interrupt is pointless. Hence, we do
3079          * not need an engine->irq_seqno_barrier() before the seqno reads.
3080          */
3081         list_for_each_entry(request, &engine->request_list, list) {
3082                 if (i915_gem_request_completed(request))
3083                         continue;
3084
3085                 return request;
3086         }
3087
3088         return NULL;
3089 }
3090
3091 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
3092                                        struct intel_engine_cs *engine)
3093 {
3094         struct drm_i915_gem_request *request;
3095         bool ring_hung;
3096
3097         request = i915_gem_find_active_request(engine);
3098
3099         if (request == NULL)
3100                 return;
3101
3102         ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
3103
3104         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
3105
3106         list_for_each_entry_continue(request, &engine->request_list, list)
3107                 i915_set_reset_status(dev_priv, request->ctx, false);
3108 }
3109
3110 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
3111                                         struct intel_engine_cs *engine)
3112 {
3113         struct intel_ringbuffer *buffer;
3114
3115         while (!list_empty(&engine->active_list)) {
3116                 struct drm_i915_gem_object *obj;
3117
3118                 obj = list_first_entry(&engine->active_list,
3119                                        struct drm_i915_gem_object,
3120                                        engine_list[engine->id]);
3121
3122                 i915_gem_object_retire__read(obj, engine->id);
3123         }
3124
3125         /*
3126          * Clear the execlists queue up before freeing the requests, as those
3127          * are the ones that keep the context and ringbuffer backing objects
3128          * pinned in place.
3129          */
3130
3131         if (i915.enable_execlists) {
3132                 /* Ensure irq handler finishes or is cancelled. */
3133                 tasklet_kill(&engine->irq_tasklet);
3134
3135                 intel_execlists_cancel_requests(engine);
3136         }
3137
3138         /*
3139          * We must free the requests after all the corresponding objects have
3140          * been moved off active lists. Which is the same order as the normal
3141          * retire_requests function does. This is important if object hold
3142          * implicit references on things like e.g. ppgtt address spaces through
3143          * the request.
3144          */
3145         while (!list_empty(&engine->request_list)) {
3146                 struct drm_i915_gem_request *request;
3147
3148                 request = list_first_entry(&engine->request_list,
3149                                            struct drm_i915_gem_request,
3150                                            list);
3151
3152                 i915_gem_request_retire(request);
3153         }
3154
3155         /* Having flushed all requests from all queues, we know that all
3156          * ringbuffers must now be empty. However, since we do not reclaim
3157          * all space when retiring the request (to prevent HEADs colliding
3158          * with rapid ringbuffer wraparound) the amount of available space
3159          * upon reset is less than when we start. Do one more pass over
3160          * all the ringbuffers to reset last_retired_head.
3161          */
3162         list_for_each_entry(buffer, &engine->buffers, link) {
3163                 buffer->last_retired_head = buffer->tail;
3164                 intel_ring_update_space(buffer);
3165         }
3166
3167         intel_ring_init_seqno(engine, engine->last_submitted_seqno);
3168 }
3169
3170 void i915_gem_reset(struct drm_device *dev)
3171 {
3172         struct drm_i915_private *dev_priv = dev->dev_private;
3173         struct intel_engine_cs *engine;
3174
3175         /*
3176          * Before we free the objects from the requests, we need to inspect
3177          * them for finding the guilty party. As the requests only borrow
3178          * their reference to the objects, the inspection must be done first.
3179          */
3180         for_each_engine(engine, dev_priv)
3181                 i915_gem_reset_engine_status(dev_priv, engine);
3182
3183         for_each_engine(engine, dev_priv)
3184                 i915_gem_reset_engine_cleanup(dev_priv, engine);
3185
3186         i915_gem_context_reset(dev);
3187
3188         i915_gem_restore_fences(dev);
3189
3190         WARN_ON(i915_verify_lists(dev));
3191 }
3192
3193 /**
3194  * This function clears the request list as sequence numbers are passed.
3195  * @engine: engine to retire requests on
3196  */
3197 void
3198 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
3199 {
3200         WARN_ON(i915_verify_lists(engine->dev));
3201
3202         /* Retire requests first as we use it above for the early return.
3203          * If we retire requests last, we may use a later seqno and so clear
3204          * the requests lists without clearing the active list, leading to
3205          * confusion.
3206          */
3207         while (!list_empty(&engine->request_list)) {
3208                 struct drm_i915_gem_request *request;
3209
3210                 request = list_first_entry(&engine->request_list,
3211                                            struct drm_i915_gem_request,
3212                                            list);
3213
3214                 if (!i915_gem_request_completed(request))
3215                         break;
3216
3217                 i915_gem_request_retire(request);
3218         }
3219
3220         /* Move any buffers on the active list that are no longer referenced
3221          * by the ringbuffer to the flushing/inactive lists as appropriate,
3222          * before we free the context associated with the requests.
3223          */
3224         while (!list_empty(&engine->active_list)) {
3225                 struct drm_i915_gem_object *obj;
3226
3227                 obj = list_first_entry(&engine->active_list,
3228                                        struct drm_i915_gem_object,
3229                                        engine_list[engine->id]);
3230
3231                 if (!list_empty(&obj->last_read_req[engine->id]->list))
3232                         break;
3233
3234                 i915_gem_object_retire__read(obj, engine->id);
3235         }
3236
3237         WARN_ON(i915_verify_lists(engine->dev));
3238 }
3239
3240 void i915_gem_retire_requests(struct drm_i915_private *dev_priv)
3241 {
3242         struct intel_engine_cs *engine;
3243
3244         lockdep_assert_held(&dev_priv->dev->struct_mutex);
3245
3246         if (dev_priv->gt.active_engines == 0)
3247                 return;
3248
3249         GEM_BUG_ON(!dev_priv->gt.awake);
3250
3251         for_each_engine(engine, dev_priv) {
3252                 i915_gem_retire_requests_ring(engine);
3253                 if (list_empty(&engine->request_list))
3254                         dev_priv->gt.active_engines &= ~intel_engine_flag(engine);
3255         }
3256
3257         if (dev_priv->gt.active_engines == 0)
3258                 queue_delayed_work(dev_priv->wq,
3259                                    &dev_priv->gt.idle_work,
3260                                    msecs_to_jiffies(100));
3261 }
3262
3263 static void
3264 i915_gem_retire_work_handler(struct work_struct *work)
3265 {
3266         struct drm_i915_private *dev_priv =
3267                 container_of(work, typeof(*dev_priv), gt.retire_work.work);
3268         struct drm_device *dev = dev_priv->dev;
3269
3270         /* Come back later if the device is busy... */
3271         if (mutex_trylock(&dev->struct_mutex)) {
3272                 i915_gem_retire_requests(dev_priv);
3273                 mutex_unlock(&dev->struct_mutex);
3274         }
3275
3276         /* Keep the retire handler running until we are finally idle.
3277          * We do not need to do this test under locking as in the worst-case
3278          * we queue the retire worker once too often.
3279          */
3280         if (lockless_dereference(dev_priv->gt.awake))
3281                 queue_delayed_work(dev_priv->wq,
3282                                    &dev_priv->gt.retire_work,
3283                                    round_jiffies_up_relative(HZ));
3284 }
3285
3286 static void
3287 i915_gem_idle_work_handler(struct work_struct *work)
3288 {
3289         struct drm_i915_private *dev_priv =
3290                 container_of(work, typeof(*dev_priv), gt.idle_work.work);
3291         struct drm_device *dev = dev_priv->dev;
3292         struct intel_engine_cs *engine;
3293         unsigned int stuck_engines;
3294         bool rearm_hangcheck;
3295
3296         if (!READ_ONCE(dev_priv->gt.awake))
3297                 return;
3298
3299         if (READ_ONCE(dev_priv->gt.active_engines))
3300                 return;
3301
3302         rearm_hangcheck =
3303                 cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
3304
3305         if (!mutex_trylock(&dev->struct_mutex)) {
3306                 /* Currently busy, come back later */
3307                 mod_delayed_work(dev_priv->wq,
3308                                  &dev_priv->gt.idle_work,
3309                                  msecs_to_jiffies(50));
3310                 goto out_rearm;
3311         }
3312
3313         if (dev_priv->gt.active_engines)
3314                 goto out_unlock;
3315
3316         for_each_engine(engine, dev_priv)
3317                 i915_gem_batch_pool_fini(&engine->batch_pool);
3318
3319         GEM_BUG_ON(!dev_priv->gt.awake);
3320         dev_priv->gt.awake = false;
3321         rearm_hangcheck = false;
3322
3323         stuck_engines = intel_kick_waiters(dev_priv);
3324         if (unlikely(stuck_engines)) {
3325                 DRM_DEBUG_DRIVER("kicked stuck waiters...missed irq\n");
3326                 dev_priv->gpu_error.missed_irq_rings |= stuck_engines;
3327         }
3328
3329         if (INTEL_GEN(dev_priv) >= 6)
3330                 gen6_rps_idle(dev_priv);
3331         intel_runtime_pm_put(dev_priv);
3332 out_unlock:
3333         mutex_unlock(&dev->struct_mutex);
3334
3335 out_rearm:
3336         if (rearm_hangcheck) {
3337                 GEM_BUG_ON(!dev_priv->gt.awake);
3338                 i915_queue_hangcheck(dev_priv);
3339         }
3340 }
3341
3342 /**
3343  * Ensures that an object will eventually get non-busy by flushing any required
3344  * write domains, emitting any outstanding lazy request and retiring and
3345  * completed requests.
3346  * @obj: object to flush
3347  */
3348 static int
3349 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3350 {
3351         int i;
3352
3353         if (!obj->active)
3354                 return 0;
3355
3356         for (i = 0; i < I915_NUM_ENGINES; i++) {
3357                 struct drm_i915_gem_request *req;
3358
3359                 req = obj->last_read_req[i];
3360                 if (req == NULL)
3361                         continue;
3362
3363                 if (i915_gem_request_completed(req))
3364                         i915_gem_object_retire__read(obj, i);
3365         }
3366
3367         return 0;
3368 }
3369
3370 /**
3371  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3372  * @dev: drm device pointer
3373  * @data: ioctl data blob
3374  * @file: drm file pointer
3375  *
3376  * Returns 0 if successful, else an error is returned with the remaining time in
3377  * the timeout parameter.
3378  *  -ETIME: object is still busy after timeout
3379  *  -ERESTARTSYS: signal interrupted the wait
3380  *  -ENONENT: object doesn't exist
3381  * Also possible, but rare:
3382  *  -EAGAIN: GPU wedged
3383  *  -ENOMEM: damn
3384  *  -ENODEV: Internal IRQ fail
3385  *  -E?: The add request failed
3386  *
3387  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3388  * non-zero timeout parameter the wait ioctl will wait for the given number of
3389  * nanoseconds on an object becoming unbusy. Since the wait itself does so
3390  * without holding struct_mutex the object may become re-busied before this
3391  * function completes. A similar but shorter * race condition exists in the busy
3392  * ioctl
3393  */
3394 int
3395 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3396 {
3397         struct drm_i915_gem_wait *args = data;
3398         struct drm_i915_gem_object *obj;
3399         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3400         int i, n = 0;
3401         int ret;
3402
3403         if (args->flags != 0)
3404                 return -EINVAL;
3405
3406         ret = i915_mutex_lock_interruptible(dev);
3407         if (ret)
3408                 return ret;
3409
3410         obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle));
3411         if (&obj->base == NULL) {
3412                 mutex_unlock(&dev->struct_mutex);
3413                 return -ENOENT;
3414         }
3415
3416         /* Need to make sure the object gets inactive eventually. */
3417         ret = i915_gem_object_flush_active(obj);
3418         if (ret)
3419                 goto out;
3420
3421         if (!obj->active)
3422                 goto out;
3423
3424         /* Do this after OLR check to make sure we make forward progress polling
3425          * on this IOCTL with a timeout == 0 (like busy ioctl)
3426          */
3427         if (args->timeout_ns == 0) {
3428                 ret = -ETIME;
3429                 goto out;
3430         }
3431
3432         drm_gem_object_unreference(&obj->base);
3433
3434         for (i = 0; i < I915_NUM_ENGINES; i++) {
3435                 if (obj->last_read_req[i] == NULL)
3436                         continue;
3437
3438                 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3439         }
3440
3441         mutex_unlock(&dev->struct_mutex);
3442
3443         for (i = 0; i < n; i++) {
3444                 if (ret == 0)
3445                         ret = __i915_wait_request(req[i], true,
3446                                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3447                                                   to_rps_client(file));
3448                 i915_gem_request_unreference(req[i]);
3449         }
3450         return ret;
3451
3452 out:
3453         drm_gem_object_unreference(&obj->base);
3454         mutex_unlock(&dev->struct_mutex);
3455         return ret;
3456 }
3457
3458 static int
3459 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3460                        struct intel_engine_cs *to,
3461                        struct drm_i915_gem_request *from_req,
3462                        struct drm_i915_gem_request **to_req)
3463 {
3464         struct intel_engine_cs *from;
3465         int ret;
3466
3467         from = i915_gem_request_get_engine(from_req);
3468         if (to == from)
3469                 return 0;
3470
3471         if (i915_gem_request_completed(from_req))
3472                 return 0;
3473
3474         if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
3475                 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3476                 ret = __i915_wait_request(from_req,
3477                                           i915->mm.interruptible,
3478                                           NULL,
3479                                           &i915->rps.semaphores);
3480                 if (ret)
3481                         return ret;
3482
3483                 i915_gem_object_retire_request(obj, from_req);
3484         } else {
3485                 int idx = intel_ring_sync_index(from, to);
3486                 u32 seqno = i915_gem_request_get_seqno(from_req);
3487
3488                 WARN_ON(!to_req);
3489
3490                 if (seqno <= from->semaphore.sync_seqno[idx])
3491                         return 0;
3492
3493                 if (*to_req == NULL) {
3494                         struct drm_i915_gem_request *req;
3495
3496                         req = i915_gem_request_alloc(to, NULL);
3497                         if (IS_ERR(req))
3498                                 return PTR_ERR(req);
3499
3500                         *to_req = req;
3501                 }
3502
3503                 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3504                 ret = to->semaphore.sync_to(*to_req, from, seqno);
3505                 if (ret)
3506                         return ret;
3507
3508                 /* We use last_read_req because sync_to()
3509                  * might have just caused seqno wrap under
3510                  * the radar.
3511                  */
3512                 from->semaphore.sync_seqno[idx] =
3513                         i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3514         }
3515
3516         return 0;
3517 }
3518
3519 /**
3520  * i915_gem_object_sync - sync an object to a ring.
3521  *
3522  * @obj: object which may be in use on another ring.
3523  * @to: ring we wish to use the object on. May be NULL.
3524  * @to_req: request we wish to use the object for. See below.
3525  *          This will be allocated and returned if a request is
3526  *          required but not passed in.
3527  *
3528  * This code is meant to abstract object synchronization with the GPU.
3529  * Calling with NULL implies synchronizing the object with the CPU
3530  * rather than a particular GPU ring. Conceptually we serialise writes
3531  * between engines inside the GPU. We only allow one engine to write
3532  * into a buffer at any time, but multiple readers. To ensure each has
3533  * a coherent view of memory, we must:
3534  *
3535  * - If there is an outstanding write request to the object, the new
3536  *   request must wait for it to complete (either CPU or in hw, requests
3537  *   on the same ring will be naturally ordered).
3538  *
3539  * - If we are a write request (pending_write_domain is set), the new
3540  *   request must wait for outstanding read requests to complete.
3541  *
3542  * For CPU synchronisation (NULL to) no request is required. For syncing with
3543  * rings to_req must be non-NULL. However, a request does not have to be
3544  * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3545  * request will be allocated automatically and returned through *to_req. Note
3546  * that it is not guaranteed that commands will be emitted (because the system
3547  * might already be idle). Hence there is no need to create a request that
3548  * might never have any work submitted. Note further that if a request is
3549  * returned in *to_req, it is the responsibility of the caller to submit
3550  * that request (after potentially adding more work to it).
3551  *
3552  * Returns 0 if successful, else propagates up the lower layer error.
3553  */
3554 int
3555 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3556                      struct intel_engine_cs *to,
3557                      struct drm_i915_gem_request **to_req)
3558 {
3559         const bool readonly = obj->base.pending_write_domain == 0;
3560         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3561         int ret, i, n;
3562
3563         if (!obj->active)
3564                 return 0;
3565
3566         if (to == NULL)
3567                 return i915_gem_object_wait_rendering(obj, readonly);
3568
3569         n = 0;
3570         if (readonly) {
3571                 if (obj->last_write_req)
3572                         req[n++] = obj->last_write_req;
3573         } else {
3574                 for (i = 0; i < I915_NUM_ENGINES; i++)
3575                         if (obj->last_read_req[i])
3576                                 req[n++] = obj->last_read_req[i];
3577         }
3578         for (i = 0; i < n; i++) {
3579                 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3580                 if (ret)
3581                         return ret;
3582         }
3583
3584         return 0;
3585 }
3586
3587 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3588 {
3589         u32 old_write_domain, old_read_domains;
3590
3591         /* Force a pagefault for domain tracking on next user access */
3592         i915_gem_release_mmap(obj);
3593
3594         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3595                 return;
3596
3597         old_read_domains = obj->base.read_domains;
3598         old_write_domain = obj->base.write_domain;
3599
3600         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3601         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3602
3603         trace_i915_gem_object_change_domain(obj,
3604                                             old_read_domains,
3605                                             old_write_domain);
3606 }
3607
3608 static void __i915_vma_iounmap(struct i915_vma *vma)
3609 {
3610         GEM_BUG_ON(vma->pin_count);
3611
3612         if (vma->iomap == NULL)
3613                 return;
3614
3615         io_mapping_unmap(vma->iomap);
3616         vma->iomap = NULL;
3617 }
3618
3619 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3620 {
3621         struct drm_i915_gem_object *obj = vma->obj;
3622         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3623         int ret;
3624
3625         if (list_empty(&vma->obj_link))
3626                 return 0;
3627
3628         if (!drm_mm_node_allocated(&vma->node)) {
3629                 i915_gem_vma_destroy(vma);
3630                 return 0;
3631         }
3632
3633         if (vma->pin_count)
3634                 return -EBUSY;
3635
3636         BUG_ON(obj->pages == NULL);
3637
3638         if (wait) {
3639                 ret = i915_gem_object_wait_rendering(obj, false);
3640                 if (ret)
3641                         return ret;
3642         }
3643
3644         if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3645                 i915_gem_object_finish_gtt(obj);
3646
3647                 /* release the fence reg _after_ flushing */
3648                 ret = i915_gem_object_put_fence(obj);
3649                 if (ret)
3650                         return ret;
3651
3652                 __i915_vma_iounmap(vma);
3653         }
3654
3655         trace_i915_vma_unbind(vma);
3656
3657         vma->vm->unbind_vma(vma);
3658         vma->bound = 0;
3659
3660         list_del_init(&vma->vm_link);
3661         if (vma->is_ggtt) {
3662                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3663                         obj->map_and_fenceable = false;
3664                 } else if (vma->ggtt_view.pages) {
3665                         sg_free_table(vma->ggtt_view.pages);
3666                         kfree(vma->ggtt_view.pages);
3667                 }
3668                 vma->ggtt_view.pages = NULL;
3669         }
3670
3671         drm_mm_remove_node(&vma->node);
3672         i915_gem_vma_destroy(vma);
3673
3674         /* Since the unbound list is global, only move to that list if
3675          * no more VMAs exist. */
3676         if (list_empty(&obj->vma_list))
3677                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3678
3679         /* And finally now the object is completely decoupled from this vma,
3680          * we can drop its hold on the backing storage and allow it to be
3681          * reaped by the shrinker.
3682          */
3683         i915_gem_object_unpin_pages(obj);
3684
3685         return 0;
3686 }
3687
3688 int i915_vma_unbind(struct i915_vma *vma)
3689 {
3690         return __i915_vma_unbind(vma, true);
3691 }
3692
3693 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3694 {
3695         return __i915_vma_unbind(vma, false);
3696 }
3697
3698 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
3699 {
3700         struct intel_engine_cs *engine;
3701         int ret;
3702
3703         lockdep_assert_held(&dev_priv->dev->struct_mutex);
3704
3705         for_each_engine(engine, dev_priv) {
3706                 if (engine->last_context == NULL)
3707                         continue;
3708
3709                 ret = intel_engine_idle(engine);
3710                 if (ret)
3711                         return ret;
3712         }
3713
3714         WARN_ON(i915_verify_lists(dev));
3715         return 0;
3716 }
3717
3718 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3719                                      unsigned long cache_level)
3720 {
3721         struct drm_mm_node *gtt_space = &vma->node;
3722         struct drm_mm_node *other;
3723
3724         /*
3725          * On some machines we have to be careful when putting differing types
3726          * of snoopable memory together to avoid the prefetcher crossing memory
3727          * domains and dying. During vm initialisation, we decide whether or not
3728          * these constraints apply and set the drm_mm.color_adjust
3729          * appropriately.
3730          */
3731         if (vma->vm->mm.color_adjust == NULL)
3732                 return true;
3733
3734         if (!drm_mm_node_allocated(gtt_space))
3735                 return true;
3736
3737         if (list_empty(&gtt_space->node_list))
3738                 return true;
3739
3740         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3741         if (other->allocated && !other->hole_follows && other->color != cache_level)
3742                 return false;
3743
3744         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3745         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3746                 return false;
3747
3748         return true;
3749 }
3750
3751 /**
3752  * Finds free space in the GTT aperture and binds the object or a view of it
3753  * there.
3754  * @obj: object to bind
3755  * @vm: address space to bind into
3756  * @ggtt_view: global gtt view if applicable
3757  * @alignment: requested alignment
3758  * @flags: mask of PIN_* flags to use
3759  */
3760 static struct i915_vma *
3761 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3762                            struct i915_address_space *vm,
3763                            const struct i915_ggtt_view *ggtt_view,
3764                            unsigned alignment,
3765                            uint64_t flags)
3766 {
3767         struct drm_device *dev = obj->base.dev;
3768         struct drm_i915_private *dev_priv = to_i915(dev);
3769         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3770         u32 fence_alignment, unfenced_alignment;
3771         u32 search_flag, alloc_flag;
3772         u64 start, end;
3773         u64 size, fence_size;
3774         struct i915_vma *vma;
3775         int ret;
3776
3777         if (i915_is_ggtt(vm)) {
3778                 u32 view_size;
3779
3780                 if (WARN_ON(!ggtt_view))
3781                         return ERR_PTR(-EINVAL);
3782
3783                 view_size = i915_ggtt_view_size(obj, ggtt_view);
3784
3785                 fence_size = i915_gem_get_gtt_size(dev,
3786                                                    view_size,
3787                                                    obj->tiling_mode);
3788                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3789                                                              view_size,
3790                                                              obj->tiling_mode,
3791                                                              true);
3792                 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3793                                                                 view_size,
3794                                                                 obj->tiling_mode,
3795                                                                 false);
3796                 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3797         } else {
3798                 fence_size = i915_gem_get_gtt_size(dev,
3799                                                    obj->base.size,
3800                                                    obj->tiling_mode);
3801                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3802                                                              obj->base.size,
3803                                                              obj->tiling_mode,
3804                                                              true);
3805                 unfenced_alignment =
3806                         i915_gem_get_gtt_alignment(dev,
3807                                                    obj->base.size,
3808                                                    obj->tiling_mode,
3809                                                    false);
3810                 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3811         }
3812
3813         start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3814         end = vm->total;
3815         if (flags & PIN_MAPPABLE)
3816                 end = min_t(u64, end, ggtt->mappable_end);
3817         if (flags & PIN_ZONE_4G)
3818                 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3819
3820         if (alignment == 0)
3821                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3822                                                 unfenced_alignment;
3823         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3824                 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3825                           ggtt_view ? ggtt_view->type : 0,
3826                           alignment);
3827                 return ERR_PTR(-EINVAL);
3828         }
3829
3830         /* If binding the object/GGTT view requires more space than the entire
3831          * aperture has, reject it early before evicting everything in a vain
3832          * attempt to find space.
3833          */
3834         if (size > end) {
3835                 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3836                           ggtt_view ? ggtt_view->type : 0,
3837                           size,
3838                           flags & PIN_MAPPABLE ? "mappable" : "total",
3839                           end);
3840                 return ERR_PTR(-E2BIG);
3841         }
3842
3843         ret = i915_gem_object_get_pages(obj);
3844         if (ret)
3845                 return ERR_PTR(ret);
3846
3847         i915_gem_object_pin_pages(obj);
3848
3849         vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3850                           i915_gem_obj_lookup_or_create_vma(obj, vm);
3851
3852         if (IS_ERR(vma))
3853                 goto err_unpin;
3854
3855         if (flags & PIN_OFFSET_FIXED) {
3856                 uint64_t offset = flags & PIN_OFFSET_MASK;
3857
3858                 if (offset & (alignment - 1) || offset + size > end) {
3859                         ret = -EINVAL;
3860                         goto err_free_vma;
3861                 }
3862                 vma->node.start = offset;
3863                 vma->node.size = size;
3864                 vma->node.color = obj->cache_level;
3865                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3866                 if (ret) {
3867                         ret = i915_gem_evict_for_vma(vma);
3868                         if (ret == 0)
3869                                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3870                 }
3871                 if (ret)
3872                         goto err_free_vma;
3873         } else {
3874                 if (flags & PIN_HIGH) {
3875                         search_flag = DRM_MM_SEARCH_BELOW;
3876                         alloc_flag = DRM_MM_CREATE_TOP;
3877                 } else {
3878                         search_flag = DRM_MM_SEARCH_DEFAULT;
3879                         alloc_flag = DRM_MM_CREATE_DEFAULT;
3880                 }
3881
3882 search_free:
3883                 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3884                                                           size, alignment,
3885                                                           obj->cache_level,
3886                                                           start, end,
3887                                                           search_flag,
3888                                                           alloc_flag);
3889                 if (ret) {
3890                         ret = i915_gem_evict_something(dev, vm, size, alignment,
3891                                                        obj->cache_level,
3892                                                        start, end,
3893                                                        flags);
3894                         if (ret == 0)
3895                                 goto search_free;
3896
3897                         goto err_free_vma;
3898                 }
3899         }
3900         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3901                 ret = -EINVAL;
3902                 goto err_remove_node;
3903         }
3904
3905         trace_i915_vma_bind(vma, flags);
3906         ret = i915_vma_bind(vma, obj->cache_level, flags);
3907         if (ret)
3908                 goto err_remove_node;
3909
3910         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3911         list_add_tail(&vma->vm_link, &vm->inactive_list);
3912
3913         return vma;
3914
3915 err_remove_node:
3916         drm_mm_remove_node(&vma->node);
3917 err_free_vma:
3918         i915_gem_vma_destroy(vma);
3919         vma = ERR_PTR(ret);
3920 err_unpin:
3921         i915_gem_object_unpin_pages(obj);
3922         return vma;
3923 }
3924
3925 bool
3926 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3927                         bool force)
3928 {
3929         /* If we don't have a page list set up, then we're not pinned
3930          * to GPU, and we can ignore the cache flush because it'll happen
3931          * again at bind time.
3932          */
3933         if (obj->pages == NULL)
3934                 return false;
3935
3936         /*
3937          * Stolen memory is always coherent with the GPU as it is explicitly
3938          * marked as wc by the system, or the system is cache-coherent.
3939          */
3940         if (obj->stolen || obj->phys_handle)
3941                 return false;
3942
3943         /* If the GPU is snooping the contents of the CPU cache,
3944          * we do not need to manually clear the CPU cache lines.  However,
3945          * the caches are only snooped when the render cache is
3946          * flushed/invalidated.  As we always have to emit invalidations
3947          * and flushes when moving into and out of the RENDER domain, correct
3948          * snooping behaviour occurs naturally as the result of our domain
3949          * tracking.
3950          */
3951         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3952                 obj->cache_dirty = true;
3953                 return false;
3954         }
3955
3956         trace_i915_gem_object_clflush(obj);
3957         drm_clflush_sg(obj->pages);
3958         obj->cache_dirty = false;
3959
3960         return true;
3961 }
3962
3963 /** Flushes the GTT write domain for the object if it's dirty. */
3964 static void
3965 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3966 {
3967         uint32_t old_write_domain;
3968
3969         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3970                 return;
3971
3972         /* No actual flushing is required for the GTT write domain.  Writes
3973          * to it immediately go to main memory as far as we know, so there's
3974          * no chipset flush.  It also doesn't land in render cache.
3975          *
3976          * However, we do have to enforce the order so that all writes through
3977          * the GTT land before any writes to the device, such as updates to
3978          * the GATT itself.
3979          */
3980         wmb();
3981
3982         old_write_domain = obj->base.write_domain;
3983         obj->base.write_domain = 0;
3984
3985         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3986
3987         trace_i915_gem_object_change_domain(obj,
3988                                             obj->base.read_domains,
3989                                             old_write_domain);
3990 }
3991
3992 /** Flushes the CPU write domain for the object if it's dirty. */
3993 static void
3994 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3995 {
3996         uint32_t old_write_domain;
3997
3998         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3999                 return;
4000
4001         if (i915_gem_clflush_object(obj, obj->pin_display))
4002                 i915_gem_chipset_flush(to_i915(obj->base.dev));
4003
4004         old_write_domain = obj->base.write_domain;
4005         obj->base.write_domain = 0;
4006
4007         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
4008
4009         trace_i915_gem_object_change_domain(obj,
4010                                             obj->base.read_domains,
4011                                             old_write_domain);
4012 }
4013
4014 /**
4015  * Moves a single object to the GTT read, and possibly write domain.
4016  * @obj: object to act on
4017  * @write: ask for write access or read only
4018  *
4019  * This function returns when the move is complete, including waiting on
4020  * flushes to occur.
4021  */
4022 int
4023 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
4024 {
4025         struct drm_device *dev = obj->base.dev;
4026         struct drm_i915_private *dev_priv = to_i915(dev);
4027         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4028         uint32_t old_write_domain, old_read_domains;
4029         struct i915_vma *vma;
4030         int ret;
4031
4032         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
4033                 return 0;
4034
4035         ret = i915_gem_object_wait_rendering(obj, !write);
4036         if (ret)
4037                 return ret;
4038
4039         /* Flush and acquire obj->pages so that we are coherent through
4040          * direct access in memory with previous cached writes through
4041          * shmemfs and that our cache domain tracking remains valid.
4042          * For example, if the obj->filp was moved to swap without us
4043          * being notified and releasing the pages, we would mistakenly
4044          * continue to assume that the obj remained out of the CPU cached
4045          * domain.
4046          */
4047         ret = i915_gem_object_get_pages(obj);
4048         if (ret)
4049                 return ret;
4050
4051         i915_gem_object_flush_cpu_write_domain(obj);
4052
4053         /* Serialise direct access to this object with the barriers for
4054          * coherent writes from the GPU, by effectively invalidating the
4055          * GTT domain upon first access.
4056          */
4057         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
4058                 mb();
4059
4060         old_write_domain = obj->base.write_domain;
4061         old_read_domains = obj->base.read_domains;
4062
4063         /* It should now be out of any other write domains, and we can update
4064          * the domain values for our changes.
4065          */
4066         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
4067         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4068         if (write) {
4069                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
4070                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
4071                 obj->dirty = 1;
4072         }
4073
4074         trace_i915_gem_object_change_domain(obj,
4075                                             old_read_domains,
4076                                             old_write_domain);
4077
4078         /* And bump the LRU for this access */
4079         vma = i915_gem_obj_to_ggtt(obj);
4080         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
4081                 list_move_tail(&vma->vm_link,
4082                                &ggtt->base.inactive_list);
4083
4084         return 0;
4085 }
4086
4087 /**
4088  * Changes the cache-level of an object across all VMA.
4089  * @obj: object to act on
4090  * @cache_level: new cache level to set for the object
4091  *
4092  * After this function returns, the object will be in the new cache-level
4093  * across all GTT and the contents of the backing storage will be coherent,
4094  * with respect to the new cache-level. In order to keep the backing storage
4095  * coherent for all users, we only allow a single cache level to be set
4096  * globally on the object and prevent it from being changed whilst the
4097  * hardware is reading from the object. That is if the object is currently
4098  * on the scanout it will be set to uncached (or equivalent display
4099  * cache coherency) and all non-MOCS GPU access will also be uncached so
4100  * that all direct access to the scanout remains coherent.
4101  */
4102 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4103                                     enum i915_cache_level cache_level)
4104 {
4105         struct drm_device *dev = obj->base.dev;
4106         struct i915_vma *vma, *next;
4107         bool bound = false;
4108         int ret = 0;
4109
4110         if (obj->cache_level == cache_level)
4111                 goto out;
4112
4113         /* Inspect the list of currently bound VMA and unbind any that would
4114          * be invalid given the new cache-level. This is principally to
4115          * catch the issue of the CS prefetch crossing page boundaries and
4116          * reading an invalid PTE on older architectures.
4117          */
4118         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4119                 if (!drm_mm_node_allocated(&vma->node))
4120                         continue;
4121
4122                 if (vma->pin_count) {
4123                         DRM_DEBUG("can not change the cache level of pinned objects\n");
4124                         return -EBUSY;
4125                 }
4126
4127                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
4128                         ret = i915_vma_unbind(vma);
4129                         if (ret)
4130                                 return ret;
4131                 } else
4132                         bound = true;
4133         }
4134
4135         /* We can reuse the existing drm_mm nodes but need to change the
4136          * cache-level on the PTE. We could simply unbind them all and
4137          * rebind with the correct cache-level on next use. However since
4138          * we already have a valid slot, dma mapping, pages etc, we may as
4139          * rewrite the PTE in the belief that doing so tramples upon less
4140          * state and so involves less work.
4141          */
4142         if (bound) {
4143                 /* Before we change the PTE, the GPU must not be accessing it.
4144                  * If we wait upon the object, we know that all the bound
4145                  * VMA are no longer active.
4146                  */
4147                 ret = i915_gem_object_wait_rendering(obj, false);
4148                 if (ret)
4149                         return ret;
4150
4151                 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
4152                         /* Access to snoopable pages through the GTT is
4153                          * incoherent and on some machines causes a hard
4154                          * lockup. Relinquish the CPU mmaping to force
4155                          * userspace to refault in the pages and we can
4156                          * then double check if the GTT mapping is still
4157                          * valid for that pointer access.
4158                          */
4159                         i915_gem_release_mmap(obj);
4160
4161                         /* As we no longer need a fence for GTT access,
4162                          * we can relinquish it now (and so prevent having
4163                          * to steal a fence from someone else on the next
4164                          * fence request). Note GPU activity would have
4165                          * dropped the fence as all snoopable access is
4166                          * supposed to be linear.
4167                          */
4168                         ret = i915_gem_object_put_fence(obj);
4169                         if (ret)
4170                                 return ret;
4171                 } else {
4172                         /* We either have incoherent backing store and
4173                          * so no GTT access or the architecture is fully
4174                          * coherent. In such cases, existing GTT mmaps
4175                          * ignore the cache bit in the PTE and we can
4176                          * rewrite it without confusing the GPU or having
4177                          * to force userspace to fault back in its mmaps.
4178                          */
4179                 }
4180
4181                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4182                         if (!drm_mm_node_allocated(&vma->node))
4183                                 continue;
4184
4185                         ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
4186                         if (ret)
4187                                 return ret;
4188                 }
4189         }
4190
4191         list_for_each_entry(vma, &obj->vma_list, obj_link)
4192                 vma->node.color = cache_level;
4193         obj->cache_level = cache_level;
4194
4195 out:
4196         /* Flush the dirty CPU caches to the backing storage so that the
4197          * object is now coherent at its new cache level (with respect
4198          * to the access domain).
4199          */
4200         if (obj->cache_dirty && cpu_write_needs_clflush(obj)) {
4201                 if (i915_gem_clflush_object(obj, true))
4202                         i915_gem_chipset_flush(to_i915(obj->base.dev));
4203         }
4204
4205         return 0;
4206 }
4207
4208 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4209                                struct drm_file *file)
4210 {
4211         struct drm_i915_gem_caching *args = data;
4212         struct drm_i915_gem_object *obj;
4213
4214         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4215         if (&obj->base == NULL)
4216                 return -ENOENT;
4217
4218         switch (obj->cache_level) {
4219         case I915_CACHE_LLC:
4220         case I915_CACHE_L3_LLC:
4221                 args->caching = I915_CACHING_CACHED;
4222                 break;
4223
4224         case I915_CACHE_WT:
4225                 args->caching = I915_CACHING_DISPLAY;
4226                 break;
4227
4228         default:
4229                 args->caching = I915_CACHING_NONE;
4230                 break;
4231         }
4232
4233         drm_gem_object_unreference_unlocked(&obj->base);
4234         return 0;
4235 }
4236
4237 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4238                                struct drm_file *file)
4239 {
4240         struct drm_i915_private *dev_priv = dev->dev_private;
4241         struct drm_i915_gem_caching *args = data;
4242         struct drm_i915_gem_object *obj;
4243         enum i915_cache_level level;
4244         int ret;
4245
4246         switch (args->caching) {
4247         case I915_CACHING_NONE:
4248                 level = I915_CACHE_NONE;
4249                 break;
4250         case I915_CACHING_CACHED:
4251                 /*
4252                  * Due to a HW issue on BXT A stepping, GPU stores via a
4253                  * snooped mapping may leave stale data in a corresponding CPU
4254                  * cacheline, whereas normally such cachelines would get
4255                  * invalidated.
4256                  */
4257                 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
4258                         return -ENODEV;
4259
4260                 level = I915_CACHE_LLC;
4261                 break;
4262         case I915_CACHING_DISPLAY:
4263                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4264                 break;
4265         default:
4266                 return -EINVAL;
4267         }
4268
4269         intel_runtime_pm_get(dev_priv);
4270
4271         ret = i915_mutex_lock_interruptible(dev);
4272         if (ret)
4273                 goto rpm_put;
4274
4275         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4276         if (&obj->base == NULL) {
4277                 ret = -ENOENT;
4278                 goto unlock;
4279         }
4280
4281         ret = i915_gem_object_set_cache_level(obj, level);
4282
4283         drm_gem_object_unreference(&obj->base);
4284 unlock:
4285         mutex_unlock(&dev->struct_mutex);
4286 rpm_put:
4287         intel_runtime_pm_put(dev_priv);
4288
4289         return ret;
4290 }
4291
4292 /*
4293  * Prepare buffer for display plane (scanout, cursors, etc).
4294  * Can be called from an uninterruptible phase (modesetting) and allows
4295  * any flushes to be pipelined (for pageflips).
4296  */
4297 int
4298 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4299                                      u32 alignment,
4300                                      const struct i915_ggtt_view *view)
4301 {
4302         u32 old_read_domains, old_write_domain;
4303         int ret;
4304
4305         /* Mark the pin_display early so that we account for the
4306          * display coherency whilst setting up the cache domains.
4307          */
4308         obj->pin_display++;
4309
4310         /* The display engine is not coherent with the LLC cache on gen6.  As
4311          * a result, we make sure that the pinning that is about to occur is
4312          * done with uncached PTEs. This is lowest common denominator for all
4313          * chipsets.
4314          *
4315          * However for gen6+, we could do better by using the GFDT bit instead
4316          * of uncaching, which would allow us to flush all the LLC-cached data
4317          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4318          */
4319         ret = i915_gem_object_set_cache_level(obj,
4320                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4321         if (ret)
4322                 goto err_unpin_display;
4323
4324         /* As the user may map the buffer once pinned in the display plane
4325          * (e.g. libkms for the bootup splash), we have to ensure that we
4326          * always use map_and_fenceable for all scanout buffers.
4327          */
4328         ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4329                                        view->type == I915_GGTT_VIEW_NORMAL ?
4330                                        PIN_MAPPABLE : 0);
4331         if (ret)
4332                 goto err_unpin_display;
4333
4334         i915_gem_object_flush_cpu_write_domain(obj);
4335
4336         old_write_domain = obj->base.write_domain;
4337         old_read_domains = obj->base.read_domains;
4338
4339         /* It should now be out of any other write domains, and we can update
4340          * the domain values for our changes.
4341          */
4342         obj->base.write_domain = 0;
4343         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4344
4345         trace_i915_gem_object_change_domain(obj,
4346                                             old_read_domains,
4347                                             old_write_domain);
4348
4349         return 0;
4350
4351 err_unpin_display:
4352         obj->pin_display--;
4353         return ret;
4354 }
4355
4356 void
4357 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4358                                          const struct i915_ggtt_view *view)
4359 {
4360         if (WARN_ON(obj->pin_display == 0))
4361                 return;
4362
4363         i915_gem_object_ggtt_unpin_view(obj, view);
4364
4365         obj->pin_display--;
4366 }
4367
4368 /**
4369  * Moves a single object to the CPU read, and possibly write domain.
4370  * @obj: object to act on
4371  * @write: requesting write or read-only access
4372  *
4373  * This function returns when the move is complete, including waiting on
4374  * flushes to occur.
4375  */
4376 int
4377 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4378 {
4379         uint32_t old_write_domain, old_read_domains;
4380         int ret;
4381
4382         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4383                 return 0;
4384
4385         ret = i915_gem_object_wait_rendering(obj, !write);
4386         if (ret)
4387                 return ret;
4388
4389         i915_gem_object_flush_gtt_write_domain(obj);
4390
4391         old_write_domain = obj->base.write_domain;
4392         old_read_domains = obj->base.read_domains;
4393
4394         /* Flush the CPU cache if it's still invalid. */
4395         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4396                 i915_gem_clflush_object(obj, false);
4397
4398                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4399         }
4400
4401         /* It should now be out of any other write domains, and we can update
4402          * the domain values for our changes.
4403          */
4404         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4405
4406         /* If we're writing through the CPU, then the GPU read domains will
4407          * need to be invalidated at next use.
4408          */
4409         if (write) {
4410                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4411                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4412         }
4413
4414         trace_i915_gem_object_change_domain(obj,
4415                                             old_read_domains,
4416                                             old_write_domain);
4417
4418         return 0;
4419 }
4420
4421 /* Throttle our rendering by waiting until the ring has completed our requests
4422  * emitted over 20 msec ago.
4423  *
4424  * Note that if we were to use the current jiffies each time around the loop,
4425  * we wouldn't escape the function with any frames outstanding if the time to
4426  * render a frame was over 20ms.
4427  *
4428  * This should get us reasonable parallelism between CPU and GPU but also
4429  * relatively low latency when blocking on a particular request to finish.
4430  */
4431 static int
4432 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4433 {
4434         struct drm_i915_private *dev_priv = dev->dev_private;
4435         struct drm_i915_file_private *file_priv = file->driver_priv;
4436         unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4437         struct drm_i915_gem_request *request, *target = NULL;
4438         int ret;
4439
4440         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4441         if (ret)
4442                 return ret;
4443
4444         /* ABI: return -EIO if already wedged */
4445         if (i915_terminally_wedged(&dev_priv->gpu_error))
4446                 return -EIO;
4447
4448         spin_lock(&file_priv->mm.lock);
4449         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4450                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4451                         break;
4452
4453                 /*
4454                  * Note that the request might not have been submitted yet.
4455                  * In which case emitted_jiffies will be zero.
4456                  */
4457                 if (!request->emitted_jiffies)
4458                         continue;
4459
4460                 target = request;
4461         }
4462         if (target)
4463                 i915_gem_request_reference(target);
4464         spin_unlock(&file_priv->mm.lock);
4465
4466         if (target == NULL)
4467                 return 0;
4468
4469         ret = __i915_wait_request(target, true, NULL, NULL);
4470         if (ret == 0)
4471                 queue_delayed_work(dev_priv->wq, &dev_priv->gt.retire_work, 0);
4472
4473         i915_gem_request_unreference(target);
4474
4475         return ret;
4476 }
4477
4478 static bool
4479 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4480 {
4481         struct drm_i915_gem_object *obj = vma->obj;
4482
4483         if (alignment &&
4484             vma->node.start & (alignment - 1))
4485                 return true;
4486
4487         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4488                 return true;
4489
4490         if (flags & PIN_OFFSET_BIAS &&
4491             vma->node.start < (flags & PIN_OFFSET_MASK))
4492                 return true;
4493
4494         if (flags & PIN_OFFSET_FIXED &&
4495             vma->node.start != (flags & PIN_OFFSET_MASK))
4496                 return true;
4497
4498         return false;
4499 }
4500
4501 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4502 {
4503         struct drm_i915_gem_object *obj = vma->obj;
4504         bool mappable, fenceable;
4505         u32 fence_size, fence_alignment;
4506
4507         fence_size = i915_gem_get_gtt_size(obj->base.dev,
4508                                            obj->base.size,
4509                                            obj->tiling_mode);
4510         fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4511                                                      obj->base.size,
4512                                                      obj->tiling_mode,
4513                                                      true);
4514
4515         fenceable = (vma->node.size == fence_size &&
4516                      (vma->node.start & (fence_alignment - 1)) == 0);
4517
4518         mappable = (vma->node.start + fence_size <=
4519                     to_i915(obj->base.dev)->ggtt.mappable_end);
4520
4521         obj->map_and_fenceable = mappable && fenceable;
4522 }
4523
4524 static int
4525 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4526                        struct i915_address_space *vm,
4527                        const struct i915_ggtt_view *ggtt_view,
4528                        uint32_t alignment,
4529                        uint64_t flags)
4530 {
4531         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4532         struct i915_vma *vma;
4533         unsigned bound;
4534         int ret;
4535
4536         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4537                 return -ENODEV;
4538
4539         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4540                 return -EINVAL;
4541
4542         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4543                 return -EINVAL;
4544
4545         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4546                 return -EINVAL;
4547
4548         vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4549                           i915_gem_obj_to_vma(obj, vm);
4550
4551         if (vma) {
4552                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4553                         return -EBUSY;
4554
4555                 if (i915_vma_misplaced(vma, alignment, flags)) {
4556                         WARN(vma->pin_count,
4557                              "bo is already pinned in %s with incorrect alignment:"
4558                              " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4559                              " obj->map_and_fenceable=%d\n",
4560                              ggtt_view ? "ggtt" : "ppgtt",
4561                              upper_32_bits(vma->node.start),
4562                              lower_32_bits(vma->node.start),
4563                              alignment,
4564                              !!(flags & PIN_MAPPABLE),
4565                              obj->map_and_fenceable);
4566                         ret = i915_vma_unbind(vma);
4567                         if (ret)
4568                                 return ret;
4569
4570                         vma = NULL;
4571                 }
4572         }
4573
4574         bound = vma ? vma->bound : 0;
4575         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4576                 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4577                                                  flags);
4578                 if (IS_ERR(vma))
4579                         return PTR_ERR(vma);
4580         } else {
4581                 ret = i915_vma_bind(vma, obj->cache_level, flags);
4582                 if (ret)
4583                         return ret;
4584         }
4585
4586         if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4587             (bound ^ vma->bound) & GLOBAL_BIND) {
4588                 __i915_vma_set_map_and_fenceable(vma);
4589                 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4590         }
4591
4592         vma->pin_count++;
4593         return 0;
4594 }
4595
4596 int
4597 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4598                     struct i915_address_space *vm,
4599                     uint32_t alignment,
4600                     uint64_t flags)
4601 {
4602         return i915_gem_object_do_pin(obj, vm,
4603                                       i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4604                                       alignment, flags);
4605 }
4606
4607 int
4608 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4609                          const struct i915_ggtt_view *view,
4610                          uint32_t alignment,
4611                          uint64_t flags)
4612 {
4613         struct drm_device *dev = obj->base.dev;
4614         struct drm_i915_private *dev_priv = to_i915(dev);
4615         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4616
4617         BUG_ON(!view);
4618
4619         return i915_gem_object_do_pin(obj, &ggtt->base, view,
4620                                       alignment, flags | PIN_GLOBAL);
4621 }
4622
4623 void
4624 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4625                                 const struct i915_ggtt_view *view)
4626 {
4627         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4628
4629         WARN_ON(vma->pin_count == 0);
4630         WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4631
4632         --vma->pin_count;
4633 }
4634
4635 int
4636 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4637                     struct drm_file *file)
4638 {
4639         struct drm_i915_gem_busy *args = data;
4640         struct drm_i915_gem_object *obj;
4641         int ret;
4642
4643         ret = i915_mutex_lock_interruptible(dev);
4644         if (ret)
4645                 return ret;
4646
4647         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4648         if (&obj->base == NULL) {
4649                 ret = -ENOENT;
4650                 goto unlock;
4651         }
4652
4653         /* Count all active objects as busy, even if they are currently not used
4654          * by the gpu. Users of this interface expect objects to eventually
4655          * become non-busy without any further actions, therefore emit any
4656          * necessary flushes here.
4657          */
4658         ret = i915_gem_object_flush_active(obj);
4659         if (ret)
4660                 goto unref;
4661
4662         args->busy = 0;
4663         if (obj->active) {
4664                 int i;
4665
4666                 for (i = 0; i < I915_NUM_ENGINES; i++) {
4667                         struct drm_i915_gem_request *req;
4668
4669                         req = obj->last_read_req[i];
4670                         if (req)
4671                                 args->busy |= 1 << (16 + req->engine->exec_id);
4672                 }
4673                 if (obj->last_write_req)
4674                         args->busy |= obj->last_write_req->engine->exec_id;
4675         }
4676
4677 unref:
4678         drm_gem_object_unreference(&obj->base);
4679 unlock:
4680         mutex_unlock(&dev->struct_mutex);
4681         return ret;
4682 }
4683
4684 int
4685 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4686                         struct drm_file *file_priv)
4687 {
4688         return i915_gem_ring_throttle(dev, file_priv);
4689 }
4690
4691 int
4692 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4693                        struct drm_file *file_priv)
4694 {
4695         struct drm_i915_private *dev_priv = dev->dev_private;
4696         struct drm_i915_gem_madvise *args = data;
4697         struct drm_i915_gem_object *obj;
4698         int ret;
4699
4700         switch (args->madv) {
4701         case I915_MADV_DONTNEED:
4702         case I915_MADV_WILLNEED:
4703             break;
4704         default:
4705             return -EINVAL;
4706         }
4707
4708         ret = i915_mutex_lock_interruptible(dev);
4709         if (ret)
4710                 return ret;
4711
4712         obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle));
4713         if (&obj->base == NULL) {
4714                 ret = -ENOENT;
4715                 goto unlock;
4716         }
4717
4718         if (i915_gem_obj_is_pinned(obj)) {
4719                 ret = -EINVAL;
4720                 goto out;
4721         }
4722
4723         if (obj->pages &&
4724             obj->tiling_mode != I915_TILING_NONE &&
4725             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4726                 if (obj->madv == I915_MADV_WILLNEED)
4727                         i915_gem_object_unpin_pages(obj);
4728                 if (args->madv == I915_MADV_WILLNEED)
4729                         i915_gem_object_pin_pages(obj);
4730         }
4731
4732         if (obj->madv != __I915_MADV_PURGED)
4733                 obj->madv = args->madv;
4734
4735         /* if the object is no longer attached, discard its backing storage */
4736         if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4737                 i915_gem_object_truncate(obj);
4738
4739         args->retained = obj->madv != __I915_MADV_PURGED;
4740
4741 out:
4742         drm_gem_object_unreference(&obj->base);
4743 unlock:
4744         mutex_unlock(&dev->struct_mutex);
4745         return ret;
4746 }
4747
4748 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4749                           const struct drm_i915_gem_object_ops *ops)
4750 {
4751         int i;
4752
4753         INIT_LIST_HEAD(&obj->global_list);
4754         for (i = 0; i < I915_NUM_ENGINES; i++)
4755                 INIT_LIST_HEAD(&obj->engine_list[i]);
4756         INIT_LIST_HEAD(&obj->obj_exec_link);
4757         INIT_LIST_HEAD(&obj->vma_list);
4758         INIT_LIST_HEAD(&obj->batch_pool_link);
4759
4760         obj->ops = ops;
4761
4762         obj->fence_reg = I915_FENCE_REG_NONE;
4763         obj->madv = I915_MADV_WILLNEED;
4764
4765         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4766 }
4767
4768 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4769         .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4770         .get_pages = i915_gem_object_get_pages_gtt,
4771         .put_pages = i915_gem_object_put_pages_gtt,
4772 };
4773
4774 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
4775                                                   size_t size)
4776 {
4777         struct drm_i915_gem_object *obj;
4778         struct address_space *mapping;
4779         gfp_t mask;
4780         int ret;
4781
4782         obj = i915_gem_object_alloc(dev);
4783         if (obj == NULL)
4784                 return ERR_PTR(-ENOMEM);
4785
4786         ret = drm_gem_object_init(dev, &obj->base, size);
4787         if (ret)
4788                 goto fail;
4789
4790         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4791         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4792                 /* 965gm cannot relocate objects above 4GiB. */
4793                 mask &= ~__GFP_HIGHMEM;
4794                 mask |= __GFP_DMA32;
4795         }
4796
4797         mapping = file_inode(obj->base.filp)->i_mapping;
4798         mapping_set_gfp_mask(mapping, mask);
4799
4800         i915_gem_object_init(obj, &i915_gem_object_ops);
4801
4802         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4803         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4804
4805         if (HAS_LLC(dev)) {
4806                 /* On some devices, we can have the GPU use the LLC (the CPU
4807                  * cache) for about a 10% performance improvement
4808                  * compared to uncached.  Graphics requests other than
4809                  * display scanout are coherent with the CPU in
4810                  * accessing this cache.  This means in this mode we
4811                  * don't need to clflush on the CPU side, and on the
4812                  * GPU side we only need to flush internal caches to
4813                  * get data visible to the CPU.
4814                  *
4815                  * However, we maintain the display planes as UC, and so
4816                  * need to rebind when first used as such.
4817                  */
4818                 obj->cache_level = I915_CACHE_LLC;
4819         } else
4820                 obj->cache_level = I915_CACHE_NONE;
4821
4822         trace_i915_gem_object_create(obj);
4823
4824         return obj;
4825
4826 fail:
4827         i915_gem_object_free(obj);
4828
4829         return ERR_PTR(ret);
4830 }
4831
4832 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4833 {
4834         /* If we are the last user of the backing storage (be it shmemfs
4835          * pages or stolen etc), we know that the pages are going to be
4836          * immediately released. In this case, we can then skip copying
4837          * back the contents from the GPU.
4838          */
4839
4840         if (obj->madv != I915_MADV_WILLNEED)
4841                 return false;
4842
4843         if (obj->base.filp == NULL)
4844                 return true;
4845
4846         /* At first glance, this looks racy, but then again so would be
4847          * userspace racing mmap against close. However, the first external
4848          * reference to the filp can only be obtained through the
4849          * i915_gem_mmap_ioctl() which safeguards us against the user
4850          * acquiring such a reference whilst we are in the middle of
4851          * freeing the object.
4852          */
4853         return atomic_long_read(&obj->base.filp->f_count) == 1;
4854 }
4855
4856 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4857 {
4858         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4859         struct drm_device *dev = obj->base.dev;
4860         struct drm_i915_private *dev_priv = dev->dev_private;
4861         struct i915_vma *vma, *next;
4862
4863         intel_runtime_pm_get(dev_priv);
4864
4865         trace_i915_gem_object_destroy(obj);
4866
4867         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4868                 int ret;
4869
4870                 vma->pin_count = 0;
4871                 ret = i915_vma_unbind(vma);
4872                 if (WARN_ON(ret == -ERESTARTSYS)) {
4873                         bool was_interruptible;
4874
4875                         was_interruptible = dev_priv->mm.interruptible;
4876                         dev_priv->mm.interruptible = false;
4877
4878                         WARN_ON(i915_vma_unbind(vma));
4879
4880                         dev_priv->mm.interruptible = was_interruptible;
4881                 }
4882         }
4883
4884         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4885          * before progressing. */
4886         if (obj->stolen)
4887                 i915_gem_object_unpin_pages(obj);
4888
4889         WARN_ON(obj->frontbuffer_bits);
4890
4891         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4892             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4893             obj->tiling_mode != I915_TILING_NONE)
4894                 i915_gem_object_unpin_pages(obj);
4895
4896         if (WARN_ON(obj->pages_pin_count))
4897                 obj->pages_pin_count = 0;
4898         if (discard_backing_storage(obj))
4899                 obj->madv = I915_MADV_DONTNEED;
4900         i915_gem_object_put_pages(obj);
4901         i915_gem_object_free_mmap_offset(obj);
4902
4903         BUG_ON(obj->pages);
4904
4905         if (obj->base.import_attach)
4906                 drm_prime_gem_destroy(&obj->base, NULL);
4907
4908         if (obj->ops->release)
4909                 obj->ops->release(obj);
4910
4911         drm_gem_object_release(&obj->base);
4912         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4913
4914         kfree(obj->bit_17);
4915         i915_gem_object_free(obj);
4916
4917         intel_runtime_pm_put(dev_priv);
4918 }
4919
4920 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4921                                      struct i915_address_space *vm)
4922 {
4923         struct i915_vma *vma;
4924         list_for_each_entry(vma, &obj->vma_list, obj_link) {
4925                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4926                     vma->vm == vm)
4927                         return vma;
4928         }
4929         return NULL;
4930 }
4931
4932 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4933                                            const struct i915_ggtt_view *view)
4934 {
4935         struct i915_vma *vma;
4936
4937         GEM_BUG_ON(!view);
4938
4939         list_for_each_entry(vma, &obj->vma_list, obj_link)
4940                 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
4941                         return vma;
4942         return NULL;
4943 }
4944
4945 void i915_gem_vma_destroy(struct i915_vma *vma)
4946 {
4947         WARN_ON(vma->node.allocated);
4948
4949         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4950         if (!list_empty(&vma->exec_list))
4951                 return;
4952
4953         if (!vma->is_ggtt)
4954                 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4955
4956         list_del(&vma->obj_link);
4957
4958         kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4959 }
4960
4961 static void
4962 i915_gem_stop_engines(struct drm_device *dev)
4963 {
4964         struct drm_i915_private *dev_priv = dev->dev_private;
4965         struct intel_engine_cs *engine;
4966
4967         for_each_engine(engine, dev_priv)
4968                 dev_priv->gt.stop_engine(engine);
4969 }
4970
4971 int
4972 i915_gem_suspend(struct drm_device *dev)
4973 {
4974         struct drm_i915_private *dev_priv = dev->dev_private;
4975         int ret = 0;
4976
4977         mutex_lock(&dev->struct_mutex);
4978         ret = i915_gem_wait_for_idle(dev_priv);
4979         if (ret)
4980                 goto err;
4981
4982         i915_gem_retire_requests(dev_priv);
4983
4984         i915_gem_stop_engines(dev);
4985         i915_gem_context_lost(dev_priv);
4986         mutex_unlock(&dev->struct_mutex);
4987
4988         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4989         cancel_delayed_work_sync(&dev_priv->gt.retire_work);
4990         flush_delayed_work(&dev_priv->gt.idle_work);
4991
4992         /* Assert that we sucessfully flushed all the work and
4993          * reset the GPU back to its idle, low power state.
4994          */
4995         WARN_ON(dev_priv->gt.awake);
4996
4997         return 0;
4998
4999 err:
5000         mutex_unlock(&dev->struct_mutex);
5001         return ret;
5002 }
5003
5004 void i915_gem_init_swizzling(struct drm_device *dev)
5005 {
5006         struct drm_i915_private *dev_priv = dev->dev_private;
5007
5008         if (INTEL_INFO(dev)->gen < 5 ||
5009             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
5010                 return;
5011
5012         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
5013                                  DISP_TILE_SURFACE_SWIZZLING);
5014
5015         if (IS_GEN5(dev))
5016                 return;
5017
5018         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
5019         if (IS_GEN6(dev))
5020                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
5021         else if (IS_GEN7(dev))
5022                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
5023         else if (IS_GEN8(dev))
5024                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
5025         else
5026                 BUG();
5027 }
5028
5029 static void init_unused_ring(struct drm_device *dev, u32 base)
5030 {
5031         struct drm_i915_private *dev_priv = dev->dev_private;
5032
5033         I915_WRITE(RING_CTL(base), 0);
5034         I915_WRITE(RING_HEAD(base), 0);
5035         I915_WRITE(RING_TAIL(base), 0);
5036         I915_WRITE(RING_START(base), 0);
5037 }
5038
5039 static void init_unused_rings(struct drm_device *dev)
5040 {
5041         if (IS_I830(dev)) {
5042                 init_unused_ring(dev, PRB1_BASE);
5043                 init_unused_ring(dev, SRB0_BASE);
5044                 init_unused_ring(dev, SRB1_BASE);
5045                 init_unused_ring(dev, SRB2_BASE);
5046                 init_unused_ring(dev, SRB3_BASE);
5047         } else if (IS_GEN2(dev)) {
5048                 init_unused_ring(dev, SRB0_BASE);
5049                 init_unused_ring(dev, SRB1_BASE);
5050         } else if (IS_GEN3(dev)) {
5051                 init_unused_ring(dev, PRB1_BASE);
5052                 init_unused_ring(dev, PRB2_BASE);
5053         }
5054 }
5055
5056 int i915_gem_init_engines(struct drm_device *dev)
5057 {
5058         struct drm_i915_private *dev_priv = dev->dev_private;
5059         int ret;
5060
5061         ret = intel_init_render_ring_buffer(dev);
5062         if (ret)
5063                 return ret;
5064
5065         if (HAS_BSD(dev)) {
5066                 ret = intel_init_bsd_ring_buffer(dev);
5067                 if (ret)
5068                         goto cleanup_render_ring;
5069         }
5070
5071         if (HAS_BLT(dev)) {
5072                 ret = intel_init_blt_ring_buffer(dev);
5073                 if (ret)
5074                         goto cleanup_bsd_ring;
5075         }
5076
5077         if (HAS_VEBOX(dev)) {
5078                 ret = intel_init_vebox_ring_buffer(dev);
5079                 if (ret)
5080                         goto cleanup_blt_ring;
5081         }
5082
5083         if (HAS_BSD2(dev)) {
5084                 ret = intel_init_bsd2_ring_buffer(dev);
5085                 if (ret)
5086                         goto cleanup_vebox_ring;
5087         }
5088
5089         return 0;
5090
5091 cleanup_vebox_ring:
5092         intel_cleanup_engine(&dev_priv->engine[VECS]);
5093 cleanup_blt_ring:
5094         intel_cleanup_engine(&dev_priv->engine[BCS]);
5095 cleanup_bsd_ring:
5096         intel_cleanup_engine(&dev_priv->engine[VCS]);
5097 cleanup_render_ring:
5098         intel_cleanup_engine(&dev_priv->engine[RCS]);
5099
5100         return ret;
5101 }
5102
5103 int
5104 i915_gem_init_hw(struct drm_device *dev)
5105 {
5106         struct drm_i915_private *dev_priv = dev->dev_private;
5107         struct intel_engine_cs *engine;
5108         int ret;
5109
5110         /* Double layer security blanket, see i915_gem_init() */
5111         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5112
5113         if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
5114                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5115
5116         if (IS_HASWELL(dev))
5117                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
5118                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5119
5120         if (HAS_PCH_NOP(dev)) {
5121                 if (IS_IVYBRIDGE(dev)) {
5122                         u32 temp = I915_READ(GEN7_MSG_CTL);
5123                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5124                         I915_WRITE(GEN7_MSG_CTL, temp);
5125                 } else if (INTEL_INFO(dev)->gen >= 7) {
5126                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5127                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5128                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5129                 }
5130         }
5131
5132         i915_gem_init_swizzling(dev);
5133
5134         /*
5135          * At least 830 can leave some of the unused rings
5136          * "active" (ie. head != tail) after resume which
5137          * will prevent c3 entry. Makes sure all unused rings
5138          * are totally idle.
5139          */
5140         init_unused_rings(dev);
5141
5142         BUG_ON(!dev_priv->kernel_context);
5143
5144         ret = i915_ppgtt_init_hw(dev);
5145         if (ret) {
5146                 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
5147                 goto out;
5148         }
5149
5150         /* Need to do basic initialisation of all rings first: */
5151         for_each_engine(engine, dev_priv) {
5152                 ret = engine->init_hw(engine);
5153                 if (ret)
5154                         goto out;
5155         }
5156
5157         intel_mocs_init_l3cc_table(dev);
5158
5159         /* We can't enable contexts until all firmware is loaded */
5160         ret = intel_guc_setup(dev);
5161         if (ret)
5162                 goto out;
5163
5164 out:
5165         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5166         return ret;
5167 }
5168
5169 int i915_gem_init(struct drm_device *dev)
5170 {
5171         struct drm_i915_private *dev_priv = dev->dev_private;
5172         int ret;
5173
5174         mutex_lock(&dev->struct_mutex);
5175
5176         if (!i915.enable_execlists) {
5177                 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5178                 dev_priv->gt.init_engines = i915_gem_init_engines;
5179                 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
5180                 dev_priv->gt.stop_engine = intel_stop_engine;
5181         } else {
5182                 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5183                 dev_priv->gt.init_engines = intel_logical_rings_init;
5184                 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
5185                 dev_priv->gt.stop_engine = intel_logical_ring_stop;
5186         }
5187
5188         /* This is just a security blanket to placate dragons.
5189          * On some systems, we very sporadically observe that the first TLBs
5190          * used by the CS may be stale, despite us poking the TLB reset. If
5191          * we hold the forcewake during initialisation these problems
5192          * just magically go away.
5193          */
5194         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5195
5196         i915_gem_init_userptr(dev_priv);
5197         i915_gem_init_ggtt(dev);
5198
5199         ret = i915_gem_context_init(dev);
5200         if (ret)
5201                 goto out_unlock;
5202
5203         ret = dev_priv->gt.init_engines(dev);
5204         if (ret)
5205                 goto out_unlock;
5206
5207         ret = i915_gem_init_hw(dev);
5208         if (ret == -EIO) {
5209                 /* Allow ring initialisation to fail by marking the GPU as
5210                  * wedged. But we only want to do this where the GPU is angry,
5211                  * for all other failure, such as an allocation failure, bail.
5212                  */
5213                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5214                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5215                 ret = 0;
5216         }
5217
5218 out_unlock:
5219         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5220         mutex_unlock(&dev->struct_mutex);
5221
5222         return ret;
5223 }
5224
5225 void
5226 i915_gem_cleanup_engines(struct drm_device *dev)
5227 {
5228         struct drm_i915_private *dev_priv = dev->dev_private;
5229         struct intel_engine_cs *engine;
5230
5231         for_each_engine(engine, dev_priv)
5232                 dev_priv->gt.cleanup_engine(engine);
5233 }
5234
5235 static void
5236 init_engine_lists(struct intel_engine_cs *engine)
5237 {
5238         INIT_LIST_HEAD(&engine->active_list);
5239         INIT_LIST_HEAD(&engine->request_list);
5240 }
5241
5242 void
5243 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5244 {
5245         struct drm_device *dev = dev_priv->dev;
5246
5247         if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5248             !IS_CHERRYVIEW(dev_priv))
5249                 dev_priv->num_fence_regs = 32;
5250         else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
5251                  IS_I945GM(dev_priv) || IS_G33(dev_priv))
5252                 dev_priv->num_fence_regs = 16;
5253         else
5254                 dev_priv->num_fence_regs = 8;
5255
5256         if (intel_vgpu_active(dev_priv))
5257                 dev_priv->num_fence_regs =
5258                                 I915_READ(vgtif_reg(avail_rs.fence_num));
5259
5260         /* Initialize fence registers to zero */
5261         i915_gem_restore_fences(dev);
5262
5263         i915_gem_detect_bit_6_swizzle(dev);
5264 }
5265
5266 void
5267 i915_gem_load_init(struct drm_device *dev)
5268 {
5269         struct drm_i915_private *dev_priv = dev->dev_private;
5270         int i;
5271
5272         dev_priv->objects =
5273                 kmem_cache_create("i915_gem_object",
5274                                   sizeof(struct drm_i915_gem_object), 0,
5275                                   SLAB_HWCACHE_ALIGN,
5276                                   NULL);
5277         dev_priv->vmas =
5278                 kmem_cache_create("i915_gem_vma",
5279                                   sizeof(struct i915_vma), 0,
5280                                   SLAB_HWCACHE_ALIGN,
5281                                   NULL);
5282         dev_priv->requests =
5283                 kmem_cache_create("i915_gem_request",
5284                                   sizeof(struct drm_i915_gem_request), 0,
5285                                   SLAB_HWCACHE_ALIGN,
5286                                   NULL);
5287
5288         INIT_LIST_HEAD(&dev_priv->vm_list);
5289         INIT_LIST_HEAD(&dev_priv->context_list);
5290         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5291         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5292         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5293         for (i = 0; i < I915_NUM_ENGINES; i++)
5294                 init_engine_lists(&dev_priv->engine[i]);
5295         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5296                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5297         INIT_DELAYED_WORK(&dev_priv->gt.retire_work,
5298                           i915_gem_retire_work_handler);
5299         INIT_DELAYED_WORK(&dev_priv->gt.idle_work,
5300                           i915_gem_idle_work_handler);
5301         init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
5302         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5303
5304         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5305
5306         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5307
5308         init_waitqueue_head(&dev_priv->pending_flip_queue);
5309
5310         dev_priv->mm.interruptible = true;
5311
5312         mutex_init(&dev_priv->fb_tracking.lock);
5313 }
5314
5315 void i915_gem_load_cleanup(struct drm_device *dev)
5316 {
5317         struct drm_i915_private *dev_priv = to_i915(dev);
5318
5319         kmem_cache_destroy(dev_priv->requests);
5320         kmem_cache_destroy(dev_priv->vmas);
5321         kmem_cache_destroy(dev_priv->objects);
5322 }
5323
5324 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
5325 {
5326         struct drm_i915_gem_object *obj;
5327
5328         /* Called just before we write the hibernation image.
5329          *
5330          * We need to update the domain tracking to reflect that the CPU
5331          * will be accessing all the pages to create and restore from the
5332          * hibernation, and so upon restoration those pages will be in the
5333          * CPU domain.
5334          *
5335          * To make sure the hibernation image contains the latest state,
5336          * we update that state just before writing out the image.
5337          */
5338
5339         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5340                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
5341                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
5342         }
5343
5344         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5345                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
5346                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
5347         }
5348
5349         return 0;
5350 }
5351
5352 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5353 {
5354         struct drm_i915_file_private *file_priv = file->driver_priv;
5355
5356         /* Clean up our request list when the client is going away, so that
5357          * later retire_requests won't dereference our soon-to-be-gone
5358          * file_priv.
5359          */
5360         spin_lock(&file_priv->mm.lock);
5361         while (!list_empty(&file_priv->mm.request_list)) {
5362                 struct drm_i915_gem_request *request;
5363
5364                 request = list_first_entry(&file_priv->mm.request_list,
5365                                            struct drm_i915_gem_request,
5366                                            client_list);
5367                 list_del(&request->client_list);
5368                 request->file_priv = NULL;
5369         }
5370         spin_unlock(&file_priv->mm.lock);
5371
5372         if (!list_empty(&file_priv->rps.link)) {
5373                 spin_lock(&to_i915(dev)->rps.client_lock);
5374                 list_del(&file_priv->rps.link);
5375                 spin_unlock(&to_i915(dev)->rps.client_lock);
5376         }
5377 }
5378
5379 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5380 {
5381         struct drm_i915_file_private *file_priv;
5382         int ret;
5383
5384         DRM_DEBUG_DRIVER("\n");
5385
5386         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5387         if (!file_priv)
5388                 return -ENOMEM;
5389
5390         file->driver_priv = file_priv;
5391         file_priv->dev_priv = dev->dev_private;
5392         file_priv->file = file;
5393         INIT_LIST_HEAD(&file_priv->rps.link);
5394
5395         spin_lock_init(&file_priv->mm.lock);
5396         INIT_LIST_HEAD(&file_priv->mm.request_list);
5397
5398         file_priv->bsd_ring = -1;
5399
5400         ret = i915_gem_context_open(dev, file);
5401         if (ret)
5402                 kfree(file_priv);
5403
5404         return ret;
5405 }
5406
5407 /**
5408  * i915_gem_track_fb - update frontbuffer tracking
5409  * @old: current GEM buffer for the frontbuffer slots
5410  * @new: new GEM buffer for the frontbuffer slots
5411  * @frontbuffer_bits: bitmask of frontbuffer slots
5412  *
5413  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5414  * from @old and setting them in @new. Both @old and @new can be NULL.
5415  */
5416 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5417                        struct drm_i915_gem_object *new,
5418                        unsigned frontbuffer_bits)
5419 {
5420         if (old) {
5421                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5422                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5423                 old->frontbuffer_bits &= ~frontbuffer_bits;
5424         }
5425
5426         if (new) {
5427                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5428                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5429                 new->frontbuffer_bits |= frontbuffer_bits;
5430         }
5431 }
5432
5433 /* All the new VM stuff */
5434 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5435                         struct i915_address_space *vm)
5436 {
5437         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5438         struct i915_vma *vma;
5439
5440         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5441
5442         list_for_each_entry(vma, &o->vma_list, obj_link) {
5443                 if (vma->is_ggtt &&
5444                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5445                         continue;
5446                 if (vma->vm == vm)
5447                         return vma->node.start;
5448         }
5449
5450         WARN(1, "%s vma for this object not found.\n",
5451              i915_is_ggtt(vm) ? "global" : "ppgtt");
5452         return -1;
5453 }
5454
5455 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5456                                   const struct i915_ggtt_view *view)
5457 {
5458         struct i915_vma *vma;
5459
5460         list_for_each_entry(vma, &o->vma_list, obj_link)
5461                 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
5462                         return vma->node.start;
5463
5464         WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5465         return -1;
5466 }
5467
5468 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5469                         struct i915_address_space *vm)
5470 {
5471         struct i915_vma *vma;
5472
5473         list_for_each_entry(vma, &o->vma_list, obj_link) {
5474                 if (vma->is_ggtt &&
5475                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5476                         continue;
5477                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5478                         return true;
5479         }
5480
5481         return false;
5482 }
5483
5484 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5485                                   const struct i915_ggtt_view *view)
5486 {
5487         struct i915_vma *vma;
5488
5489         list_for_each_entry(vma, &o->vma_list, obj_link)
5490                 if (vma->is_ggtt &&
5491                     i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5492                     drm_mm_node_allocated(&vma->node))
5493                         return true;
5494
5495         return false;
5496 }
5497
5498 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5499 {
5500         struct i915_vma *vma;
5501
5502         list_for_each_entry(vma, &o->vma_list, obj_link)
5503                 if (drm_mm_node_allocated(&vma->node))
5504                         return true;
5505
5506         return false;
5507 }
5508
5509 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
5510 {
5511         struct i915_vma *vma;
5512
5513         GEM_BUG_ON(list_empty(&o->vma_list));
5514
5515         list_for_each_entry(vma, &o->vma_list, obj_link) {
5516                 if (vma->is_ggtt &&
5517                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5518                         return vma->node.size;
5519         }
5520
5521         return 0;
5522 }
5523
5524 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5525 {
5526         struct i915_vma *vma;
5527         list_for_each_entry(vma, &obj->vma_list, obj_link)
5528                 if (vma->pin_count > 0)
5529                         return true;
5530
5531         return false;
5532 }
5533
5534 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5535 struct page *
5536 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5537 {
5538         struct page *page;
5539
5540         /* Only default objects have per-page dirty tracking */
5541         if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
5542                 return NULL;
5543
5544         page = i915_gem_object_get_page(obj, n);
5545         set_page_dirty(page);
5546         return page;
5547 }
5548
5549 /* Allocate a new GEM object and fill it with the supplied data */
5550 struct drm_i915_gem_object *
5551 i915_gem_object_create_from_data(struct drm_device *dev,
5552                                  const void *data, size_t size)
5553 {
5554         struct drm_i915_gem_object *obj;
5555         struct sg_table *sg;
5556         size_t bytes;
5557         int ret;
5558
5559         obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
5560         if (IS_ERR(obj))
5561                 return obj;
5562
5563         ret = i915_gem_object_set_to_cpu_domain(obj, true);
5564         if (ret)
5565                 goto fail;
5566
5567         ret = i915_gem_object_get_pages(obj);
5568         if (ret)
5569                 goto fail;
5570
5571         i915_gem_object_pin_pages(obj);
5572         sg = obj->pages;
5573         bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5574         obj->dirty = 1;         /* Backing store is now out of date */
5575         i915_gem_object_unpin_pages(obj);
5576
5577         if (WARN_ON(bytes != size)) {
5578                 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5579                 ret = -EFAULT;
5580                 goto fail;
5581         }
5582
5583         return obj;
5584
5585 fail:
5586         drm_gem_object_unreference(&obj->base);
5587         return ERR_PTR(ret);
5588 }