drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008-2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_vgpu.h"
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35 #include "intel_mocs.h"
  36 #include <linux/shmem_fs.h>
  37 #include <linux/slab.h>
  38 #include <linux/swap.h>
  39 #include <linux/pci.h>
  40 #include <linux/dma-buf.h>
  41
  42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
  44 static void
  45 i915_gem_object_retire__write(struct drm_i915_gem_object *obj);
  46 static void
  47 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring);
  48
  49 static bool cpu_cache_is_coherent(struct drm_device *dev,
  50                                   enum i915_cache_level level)
  51 {
  52         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  53 }
  54
  55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  56 {
  57         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
  58                 return false;
  59
  60         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  61                 return true;
  62
  63         return obj->pin_display;
  64 }
  65
  66 static int
  67 insert_mappable_node(struct drm_i915_private *i915,
  68                      struct drm_mm_node *node, u32 size)
  69 {
  70         memset(node, 0, sizeof(*node));
  71         return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node,
  72                                                    size, 0, 0, 0,
  73                                                    i915->ggtt.mappable_end,
  74                                                    DRM_MM_SEARCH_DEFAULT,
  75                                                    DRM_MM_CREATE_DEFAULT);
  76 }
  77
  78 static void
  79 remove_mappable_node(struct drm_mm_node *node)
  80 {
  81         drm_mm_remove_node(node);
  82 }
  83
  84 /* some bookkeeping */
  85 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  86                                   size_t size)
  87 {
  88         spin_lock(&dev_priv->mm.object_stat_lock);
  89         dev_priv->mm.object_count++;
  90         dev_priv->mm.object_memory += size;
  91         spin_unlock(&dev_priv->mm.object_stat_lock);
  92 }
  93
  94 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
  95                                      size_t size)
  96 {
  97         spin_lock(&dev_priv->mm.object_stat_lock);
  98         dev_priv->mm.object_count--;
  99         dev_priv->mm.object_memory -= size;
 100         spin_unlock(&dev_priv->mm.object_stat_lock);
 101 }
 102
 103 static int
 104 i915_gem_wait_for_error(struct i915_gpu_error *error)
 105 {
 106         int ret;
 107
 108         if (!i915_reset_in_progress(error))
 109                 return 0;
 110
 111         /*
 112          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 113          * userspace. If it takes that long something really bad is going on and
 114          * we should simply try to bail out and fail as gracefully as possible.
 115          */
 116         ret = wait_event_interruptible_timeout(error->reset_queue,
 117                                                !i915_reset_in_progress(error),
 118                                                10*HZ);
 119         if (ret == 0) {
 120                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 121                 return -EIO;
 122         } else if (ret < 0) {
 123                 return ret;
 124         } else {
 125                 return 0;
 126         }
 127 }
 128
 129 int i915_mutex_lock_interruptible(struct drm_device *dev)
 130 {
 131         struct drm_i915_private *dev_priv = dev->dev_private;
 132         int ret;
 133
 134         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 135         if (ret)
 136                 return ret;
 137
 138         ret = mutex_lock_interruptible(&dev->struct_mutex);
 139         if (ret)
 140                 return ret;
 141
 142         WARN_ON(i915_verify_lists(dev));
 143         return 0;
 144 }
 145
 146 int
 147 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 148                             struct drm_file *file)
 149 {
 150         struct drm_i915_private *dev_priv = to_i915(dev);
 151         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 152         struct drm_i915_gem_get_aperture *args = data;
 153         struct i915_vma *vma;
 154         size_t pinned;
 155
 156         pinned = 0;
 157         mutex_lock(&dev->struct_mutex);
 158         list_for_each_entry(vma, &ggtt->base.active_list, vm_link)
 159                 if (vma->pin_count)
 160                         pinned += vma->node.size;
 161         list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link)
 162                 if (vma->pin_count)
 163                         pinned += vma->node.size;
 164         mutex_unlock(&dev->struct_mutex);
 165
 166         args->aper_size = ggtt->base.total;
 167         args->aper_available_size = args->aper_size - pinned;
 168
 169         return 0;
 170 }
 171
 172 static int
 173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj)
 174 {
 175         struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 176         char *vaddr = obj->phys_handle->vaddr;
 177         struct sg_table *st;
 178         struct scatterlist *sg;
 179         int i;
 180
 181         if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj)))
 182                 return -EINVAL;
 183
 184         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 185                 struct page *page;
 186                 char *src;
 187
 188                 page = shmem_read_mapping_page(mapping, i);
 189                 if (IS_ERR(page))
 190                         return PTR_ERR(page);
 191
 192                 src = kmap_atomic(page);
 193                 memcpy(vaddr, src, PAGE_SIZE);
 194                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 195                 kunmap_atomic(src);
 196
 197                 put_page(page);
 198                 vaddr += PAGE_SIZE;
 199         }
 200
 201         i915_gem_chipset_flush(to_i915(obj->base.dev));
 202
 203         st = kmalloc(sizeof(*st), GFP_KERNEL);
 204         if (st == NULL)
 205                 return -ENOMEM;
 206
 207         if (sg_alloc_table(st, 1, GFP_KERNEL)) {
 208                 kfree(st);
 209                 return -ENOMEM;
 210         }
 211
 212         sg = st->sgl;
 213         sg->offset = 0;
 214         sg->length = obj->base.size;
 215
 216         sg_dma_address(sg) = obj->phys_handle->busaddr;
 217         sg_dma_len(sg) = obj->base.size;
 218
 219         obj->pages = st;
 220         return 0;
 221 }
 222
 223 static void
 224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj)
 225 {
 226         int ret;
 227
 228         BUG_ON(obj->madv == __I915_MADV_PURGED);
 229
 230         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 231         if (WARN_ON(ret)) {
 232                 /* In the event of a disaster, abandon all caches and
 233                  * hope for the best.
 234                  */
 235                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
 236         }
 237
 238         if (obj->madv == I915_MADV_DONTNEED)
 239                 obj->dirty = 0;
 240
 241         if (obj->dirty) {
 242                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 243                 char *vaddr = obj->phys_handle->vaddr;
 244                 int i;
 245
 246                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 247                         struct page *page;
 248                         char *dst;
 249
 250                         page = shmem_read_mapping_page(mapping, i);
 251                         if (IS_ERR(page))
 252                                 continue;
 253
 254                         dst = kmap_atomic(page);
 255                         drm_clflush_virt_range(vaddr, PAGE_SIZE);
 256                         memcpy(dst, vaddr, PAGE_SIZE);
 257                         kunmap_atomic(dst);
 258
 259                         set_page_dirty(page);
 260                         if (obj->madv == I915_MADV_WILLNEED)
 261                                 mark_page_accessed(page);
 262                         put_page(page);
 263                         vaddr += PAGE_SIZE;
 264                 }
 265                 obj->dirty = 0;
 266         }
 267
 268         sg_free_table(obj->pages);
 269         kfree(obj->pages);
 270 }
 271
 272 static void
 273 i915_gem_object_release_phys(struct drm_i915_gem_object *obj)
 274 {
 275         drm_pci_free(obj->base.dev, obj->phys_handle);
 276 }
 277
 278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops = {
 279         .get_pages = i915_gem_object_get_pages_phys,
 280         .put_pages = i915_gem_object_put_pages_phys,
 281         .release = i915_gem_object_release_phys,
 282 };
 283
 284 static int
 285 drop_pages(struct drm_i915_gem_object *obj)
 286 {
 287         struct i915_vma *vma, *next;
 288         int ret;
 289
 290         drm_gem_object_reference(&obj->base);
 291         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link)
 292                 if (i915_vma_unbind(vma))
 293                         break;
 294
 295         ret = i915_gem_object_put_pages(obj);
 296         drm_gem_object_unreference(&obj->base);
 297
 298         return ret;
 299 }
 300
 301 int
 302 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 303                             int align)
 304 {
 305         drm_dma_handle_t *phys;
 306         int ret;
 307
 308         if (obj->phys_handle) {
 309                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 310                         return -EBUSY;
 311
 312                 return 0;
 313         }
 314
 315         if (obj->madv != I915_MADV_WILLNEED)
 316                 return -EFAULT;
 317
 318         if (obj->base.filp == NULL)
 319                 return -EINVAL;
 320
 321         ret = drop_pages(obj);
 322         if (ret)
 323                 return ret;
 324
 325         /* create a new object */
 326         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 327         if (!phys)
 328                 return -ENOMEM;
 329
 330         obj->phys_handle = phys;
 331         obj->ops = &i915_gem_phys_ops;
 332
 333         return i915_gem_object_get_pages(obj);
 334 }
 335
 336 static int
 337 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 338                      struct drm_i915_gem_pwrite *args,
 339                      struct drm_file *file_priv)
 340 {
 341         struct drm_device *dev = obj->base.dev;
 342         void *vaddr = obj->phys_handle->vaddr + args->offset;
 343         char __user *user_data = u64_to_user_ptr(args->data_ptr);
 344         int ret = 0;
 345
 346         /* We manually control the domain here and pretend that it
 347          * remains coherent i.e. in the GTT domain, like shmem_pwrite.
 348          */
 349         ret = i915_gem_object_wait_rendering(obj, false);
 350         if (ret)
 351                 return ret;
 352
 353         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
 354         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 355                 unsigned long unwritten;
 356
 357                 /* The physical object once assigned is fixed for the lifetime
 358                  * of the obj, so we can safely drop the lock and continue
 359                  * to access vaddr.
 360                  */
 361                 mutex_unlock(&dev->struct_mutex);
 362                 unwritten = copy_from_user(vaddr, user_data, args->size);
 363                 mutex_lock(&dev->struct_mutex);
 364                 if (unwritten) {
 365                         ret = -EFAULT;
 366                         goto out;
 367                 }
 368         }
 369
 370         drm_clflush_virt_range(vaddr, args->size);
 371         i915_gem_chipset_flush(to_i915(dev));
 372
 373 out:
 374         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
 375         return ret;
 376 }
 377
 378 void *i915_gem_object_alloc(struct drm_device *dev)
 379 {
 380         struct drm_i915_private *dev_priv = dev->dev_private;
 381         return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
 382 }
 383
 384 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 385 {
 386         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 387         kmem_cache_free(dev_priv->objects, obj);
 388 }
 389
 390 static int
 391 i915_gem_create(struct drm_file *file,
 392                 struct drm_device *dev,
 393                 uint64_t size,
 394                 uint32_t *handle_p)
 395 {
 396         struct drm_i915_gem_object *obj;
 397         int ret;
 398         u32 handle;
 399
 400         size = roundup(size, PAGE_SIZE);
 401         if (size == 0)
 402                 return -EINVAL;
 403
 404         /* Allocate the new object */
 405         obj = i915_gem_object_create(dev, size);
 406         if (IS_ERR(obj))
 407                 return PTR_ERR(obj);
 408
 409         ret = drm_gem_handle_create(file, &obj->base, &handle);
 410         /* drop reference from allocate - handle holds it now */
 411         drm_gem_object_unreference_unlocked(&obj->base);
 412         if (ret)
 413                 return ret;
 414
 415         *handle_p = handle;
 416         return 0;
 417 }
 418
 419 int
 420 i915_gem_dumb_create(struct drm_file *file,
 421                      struct drm_device *dev,
 422                      struct drm_mode_create_dumb *args)
 423 {
 424         /* have to work out size/pitch and return them */
 425         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 426         args->size = args->pitch * args->height;
 427         return i915_gem_create(file, dev,
 428                                args->size, &args->handle);
 429 }
 430
 431 /**
 432  * Creates a new mm object and returns a handle to it.
 433  * @dev: drm device pointer
 434  * @data: ioctl data blob
 435  * @file: drm file pointer
 436  */
 437 int
 438 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 439                       struct drm_file *file)
 440 {
 441         struct drm_i915_gem_create *args = data;
 442
 443         return i915_gem_create(file, dev,
 444                                args->size, &args->handle);
 445 }
 446
 447 static inline int
 448 __copy_to_user_swizzled(char __user *cpu_vaddr,
 449                         const char *gpu_vaddr, int gpu_offset,
 450                         int length)
 451 {
 452         int ret, cpu_offset = 0;
 453
 454         while (length > 0) {
 455                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 456                 int this_length = min(cacheline_end - gpu_offset, length);
 457                 int swizzled_gpu_offset = gpu_offset ^ 64;
 458
 459                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 460                                      gpu_vaddr + swizzled_gpu_offset,
 461                                      this_length);
 462                 if (ret)
 463                         return ret + length;
 464
 465                 cpu_offset += this_length;
 466                 gpu_offset += this_length;
 467                 length -= this_length;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static inline int
 474 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 475                           const char __user *cpu_vaddr,
 476                           int length)
 477 {
 478         int ret, cpu_offset = 0;
 479
 480         while (length > 0) {
 481                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 482                 int this_length = min(cacheline_end - gpu_offset, length);
 483                 int swizzled_gpu_offset = gpu_offset ^ 64;
 484
 485                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 486                                        cpu_vaddr + cpu_offset,
 487                                        this_length);
 488                 if (ret)
 489                         return ret + length;
 490
 491                 cpu_offset += this_length;
 492                 gpu_offset += this_length;
 493                 length -= this_length;
 494         }
 495
 496         return 0;
 497 }
 498
 499 /*
 500  * Pins the specified object's pages and synchronizes the object with
 501  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 502  * flush the object from the CPU cache.
 503  */
 504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 505                                     int *needs_clflush)
 506 {
 507         int ret;
 508
 509         *needs_clflush = 0;
 510
 511         if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
 512                 return -EINVAL;
 513
 514         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 515                 /* If we're not in the cpu read domain, set ourself into the gtt
 516                  * read domain and manually flush cachelines (if required). This
 517                  * optimizes for the case when the gpu will dirty the data
 518                  * anyway again before the next pread happens. */
 519                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 520                                                         obj->cache_level);
 521                 ret = i915_gem_object_wait_rendering(obj, true);
 522                 if (ret)
 523                         return ret;
 524         }
 525
 526         ret = i915_gem_object_get_pages(obj);
 527         if (ret)
 528                 return ret;
 529
 530         i915_gem_object_pin_pages(obj);
 531
 532         return ret;
 533 }
 534
 535 /* Per-page copy function for the shmem pread fastpath.
 536  * Flushes invalid cachelines before reading the target if
 537  * needs_clflush is set. */
 538 static int
 539 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 540                  char __user *user_data,
 541                  bool page_do_bit17_swizzling, bool needs_clflush)
 542 {
 543         char *vaddr;
 544         int ret;
 545
 546         if (unlikely(page_do_bit17_swizzling))
 547                 return -EINVAL;
 548
 549         vaddr = kmap_atomic(page);
 550         if (needs_clflush)
 551                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 552                                        page_length);
 553         ret = __copy_to_user_inatomic(user_data,
 554                                       vaddr + shmem_page_offset,
 555                                       page_length);
 556         kunmap_atomic(vaddr);
 557
 558         return ret ? -EFAULT : 0;
 559 }
 560
 561 static void
 562 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 563                              bool swizzled)
 564 {
 565         if (unlikely(swizzled)) {
 566                 unsigned long start = (unsigned long) addr;
 567                 unsigned long end = (unsigned long) addr + length;
 568
 569                 /* For swizzling simply ensure that we always flush both
 570                  * channels. Lame, but simple and it works. Swizzled
 571                  * pwrite/pread is far from a hotpath - current userspace
 572                  * doesn't use it at all. */
 573                 start = round_down(start, 128);
 574                 end = round_up(end, 128);
 575
 576                 drm_clflush_virt_range((void *)start, end - start);
 577         } else {
 578                 drm_clflush_virt_range(addr, length);
 579         }
 580
 581 }
 582
 583 /* Only difference to the fast-path function is that this can handle bit17
 584  * and uses non-atomic copy and kmap functions. */
 585 static int
 586 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 587                  char __user *user_data,
 588                  bool page_do_bit17_swizzling, bool needs_clflush)
 589 {
 590         char *vaddr;
 591         int ret;
 592
 593         vaddr = kmap(page);
 594         if (needs_clflush)
 595                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 596                                              page_length,
 597                                              page_do_bit17_swizzling);
 598
 599         if (page_do_bit17_swizzling)
 600                 ret = __copy_to_user_swizzled(user_data,
 601                                               vaddr, shmem_page_offset,
 602                                               page_length);
 603         else
 604                 ret = __copy_to_user(user_data,
 605                                      vaddr + shmem_page_offset,
 606                                      page_length);
 607         kunmap(page);
 608
 609         return ret ? - EFAULT : 0;
 610 }
 611
 612 static inline unsigned long
 613 slow_user_access(struct io_mapping *mapping,
 614                  uint64_t page_base, int page_offset,
 615                  char __user *user_data,
 616                  unsigned long length, bool pwrite)
 617 {
 618         void __iomem *ioaddr;
 619         void *vaddr;
 620         uint64_t unwritten;
 621
 622         ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE);
 623         /* We can use the cpu mem copy function because this is X86. */
 624         vaddr = (void __force *)ioaddr + page_offset;
 625         if (pwrite)
 626                 unwritten = __copy_from_user(vaddr, user_data, length);
 627         else
 628                 unwritten = __copy_to_user(user_data, vaddr, length);
 629
 630         io_mapping_unmap(ioaddr);
 631         return unwritten;
 632 }
 633
 634 static int
 635 i915_gem_gtt_pread(struct drm_device *dev,
 636                    struct drm_i915_gem_object *obj, uint64_t size,
 637                    uint64_t data_offset, uint64_t data_ptr)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 641         struct drm_mm_node node;
 642         char __user *user_data;
 643         uint64_t remain;
 644         uint64_t offset;
 645         int ret;
 646
 647         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
 648         if (ret) {
 649                 ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE);
 650                 if (ret)
 651                         goto out;
 652
 653                 ret = i915_gem_object_get_pages(obj);
 654                 if (ret) {
 655                         remove_mappable_node(&node);
 656                         goto out;
 657                 }
 658
 659                 i915_gem_object_pin_pages(obj);
 660         } else {
 661                 node.start = i915_gem_obj_ggtt_offset(obj);
 662                 node.allocated = false;
 663                 ret = i915_gem_object_put_fence(obj);
 664                 if (ret)
 665                         goto out_unpin;
 666         }
 667
 668         ret = i915_gem_object_set_to_gtt_domain(obj, false);
 669         if (ret)
 670                 goto out_unpin;
 671
 672         user_data = u64_to_user_ptr(data_ptr);
 673         remain = size;
 674         offset = data_offset;
 675
 676         mutex_unlock(&dev->struct_mutex);
 677         if (likely(!i915.prefault_disable)) {
 678                 ret = fault_in_multipages_writeable(user_data, remain);
 679                 if (ret) {
 680                         mutex_lock(&dev->struct_mutex);
 681                         goto out_unpin;
 682                 }
 683         }
 684
 685         while (remain > 0) {
 686                 /* Operation in this page
 687                  *
 688                  * page_base = page offset within aperture
 689                  * page_offset = offset within page
 690                  * page_length = bytes to copy for this page
 691                  */
 692                 u32 page_base = node.start;
 693                 unsigned page_offset = offset_in_page(offset);
 694                 unsigned page_length = PAGE_SIZE - page_offset;
 695                 page_length = remain < page_length ? remain : page_length;
 696                 if (node.allocated) {
 697                         wmb();
 698                         ggtt->base.insert_page(&ggtt->base,
 699                                                i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
 700                                                node.start,
 701                                                I915_CACHE_NONE, 0);
 702                         wmb();
 703                 } else {
 704                         page_base += offset & PAGE_MASK;
 705                 }
 706                 /* This is a slow read/write as it tries to read from
 707                  * and write to user memory which may result into page
 708                  * faults, and so we cannot perform this under struct_mutex.
 709                  */
 710                 if (slow_user_access(ggtt->mappable, page_base,
 711                                      page_offset, user_data,
 712                                      page_length, false)) {
 713                         ret = -EFAULT;
 714                         break;
 715                 }
 716
 717                 remain -= page_length;
 718                 user_data += page_length;
 719                 offset += page_length;
 720         }
 721
 722         mutex_lock(&dev->struct_mutex);
 723         if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
 724                 /* The user has modified the object whilst we tried
 725                  * reading from it, and we now have no idea what domain
 726                  * the pages should be in. As we have just been touching
 727                  * them directly, flush everything back to the GTT
 728                  * domain.
 729                  */
 730                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
 731         }
 732
 733 out_unpin:
 734         if (node.allocated) {
 735                 wmb();
 736                 ggtt->base.clear_range(&ggtt->base,
 737                                        node.start, node.size,
 738                                        true);
 739                 i915_gem_object_unpin_pages(obj);
 740                 remove_mappable_node(&node);
 741         } else {
 742                 i915_gem_object_ggtt_unpin(obj);
 743         }
 744 out:
 745         return ret;
 746 }
 747
 748 static int
 749 i915_gem_shmem_pread(struct drm_device *dev,
 750                      struct drm_i915_gem_object *obj,
 751                      struct drm_i915_gem_pread *args,
 752                      struct drm_file *file)
 753 {
 754         char __user *user_data;
 755         ssize_t remain;
 756         loff_t offset;
 757         int shmem_page_offset, page_length, ret = 0;
 758         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 759         int prefaulted = 0;
 760         int needs_clflush = 0;
 761         struct sg_page_iter sg_iter;
 762
 763         if (!i915_gem_object_has_struct_page(obj))
 764                 return -ENODEV;
 765
 766         user_data = u64_to_user_ptr(args->data_ptr);
 767         remain = args->size;
 768
 769         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 770
 771         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 772         if (ret)
 773                 return ret;
 774
 775         offset = args->offset;
 776
 777         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 778                          offset >> PAGE_SHIFT) {
 779                 struct page *page = sg_page_iter_page(&sg_iter);
 780
 781                 if (remain <= 0)
 782                         break;
 783
 784                 /* Operation in this page
 785                  *
 786                  * shmem_page_offset = offset within page in shmem file
 787                  * page_length = bytes to copy for this page
 788                  */
 789                 shmem_page_offset = offset_in_page(offset);
 790                 page_length = remain;
 791                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 792                         page_length = PAGE_SIZE - shmem_page_offset;
 793
 794                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 795                         (page_to_phys(page) & (1 << 17)) != 0;
 796
 797                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 798                                        user_data, page_do_bit17_swizzling,
 799                                        needs_clflush);
 800                 if (ret == 0)
 801                         goto next_page;
 802
 803                 mutex_unlock(&dev->struct_mutex);
 804
 805                 if (likely(!i915.prefault_disable) && !prefaulted) {
 806                         ret = fault_in_multipages_writeable(user_data, remain);
 807                         /* Userspace is tricking us, but we've already clobbered
 808                          * its pages with the prefault and promised to write the
 809                          * data up to the first fault. Hence ignore any errors
 810                          * and just continue. */
 811                         (void)ret;
 812                         prefaulted = 1;
 813                 }
 814
 815                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 816                                        user_data, page_do_bit17_swizzling,
 817                                        needs_clflush);
 818
 819                 mutex_lock(&dev->struct_mutex);
 820
 821                 if (ret)
 822                         goto out;
 823
 824 next_page:
 825                 remain -= page_length;
 826                 user_data += page_length;
 827                 offset += page_length;
 828         }
 829
 830 out:
 831         i915_gem_object_unpin_pages(obj);
 832
 833         return ret;
 834 }
 835
 836 /**
 837  * Reads data from the object referenced by handle.
 838  * @dev: drm device pointer
 839  * @data: ioctl data blob
 840  * @file: drm file pointer
 841  *
 842  * On error, the contents of *data are undefined.
 843  */
 844 int
 845 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 846                      struct drm_file *file)
 847 {
 848         struct drm_i915_gem_pread *args = data;
 849         struct drm_i915_gem_object *obj;
 850         int ret = 0;
 851
 852         if (args->size == 0)
 853                 return 0;
 854
 855         if (!access_ok(VERIFY_WRITE,
 856                        u64_to_user_ptr(args->data_ptr),
 857                        args->size))
 858                 return -EFAULT;
 859
 860         ret = i915_mutex_lock_interruptible(dev);
 861         if (ret)
 862                 return ret;
 863
 864         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
 865         if (&obj->base == NULL) {
 866                 ret = -ENOENT;
 867                 goto unlock;
 868         }
 869
 870         /* Bounds check source.  */
 871         if (args->offset > obj->base.size ||
 872             args->size > obj->base.size - args->offset) {
 873                 ret = -EINVAL;
 874                 goto out;
 875         }
 876
 877         trace_i915_gem_object_pread(obj, args->offset, args->size);
 878
 879         ret = i915_gem_shmem_pread(dev, obj, args, file);
 880
 881         /* pread for non shmem backed objects */
 882         if (ret == -EFAULT || ret == -ENODEV)
 883                 ret = i915_gem_gtt_pread(dev, obj, args->size,
 884                                         args->offset, args->data_ptr);
 885
 886 out:
 887         drm_gem_object_unreference(&obj->base);
 888 unlock:
 889         mutex_unlock(&dev->struct_mutex);
 890         return ret;
 891 }
 892
 893 /* This is the fast write path which cannot handle
 894  * page faults in the source data
 895  */
 896
 897 static inline int
 898 fast_user_write(struct io_mapping *mapping,
 899                 loff_t page_base, int page_offset,
 900                 char __user *user_data,
 901                 int length)
 902 {
 903         void __iomem *vaddr_atomic;
 904         void *vaddr;
 905         unsigned long unwritten;
 906
 907         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 908         /* We can use the cpu mem copy function because this is X86. */
 909         vaddr = (void __force*)vaddr_atomic + page_offset;
 910         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 911                                                       user_data, length);
 912         io_mapping_unmap_atomic(vaddr_atomic);
 913         return unwritten;
 914 }
 915
 916 /**
 917  * This is the fast pwrite path, where we copy the data directly from the
 918  * user into the GTT, uncached.
 919  * @dev: drm device pointer
 920  * @obj: i915 gem object
 921  * @args: pwrite arguments structure
 922  * @file: drm file pointer
 923  */
 924 static int
 925 i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915,
 926                          struct drm_i915_gem_object *obj,
 927                          struct drm_i915_gem_pwrite *args,
 928                          struct drm_file *file)
 929 {
 930         struct i915_ggtt *ggtt = &i915->ggtt;
 931         struct drm_device *dev = obj->base.dev;
 932         struct drm_mm_node node;
 933         uint64_t remain, offset;
 934         char __user *user_data;
 935         int ret;
 936         bool hit_slow_path = false;
 937
 938         if (obj->tiling_mode != I915_TILING_NONE)
 939                 return -EFAULT;
 940
 941         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 942         if (ret) {
 943                 ret = insert_mappable_node(i915, &node, PAGE_SIZE);
 944                 if (ret)
 945                         goto out;
 946
 947                 ret = i915_gem_object_get_pages(obj);
 948                 if (ret) {
 949                         remove_mappable_node(&node);
 950                         goto out;
 951                 }
 952
 953                 i915_gem_object_pin_pages(obj);
 954         } else {
 955                 node.start = i915_gem_obj_ggtt_offset(obj);
 956                 node.allocated = false;
 957                 ret = i915_gem_object_put_fence(obj);
 958                 if (ret)
 959                         goto out_unpin;
 960         }
 961
 962         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 963         if (ret)
 964                 goto out_unpin;
 965
 966         intel_fb_obj_invalidate(obj, ORIGIN_GTT);
 967         obj->dirty = true;
 968
 969         user_data = u64_to_user_ptr(args->data_ptr);
 970         offset = args->offset;
 971         remain = args->size;
 972         while (remain) {
 973                 /* Operation in this page
 974                  *
 975                  * page_base = page offset within aperture
 976                  * page_offset = offset within page
 977                  * page_length = bytes to copy for this page
 978                  */
 979                 u32 page_base = node.start;
 980                 unsigned page_offset = offset_in_page(offset);
 981                 unsigned page_length = PAGE_SIZE - page_offset;
 982                 page_length = remain < page_length ? remain : page_length;
 983                 if (node.allocated) {
 984                         wmb(); /* flush the write before we modify the GGTT */
 985                         ggtt->base.insert_page(&ggtt->base,
 986                                                i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT),
 987                                                node.start, I915_CACHE_NONE, 0);
 988                         wmb(); /* flush modifications to the GGTT (insert_page) */
 989                 } else {
 990                         page_base += offset & PAGE_MASK;
 991                 }
 992                 /* If we get a fault while copying data, then (presumably) our
 993                  * source page isn't available.  Return the error and we'll
 994                  * retry in the slow path.
 995                  * If the object is non-shmem backed, we retry again with the
 996                  * path that handles page fault.
 997                  */
 998                 if (fast_user_write(ggtt->mappable, page_base,
 999                                     page_offset, user_data, page_length)) {
1000                         hit_slow_path = true;
1001                         mutex_unlock(&dev->struct_mutex);
1002                         if (slow_user_access(ggtt->mappable,
1003                                              page_base,
1004                                              page_offset, user_data,
1005                                              page_length, true)) {
1006                                 ret = -EFAULT;
1007                                 mutex_lock(&dev->struct_mutex);
1008                                 goto out_flush;
1009                         }
1010
1011                         mutex_lock(&dev->struct_mutex);
1012                 }
1013
1014                 remain -= page_length;
1015                 user_data += page_length;
1016                 offset += page_length;
1017         }
1018
1019 out_flush:
1020         if (hit_slow_path) {
1021                 if (ret == 0 &&
1022                     (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) {
1023                         /* The user has modified the object whilst we tried
1024                          * reading from it, and we now have no idea what domain
1025                          * the pages should be in. As we have just been touching
1026                          * them directly, flush everything back to the GTT
1027                          * domain.
1028                          */
1029                         ret = i915_gem_object_set_to_gtt_domain(obj, false);
1030                 }
1031         }
1032
1033         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
1034 out_unpin:
1035         if (node.allocated) {
1036                 wmb();
1037                 ggtt->base.clear_range(&ggtt->base,
1038                                        node.start, node.size,
1039                                        true);
1040                 i915_gem_object_unpin_pages(obj);
1041                 remove_mappable_node(&node);
1042         } else {
1043                 i915_gem_object_ggtt_unpin(obj);
1044         }
1045 out:
1046         return ret;
1047 }
1048
1049 /* Per-page copy function for the shmem pwrite fastpath.
1050  * Flushes invalid cachelines before writing to the target if
1051  * needs_clflush_before is set and flushes out any written cachelines after
1052  * writing if needs_clflush is set. */
1053 static int
1054 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
1055                   char __user *user_data,
1056                   bool page_do_bit17_swizzling,
1057                   bool needs_clflush_before,
1058                   bool needs_clflush_after)
1059 {
1060         char *vaddr;
1061         int ret;
1062
1063         if (unlikely(page_do_bit17_swizzling))
1064                 return -EINVAL;
1065
1066         vaddr = kmap_atomic(page);
1067         if (needs_clflush_before)
1068                 drm_clflush_virt_range(vaddr + shmem_page_offset,
1069                                        page_length);
1070         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
1071                                         user_data, page_length);
1072         if (needs_clflush_after)
1073                 drm_clflush_virt_range(vaddr + shmem_page_offset,
1074                                        page_length);
1075         kunmap_atomic(vaddr);
1076
1077         return ret ? -EFAULT : 0;
1078 }
1079
1080 /* Only difference to the fast-path function is that this can handle bit17
1081  * and uses non-atomic copy and kmap functions. */
1082 static int
1083 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
1084                   char __user *user_data,
1085                   bool page_do_bit17_swizzling,
1086                   bool needs_clflush_before,
1087                   bool needs_clflush_after)
1088 {
1089         char *vaddr;
1090         int ret;
1091
1092         vaddr = kmap(page);
1093         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
1094                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1095                                              page_length,
1096                                              page_do_bit17_swizzling);
1097         if (page_do_bit17_swizzling)
1098                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
1099                                                 user_data,
1100                                                 page_length);
1101         else
1102                 ret = __copy_from_user(vaddr + shmem_page_offset,
1103                                        user_data,
1104                                        page_length);
1105         if (needs_clflush_after)
1106                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
1107                                              page_length,
1108                                              page_do_bit17_swizzling);
1109         kunmap(page);
1110
1111         return ret ? -EFAULT : 0;
1112 }
1113
1114 static int
1115 i915_gem_shmem_pwrite(struct drm_device *dev,
1116                       struct drm_i915_gem_object *obj,
1117                       struct drm_i915_gem_pwrite *args,
1118                       struct drm_file *file)
1119 {
1120         ssize_t remain;
1121         loff_t offset;
1122         char __user *user_data;
1123         int shmem_page_offset, page_length, ret = 0;
1124         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
1125         int hit_slowpath = 0;
1126         int needs_clflush_after = 0;
1127         int needs_clflush_before = 0;
1128         struct sg_page_iter sg_iter;
1129
1130         user_data = u64_to_user_ptr(args->data_ptr);
1131         remain = args->size;
1132
1133         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
1134
1135         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1136                 /* If we're not in the cpu write domain, set ourself into the gtt
1137                  * write domain and manually flush cachelines (if required). This
1138                  * optimizes for the case when the gpu will use the data
1139                  * right away and we therefore have to clflush anyway. */
1140                 needs_clflush_after = cpu_write_needs_clflush(obj);
1141                 ret = i915_gem_object_wait_rendering(obj, false);
1142                 if (ret)
1143                         return ret;
1144         }
1145         /* Same trick applies to invalidate partially written cachelines read
1146          * before writing. */
1147         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
1148                 needs_clflush_before =
1149                         !cpu_cache_is_coherent(dev, obj->cache_level);
1150
1151         ret = i915_gem_object_get_pages(obj);
1152         if (ret)
1153                 return ret;
1154
1155         intel_fb_obj_invalidate(obj, ORIGIN_CPU);
1156
1157         i915_gem_object_pin_pages(obj);
1158
1159         offset = args->offset;
1160         obj->dirty = 1;
1161
1162         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
1163                          offset >> PAGE_SHIFT) {
1164                 struct page *page = sg_page_iter_page(&sg_iter);
1165                 int partial_cacheline_write;
1166
1167                 if (remain <= 0)
1168                         break;
1169
1170                 /* Operation in this page
1171                  *
1172                  * shmem_page_offset = offset within page in shmem file
1173                  * page_length = bytes to copy for this page
1174                  */
1175                 shmem_page_offset = offset_in_page(offset);
1176
1177                 page_length = remain;
1178                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1179                         page_length = PAGE_SIZE - shmem_page_offset;
1180
1181                 /* If we don't overwrite a cacheline completely we need to be
1182                  * careful to have up-to-date data by first clflushing. Don't
1183                  * overcomplicate things and flush the entire patch. */
1184                 partial_cacheline_write = needs_clflush_before &&
1185                         ((shmem_page_offset | page_length)
1186                                 & (boot_cpu_data.x86_clflush_size - 1));
1187
1188                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
1189                         (page_to_phys(page) & (1 << 17)) != 0;
1190
1191                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
1192                                         user_data, page_do_bit17_swizzling,
1193                                         partial_cacheline_write,
1194                                         needs_clflush_after);
1195                 if (ret == 0)
1196                         goto next_page;
1197
1198                 hit_slowpath = 1;
1199                 mutex_unlock(&dev->struct_mutex);
1200                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
1201                                         user_data, page_do_bit17_swizzling,
1202                                         partial_cacheline_write,
1203                                         needs_clflush_after);
1204
1205                 mutex_lock(&dev->struct_mutex);
1206
1207                 if (ret)
1208                         goto out;
1209
1210 next_page:
1211                 remain -= page_length;
1212                 user_data += page_length;
1213                 offset += page_length;
1214         }
1215
1216 out:
1217         i915_gem_object_unpin_pages(obj);
1218
1219         if (hit_slowpath) {
1220                 /*
1221                  * Fixup: Flush cpu caches in case we didn't flush the dirty
1222                  * cachelines in-line while writing and the object moved
1223                  * out of the cpu write domain while we've dropped the lock.
1224                  */
1225                 if (!needs_clflush_after &&
1226                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
1227                         if (i915_gem_clflush_object(obj, obj->pin_display))
1228                                 needs_clflush_after = true;
1229                 }
1230         }
1231
1232         if (needs_clflush_after)
1233                 i915_gem_chipset_flush(to_i915(dev));
1234         else
1235                 obj->cache_dirty = true;
1236
1237         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
1238         return ret;
1239 }
1240
1241 /**
1242  * Writes data to the object referenced by handle.
1243  * @dev: drm device
1244  * @data: ioctl data blob
1245  * @file: drm file
1246  *
1247  * On error, the contents of the buffer that were to be modified are undefined.
1248  */
1249 int
1250 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1251                       struct drm_file *file)
1252 {
1253         struct drm_i915_private *dev_priv = dev->dev_private;
1254         struct drm_i915_gem_pwrite *args = data;
1255         struct drm_i915_gem_object *obj;
1256         int ret;
1257
1258         if (args->size == 0)
1259                 return 0;
1260
1261         if (!access_ok(VERIFY_READ,
1262                        u64_to_user_ptr(args->data_ptr),
1263                        args->size))
1264                 return -EFAULT;
1265
1266         if (likely(!i915.prefault_disable)) {
1267                 ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr),
1268                                                    args->size);
1269                 if (ret)
1270                         return -EFAULT;
1271         }
1272
1273         intel_runtime_pm_get(dev_priv);
1274
1275         ret = i915_mutex_lock_interruptible(dev);
1276         if (ret)
1277                 goto put_rpm;
1278
1279         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1280         if (&obj->base == NULL) {
1281                 ret = -ENOENT;
1282                 goto unlock;
1283         }
1284
1285         /* Bounds check destination. */
1286         if (args->offset > obj->base.size ||
1287             args->size > obj->base.size - args->offset) {
1288                 ret = -EINVAL;
1289                 goto out;
1290         }
1291
1292         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1293
1294         ret = -EFAULT;
1295         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1296          * it would end up going through the fenced access, and we'll get
1297          * different detiling behavior between reading and writing.
1298          * pread/pwrite currently are reading and writing from the CPU
1299          * perspective, requiring manual detiling by the client.
1300          */
1301         if (!i915_gem_object_has_struct_page(obj) ||
1302             cpu_write_needs_clflush(obj)) {
1303                 ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file);
1304                 /* Note that the gtt paths might fail with non-page-backed user
1305                  * pointers (e.g. gtt mappings when moving data between
1306                  * textures). Fallback to the shmem path in that case. */
1307         }
1308
1309         if (ret == -EFAULT) {
1310                 if (obj->phys_handle)
1311                         ret = i915_gem_phys_pwrite(obj, args, file);
1312                 else if (i915_gem_object_has_struct_page(obj))
1313                         ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1314                 else
1315                         ret = -ENODEV;
1316         }
1317
1318 out:
1319         drm_gem_object_unreference(&obj->base);
1320 unlock:
1321         mutex_unlock(&dev->struct_mutex);
1322 put_rpm:
1323         intel_runtime_pm_put(dev_priv);
1324
1325         return ret;
1326 }
1327
1328 static int
1329 i915_gem_check_wedge(unsigned reset_counter, bool interruptible)
1330 {
1331         if (__i915_terminally_wedged(reset_counter))
1332                 return -EIO;
1333
1334         if (__i915_reset_in_progress(reset_counter)) {
1335                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1336                  * -EIO unconditionally for these. */
1337                 if (!interruptible)
1338                         return -EIO;
1339
1340                 return -EAGAIN;
1341         }
1342
1343         return 0;
1344 }
1345
1346 static unsigned long local_clock_us(unsigned *cpu)
1347 {
1348         unsigned long t;
1349
1350         /* Cheaply and approximately convert from nanoseconds to microseconds.
1351          * The result and subsequent calculations are also defined in the same
1352          * approximate microseconds units. The principal source of timing
1353          * error here is from the simple truncation.
1354          *
1355          * Note that local_clock() is only defined wrt to the current CPU;
1356          * the comparisons are no longer valid if we switch CPUs. Instead of
1357          * blocking preemption for the entire busywait, we can detect the CPU
1358          * switch and use that as indicator of system load and a reason to
1359          * stop busywaiting, see busywait_stop().
1360          */
1361         *cpu = get_cpu();
1362         t = local_clock() >> 10;
1363         put_cpu();
1364
1365         return t;
1366 }
1367
1368 static bool busywait_stop(unsigned long timeout, unsigned cpu)
1369 {
1370         unsigned this_cpu;
1371
1372         if (time_after(local_clock_us(&this_cpu), timeout))
1373                 return true;
1374
1375         return this_cpu != cpu;
1376 }
1377
1378 static bool __i915_spin_request(struct drm_i915_gem_request *req, int state)
1379 {
1380         unsigned long timeout;
1381         unsigned cpu;
1382
1383         /* When waiting for high frequency requests, e.g. during synchronous
1384          * rendering split between the CPU and GPU, the finite amount of time
1385          * required to set up the irq and wait upon it limits the response
1386          * rate. By busywaiting on the request completion for a short while we
1387          * can service the high frequency waits as quick as possible. However,
1388          * if it is a slow request, we want to sleep as quickly as possible.
1389          * The tradeoff between waiting and sleeping is roughly the time it
1390          * takes to sleep on a request, on the order of a microsecond.
1391          */
1392
1393         /* Only spin if we know the GPU is processing this request */
1394         if (!i915_gem_request_started(req, true))
1395                 return false;
1396
1397         timeout = local_clock_us(&cpu) + 5;
1398         do {
1399                 if (i915_gem_request_completed(req, true))
1400                         return true;
1401
1402                 if (signal_pending_state(state, current))
1403                         break;
1404
1405                 if (busywait_stop(timeout, cpu))
1406                         break;
1407
1408                 cpu_relax_lowlatency();
1409         } while (!need_resched());
1410
1411         return false;
1412 }
1413
1414 /**
1415  * __i915_wait_request - wait until execution of request has finished
1416  * @req: duh!
1417  * @interruptible: do an interruptible wait (normally yes)
1418  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1419  * @rps: RPS client
1420  *
1421  * Note: It is of utmost importance that the passed in seqno and reset_counter
1422  * values have been read by the caller in an smp safe manner. Where read-side
1423  * locks are involved, it is sufficient to read the reset_counter before
1424  * unlocking the lock that protects the seqno. For lockless tricks, the
1425  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1426  * inserted.
1427  *
1428  * Returns 0 if the request was found within the alloted time. Else returns the
1429  * errno with remaining time filled in timeout argument.
1430  */
1431 int __i915_wait_request(struct drm_i915_gem_request *req,
1432                         bool interruptible,
1433                         s64 *timeout,
1434                         struct intel_rps_client *rps)
1435 {
1436         int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
1437         DEFINE_WAIT(reset);
1438         struct intel_wait wait;
1439         unsigned long timeout_remain;
1440         s64 before = 0; /* Only to silence a compiler warning. */
1441         int ret = 0;
1442
1443         might_sleep();
1444
1445         if (list_empty(&req->list))
1446                 return 0;
1447
1448         if (i915_gem_request_completed(req, true))
1449                 return 0;
1450
1451         timeout_remain = MAX_SCHEDULE_TIMEOUT;
1452         if (timeout) {
1453                 if (WARN_ON(*timeout < 0))
1454                         return -EINVAL;
1455
1456                 if (*timeout == 0)
1457                         return -ETIME;
1458
1459                 timeout_remain = nsecs_to_jiffies_timeout(*timeout);
1460
1461                 /*
1462                  * Record current time in case interrupted by signal, or wedged.
1463                  */
1464                 before = ktime_get_raw_ns();
1465         }
1466
1467         trace_i915_gem_request_wait_begin(req);
1468
1469         if (INTEL_INFO(req->i915)->gen >= 6)
1470                 gen6_rps_boost(req->i915, rps, req->emitted_jiffies);
1471
1472         /* Optimistic spin for the next ~jiffie before touching IRQs */
1473         if (__i915_spin_request(req, state))
1474                 goto complete;
1475
1476         set_current_state(state);
1477         add_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1478
1479         intel_wait_init(&wait, req->seqno);
1480         if (intel_engine_add_wait(req->engine, &wait))
1481                 /* In order to check that we haven't missed the interrupt
1482                  * as we enabled it, we need to kick ourselves to do a
1483                  * coherent check on the seqno before we sleep.
1484                  */
1485                 goto wakeup;
1486
1487         for (;;) {
1488                 if (signal_pending_state(state, current)) {
1489                         ret = -ERESTARTSYS;
1490                         break;
1491                 }
1492
1493                 /* Ensure that even if the GPU hangs, we get woken up.
1494                  *
1495                  * However, note that if no one is waiting, we never notice
1496                  * a gpu hang. Eventually, we will have to wait for a resource
1497                  * held by the GPU and so trigger a hangcheck. In the most
1498                  * pathological case, this will be upon memory starvation!
1499                  */
1500                 i915_queue_hangcheck(req->i915);
1501
1502                 timeout_remain = io_schedule_timeout(timeout_remain);
1503                 if (timeout_remain == 0) {
1504                         ret = -ETIME;
1505                         break;
1506                 }
1507
1508                 if (intel_wait_complete(&wait))
1509                         break;
1510
1511                 set_current_state(state);
1512
1513 wakeup:
1514                 /* Carefully check if the request is complete, giving time
1515                  * for the seqno to be visible following the interrupt.
1516                  * We also have to check in case we are kicked by the GPU
1517                  * reset in order to drop the struct_mutex.
1518                  */
1519                 if (__i915_request_irq_complete(req))
1520                         break;
1521         }
1522         remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset);
1523
1524         intel_engine_remove_wait(req->engine, &wait);
1525         __set_current_state(TASK_RUNNING);
1526 complete:
1527         trace_i915_gem_request_wait_end(req);
1528
1529         if (timeout) {
1530                 s64 tres = *timeout - (ktime_get_raw_ns() - before);
1531
1532                 *timeout = tres < 0 ? 0 : tres;
1533
1534                 /*
1535                  * Apparently ktime isn't accurate enough and occasionally has a
1536                  * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1537                  * things up to make the test happy. We allow up to 1 jiffy.
1538                  *
1539                  * This is a regrssion from the timespec->ktime conversion.
1540                  */
1541                 if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000)
1542                         *timeout = 0;
1543         }
1544
1545         return ret;
1546 }
1547
1548 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
1549                                    struct drm_file *file)
1550 {
1551         struct drm_i915_file_private *file_priv;
1552
1553         WARN_ON(!req || !file || req->file_priv);
1554
1555         if (!req || !file)
1556                 return -EINVAL;
1557
1558         if (req->file_priv)
1559                 return -EINVAL;
1560
1561         file_priv = file->driver_priv;
1562
1563         spin_lock(&file_priv->mm.lock);
1564         req->file_priv = file_priv;
1565         list_add_tail(&req->client_list, &file_priv->mm.request_list);
1566         spin_unlock(&file_priv->mm.lock);
1567
1568         req->pid = get_pid(task_pid(current));
1569
1570         return 0;
1571 }
1572
1573 static inline void
1574 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
1575 {
1576         struct drm_i915_file_private *file_priv = request->file_priv;
1577
1578         if (!file_priv)
1579                 return;
1580
1581         spin_lock(&file_priv->mm.lock);
1582         list_del(&request->client_list);
1583         request->file_priv = NULL;
1584         spin_unlock(&file_priv->mm.lock);
1585
1586         put_pid(request->pid);
1587         request->pid = NULL;
1588 }
1589
1590 static void i915_gem_request_retire(struct drm_i915_gem_request *request)
1591 {
1592         trace_i915_gem_request_retire(request);
1593
1594         /* We know the GPU must have read the request to have
1595          * sent us the seqno + interrupt, so use the position
1596          * of tail of the request to update the last known position
1597          * of the GPU head.
1598          *
1599          * Note this requires that we are always called in request
1600          * completion order.
1601          */
1602         request->ringbuf->last_retired_head = request->postfix;
1603
1604         list_del_init(&request->list);
1605         i915_gem_request_remove_from_client(request);
1606
1607         if (request->previous_context) {
1608                 if (i915.enable_execlists)
1609                         intel_lr_context_unpin(request->previous_context,
1610                                                request->engine);
1611         }
1612
1613         i915_gem_context_unreference(request->ctx);
1614         i915_gem_request_unreference(request);
1615 }
1616
1617 static void
1618 __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
1619 {
1620         struct intel_engine_cs *engine = req->engine;
1621         struct drm_i915_gem_request *tmp;
1622
1623         lockdep_assert_held(&engine->i915->dev->struct_mutex);
1624
1625         if (list_empty(&req->list))
1626                 return;
1627
1628         do {
1629                 tmp = list_first_entry(&engine->request_list,
1630                                        typeof(*tmp), list);
1631
1632                 i915_gem_request_retire(tmp);
1633         } while (tmp != req);
1634
1635         WARN_ON(i915_verify_lists(engine->dev));
1636 }
1637
1638 /**
1639  * Waits for a request to be signaled, and cleans up the
1640  * request and object lists appropriately for that event.
1641  * @req: request to wait on
1642  */
1643 int
1644 i915_wait_request(struct drm_i915_gem_request *req)
1645 {
1646         struct drm_i915_private *dev_priv = req->i915;
1647         bool interruptible;
1648         int ret;
1649
1650         interruptible = dev_priv->mm.interruptible;
1651
1652         BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
1653
1654         ret = __i915_wait_request(req, interruptible, NULL, NULL);
1655         if (ret)
1656                 return ret;
1657
1658         /* If the GPU hung, we want to keep the requests to find the guilty. */
1659         if (!i915_reset_in_progress(&dev_priv->gpu_error))
1660                 __i915_gem_request_retire__upto(req);
1661
1662         return 0;
1663 }
1664
1665 /**
1666  * Ensures that all rendering to the object has completed and the object is
1667  * safe to unbind from the GTT or access from the CPU.
1668  * @obj: i915 gem object
1669  * @readonly: waiting for read access or write
1670  */
1671 int
1672 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1673                                bool readonly)
1674 {
1675         int ret, i;
1676
1677         if (!obj->active)
1678                 return 0;
1679
1680         if (readonly) {
1681                 if (obj->last_write_req != NULL) {
1682                         ret = i915_wait_request(obj->last_write_req);
1683                         if (ret)
1684                                 return ret;
1685
1686                         i = obj->last_write_req->engine->id;
1687                         if (obj->last_read_req[i] == obj->last_write_req)
1688                                 i915_gem_object_retire__read(obj, i);
1689                         else
1690                                 i915_gem_object_retire__write(obj);
1691                 }
1692         } else {
1693                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1694                         if (obj->last_read_req[i] == NULL)
1695                                 continue;
1696
1697                         ret = i915_wait_request(obj->last_read_req[i]);
1698                         if (ret)
1699                                 return ret;
1700
1701                         i915_gem_object_retire__read(obj, i);
1702                 }
1703                 GEM_BUG_ON(obj->active);
1704         }
1705
1706         return 0;
1707 }
1708
1709 static void
1710 i915_gem_object_retire_request(struct drm_i915_gem_object *obj,
1711                                struct drm_i915_gem_request *req)
1712 {
1713         int ring = req->engine->id;
1714
1715         if (obj->last_read_req[ring] == req)
1716                 i915_gem_object_retire__read(obj, ring);
1717         else if (obj->last_write_req == req)
1718                 i915_gem_object_retire__write(obj);
1719
1720         if (!i915_reset_in_progress(&req->i915->gpu_error))
1721                 __i915_gem_request_retire__upto(req);
1722 }
1723
1724 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1725  * as the object state may change during this call.
1726  */
1727 static __must_check int
1728 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1729                                             struct intel_rps_client *rps,
1730                                             bool readonly)
1731 {
1732         struct drm_device *dev = obj->base.dev;
1733         struct drm_i915_private *dev_priv = dev->dev_private;
1734         struct drm_i915_gem_request *requests[I915_NUM_ENGINES];
1735         int ret, i, n = 0;
1736
1737         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1738         BUG_ON(!dev_priv->mm.interruptible);
1739
1740         if (!obj->active)
1741                 return 0;
1742
1743         if (readonly) {
1744                 struct drm_i915_gem_request *req;
1745
1746                 req = obj->last_write_req;
1747                 if (req == NULL)
1748                         return 0;
1749
1750                 requests[n++] = i915_gem_request_reference(req);
1751         } else {
1752                 for (i = 0; i < I915_NUM_ENGINES; i++) {
1753                         struct drm_i915_gem_request *req;
1754
1755                         req = obj->last_read_req[i];
1756                         if (req == NULL)
1757                                 continue;
1758
1759                         requests[n++] = i915_gem_request_reference(req);
1760                 }
1761         }
1762
1763         mutex_unlock(&dev->struct_mutex);
1764         ret = 0;
1765         for (i = 0; ret == 0 && i < n; i++)
1766                 ret = __i915_wait_request(requests[i], true, NULL, rps);
1767         mutex_lock(&dev->struct_mutex);
1768
1769         for (i = 0; i < n; i++) {
1770                 if (ret == 0)
1771                         i915_gem_object_retire_request(obj, requests[i]);
1772                 i915_gem_request_unreference(requests[i]);
1773         }
1774
1775         return ret;
1776 }
1777
1778 static struct intel_rps_client *to_rps_client(struct drm_file *file)
1779 {
1780         struct drm_i915_file_private *fpriv = file->driver_priv;
1781         return &fpriv->rps;
1782 }
1783
1784 static enum fb_op_origin
1785 write_origin(struct drm_i915_gem_object *obj, unsigned domain)
1786 {
1787         return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ?
1788                ORIGIN_GTT : ORIGIN_CPU;
1789 }
1790
1791 /**
1792  * Called when user space prepares to use an object with the CPU, either
1793  * through the mmap ioctl's mapping or a GTT mapping.
1794  * @dev: drm device
1795  * @data: ioctl data blob
1796  * @file: drm file
1797  */
1798 int
1799 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1800                           struct drm_file *file)
1801 {
1802         struct drm_i915_gem_set_domain *args = data;
1803         struct drm_i915_gem_object *obj;
1804         uint32_t read_domains = args->read_domains;
1805         uint32_t write_domain = args->write_domain;
1806         int ret;
1807
1808         /* Only handle setting domains to types used by the CPU. */
1809         if (write_domain & I915_GEM_GPU_DOMAINS)
1810                 return -EINVAL;
1811
1812         if (read_domains & I915_GEM_GPU_DOMAINS)
1813                 return -EINVAL;
1814
1815         /* Having something in the write domain implies it's in the read
1816          * domain, and only that read domain.  Enforce that in the request.
1817          */
1818         if (write_domain != 0 && read_domains != write_domain)
1819                 return -EINVAL;
1820
1821         ret = i915_mutex_lock_interruptible(dev);
1822         if (ret)
1823                 return ret;
1824
1825         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1826         if (&obj->base == NULL) {
1827                 ret = -ENOENT;
1828                 goto unlock;
1829         }
1830
1831         /* Try to flush the object off the GPU without holding the lock.
1832          * We will repeat the flush holding the lock in the normal manner
1833          * to catch cases where we are gazumped.
1834          */
1835         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1836                                                           to_rps_client(file),
1837                                                           !write_domain);
1838         if (ret)
1839                 goto unref;
1840
1841         if (read_domains & I915_GEM_DOMAIN_GTT)
1842                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1843         else
1844                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1845
1846         if (write_domain != 0)
1847                 intel_fb_obj_invalidate(obj, write_origin(obj, write_domain));
1848
1849 unref:
1850         drm_gem_object_unreference(&obj->base);
1851 unlock:
1852         mutex_unlock(&dev->struct_mutex);
1853         return ret;
1854 }
1855
1856 /**
1857  * Called when user space has done writes to this buffer
1858  * @dev: drm device
1859  * @data: ioctl data blob
1860  * @file: drm file
1861  */
1862 int
1863 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1864                          struct drm_file *file)
1865 {
1866         struct drm_i915_gem_sw_finish *args = data;
1867         struct drm_i915_gem_object *obj;
1868         int ret = 0;
1869
1870         ret = i915_mutex_lock_interruptible(dev);
1871         if (ret)
1872                 return ret;
1873
1874         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
1875         if (&obj->base == NULL) {
1876                 ret = -ENOENT;
1877                 goto unlock;
1878         }
1879
1880         /* Pinned buffers may be scanout, so flush the cache */
1881         if (obj->pin_display)
1882                 i915_gem_object_flush_cpu_write_domain(obj);
1883
1884         drm_gem_object_unreference(&obj->base);
1885 unlock:
1886         mutex_unlock(&dev->struct_mutex);
1887         return ret;
1888 }
1889
1890 /**
1891  * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1892  *                       it is mapped to.
1893  * @dev: drm device
1894  * @data: ioctl data blob
1895  * @file: drm file
1896  *
1897  * While the mapping holds a reference on the contents of the object, it doesn't
1898  * imply a ref on the object itself.
1899  *
1900  * IMPORTANT:
1901  *
1902  * DRM driver writers who look a this function as an example for how to do GEM
1903  * mmap support, please don't implement mmap support like here. The modern way
1904  * to implement DRM mmap support is with an mmap offset ioctl (like
1905  * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1906  * That way debug tooling like valgrind will understand what's going on, hiding
1907  * the mmap call in a driver private ioctl will break that. The i915 driver only
1908  * does cpu mmaps this way because we didn't know better.
1909  */
1910 int
1911 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1912                     struct drm_file *file)
1913 {
1914         struct drm_i915_gem_mmap *args = data;
1915         struct drm_gem_object *obj;
1916         unsigned long addr;
1917
1918         if (args->flags & ~(I915_MMAP_WC))
1919                 return -EINVAL;
1920
1921         if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT))
1922                 return -ENODEV;
1923
1924         obj = drm_gem_object_lookup(file, args->handle);
1925         if (obj == NULL)
1926                 return -ENOENT;
1927
1928         /* prime objects have no backing filp to GEM mmap
1929          * pages from.
1930          */
1931         if (!obj->filp) {
1932                 drm_gem_object_unreference_unlocked(obj);
1933                 return -EINVAL;
1934         }
1935
1936         addr = vm_mmap(obj->filp, 0, args->size,
1937                        PROT_READ | PROT_WRITE, MAP_SHARED,
1938                        args->offset);
1939         if (args->flags & I915_MMAP_WC) {
1940                 struct mm_struct *mm = current->mm;
1941                 struct vm_area_struct *vma;
1942
1943                 if (down_write_killable(&mm->mmap_sem)) {
1944                         drm_gem_object_unreference_unlocked(obj);
1945                         return -EINTR;
1946                 }
1947                 vma = find_vma(mm, addr);
1948                 if (vma)
1949                         vma->vm_page_prot =
1950                                 pgprot_writecombine(vm_get_page_prot(vma->vm_flags));
1951                 else
1952                         addr = -ENOMEM;
1953                 up_write(&mm->mmap_sem);
1954
1955                 /* This may race, but that's ok, it only gets set */
1956                 WRITE_ONCE(to_intel_bo(obj)->has_wc_mmap, true);
1957         }
1958         drm_gem_object_unreference_unlocked(obj);
1959         if (IS_ERR((void *)addr))
1960                 return addr;
1961
1962         args->addr_ptr = (uint64_t) addr;
1963
1964         return 0;
1965 }
1966
1967 /**
1968  * i915_gem_fault - fault a page into the GTT
1969  * @vma: VMA in question
1970  * @vmf: fault info
1971  *
1972  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1973  * from userspace.  The fault handler takes care of binding the object to
1974  * the GTT (if needed), allocating and programming a fence register (again,
1975  * only if needed based on whether the old reg is still valid or the object
1976  * is tiled) and inserting a new PTE into the faulting process.
1977  *
1978  * Note that the faulting process may involve evicting existing objects
1979  * from the GTT and/or fence registers to make room.  So performance may
1980  * suffer if the GTT working set is large or there are few fence registers
1981  * left.
1982  */
1983 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1984 {
1985         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1986         struct drm_device *dev = obj->base.dev;
1987         struct drm_i915_private *dev_priv = to_i915(dev);
1988         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1989         struct i915_ggtt_view view = i915_ggtt_view_normal;
1990         pgoff_t page_offset;
1991         unsigned long pfn;
1992         int ret = 0;
1993         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1994
1995         intel_runtime_pm_get(dev_priv);
1996
1997         /* We don't use vmf->pgoff since that has the fake offset */
1998         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1999                 PAGE_SHIFT;
2000
2001         ret = i915_mutex_lock_interruptible(dev);
2002         if (ret)
2003                 goto out;
2004
2005         trace_i915_gem_object_fault(obj, page_offset, true, write);
2006
2007         /* Try to flush the object off the GPU first without holding the lock.
2008          * Upon reacquiring the lock, we will perform our sanity checks and then
2009          * repeat the flush holding the lock in the normal manner to catch cases
2010          * where we are gazumped.
2011          */
2012         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
2013         if (ret)
2014                 goto unlock;
2015
2016         /* Access to snoopable pages through the GTT is incoherent. */
2017         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
2018                 ret = -EFAULT;
2019                 goto unlock;
2020         }
2021
2022         /* Use a partial view if the object is bigger than the aperture. */
2023         if (obj->base.size >= ggtt->mappable_end &&
2024             obj->tiling_mode == I915_TILING_NONE) {
2025                 static const unsigned int chunk_size = 256; // 1 MiB
2026
2027                 memset(&view, 0, sizeof(view));
2028                 view.type = I915_GGTT_VIEW_PARTIAL;
2029                 view.params.partial.offset = rounddown(page_offset, chunk_size);
2030                 view.params.partial.size =
2031                         min_t(unsigned int,
2032                               chunk_size,
2033                               (vma->vm_end - vma->vm_start)/PAGE_SIZE -
2034                               view.params.partial.offset);
2035         }
2036
2037         /* Now pin it into the GTT if needed */
2038         ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE);
2039         if (ret)
2040                 goto unlock;
2041
2042         ret = i915_gem_object_set_to_gtt_domain(obj, write);
2043         if (ret)
2044                 goto unpin;
2045
2046         ret = i915_gem_object_get_fence(obj);
2047         if (ret)
2048                 goto unpin;
2049
2050         /* Finally, remap it using the new GTT offset */
2051         pfn = ggtt->mappable_base +
2052                 i915_gem_obj_ggtt_offset_view(obj, &view);
2053         pfn >>= PAGE_SHIFT;
2054
2055         if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) {
2056                 /* Overriding existing pages in partial view does not cause
2057                  * us any trouble as TLBs are still valid because the fault
2058                  * is due to userspace losing part of the mapping or never
2059                  * having accessed it before (at this partials' range).
2060                  */
2061                 unsigned long base = vma->vm_start +
2062                                      (view.params.partial.offset << PAGE_SHIFT);
2063                 unsigned int i;
2064
2065                 for (i = 0; i < view.params.partial.size; i++) {
2066                         ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i);
2067                         if (ret)
2068                                 break;
2069                 }
2070
2071                 obj->fault_mappable = true;
2072         } else {
2073                 if (!obj->fault_mappable) {
2074                         unsigned long size = min_t(unsigned long,
2075                                                    vma->vm_end - vma->vm_start,
2076                                                    obj->base.size);
2077                         int i;
2078
2079                         for (i = 0; i < size >> PAGE_SHIFT; i++) {
2080                                 ret = vm_insert_pfn(vma,
2081                                                     (unsigned long)vma->vm_start + i * PAGE_SIZE,
2082                                                     pfn + i);
2083                                 if (ret)
2084                                         break;
2085                         }
2086
2087                         obj->fault_mappable = true;
2088                 } else
2089                         ret = vm_insert_pfn(vma,
2090                                             (unsigned long)vmf->virtual_address,
2091                                             pfn + page_offset);
2092         }
2093 unpin:
2094         i915_gem_object_ggtt_unpin_view(obj, &view);
2095 unlock:
2096         mutex_unlock(&dev->struct_mutex);
2097 out:
2098         switch (ret) {
2099         case -EIO:
2100                 /*
2101                  * We eat errors when the gpu is terminally wedged to avoid
2102                  * userspace unduly crashing (gl has no provisions for mmaps to
2103                  * fail). But any other -EIO isn't ours (e.g. swap in failure)
2104                  * and so needs to be reported.
2105                  */
2106                 if (!i915_terminally_wedged(&dev_priv->gpu_error)) {
2107                         ret = VM_FAULT_SIGBUS;
2108                         break;
2109                 }
2110         case -EAGAIN:
2111                 /*
2112                  * EAGAIN means the gpu is hung and we'll wait for the error
2113                  * handler to reset everything when re-faulting in
2114                  * i915_mutex_lock_interruptible.
2115                  */
2116         case 0:
2117         case -ERESTARTSYS:
2118         case -EINTR:
2119         case -EBUSY:
2120                 /*
2121                  * EBUSY is ok: this just means that another thread
2122                  * already did the job.
2123                  */
2124                 ret = VM_FAULT_NOPAGE;
2125                 break;
2126         case -ENOMEM:
2127                 ret = VM_FAULT_OOM;
2128                 break;
2129         case -ENOSPC:
2130         case -EFAULT:
2131                 ret = VM_FAULT_SIGBUS;
2132                 break;
2133         default:
2134                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
2135                 ret = VM_FAULT_SIGBUS;
2136                 break;
2137         }
2138
2139         intel_runtime_pm_put(dev_priv);
2140         return ret;
2141 }
2142
2143 /**
2144  * i915_gem_release_mmap - remove physical page mappings
2145  * @obj: obj in question
2146  *
2147  * Preserve the reservation of the mmapping with the DRM core code, but
2148  * relinquish ownership of the pages back to the system.
2149  *
2150  * It is vital that we remove the page mapping if we have mapped a tiled
2151  * object through the GTT and then lose the fence register due to
2152  * resource pressure. Similarly if the object has been moved out of the
2153  * aperture, than pages mapped into userspace must be revoked. Removing the
2154  * mapping will then trigger a page fault on the next user access, allowing
2155  * fixup by i915_gem_fault().
2156  */
2157 void
2158 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
2159 {
2160         /* Serialisation between user GTT access and our code depends upon
2161          * revoking the CPU's PTE whilst the mutex is held. The next user
2162          * pagefault then has to wait until we release the mutex.
2163          */
2164         lockdep_assert_held(&obj->base.dev->struct_mutex);
2165
2166         if (!obj->fault_mappable)
2167                 return;
2168
2169         drm_vma_node_unmap(&obj->base.vma_node,
2170                            obj->base.dev->anon_inode->i_mapping);
2171
2172         /* Ensure that the CPU's PTE are revoked and there are not outstanding
2173          * memory transactions from userspace before we return. The TLB
2174          * flushing implied above by changing the PTE above *should* be
2175          * sufficient, an extra barrier here just provides us with a bit
2176          * of paranoid documentation about our requirement to serialise
2177          * memory writes before touching registers / GSM.
2178          */
2179         wmb();
2180
2181         obj->fault_mappable = false;
2182 }
2183
2184 void
2185 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
2186 {
2187         struct drm_i915_gem_object *obj;
2188
2189         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
2190                 i915_gem_release_mmap(obj);
2191 }
2192
2193 uint32_t
2194 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
2195 {
2196         uint32_t gtt_size;
2197
2198         if (INTEL_INFO(dev)->gen >= 4 ||
2199             tiling_mode == I915_TILING_NONE)
2200                 return size;
2201
2202         /* Previous chips need a power-of-two fence region when tiling */
2203         if (IS_GEN3(dev))
2204                 gtt_size = 1024*1024;
2205         else
2206                 gtt_size = 512*1024;
2207
2208         while (gtt_size < size)
2209                 gtt_size <<= 1;
2210
2211         return gtt_size;
2212 }
2213
2214 /**
2215  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2216  * @dev: drm device
2217  * @size: object size
2218  * @tiling_mode: tiling mode
2219  * @fenced: is fenced alignemned required or not
2220  *
2221  * Return the required GTT alignment for an object, taking into account
2222  * potential fence register mapping.
2223  */
2224 uint32_t
2225 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2226                            int tiling_mode, bool fenced)
2227 {
2228         /*
2229          * Minimum alignment is 4k (GTT page size), but might be greater
2230          * if a fence register is needed for the object.
2231          */
2232         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
2233             tiling_mode == I915_TILING_NONE)
2234                 return 4096;
2235
2236         /*
2237          * Previous chips need to be aligned to the size of the smallest
2238          * fence register that can contain the object.
2239          */
2240         return i915_gem_get_gtt_size(dev, size, tiling_mode);
2241 }
2242
2243 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
2244 {
2245         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2246         int ret;
2247
2248         dev_priv->mm.shrinker_no_lock_stealing = true;
2249
2250         ret = drm_gem_create_mmap_offset(&obj->base);
2251         if (ret != -ENOSPC)
2252                 goto out;
2253
2254         /* Badly fragmented mmap space? The only way we can recover
2255          * space is by destroying unwanted objects. We can't randomly release
2256          * mmap_offsets as userspace expects them to be persistent for the
2257          * lifetime of the objects. The closest we can is to release the
2258          * offsets on purgeable objects by truncating it and marking it purged,
2259          * which prevents userspace from ever using that object again.
2260          */
2261         i915_gem_shrink(dev_priv,
2262                         obj->base.size >> PAGE_SHIFT,
2263                         I915_SHRINK_BOUND |
2264                         I915_SHRINK_UNBOUND |
2265                         I915_SHRINK_PURGEABLE);
2266         ret = drm_gem_create_mmap_offset(&obj->base);
2267         if (ret != -ENOSPC)
2268                 goto out;
2269
2270         i915_gem_shrink_all(dev_priv);
2271         ret = drm_gem_create_mmap_offset(&obj->base);
2272 out:
2273         dev_priv->mm.shrinker_no_lock_stealing = false;
2274
2275         return ret;
2276 }
2277
2278 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
2279 {
2280         drm_gem_free_mmap_offset(&obj->base);
2281 }
2282
2283 int
2284 i915_gem_mmap_gtt(struct drm_file *file,
2285                   struct drm_device *dev,
2286                   uint32_t handle,
2287                   uint64_t *offset)
2288 {
2289         struct drm_i915_gem_object *obj;
2290         int ret;
2291
2292         ret = i915_mutex_lock_interruptible(dev);
2293         if (ret)
2294                 return ret;
2295
2296         obj = to_intel_bo(drm_gem_object_lookup(file, handle));
2297         if (&obj->base == NULL) {
2298                 ret = -ENOENT;
2299                 goto unlock;
2300         }
2301
2302         if (obj->madv != I915_MADV_WILLNEED) {
2303                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2304                 ret = -EFAULT;
2305                 goto out;
2306         }
2307
2308         ret = i915_gem_object_create_mmap_offset(obj);
2309         if (ret)
2310                 goto out;
2311
2312         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
2313
2314 out:
2315         drm_gem_object_unreference(&obj->base);
2316 unlock:
2317         mutex_unlock(&dev->struct_mutex);
2318         return ret;
2319 }
2320
2321 /**
2322  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2323  * @dev: DRM device
2324  * @data: GTT mapping ioctl data
2325  * @file: GEM object info
2326  *
2327  * Simply returns the fake offset to userspace so it can mmap it.
2328  * The mmap call will end up in drm_gem_mmap(), which will set things
2329  * up so we can get faults in the handler above.
2330  *
2331  * The fault handler will take care of binding the object into the GTT
2332  * (since it may have been evicted to make room for something), allocating
2333  * a fence register, and mapping the appropriate aperture address into
2334  * userspace.
2335  */
2336 int
2337 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2338                         struct drm_file *file)
2339 {
2340         struct drm_i915_gem_mmap_gtt *args = data;
2341
2342         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
2343 }
2344
2345 /* Immediately discard the backing storage */
2346 static void
2347 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
2348 {
2349         i915_gem_object_free_mmap_offset(obj);
2350
2351         if (obj->base.filp == NULL)
2352                 return;
2353
2354         /* Our goal here is to return as much of the memory as
2355          * is possible back to the system as we are called from OOM.
2356          * To do this we must instruct the shmfs to drop all of its
2357          * backing pages, *now*.
2358          */
2359         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
2360         obj->madv = __I915_MADV_PURGED;
2361 }
2362
2363 /* Try to discard unwanted pages */
2364 static void
2365 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
2366 {
2367         struct address_space *mapping;
2368
2369         switch (obj->madv) {
2370         case I915_MADV_DONTNEED:
2371                 i915_gem_object_truncate(obj);
2372         case __I915_MADV_PURGED:
2373                 return;
2374         }
2375
2376         if (obj->base.filp == NULL)
2377                 return;
2378
2379         mapping = file_inode(obj->base.filp)->i_mapping,
2380         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
2381 }
2382
2383 static void
2384 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
2385 {
2386         struct sgt_iter sgt_iter;
2387         struct page *page;
2388         int ret;
2389
2390         BUG_ON(obj->madv == __I915_MADV_PURGED);
2391
2392         ret = i915_gem_object_set_to_cpu_domain(obj, true);
2393         if (WARN_ON(ret)) {
2394                 /* In the event of a disaster, abandon all caches and
2395                  * hope for the best.
2396                  */
2397                 i915_gem_clflush_object(obj, true);
2398                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
2399         }
2400
2401         i915_gem_gtt_finish_object(obj);
2402
2403         if (i915_gem_object_needs_bit17_swizzle(obj))
2404                 i915_gem_object_save_bit_17_swizzle(obj);
2405
2406         if (obj->madv == I915_MADV_DONTNEED)
2407                 obj->dirty = 0;
2408
2409         for_each_sgt_page(page, sgt_iter, obj->pages) {
2410                 if (obj->dirty)
2411                         set_page_dirty(page);
2412
2413                 if (obj->madv == I915_MADV_WILLNEED)
2414                         mark_page_accessed(page);
2415
2416                 put_page(page);
2417         }
2418         obj->dirty = 0;
2419
2420         sg_free_table(obj->pages);
2421         kfree(obj->pages);
2422 }
2423
2424 int
2425 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
2426 {
2427         const struct drm_i915_gem_object_ops *ops = obj->ops;
2428
2429         if (obj->pages == NULL)
2430                 return 0;
2431
2432         if (obj->pages_pin_count)
2433                 return -EBUSY;
2434
2435         BUG_ON(i915_gem_obj_bound_any(obj));
2436
2437         /* ->put_pages might need to allocate memory for the bit17 swizzle
2438          * array, hence protect them from being reaped by removing them from gtt
2439          * lists early. */
2440         list_del(&obj->global_list);
2441
2442         if (obj->mapping) {
2443                 if (is_vmalloc_addr(obj->mapping))
2444                         vunmap(obj->mapping);
2445                 else
2446                         kunmap(kmap_to_page(obj->mapping));
2447                 obj->mapping = NULL;
2448         }
2449
2450         ops->put_pages(obj);
2451         obj->pages = NULL;
2452
2453         i915_gem_object_invalidate(obj);
2454
2455         return 0;
2456 }
2457
2458 static int
2459 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2460 {
2461         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2462         int page_count, i;
2463         struct address_space *mapping;
2464         struct sg_table *st;
2465         struct scatterlist *sg;
2466         struct sgt_iter sgt_iter;
2467         struct page *page;
2468         unsigned long last_pfn = 0;     /* suppress gcc warning */
2469         int ret;
2470         gfp_t gfp;
2471
2472         /* Assert that the object is not currently in any GPU domain. As it
2473          * wasn't in the GTT, there shouldn't be any way it could have been in
2474          * a GPU cache
2475          */
2476         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2477         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2478
2479         st = kmalloc(sizeof(*st), GFP_KERNEL);
2480         if (st == NULL)
2481                 return -ENOMEM;
2482
2483         page_count = obj->base.size / PAGE_SIZE;
2484         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2485                 kfree(st);
2486                 return -ENOMEM;
2487         }
2488
2489         /* Get the list of pages out of our struct file.  They'll be pinned
2490          * at this point until we release them.
2491          *
2492          * Fail silently without starting the shrinker
2493          */
2494         mapping = file_inode(obj->base.filp)->i_mapping;
2495         gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM));
2496         gfp |= __GFP_NORETRY | __GFP_NOWARN;
2497         sg = st->sgl;
2498         st->nents = 0;
2499         for (i = 0; i < page_count; i++) {
2500                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2501                 if (IS_ERR(page)) {
2502                         i915_gem_shrink(dev_priv,
2503                                         page_count,
2504                                         I915_SHRINK_BOUND |
2505                                         I915_SHRINK_UNBOUND |
2506                                         I915_SHRINK_PURGEABLE);
2507                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2508                 }
2509                 if (IS_ERR(page)) {
2510                         /* We've tried hard to allocate the memory by reaping
2511                          * our own buffer, now let the real VM do its job and
2512                          * go down in flames if truly OOM.
2513                          */
2514                         i915_gem_shrink_all(dev_priv);
2515                         page = shmem_read_mapping_page(mapping, i);
2516                         if (IS_ERR(page)) {
2517                                 ret = PTR_ERR(page);
2518                                 goto err_pages;
2519                         }
2520                 }
2521 #ifdef CONFIG_SWIOTLB
2522                 if (swiotlb_nr_tbl()) {
2523                         st->nents++;
2524                         sg_set_page(sg, page, PAGE_SIZE, 0);
2525                         sg = sg_next(sg);
2526                         continue;
2527                 }
2528 #endif
2529                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2530                         if (i)
2531                                 sg = sg_next(sg);
2532                         st->nents++;
2533                         sg_set_page(sg, page, PAGE_SIZE, 0);
2534                 } else {
2535                         sg->length += PAGE_SIZE;
2536                 }
2537                 last_pfn = page_to_pfn(page);
2538
2539                 /* Check that the i965g/gm workaround works. */
2540                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2541         }
2542 #ifdef CONFIG_SWIOTLB
2543         if (!swiotlb_nr_tbl())
2544 #endif
2545                 sg_mark_end(sg);
2546         obj->pages = st;
2547
2548         ret = i915_gem_gtt_prepare_object(obj);
2549         if (ret)
2550                 goto err_pages;
2551
2552         if (i915_gem_object_needs_bit17_swizzle(obj))
2553                 i915_gem_object_do_bit_17_swizzle(obj);
2554
2555         if (obj->tiling_mode != I915_TILING_NONE &&
2556             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2557                 i915_gem_object_pin_pages(obj);
2558
2559         return 0;
2560
2561 err_pages:
2562         sg_mark_end(sg);
2563         for_each_sgt_page(page, sgt_iter, st)
2564                 put_page(page);
2565         sg_free_table(st);
2566         kfree(st);
2567
2568         /* shmemfs first checks if there is enough memory to allocate the page
2569          * and reports ENOSPC should there be insufficient, along with the usual
2570          * ENOMEM for a genuine allocation failure.
2571          *
2572          * We use ENOSPC in our driver to mean that we have run out of aperture
2573          * space and so want to translate the error from shmemfs back to our
2574          * usual understanding of ENOMEM.
2575          */
2576         if (ret == -ENOSPC)
2577                 ret = -ENOMEM;
2578
2579         return ret;
2580 }
2581
2582 /* Ensure that the associated pages are gathered from the backing storage
2583  * and pinned into our object. i915_gem_object_get_pages() may be called
2584  * multiple times before they are released by a single call to
2585  * i915_gem_object_put_pages() - once the pages are no longer referenced
2586  * either as a result of memory pressure (reaping pages under the shrinker)
2587  * or as the object is itself released.
2588  */
2589 int
2590 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2591 {
2592         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2593         const struct drm_i915_gem_object_ops *ops = obj->ops;
2594         int ret;
2595
2596         if (obj->pages)
2597                 return 0;
2598
2599         if (obj->madv != I915_MADV_WILLNEED) {
2600                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2601                 return -EFAULT;
2602         }
2603
2604         BUG_ON(obj->pages_pin_count);
2605
2606         ret = ops->get_pages(obj);
2607         if (ret)
2608                 return ret;
2609
2610         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2611
2612         obj->get_page.sg = obj->pages->sgl;
2613         obj->get_page.last = 0;
2614
2615         return 0;
2616 }
2617
2618 /* The 'mapping' part of i915_gem_object_pin_map() below */
2619 static void *i915_gem_object_map(const struct drm_i915_gem_object *obj)
2620 {
2621         unsigned long n_pages = obj->base.size >> PAGE_SHIFT;
2622         struct sg_table *sgt = obj->pages;
2623         struct sgt_iter sgt_iter;
2624         struct page *page;
2625         struct page *stack_pages[32];
2626         struct page **pages = stack_pages;
2627         unsigned long i = 0;
2628         void *addr;
2629
2630         /* A single page can always be kmapped */
2631         if (n_pages == 1)
2632                 return kmap(sg_page(sgt->sgl));
2633
2634         if (n_pages > ARRAY_SIZE(stack_pages)) {
2635                 /* Too big for stack -- allocate temporary array instead */
2636                 pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY);
2637                 if (!pages)
2638                         return NULL;
2639         }
2640
2641         for_each_sgt_page(page, sgt_iter, sgt)
2642                 pages[i++] = page;
2643
2644         /* Check that we have the expected number of pages */
2645         GEM_BUG_ON(i != n_pages);
2646
2647         addr = vmap(pages, n_pages, 0, PAGE_KERNEL);
2648
2649         if (pages != stack_pages)
2650                 drm_free_large(pages);
2651
2652         return addr;
2653 }
2654
2655 /* get, pin, and map the pages of the object into kernel space */
2656 void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj)
2657 {
2658         int ret;
2659
2660         lockdep_assert_held(&obj->base.dev->struct_mutex);
2661
2662         ret = i915_gem_object_get_pages(obj);
2663         if (ret)
2664                 return ERR_PTR(ret);
2665
2666         i915_gem_object_pin_pages(obj);
2667
2668         if (!obj->mapping) {
2669                 obj->mapping = i915_gem_object_map(obj);
2670                 if (!obj->mapping) {
2671                         i915_gem_object_unpin_pages(obj);
2672                         return ERR_PTR(-ENOMEM);
2673                 }
2674         }
2675
2676         return obj->mapping;
2677 }
2678
2679 void i915_vma_move_to_active(struct i915_vma *vma,
2680                              struct drm_i915_gem_request *req)
2681 {
2682         struct drm_i915_gem_object *obj = vma->obj;
2683         struct intel_engine_cs *engine;
2684
2685         engine = i915_gem_request_get_engine(req);
2686
2687         /* Add a reference if we're newly entering the active list. */
2688         if (obj->active == 0)
2689                 drm_gem_object_reference(&obj->base);
2690         obj->active |= intel_engine_flag(engine);
2691
2692         list_move_tail(&obj->engine_list[engine->id], &engine->active_list);
2693         i915_gem_request_assign(&obj->last_read_req[engine->id], req);
2694
2695         list_move_tail(&vma->vm_link, &vma->vm->active_list);
2696 }
2697
2698 static void
2699 i915_gem_object_retire__write(struct drm_i915_gem_object *obj)
2700 {
2701         GEM_BUG_ON(obj->last_write_req == NULL);
2702         GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine)));
2703
2704         i915_gem_request_assign(&obj->last_write_req, NULL);
2705         intel_fb_obj_flush(obj, true, ORIGIN_CS);
2706 }
2707
2708 static void
2709 i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
2710 {
2711         struct i915_vma *vma;
2712
2713         GEM_BUG_ON(obj->last_read_req[ring] == NULL);
2714         GEM_BUG_ON(!(obj->active & (1 << ring)));
2715
2716         list_del_init(&obj->engine_list[ring]);
2717         i915_gem_request_assign(&obj->last_read_req[ring], NULL);
2718
2719         if (obj->last_write_req && obj->last_write_req->engine->id == ring)
2720                 i915_gem_object_retire__write(obj);
2721
2722         obj->active &= ~(1 << ring);
2723         if (obj->active)
2724                 return;
2725
2726         /* Bump our place on the bound list to keep it roughly in LRU order
2727          * so that we don't steal from recently used but inactive objects
2728          * (unless we are forced to ofc!)
2729          */
2730         list_move_tail(&obj->global_list,
2731                        &to_i915(obj->base.dev)->mm.bound_list);
2732
2733         list_for_each_entry(vma, &obj->vma_list, obj_link) {
2734                 if (!list_empty(&vma->vm_link))
2735                         list_move_tail(&vma->vm_link, &vma->vm->inactive_list);
2736         }
2737
2738         i915_gem_request_assign(&obj->last_fenced_req, NULL);
2739         drm_gem_object_unreference(&obj->base);
2740 }
2741
2742 static int
2743 i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno)
2744 {
2745         struct intel_engine_cs *engine;
2746         int ret;
2747
2748         /* Carefully retire all requests without writing to the rings */
2749         for_each_engine(engine, dev_priv) {
2750                 ret = intel_engine_idle(engine);
2751                 if (ret)
2752                         return ret;
2753         }
2754         i915_gem_retire_requests(dev_priv);
2755
2756         /* If the seqno wraps around, we need to clear the breadcrumb rbtree */
2757         if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) {
2758                 while (intel_kick_waiters(dev_priv))
2759                         yield();
2760         }
2761
2762         /* Finally reset hw state */
2763         for_each_engine(engine, dev_priv)
2764                 intel_ring_init_seqno(engine, seqno);
2765
2766         return 0;
2767 }
2768
2769 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2770 {
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         int ret;
2773
2774         if (seqno == 0)
2775                 return -EINVAL;
2776
2777         /* HWS page needs to be set less than what we
2778          * will inject to ring
2779          */
2780         ret = i915_gem_init_seqno(dev_priv, seqno - 1);
2781         if (ret)
2782                 return ret;
2783
2784         /* Carefully set the last_seqno value so that wrap
2785          * detection still works
2786          */
2787         dev_priv->next_seqno = seqno;
2788         dev_priv->last_seqno = seqno - 1;
2789         if (dev_priv->last_seqno == 0)
2790                 dev_priv->last_seqno--;
2791
2792         return 0;
2793 }
2794
2795 int
2796 i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno)
2797 {
2798         /* reserve 0 for non-seqno */
2799         if (dev_priv->next_seqno == 0) {
2800                 int ret = i915_gem_init_seqno(dev_priv, 0);
2801                 if (ret)
2802                         return ret;
2803
2804                 dev_priv->next_seqno = 1;
2805         }
2806
2807         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2808         return 0;
2809 }
2810
2811 /*
2812  * NB: This function is not allowed to fail. Doing so would mean the the
2813  * request is not being tracked for completion but the work itself is
2814  * going to happen on the hardware. This would be a Bad Thing(tm).
2815  */
2816 void __i915_add_request(struct drm_i915_gem_request *request,
2817                         struct drm_i915_gem_object *obj,
2818                         bool flush_caches)
2819 {
2820         struct intel_engine_cs *engine;
2821         struct drm_i915_private *dev_priv;
2822         struct intel_ringbuffer *ringbuf;
2823         u32 request_start;
2824         u32 reserved_tail;
2825         int ret;
2826
2827         if (WARN_ON(request == NULL))
2828                 return;
2829
2830         engine = request->engine;
2831         dev_priv = request->i915;
2832         ringbuf = request->ringbuf;
2833
2834         /*
2835          * To ensure that this call will not fail, space for its emissions
2836          * should already have been reserved in the ring buffer. Let the ring
2837          * know that it is time to use that space up.
2838          */
2839         request_start = intel_ring_get_tail(ringbuf);
2840         reserved_tail = request->reserved_space;
2841         request->reserved_space = 0;
2842
2843         /*
2844          * Emit any outstanding flushes - execbuf can fail to emit the flush
2845          * after having emitted the batchbuffer command. Hence we need to fix
2846          * things up similar to emitting the lazy request. The difference here
2847          * is that the flush _must_ happen before the next request, no matter
2848          * what.
2849          */
2850         if (flush_caches) {
2851                 if (i915.enable_execlists)
2852                         ret = logical_ring_flush_all_caches(request);
2853                 else
2854                         ret = intel_ring_flush_all_caches(request);
2855                 /* Not allowed to fail! */
2856                 WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret);
2857         }
2858
2859         trace_i915_gem_request_add(request);
2860
2861         request->head = request_start;
2862
2863         /* Whilst this request exists, batch_obj will be on the
2864          * active_list, and so will hold the active reference. Only when this
2865          * request is retired will the the batch_obj be moved onto the
2866          * inactive_list and lose its active reference. Hence we do not need
2867          * to explicitly hold another reference here.
2868          */
2869         request->batch_obj = obj;
2870
2871         /* Seal the request and mark it as pending execution. Note that
2872          * we may inspect this state, without holding any locks, during
2873          * hangcheck. Hence we apply the barrier to ensure that we do not
2874          * see a more recent value in the hws than we are tracking.
2875          */
2876         request->emitted_jiffies = jiffies;
2877         request->previous_seqno = engine->last_submitted_seqno;
2878         smp_store_mb(engine->last_submitted_seqno, request->seqno);
2879         list_add_tail(&request->list, &engine->request_list);
2880
2881         /* Record the position of the start of the request so that
2882          * should we detect the updated seqno part-way through the
2883          * GPU processing the request, we never over-estimate the
2884          * position of the head.
2885          */
2886         request->postfix = intel_ring_get_tail(ringbuf);
2887
2888         if (i915.enable_execlists)
2889                 ret = engine->emit_request(request);
2890         else {
2891                 ret = engine->add_request(request);
2892
2893                 request->tail = intel_ring_get_tail(ringbuf);
2894         }
2895         /* Not allowed to fail! */
2896         WARN(ret, "emit|add_request failed: %d!\n", ret);
2897
2898         queue_delayed_work(dev_priv->wq,
2899                            &dev_priv->mm.retire_work,
2900                            round_jiffies_up_relative(HZ));
2901         intel_mark_busy(dev_priv);
2902
2903         /* Sanity check that the reserved size was large enough. */
2904         ret = intel_ring_get_tail(ringbuf) - request_start;
2905         if (ret < 0)
2906                 ret += ringbuf->size;
2907         WARN_ONCE(ret > reserved_tail,
2908                   "Not enough space reserved (%d bytes) "
2909                   "for adding the request (%d bytes)\n",
2910                   reserved_tail, ret);
2911 }
2912
2913 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2914                                    const struct i915_gem_context *ctx)
2915 {
2916         unsigned long elapsed;
2917
2918         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2919
2920         if (ctx->hang_stats.banned)
2921                 return true;
2922
2923         if (ctx->hang_stats.ban_period_seconds &&
2924             elapsed <= ctx->hang_stats.ban_period_seconds) {
2925                 if (!i915_gem_context_is_default(ctx)) {
2926                         DRM_DEBUG("context hanging too fast, banning!\n");
2927                         return true;
2928                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2929                         if (i915_stop_ring_allow_warn(dev_priv))
2930                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2931                         return true;
2932                 }
2933         }
2934
2935         return false;
2936 }
2937
2938 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2939                                   struct i915_gem_context *ctx,
2940                                   const bool guilty)
2941 {
2942         struct i915_ctx_hang_stats *hs;
2943
2944         if (WARN_ON(!ctx))
2945                 return;
2946
2947         hs = &ctx->hang_stats;
2948
2949         if (guilty) {
2950                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2951                 hs->batch_active++;
2952                 hs->guilty_ts = get_seconds();
2953         } else {
2954                 hs->batch_pending++;
2955         }
2956 }
2957
2958 void i915_gem_request_free(struct kref *req_ref)
2959 {
2960         struct drm_i915_gem_request *req = container_of(req_ref,
2961                                                  typeof(*req), ref);
2962         kmem_cache_free(req->i915->requests, req);
2963 }
2964
2965 static inline int
2966 __i915_gem_request_alloc(struct intel_engine_cs *engine,
2967                          struct i915_gem_context *ctx,
2968                          struct drm_i915_gem_request **req_out)
2969 {
2970         struct drm_i915_private *dev_priv = engine->i915;
2971         unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
2972         struct drm_i915_gem_request *req;
2973         int ret;
2974
2975         if (!req_out)
2976                 return -EINVAL;
2977
2978         *req_out = NULL;
2979
2980         /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2981          * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2982          * and restart.
2983          */
2984         ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible);
2985         if (ret)
2986                 return ret;
2987
2988         req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL);
2989         if (req == NULL)
2990                 return -ENOMEM;
2991
2992         ret = i915_gem_get_seqno(engine->i915, &req->seqno);
2993         if (ret)
2994                 goto err;
2995
2996         kref_init(&req->ref);
2997         req->i915 = dev_priv;
2998         req->engine = engine;
2999         req->ctx  = ctx;
3000         i915_gem_context_reference(req->ctx);
3001
3002         /*
3003          * Reserve space in the ring buffer for all the commands required to
3004          * eventually emit this request. This is to guarantee that the
3005          * i915_add_request() call can't fail. Note that the reserve may need
3006          * to be redone if the request is not actually submitted straight
3007          * away, e.g. because a GPU scheduler has deferred it.
3008          */
3009         req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST;
3010
3011         if (i915.enable_execlists)
3012                 ret = intel_logical_ring_alloc_request_extras(req);
3013         else
3014                 ret = intel_ring_alloc_request_extras(req);
3015         if (ret)
3016                 goto err_ctx;
3017
3018         *req_out = req;
3019         return 0;
3020
3021 err_ctx:
3022         i915_gem_context_unreference(ctx);
3023 err:
3024         kmem_cache_free(dev_priv->requests, req);
3025         return ret;
3026 }
3027
3028 /**
3029  * i915_gem_request_alloc - allocate a request structure
3030  *
3031  * @engine: engine that we wish to issue the request on.
3032  * @ctx: context that the request will be associated with.
3033  *       This can be NULL if the request is not directly related to
3034  *       any specific user context, in which case this function will
3035  *       choose an appropriate context to use.
3036  *
3037  * Returns a pointer to the allocated request if successful,
3038  * or an error code if not.
3039  */
3040 struct drm_i915_gem_request *
3041 i915_gem_request_alloc(struct intel_engine_cs *engine,
3042                        struct i915_gem_context *ctx)
3043 {
3044         struct drm_i915_gem_request *req;
3045         int err;
3046
3047         if (ctx == NULL)
3048                 ctx = engine->i915->kernel_context;
3049         err = __i915_gem_request_alloc(engine, ctx, &req);
3050         return err ? ERR_PTR(err) : req;
3051 }
3052
3053 struct drm_i915_gem_request *
3054 i915_gem_find_active_request(struct intel_engine_cs *engine)
3055 {
3056         struct drm_i915_gem_request *request;
3057
3058         list_for_each_entry(request, &engine->request_list, list) {
3059                 if (i915_gem_request_completed(request, false))
3060                         continue;
3061
3062                 return request;
3063         }
3064
3065         return NULL;
3066 }
3067
3068 static void i915_gem_reset_engine_status(struct drm_i915_private *dev_priv,
3069                                        struct intel_engine_cs *engine)
3070 {
3071         struct drm_i915_gem_request *request;
3072         bool ring_hung;
3073
3074         request = i915_gem_find_active_request(engine);
3075
3076         if (request == NULL)
3077                 return;
3078
3079         ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
3080
3081         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
3082
3083         list_for_each_entry_continue(request, &engine->request_list, list)
3084                 i915_set_reset_status(dev_priv, request->ctx, false);
3085 }
3086
3087 static void i915_gem_reset_engine_cleanup(struct drm_i915_private *dev_priv,
3088                                         struct intel_engine_cs *engine)
3089 {
3090         struct intel_ringbuffer *buffer;
3091
3092         while (!list_empty(&engine->active_list)) {
3093                 struct drm_i915_gem_object *obj;
3094
3095                 obj = list_first_entry(&engine->active_list,
3096                                        struct drm_i915_gem_object,
3097                                        engine_list[engine->id]);
3098
3099                 i915_gem_object_retire__read(obj, engine->id);
3100         }
3101
3102         /*
3103          * Clear the execlists queue up before freeing the requests, as those
3104          * are the ones that keep the context and ringbuffer backing objects
3105          * pinned in place.
3106          */
3107
3108         if (i915.enable_execlists) {
3109                 /* Ensure irq handler finishes or is cancelled. */
3110                 tasklet_kill(&engine->irq_tasklet);
3111
3112                 intel_execlists_cancel_requests(engine);
3113         }
3114
3115         /*
3116          * We must free the requests after all the corresponding objects have
3117          * been moved off active lists. Which is the same order as the normal
3118          * retire_requests function does. This is important if object hold
3119          * implicit references on things like e.g. ppgtt address spaces through
3120          * the request.
3121          */
3122         while (!list_empty(&engine->request_list)) {
3123                 struct drm_i915_gem_request *request;
3124
3125                 request = list_first_entry(&engine->request_list,
3126                                            struct drm_i915_gem_request,
3127                                            list);
3128
3129                 i915_gem_request_retire(request);
3130         }
3131
3132         /* Having flushed all requests from all queues, we know that all
3133          * ringbuffers must now be empty. However, since we do not reclaim
3134          * all space when retiring the request (to prevent HEADs colliding
3135          * with rapid ringbuffer wraparound) the amount of available space
3136          * upon reset is less than when we start. Do one more pass over
3137          * all the ringbuffers to reset last_retired_head.
3138          */
3139         list_for_each_entry(buffer, &engine->buffers, link) {
3140                 buffer->last_retired_head = buffer->tail;
3141                 intel_ring_update_space(buffer);
3142         }
3143
3144         intel_ring_init_seqno(engine, engine->last_submitted_seqno);
3145 }
3146
3147 void i915_gem_reset(struct drm_device *dev)
3148 {
3149         struct drm_i915_private *dev_priv = dev->dev_private;
3150         struct intel_engine_cs *engine;
3151
3152         /*
3153          * Before we free the objects from the requests, we need to inspect
3154          * them for finding the guilty party. As the requests only borrow
3155          * their reference to the objects, the inspection must be done first.
3156          */
3157         for_each_engine(engine, dev_priv)
3158                 i915_gem_reset_engine_status(dev_priv, engine);
3159
3160         for_each_engine(engine, dev_priv)
3161                 i915_gem_reset_engine_cleanup(dev_priv, engine);
3162
3163         i915_gem_context_reset(dev);
3164
3165         i915_gem_restore_fences(dev);
3166
3167         WARN_ON(i915_verify_lists(dev));
3168 }
3169
3170 /**
3171  * This function clears the request list as sequence numbers are passed.
3172  * @engine: engine to retire requests on
3173  */
3174 void
3175 i915_gem_retire_requests_ring(struct intel_engine_cs *engine)
3176 {
3177         WARN_ON(i915_verify_lists(engine->dev));
3178
3179         /* Retire requests first as we use it above for the early return.
3180          * If we retire requests last, we may use a later seqno and so clear
3181          * the requests lists without clearing the active list, leading to
3182          * confusion.
3183          */
3184         while (!list_empty(&engine->request_list)) {
3185                 struct drm_i915_gem_request *request;
3186
3187                 request = list_first_entry(&engine->request_list,
3188                                            struct drm_i915_gem_request,
3189                                            list);
3190
3191                 if (!i915_gem_request_completed(request, true))
3192                         break;
3193
3194                 i915_gem_request_retire(request);
3195         }
3196
3197         /* Move any buffers on the active list that are no longer referenced
3198          * by the ringbuffer to the flushing/inactive lists as appropriate,
3199          * before we free the context associated with the requests.
3200          */
3201         while (!list_empty(&engine->active_list)) {
3202                 struct drm_i915_gem_object *obj;
3203
3204                 obj = list_first_entry(&engine->active_list,
3205                                        struct drm_i915_gem_object,
3206                                        engine_list[engine->id]);
3207
3208                 if (!list_empty(&obj->last_read_req[engine->id]->list))
3209                         break;
3210
3211                 i915_gem_object_retire__read(obj, engine->id);
3212         }
3213
3214         if (unlikely(engine->trace_irq_req &&
3215                      i915_gem_request_completed(engine->trace_irq_req, true))) {
3216                 engine->irq_put(engine);
3217                 i915_gem_request_assign(&engine->trace_irq_req, NULL);
3218         }
3219
3220         WARN_ON(i915_verify_lists(engine->dev));
3221 }
3222
3223 bool
3224 i915_gem_retire_requests(struct drm_i915_private *dev_priv)
3225 {
3226         struct intel_engine_cs *engine;
3227         bool idle = true;
3228
3229         for_each_engine(engine, dev_priv) {
3230                 i915_gem_retire_requests_ring(engine);
3231                 idle &= list_empty(&engine->request_list);
3232                 if (i915.enable_execlists) {
3233                         spin_lock_bh(&engine->execlist_lock);
3234                         idle &= list_empty(&engine->execlist_queue);
3235                         spin_unlock_bh(&engine->execlist_lock);
3236                 }
3237         }
3238
3239         if (idle)
3240                 mod_delayed_work(dev_priv->wq,
3241                                  &dev_priv->mm.idle_work,
3242                                  msecs_to_jiffies(100));
3243
3244         return idle;
3245 }
3246
3247 static void
3248 i915_gem_retire_work_handler(struct work_struct *work)
3249 {
3250         struct drm_i915_private *dev_priv =
3251                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
3252         struct drm_device *dev = dev_priv->dev;
3253         bool idle;
3254
3255         /* Come back later if the device is busy... */
3256         idle = false;
3257         if (mutex_trylock(&dev->struct_mutex)) {
3258                 idle = i915_gem_retire_requests(dev_priv);
3259                 mutex_unlock(&dev->struct_mutex);
3260         }
3261         if (!idle)
3262                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
3263                                    round_jiffies_up_relative(HZ));
3264 }
3265
3266 static void
3267 i915_gem_idle_work_handler(struct work_struct *work)
3268 {
3269         struct drm_i915_private *dev_priv =
3270                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
3271         struct drm_device *dev = dev_priv->dev;
3272         struct intel_engine_cs *engine;
3273
3274         for_each_engine(engine, dev_priv)
3275                 if (!list_empty(&engine->request_list))
3276                         return;
3277
3278         /* we probably should sync with hangcheck here, using cancel_work_sync.
3279          * Also locking seems to be fubar here, engine->request_list is protected
3280          * by dev->struct_mutex. */
3281
3282         intel_mark_idle(dev_priv);
3283
3284         if (mutex_trylock(&dev->struct_mutex)) {
3285                 for_each_engine(engine, dev_priv)
3286                         i915_gem_batch_pool_fini(&engine->batch_pool);
3287
3288                 mutex_unlock(&dev->struct_mutex);
3289         }
3290 }
3291
3292 /**
3293  * Ensures that an object will eventually get non-busy by flushing any required
3294  * write domains, emitting any outstanding lazy request and retiring and
3295  * completed requests.
3296  * @obj: object to flush
3297  */
3298 static int
3299 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
3300 {
3301         int i;
3302
3303         if (!obj->active)
3304                 return 0;
3305
3306         for (i = 0; i < I915_NUM_ENGINES; i++) {
3307                 struct drm_i915_gem_request *req;
3308
3309                 req = obj->last_read_req[i];
3310                 if (req == NULL)
3311                         continue;
3312
3313                 if (i915_gem_request_completed(req, true))
3314                         i915_gem_object_retire__read(obj, i);
3315         }
3316
3317         return 0;
3318 }
3319
3320 /**
3321  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3322  * @dev: drm device pointer
3323  * @data: ioctl data blob
3324  * @file: drm file pointer
3325  *
3326  * Returns 0 if successful, else an error is returned with the remaining time in
3327  * the timeout parameter.
3328  *  -ETIME: object is still busy after timeout
3329  *  -ERESTARTSYS: signal interrupted the wait
3330  *  -ENONENT: object doesn't exist
3331  * Also possible, but rare:
3332  *  -EAGAIN: GPU wedged
3333  *  -ENOMEM: damn
3334  *  -ENODEV: Internal IRQ fail
3335  *  -E?: The add request failed
3336  *
3337  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3338  * non-zero timeout parameter the wait ioctl will wait for the given number of
3339  * nanoseconds on an object becoming unbusy. Since the wait itself does so
3340  * without holding struct_mutex the object may become re-busied before this
3341  * function completes. A similar but shorter * race condition exists in the busy
3342  * ioctl
3343  */
3344 int
3345 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
3346 {
3347         struct drm_i915_gem_wait *args = data;
3348         struct drm_i915_gem_object *obj;
3349         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3350         int i, n = 0;
3351         int ret;
3352
3353         if (args->flags != 0)
3354                 return -EINVAL;
3355
3356         ret = i915_mutex_lock_interruptible(dev);
3357         if (ret)
3358                 return ret;
3359
3360         obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle));
3361         if (&obj->base == NULL) {
3362                 mutex_unlock(&dev->struct_mutex);
3363                 return -ENOENT;
3364         }
3365
3366         /* Need to make sure the object gets inactive eventually. */
3367         ret = i915_gem_object_flush_active(obj);
3368         if (ret)
3369                 goto out;
3370
3371         if (!obj->active)
3372                 goto out;
3373
3374         /* Do this after OLR check to make sure we make forward progress polling
3375          * on this IOCTL with a timeout == 0 (like busy ioctl)
3376          */
3377         if (args->timeout_ns == 0) {
3378                 ret = -ETIME;
3379                 goto out;
3380         }
3381
3382         drm_gem_object_unreference(&obj->base);
3383
3384         for (i = 0; i < I915_NUM_ENGINES; i++) {
3385                 if (obj->last_read_req[i] == NULL)
3386                         continue;
3387
3388                 req[n++] = i915_gem_request_reference(obj->last_read_req[i]);
3389         }
3390
3391         mutex_unlock(&dev->struct_mutex);
3392
3393         for (i = 0; i < n; i++) {
3394                 if (ret == 0)
3395                         ret = __i915_wait_request(req[i], true,
3396                                                   args->timeout_ns > 0 ? &args->timeout_ns : NULL,
3397                                                   to_rps_client(file));
3398                 i915_gem_request_unreference(req[i]);
3399         }
3400         return ret;
3401
3402 out:
3403         drm_gem_object_unreference(&obj->base);
3404         mutex_unlock(&dev->struct_mutex);
3405         return ret;
3406 }
3407
3408 static int
3409 __i915_gem_object_sync(struct drm_i915_gem_object *obj,
3410                        struct intel_engine_cs *to,
3411                        struct drm_i915_gem_request *from_req,
3412                        struct drm_i915_gem_request **to_req)
3413 {
3414         struct intel_engine_cs *from;
3415         int ret;
3416
3417         from = i915_gem_request_get_engine(from_req);
3418         if (to == from)
3419                 return 0;
3420
3421         if (i915_gem_request_completed(from_req, true))
3422                 return 0;
3423
3424         if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) {
3425                 struct drm_i915_private *i915 = to_i915(obj->base.dev);
3426                 ret = __i915_wait_request(from_req,
3427                                           i915->mm.interruptible,
3428                                           NULL,
3429                                           &i915->rps.semaphores);
3430                 if (ret)
3431                         return ret;
3432
3433                 i915_gem_object_retire_request(obj, from_req);
3434         } else {
3435                 int idx = intel_ring_sync_index(from, to);
3436                 u32 seqno = i915_gem_request_get_seqno(from_req);
3437
3438                 WARN_ON(!to_req);
3439
3440                 if (seqno <= from->semaphore.sync_seqno[idx])
3441                         return 0;
3442
3443                 if (*to_req == NULL) {
3444                         struct drm_i915_gem_request *req;
3445
3446                         req = i915_gem_request_alloc(to, NULL);
3447                         if (IS_ERR(req))
3448                                 return PTR_ERR(req);
3449
3450                         *to_req = req;
3451                 }
3452
3453                 trace_i915_gem_ring_sync_to(*to_req, from, from_req);
3454                 ret = to->semaphore.sync_to(*to_req, from, seqno);
3455                 if (ret)
3456                         return ret;
3457
3458                 /* We use last_read_req because sync_to()
3459                  * might have just caused seqno wrap under
3460                  * the radar.
3461                  */
3462                 from->semaphore.sync_seqno[idx] =
3463                         i915_gem_request_get_seqno(obj->last_read_req[from->id]);
3464         }
3465
3466         return 0;
3467 }
3468
3469 /**
3470  * i915_gem_object_sync - sync an object to a ring.
3471  *
3472  * @obj: object which may be in use on another ring.
3473  * @to: ring we wish to use the object on. May be NULL.
3474  * @to_req: request we wish to use the object for. See below.
3475  *          This will be allocated and returned if a request is
3476  *          required but not passed in.
3477  *
3478  * This code is meant to abstract object synchronization with the GPU.
3479  * Calling with NULL implies synchronizing the object with the CPU
3480  * rather than a particular GPU ring. Conceptually we serialise writes
3481  * between engines inside the GPU. We only allow one engine to write
3482  * into a buffer at any time, but multiple readers. To ensure each has
3483  * a coherent view of memory, we must:
3484  *
3485  * - If there is an outstanding write request to the object, the new
3486  *   request must wait for it to complete (either CPU or in hw, requests
3487  *   on the same ring will be naturally ordered).
3488  *
3489  * - If we are a write request (pending_write_domain is set), the new
3490  *   request must wait for outstanding read requests to complete.
3491  *
3492  * For CPU synchronisation (NULL to) no request is required. For syncing with
3493  * rings to_req must be non-NULL. However, a request does not have to be
3494  * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3495  * request will be allocated automatically and returned through *to_req. Note
3496  * that it is not guaranteed that commands will be emitted (because the system
3497  * might already be idle). Hence there is no need to create a request that
3498  * might never have any work submitted. Note further that if a request is
3499  * returned in *to_req, it is the responsibility of the caller to submit
3500  * that request (after potentially adding more work to it).
3501  *
3502  * Returns 0 if successful, else propagates up the lower layer error.
3503  */
3504 int
3505 i915_gem_object_sync(struct drm_i915_gem_object *obj,
3506                      struct intel_engine_cs *to,
3507                      struct drm_i915_gem_request **to_req)
3508 {
3509         const bool readonly = obj->base.pending_write_domain == 0;
3510         struct drm_i915_gem_request *req[I915_NUM_ENGINES];
3511         int ret, i, n;
3512
3513         if (!obj->active)
3514                 return 0;
3515
3516         if (to == NULL)
3517                 return i915_gem_object_wait_rendering(obj, readonly);
3518
3519         n = 0;
3520         if (readonly) {
3521                 if (obj->last_write_req)
3522                         req[n++] = obj->last_write_req;
3523         } else {
3524                 for (i = 0; i < I915_NUM_ENGINES; i++)
3525                         if (obj->last_read_req[i])
3526                                 req[n++] = obj->last_read_req[i];
3527         }
3528         for (i = 0; i < n; i++) {
3529                 ret = __i915_gem_object_sync(obj, to, req[i], to_req);
3530                 if (ret)
3531                         return ret;
3532         }
3533
3534         return 0;
3535 }
3536
3537 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
3538 {
3539         u32 old_write_domain, old_read_domains;
3540
3541         /* Force a pagefault for domain tracking on next user access */
3542         i915_gem_release_mmap(obj);
3543
3544         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3545                 return;
3546
3547         old_read_domains = obj->base.read_domains;
3548         old_write_domain = obj->base.write_domain;
3549
3550         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
3551         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
3552
3553         trace_i915_gem_object_change_domain(obj,
3554                                             old_read_domains,
3555                                             old_write_domain);
3556 }
3557
3558 static void __i915_vma_iounmap(struct i915_vma *vma)
3559 {
3560         GEM_BUG_ON(vma->pin_count);
3561
3562         if (vma->iomap == NULL)
3563                 return;
3564
3565         io_mapping_unmap(vma->iomap);
3566         vma->iomap = NULL;
3567 }
3568
3569 static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
3570 {
3571         struct drm_i915_gem_object *obj = vma->obj;
3572         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3573         int ret;
3574
3575         if (list_empty(&vma->obj_link))
3576                 return 0;
3577
3578         if (!drm_mm_node_allocated(&vma->node)) {
3579                 i915_gem_vma_destroy(vma);
3580                 return 0;
3581         }
3582
3583         if (vma->pin_count)
3584                 return -EBUSY;
3585
3586         BUG_ON(obj->pages == NULL);
3587
3588         if (wait) {
3589                 ret = i915_gem_object_wait_rendering(obj, false);
3590                 if (ret)
3591                         return ret;
3592         }
3593
3594         if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3595                 i915_gem_object_finish_gtt(obj);
3596
3597                 /* release the fence reg _after_ flushing */
3598                 ret = i915_gem_object_put_fence(obj);
3599                 if (ret)
3600                         return ret;
3601
3602                 __i915_vma_iounmap(vma);
3603         }
3604
3605         trace_i915_vma_unbind(vma);
3606
3607         vma->vm->unbind_vma(vma);
3608         vma->bound = 0;
3609
3610         list_del_init(&vma->vm_link);
3611         if (vma->is_ggtt) {
3612                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) {
3613                         obj->map_and_fenceable = false;
3614                 } else if (vma->ggtt_view.pages) {
3615                         sg_free_table(vma->ggtt_view.pages);
3616                         kfree(vma->ggtt_view.pages);
3617                 }
3618                 vma->ggtt_view.pages = NULL;
3619         }
3620
3621         drm_mm_remove_node(&vma->node);
3622         i915_gem_vma_destroy(vma);
3623
3624         /* Since the unbound list is global, only move to that list if
3625          * no more VMAs exist. */
3626         if (list_empty(&obj->vma_list))
3627                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
3628
3629         /* And finally now the object is completely decoupled from this vma,
3630          * we can drop its hold on the backing storage and allow it to be
3631          * reaped by the shrinker.
3632          */
3633         i915_gem_object_unpin_pages(obj);
3634
3635         return 0;
3636 }
3637
3638 int i915_vma_unbind(struct i915_vma *vma)
3639 {
3640         return __i915_vma_unbind(vma, true);
3641 }
3642
3643 int __i915_vma_unbind_no_wait(struct i915_vma *vma)
3644 {
3645         return __i915_vma_unbind(vma, false);
3646 }
3647
3648 int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv)
3649 {
3650         struct intel_engine_cs *engine;
3651         int ret;
3652
3653         lockdep_assert_held(&dev_priv->dev->struct_mutex);
3654
3655         for_each_engine(engine, dev_priv) {
3656                 if (engine->last_context == NULL)
3657                         continue;
3658
3659                 ret = intel_engine_idle(engine);
3660                 if (ret)
3661                         return ret;
3662         }
3663
3664         WARN_ON(i915_verify_lists(dev));
3665         return 0;
3666 }
3667
3668 static bool i915_gem_valid_gtt_space(struct i915_vma *vma,
3669                                      unsigned long cache_level)
3670 {
3671         struct drm_mm_node *gtt_space = &vma->node;
3672         struct drm_mm_node *other;
3673
3674         /*
3675          * On some machines we have to be careful when putting differing types
3676          * of snoopable memory together to avoid the prefetcher crossing memory
3677          * domains and dying. During vm initialisation, we decide whether or not
3678          * these constraints apply and set the drm_mm.color_adjust
3679          * appropriately.
3680          */
3681         if (vma->vm->mm.color_adjust == NULL)
3682                 return true;
3683
3684         if (!drm_mm_node_allocated(gtt_space))
3685                 return true;
3686
3687         if (list_empty(&gtt_space->node_list))
3688                 return true;
3689
3690         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3691         if (other->allocated && !other->hole_follows && other->color != cache_level)
3692                 return false;
3693
3694         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3695         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3696                 return false;
3697
3698         return true;
3699 }
3700
3701 /**
3702  * Finds free space in the GTT aperture and binds the object or a view of it
3703  * there.
3704  * @obj: object to bind
3705  * @vm: address space to bind into
3706  * @ggtt_view: global gtt view if applicable
3707  * @alignment: requested alignment
3708  * @flags: mask of PIN_* flags to use
3709  */
3710 static struct i915_vma *
3711 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3712                            struct i915_address_space *vm,
3713                            const struct i915_ggtt_view *ggtt_view,
3714                            unsigned alignment,
3715                            uint64_t flags)
3716 {
3717         struct drm_device *dev = obj->base.dev;
3718         struct drm_i915_private *dev_priv = to_i915(dev);
3719         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3720         u32 fence_alignment, unfenced_alignment;
3721         u32 search_flag, alloc_flag;
3722         u64 start, end;
3723         u64 size, fence_size;
3724         struct i915_vma *vma;
3725         int ret;
3726
3727         if (i915_is_ggtt(vm)) {
3728                 u32 view_size;
3729
3730                 if (WARN_ON(!ggtt_view))
3731                         return ERR_PTR(-EINVAL);
3732
3733                 view_size = i915_ggtt_view_size(obj, ggtt_view);
3734
3735                 fence_size = i915_gem_get_gtt_size(dev,
3736                                                    view_size,
3737                                                    obj->tiling_mode);
3738                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3739                                                              view_size,
3740                                                              obj->tiling_mode,
3741                                                              true);
3742                 unfenced_alignment = i915_gem_get_gtt_alignment(dev,
3743                                                                 view_size,
3744                                                                 obj->tiling_mode,
3745                                                                 false);
3746                 size = flags & PIN_MAPPABLE ? fence_size : view_size;
3747         } else {
3748                 fence_size = i915_gem_get_gtt_size(dev,
3749                                                    obj->base.size,
3750                                                    obj->tiling_mode);
3751                 fence_alignment = i915_gem_get_gtt_alignment(dev,
3752                                                              obj->base.size,
3753                                                              obj->tiling_mode,
3754                                                              true);
3755                 unfenced_alignment =
3756                         i915_gem_get_gtt_alignment(dev,
3757                                                    obj->base.size,
3758                                                    obj->tiling_mode,
3759                                                    false);
3760                 size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3761         }
3762
3763         start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3764         end = vm->total;
3765         if (flags & PIN_MAPPABLE)
3766                 end = min_t(u64, end, ggtt->mappable_end);
3767         if (flags & PIN_ZONE_4G)
3768                 end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE);
3769
3770         if (alignment == 0)
3771                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3772                                                 unfenced_alignment;
3773         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3774                 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3775                           ggtt_view ? ggtt_view->type : 0,
3776                           alignment);
3777                 return ERR_PTR(-EINVAL);
3778         }
3779
3780         /* If binding the object/GGTT view requires more space than the entire
3781          * aperture has, reject it early before evicting everything in a vain
3782          * attempt to find space.
3783          */
3784         if (size > end) {
3785                 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3786                           ggtt_view ? ggtt_view->type : 0,
3787                           size,
3788                           flags & PIN_MAPPABLE ? "mappable" : "total",
3789                           end);
3790                 return ERR_PTR(-E2BIG);
3791         }
3792
3793         ret = i915_gem_object_get_pages(obj);
3794         if (ret)
3795                 return ERR_PTR(ret);
3796
3797         i915_gem_object_pin_pages(obj);
3798
3799         vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) :
3800                           i915_gem_obj_lookup_or_create_vma(obj, vm);
3801
3802         if (IS_ERR(vma))
3803                 goto err_unpin;
3804
3805         if (flags & PIN_OFFSET_FIXED) {
3806                 uint64_t offset = flags & PIN_OFFSET_MASK;
3807
3808                 if (offset & (alignment - 1) || offset + size > end) {
3809                         ret = -EINVAL;
3810                         goto err_free_vma;
3811                 }
3812                 vma->node.start = offset;
3813                 vma->node.size = size;
3814                 vma->node.color = obj->cache_level;
3815                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3816                 if (ret) {
3817                         ret = i915_gem_evict_for_vma(vma);
3818                         if (ret == 0)
3819                                 ret = drm_mm_reserve_node(&vm->mm, &vma->node);
3820                 }
3821                 if (ret)
3822                         goto err_free_vma;
3823         } else {
3824                 if (flags & PIN_HIGH) {
3825                         search_flag = DRM_MM_SEARCH_BELOW;
3826                         alloc_flag = DRM_MM_CREATE_TOP;
3827                 } else {
3828                         search_flag = DRM_MM_SEARCH_DEFAULT;
3829                         alloc_flag = DRM_MM_CREATE_DEFAULT;
3830                 }
3831
3832 search_free:
3833                 ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3834                                                           size, alignment,
3835                                                           obj->cache_level,
3836                                                           start, end,
3837                                                           search_flag,
3838                                                           alloc_flag);
3839                 if (ret) {
3840                         ret = i915_gem_evict_something(dev, vm, size, alignment,
3841                                                        obj->cache_level,
3842                                                        start, end,
3843                                                        flags);
3844                         if (ret == 0)
3845                                 goto search_free;
3846
3847                         goto err_free_vma;
3848                 }
3849         }
3850         if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) {
3851                 ret = -EINVAL;
3852                 goto err_remove_node;
3853         }
3854
3855         trace_i915_vma_bind(vma, flags);
3856         ret = i915_vma_bind(vma, obj->cache_level, flags);
3857         if (ret)
3858                 goto err_remove_node;
3859
3860         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3861         list_add_tail(&vma->vm_link, &vm->inactive_list);
3862
3863         return vma;
3864
3865 err_remove_node:
3866         drm_mm_remove_node(&vma->node);
3867 err_free_vma:
3868         i915_gem_vma_destroy(vma);
3869         vma = ERR_PTR(ret);
3870 err_unpin:
3871         i915_gem_object_unpin_pages(obj);
3872         return vma;
3873 }
3874
3875 bool
3876 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3877                         bool force)
3878 {
3879         /* If we don't have a page list set up, then we're not pinned
3880          * to GPU, and we can ignore the cache flush because it'll happen
3881          * again at bind time.
3882          */
3883         if (obj->pages == NULL)
3884                 return false;
3885
3886         /*
3887          * Stolen memory is always coherent with the GPU as it is explicitly
3888          * marked as wc by the system, or the system is cache-coherent.
3889          */
3890         if (obj->stolen || obj->phys_handle)
3891                 return false;
3892
3893         /* If the GPU is snooping the contents of the CPU cache,
3894          * we do not need to manually clear the CPU cache lines.  However,
3895          * the caches are only snooped when the render cache is
3896          * flushed/invalidated.  As we always have to emit invalidations
3897          * and flushes when moving into and out of the RENDER domain, correct
3898          * snooping behaviour occurs naturally as the result of our domain
3899          * tracking.
3900          */
3901         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) {
3902                 obj->cache_dirty = true;
3903                 return false;
3904         }
3905
3906         trace_i915_gem_object_clflush(obj);
3907         drm_clflush_sg(obj->pages);
3908         obj->cache_dirty = false;
3909
3910         return true;
3911 }
3912
3913 /** Flushes the GTT write domain for the object if it's dirty. */
3914 static void
3915 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3916 {
3917         uint32_t old_write_domain;
3918
3919         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3920                 return;
3921
3922         /* No actual flushing is required for the GTT write domain.  Writes
3923          * to it immediately go to main memory as far as we know, so there's
3924          * no chipset flush.  It also doesn't land in render cache.
3925          *
3926          * However, we do have to enforce the order so that all writes through
3927          * the GTT land before any writes to the device, such as updates to
3928          * the GATT itself.
3929          */
3930         wmb();
3931
3932         old_write_domain = obj->base.write_domain;
3933         obj->base.write_domain = 0;
3934
3935         intel_fb_obj_flush(obj, false, ORIGIN_GTT);
3936
3937         trace_i915_gem_object_change_domain(obj,
3938                                             obj->base.read_domains,
3939                                             old_write_domain);
3940 }
3941
3942 /** Flushes the CPU write domain for the object if it's dirty. */
3943 static void
3944 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
3945 {
3946         uint32_t old_write_domain;
3947
3948         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3949                 return;
3950
3951         if (i915_gem_clflush_object(obj, obj->pin_display))
3952                 i915_gem_chipset_flush(to_i915(obj->base.dev));
3953
3954         old_write_domain = obj->base.write_domain;
3955         obj->base.write_domain = 0;
3956
3957         intel_fb_obj_flush(obj, false, ORIGIN_CPU);
3958
3959         trace_i915_gem_object_change_domain(obj,
3960                                             obj->base.read_domains,
3961                                             old_write_domain);
3962 }
3963
3964 /**
3965  * Moves a single object to the GTT read, and possibly write domain.
3966  * @obj: object to act on
3967  * @write: ask for write access or read only
3968  *
3969  * This function returns when the move is complete, including waiting on
3970  * flushes to occur.
3971  */
3972 int
3973 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3974 {
3975         struct drm_device *dev = obj->base.dev;
3976         struct drm_i915_private *dev_priv = to_i915(dev);
3977         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3978         uint32_t old_write_domain, old_read_domains;
3979         struct i915_vma *vma;
3980         int ret;
3981
3982         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3983                 return 0;
3984
3985         ret = i915_gem_object_wait_rendering(obj, !write);
3986         if (ret)
3987                 return ret;
3988
3989         /* Flush and acquire obj->pages so that we are coherent through
3990          * direct access in memory with previous cached writes through
3991          * shmemfs and that our cache domain tracking remains valid.
3992          * For example, if the obj->filp was moved to swap without us
3993          * being notified and releasing the pages, we would mistakenly
3994          * continue to assume that the obj remained out of the CPU cached
3995          * domain.
3996          */
3997         ret = i915_gem_object_get_pages(obj);
3998         if (ret)
3999                 return ret;
4000
4001         i915_gem_object_flush_cpu_write_domain(obj);
4002
4003         /* Serialise direct access to this object with the barriers for
4004          * coherent writes from the GPU, by effectively invalidating the
4005          * GTT domain upon first access.
4006          */
4007         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
4008                 mb();
4009
4010         old_write_domain = obj->base.write_domain;
4011         old_read_domains = obj->base.read_domains;
4012
4013         /* It should now be out of any other write domains, and we can update
4014          * the domain values for our changes.
4015          */
4016         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
4017         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4018         if (write) {
4019                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
4020                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
4021                 obj->dirty = 1;
4022         }
4023
4024         trace_i915_gem_object_change_domain(obj,
4025                                             old_read_domains,
4026                                             old_write_domain);
4027
4028         /* And bump the LRU for this access */
4029         vma = i915_gem_obj_to_ggtt(obj);
4030         if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
4031                 list_move_tail(&vma->vm_link,
4032                                &ggtt->base.inactive_list);
4033
4034         return 0;
4035 }
4036
4037 /**
4038  * Changes the cache-level of an object across all VMA.
4039  * @obj: object to act on
4040  * @cache_level: new cache level to set for the object
4041  *
4042  * After this function returns, the object will be in the new cache-level
4043  * across all GTT and the contents of the backing storage will be coherent,
4044  * with respect to the new cache-level. In order to keep the backing storage
4045  * coherent for all users, we only allow a single cache level to be set
4046  * globally on the object and prevent it from being changed whilst the
4047  * hardware is reading from the object. That is if the object is currently
4048  * on the scanout it will be set to uncached (or equivalent display
4049  * cache coherency) and all non-MOCS GPU access will also be uncached so
4050  * that all direct access to the scanout remains coherent.
4051  */
4052 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
4053                                     enum i915_cache_level cache_level)
4054 {
4055         struct drm_device *dev = obj->base.dev;
4056         struct i915_vma *vma, *next;
4057         bool bound = false;
4058         int ret = 0;
4059
4060         if (obj->cache_level == cache_level)
4061                 goto out;
4062
4063         /* Inspect the list of currently bound VMA and unbind any that would
4064          * be invalid given the new cache-level. This is principally to
4065          * catch the issue of the CS prefetch crossing page boundaries and
4066          * reading an invalid PTE on older architectures.
4067          */
4068         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4069                 if (!drm_mm_node_allocated(&vma->node))
4070                         continue;
4071
4072                 if (vma->pin_count) {
4073                         DRM_DEBUG("can not change the cache level of pinned objects\n");
4074                         return -EBUSY;
4075                 }
4076
4077                 if (!i915_gem_valid_gtt_space(vma, cache_level)) {
4078                         ret = i915_vma_unbind(vma);
4079                         if (ret)
4080                                 return ret;
4081                 } else
4082                         bound = true;
4083         }
4084
4085         /* We can reuse the existing drm_mm nodes but need to change the
4086          * cache-level on the PTE. We could simply unbind them all and
4087          * rebind with the correct cache-level on next use. However since
4088          * we already have a valid slot, dma mapping, pages etc, we may as
4089          * rewrite the PTE in the belief that doing so tramples upon less
4090          * state and so involves less work.
4091          */
4092         if (bound) {
4093                 /* Before we change the PTE, the GPU must not be accessing it.
4094                  * If we wait upon the object, we know that all the bound
4095                  * VMA are no longer active.
4096                  */
4097                 ret = i915_gem_object_wait_rendering(obj, false);
4098                 if (ret)
4099                         return ret;
4100
4101                 if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
4102                         /* Access to snoopable pages through the GTT is
4103                          * incoherent and on some machines causes a hard
4104                          * lockup. Relinquish the CPU mmaping to force
4105                          * userspace to refault in the pages and we can
4106                          * then double check if the GTT mapping is still
4107                          * valid for that pointer access.
4108                          */
4109                         i915_gem_release_mmap(obj);
4110
4111                         /* As we no longer need a fence for GTT access,
4112                          * we can relinquish it now (and so prevent having
4113                          * to steal a fence from someone else on the next
4114                          * fence request). Note GPU activity would have
4115                          * dropped the fence as all snoopable access is
4116                          * supposed to be linear.
4117                          */
4118                         ret = i915_gem_object_put_fence(obj);
4119                         if (ret)
4120                                 return ret;
4121                 } else {
4122                         /* We either have incoherent backing store and
4123                          * so no GTT access or the architecture is fully
4124                          * coherent. In such cases, existing GTT mmaps
4125                          * ignore the cache bit in the PTE and we can
4126                          * rewrite it without confusing the GPU or having
4127                          * to force userspace to fault back in its mmaps.
4128                          */
4129                 }
4130
4131                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
4132                         if (!drm_mm_node_allocated(&vma->node))
4133                                 continue;
4134
4135                         ret = i915_vma_bind(vma, cache_level, PIN_UPDATE);
4136                         if (ret)
4137                                 return ret;
4138                 }
4139         }
4140
4141         list_for_each_entry(vma, &obj->vma_list, obj_link)
4142                 vma->node.color = cache_level;
4143         obj->cache_level = cache_level;
4144
4145 out:
4146         /* Flush the dirty CPU caches to the backing storage so that the
4147          * object is now coherent at its new cache level (with respect
4148          * to the access domain).
4149          */
4150         if (obj->cache_dirty && cpu_write_needs_clflush(obj)) {
4151                 if (i915_gem_clflush_object(obj, true))
4152                         i915_gem_chipset_flush(to_i915(obj->base.dev));
4153         }
4154
4155         return 0;
4156 }
4157
4158 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
4159                                struct drm_file *file)
4160 {
4161         struct drm_i915_gem_caching *args = data;
4162         struct drm_i915_gem_object *obj;
4163
4164         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4165         if (&obj->base == NULL)
4166                 return -ENOENT;
4167
4168         switch (obj->cache_level) {
4169         case I915_CACHE_LLC:
4170         case I915_CACHE_L3_LLC:
4171                 args->caching = I915_CACHING_CACHED;
4172                 break;
4173
4174         case I915_CACHE_WT:
4175                 args->caching = I915_CACHING_DISPLAY;
4176                 break;
4177
4178         default:
4179                 args->caching = I915_CACHING_NONE;
4180                 break;
4181         }
4182
4183         drm_gem_object_unreference_unlocked(&obj->base);
4184         return 0;
4185 }
4186
4187 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
4188                                struct drm_file *file)
4189 {
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         struct drm_i915_gem_caching *args = data;
4192         struct drm_i915_gem_object *obj;
4193         enum i915_cache_level level;
4194         int ret;
4195
4196         switch (args->caching) {
4197         case I915_CACHING_NONE:
4198                 level = I915_CACHE_NONE;
4199                 break;
4200         case I915_CACHING_CACHED:
4201                 /*
4202                  * Due to a HW issue on BXT A stepping, GPU stores via a
4203                  * snooped mapping may leave stale data in a corresponding CPU
4204                  * cacheline, whereas normally such cachelines would get
4205                  * invalidated.
4206                  */
4207                 if (!HAS_LLC(dev) && !HAS_SNOOP(dev))
4208                         return -ENODEV;
4209
4210                 level = I915_CACHE_LLC;
4211                 break;
4212         case I915_CACHING_DISPLAY:
4213                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
4214                 break;
4215         default:
4216                 return -EINVAL;
4217         }
4218
4219         intel_runtime_pm_get(dev_priv);
4220
4221         ret = i915_mutex_lock_interruptible(dev);
4222         if (ret)
4223                 goto rpm_put;
4224
4225         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4226         if (&obj->base == NULL) {
4227                 ret = -ENOENT;
4228                 goto unlock;
4229         }
4230
4231         ret = i915_gem_object_set_cache_level(obj, level);
4232
4233         drm_gem_object_unreference(&obj->base);
4234 unlock:
4235         mutex_unlock(&dev->struct_mutex);
4236 rpm_put:
4237         intel_runtime_pm_put(dev_priv);
4238
4239         return ret;
4240 }
4241
4242 /*
4243  * Prepare buffer for display plane (scanout, cursors, etc).
4244  * Can be called from an uninterruptible phase (modesetting) and allows
4245  * any flushes to be pipelined (for pageflips).
4246  */
4247 int
4248 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
4249                                      u32 alignment,
4250                                      const struct i915_ggtt_view *view)
4251 {
4252         u32 old_read_domains, old_write_domain;
4253         int ret;
4254
4255         /* Mark the pin_display early so that we account for the
4256          * display coherency whilst setting up the cache domains.
4257          */
4258         obj->pin_display++;
4259
4260         /* The display engine is not coherent with the LLC cache on gen6.  As
4261          * a result, we make sure that the pinning that is about to occur is
4262          * done with uncached PTEs. This is lowest common denominator for all
4263          * chipsets.
4264          *
4265          * However for gen6+, we could do better by using the GFDT bit instead
4266          * of uncaching, which would allow us to flush all the LLC-cached data
4267          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4268          */
4269         ret = i915_gem_object_set_cache_level(obj,
4270                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
4271         if (ret)
4272                 goto err_unpin_display;
4273
4274         /* As the user may map the buffer once pinned in the display plane
4275          * (e.g. libkms for the bootup splash), we have to ensure that we
4276          * always use map_and_fenceable for all scanout buffers.
4277          */
4278         ret = i915_gem_object_ggtt_pin(obj, view, alignment,
4279                                        view->type == I915_GGTT_VIEW_NORMAL ?
4280                                        PIN_MAPPABLE : 0);
4281         if (ret)
4282                 goto err_unpin_display;
4283
4284         i915_gem_object_flush_cpu_write_domain(obj);
4285
4286         old_write_domain = obj->base.write_domain;
4287         old_read_domains = obj->base.read_domains;
4288
4289         /* It should now be out of any other write domains, and we can update
4290          * the domain values for our changes.
4291          */
4292         obj->base.write_domain = 0;
4293         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
4294
4295         trace_i915_gem_object_change_domain(obj,
4296                                             old_read_domains,
4297                                             old_write_domain);
4298
4299         return 0;
4300
4301 err_unpin_display:
4302         obj->pin_display--;
4303         return ret;
4304 }
4305
4306 void
4307 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
4308                                          const struct i915_ggtt_view *view)
4309 {
4310         if (WARN_ON(obj->pin_display == 0))
4311                 return;
4312
4313         i915_gem_object_ggtt_unpin_view(obj, view);
4314
4315         obj->pin_display--;
4316 }
4317
4318 /**
4319  * Moves a single object to the CPU read, and possibly write domain.
4320  * @obj: object to act on
4321  * @write: requesting write or read-only access
4322  *
4323  * This function returns when the move is complete, including waiting on
4324  * flushes to occur.
4325  */
4326 int
4327 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
4328 {
4329         uint32_t old_write_domain, old_read_domains;
4330         int ret;
4331
4332         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
4333                 return 0;
4334
4335         ret = i915_gem_object_wait_rendering(obj, !write);
4336         if (ret)
4337                 return ret;
4338
4339         i915_gem_object_flush_gtt_write_domain(obj);
4340
4341         old_write_domain = obj->base.write_domain;
4342         old_read_domains = obj->base.read_domains;
4343
4344         /* Flush the CPU cache if it's still invalid. */
4345         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
4346                 i915_gem_clflush_object(obj, false);
4347
4348                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
4349         }
4350
4351         /* It should now be out of any other write domains, and we can update
4352          * the domain values for our changes.
4353          */
4354         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
4355
4356         /* If we're writing through the CPU, then the GPU read domains will
4357          * need to be invalidated at next use.
4358          */
4359         if (write) {
4360                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4361                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4362         }
4363
4364         trace_i915_gem_object_change_domain(obj,
4365                                             old_read_domains,
4366                                             old_write_domain);
4367
4368         return 0;
4369 }
4370
4371 /* Throttle our rendering by waiting until the ring has completed our requests
4372  * emitted over 20 msec ago.
4373  *
4374  * Note that if we were to use the current jiffies each time around the loop,
4375  * we wouldn't escape the function with any frames outstanding if the time to
4376  * render a frame was over 20ms.
4377  *
4378  * This should get us reasonable parallelism between CPU and GPU but also
4379  * relatively low latency when blocking on a particular request to finish.
4380  */
4381 static int
4382 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4383 {
4384         struct drm_i915_private *dev_priv = dev->dev_private;
4385         struct drm_i915_file_private *file_priv = file->driver_priv;
4386         unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES;
4387         struct drm_i915_gem_request *request, *target = NULL;
4388         int ret;
4389
4390         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4391         if (ret)
4392                 return ret;
4393
4394         /* ABI: return -EIO if already wedged */
4395         if (i915_terminally_wedged(&dev_priv->gpu_error))
4396                 return -EIO;
4397
4398         spin_lock(&file_priv->mm.lock);
4399         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4400                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4401                         break;
4402
4403                 /*
4404                  * Note that the request might not have been submitted yet.
4405                  * In which case emitted_jiffies will be zero.
4406                  */
4407                 if (!request->emitted_jiffies)
4408                         continue;
4409
4410                 target = request;
4411         }
4412         if (target)
4413                 i915_gem_request_reference(target);
4414         spin_unlock(&file_priv->mm.lock);
4415
4416         if (target == NULL)
4417                 return 0;
4418
4419         ret = __i915_wait_request(target, true, NULL, NULL);
4420         if (ret == 0)
4421                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4422
4423         i915_gem_request_unreference(target);
4424
4425         return ret;
4426 }
4427
4428 static bool
4429 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4430 {
4431         struct drm_i915_gem_object *obj = vma->obj;
4432
4433         if (alignment &&
4434             vma->node.start & (alignment - 1))
4435                 return true;
4436
4437         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4438                 return true;
4439
4440         if (flags & PIN_OFFSET_BIAS &&
4441             vma->node.start < (flags & PIN_OFFSET_MASK))
4442                 return true;
4443
4444         if (flags & PIN_OFFSET_FIXED &&
4445             vma->node.start != (flags & PIN_OFFSET_MASK))
4446                 return true;
4447
4448         return false;
4449 }
4450
4451 void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
4452 {
4453         struct drm_i915_gem_object *obj = vma->obj;
4454         bool mappable, fenceable;
4455         u32 fence_size, fence_alignment;
4456
4457         fence_size = i915_gem_get_gtt_size(obj->base.dev,
4458                                            obj->base.size,
4459                                            obj->tiling_mode);
4460         fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev,
4461                                                      obj->base.size,
4462                                                      obj->tiling_mode,
4463                                                      true);
4464
4465         fenceable = (vma->node.size == fence_size &&
4466                      (vma->node.start & (fence_alignment - 1)) == 0);
4467
4468         mappable = (vma->node.start + fence_size <=
4469                     to_i915(obj->base.dev)->ggtt.mappable_end);
4470
4471         obj->map_and_fenceable = mappable && fenceable;
4472 }
4473
4474 static int
4475 i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
4476                        struct i915_address_space *vm,
4477                        const struct i915_ggtt_view *ggtt_view,
4478                        uint32_t alignment,
4479                        uint64_t flags)
4480 {
4481         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4482         struct i915_vma *vma;
4483         unsigned bound;
4484         int ret;
4485
4486         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4487                 return -ENODEV;
4488
4489         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4490                 return -EINVAL;
4491
4492         if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE))
4493                 return -EINVAL;
4494
4495         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
4496                 return -EINVAL;
4497
4498         vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) :
4499                           i915_gem_obj_to_vma(obj, vm);
4500
4501         if (vma) {
4502                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4503                         return -EBUSY;
4504
4505                 if (i915_vma_misplaced(vma, alignment, flags)) {
4506                         WARN(vma->pin_count,
4507                              "bo is already pinned in %s with incorrect alignment:"
4508                              " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4509                              " obj->map_and_fenceable=%d\n",
4510                              ggtt_view ? "ggtt" : "ppgtt",
4511                              upper_32_bits(vma->node.start),
4512                              lower_32_bits(vma->node.start),
4513                              alignment,
4514                              !!(flags & PIN_MAPPABLE),
4515                              obj->map_and_fenceable);
4516                         ret = i915_vma_unbind(vma);
4517                         if (ret)
4518                                 return ret;
4519
4520                         vma = NULL;
4521                 }
4522         }
4523
4524         bound = vma ? vma->bound : 0;
4525         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4526                 vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment,
4527                                                  flags);
4528                 if (IS_ERR(vma))
4529                         return PTR_ERR(vma);
4530         } else {
4531                 ret = i915_vma_bind(vma, obj->cache_level, flags);
4532                 if (ret)
4533                         return ret;
4534         }
4535
4536         if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL &&
4537             (bound ^ vma->bound) & GLOBAL_BIND) {
4538                 __i915_vma_set_map_and_fenceable(vma);
4539                 WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
4540         }
4541
4542         vma->pin_count++;
4543         return 0;
4544 }
4545
4546 int
4547 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4548                     struct i915_address_space *vm,
4549                     uint32_t alignment,
4550                     uint64_t flags)
4551 {
4552         return i915_gem_object_do_pin(obj, vm,
4553                                       i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL,
4554                                       alignment, flags);
4555 }
4556
4557 int
4558 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
4559                          const struct i915_ggtt_view *view,
4560                          uint32_t alignment,
4561                          uint64_t flags)
4562 {
4563         struct drm_device *dev = obj->base.dev;
4564         struct drm_i915_private *dev_priv = to_i915(dev);
4565         struct i915_ggtt *ggtt = &dev_priv->ggtt;
4566
4567         BUG_ON(!view);
4568
4569         return i915_gem_object_do_pin(obj, &ggtt->base, view,
4570                                       alignment, flags | PIN_GLOBAL);
4571 }
4572
4573 void
4574 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
4575                                 const struct i915_ggtt_view *view)
4576 {
4577         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
4578
4579         WARN_ON(vma->pin_count == 0);
4580         WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view));
4581
4582         --vma->pin_count;
4583 }
4584
4585 int
4586 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4587                     struct drm_file *file)
4588 {
4589         struct drm_i915_gem_busy *args = data;
4590         struct drm_i915_gem_object *obj;
4591         int ret;
4592
4593         ret = i915_mutex_lock_interruptible(dev);
4594         if (ret)
4595                 return ret;
4596
4597         obj = to_intel_bo(drm_gem_object_lookup(file, args->handle));
4598         if (&obj->base == NULL) {
4599                 ret = -ENOENT;
4600                 goto unlock;
4601         }
4602
4603         /* Count all active objects as busy, even if they are currently not used
4604          * by the gpu. Users of this interface expect objects to eventually
4605          * become non-busy without any further actions, therefore emit any
4606          * necessary flushes here.
4607          */
4608         ret = i915_gem_object_flush_active(obj);
4609         if (ret)
4610                 goto unref;
4611
4612         args->busy = 0;
4613         if (obj->active) {
4614                 int i;
4615
4616                 for (i = 0; i < I915_NUM_ENGINES; i++) {
4617                         struct drm_i915_gem_request *req;
4618
4619                         req = obj->last_read_req[i];
4620                         if (req)
4621                                 args->busy |= 1 << (16 + req->engine->exec_id);
4622                 }
4623                 if (obj->last_write_req)
4624                         args->busy |= obj->last_write_req->engine->exec_id;
4625         }
4626
4627 unref:
4628         drm_gem_object_unreference(&obj->base);
4629 unlock:
4630         mutex_unlock(&dev->struct_mutex);
4631         return ret;
4632 }
4633
4634 int
4635 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4636                         struct drm_file *file_priv)
4637 {
4638         return i915_gem_ring_throttle(dev, file_priv);
4639 }
4640
4641 int
4642 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4643                        struct drm_file *file_priv)
4644 {
4645         struct drm_i915_private *dev_priv = dev->dev_private;
4646         struct drm_i915_gem_madvise *args = data;
4647         struct drm_i915_gem_object *obj;
4648         int ret;
4649
4650         switch (args->madv) {
4651         case I915_MADV_DONTNEED:
4652         case I915_MADV_WILLNEED:
4653             break;
4654         default:
4655             return -EINVAL;
4656         }
4657
4658         ret = i915_mutex_lock_interruptible(dev);
4659         if (ret)
4660                 return ret;
4661
4662         obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle));
4663         if (&obj->base == NULL) {
4664                 ret = -ENOENT;
4665                 goto unlock;
4666         }
4667
4668         if (i915_gem_obj_is_pinned(obj)) {
4669                 ret = -EINVAL;
4670                 goto out;
4671         }
4672
4673         if (obj->pages &&
4674             obj->tiling_mode != I915_TILING_NONE &&
4675             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
4676                 if (obj->madv == I915_MADV_WILLNEED)
4677                         i915_gem_object_unpin_pages(obj);
4678                 if (args->madv == I915_MADV_WILLNEED)
4679                         i915_gem_object_pin_pages(obj);
4680         }
4681
4682         if (obj->madv != __I915_MADV_PURGED)
4683                 obj->madv = args->madv;
4684
4685         /* if the object is no longer attached, discard its backing storage */
4686         if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL)
4687                 i915_gem_object_truncate(obj);
4688
4689         args->retained = obj->madv != __I915_MADV_PURGED;
4690
4691 out:
4692         drm_gem_object_unreference(&obj->base);
4693 unlock:
4694         mutex_unlock(&dev->struct_mutex);
4695         return ret;
4696 }
4697
4698 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4699                           const struct drm_i915_gem_object_ops *ops)
4700 {
4701         int i;
4702
4703         INIT_LIST_HEAD(&obj->global_list);
4704         for (i = 0; i < I915_NUM_ENGINES; i++)
4705                 INIT_LIST_HEAD(&obj->engine_list[i]);
4706         INIT_LIST_HEAD(&obj->obj_exec_link);
4707         INIT_LIST_HEAD(&obj->vma_list);
4708         INIT_LIST_HEAD(&obj->batch_pool_link);
4709
4710         obj->ops = ops;
4711
4712         obj->fence_reg = I915_FENCE_REG_NONE;
4713         obj->madv = I915_MADV_WILLNEED;
4714
4715         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4716 }
4717
4718 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4719         .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE,
4720         .get_pages = i915_gem_object_get_pages_gtt,
4721         .put_pages = i915_gem_object_put_pages_gtt,
4722 };
4723
4724 struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
4725                                                   size_t size)
4726 {
4727         struct drm_i915_gem_object *obj;
4728         struct address_space *mapping;
4729         gfp_t mask;
4730         int ret;
4731
4732         obj = i915_gem_object_alloc(dev);
4733         if (obj == NULL)
4734                 return ERR_PTR(-ENOMEM);
4735
4736         ret = drm_gem_object_init(dev, &obj->base, size);
4737         if (ret)
4738                 goto fail;
4739
4740         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4741         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4742                 /* 965gm cannot relocate objects above 4GiB. */
4743                 mask &= ~__GFP_HIGHMEM;
4744                 mask |= __GFP_DMA32;
4745         }
4746
4747         mapping = file_inode(obj->base.filp)->i_mapping;
4748         mapping_set_gfp_mask(mapping, mask);
4749
4750         i915_gem_object_init(obj, &i915_gem_object_ops);
4751
4752         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4753         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4754
4755         if (HAS_LLC(dev)) {
4756                 /* On some devices, we can have the GPU use the LLC (the CPU
4757                  * cache) for about a 10% performance improvement
4758                  * compared to uncached.  Graphics requests other than
4759                  * display scanout are coherent with the CPU in
4760                  * accessing this cache.  This means in this mode we
4761                  * don't need to clflush on the CPU side, and on the
4762                  * GPU side we only need to flush internal caches to
4763                  * get data visible to the CPU.
4764                  *
4765                  * However, we maintain the display planes as UC, and so
4766                  * need to rebind when first used as such.
4767                  */
4768                 obj->cache_level = I915_CACHE_LLC;
4769         } else
4770                 obj->cache_level = I915_CACHE_NONE;
4771
4772         trace_i915_gem_object_create(obj);
4773
4774         return obj;
4775
4776 fail:
4777         i915_gem_object_free(obj);
4778
4779         return ERR_PTR(ret);
4780 }
4781
4782 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4783 {
4784         /* If we are the last user of the backing storage (be it shmemfs
4785          * pages or stolen etc), we know that the pages are going to be
4786          * immediately released. In this case, we can then skip copying
4787          * back the contents from the GPU.
4788          */
4789
4790         if (obj->madv != I915_MADV_WILLNEED)
4791                 return false;
4792
4793         if (obj->base.filp == NULL)
4794                 return true;
4795
4796         /* At first glance, this looks racy, but then again so would be
4797          * userspace racing mmap against close. However, the first external
4798          * reference to the filp can only be obtained through the
4799          * i915_gem_mmap_ioctl() which safeguards us against the user
4800          * acquiring such a reference whilst we are in the middle of
4801          * freeing the object.
4802          */
4803         return atomic_long_read(&obj->base.filp->f_count) == 1;
4804 }
4805
4806 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4807 {
4808         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4809         struct drm_device *dev = obj->base.dev;
4810         struct drm_i915_private *dev_priv = dev->dev_private;
4811         struct i915_vma *vma, *next;
4812
4813         intel_runtime_pm_get(dev_priv);
4814
4815         trace_i915_gem_object_destroy(obj);
4816
4817         list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) {
4818                 int ret;
4819
4820                 vma->pin_count = 0;
4821                 ret = i915_vma_unbind(vma);
4822                 if (WARN_ON(ret == -ERESTARTSYS)) {
4823                         bool was_interruptible;
4824
4825                         was_interruptible = dev_priv->mm.interruptible;
4826                         dev_priv->mm.interruptible = false;
4827
4828                         WARN_ON(i915_vma_unbind(vma));
4829
4830                         dev_priv->mm.interruptible = was_interruptible;
4831                 }
4832         }
4833
4834         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4835          * before progressing. */
4836         if (obj->stolen)
4837                 i915_gem_object_unpin_pages(obj);
4838
4839         WARN_ON(obj->frontbuffer_bits);
4840
4841         if (obj->pages && obj->madv == I915_MADV_WILLNEED &&
4842             dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES &&
4843             obj->tiling_mode != I915_TILING_NONE)
4844                 i915_gem_object_unpin_pages(obj);
4845
4846         if (WARN_ON(obj->pages_pin_count))
4847                 obj->pages_pin_count = 0;
4848         if (discard_backing_storage(obj))
4849                 obj->madv = I915_MADV_DONTNEED;
4850         i915_gem_object_put_pages(obj);
4851         i915_gem_object_free_mmap_offset(obj);
4852
4853         BUG_ON(obj->pages);
4854
4855         if (obj->base.import_attach)
4856                 drm_prime_gem_destroy(&obj->base, NULL);
4857
4858         if (obj->ops->release)
4859                 obj->ops->release(obj);
4860
4861         drm_gem_object_release(&obj->base);
4862         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4863
4864         kfree(obj->bit_17);
4865         i915_gem_object_free(obj);
4866
4867         intel_runtime_pm_put(dev_priv);
4868 }
4869
4870 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4871                                      struct i915_address_space *vm)
4872 {
4873         struct i915_vma *vma;
4874         list_for_each_entry(vma, &obj->vma_list, obj_link) {
4875                 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL &&
4876                     vma->vm == vm)
4877                         return vma;
4878         }
4879         return NULL;
4880 }
4881
4882 struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
4883                                            const struct i915_ggtt_view *view)
4884 {
4885         struct i915_vma *vma;
4886
4887         GEM_BUG_ON(!view);
4888
4889         list_for_each_entry(vma, &obj->vma_list, obj_link)
4890                 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
4891                         return vma;
4892         return NULL;
4893 }
4894
4895 void i915_gem_vma_destroy(struct i915_vma *vma)
4896 {
4897         WARN_ON(vma->node.allocated);
4898
4899         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4900         if (!list_empty(&vma->exec_list))
4901                 return;
4902
4903         if (!vma->is_ggtt)
4904                 i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm));
4905
4906         list_del(&vma->obj_link);
4907
4908         kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
4909 }
4910
4911 static void
4912 i915_gem_stop_engines(struct drm_device *dev)
4913 {
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         struct intel_engine_cs *engine;
4916
4917         for_each_engine(engine, dev_priv)
4918                 dev_priv->gt.stop_engine(engine);
4919 }
4920
4921 int
4922 i915_gem_suspend(struct drm_device *dev)
4923 {
4924         struct drm_i915_private *dev_priv = dev->dev_private;
4925         int ret = 0;
4926
4927         mutex_lock(&dev->struct_mutex);
4928         ret = i915_gem_wait_for_idle(dev_priv);
4929         if (ret)
4930                 goto err;
4931
4932         i915_gem_retire_requests(dev_priv);
4933
4934         i915_gem_stop_engines(dev);
4935         i915_gem_context_lost(dev_priv);
4936         mutex_unlock(&dev->struct_mutex);
4937
4938         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
4939         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4940         flush_delayed_work(&dev_priv->mm.idle_work);
4941
4942         /* Assert that we sucessfully flushed all the work and
4943          * reset the GPU back to its idle, low power state.
4944          */
4945         WARN_ON(dev_priv->mm.busy);
4946
4947         return 0;
4948
4949 err:
4950         mutex_unlock(&dev->struct_mutex);
4951         return ret;
4952 }
4953
4954 void i915_gem_init_swizzling(struct drm_device *dev)
4955 {
4956         struct drm_i915_private *dev_priv = dev->dev_private;
4957
4958         if (INTEL_INFO(dev)->gen < 5 ||
4959             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4960                 return;
4961
4962         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4963                                  DISP_TILE_SURFACE_SWIZZLING);
4964
4965         if (IS_GEN5(dev))
4966                 return;
4967
4968         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4969         if (IS_GEN6(dev))
4970                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4971         else if (IS_GEN7(dev))
4972                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4973         else if (IS_GEN8(dev))
4974                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4975         else
4976                 BUG();
4977 }
4978
4979 static void init_unused_ring(struct drm_device *dev, u32 base)
4980 {
4981         struct drm_i915_private *dev_priv = dev->dev_private;
4982
4983         I915_WRITE(RING_CTL(base), 0);
4984         I915_WRITE(RING_HEAD(base), 0);
4985         I915_WRITE(RING_TAIL(base), 0);
4986         I915_WRITE(RING_START(base), 0);
4987 }
4988
4989 static void init_unused_rings(struct drm_device *dev)
4990 {
4991         if (IS_I830(dev)) {
4992                 init_unused_ring(dev, PRB1_BASE);
4993                 init_unused_ring(dev, SRB0_BASE);
4994                 init_unused_ring(dev, SRB1_BASE);
4995                 init_unused_ring(dev, SRB2_BASE);
4996                 init_unused_ring(dev, SRB3_BASE);
4997         } else if (IS_GEN2(dev)) {
4998                 init_unused_ring(dev, SRB0_BASE);
4999                 init_unused_ring(dev, SRB1_BASE);
5000         } else if (IS_GEN3(dev)) {
5001                 init_unused_ring(dev, PRB1_BASE);
5002                 init_unused_ring(dev, PRB2_BASE);
5003         }
5004 }
5005
5006 int i915_gem_init_engines(struct drm_device *dev)
5007 {
5008         struct drm_i915_private *dev_priv = dev->dev_private;
5009         int ret;
5010
5011         ret = intel_init_render_ring_buffer(dev);
5012         if (ret)
5013                 return ret;
5014
5015         if (HAS_BSD(dev)) {
5016                 ret = intel_init_bsd_ring_buffer(dev);
5017                 if (ret)
5018                         goto cleanup_render_ring;
5019         }
5020
5021         if (HAS_BLT(dev)) {
5022                 ret = intel_init_blt_ring_buffer(dev);
5023                 if (ret)
5024                         goto cleanup_bsd_ring;
5025         }
5026
5027         if (HAS_VEBOX(dev)) {
5028                 ret = intel_init_vebox_ring_buffer(dev);
5029                 if (ret)
5030                         goto cleanup_blt_ring;
5031         }
5032
5033         if (HAS_BSD2(dev)) {
5034                 ret = intel_init_bsd2_ring_buffer(dev);
5035                 if (ret)
5036                         goto cleanup_vebox_ring;
5037         }
5038
5039         return 0;
5040
5041 cleanup_vebox_ring:
5042         intel_cleanup_engine(&dev_priv->engine[VECS]);
5043 cleanup_blt_ring:
5044         intel_cleanup_engine(&dev_priv->engine[BCS]);
5045 cleanup_bsd_ring:
5046         intel_cleanup_engine(&dev_priv->engine[VCS]);
5047 cleanup_render_ring:
5048         intel_cleanup_engine(&dev_priv->engine[RCS]);
5049
5050         return ret;
5051 }
5052
5053 int
5054 i915_gem_init_hw(struct drm_device *dev)
5055 {
5056         struct drm_i915_private *dev_priv = dev->dev_private;
5057         struct intel_engine_cs *engine;
5058         int ret;
5059
5060         /* Double layer security blanket, see i915_gem_init() */
5061         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5062
5063         if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9)
5064                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
5065
5066         if (IS_HASWELL(dev))
5067                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
5068                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
5069
5070         if (HAS_PCH_NOP(dev)) {
5071                 if (IS_IVYBRIDGE(dev)) {
5072                         u32 temp = I915_READ(GEN7_MSG_CTL);
5073                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
5074                         I915_WRITE(GEN7_MSG_CTL, temp);
5075                 } else if (INTEL_INFO(dev)->gen >= 7) {
5076                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
5077                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
5078                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
5079                 }
5080         }
5081
5082         i915_gem_init_swizzling(dev);
5083
5084         /*
5085          * At least 830 can leave some of the unused rings
5086          * "active" (ie. head != tail) after resume which
5087          * will prevent c3 entry. Makes sure all unused rings
5088          * are totally idle.
5089          */
5090         init_unused_rings(dev);
5091
5092         BUG_ON(!dev_priv->kernel_context);
5093
5094         ret = i915_ppgtt_init_hw(dev);
5095         if (ret) {
5096                 DRM_ERROR("PPGTT enable HW failed %d\n", ret);
5097                 goto out;
5098         }
5099
5100         /* Need to do basic initialisation of all rings first: */
5101         for_each_engine(engine, dev_priv) {
5102                 ret = engine->init_hw(engine);
5103                 if (ret)
5104                         goto out;
5105         }
5106
5107         intel_mocs_init_l3cc_table(dev);
5108
5109         /* We can't enable contexts until all firmware is loaded */
5110         ret = intel_guc_setup(dev);
5111         if (ret)
5112                 goto out;
5113
5114         /*
5115          * Increment the next seqno by 0x100 so we have a visible break
5116          * on re-initialisation
5117          */
5118         ret = i915_gem_set_seqno(dev, dev_priv->next_seqno+0x100);
5119
5120 out:
5121         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5122         return ret;
5123 }
5124
5125 int i915_gem_init(struct drm_device *dev)
5126 {
5127         struct drm_i915_private *dev_priv = dev->dev_private;
5128         int ret;
5129
5130         mutex_lock(&dev->struct_mutex);
5131
5132         if (!i915.enable_execlists) {
5133                 dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission;
5134                 dev_priv->gt.init_engines = i915_gem_init_engines;
5135                 dev_priv->gt.cleanup_engine = intel_cleanup_engine;
5136                 dev_priv->gt.stop_engine = intel_stop_engine;
5137         } else {
5138                 dev_priv->gt.execbuf_submit = intel_execlists_submission;
5139                 dev_priv->gt.init_engines = intel_logical_rings_init;
5140                 dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup;
5141                 dev_priv->gt.stop_engine = intel_logical_ring_stop;
5142         }
5143
5144         /* This is just a security blanket to placate dragons.
5145          * On some systems, we very sporadically observe that the first TLBs
5146          * used by the CS may be stale, despite us poking the TLB reset. If
5147          * we hold the forcewake during initialisation these problems
5148          * just magically go away.
5149          */
5150         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5151
5152         i915_gem_init_userptr(dev_priv);
5153         i915_gem_init_ggtt(dev);
5154
5155         ret = i915_gem_context_init(dev);
5156         if (ret)
5157                 goto out_unlock;
5158
5159         ret = dev_priv->gt.init_engines(dev);
5160         if (ret)
5161                 goto out_unlock;
5162
5163         ret = i915_gem_init_hw(dev);
5164         if (ret == -EIO) {
5165                 /* Allow ring initialisation to fail by marking the GPU as
5166                  * wedged. But we only want to do this where the GPU is angry,
5167                  * for all other failure, such as an allocation failure, bail.
5168                  */
5169                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5170                 atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
5171                 ret = 0;
5172         }
5173
5174 out_unlock:
5175         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5176         mutex_unlock(&dev->struct_mutex);
5177
5178         return ret;
5179 }
5180
5181 void
5182 i915_gem_cleanup_engines(struct drm_device *dev)
5183 {
5184         struct drm_i915_private *dev_priv = dev->dev_private;
5185         struct intel_engine_cs *engine;
5186
5187         for_each_engine(engine, dev_priv)
5188                 dev_priv->gt.cleanup_engine(engine);
5189 }
5190
5191 static void
5192 init_engine_lists(struct intel_engine_cs *engine)
5193 {
5194         INIT_LIST_HEAD(&engine->active_list);
5195         INIT_LIST_HEAD(&engine->request_list);
5196 }
5197
5198 void
5199 i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
5200 {
5201         struct drm_device *dev = dev_priv->dev;
5202
5203         if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
5204             !IS_CHERRYVIEW(dev_priv))
5205                 dev_priv->num_fence_regs = 32;
5206         else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
5207                  IS_I945GM(dev_priv) || IS_G33(dev_priv))
5208                 dev_priv->num_fence_regs = 16;
5209         else
5210                 dev_priv->num_fence_regs = 8;
5211
5212         if (intel_vgpu_active(dev_priv))
5213                 dev_priv->num_fence_regs =
5214                                 I915_READ(vgtif_reg(avail_rs.fence_num));
5215
5216         /* Initialize fence registers to zero */
5217         i915_gem_restore_fences(dev);
5218
5219         i915_gem_detect_bit_6_swizzle(dev);
5220 }
5221
5222 void
5223 i915_gem_load_init(struct drm_device *dev)
5224 {
5225         struct drm_i915_private *dev_priv = dev->dev_private;
5226         int i;
5227
5228         dev_priv->objects =
5229                 kmem_cache_create("i915_gem_object",
5230                                   sizeof(struct drm_i915_gem_object), 0,
5231                                   SLAB_HWCACHE_ALIGN,
5232                                   NULL);
5233         dev_priv->vmas =
5234                 kmem_cache_create("i915_gem_vma",
5235                                   sizeof(struct i915_vma), 0,
5236                                   SLAB_HWCACHE_ALIGN,
5237                                   NULL);
5238         dev_priv->requests =
5239                 kmem_cache_create("i915_gem_request",
5240                                   sizeof(struct drm_i915_gem_request), 0,
5241                                   SLAB_HWCACHE_ALIGN,
5242                                   NULL);
5243
5244         INIT_LIST_HEAD(&dev_priv->vm_list);
5245         INIT_LIST_HEAD(&dev_priv->context_list);
5246         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
5247         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
5248         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5249         for (i = 0; i < I915_NUM_ENGINES; i++)
5250                 init_engine_lists(&dev_priv->engine[i]);
5251         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
5252                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
5253         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
5254                           i915_gem_retire_work_handler);
5255         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
5256                           i915_gem_idle_work_handler);
5257         init_waitqueue_head(&dev_priv->gpu_error.wait_queue);
5258         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
5259
5260         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
5261
5262         /*
5263          * Set initial sequence number for requests.
5264          * Using this number allows the wraparound to happen early,
5265          * catching any obvious problems.
5266          */
5267         dev_priv->next_seqno = ((u32)~0 - 0x1100);
5268         dev_priv->last_seqno = ((u32)~0 - 0x1101);
5269
5270         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
5271
5272         init_waitqueue_head(&dev_priv->pending_flip_queue);
5273
5274         dev_priv->mm.interruptible = true;
5275
5276         mutex_init(&dev_priv->fb_tracking.lock);
5277 }
5278
5279 void i915_gem_load_cleanup(struct drm_device *dev)
5280 {
5281         struct drm_i915_private *dev_priv = to_i915(dev);
5282
5283         kmem_cache_destroy(dev_priv->requests);
5284         kmem_cache_destroy(dev_priv->vmas);
5285         kmem_cache_destroy(dev_priv->objects);
5286 }
5287
5288 int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
5289 {
5290         struct drm_i915_gem_object *obj;
5291
5292         /* Called just before we write the hibernation image.
5293          *
5294          * We need to update the domain tracking to reflect that the CPU
5295          * will be accessing all the pages to create and restore from the
5296          * hibernation, and so upon restoration those pages will be in the
5297          * CPU domain.
5298          *
5299          * To make sure the hibernation image contains the latest state,
5300          * we update that state just before writing out the image.
5301          */
5302
5303         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5304                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
5305                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
5306         }
5307
5308         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5309                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
5310                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
5311         }
5312
5313         return 0;
5314 }
5315
5316 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5317 {
5318         struct drm_i915_file_private *file_priv = file->driver_priv;
5319
5320         /* Clean up our request list when the client is going away, so that
5321          * later retire_requests won't dereference our soon-to-be-gone
5322          * file_priv.
5323          */
5324         spin_lock(&file_priv->mm.lock);
5325         while (!list_empty(&file_priv->mm.request_list)) {
5326                 struct drm_i915_gem_request *request;
5327
5328                 request = list_first_entry(&file_priv->mm.request_list,
5329                                            struct drm_i915_gem_request,
5330                                            client_list);
5331                 list_del(&request->client_list);
5332                 request->file_priv = NULL;
5333         }
5334         spin_unlock(&file_priv->mm.lock);
5335
5336         if (!list_empty(&file_priv->rps.link)) {
5337                 spin_lock(&to_i915(dev)->rps.client_lock);
5338                 list_del(&file_priv->rps.link);
5339                 spin_unlock(&to_i915(dev)->rps.client_lock);
5340         }
5341 }
5342
5343 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5344 {
5345         struct drm_i915_file_private *file_priv;
5346         int ret;
5347
5348         DRM_DEBUG_DRIVER("\n");
5349
5350         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5351         if (!file_priv)
5352                 return -ENOMEM;
5353
5354         file->driver_priv = file_priv;
5355         file_priv->dev_priv = dev->dev_private;
5356         file_priv->file = file;
5357         INIT_LIST_HEAD(&file_priv->rps.link);
5358
5359         spin_lock_init(&file_priv->mm.lock);
5360         INIT_LIST_HEAD(&file_priv->mm.request_list);
5361
5362         file_priv->bsd_ring = -1;
5363
5364         ret = i915_gem_context_open(dev, file);
5365         if (ret)
5366                 kfree(file_priv);
5367
5368         return ret;
5369 }
5370
5371 /**
5372  * i915_gem_track_fb - update frontbuffer tracking
5373  * @old: current GEM buffer for the frontbuffer slots
5374  * @new: new GEM buffer for the frontbuffer slots
5375  * @frontbuffer_bits: bitmask of frontbuffer slots
5376  *
5377  * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5378  * from @old and setting them in @new. Both @old and @new can be NULL.
5379  */
5380 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5381                        struct drm_i915_gem_object *new,
5382                        unsigned frontbuffer_bits)
5383 {
5384         if (old) {
5385                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5386                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5387                 old->frontbuffer_bits &= ~frontbuffer_bits;
5388         }
5389
5390         if (new) {
5391                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5392                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5393                 new->frontbuffer_bits |= frontbuffer_bits;
5394         }
5395 }
5396
5397 /* All the new VM stuff */
5398 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
5399                         struct i915_address_space *vm)
5400 {
5401         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5402         struct i915_vma *vma;
5403
5404         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5405
5406         list_for_each_entry(vma, &o->vma_list, obj_link) {
5407                 if (vma->is_ggtt &&
5408                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5409                         continue;
5410                 if (vma->vm == vm)
5411                         return vma->node.start;
5412         }
5413
5414         WARN(1, "%s vma for this object not found.\n",
5415              i915_is_ggtt(vm) ? "global" : "ppgtt");
5416         return -1;
5417 }
5418
5419 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
5420                                   const struct i915_ggtt_view *view)
5421 {
5422         struct i915_vma *vma;
5423
5424         list_for_each_entry(vma, &o->vma_list, obj_link)
5425                 if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view))
5426                         return vma->node.start;
5427
5428         WARN(1, "global vma for this object not found. (view=%u)\n", view->type);
5429         return -1;
5430 }
5431
5432 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5433                         struct i915_address_space *vm)
5434 {
5435         struct i915_vma *vma;
5436
5437         list_for_each_entry(vma, &o->vma_list, obj_link) {
5438                 if (vma->is_ggtt &&
5439                     vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL)
5440                         continue;
5441                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5442                         return true;
5443         }
5444
5445         return false;
5446 }
5447
5448 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
5449                                   const struct i915_ggtt_view *view)
5450 {
5451         struct i915_vma *vma;
5452
5453         list_for_each_entry(vma, &o->vma_list, obj_link)
5454                 if (vma->is_ggtt &&
5455                     i915_ggtt_view_equal(&vma->ggtt_view, view) &&
5456                     drm_mm_node_allocated(&vma->node))
5457                         return true;
5458
5459         return false;
5460 }
5461
5462 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5463 {
5464         struct i915_vma *vma;
5465
5466         list_for_each_entry(vma, &o->vma_list, obj_link)
5467                 if (drm_mm_node_allocated(&vma->node))
5468                         return true;
5469
5470         return false;
5471 }
5472
5473 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
5474 {
5475         struct i915_vma *vma;
5476
5477         GEM_BUG_ON(list_empty(&o->vma_list));
5478
5479         list_for_each_entry(vma, &o->vma_list, obj_link) {
5480                 if (vma->is_ggtt &&
5481                     vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
5482                         return vma->node.size;
5483         }
5484
5485         return 0;
5486 }
5487
5488 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj)
5489 {
5490         struct i915_vma *vma;
5491         list_for_each_entry(vma, &obj->vma_list, obj_link)
5492                 if (vma->pin_count > 0)
5493                         return true;
5494
5495         return false;
5496 }
5497
5498 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5499 struct page *
5500 i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n)
5501 {
5502         struct page *page;
5503
5504         /* Only default objects have per-page dirty tracking */
5505         if (WARN_ON(!i915_gem_object_has_struct_page(obj)))
5506                 return NULL;
5507
5508         page = i915_gem_object_get_page(obj, n);
5509         set_page_dirty(page);
5510         return page;
5511 }
5512
5513 /* Allocate a new GEM object and fill it with the supplied data */
5514 struct drm_i915_gem_object *
5515 i915_gem_object_create_from_data(struct drm_device *dev,
5516                                  const void *data, size_t size)
5517 {
5518         struct drm_i915_gem_object *obj;
5519         struct sg_table *sg;
5520         size_t bytes;
5521         int ret;
5522
5523         obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE));
5524         if (IS_ERR(obj))
5525                 return obj;
5526
5527         ret = i915_gem_object_set_to_cpu_domain(obj, true);
5528         if (ret)
5529                 goto fail;
5530
5531         ret = i915_gem_object_get_pages(obj);
5532         if (ret)
5533                 goto fail;
5534
5535         i915_gem_object_pin_pages(obj);
5536         sg = obj->pages;
5537         bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size);
5538         obj->dirty = 1;         /* Backing store is now out of date */
5539         i915_gem_object_unpin_pages(obj);
5540
5541         if (WARN_ON(bytes != size)) {
5542                 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size);
5543                 ret = -EFAULT;
5544                 goto fail;
5545         }
5546
5547         return obj;
5548
5549 fail:
5550         drm_gem_object_unreference(&obj->base);
5551         return ERR_PTR(ret);
5552 }