drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include <drm/drmP.h>
  29 #include <drm/drm_vma_manager.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/oom.h>
  35 #include <linux/shmem_fs.h>
  36 #include <linux/slab.h>
  37 #include <linux/swap.h>
  38 #include <linux/pci.h>
  39 #include <linux/dma-buf.h>
  40
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
  43                                                    bool force);
  44 static __must_check int
  45 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
  46                                bool readonly);
  47 static void
  48 i915_gem_object_retire(struct drm_i915_gem_object *obj);
  49
  50 static void i915_gem_write_fence(struct drm_device *dev, int reg,
  51                                  struct drm_i915_gem_object *obj);
  52 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
  53                                          struct drm_i915_fence_reg *fence,
  54                                          bool enable);
  55
  56 static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker,
  57                                              struct shrink_control *sc);
  58 static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker,
  59                                             struct shrink_control *sc);
  60 static int i915_gem_shrinker_oom(struct notifier_block *nb,
  61                                  unsigned long event,
  62                                  void *ptr);
  63 static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target);
  64 static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
  65
  66 static bool cpu_cache_is_coherent(struct drm_device *dev,
  67                                   enum i915_cache_level level)
  68 {
  69         return HAS_LLC(dev) || level != I915_CACHE_NONE;
  70 }
  71
  72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
  73 {
  74         if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
  75                 return true;
  76
  77         return obj->pin_display;
  78 }
  79
  80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj)
  81 {
  82         if (obj->tiling_mode)
  83                 i915_gem_release_mmap(obj);
  84
  85         /* As we do not have an associated fence register, we will force
  86          * a tiling change if we ever need to acquire one.
  87          */
  88         obj->fence_dirty = false;
  89         obj->fence_reg = I915_FENCE_REG_NONE;
  90 }
  91
  92 /* some bookkeeping */
  93 static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
  94                                   size_t size)
  95 {
  96         spin_lock(&dev_priv->mm.object_stat_lock);
  97         dev_priv->mm.object_count++;
  98         dev_priv->mm.object_memory += size;
  99         spin_unlock(&dev_priv->mm.object_stat_lock);
 100 }
 101
 102 static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
 103                                      size_t size)
 104 {
 105         spin_lock(&dev_priv->mm.object_stat_lock);
 106         dev_priv->mm.object_count--;
 107         dev_priv->mm.object_memory -= size;
 108         spin_unlock(&dev_priv->mm.object_stat_lock);
 109 }
 110
 111 static int
 112 i915_gem_wait_for_error(struct i915_gpu_error *error)
 113 {
 114         int ret;
 115
 116 #define EXIT_COND (!i915_reset_in_progress(error) || \
 117                    i915_terminally_wedged(error))
 118         if (EXIT_COND)
 119                 return 0;
 120
 121         /*
 122          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
 123          * userspace. If it takes that long something really bad is going on and
 124          * we should simply try to bail out and fail as gracefully as possible.
 125          */
 126         ret = wait_event_interruptible_timeout(error->reset_queue,
 127                                                EXIT_COND,
 128                                                10*HZ);
 129         if (ret == 0) {
 130                 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
 131                 return -EIO;
 132         } else if (ret < 0) {
 133                 return ret;
 134         }
 135 #undef EXIT_COND
 136
 137         return 0;
 138 }
 139
 140 int i915_mutex_lock_interruptible(struct drm_device *dev)
 141 {
 142         struct drm_i915_private *dev_priv = dev->dev_private;
 143         int ret;
 144
 145         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
 146         if (ret)
 147                 return ret;
 148
 149         ret = mutex_lock_interruptible(&dev->struct_mutex);
 150         if (ret)
 151                 return ret;
 152
 153         WARN_ON(i915_verify_lists(dev));
 154         return 0;
 155 }
 156
 157 static inline bool
 158 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
 159 {
 160         return i915_gem_obj_bound_any(obj) && !obj->active;
 161 }
 162
 163 int
 164 i915_gem_init_ioctl(struct drm_device *dev, void *data,
 165                     struct drm_file *file)
 166 {
 167         struct drm_i915_private *dev_priv = dev->dev_private;
 168         struct drm_i915_gem_init *args = data;
 169
 170         if (drm_core_check_feature(dev, DRIVER_MODESET))
 171                 return -ENODEV;
 172
 173         if (args->gtt_start >= args->gtt_end ||
 174             (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
 175                 return -EINVAL;
 176
 177         /* GEM with user mode setting was never supported on ilk and later. */
 178         if (INTEL_INFO(dev)->gen >= 5)
 179                 return -ENODEV;
 180
 181         mutex_lock(&dev->struct_mutex);
 182         i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end,
 183                                   args->gtt_end);
 184         dev_priv->gtt.mappable_end = args->gtt_end;
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         return 0;
 188 }
 189
 190 int
 191 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 192                             struct drm_file *file)
 193 {
 194         struct drm_i915_private *dev_priv = dev->dev_private;
 195         struct drm_i915_gem_get_aperture *args = data;
 196         struct drm_i915_gem_object *obj;
 197         size_t pinned;
 198
 199         pinned = 0;
 200         mutex_lock(&dev->struct_mutex);
 201         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
 202                 if (i915_gem_obj_is_pinned(obj))
 203                         pinned += i915_gem_obj_ggtt_size(obj);
 204         mutex_unlock(&dev->struct_mutex);
 205
 206         args->aper_size = dev_priv->gtt.base.total;
 207         args->aper_available_size = args->aper_size - pinned;
 208
 209         return 0;
 210 }
 211
 212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object *obj)
 213 {
 214         drm_dma_handle_t *phys = obj->phys_handle;
 215
 216         if (!phys)
 217                 return;
 218
 219         if (obj->madv == I915_MADV_WILLNEED) {
 220                 struct address_space *mapping = file_inode(obj->base.filp)->i_mapping;
 221                 char *vaddr = phys->vaddr;
 222                 int i;
 223
 224                 for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 225                         struct page *page = shmem_read_mapping_page(mapping, i);
 226                         if (!IS_ERR(page)) {
 227                                 char *dst = kmap_atomic(page);
 228                                 memcpy(dst, vaddr, PAGE_SIZE);
 229                                 drm_clflush_virt_range(dst, PAGE_SIZE);
 230                                 kunmap_atomic(dst);
 231
 232                                 set_page_dirty(page);
 233                                 mark_page_accessed(page);
 234                                 page_cache_release(page);
 235                         }
 236                         vaddr += PAGE_SIZE;
 237                 }
 238                 i915_gem_chipset_flush(obj->base.dev);
 239         }
 240
 241 #ifdef CONFIG_X86
 242         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 243 #endif
 244         drm_pci_free(obj->base.dev, phys);
 245         obj->phys_handle = NULL;
 246 }
 247
 248 int
 249 i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
 250                             int align)
 251 {
 252         drm_dma_handle_t *phys;
 253         struct address_space *mapping;
 254         char *vaddr;
 255         int i;
 256
 257         if (obj->phys_handle) {
 258                 if ((unsigned long)obj->phys_handle->vaddr & (align -1))
 259                         return -EBUSY;
 260
 261                 return 0;
 262         }
 263
 264         if (obj->madv != I915_MADV_WILLNEED)
 265                 return -EFAULT;
 266
 267         if (obj->base.filp == NULL)
 268                 return -EINVAL;
 269
 270         /* create a new object */
 271         phys = drm_pci_alloc(obj->base.dev, obj->base.size, align);
 272         if (!phys)
 273                 return -ENOMEM;
 274
 275         vaddr = phys->vaddr;
 276 #ifdef CONFIG_X86
 277         set_memory_wc((unsigned long)vaddr, phys->size / PAGE_SIZE);
 278 #endif
 279         mapping = file_inode(obj->base.filp)->i_mapping;
 280         for (i = 0; i < obj->base.size / PAGE_SIZE; i++) {
 281                 struct page *page;
 282                 char *src;
 283
 284                 page = shmem_read_mapping_page(mapping, i);
 285                 if (IS_ERR(page)) {
 286 #ifdef CONFIG_X86
 287                         set_memory_wb((unsigned long)phys->vaddr, phys->size / PAGE_SIZE);
 288 #endif
 289                         drm_pci_free(obj->base.dev, phys);
 290                         return PTR_ERR(page);
 291                 }
 292
 293                 src = kmap_atomic(page);
 294                 memcpy(vaddr, src, PAGE_SIZE);
 295                 kunmap_atomic(src);
 296
 297                 mark_page_accessed(page);
 298                 page_cache_release(page);
 299
 300                 vaddr += PAGE_SIZE;
 301         }
 302
 303         obj->phys_handle = phys;
 304         return 0;
 305 }
 306
 307 static int
 308 i915_gem_phys_pwrite(struct drm_i915_gem_object *obj,
 309                      struct drm_i915_gem_pwrite *args,
 310                      struct drm_file *file_priv)
 311 {
 312         struct drm_device *dev = obj->base.dev;
 313         void *vaddr = obj->phys_handle->vaddr + args->offset;
 314         char __user *user_data = to_user_ptr(args->data_ptr);
 315
 316         if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
 317                 unsigned long unwritten;
 318
 319                 /* The physical object once assigned is fixed for the lifetime
 320                  * of the obj, so we can safely drop the lock and continue
 321                  * to access vaddr.
 322                  */
 323                 mutex_unlock(&dev->struct_mutex);
 324                 unwritten = copy_from_user(vaddr, user_data, args->size);
 325                 mutex_lock(&dev->struct_mutex);
 326                 if (unwritten)
 327                         return -EFAULT;
 328         }
 329
 330         i915_gem_chipset_flush(dev);
 331         return 0;
 332 }
 333
 334 void *i915_gem_object_alloc(struct drm_device *dev)
 335 {
 336         struct drm_i915_private *dev_priv = dev->dev_private;
 337         return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL);
 338 }
 339
 340 void i915_gem_object_free(struct drm_i915_gem_object *obj)
 341 {
 342         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
 343         kmem_cache_free(dev_priv->slab, obj);
 344 }
 345
 346 static int
 347 i915_gem_create(struct drm_file *file,
 348                 struct drm_device *dev,
 349                 uint64_t size,
 350                 uint32_t *handle_p)
 351 {
 352         struct drm_i915_gem_object *obj;
 353         int ret;
 354         u32 handle;
 355
 356         size = roundup(size, PAGE_SIZE);
 357         if (size == 0)
 358                 return -EINVAL;
 359
 360         /* Allocate the new object */
 361         obj = i915_gem_alloc_object(dev, size);
 362         if (obj == NULL)
 363                 return -ENOMEM;
 364
 365         ret = drm_gem_handle_create(file, &obj->base, &handle);
 366         /* drop reference from allocate - handle holds it now */
 367         drm_gem_object_unreference_unlocked(&obj->base);
 368         if (ret)
 369                 return ret;
 370
 371         *handle_p = handle;
 372         return 0;
 373 }
 374
 375 int
 376 i915_gem_dumb_create(struct drm_file *file,
 377                      struct drm_device *dev,
 378                      struct drm_mode_create_dumb *args)
 379 {
 380         /* have to work out size/pitch and return them */
 381         args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64);
 382         args->size = args->pitch * args->height;
 383         return i915_gem_create(file, dev,
 384                                args->size, &args->handle);
 385 }
 386
 387 /**
 388  * Creates a new mm object and returns a handle to it.
 389  */
 390 int
 391 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 392                       struct drm_file *file)
 393 {
 394         struct drm_i915_gem_create *args = data;
 395
 396         return i915_gem_create(file, dev,
 397                                args->size, &args->handle);
 398 }
 399
 400 static inline int
 401 __copy_to_user_swizzled(char __user *cpu_vaddr,
 402                         const char *gpu_vaddr, int gpu_offset,
 403                         int length)
 404 {
 405         int ret, cpu_offset = 0;
 406
 407         while (length > 0) {
 408                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 409                 int this_length = min(cacheline_end - gpu_offset, length);
 410                 int swizzled_gpu_offset = gpu_offset ^ 64;
 411
 412                 ret = __copy_to_user(cpu_vaddr + cpu_offset,
 413                                      gpu_vaddr + swizzled_gpu_offset,
 414                                      this_length);
 415                 if (ret)
 416                         return ret + length;
 417
 418                 cpu_offset += this_length;
 419                 gpu_offset += this_length;
 420                 length -= this_length;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static inline int
 427 __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 428                           const char __user *cpu_vaddr,
 429                           int length)
 430 {
 431         int ret, cpu_offset = 0;
 432
 433         while (length > 0) {
 434                 int cacheline_end = ALIGN(gpu_offset + 1, 64);
 435                 int this_length = min(cacheline_end - gpu_offset, length);
 436                 int swizzled_gpu_offset = gpu_offset ^ 64;
 437
 438                 ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset,
 439                                        cpu_vaddr + cpu_offset,
 440                                        this_length);
 441                 if (ret)
 442                         return ret + length;
 443
 444                 cpu_offset += this_length;
 445                 gpu_offset += this_length;
 446                 length -= this_length;
 447         }
 448
 449         return 0;
 450 }
 451
 452 /*
 453  * Pins the specified object's pages and synchronizes the object with
 454  * GPU accesses. Sets needs_clflush to non-zero if the caller should
 455  * flush the object from the CPU cache.
 456  */
 457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 458                                     int *needs_clflush)
 459 {
 460         int ret;
 461
 462         *needs_clflush = 0;
 463
 464         if (!obj->base.filp)
 465                 return -EINVAL;
 466
 467         if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) {
 468                 /* If we're not in the cpu read domain, set ourself into the gtt
 469                  * read domain and manually flush cachelines (if required). This
 470                  * optimizes for the case when the gpu will dirty the data
 471                  * anyway again before the next pread happens. */
 472                 *needs_clflush = !cpu_cache_is_coherent(obj->base.dev,
 473                                                         obj->cache_level);
 474                 ret = i915_gem_object_wait_rendering(obj, true);
 475                 if (ret)
 476                         return ret;
 477
 478                 i915_gem_object_retire(obj);
 479         }
 480
 481         ret = i915_gem_object_get_pages(obj);
 482         if (ret)
 483                 return ret;
 484
 485         i915_gem_object_pin_pages(obj);
 486
 487         return ret;
 488 }
 489
 490 /* Per-page copy function for the shmem pread fastpath.
 491  * Flushes invalid cachelines before reading the target if
 492  * needs_clflush is set. */
 493 static int
 494 shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length,
 495                  char __user *user_data,
 496                  bool page_do_bit17_swizzling, bool needs_clflush)
 497 {
 498         char *vaddr;
 499         int ret;
 500
 501         if (unlikely(page_do_bit17_swizzling))
 502                 return -EINVAL;
 503
 504         vaddr = kmap_atomic(page);
 505         if (needs_clflush)
 506                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 507                                        page_length);
 508         ret = __copy_to_user_inatomic(user_data,
 509                                       vaddr + shmem_page_offset,
 510                                       page_length);
 511         kunmap_atomic(vaddr);
 512
 513         return ret ? -EFAULT : 0;
 514 }
 515
 516 static void
 517 shmem_clflush_swizzled_range(char *addr, unsigned long length,
 518                              bool swizzled)
 519 {
 520         if (unlikely(swizzled)) {
 521                 unsigned long start = (unsigned long) addr;
 522                 unsigned long end = (unsigned long) addr + length;
 523
 524                 /* For swizzling simply ensure that we always flush both
 525                  * channels. Lame, but simple and it works. Swizzled
 526                  * pwrite/pread is far from a hotpath - current userspace
 527                  * doesn't use it at all. */
 528                 start = round_down(start, 128);
 529                 end = round_up(end, 128);
 530
 531                 drm_clflush_virt_range((void *)start, end - start);
 532         } else {
 533                 drm_clflush_virt_range(addr, length);
 534         }
 535
 536 }
 537
 538 /* Only difference to the fast-path function is that this can handle bit17
 539  * and uses non-atomic copy and kmap functions. */
 540 static int
 541 shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length,
 542                  char __user *user_data,
 543                  bool page_do_bit17_swizzling, bool needs_clflush)
 544 {
 545         char *vaddr;
 546         int ret;
 547
 548         vaddr = kmap(page);
 549         if (needs_clflush)
 550                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 551                                              page_length,
 552                                              page_do_bit17_swizzling);
 553
 554         if (page_do_bit17_swizzling)
 555                 ret = __copy_to_user_swizzled(user_data,
 556                                               vaddr, shmem_page_offset,
 557                                               page_length);
 558         else
 559                 ret = __copy_to_user(user_data,
 560                                      vaddr + shmem_page_offset,
 561                                      page_length);
 562         kunmap(page);
 563
 564         return ret ? - EFAULT : 0;
 565 }
 566
 567 static int
 568 i915_gem_shmem_pread(struct drm_device *dev,
 569                      struct drm_i915_gem_object *obj,
 570                      struct drm_i915_gem_pread *args,
 571                      struct drm_file *file)
 572 {
 573         char __user *user_data;
 574         ssize_t remain;
 575         loff_t offset;
 576         int shmem_page_offset, page_length, ret = 0;
 577         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 578         int prefaulted = 0;
 579         int needs_clflush = 0;
 580         struct sg_page_iter sg_iter;
 581
 582         user_data = to_user_ptr(args->data_ptr);
 583         remain = args->size;
 584
 585         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 586
 587         ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush);
 588         if (ret)
 589                 return ret;
 590
 591         offset = args->offset;
 592
 593         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 594                          offset >> PAGE_SHIFT) {
 595                 struct page *page = sg_page_iter_page(&sg_iter);
 596
 597                 if (remain <= 0)
 598                         break;
 599
 600                 /* Operation in this page
 601                  *
 602                  * shmem_page_offset = offset within page in shmem file
 603                  * page_length = bytes to copy for this page
 604                  */
 605                 shmem_page_offset = offset_in_page(offset);
 606                 page_length = remain;
 607                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 608                         page_length = PAGE_SIZE - shmem_page_offset;
 609
 610                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 611                         (page_to_phys(page) & (1 << 17)) != 0;
 612
 613                 ret = shmem_pread_fast(page, shmem_page_offset, page_length,
 614                                        user_data, page_do_bit17_swizzling,
 615                                        needs_clflush);
 616                 if (ret == 0)
 617                         goto next_page;
 618
 619                 mutex_unlock(&dev->struct_mutex);
 620
 621                 if (likely(!i915.prefault_disable) && !prefaulted) {
 622                         ret = fault_in_multipages_writeable(user_data, remain);
 623                         /* Userspace is tricking us, but we've already clobbered
 624                          * its pages with the prefault and promised to write the
 625                          * data up to the first fault. Hence ignore any errors
 626                          * and just continue. */
 627                         (void)ret;
 628                         prefaulted = 1;
 629                 }
 630
 631                 ret = shmem_pread_slow(page, shmem_page_offset, page_length,
 632                                        user_data, page_do_bit17_swizzling,
 633                                        needs_clflush);
 634
 635                 mutex_lock(&dev->struct_mutex);
 636
 637                 if (ret)
 638                         goto out;
 639
 640 next_page:
 641                 remain -= page_length;
 642                 user_data += page_length;
 643                 offset += page_length;
 644         }
 645
 646 out:
 647         i915_gem_object_unpin_pages(obj);
 648
 649         return ret;
 650 }
 651
 652 /**
 653  * Reads data from the object referenced by handle.
 654  *
 655  * On error, the contents of *data are undefined.
 656  */
 657 int
 658 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 659                      struct drm_file *file)
 660 {
 661         struct drm_i915_gem_pread *args = data;
 662         struct drm_i915_gem_object *obj;
 663         int ret = 0;
 664
 665         if (args->size == 0)
 666                 return 0;
 667
 668         if (!access_ok(VERIFY_WRITE,
 669                        to_user_ptr(args->data_ptr),
 670                        args->size))
 671                 return -EFAULT;
 672
 673         ret = i915_mutex_lock_interruptible(dev);
 674         if (ret)
 675                 return ret;
 676
 677         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
 678         if (&obj->base == NULL) {
 679                 ret = -ENOENT;
 680                 goto unlock;
 681         }
 682
 683         /* Bounds check source.  */
 684         if (args->offset > obj->base.size ||
 685             args->size > obj->base.size - args->offset) {
 686                 ret = -EINVAL;
 687                 goto out;
 688         }
 689
 690         /* prime objects have no backing filp to GEM pread/pwrite
 691          * pages from.
 692          */
 693         if (!obj->base.filp) {
 694                 ret = -EINVAL;
 695                 goto out;
 696         }
 697
 698         trace_i915_gem_object_pread(obj, args->offset, args->size);
 699
 700         ret = i915_gem_shmem_pread(dev, obj, args, file);
 701
 702 out:
 703         drm_gem_object_unreference(&obj->base);
 704 unlock:
 705         mutex_unlock(&dev->struct_mutex);
 706         return ret;
 707 }
 708
 709 /* This is the fast write path which cannot handle
 710  * page faults in the source data
 711  */
 712
 713 static inline int
 714 fast_user_write(struct io_mapping *mapping,
 715                 loff_t page_base, int page_offset,
 716                 char __user *user_data,
 717                 int length)
 718 {
 719         void __iomem *vaddr_atomic;
 720         void *vaddr;
 721         unsigned long unwritten;
 722
 723         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 724         /* We can use the cpu mem copy function because this is X86. */
 725         vaddr = (void __force*)vaddr_atomic + page_offset;
 726         unwritten = __copy_from_user_inatomic_nocache(vaddr,
 727                                                       user_data, length);
 728         io_mapping_unmap_atomic(vaddr_atomic);
 729         return unwritten;
 730 }
 731
 732 /**
 733  * This is the fast pwrite path, where we copy the data directly from the
 734  * user into the GTT, uncached.
 735  */
 736 static int
 737 i915_gem_gtt_pwrite_fast(struct drm_device *dev,
 738                          struct drm_i915_gem_object *obj,
 739                          struct drm_i915_gem_pwrite *args,
 740                          struct drm_file *file)
 741 {
 742         struct drm_i915_private *dev_priv = dev->dev_private;
 743         ssize_t remain;
 744         loff_t offset, page_base;
 745         char __user *user_data;
 746         int page_offset, page_length, ret;
 747
 748         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK);
 749         if (ret)
 750                 goto out;
 751
 752         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 753         if (ret)
 754                 goto out_unpin;
 755
 756         ret = i915_gem_object_put_fence(obj);
 757         if (ret)
 758                 goto out_unpin;
 759
 760         user_data = to_user_ptr(args->data_ptr);
 761         remain = args->size;
 762
 763         offset = i915_gem_obj_ggtt_offset(obj) + args->offset;
 764
 765         while (remain > 0) {
 766                 /* Operation in this page
 767                  *
 768                  * page_base = page offset within aperture
 769                  * page_offset = offset within page
 770                  * page_length = bytes to copy for this page
 771                  */
 772                 page_base = offset & PAGE_MASK;
 773                 page_offset = offset_in_page(offset);
 774                 page_length = remain;
 775                 if ((page_offset + remain) > PAGE_SIZE)
 776                         page_length = PAGE_SIZE - page_offset;
 777
 778                 /* If we get a fault while copying data, then (presumably) our
 779                  * source page isn't available.  Return the error and we'll
 780                  * retry in the slow path.
 781                  */
 782                 if (fast_user_write(dev_priv->gtt.mappable, page_base,
 783                                     page_offset, user_data, page_length)) {
 784                         ret = -EFAULT;
 785                         goto out_unpin;
 786                 }
 787
 788                 remain -= page_length;
 789                 user_data += page_length;
 790                 offset += page_length;
 791         }
 792
 793 out_unpin:
 794         i915_gem_object_ggtt_unpin(obj);
 795 out:
 796         return ret;
 797 }
 798
 799 /* Per-page copy function for the shmem pwrite fastpath.
 800  * Flushes invalid cachelines before writing to the target if
 801  * needs_clflush_before is set and flushes out any written cachelines after
 802  * writing if needs_clflush is set. */
 803 static int
 804 shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length,
 805                   char __user *user_data,
 806                   bool page_do_bit17_swizzling,
 807                   bool needs_clflush_before,
 808                   bool needs_clflush_after)
 809 {
 810         char *vaddr;
 811         int ret;
 812
 813         if (unlikely(page_do_bit17_swizzling))
 814                 return -EINVAL;
 815
 816         vaddr = kmap_atomic(page);
 817         if (needs_clflush_before)
 818                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 819                                        page_length);
 820         ret = __copy_from_user_inatomic(vaddr + shmem_page_offset,
 821                                         user_data, page_length);
 822         if (needs_clflush_after)
 823                 drm_clflush_virt_range(vaddr + shmem_page_offset,
 824                                        page_length);
 825         kunmap_atomic(vaddr);
 826
 827         return ret ? -EFAULT : 0;
 828 }
 829
 830 /* Only difference to the fast-path function is that this can handle bit17
 831  * and uses non-atomic copy and kmap functions. */
 832 static int
 833 shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length,
 834                   char __user *user_data,
 835                   bool page_do_bit17_swizzling,
 836                   bool needs_clflush_before,
 837                   bool needs_clflush_after)
 838 {
 839         char *vaddr;
 840         int ret;
 841
 842         vaddr = kmap(page);
 843         if (unlikely(needs_clflush_before || page_do_bit17_swizzling))
 844                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 845                                              page_length,
 846                                              page_do_bit17_swizzling);
 847         if (page_do_bit17_swizzling)
 848                 ret = __copy_from_user_swizzled(vaddr, shmem_page_offset,
 849                                                 user_data,
 850                                                 page_length);
 851         else
 852                 ret = __copy_from_user(vaddr + shmem_page_offset,
 853                                        user_data,
 854                                        page_length);
 855         if (needs_clflush_after)
 856                 shmem_clflush_swizzled_range(vaddr + shmem_page_offset,
 857                                              page_length,
 858                                              page_do_bit17_swizzling);
 859         kunmap(page);
 860
 861         return ret ? -EFAULT : 0;
 862 }
 863
 864 static int
 865 i915_gem_shmem_pwrite(struct drm_device *dev,
 866                       struct drm_i915_gem_object *obj,
 867                       struct drm_i915_gem_pwrite *args,
 868                       struct drm_file *file)
 869 {
 870         ssize_t remain;
 871         loff_t offset;
 872         char __user *user_data;
 873         int shmem_page_offset, page_length, ret = 0;
 874         int obj_do_bit17_swizzling, page_do_bit17_swizzling;
 875         int hit_slowpath = 0;
 876         int needs_clflush_after = 0;
 877         int needs_clflush_before = 0;
 878         struct sg_page_iter sg_iter;
 879
 880         user_data = to_user_ptr(args->data_ptr);
 881         remain = args->size;
 882
 883         obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
 884
 885         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 886                 /* If we're not in the cpu write domain, set ourself into the gtt
 887                  * write domain and manually flush cachelines (if required). This
 888                  * optimizes for the case when the gpu will use the data
 889                  * right away and we therefore have to clflush anyway. */
 890                 needs_clflush_after = cpu_write_needs_clflush(obj);
 891                 ret = i915_gem_object_wait_rendering(obj, false);
 892                 if (ret)
 893                         return ret;
 894
 895                 i915_gem_object_retire(obj);
 896         }
 897         /* Same trick applies to invalidate partially written cachelines read
 898          * before writing. */
 899         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
 900                 needs_clflush_before =
 901                         !cpu_cache_is_coherent(dev, obj->cache_level);
 902
 903         ret = i915_gem_object_get_pages(obj);
 904         if (ret)
 905                 return ret;
 906
 907         i915_gem_object_pin_pages(obj);
 908
 909         offset = args->offset;
 910         obj->dirty = 1;
 911
 912         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 913                          offset >> PAGE_SHIFT) {
 914                 struct page *page = sg_page_iter_page(&sg_iter);
 915                 int partial_cacheline_write;
 916
 917                 if (remain <= 0)
 918                         break;
 919
 920                 /* Operation in this page
 921                  *
 922                  * shmem_page_offset = offset within page in shmem file
 923                  * page_length = bytes to copy for this page
 924                  */
 925                 shmem_page_offset = offset_in_page(offset);
 926
 927                 page_length = remain;
 928                 if ((shmem_page_offset + page_length) > PAGE_SIZE)
 929                         page_length = PAGE_SIZE - shmem_page_offset;
 930
 931                 /* If we don't overwrite a cacheline completely we need to be
 932                  * careful to have up-to-date data by first clflushing. Don't
 933                  * overcomplicate things and flush the entire patch. */
 934                 partial_cacheline_write = needs_clflush_before &&
 935                         ((shmem_page_offset | page_length)
 936                                 & (boot_cpu_data.x86_clflush_size - 1));
 937
 938                 page_do_bit17_swizzling = obj_do_bit17_swizzling &&
 939                         (page_to_phys(page) & (1 << 17)) != 0;
 940
 941                 ret = shmem_pwrite_fast(page, shmem_page_offset, page_length,
 942                                         user_data, page_do_bit17_swizzling,
 943                                         partial_cacheline_write,
 944                                         needs_clflush_after);
 945                 if (ret == 0)
 946                         goto next_page;
 947
 948                 hit_slowpath = 1;
 949                 mutex_unlock(&dev->struct_mutex);
 950                 ret = shmem_pwrite_slow(page, shmem_page_offset, page_length,
 951                                         user_data, page_do_bit17_swizzling,
 952                                         partial_cacheline_write,
 953                                         needs_clflush_after);
 954
 955                 mutex_lock(&dev->struct_mutex);
 956
 957                 if (ret)
 958                         goto out;
 959
 960 next_page:
 961                 remain -= page_length;
 962                 user_data += page_length;
 963                 offset += page_length;
 964         }
 965
 966 out:
 967         i915_gem_object_unpin_pages(obj);
 968
 969         if (hit_slowpath) {
 970                 /*
 971                  * Fixup: Flush cpu caches in case we didn't flush the dirty
 972                  * cachelines in-line while writing and the object moved
 973                  * out of the cpu write domain while we've dropped the lock.
 974                  */
 975                 if (!needs_clflush_after &&
 976                     obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
 977                         if (i915_gem_clflush_object(obj, obj->pin_display))
 978                                 i915_gem_chipset_flush(dev);
 979                 }
 980         }
 981
 982         if (needs_clflush_after)
 983                 i915_gem_chipset_flush(dev);
 984
 985         return ret;
 986 }
 987
 988 /**
 989  * Writes data to the object referenced by handle.
 990  *
 991  * On error, the contents of the buffer that were to be modified are undefined.
 992  */
 993 int
 994 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 995                       struct drm_file *file)
 996 {
 997         struct drm_i915_gem_pwrite *args = data;
 998         struct drm_i915_gem_object *obj;
 999         int ret;
1000
1001         if (args->size == 0)
1002                 return 0;
1003
1004         if (!access_ok(VERIFY_READ,
1005                        to_user_ptr(args->data_ptr),
1006                        args->size))
1007                 return -EFAULT;
1008
1009         if (likely(!i915.prefault_disable)) {
1010                 ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr),
1011                                                    args->size);
1012                 if (ret)
1013                         return -EFAULT;
1014         }
1015
1016         ret = i915_mutex_lock_interruptible(dev);
1017         if (ret)
1018                 return ret;
1019
1020         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1021         if (&obj->base == NULL) {
1022                 ret = -ENOENT;
1023                 goto unlock;
1024         }
1025
1026         /* Bounds check destination. */
1027         if (args->offset > obj->base.size ||
1028             args->size > obj->base.size - args->offset) {
1029                 ret = -EINVAL;
1030                 goto out;
1031         }
1032
1033         /* prime objects have no backing filp to GEM pread/pwrite
1034          * pages from.
1035          */
1036         if (!obj->base.filp) {
1037                 ret = -EINVAL;
1038                 goto out;
1039         }
1040
1041         trace_i915_gem_object_pwrite(obj, args->offset, args->size);
1042
1043         ret = -EFAULT;
1044         /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045          * it would end up going through the fenced access, and we'll get
1046          * different detiling behavior between reading and writing.
1047          * pread/pwrite currently are reading and writing from the CPU
1048          * perspective, requiring manual detiling by the client.
1049          */
1050         if (obj->phys_handle) {
1051                 ret = i915_gem_phys_pwrite(obj, args, file);
1052                 goto out;
1053         }
1054
1055         if (obj->tiling_mode == I915_TILING_NONE &&
1056             obj->base.write_domain != I915_GEM_DOMAIN_CPU &&
1057             cpu_write_needs_clflush(obj)) {
1058                 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1059                 /* Note that the gtt paths might fail with non-page-backed user
1060                  * pointers (e.g. gtt mappings when moving data between
1061                  * textures). Fallback to the shmem path in that case. */
1062         }
1063
1064         if (ret == -EFAULT || ret == -ENOSPC)
1065                 ret = i915_gem_shmem_pwrite(dev, obj, args, file);
1066
1067 out:
1068         drm_gem_object_unreference(&obj->base);
1069 unlock:
1070         mutex_unlock(&dev->struct_mutex);
1071         return ret;
1072 }
1073
1074 int
1075 i915_gem_check_wedge(struct i915_gpu_error *error,
1076                      bool interruptible)
1077 {
1078         if (i915_reset_in_progress(error)) {
1079                 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080                  * -EIO unconditionally for these. */
1081                 if (!interruptible)
1082                         return -EIO;
1083
1084                 /* Recovery complete, but the reset failed ... */
1085                 if (i915_terminally_wedged(error))
1086                         return -EIO;
1087
1088                 return -EAGAIN;
1089         }
1090
1091         return 0;
1092 }
1093
1094 /*
1095  * Compare seqno against outstanding lazy request. Emit a request if they are
1096  * equal.
1097  */
1098 int
1099 i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno)
1100 {
1101         int ret;
1102
1103         BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex));
1104
1105         ret = 0;
1106         if (seqno == ring->outstanding_lazy_seqno)
1107                 ret = i915_add_request(ring, NULL);
1108
1109         return ret;
1110 }
1111
1112 static void fake_irq(unsigned long data)
1113 {
1114         wake_up_process((struct task_struct *)data);
1115 }
1116
1117 static bool missed_irq(struct drm_i915_private *dev_priv,
1118                        struct intel_engine_cs *ring)
1119 {
1120         return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings);
1121 }
1122
1123 static bool can_wait_boost(struct drm_i915_file_private *file_priv)
1124 {
1125         if (file_priv == NULL)
1126                 return true;
1127
1128         return !atomic_xchg(&file_priv->rps_wait_boost, true);
1129 }
1130
1131 /**
1132  * __wait_seqno - wait until execution of seqno has finished
1133  * @ring: the ring expected to report seqno
1134  * @seqno: duh!
1135  * @reset_counter: reset sequence associated with the given seqno
1136  * @interruptible: do an interruptible wait (normally yes)
1137  * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1138  *
1139  * Note: It is of utmost importance that the passed in seqno and reset_counter
1140  * values have been read by the caller in an smp safe manner. Where read-side
1141  * locks are involved, it is sufficient to read the reset_counter before
1142  * unlocking the lock that protects the seqno. For lockless tricks, the
1143  * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1144  * inserted.
1145  *
1146  * Returns 0 if the seqno was found within the alloted time. Else returns the
1147  * errno with remaining time filled in timeout argument.
1148  */
1149 static int __wait_seqno(struct intel_engine_cs *ring, u32 seqno,
1150                         unsigned reset_counter,
1151                         bool interruptible,
1152                         s64 *timeout,
1153                         struct drm_i915_file_private *file_priv)
1154 {
1155         struct drm_device *dev = ring->dev;
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         const bool irq_test_in_progress =
1158                 ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring);
1159         DEFINE_WAIT(wait);
1160         unsigned long timeout_expire;
1161         s64 before, now;
1162         int ret;
1163
1164         WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled");
1165
1166         if (i915_seqno_passed(ring->get_seqno(ring, true), seqno))
1167                 return 0;
1168
1169         timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0;
1170
1171         if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) {
1172                 gen6_rps_boost(dev_priv);
1173                 if (file_priv)
1174                         mod_delayed_work(dev_priv->wq,
1175                                          &file_priv->mm.idle_work,
1176                                          msecs_to_jiffies(100));
1177         }
1178
1179         if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring)))
1180                 return -ENODEV;
1181
1182         /* Record current time in case interrupted by signal, or wedged */
1183         trace_i915_gem_request_wait_begin(ring, seqno);
1184         before = ktime_get_raw_ns();
1185         for (;;) {
1186                 struct timer_list timer;
1187
1188                 prepare_to_wait(&ring->irq_queue, &wait,
1189                                 interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
1190
1191                 /* We need to check whether any gpu reset happened in between
1192                  * the caller grabbing the seqno and now ... */
1193                 if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) {
1194                         /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195                          * is truely gone. */
1196                         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1197                         if (ret == 0)
1198                                 ret = -EAGAIN;
1199                         break;
1200                 }
1201
1202                 if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) {
1203                         ret = 0;
1204                         break;
1205                 }
1206
1207                 if (interruptible && signal_pending(current)) {
1208                         ret = -ERESTARTSYS;
1209                         break;
1210                 }
1211
1212                 if (timeout && time_after_eq(jiffies, timeout_expire)) {
1213                         ret = -ETIME;
1214                         break;
1215                 }
1216
1217                 timer.function = NULL;
1218                 if (timeout || missed_irq(dev_priv, ring)) {
1219                         unsigned long expire;
1220
1221                         setup_timer_on_stack(&timer, fake_irq, (unsigned long)current);
1222                         expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire;
1223                         mod_timer(&timer, expire);
1224                 }
1225
1226                 io_schedule();
1227
1228                 if (timer.function) {
1229                         del_singleshot_timer_sync(&timer);
1230                         destroy_timer_on_stack(&timer);
1231                 }
1232         }
1233         now = ktime_get_raw_ns();
1234         trace_i915_gem_request_wait_end(ring, seqno);
1235
1236         if (!irq_test_in_progress)
1237                 ring->irq_put(ring);
1238
1239         finish_wait(&ring->irq_queue, &wait);
1240
1241         if (timeout) {
1242                 s64 tres = *timeout - (now - before);
1243
1244                 *timeout = tres < 0 ? 0 : tres;
1245         }
1246
1247         return ret;
1248 }
1249
1250 /**
1251  * Waits for a sequence number to be signaled, and cleans up the
1252  * request and object lists appropriately for that event.
1253  */
1254 int
1255 i915_wait_seqno(struct intel_engine_cs *ring, uint32_t seqno)
1256 {
1257         struct drm_device *dev = ring->dev;
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         bool interruptible = dev_priv->mm.interruptible;
1260         int ret;
1261
1262         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1263         BUG_ON(seqno == 0);
1264
1265         ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible);
1266         if (ret)
1267                 return ret;
1268
1269         ret = i915_gem_check_olr(ring, seqno);
1270         if (ret)
1271                 return ret;
1272
1273         return __wait_seqno(ring, seqno,
1274                             atomic_read(&dev_priv->gpu_error.reset_counter),
1275                             interruptible, NULL, NULL);
1276 }
1277
1278 static int
1279 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj,
1280                                      struct intel_engine_cs *ring)
1281 {
1282         if (!obj->active)
1283                 return 0;
1284
1285         /* Manually manage the write flush as we may have not yet
1286          * retired the buffer.
1287          *
1288          * Note that the last_write_seqno is always the earlier of
1289          * the two (read/write) seqno, so if we haved successfully waited,
1290          * we know we have passed the last write.
1291          */
1292         obj->last_write_seqno = 0;
1293
1294         return 0;
1295 }
1296
1297 /**
1298  * Ensures that all rendering to the object has completed and the object is
1299  * safe to unbind from the GTT or access from the CPU.
1300  */
1301 static __must_check int
1302 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
1303                                bool readonly)
1304 {
1305         struct intel_engine_cs *ring = obj->ring;
1306         u32 seqno;
1307         int ret;
1308
1309         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1310         if (seqno == 0)
1311                 return 0;
1312
1313         ret = i915_wait_seqno(ring, seqno);
1314         if (ret)
1315                 return ret;
1316
1317         return i915_gem_object_wait_rendering__tail(obj, ring);
1318 }
1319
1320 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1321  * as the object state may change during this call.
1322  */
1323 static __must_check int
1324 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj,
1325                                             struct drm_i915_file_private *file_priv,
1326                                             bool readonly)
1327 {
1328         struct drm_device *dev = obj->base.dev;
1329         struct drm_i915_private *dev_priv = dev->dev_private;
1330         struct intel_engine_cs *ring = obj->ring;
1331         unsigned reset_counter;
1332         u32 seqno;
1333         int ret;
1334
1335         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1336         BUG_ON(!dev_priv->mm.interruptible);
1337
1338         seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno;
1339         if (seqno == 0)
1340                 return 0;
1341
1342         ret = i915_gem_check_wedge(&dev_priv->gpu_error, true);
1343         if (ret)
1344                 return ret;
1345
1346         ret = i915_gem_check_olr(ring, seqno);
1347         if (ret)
1348                 return ret;
1349
1350         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
1351         mutex_unlock(&dev->struct_mutex);
1352         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file_priv);
1353         mutex_lock(&dev->struct_mutex);
1354         if (ret)
1355                 return ret;
1356
1357         return i915_gem_object_wait_rendering__tail(obj, ring);
1358 }
1359
1360 /**
1361  * Called when user space prepares to use an object with the CPU, either
1362  * through the mmap ioctl's mapping or a GTT mapping.
1363  */
1364 int
1365 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1366                           struct drm_file *file)
1367 {
1368         struct drm_i915_gem_set_domain *args = data;
1369         struct drm_i915_gem_object *obj;
1370         uint32_t read_domains = args->read_domains;
1371         uint32_t write_domain = args->write_domain;
1372         int ret;
1373
1374         /* Only handle setting domains to types used by the CPU. */
1375         if (write_domain & I915_GEM_GPU_DOMAINS)
1376                 return -EINVAL;
1377
1378         if (read_domains & I915_GEM_GPU_DOMAINS)
1379                 return -EINVAL;
1380
1381         /* Having something in the write domain implies it's in the read
1382          * domain, and only that read domain.  Enforce that in the request.
1383          */
1384         if (write_domain != 0 && read_domains != write_domain)
1385                 return -EINVAL;
1386
1387         ret = i915_mutex_lock_interruptible(dev);
1388         if (ret)
1389                 return ret;
1390
1391         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1392         if (&obj->base == NULL) {
1393                 ret = -ENOENT;
1394                 goto unlock;
1395         }
1396
1397         /* Try to flush the object off the GPU without holding the lock.
1398          * We will repeat the flush holding the lock in the normal manner
1399          * to catch cases where we are gazumped.
1400          */
1401         ret = i915_gem_object_wait_rendering__nonblocking(obj,
1402                                                           file->driver_priv,
1403                                                           !write_domain);
1404         if (ret)
1405                 goto unref;
1406
1407         if (read_domains & I915_GEM_DOMAIN_GTT) {
1408                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1409
1410                 /* Silently promote "you're not bound, there was nothing to do"
1411                  * to success, since the client was just asking us to
1412                  * make sure everything was done.
1413                  */
1414                 if (ret == -EINVAL)
1415                         ret = 0;
1416         } else {
1417                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1418         }
1419
1420 unref:
1421         drm_gem_object_unreference(&obj->base);
1422 unlock:
1423         mutex_unlock(&dev->struct_mutex);
1424         return ret;
1425 }
1426
1427 /**
1428  * Called when user space has done writes to this buffer
1429  */
1430 int
1431 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1432                          struct drm_file *file)
1433 {
1434         struct drm_i915_gem_sw_finish *args = data;
1435         struct drm_i915_gem_object *obj;
1436         int ret = 0;
1437
1438         ret = i915_mutex_lock_interruptible(dev);
1439         if (ret)
1440                 return ret;
1441
1442         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
1443         if (&obj->base == NULL) {
1444                 ret = -ENOENT;
1445                 goto unlock;
1446         }
1447
1448         /* Pinned buffers may be scanout, so flush the cache */
1449         if (obj->pin_display)
1450                 i915_gem_object_flush_cpu_write_domain(obj, true);
1451
1452         drm_gem_object_unreference(&obj->base);
1453 unlock:
1454         mutex_unlock(&dev->struct_mutex);
1455         return ret;
1456 }
1457
1458 /**
1459  * Maps the contents of an object, returning the address it is mapped
1460  * into.
1461  *
1462  * While the mapping holds a reference on the contents of the object, it doesn't
1463  * imply a ref on the object itself.
1464  */
1465 int
1466 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1467                     struct drm_file *file)
1468 {
1469         struct drm_i915_gem_mmap *args = data;
1470         struct drm_gem_object *obj;
1471         unsigned long addr;
1472
1473         obj = drm_gem_object_lookup(dev, file, args->handle);
1474         if (obj == NULL)
1475                 return -ENOENT;
1476
1477         /* prime objects have no backing filp to GEM mmap
1478          * pages from.
1479          */
1480         if (!obj->filp) {
1481                 drm_gem_object_unreference_unlocked(obj);
1482                 return -EINVAL;
1483         }
1484
1485         addr = vm_mmap(obj->filp, 0, args->size,
1486                        PROT_READ | PROT_WRITE, MAP_SHARED,
1487                        args->offset);
1488         drm_gem_object_unreference_unlocked(obj);
1489         if (IS_ERR((void *)addr))
1490                 return addr;
1491
1492         args->addr_ptr = (uint64_t) addr;
1493
1494         return 0;
1495 }
1496
1497 /**
1498  * i915_gem_fault - fault a page into the GTT
1499  * vma: VMA in question
1500  * vmf: fault info
1501  *
1502  * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1503  * from userspace.  The fault handler takes care of binding the object to
1504  * the GTT (if needed), allocating and programming a fence register (again,
1505  * only if needed based on whether the old reg is still valid or the object
1506  * is tiled) and inserting a new PTE into the faulting process.
1507  *
1508  * Note that the faulting process may involve evicting existing objects
1509  * from the GTT and/or fence registers to make room.  So performance may
1510  * suffer if the GTT working set is large or there are few fence registers
1511  * left.
1512  */
1513 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1514 {
1515         struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1516         struct drm_device *dev = obj->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         pgoff_t page_offset;
1519         unsigned long pfn;
1520         int ret = 0;
1521         bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1522
1523         intel_runtime_pm_get(dev_priv);
1524
1525         /* We don't use vmf->pgoff since that has the fake offset */
1526         page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1527                 PAGE_SHIFT;
1528
1529         ret = i915_mutex_lock_interruptible(dev);
1530         if (ret)
1531                 goto out;
1532
1533         trace_i915_gem_object_fault(obj, page_offset, true, write);
1534
1535         /* Try to flush the object off the GPU first without holding the lock.
1536          * Upon reacquiring the lock, we will perform our sanity checks and then
1537          * repeat the flush holding the lock in the normal manner to catch cases
1538          * where we are gazumped.
1539          */
1540         ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write);
1541         if (ret)
1542                 goto unlock;
1543
1544         /* Access to snoopable pages through the GTT is incoherent. */
1545         if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) {
1546                 ret = -EFAULT;
1547                 goto unlock;
1548         }
1549
1550         /* Now bind it into the GTT if needed */
1551         ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE);
1552         if (ret)
1553                 goto unlock;
1554
1555         ret = i915_gem_object_set_to_gtt_domain(obj, write);
1556         if (ret)
1557                 goto unpin;
1558
1559         ret = i915_gem_object_get_fence(obj);
1560         if (ret)
1561                 goto unpin;
1562
1563         /* Finally, remap it using the new GTT offset */
1564         pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj);
1565         pfn >>= PAGE_SHIFT;
1566
1567         if (!obj->fault_mappable) {
1568                 unsigned long size = min_t(unsigned long,
1569                                            vma->vm_end - vma->vm_start,
1570                                            obj->base.size);
1571                 int i;
1572
1573                 for (i = 0; i < size >> PAGE_SHIFT; i++) {
1574                         ret = vm_insert_pfn(vma,
1575                                             (unsigned long)vma->vm_start + i * PAGE_SIZE,
1576                                             pfn + i);
1577                         if (ret)
1578                                 break;
1579                 }
1580
1581                 obj->fault_mappable = true;
1582         } else
1583                 ret = vm_insert_pfn(vma,
1584                                     (unsigned long)vmf->virtual_address,
1585                                     pfn + page_offset);
1586 unpin:
1587         i915_gem_object_ggtt_unpin(obj);
1588 unlock:
1589         mutex_unlock(&dev->struct_mutex);
1590 out:
1591         switch (ret) {
1592         case -EIO:
1593                 /* If this -EIO is due to a gpu hang, give the reset code a
1594                  * chance to clean up the mess. Otherwise return the proper
1595                  * SIGBUS. */
1596                 if (i915_terminally_wedged(&dev_priv->gpu_error)) {
1597                         ret = VM_FAULT_SIGBUS;
1598                         break;
1599                 }
1600         case -EAGAIN:
1601                 /*
1602                  * EAGAIN means the gpu is hung and we'll wait for the error
1603                  * handler to reset everything when re-faulting in
1604                  * i915_mutex_lock_interruptible.
1605                  */
1606         case 0:
1607         case -ERESTARTSYS:
1608         case -EINTR:
1609         case -EBUSY:
1610                 /*
1611                  * EBUSY is ok: this just means that another thread
1612                  * already did the job.
1613                  */
1614                 ret = VM_FAULT_NOPAGE;
1615                 break;
1616         case -ENOMEM:
1617                 ret = VM_FAULT_OOM;
1618                 break;
1619         case -ENOSPC:
1620         case -EFAULT:
1621                 ret = VM_FAULT_SIGBUS;
1622                 break;
1623         default:
1624                 WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret);
1625                 ret = VM_FAULT_SIGBUS;
1626                 break;
1627         }
1628
1629         intel_runtime_pm_put(dev_priv);
1630         return ret;
1631 }
1632
1633 /**
1634  * i915_gem_release_mmap - remove physical page mappings
1635  * @obj: obj in question
1636  *
1637  * Preserve the reservation of the mmapping with the DRM core code, but
1638  * relinquish ownership of the pages back to the system.
1639  *
1640  * It is vital that we remove the page mapping if we have mapped a tiled
1641  * object through the GTT and then lose the fence register due to
1642  * resource pressure. Similarly if the object has been moved out of the
1643  * aperture, than pages mapped into userspace must be revoked. Removing the
1644  * mapping will then trigger a page fault on the next user access, allowing
1645  * fixup by i915_gem_fault().
1646  */
1647 void
1648 i915_gem_release_mmap(struct drm_i915_gem_object *obj)
1649 {
1650         if (!obj->fault_mappable)
1651                 return;
1652
1653         drm_vma_node_unmap(&obj->base.vma_node,
1654                            obj->base.dev->anon_inode->i_mapping);
1655         obj->fault_mappable = false;
1656 }
1657
1658 void
1659 i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv)
1660 {
1661         struct drm_i915_gem_object *obj;
1662
1663         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1664                 i915_gem_release_mmap(obj);
1665 }
1666
1667 uint32_t
1668 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
1669 {
1670         uint32_t gtt_size;
1671
1672         if (INTEL_INFO(dev)->gen >= 4 ||
1673             tiling_mode == I915_TILING_NONE)
1674                 return size;
1675
1676         /* Previous chips need a power-of-two fence region when tiling */
1677         if (INTEL_INFO(dev)->gen == 3)
1678                 gtt_size = 1024*1024;
1679         else
1680                 gtt_size = 512*1024;
1681
1682         while (gtt_size < size)
1683                 gtt_size <<= 1;
1684
1685         return gtt_size;
1686 }
1687
1688 /**
1689  * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1690  * @obj: object to check
1691  *
1692  * Return the required GTT alignment for an object, taking into account
1693  * potential fence register mapping.
1694  */
1695 uint32_t
1696 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1697                            int tiling_mode, bool fenced)
1698 {
1699         /*
1700          * Minimum alignment is 4k (GTT page size), but might be greater
1701          * if a fence register is needed for the object.
1702          */
1703         if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) ||
1704             tiling_mode == I915_TILING_NONE)
1705                 return 4096;
1706
1707         /*
1708          * Previous chips need to be aligned to the size of the smallest
1709          * fence register that can contain the object.
1710          */
1711         return i915_gem_get_gtt_size(dev, size, tiling_mode);
1712 }
1713
1714 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
1715 {
1716         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1717         int ret;
1718
1719         if (drm_vma_node_has_offset(&obj->base.vma_node))
1720                 return 0;
1721
1722         dev_priv->mm.shrinker_no_lock_stealing = true;
1723
1724         ret = drm_gem_create_mmap_offset(&obj->base);
1725         if (ret != -ENOSPC)
1726                 goto out;
1727
1728         /* Badly fragmented mmap space? The only way we can recover
1729          * space is by destroying unwanted objects. We can't randomly release
1730          * mmap_offsets as userspace expects them to be persistent for the
1731          * lifetime of the objects. The closest we can is to release the
1732          * offsets on purgeable objects by truncating it and marking it purged,
1733          * which prevents userspace from ever using that object again.
1734          */
1735         i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT);
1736         ret = drm_gem_create_mmap_offset(&obj->base);
1737         if (ret != -ENOSPC)
1738                 goto out;
1739
1740         i915_gem_shrink_all(dev_priv);
1741         ret = drm_gem_create_mmap_offset(&obj->base);
1742 out:
1743         dev_priv->mm.shrinker_no_lock_stealing = false;
1744
1745         return ret;
1746 }
1747
1748 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj)
1749 {
1750         drm_gem_free_mmap_offset(&obj->base);
1751 }
1752
1753 int
1754 i915_gem_mmap_gtt(struct drm_file *file,
1755                   struct drm_device *dev,
1756                   uint32_t handle,
1757                   uint64_t *offset)
1758 {
1759         struct drm_i915_private *dev_priv = dev->dev_private;
1760         struct drm_i915_gem_object *obj;
1761         int ret;
1762
1763         ret = i915_mutex_lock_interruptible(dev);
1764         if (ret)
1765                 return ret;
1766
1767         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
1768         if (&obj->base == NULL) {
1769                 ret = -ENOENT;
1770                 goto unlock;
1771         }
1772
1773         if (obj->base.size > dev_priv->gtt.mappable_end) {
1774                 ret = -E2BIG;
1775                 goto out;
1776         }
1777
1778         if (obj->madv != I915_MADV_WILLNEED) {
1779                 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1780                 ret = -EFAULT;
1781                 goto out;
1782         }
1783
1784         ret = i915_gem_object_create_mmap_offset(obj);
1785         if (ret)
1786                 goto out;
1787
1788         *offset = drm_vma_node_offset_addr(&obj->base.vma_node);
1789
1790 out:
1791         drm_gem_object_unreference(&obj->base);
1792 unlock:
1793         mutex_unlock(&dev->struct_mutex);
1794         return ret;
1795 }
1796
1797 /**
1798  * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1799  * @dev: DRM device
1800  * @data: GTT mapping ioctl data
1801  * @file: GEM object info
1802  *
1803  * Simply returns the fake offset to userspace so it can mmap it.
1804  * The mmap call will end up in drm_gem_mmap(), which will set things
1805  * up so we can get faults in the handler above.
1806  *
1807  * The fault handler will take care of binding the object into the GTT
1808  * (since it may have been evicted to make room for something), allocating
1809  * a fence register, and mapping the appropriate aperture address into
1810  * userspace.
1811  */
1812 int
1813 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1814                         struct drm_file *file)
1815 {
1816         struct drm_i915_gem_mmap_gtt *args = data;
1817
1818         return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1819 }
1820
1821 static inline int
1822 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
1823 {
1824         return obj->madv == I915_MADV_DONTNEED;
1825 }
1826
1827 /* Immediately discard the backing storage */
1828 static void
1829 i915_gem_object_truncate(struct drm_i915_gem_object *obj)
1830 {
1831         i915_gem_object_free_mmap_offset(obj);
1832
1833         if (obj->base.filp == NULL)
1834                 return;
1835
1836         /* Our goal here is to return as much of the memory as
1837          * is possible back to the system as we are called from OOM.
1838          * To do this we must instruct the shmfs to drop all of its
1839          * backing pages, *now*.
1840          */
1841         shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1);
1842         obj->madv = __I915_MADV_PURGED;
1843 }
1844
1845 /* Try to discard unwanted pages */
1846 static void
1847 i915_gem_object_invalidate(struct drm_i915_gem_object *obj)
1848 {
1849         struct address_space *mapping;
1850
1851         switch (obj->madv) {
1852         case I915_MADV_DONTNEED:
1853                 i915_gem_object_truncate(obj);
1854         case __I915_MADV_PURGED:
1855                 return;
1856         }
1857
1858         if (obj->base.filp == NULL)
1859                 return;
1860
1861         mapping = file_inode(obj->base.filp)->i_mapping,
1862         invalidate_mapping_pages(mapping, 0, (loff_t)-1);
1863 }
1864
1865 static void
1866 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
1867 {
1868         struct sg_page_iter sg_iter;
1869         int ret;
1870
1871         BUG_ON(obj->madv == __I915_MADV_PURGED);
1872
1873         ret = i915_gem_object_set_to_cpu_domain(obj, true);
1874         if (ret) {
1875                 /* In the event of a disaster, abandon all caches and
1876                  * hope for the best.
1877                  */
1878                 WARN_ON(ret != -EIO);
1879                 i915_gem_clflush_object(obj, true);
1880                 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
1881         }
1882
1883         if (i915_gem_object_needs_bit17_swizzle(obj))
1884                 i915_gem_object_save_bit_17_swizzle(obj);
1885
1886         if (obj->madv == I915_MADV_DONTNEED)
1887                 obj->dirty = 0;
1888
1889         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
1890                 struct page *page = sg_page_iter_page(&sg_iter);
1891
1892                 if (obj->dirty)
1893                         set_page_dirty(page);
1894
1895                 if (obj->madv == I915_MADV_WILLNEED)
1896                         mark_page_accessed(page);
1897
1898                 page_cache_release(page);
1899         }
1900         obj->dirty = 0;
1901
1902         sg_free_table(obj->pages);
1903         kfree(obj->pages);
1904 }
1905
1906 int
1907 i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
1908 {
1909         const struct drm_i915_gem_object_ops *ops = obj->ops;
1910
1911         if (obj->pages == NULL)
1912                 return 0;
1913
1914         if (obj->pages_pin_count)
1915                 return -EBUSY;
1916
1917         BUG_ON(i915_gem_obj_bound_any(obj));
1918
1919         /* ->put_pages might need to allocate memory for the bit17 swizzle
1920          * array, hence protect them from being reaped by removing them from gtt
1921          * lists early. */
1922         list_del(&obj->global_list);
1923
1924         ops->put_pages(obj);
1925         obj->pages = NULL;
1926
1927         i915_gem_object_invalidate(obj);
1928
1929         return 0;
1930 }
1931
1932 static unsigned long
1933 __i915_gem_shrink(struct drm_i915_private *dev_priv, long target,
1934                   bool purgeable_only)
1935 {
1936         struct list_head still_in_list;
1937         struct drm_i915_gem_object *obj;
1938         unsigned long count = 0;
1939
1940         /*
1941          * As we may completely rewrite the (un)bound list whilst unbinding
1942          * (due to retiring requests) we have to strictly process only
1943          * one element of the list at the time, and recheck the list
1944          * on every iteration.
1945          *
1946          * In particular, we must hold a reference whilst removing the
1947          * object as we may end up waiting for and/or retiring the objects.
1948          * This might release the final reference (held by the active list)
1949          * and result in the object being freed from under us. This is
1950          * similar to the precautions the eviction code must take whilst
1951          * removing objects.
1952          *
1953          * Also note that although these lists do not hold a reference to
1954          * the object we can safely grab one here: The final object
1955          * unreferencing and the bound_list are both protected by the
1956          * dev->struct_mutex and so we won't ever be able to observe an
1957          * object on the bound_list with a reference count equals 0.
1958          */
1959         INIT_LIST_HEAD(&still_in_list);
1960         while (count < target && !list_empty(&dev_priv->mm.unbound_list)) {
1961                 obj = list_first_entry(&dev_priv->mm.unbound_list,
1962                                        typeof(*obj), global_list);
1963                 list_move_tail(&obj->global_list, &still_in_list);
1964
1965                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1966                         continue;
1967
1968                 drm_gem_object_reference(&obj->base);
1969
1970                 if (i915_gem_object_put_pages(obj) == 0)
1971                         count += obj->base.size >> PAGE_SHIFT;
1972
1973                 drm_gem_object_unreference(&obj->base);
1974         }
1975         list_splice(&still_in_list, &dev_priv->mm.unbound_list);
1976
1977         INIT_LIST_HEAD(&still_in_list);
1978         while (count < target && !list_empty(&dev_priv->mm.bound_list)) {
1979                 struct i915_vma *vma, *v;
1980
1981                 obj = list_first_entry(&dev_priv->mm.bound_list,
1982                                        typeof(*obj), global_list);
1983                 list_move_tail(&obj->global_list, &still_in_list);
1984
1985                 if (!i915_gem_object_is_purgeable(obj) && purgeable_only)
1986                         continue;
1987
1988                 drm_gem_object_reference(&obj->base);
1989
1990                 list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link)
1991                         if (i915_vma_unbind(vma))
1992                                 break;
1993
1994                 if (i915_gem_object_put_pages(obj) == 0)
1995                         count += obj->base.size >> PAGE_SHIFT;
1996
1997                 drm_gem_object_unreference(&obj->base);
1998         }
1999         list_splice(&still_in_list, &dev_priv->mm.bound_list);
2000
2001         return count;
2002 }
2003
2004 static unsigned long
2005 i915_gem_purge(struct drm_i915_private *dev_priv, long target)
2006 {
2007         return __i915_gem_shrink(dev_priv, target, true);
2008 }
2009
2010 static unsigned long
2011 i915_gem_shrink_all(struct drm_i915_private *dev_priv)
2012 {
2013         i915_gem_evict_everything(dev_priv->dev);
2014         return __i915_gem_shrink(dev_priv, LONG_MAX, false);
2015 }
2016
2017 static int
2018 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
2019 {
2020         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2021         int page_count, i;
2022         struct address_space *mapping;
2023         struct sg_table *st;
2024         struct scatterlist *sg;
2025         struct sg_page_iter sg_iter;
2026         struct page *page;
2027         unsigned long last_pfn = 0;     /* suppress gcc warning */
2028         gfp_t gfp;
2029
2030         /* Assert that the object is not currently in any GPU domain. As it
2031          * wasn't in the GTT, there shouldn't be any way it could have been in
2032          * a GPU cache
2033          */
2034         BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2035         BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
2036
2037         st = kmalloc(sizeof(*st), GFP_KERNEL);
2038         if (st == NULL)
2039                 return -ENOMEM;
2040
2041         page_count = obj->base.size / PAGE_SIZE;
2042         if (sg_alloc_table(st, page_count, GFP_KERNEL)) {
2043                 kfree(st);
2044                 return -ENOMEM;
2045         }
2046
2047         /* Get the list of pages out of our struct file.  They'll be pinned
2048          * at this point until we release them.
2049          *
2050          * Fail silently without starting the shrinker
2051          */
2052         mapping = file_inode(obj->base.filp)->i_mapping;
2053         gfp = mapping_gfp_mask(mapping);
2054         gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD;
2055         gfp &= ~(__GFP_IO | __GFP_WAIT);
2056         sg = st->sgl;
2057         st->nents = 0;
2058         for (i = 0; i < page_count; i++) {
2059                 page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2060                 if (IS_ERR(page)) {
2061                         i915_gem_purge(dev_priv, page_count);
2062                         page = shmem_read_mapping_page_gfp(mapping, i, gfp);
2063                 }
2064                 if (IS_ERR(page)) {
2065                         /* We've tried hard to allocate the memory by reaping
2066                          * our own buffer, now let the real VM do its job and
2067                          * go down in flames if truly OOM.
2068                          */
2069                         i915_gem_shrink_all(dev_priv);
2070                         page = shmem_read_mapping_page(mapping, i);
2071                         if (IS_ERR(page))
2072                                 goto err_pages;
2073                 }
2074 #ifdef CONFIG_SWIOTLB
2075                 if (swiotlb_nr_tbl()) {
2076                         st->nents++;
2077                         sg_set_page(sg, page, PAGE_SIZE, 0);
2078                         sg = sg_next(sg);
2079                         continue;
2080                 }
2081 #endif
2082                 if (!i || page_to_pfn(page) != last_pfn + 1) {
2083                         if (i)
2084                                 sg = sg_next(sg);
2085                         st->nents++;
2086                         sg_set_page(sg, page, PAGE_SIZE, 0);
2087                 } else {
2088                         sg->length += PAGE_SIZE;
2089                 }
2090                 last_pfn = page_to_pfn(page);
2091
2092                 /* Check that the i965g/gm workaround works. */
2093                 WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL));
2094         }
2095 #ifdef CONFIG_SWIOTLB
2096         if (!swiotlb_nr_tbl())
2097 #endif
2098                 sg_mark_end(sg);
2099         obj->pages = st;
2100
2101         if (i915_gem_object_needs_bit17_swizzle(obj))
2102                 i915_gem_object_do_bit_17_swizzle(obj);
2103
2104         return 0;
2105
2106 err_pages:
2107         sg_mark_end(sg);
2108         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0)
2109                 page_cache_release(sg_page_iter_page(&sg_iter));
2110         sg_free_table(st);
2111         kfree(st);
2112
2113         /* shmemfs first checks if there is enough memory to allocate the page
2114          * and reports ENOSPC should there be insufficient, along with the usual
2115          * ENOMEM for a genuine allocation failure.
2116          *
2117          * We use ENOSPC in our driver to mean that we have run out of aperture
2118          * space and so want to translate the error from shmemfs back to our
2119          * usual understanding of ENOMEM.
2120          */
2121         if (PTR_ERR(page) == -ENOSPC)
2122                 return -ENOMEM;
2123         else
2124                 return PTR_ERR(page);
2125 }
2126
2127 /* Ensure that the associated pages are gathered from the backing storage
2128  * and pinned into our object. i915_gem_object_get_pages() may be called
2129  * multiple times before they are released by a single call to
2130  * i915_gem_object_put_pages() - once the pages are no longer referenced
2131  * either as a result of memory pressure (reaping pages under the shrinker)
2132  * or as the object is itself released.
2133  */
2134 int
2135 i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
2136 {
2137         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2138         const struct drm_i915_gem_object_ops *ops = obj->ops;
2139         int ret;
2140
2141         if (obj->pages)
2142                 return 0;
2143
2144         if (obj->madv != I915_MADV_WILLNEED) {
2145                 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2146                 return -EFAULT;
2147         }
2148
2149         BUG_ON(obj->pages_pin_count);
2150
2151         ret = ops->get_pages(obj);
2152         if (ret)
2153                 return ret;
2154
2155         list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2156         return 0;
2157 }
2158
2159 static void
2160 i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
2161                                struct intel_engine_cs *ring)
2162 {
2163         u32 seqno = intel_ring_get_seqno(ring);
2164
2165         BUG_ON(ring == NULL);
2166         if (obj->ring != ring && obj->last_write_seqno) {
2167                 /* Keep the seqno relative to the current ring */
2168                 obj->last_write_seqno = seqno;
2169         }
2170         obj->ring = ring;
2171
2172         /* Add a reference if we're newly entering the active list. */
2173         if (!obj->active) {
2174                 drm_gem_object_reference(&obj->base);
2175                 obj->active = 1;
2176         }
2177
2178         list_move_tail(&obj->ring_list, &ring->active_list);
2179
2180         obj->last_read_seqno = seqno;
2181 }
2182
2183 void i915_vma_move_to_active(struct i915_vma *vma,
2184                              struct intel_engine_cs *ring)
2185 {
2186         list_move_tail(&vma->mm_list, &vma->vm->active_list);
2187         return i915_gem_object_move_to_active(vma->obj, ring);
2188 }
2189
2190 static void
2191 i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
2192 {
2193         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2194         struct i915_address_space *vm;
2195         struct i915_vma *vma;
2196
2197         BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
2198         BUG_ON(!obj->active);
2199
2200         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2201                 vma = i915_gem_obj_to_vma(obj, vm);
2202                 if (vma && !list_empty(&vma->mm_list))
2203                         list_move_tail(&vma->mm_list, &vm->inactive_list);
2204         }
2205
2206         intel_fb_obj_flush(obj, true);
2207
2208         list_del_init(&obj->ring_list);
2209         obj->ring = NULL;
2210
2211         obj->last_read_seqno = 0;
2212         obj->last_write_seqno = 0;
2213         obj->base.write_domain = 0;
2214
2215         obj->last_fenced_seqno = 0;
2216
2217         obj->active = 0;
2218         drm_gem_object_unreference(&obj->base);
2219
2220         WARN_ON(i915_verify_lists(dev));
2221 }
2222
2223 static void
2224 i915_gem_object_retire(struct drm_i915_gem_object *obj)
2225 {
2226         struct intel_engine_cs *ring = obj->ring;
2227
2228         if (ring == NULL)
2229                 return;
2230
2231         if (i915_seqno_passed(ring->get_seqno(ring, true),
2232                               obj->last_read_seqno))
2233                 i915_gem_object_move_to_inactive(obj);
2234 }
2235
2236 static int
2237 i915_gem_init_seqno(struct drm_device *dev, u32 seqno)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_engine_cs *ring;
2241         int ret, i, j;
2242
2243         /* Carefully retire all requests without writing to the rings */
2244         for_each_ring(ring, dev_priv, i) {
2245                 ret = intel_ring_idle(ring);
2246                 if (ret)
2247                         return ret;
2248         }
2249         i915_gem_retire_requests(dev);
2250
2251         /* Finally reset hw state */
2252         for_each_ring(ring, dev_priv, i) {
2253                 intel_ring_init_seqno(ring, seqno);
2254
2255                 for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++)
2256                         ring->semaphore.sync_seqno[j] = 0;
2257         }
2258
2259         return 0;
2260 }
2261
2262 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno)
2263 {
2264         struct drm_i915_private *dev_priv = dev->dev_private;
2265         int ret;
2266
2267         if (seqno == 0)
2268                 return -EINVAL;
2269
2270         /* HWS page needs to be set less than what we
2271          * will inject to ring
2272          */
2273         ret = i915_gem_init_seqno(dev, seqno - 1);
2274         if (ret)
2275                 return ret;
2276
2277         /* Carefully set the last_seqno value so that wrap
2278          * detection still works
2279          */
2280         dev_priv->next_seqno = seqno;
2281         dev_priv->last_seqno = seqno - 1;
2282         if (dev_priv->last_seqno == 0)
2283                 dev_priv->last_seqno--;
2284
2285         return 0;
2286 }
2287
2288 int
2289 i915_gem_get_seqno(struct drm_device *dev, u32 *seqno)
2290 {
2291         struct drm_i915_private *dev_priv = dev->dev_private;
2292
2293         /* reserve 0 for non-seqno */
2294         if (dev_priv->next_seqno == 0) {
2295                 int ret = i915_gem_init_seqno(dev, 0);
2296                 if (ret)
2297                         return ret;
2298
2299                 dev_priv->next_seqno = 1;
2300         }
2301
2302         *seqno = dev_priv->last_seqno = dev_priv->next_seqno++;
2303         return 0;
2304 }
2305
2306 int __i915_add_request(struct intel_engine_cs *ring,
2307                        struct drm_file *file,
2308                        struct drm_i915_gem_object *obj,
2309                        u32 *out_seqno)
2310 {
2311         struct drm_i915_private *dev_priv = ring->dev->dev_private;
2312         struct drm_i915_gem_request *request;
2313         struct intel_ringbuffer *ringbuf;
2314         u32 request_ring_position, request_start;
2315         int ret;
2316
2317         request = ring->preallocated_lazy_request;
2318         if (WARN_ON(request == NULL))
2319                 return -ENOMEM;
2320
2321         if (i915.enable_execlists) {
2322                 struct intel_context *ctx = request->ctx;
2323                 ringbuf = ctx->engine[ring->id].ringbuf;
2324         } else
2325                 ringbuf = ring->buffer;
2326
2327         request_start = intel_ring_get_tail(ringbuf);
2328         /*
2329          * Emit any outstanding flushes - execbuf can fail to emit the flush
2330          * after having emitted the batchbuffer command. Hence we need to fix
2331          * things up similar to emitting the lazy request. The difference here
2332          * is that the flush _must_ happen before the next request, no matter
2333          * what.
2334          */
2335         if (i915.enable_execlists) {
2336                 ret = logical_ring_flush_all_caches(ringbuf);
2337                 if (ret)
2338                         return ret;
2339         } else {
2340                 ret = intel_ring_flush_all_caches(ring);
2341                 if (ret)
2342                         return ret;
2343         }
2344
2345         /* Record the position of the start of the request so that
2346          * should we detect the updated seqno part-way through the
2347          * GPU processing the request, we never over-estimate the
2348          * position of the head.
2349          */
2350         request_ring_position = intel_ring_get_tail(ringbuf);
2351
2352         if (i915.enable_execlists) {
2353                 ret = ring->emit_request(ringbuf);
2354                 if (ret)
2355                         return ret;
2356         } else {
2357                 ret = ring->add_request(ring);
2358                 if (ret)
2359                         return ret;
2360         }
2361
2362         request->seqno = intel_ring_get_seqno(ring);
2363         request->ring = ring;
2364         request->head = request_start;
2365         request->tail = request_ring_position;
2366
2367         /* Whilst this request exists, batch_obj will be on the
2368          * active_list, and so will hold the active reference. Only when this
2369          * request is retired will the the batch_obj be moved onto the
2370          * inactive_list and lose its active reference. Hence we do not need
2371          * to explicitly hold another reference here.
2372          */
2373         request->batch_obj = obj;
2374
2375         if (!i915.enable_execlists) {
2376                 /* Hold a reference to the current context so that we can inspect
2377                  * it later in case a hangcheck error event fires.
2378                  */
2379                 request->ctx = ring->last_context;
2380                 if (request->ctx)
2381                         i915_gem_context_reference(request->ctx);
2382         }
2383
2384         request->emitted_jiffies = jiffies;
2385         list_add_tail(&request->list, &ring->request_list);
2386         request->file_priv = NULL;
2387
2388         if (file) {
2389                 struct drm_i915_file_private *file_priv = file->driver_priv;
2390
2391                 spin_lock(&file_priv->mm.lock);
2392                 request->file_priv = file_priv;
2393                 list_add_tail(&request->client_list,
2394                               &file_priv->mm.request_list);
2395                 spin_unlock(&file_priv->mm.lock);
2396         }
2397
2398         trace_i915_gem_request_add(ring, request->seqno);
2399         ring->outstanding_lazy_seqno = 0;
2400         ring->preallocated_lazy_request = NULL;
2401
2402         if (!dev_priv->ums.mm_suspended) {
2403                 i915_queue_hangcheck(ring->dev);
2404
2405                 cancel_delayed_work_sync(&dev_priv->mm.idle_work);
2406                 queue_delayed_work(dev_priv->wq,
2407                                    &dev_priv->mm.retire_work,
2408                                    round_jiffies_up_relative(HZ));
2409                 intel_mark_busy(dev_priv->dev);
2410         }
2411
2412         if (out_seqno)
2413                 *out_seqno = request->seqno;
2414         return 0;
2415 }
2416
2417 static inline void
2418 i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
2419 {
2420         struct drm_i915_file_private *file_priv = request->file_priv;
2421
2422         if (!file_priv)
2423                 return;
2424
2425         spin_lock(&file_priv->mm.lock);
2426         list_del(&request->client_list);
2427         request->file_priv = NULL;
2428         spin_unlock(&file_priv->mm.lock);
2429 }
2430
2431 static bool i915_context_is_banned(struct drm_i915_private *dev_priv,
2432                                    const struct intel_context *ctx)
2433 {
2434         unsigned long elapsed;
2435
2436         elapsed = get_seconds() - ctx->hang_stats.guilty_ts;
2437
2438         if (ctx->hang_stats.banned)
2439                 return true;
2440
2441         if (elapsed <= DRM_I915_CTX_BAN_PERIOD) {
2442                 if (!i915_gem_context_is_default(ctx)) {
2443                         DRM_DEBUG("context hanging too fast, banning!\n");
2444                         return true;
2445                 } else if (i915_stop_ring_allow_ban(dev_priv)) {
2446                         if (i915_stop_ring_allow_warn(dev_priv))
2447                                 DRM_ERROR("gpu hanging too fast, banning!\n");
2448                         return true;
2449                 }
2450         }
2451
2452         return false;
2453 }
2454
2455 static void i915_set_reset_status(struct drm_i915_private *dev_priv,
2456                                   struct intel_context *ctx,
2457                                   const bool guilty)
2458 {
2459         struct i915_ctx_hang_stats *hs;
2460
2461         if (WARN_ON(!ctx))
2462                 return;
2463
2464         hs = &ctx->hang_stats;
2465
2466         if (guilty) {
2467                 hs->banned = i915_context_is_banned(dev_priv, ctx);
2468                 hs->batch_active++;
2469                 hs->guilty_ts = get_seconds();
2470         } else {
2471                 hs->batch_pending++;
2472         }
2473 }
2474
2475 static void i915_gem_free_request(struct drm_i915_gem_request *request)
2476 {
2477         list_del(&request->list);
2478         i915_gem_request_remove_from_client(request);
2479
2480         if (request->ctx)
2481                 i915_gem_context_unreference(request->ctx);
2482
2483         kfree(request);
2484 }
2485
2486 struct drm_i915_gem_request *
2487 i915_gem_find_active_request(struct intel_engine_cs *ring)
2488 {
2489         struct drm_i915_gem_request *request;
2490         u32 completed_seqno;
2491
2492         completed_seqno = ring->get_seqno(ring, false);
2493
2494         list_for_each_entry(request, &ring->request_list, list) {
2495                 if (i915_seqno_passed(completed_seqno, request->seqno))
2496                         continue;
2497
2498                 return request;
2499         }
2500
2501         return NULL;
2502 }
2503
2504 static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv,
2505                                        struct intel_engine_cs *ring)
2506 {
2507         struct drm_i915_gem_request *request;
2508         bool ring_hung;
2509
2510         request = i915_gem_find_active_request(ring);
2511
2512         if (request == NULL)
2513                 return;
2514
2515         ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG;
2516
2517         i915_set_reset_status(dev_priv, request->ctx, ring_hung);
2518
2519         list_for_each_entry_continue(request, &ring->request_list, list)
2520                 i915_set_reset_status(dev_priv, request->ctx, false);
2521 }
2522
2523 static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2524                                         struct intel_engine_cs *ring)
2525 {
2526         while (!list_empty(&ring->active_list)) {
2527                 struct drm_i915_gem_object *obj;
2528
2529                 obj = list_first_entry(&ring->active_list,
2530                                        struct drm_i915_gem_object,
2531                                        ring_list);
2532
2533                 i915_gem_object_move_to_inactive(obj);
2534         }
2535
2536         /*
2537          * We must free the requests after all the corresponding objects have
2538          * been moved off active lists. Which is the same order as the normal
2539          * retire_requests function does. This is important if object hold
2540          * implicit references on things like e.g. ppgtt address spaces through
2541          * the request.
2542          */
2543         while (!list_empty(&ring->request_list)) {
2544                 struct drm_i915_gem_request *request;
2545
2546                 request = list_first_entry(&ring->request_list,
2547                                            struct drm_i915_gem_request,
2548                                            list);
2549
2550                 i915_gem_free_request(request);
2551         }
2552
2553         while (!list_empty(&ring->execlist_queue)) {
2554                 struct intel_ctx_submit_request *submit_req;
2555
2556                 submit_req = list_first_entry(&ring->execlist_queue,
2557                                 struct intel_ctx_submit_request,
2558                                 execlist_link);
2559                 list_del(&submit_req->execlist_link);
2560                 intel_runtime_pm_put(dev_priv);
2561                 i915_gem_context_unreference(submit_req->ctx);
2562                 kfree(submit_req);
2563         }
2564
2565         /* These may not have been flush before the reset, do so now */
2566         kfree(ring->preallocated_lazy_request);
2567         ring->preallocated_lazy_request = NULL;
2568         ring->outstanding_lazy_seqno = 0;
2569 }
2570
2571 void i915_gem_restore_fences(struct drm_device *dev)
2572 {
2573         struct drm_i915_private *dev_priv = dev->dev_private;
2574         int i;
2575
2576         for (i = 0; i < dev_priv->num_fence_regs; i++) {
2577                 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
2578
2579                 /*
2580                  * Commit delayed tiling changes if we have an object still
2581                  * attached to the fence, otherwise just clear the fence.
2582                  */
2583                 if (reg->obj) {
2584                         i915_gem_object_update_fence(reg->obj, reg,
2585                                                      reg->obj->tiling_mode);
2586                 } else {
2587                         i915_gem_write_fence(dev, i, NULL);
2588                 }
2589         }
2590 }
2591
2592 void i915_gem_reset(struct drm_device *dev)
2593 {
2594         struct drm_i915_private *dev_priv = dev->dev_private;
2595         struct intel_engine_cs *ring;
2596         int i;
2597
2598         /*
2599          * Before we free the objects from the requests, we need to inspect
2600          * them for finding the guilty party. As the requests only borrow
2601          * their reference to the objects, the inspection must be done first.
2602          */
2603         for_each_ring(ring, dev_priv, i)
2604                 i915_gem_reset_ring_status(dev_priv, ring);
2605
2606         for_each_ring(ring, dev_priv, i)
2607                 i915_gem_reset_ring_cleanup(dev_priv, ring);
2608
2609         i915_gem_context_reset(dev);
2610
2611         i915_gem_restore_fences(dev);
2612 }
2613
2614 /**
2615  * This function clears the request list as sequence numbers are passed.
2616  */
2617 void
2618 i915_gem_retire_requests_ring(struct intel_engine_cs *ring)
2619 {
2620         uint32_t seqno;
2621
2622         if (list_empty(&ring->request_list))
2623                 return;
2624
2625         WARN_ON(i915_verify_lists(ring->dev));
2626
2627         seqno = ring->get_seqno(ring, true);
2628
2629         /* Move any buffers on the active list that are no longer referenced
2630          * by the ringbuffer to the flushing/inactive lists as appropriate,
2631          * before we free the context associated with the requests.
2632          */
2633         while (!list_empty(&ring->active_list)) {
2634                 struct drm_i915_gem_object *obj;
2635
2636                 obj = list_first_entry(&ring->active_list,
2637                                       struct drm_i915_gem_object,
2638                                       ring_list);
2639
2640                 if (!i915_seqno_passed(seqno, obj->last_read_seqno))
2641                         break;
2642
2643                 i915_gem_object_move_to_inactive(obj);
2644         }
2645
2646
2647         while (!list_empty(&ring->request_list)) {
2648                 struct drm_i915_gem_request *request;
2649                 struct intel_ringbuffer *ringbuf;
2650
2651                 request = list_first_entry(&ring->request_list,
2652                                            struct drm_i915_gem_request,
2653                                            list);
2654
2655                 if (!i915_seqno_passed(seqno, request->seqno))
2656                         break;
2657
2658                 trace_i915_gem_request_retire(ring, request->seqno);
2659
2660                 /* This is one of the few common intersection points
2661                  * between legacy ringbuffer submission and execlists:
2662                  * we need to tell them apart in order to find the correct
2663                  * ringbuffer to which the request belongs to.
2664                  */
2665                 if (i915.enable_execlists) {
2666                         struct intel_context *ctx = request->ctx;
2667                         ringbuf = ctx->engine[ring->id].ringbuf;
2668                 } else
2669                         ringbuf = ring->buffer;
2670
2671                 /* We know the GPU must have read the request to have
2672                  * sent us the seqno + interrupt, so use the position
2673                  * of tail of the request to update the last known position
2674                  * of the GPU head.
2675                  */
2676                 ringbuf->last_retired_head = request->tail;
2677
2678                 i915_gem_free_request(request);
2679         }
2680
2681         if (unlikely(ring->trace_irq_seqno &&
2682                      i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
2683                 ring->irq_put(ring);
2684                 ring->trace_irq_seqno = 0;
2685         }
2686
2687         WARN_ON(i915_verify_lists(ring->dev));
2688 }
2689
2690 bool
2691 i915_gem_retire_requests(struct drm_device *dev)
2692 {
2693         struct drm_i915_private *dev_priv = dev->dev_private;
2694         struct intel_engine_cs *ring;
2695         bool idle = true;
2696         int i;
2697
2698         for_each_ring(ring, dev_priv, i) {
2699                 i915_gem_retire_requests_ring(ring);
2700                 idle &= list_empty(&ring->request_list);
2701         }
2702
2703         if (idle)
2704                 mod_delayed_work(dev_priv->wq,
2705                                    &dev_priv->mm.idle_work,
2706                                    msecs_to_jiffies(100));
2707
2708         return idle;
2709 }
2710
2711 static void
2712 i915_gem_retire_work_handler(struct work_struct *work)
2713 {
2714         struct drm_i915_private *dev_priv =
2715                 container_of(work, typeof(*dev_priv), mm.retire_work.work);
2716         struct drm_device *dev = dev_priv->dev;
2717         bool idle;
2718
2719         /* Come back later if the device is busy... */
2720         idle = false;
2721         if (mutex_trylock(&dev->struct_mutex)) {
2722                 idle = i915_gem_retire_requests(dev);
2723                 mutex_unlock(&dev->struct_mutex);
2724         }
2725         if (!idle)
2726                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work,
2727                                    round_jiffies_up_relative(HZ));
2728 }
2729
2730 static void
2731 i915_gem_idle_work_handler(struct work_struct *work)
2732 {
2733         struct drm_i915_private *dev_priv =
2734                 container_of(work, typeof(*dev_priv), mm.idle_work.work);
2735
2736         intel_mark_idle(dev_priv->dev);
2737 }
2738
2739 /**
2740  * Ensures that an object will eventually get non-busy by flushing any required
2741  * write domains, emitting any outstanding lazy request and retiring and
2742  * completed requests.
2743  */
2744 static int
2745 i915_gem_object_flush_active(struct drm_i915_gem_object *obj)
2746 {
2747         int ret;
2748
2749         if (obj->active) {
2750                 ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno);
2751                 if (ret)
2752                         return ret;
2753
2754                 i915_gem_retire_requests_ring(obj->ring);
2755         }
2756
2757         return 0;
2758 }
2759
2760 /**
2761  * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2762  * @DRM_IOCTL_ARGS: standard ioctl arguments
2763  *
2764  * Returns 0 if successful, else an error is returned with the remaining time in
2765  * the timeout parameter.
2766  *  -ETIME: object is still busy after timeout
2767  *  -ERESTARTSYS: signal interrupted the wait
2768  *  -ENONENT: object doesn't exist
2769  * Also possible, but rare:
2770  *  -EAGAIN: GPU wedged
2771  *  -ENOMEM: damn
2772  *  -ENODEV: Internal IRQ fail
2773  *  -E?: The add request failed
2774  *
2775  * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2776  * non-zero timeout parameter the wait ioctl will wait for the given number of
2777  * nanoseconds on an object becoming unbusy. Since the wait itself does so
2778  * without holding struct_mutex the object may become re-busied before this
2779  * function completes. A similar but shorter * race condition exists in the busy
2780  * ioctl
2781  */
2782 int
2783 i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
2784 {
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786         struct drm_i915_gem_wait *args = data;
2787         struct drm_i915_gem_object *obj;
2788         struct intel_engine_cs *ring = NULL;
2789         unsigned reset_counter;
2790         u32 seqno = 0;
2791         int ret = 0;
2792
2793         ret = i915_mutex_lock_interruptible(dev);
2794         if (ret)
2795                 return ret;
2796
2797         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle));
2798         if (&obj->base == NULL) {
2799                 mutex_unlock(&dev->struct_mutex);
2800                 return -ENOENT;
2801         }
2802
2803         /* Need to make sure the object gets inactive eventually. */
2804         ret = i915_gem_object_flush_active(obj);
2805         if (ret)
2806                 goto out;
2807
2808         if (obj->active) {
2809                 seqno = obj->last_read_seqno;
2810                 ring = obj->ring;
2811         }
2812
2813         if (seqno == 0)
2814                  goto out;
2815
2816         /* Do this after OLR check to make sure we make forward progress polling
2817          * on this IOCTL with a timeout <=0 (like busy ioctl)
2818          */
2819         if (args->timeout_ns <= 0) {
2820                 ret = -ETIME;
2821                 goto out;
2822         }
2823
2824         drm_gem_object_unreference(&obj->base);
2825         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
2826         mutex_unlock(&dev->struct_mutex);
2827
2828         return __wait_seqno(ring, seqno, reset_counter, true, &args->timeout_ns,
2829                             file->driver_priv);
2830
2831 out:
2832         drm_gem_object_unreference(&obj->base);
2833         mutex_unlock(&dev->struct_mutex);
2834         return ret;
2835 }
2836
2837 /**
2838  * i915_gem_object_sync - sync an object to a ring.
2839  *
2840  * @obj: object which may be in use on another ring.
2841  * @to: ring we wish to use the object on. May be NULL.
2842  *
2843  * This code is meant to abstract object synchronization with the GPU.
2844  * Calling with NULL implies synchronizing the object with the CPU
2845  * rather than a particular GPU ring.
2846  *
2847  * Returns 0 if successful, else propagates up the lower layer error.
2848  */
2849 int
2850 i915_gem_object_sync(struct drm_i915_gem_object *obj,
2851                      struct intel_engine_cs *to)
2852 {
2853         struct intel_engine_cs *from = obj->ring;
2854         u32 seqno;
2855         int ret, idx;
2856
2857         if (from == NULL || to == from)
2858                 return 0;
2859
2860         if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev))
2861                 return i915_gem_object_wait_rendering(obj, false);
2862
2863         idx = intel_ring_sync_index(from, to);
2864
2865         seqno = obj->last_read_seqno;
2866         /* Optimization: Avoid semaphore sync when we are sure we already
2867          * waited for an object with higher seqno */
2868         if (seqno <= from->semaphore.sync_seqno[idx])
2869                 return 0;
2870
2871         ret = i915_gem_check_olr(obj->ring, seqno);
2872         if (ret)
2873                 return ret;
2874
2875         trace_i915_gem_ring_sync_to(from, to, seqno);
2876         ret = to->semaphore.sync_to(to, from, seqno);
2877         if (!ret)
2878                 /* We use last_read_seqno because sync_to()
2879                  * might have just caused seqno wrap under
2880                  * the radar.
2881                  */
2882                 from->semaphore.sync_seqno[idx] = obj->last_read_seqno;
2883
2884         return ret;
2885 }
2886
2887 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2888 {
2889         u32 old_write_domain, old_read_domains;
2890
2891         /* Force a pagefault for domain tracking on next user access */
2892         i915_gem_release_mmap(obj);
2893
2894         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2895                 return;
2896
2897         /* Wait for any direct GTT access to complete */
2898         mb();
2899
2900         old_read_domains = obj->base.read_domains;
2901         old_write_domain = obj->base.write_domain;
2902
2903         obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2904         obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2905
2906         trace_i915_gem_object_change_domain(obj,
2907                                             old_read_domains,
2908                                             old_write_domain);
2909 }
2910
2911 int i915_vma_unbind(struct i915_vma *vma)
2912 {
2913         struct drm_i915_gem_object *obj = vma->obj;
2914         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2915         int ret;
2916
2917         if (list_empty(&vma->vma_link))
2918                 return 0;
2919
2920         if (!drm_mm_node_allocated(&vma->node)) {
2921                 i915_gem_vma_destroy(vma);
2922                 return 0;
2923         }
2924
2925         if (vma->pin_count)
2926                 return -EBUSY;
2927
2928         BUG_ON(obj->pages == NULL);
2929
2930         ret = i915_gem_object_finish_gpu(obj);
2931         if (ret)
2932                 return ret;
2933         /* Continue on if we fail due to EIO, the GPU is hung so we
2934          * should be safe and we need to cleanup or else we might
2935          * cause memory corruption through use-after-free.
2936          */
2937
2938         if (i915_is_ggtt(vma->vm)) {
2939                 i915_gem_object_finish_gtt(obj);
2940
2941                 /* release the fence reg _after_ flushing */
2942                 ret = i915_gem_object_put_fence(obj);
2943                 if (ret)
2944                         return ret;
2945         }
2946
2947         trace_i915_vma_unbind(vma);
2948
2949         vma->unbind_vma(vma);
2950
2951         list_del_init(&vma->mm_list);
2952         if (i915_is_ggtt(vma->vm))
2953                 obj->map_and_fenceable = false;
2954
2955         drm_mm_remove_node(&vma->node);
2956         i915_gem_vma_destroy(vma);
2957
2958         /* Since the unbound list is global, only move to that list if
2959          * no more VMAs exist. */
2960         if (list_empty(&obj->vma_list)) {
2961                 i915_gem_gtt_finish_object(obj);
2962                 list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list);
2963         }
2964
2965         /* And finally now the object is completely decoupled from this vma,
2966          * we can drop its hold on the backing storage and allow it to be
2967          * reaped by the shrinker.
2968          */
2969         i915_gem_object_unpin_pages(obj);
2970
2971         return 0;
2972 }
2973
2974 int i915_gpu_idle(struct drm_device *dev)
2975 {
2976         struct drm_i915_private *dev_priv = dev->dev_private;
2977         struct intel_engine_cs *ring;
2978         int ret, i;
2979
2980         /* Flush everything onto the inactive list. */
2981         for_each_ring(ring, dev_priv, i) {
2982                 ret = i915_switch_context(ring, ring->default_context);
2983                 if (ret)
2984                         return ret;
2985
2986                 ret = intel_ring_idle(ring);
2987                 if (ret)
2988                         return ret;
2989         }
2990
2991         return 0;
2992 }
2993
2994 static void i965_write_fence_reg(struct drm_device *dev, int reg,
2995                                  struct drm_i915_gem_object *obj)
2996 {
2997         struct drm_i915_private *dev_priv = dev->dev_private;
2998         int fence_reg;
2999         int fence_pitch_shift;
3000
3001         if (INTEL_INFO(dev)->gen >= 6) {
3002                 fence_reg = FENCE_REG_SANDYBRIDGE_0;
3003                 fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT;
3004         } else {
3005                 fence_reg = FENCE_REG_965_0;
3006                 fence_pitch_shift = I965_FENCE_PITCH_SHIFT;
3007         }
3008
3009         fence_reg += reg * 8;
3010
3011         /* To w/a incoherency with non-atomic 64-bit register updates,
3012          * we split the 64-bit update into two 32-bit writes. In order
3013          * for a partial fence not to be evaluated between writes, we
3014          * precede the update with write to turn off the fence register,
3015          * and only enable the fence as the last step.
3016          *
3017          * For extra levels of paranoia, we make sure each step lands
3018          * before applying the next step.
3019          */
3020         I915_WRITE(fence_reg, 0);
3021         POSTING_READ(fence_reg);
3022
3023         if (obj) {
3024                 u32 size = i915_gem_obj_ggtt_size(obj);
3025                 uint64_t val;
3026
3027                 val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) &
3028                                  0xfffff000) << 32;
3029                 val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000;
3030                 val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift;
3031                 if (obj->tiling_mode == I915_TILING_Y)
3032                         val |= 1 << I965_FENCE_TILING_Y_SHIFT;
3033                 val |= I965_FENCE_REG_VALID;
3034
3035                 I915_WRITE(fence_reg + 4, val >> 32);
3036                 POSTING_READ(fence_reg + 4);
3037
3038                 I915_WRITE(fence_reg + 0, val);
3039                 POSTING_READ(fence_reg);
3040         } else {
3041                 I915_WRITE(fence_reg + 4, 0);
3042                 POSTING_READ(fence_reg + 4);
3043         }
3044 }
3045
3046 static void i915_write_fence_reg(struct drm_device *dev, int reg,
3047                                  struct drm_i915_gem_object *obj)
3048 {
3049         struct drm_i915_private *dev_priv = dev->dev_private;
3050         u32 val;
3051
3052         if (obj) {
3053                 u32 size = i915_gem_obj_ggtt_size(obj);
3054                 int pitch_val;
3055                 int tile_width;
3056
3057                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) ||
3058                      (size & -size) != size ||
3059                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3060                      "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3061                      i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size);
3062
3063                 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
3064                         tile_width = 128;
3065                 else
3066                         tile_width = 512;
3067
3068                 /* Note: pitch better be a power of two tile widths */
3069                 pitch_val = obj->stride / tile_width;
3070                 pitch_val = ffs(pitch_val) - 1;
3071
3072                 val = i915_gem_obj_ggtt_offset(obj);
3073                 if (obj->tiling_mode == I915_TILING_Y)
3074                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3075                 val |= I915_FENCE_SIZE_BITS(size);
3076                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3077                 val |= I830_FENCE_REG_VALID;
3078         } else
3079                 val = 0;
3080
3081         if (reg < 8)
3082                 reg = FENCE_REG_830_0 + reg * 4;
3083         else
3084                 reg = FENCE_REG_945_8 + (reg - 8) * 4;
3085
3086         I915_WRITE(reg, val);
3087         POSTING_READ(reg);
3088 }
3089
3090 static void i830_write_fence_reg(struct drm_device *dev, int reg,
3091                                 struct drm_i915_gem_object *obj)
3092 {
3093         struct drm_i915_private *dev_priv = dev->dev_private;
3094         uint32_t val;
3095
3096         if (obj) {
3097                 u32 size = i915_gem_obj_ggtt_size(obj);
3098                 uint32_t pitch_val;
3099
3100                 WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) ||
3101                      (size & -size) != size ||
3102                      (i915_gem_obj_ggtt_offset(obj) & (size - 1)),
3103                      "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3104                      i915_gem_obj_ggtt_offset(obj), size);
3105
3106                 pitch_val = obj->stride / 128;
3107                 pitch_val = ffs(pitch_val) - 1;
3108
3109                 val = i915_gem_obj_ggtt_offset(obj);
3110                 if (obj->tiling_mode == I915_TILING_Y)
3111                         val |= 1 << I830_FENCE_TILING_Y_SHIFT;
3112                 val |= I830_FENCE_SIZE_BITS(size);
3113                 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
3114                 val |= I830_FENCE_REG_VALID;
3115         } else
3116                 val = 0;
3117
3118         I915_WRITE(FENCE_REG_830_0 + reg * 4, val);
3119         POSTING_READ(FENCE_REG_830_0 + reg * 4);
3120 }
3121
3122 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj)
3123 {
3124         return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT;
3125 }
3126
3127 static void i915_gem_write_fence(struct drm_device *dev, int reg,
3128                                  struct drm_i915_gem_object *obj)
3129 {
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131
3132         /* Ensure that all CPU reads are completed before installing a fence
3133          * and all writes before removing the fence.
3134          */
3135         if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj))
3136                 mb();
3137
3138         WARN(obj && (!obj->stride || !obj->tiling_mode),
3139              "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3140              obj->stride, obj->tiling_mode);
3141
3142         switch (INTEL_INFO(dev)->gen) {
3143         case 8:
3144         case 7:
3145         case 6:
3146         case 5:
3147         case 4: i965_write_fence_reg(dev, reg, obj); break;
3148         case 3: i915_write_fence_reg(dev, reg, obj); break;
3149         case 2: i830_write_fence_reg(dev, reg, obj); break;
3150         default: BUG();
3151         }
3152
3153         /* And similarly be paranoid that no direct access to this region
3154          * is reordered to before the fence is installed.
3155          */
3156         if (i915_gem_object_needs_mb(obj))
3157                 mb();
3158 }
3159
3160 static inline int fence_number(struct drm_i915_private *dev_priv,
3161                                struct drm_i915_fence_reg *fence)
3162 {
3163         return fence - dev_priv->fence_regs;
3164 }
3165
3166 static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
3167                                          struct drm_i915_fence_reg *fence,
3168                                          bool enable)
3169 {
3170         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3171         int reg = fence_number(dev_priv, fence);
3172
3173         i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
3174
3175         if (enable) {
3176                 obj->fence_reg = reg;
3177                 fence->obj = obj;
3178                 list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list);
3179         } else {
3180                 obj->fence_reg = I915_FENCE_REG_NONE;
3181                 fence->obj = NULL;
3182                 list_del_init(&fence->lru_list);
3183         }
3184         obj->fence_dirty = false;
3185 }
3186
3187 static int
3188 i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
3189 {
3190         if (obj->last_fenced_seqno) {
3191                 int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno);
3192                 if (ret)
3193                         return ret;
3194
3195                 obj->last_fenced_seqno = 0;
3196         }
3197
3198         return 0;
3199 }
3200
3201 int
3202 i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
3203 {
3204         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3205         struct drm_i915_fence_reg *fence;
3206         int ret;
3207
3208         ret = i915_gem_object_wait_fence(obj);
3209         if (ret)
3210                 return ret;
3211
3212         if (obj->fence_reg == I915_FENCE_REG_NONE)
3213                 return 0;
3214
3215         fence = &dev_priv->fence_regs[obj->fence_reg];
3216
3217         if (WARN_ON(fence->pin_count))
3218                 return -EBUSY;
3219
3220         i915_gem_object_fence_lost(obj);
3221         i915_gem_object_update_fence(obj, fence, false);
3222
3223         return 0;
3224 }
3225
3226 static struct drm_i915_fence_reg *
3227 i915_find_fence_reg(struct drm_device *dev)
3228 {
3229         struct drm_i915_private *dev_priv = dev->dev_private;
3230         struct drm_i915_fence_reg *reg, *avail;
3231         int i;
3232
3233         /* First try to find a free reg */
3234         avail = NULL;
3235         for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
3236                 reg = &dev_priv->fence_regs[i];
3237                 if (!reg->obj)
3238                         return reg;
3239
3240                 if (!reg->pin_count)
3241                         avail = reg;
3242         }
3243
3244         if (avail == NULL)
3245                 goto deadlock;
3246
3247         /* None available, try to steal one or wait for a user to finish */
3248         list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
3249                 if (reg->pin_count)
3250                         continue;
3251
3252                 return reg;
3253         }
3254
3255 deadlock:
3256         /* Wait for completion of pending flips which consume fences */
3257         if (intel_has_pending_fb_unpin(dev))
3258                 return ERR_PTR(-EAGAIN);
3259
3260         return ERR_PTR(-EDEADLK);
3261 }
3262
3263 /**
3264  * i915_gem_object_get_fence - set up fencing for an object
3265  * @obj: object to map through a fence reg
3266  *
3267  * When mapping objects through the GTT, userspace wants to be able to write
3268  * to them without having to worry about swizzling if the object is tiled.
3269  * This function walks the fence regs looking for a free one for @obj,
3270  * stealing one if it can't find any.
3271  *
3272  * It then sets up the reg based on the object's properties: address, pitch
3273  * and tiling format.
3274  *
3275  * For an untiled surface, this removes any existing fence.
3276  */
3277 int
3278 i915_gem_object_get_fence(struct drm_i915_gem_object *obj)
3279 {
3280         struct drm_device *dev = obj->base.dev;
3281         struct drm_i915_private *dev_priv = dev->dev_private;
3282         bool enable = obj->tiling_mode != I915_TILING_NONE;
3283         struct drm_i915_fence_reg *reg;
3284         int ret;
3285
3286         /* Have we updated the tiling parameters upon the object and so
3287          * will need to serialise the write to the associated fence register?
3288          */
3289         if (obj->fence_dirty) {
3290                 ret = i915_gem_object_wait_fence(obj);
3291                 if (ret)
3292                         return ret;
3293         }
3294
3295         /* Just update our place in the LRU if our fence is getting reused. */
3296         if (obj->fence_reg != I915_FENCE_REG_NONE) {
3297                 reg = &dev_priv->fence_regs[obj->fence_reg];
3298                 if (!obj->fence_dirty) {
3299                         list_move_tail(&reg->lru_list,
3300                                        &dev_priv->mm.fence_list);
3301                         return 0;
3302                 }
3303         } else if (enable) {
3304                 if (WARN_ON(!obj->map_and_fenceable))
3305                         return -EINVAL;
3306
3307                 reg = i915_find_fence_reg(dev);
3308                 if (IS_ERR(reg))
3309                         return PTR_ERR(reg);
3310
3311                 if (reg->obj) {
3312                         struct drm_i915_gem_object *old = reg->obj;
3313
3314                         ret = i915_gem_object_wait_fence(old);
3315                         if (ret)
3316                                 return ret;
3317
3318                         i915_gem_object_fence_lost(old);
3319                 }
3320         } else
3321                 return 0;
3322
3323         i915_gem_object_update_fence(obj, reg, enable);
3324
3325         return 0;
3326 }
3327
3328 static bool i915_gem_valid_gtt_space(struct drm_device *dev,
3329                                      struct drm_mm_node *gtt_space,
3330                                      unsigned long cache_level)
3331 {
3332         struct drm_mm_node *other;
3333
3334         /* On non-LLC machines we have to be careful when putting differing
3335          * types of snoopable memory together to avoid the prefetcher
3336          * crossing memory domains and dying.
3337          */
3338         if (HAS_LLC(dev))
3339                 return true;
3340
3341         if (!drm_mm_node_allocated(gtt_space))
3342                 return true;
3343
3344         if (list_empty(&gtt_space->node_list))
3345                 return true;
3346
3347         other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list);
3348         if (other->allocated && !other->hole_follows && other->color != cache_level)
3349                 return false;
3350
3351         other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list);
3352         if (other->allocated && !gtt_space->hole_follows && other->color != cache_level)
3353                 return false;
3354
3355         return true;
3356 }
3357
3358 static void i915_gem_verify_gtt(struct drm_device *dev)
3359 {
3360 #if WATCH_GTT
3361         struct drm_i915_private *dev_priv = dev->dev_private;
3362         struct drm_i915_gem_object *obj;
3363         int err = 0;
3364
3365         list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) {
3366                 if (obj->gtt_space == NULL) {
3367                         printk(KERN_ERR "object found on GTT list with no space reserved\n");
3368                         err++;
3369                         continue;
3370                 }
3371
3372                 if (obj->cache_level != obj->gtt_space->color) {
3373                         printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3374                                i915_gem_obj_ggtt_offset(obj),
3375                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3376                                obj->cache_level,
3377                                obj->gtt_space->color);
3378                         err++;
3379                         continue;
3380                 }
3381
3382                 if (!i915_gem_valid_gtt_space(dev,
3383                                               obj->gtt_space,
3384                                               obj->cache_level)) {
3385                         printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3386                                i915_gem_obj_ggtt_offset(obj),
3387                                i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj),
3388                                obj->cache_level);
3389                         err++;
3390                         continue;
3391                 }
3392         }
3393
3394         WARN_ON(err);
3395 #endif
3396 }
3397
3398 /**
3399  * Finds free space in the GTT aperture and binds the object there.
3400  */
3401 static struct i915_vma *
3402 i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj,
3403                            struct i915_address_space *vm,
3404                            unsigned alignment,
3405                            uint64_t flags)
3406 {
3407         struct drm_device *dev = obj->base.dev;
3408         struct drm_i915_private *dev_priv = dev->dev_private;
3409         u32 size, fence_size, fence_alignment, unfenced_alignment;
3410         unsigned long start =
3411                 flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0;
3412         unsigned long end =
3413                 flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total;
3414         struct i915_vma *vma;
3415         int ret;
3416
3417         fence_size = i915_gem_get_gtt_size(dev,
3418                                            obj->base.size,
3419                                            obj->tiling_mode);
3420         fence_alignment = i915_gem_get_gtt_alignment(dev,
3421                                                      obj->base.size,
3422                                                      obj->tiling_mode, true);
3423         unfenced_alignment =
3424                 i915_gem_get_gtt_alignment(dev,
3425                                            obj->base.size,
3426                                            obj->tiling_mode, false);
3427
3428         if (alignment == 0)
3429                 alignment = flags & PIN_MAPPABLE ? fence_alignment :
3430                                                 unfenced_alignment;
3431         if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) {
3432                 DRM_DEBUG("Invalid object alignment requested %u\n", alignment);
3433                 return ERR_PTR(-EINVAL);
3434         }
3435
3436         size = flags & PIN_MAPPABLE ? fence_size : obj->base.size;
3437
3438         /* If the object is bigger than the entire aperture, reject it early
3439          * before evicting everything in a vain attempt to find space.
3440          */
3441         if (obj->base.size > end) {
3442                 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3443                           obj->base.size,
3444                           flags & PIN_MAPPABLE ? "mappable" : "total",
3445                           end);
3446                 return ERR_PTR(-E2BIG);
3447         }
3448
3449         ret = i915_gem_object_get_pages(obj);
3450         if (ret)
3451                 return ERR_PTR(ret);
3452
3453         i915_gem_object_pin_pages(obj);
3454
3455         vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
3456         if (IS_ERR(vma))
3457                 goto err_unpin;
3458
3459 search_free:
3460         ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node,
3461                                                   size, alignment,
3462                                                   obj->cache_level,
3463                                                   start, end,
3464                                                   DRM_MM_SEARCH_DEFAULT,
3465                                                   DRM_MM_CREATE_DEFAULT);
3466         if (ret) {
3467                 ret = i915_gem_evict_something(dev, vm, size, alignment,
3468                                                obj->cache_level,
3469                                                start, end,
3470                                                flags);
3471                 if (ret == 0)
3472                         goto search_free;
3473
3474                 goto err_free_vma;
3475         }
3476         if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node,
3477                                               obj->cache_level))) {
3478                 ret = -EINVAL;
3479                 goto err_remove_node;
3480         }
3481
3482         ret = i915_gem_gtt_prepare_object(obj);
3483         if (ret)
3484                 goto err_remove_node;
3485
3486         list_move_tail(&obj->global_list, &dev_priv->mm.bound_list);
3487         list_add_tail(&vma->mm_list, &vm->inactive_list);
3488
3489         if (i915_is_ggtt(vm)) {
3490                 bool mappable, fenceable;
3491
3492                 fenceable = (vma->node.size == fence_size &&
3493                              (vma->node.start & (fence_alignment - 1)) == 0);
3494
3495                 mappable = (vma->node.start + obj->base.size <=
3496                             dev_priv->gtt.mappable_end);
3497
3498                 obj->map_and_fenceable = mappable && fenceable;
3499         }
3500
3501         WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable);
3502
3503         trace_i915_vma_bind(vma, flags);
3504         vma->bind_vma(vma, obj->cache_level,
3505                       flags & (PIN_MAPPABLE | PIN_GLOBAL) ? GLOBAL_BIND : 0);
3506
3507         i915_gem_verify_gtt(dev);
3508         return vma;
3509
3510 err_remove_node:
3511         drm_mm_remove_node(&vma->node);
3512 err_free_vma:
3513         i915_gem_vma_destroy(vma);
3514         vma = ERR_PTR(ret);
3515 err_unpin:
3516         i915_gem_object_unpin_pages(obj);
3517         return vma;
3518 }
3519
3520 bool
3521 i915_gem_clflush_object(struct drm_i915_gem_object *obj,
3522                         bool force)
3523 {
3524         /* If we don't have a page list set up, then we're not pinned
3525          * to GPU, and we can ignore the cache flush because it'll happen
3526          * again at bind time.
3527          */
3528         if (obj->pages == NULL)
3529                 return false;
3530
3531         /*
3532          * Stolen memory is always coherent with the GPU as it is explicitly
3533          * marked as wc by the system, or the system is cache-coherent.
3534          */
3535         if (obj->stolen)
3536                 return false;
3537
3538         /* If the GPU is snooping the contents of the CPU cache,
3539          * we do not need to manually clear the CPU cache lines.  However,
3540          * the caches are only snooped when the render cache is
3541          * flushed/invalidated.  As we always have to emit invalidations
3542          * and flushes when moving into and out of the RENDER domain, correct
3543          * snooping behaviour occurs naturally as the result of our domain
3544          * tracking.
3545          */
3546         if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
3547                 return false;
3548
3549         trace_i915_gem_object_clflush(obj);
3550         drm_clflush_sg(obj->pages);
3551
3552         return true;
3553 }
3554
3555 /** Flushes the GTT write domain for the object if it's dirty. */
3556 static void
3557 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
3558 {
3559         uint32_t old_write_domain;
3560
3561         if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
3562                 return;
3563
3564         /* No actual flushing is required for the GTT write domain.  Writes
3565          * to it immediately go to main memory as far as we know, so there's
3566          * no chipset flush.  It also doesn't land in render cache.
3567          *
3568          * However, we do have to enforce the order so that all writes through
3569          * the GTT land before any writes to the device, such as updates to
3570          * the GATT itself.
3571          */
3572         wmb();
3573
3574         old_write_domain = obj->base.write_domain;
3575         obj->base.write_domain = 0;
3576
3577         intel_fb_obj_flush(obj, false);
3578
3579         trace_i915_gem_object_change_domain(obj,
3580                                             obj->base.read_domains,
3581                                             old_write_domain);
3582 }
3583
3584 /** Flushes the CPU write domain for the object if it's dirty. */
3585 static void
3586 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj,
3587                                        bool force)
3588 {
3589         uint32_t old_write_domain;
3590
3591         if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
3592                 return;
3593
3594         if (i915_gem_clflush_object(obj, force))
3595                 i915_gem_chipset_flush(obj->base.dev);
3596
3597         old_write_domain = obj->base.write_domain;
3598         obj->base.write_domain = 0;
3599
3600         intel_fb_obj_flush(obj, false);
3601
3602         trace_i915_gem_object_change_domain(obj,
3603                                             obj->base.read_domains,
3604                                             old_write_domain);
3605 }
3606
3607 /**
3608  * Moves a single object to the GTT read, and possibly write domain.
3609  *
3610  * This function returns when the move is complete, including waiting on
3611  * flushes to occur.
3612  */
3613 int
3614 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
3615 {
3616         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3617         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
3618         uint32_t old_write_domain, old_read_domains;
3619         int ret;
3620
3621         /* Not valid to be called on unbound objects. */
3622         if (vma == NULL)
3623                 return -EINVAL;
3624
3625         if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
3626                 return 0;
3627
3628         ret = i915_gem_object_wait_rendering(obj, !write);
3629         if (ret)
3630                 return ret;
3631
3632         i915_gem_object_retire(obj);
3633         i915_gem_object_flush_cpu_write_domain(obj, false);
3634
3635         /* Serialise direct access to this object with the barriers for
3636          * coherent writes from the GPU, by effectively invalidating the
3637          * GTT domain upon first access.
3638          */
3639         if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
3640                 mb();
3641
3642         old_write_domain = obj->base.write_domain;
3643         old_read_domains = obj->base.read_domains;
3644
3645         /* It should now be out of any other write domains, and we can update
3646          * the domain values for our changes.
3647          */
3648         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3649         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3650         if (write) {
3651                 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3652                 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3653                 obj->dirty = 1;
3654         }
3655
3656         if (write)
3657                 intel_fb_obj_invalidate(obj, NULL);
3658
3659         trace_i915_gem_object_change_domain(obj,
3660                                             old_read_domains,
3661                                             old_write_domain);
3662
3663         /* And bump the LRU for this access */
3664         if (i915_gem_object_is_inactive(obj))
3665                 list_move_tail(&vma->mm_list,
3666                                &dev_priv->gtt.base.inactive_list);
3667
3668         return 0;
3669 }
3670
3671 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3672                                     enum i915_cache_level cache_level)
3673 {
3674         struct drm_device *dev = obj->base.dev;
3675         struct i915_vma *vma, *next;
3676         int ret;
3677
3678         if (obj->cache_level == cache_level)
3679                 return 0;
3680
3681         if (i915_gem_obj_is_pinned(obj)) {
3682                 DRM_DEBUG("can not change the cache level of pinned objects\n");
3683                 return -EBUSY;
3684         }
3685
3686         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
3687                 if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) {
3688                         ret = i915_vma_unbind(vma);
3689                         if (ret)
3690                                 return ret;
3691                 }
3692         }
3693
3694         if (i915_gem_obj_bound_any(obj)) {
3695                 ret = i915_gem_object_finish_gpu(obj);
3696                 if (ret)
3697                         return ret;
3698
3699                 i915_gem_object_finish_gtt(obj);
3700
3701                 /* Before SandyBridge, you could not use tiling or fence
3702                  * registers with snooped memory, so relinquish any fences
3703                  * currently pointing to our region in the aperture.
3704                  */
3705                 if (INTEL_INFO(dev)->gen < 6) {
3706                         ret = i915_gem_object_put_fence(obj);
3707                         if (ret)
3708                                 return ret;
3709                 }
3710
3711                 list_for_each_entry(vma, &obj->vma_list, vma_link)
3712                         if (drm_mm_node_allocated(&vma->node))
3713                                 vma->bind_vma(vma, cache_level,
3714                                               obj->has_global_gtt_mapping ? GLOBAL_BIND : 0);
3715         }
3716
3717         list_for_each_entry(vma, &obj->vma_list, vma_link)
3718                 vma->node.color = cache_level;
3719         obj->cache_level = cache_level;
3720
3721         if (cpu_write_needs_clflush(obj)) {
3722                 u32 old_read_domains, old_write_domain;
3723
3724                 /* If we're coming from LLC cached, then we haven't
3725                  * actually been tracking whether the data is in the
3726                  * CPU cache or not, since we only allow one bit set
3727                  * in obj->write_domain and have been skipping the clflushes.
3728                  * Just set it to the CPU cache for now.
3729                  */
3730                 i915_gem_object_retire(obj);
3731                 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3732
3733                 old_read_domains = obj->base.read_domains;
3734                 old_write_domain = obj->base.write_domain;
3735
3736                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3737                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3738
3739                 trace_i915_gem_object_change_domain(obj,
3740                                                     old_read_domains,
3741                                                     old_write_domain);
3742         }
3743
3744         i915_gem_verify_gtt(dev);
3745         return 0;
3746 }
3747
3748 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
3749                                struct drm_file *file)
3750 {
3751         struct drm_i915_gem_caching *args = data;
3752         struct drm_i915_gem_object *obj;
3753         int ret;
3754
3755         ret = i915_mutex_lock_interruptible(dev);
3756         if (ret)
3757                 return ret;
3758
3759         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3760         if (&obj->base == NULL) {
3761                 ret = -ENOENT;
3762                 goto unlock;
3763         }
3764
3765         switch (obj->cache_level) {
3766         case I915_CACHE_LLC:
3767         case I915_CACHE_L3_LLC:
3768                 args->caching = I915_CACHING_CACHED;
3769                 break;
3770
3771         case I915_CACHE_WT:
3772                 args->caching = I915_CACHING_DISPLAY;
3773                 break;
3774
3775         default:
3776                 args->caching = I915_CACHING_NONE;
3777                 break;
3778         }
3779
3780         drm_gem_object_unreference(&obj->base);
3781 unlock:
3782         mutex_unlock(&dev->struct_mutex);
3783         return ret;
3784 }
3785
3786 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
3787                                struct drm_file *file)
3788 {
3789         struct drm_i915_gem_caching *args = data;
3790         struct drm_i915_gem_object *obj;
3791         enum i915_cache_level level;
3792         int ret;
3793
3794         switch (args->caching) {
3795         case I915_CACHING_NONE:
3796                 level = I915_CACHE_NONE;
3797                 break;
3798         case I915_CACHING_CACHED:
3799                 level = I915_CACHE_LLC;
3800                 break;
3801         case I915_CACHING_DISPLAY:
3802                 level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE;
3803                 break;
3804         default:
3805                 return -EINVAL;
3806         }
3807
3808         ret = i915_mutex_lock_interruptible(dev);
3809         if (ret)
3810                 return ret;
3811
3812         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
3813         if (&obj->base == NULL) {
3814                 ret = -ENOENT;
3815                 goto unlock;
3816         }
3817
3818         ret = i915_gem_object_set_cache_level(obj, level);
3819
3820         drm_gem_object_unreference(&obj->base);
3821 unlock:
3822         mutex_unlock(&dev->struct_mutex);
3823         return ret;
3824 }
3825
3826 static bool is_pin_display(struct drm_i915_gem_object *obj)
3827 {
3828         struct i915_vma *vma;
3829
3830         vma = i915_gem_obj_to_ggtt(obj);
3831         if (!vma)
3832                 return false;
3833
3834         /* There are 3 sources that pin objects:
3835          *   1. The display engine (scanouts, sprites, cursors);
3836          *   2. Reservations for execbuffer;
3837          *   3. The user.
3838          *
3839          * We can ignore reservations as we hold the struct_mutex and
3840          * are only called outside of the reservation path.  The user
3841          * can only increment pin_count once, and so if after
3842          * subtracting the potential reference by the user, any pin_count
3843          * remains, it must be due to another use by the display engine.
3844          */
3845         return vma->pin_count - !!obj->user_pin_count;
3846 }
3847
3848 /*
3849  * Prepare buffer for display plane (scanout, cursors, etc).
3850  * Can be called from an uninterruptible phase (modesetting) and allows
3851  * any flushes to be pipelined (for pageflips).
3852  */
3853 int
3854 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3855                                      u32 alignment,
3856                                      struct intel_engine_cs *pipelined)
3857 {
3858         u32 old_read_domains, old_write_domain;
3859         bool was_pin_display;
3860         int ret;
3861
3862         if (pipelined != obj->ring) {
3863                 ret = i915_gem_object_sync(obj, pipelined);
3864                 if (ret)
3865                         return ret;
3866         }
3867
3868         /* Mark the pin_display early so that we account for the
3869          * display coherency whilst setting up the cache domains.
3870          */
3871         was_pin_display = obj->pin_display;
3872         obj->pin_display = true;
3873
3874         /* The display engine is not coherent with the LLC cache on gen6.  As
3875          * a result, we make sure that the pinning that is about to occur is
3876          * done with uncached PTEs. This is lowest common denominator for all
3877          * chipsets.
3878          *
3879          * However for gen6+, we could do better by using the GFDT bit instead
3880          * of uncaching, which would allow us to flush all the LLC-cached data
3881          * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3882          */
3883         ret = i915_gem_object_set_cache_level(obj,
3884                                               HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
3885         if (ret)
3886                 goto err_unpin_display;
3887
3888         /* As the user may map the buffer once pinned in the display plane
3889          * (e.g. libkms for the bootup splash), we have to ensure that we
3890          * always use map_and_fenceable for all scanout buffers.
3891          */
3892         ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE);
3893         if (ret)
3894                 goto err_unpin_display;
3895
3896         i915_gem_object_flush_cpu_write_domain(obj, true);
3897
3898         old_write_domain = obj->base.write_domain;
3899         old_read_domains = obj->base.read_domains;
3900
3901         /* It should now be out of any other write domains, and we can update
3902          * the domain values for our changes.
3903          */
3904         obj->base.write_domain = 0;
3905         obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
3906
3907         trace_i915_gem_object_change_domain(obj,
3908                                             old_read_domains,
3909                                             old_write_domain);
3910
3911         return 0;
3912
3913 err_unpin_display:
3914         WARN_ON(was_pin_display != is_pin_display(obj));
3915         obj->pin_display = was_pin_display;
3916         return ret;
3917 }
3918
3919 void
3920 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj)
3921 {
3922         i915_gem_object_ggtt_unpin(obj);
3923         obj->pin_display = is_pin_display(obj);
3924 }
3925
3926 int
3927 i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
3928 {
3929         int ret;
3930
3931         if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
3932                 return 0;
3933
3934         ret = i915_gem_object_wait_rendering(obj, false);
3935         if (ret)
3936                 return ret;
3937
3938         /* Ensure that we invalidate the GPU's caches and TLBs. */
3939         obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3940         return 0;
3941 }
3942
3943 /**
3944  * Moves a single object to the CPU read, and possibly write domain.
3945  *
3946  * This function returns when the move is complete, including waiting on
3947  * flushes to occur.
3948  */
3949 int
3950 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
3951 {
3952         uint32_t old_write_domain, old_read_domains;
3953         int ret;
3954
3955         if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3956                 return 0;
3957
3958         ret = i915_gem_object_wait_rendering(obj, !write);
3959         if (ret)
3960                 return ret;
3961
3962         i915_gem_object_retire(obj);
3963         i915_gem_object_flush_gtt_write_domain(obj);
3964
3965         old_write_domain = obj->base.write_domain;
3966         old_read_domains = obj->base.read_domains;
3967
3968         /* Flush the CPU cache if it's still invalid. */
3969         if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
3970                 i915_gem_clflush_object(obj, false);
3971
3972                 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
3973         }
3974
3975         /* It should now be out of any other write domains, and we can update
3976          * the domain values for our changes.
3977          */
3978         BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3979
3980         /* If we're writing through the CPU, then the GPU read domains will
3981          * need to be invalidated at next use.
3982          */
3983         if (write) {
3984                 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3985                 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3986         }
3987
3988         if (write)
3989                 intel_fb_obj_invalidate(obj, NULL);
3990
3991         trace_i915_gem_object_change_domain(obj,
3992                                             old_read_domains,
3993                                             old_write_domain);
3994
3995         return 0;
3996 }
3997
3998 /* Throttle our rendering by waiting until the ring has completed our requests
3999  * emitted over 20 msec ago.
4000  *
4001  * Note that if we were to use the current jiffies each time around the loop,
4002  * we wouldn't escape the function with any frames outstanding if the time to
4003  * render a frame was over 20ms.
4004  *
4005  * This should get us reasonable parallelism between CPU and GPU but also
4006  * relatively low latency when blocking on a particular request to finish.
4007  */
4008 static int
4009 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
4010 {
4011         struct drm_i915_private *dev_priv = dev->dev_private;
4012         struct drm_i915_file_private *file_priv = file->driver_priv;
4013         unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
4014         struct drm_i915_gem_request *request;
4015         struct intel_engine_cs *ring = NULL;
4016         unsigned reset_counter;
4017         u32 seqno = 0;
4018         int ret;
4019
4020         ret = i915_gem_wait_for_error(&dev_priv->gpu_error);
4021         if (ret)
4022                 return ret;
4023
4024         ret = i915_gem_check_wedge(&dev_priv->gpu_error, false);
4025         if (ret)
4026                 return ret;
4027
4028         spin_lock(&file_priv->mm.lock);
4029         list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
4030                 if (time_after_eq(request->emitted_jiffies, recent_enough))
4031                         break;
4032
4033                 ring = request->ring;
4034                 seqno = request->seqno;
4035         }
4036         reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
4037         spin_unlock(&file_priv->mm.lock);
4038
4039         if (seqno == 0)
4040                 return 0;
4041
4042         ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL);
4043         if (ret == 0)
4044                 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
4045
4046         return ret;
4047 }
4048
4049 static bool
4050 i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags)
4051 {
4052         struct drm_i915_gem_object *obj = vma->obj;
4053
4054         if (alignment &&
4055             vma->node.start & (alignment - 1))
4056                 return true;
4057
4058         if (flags & PIN_MAPPABLE && !obj->map_and_fenceable)
4059                 return true;
4060
4061         if (flags & PIN_OFFSET_BIAS &&
4062             vma->node.start < (flags & PIN_OFFSET_MASK))
4063                 return true;
4064
4065         return false;
4066 }
4067
4068 int
4069 i915_gem_object_pin(struct drm_i915_gem_object *obj,
4070                     struct i915_address_space *vm,
4071                     uint32_t alignment,
4072                     uint64_t flags)
4073 {
4074         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4075         struct i915_vma *vma;
4076         int ret;
4077
4078         if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base))
4079                 return -ENODEV;
4080
4081         if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm)))
4082                 return -EINVAL;
4083
4084         vma = i915_gem_obj_to_vma(obj, vm);
4085         if (vma) {
4086                 if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT))
4087                         return -EBUSY;
4088
4089                 if (i915_vma_misplaced(vma, alignment, flags)) {
4090                         WARN(vma->pin_count,
4091                              "bo is already pinned with incorrect alignment:"
4092                              " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4093                              " obj->map_and_fenceable=%d\n",
4094                              i915_gem_obj_offset(obj, vm), alignment,
4095                              !!(flags & PIN_MAPPABLE),
4096                              obj->map_and_fenceable);
4097                         ret = i915_vma_unbind(vma);
4098                         if (ret)
4099                                 return ret;
4100
4101                         vma = NULL;
4102                 }
4103         }
4104
4105         if (vma == NULL || !drm_mm_node_allocated(&vma->node)) {
4106                 vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags);
4107                 if (IS_ERR(vma))
4108                         return PTR_ERR(vma);
4109         }
4110
4111         if (flags & PIN_GLOBAL && !obj->has_global_gtt_mapping)
4112                 vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND);
4113
4114         vma->pin_count++;
4115         if (flags & PIN_MAPPABLE)
4116                 obj->pin_mappable |= true;
4117
4118         return 0;
4119 }
4120
4121 void
4122 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
4123 {
4124         struct i915_vma *vma = i915_gem_obj_to_ggtt(obj);
4125
4126         BUG_ON(!vma);
4127         BUG_ON(vma->pin_count == 0);
4128         BUG_ON(!i915_gem_obj_ggtt_bound(obj));
4129
4130         if (--vma->pin_count == 0)
4131                 obj->pin_mappable = false;
4132 }
4133
4134 bool
4135 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
4136 {
4137         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4138                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4139                 struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
4140
4141                 WARN_ON(!ggtt_vma ||
4142                         dev_priv->fence_regs[obj->fence_reg].pin_count >
4143                         ggtt_vma->pin_count);
4144                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
4145                 return true;
4146         } else
4147                 return false;
4148 }
4149
4150 void
4151 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
4152 {
4153         if (obj->fence_reg != I915_FENCE_REG_NONE) {
4154                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
4155                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
4156                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
4157         }
4158 }
4159
4160 int
4161 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4162                    struct drm_file *file)
4163 {
4164         struct drm_i915_gem_pin *args = data;
4165         struct drm_i915_gem_object *obj;
4166         int ret;
4167
4168         if (INTEL_INFO(dev)->gen >= 6)
4169                 return -ENODEV;
4170
4171         ret = i915_mutex_lock_interruptible(dev);
4172         if (ret)
4173                 return ret;
4174
4175         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4176         if (&obj->base == NULL) {
4177                 ret = -ENOENT;
4178                 goto unlock;
4179         }
4180
4181         if (obj->madv != I915_MADV_WILLNEED) {
4182                 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4183                 ret = -EFAULT;
4184                 goto out;
4185         }
4186
4187         if (obj->pin_filp != NULL && obj->pin_filp != file) {
4188                 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4189                           args->handle);
4190                 ret = -EINVAL;
4191                 goto out;
4192         }
4193
4194         if (obj->user_pin_count == ULONG_MAX) {
4195                 ret = -EBUSY;
4196                 goto out;
4197         }
4198
4199         if (obj->user_pin_count == 0) {
4200                 ret = i915_gem_obj_ggtt_pin(obj, args->alignment, PIN_MAPPABLE);
4201                 if (ret)
4202                         goto out;
4203         }
4204
4205         obj->user_pin_count++;
4206         obj->pin_filp = file;
4207
4208         args->offset = i915_gem_obj_ggtt_offset(obj);
4209 out:
4210         drm_gem_object_unreference(&obj->base);
4211 unlock:
4212         mutex_unlock(&dev->struct_mutex);
4213         return ret;
4214 }
4215
4216 int
4217 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4218                      struct drm_file *file)
4219 {
4220         struct drm_i915_gem_pin *args = data;
4221         struct drm_i915_gem_object *obj;
4222         int ret;
4223
4224         ret = i915_mutex_lock_interruptible(dev);
4225         if (ret)
4226                 return ret;
4227
4228         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4229         if (&obj->base == NULL) {
4230                 ret = -ENOENT;
4231                 goto unlock;
4232         }
4233
4234         if (obj->pin_filp != file) {
4235                 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4236                           args->handle);
4237                 ret = -EINVAL;
4238                 goto out;
4239         }
4240         obj->user_pin_count--;
4241         if (obj->user_pin_count == 0) {
4242                 obj->pin_filp = NULL;
4243                 i915_gem_object_ggtt_unpin(obj);
4244         }
4245
4246 out:
4247         drm_gem_object_unreference(&obj->base);
4248 unlock:
4249         mutex_unlock(&dev->struct_mutex);
4250         return ret;
4251 }
4252
4253 int
4254 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4255                     struct drm_file *file)
4256 {
4257         struct drm_i915_gem_busy *args = data;
4258         struct drm_i915_gem_object *obj;
4259         int ret;
4260
4261         ret = i915_mutex_lock_interruptible(dev);
4262         if (ret)
4263                 return ret;
4264
4265         obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
4266         if (&obj->base == NULL) {
4267                 ret = -ENOENT;
4268                 goto unlock;
4269         }
4270
4271         /* Count all active objects as busy, even if they are currently not used
4272          * by the gpu. Users of this interface expect objects to eventually
4273          * become non-busy without any further actions, therefore emit any
4274          * necessary flushes here.
4275          */
4276         ret = i915_gem_object_flush_active(obj);
4277
4278         args->busy = obj->active;
4279         if (obj->ring) {
4280                 BUILD_BUG_ON(I915_NUM_RINGS > 16);
4281                 args->busy |= intel_ring_flag(obj->ring) << 16;
4282         }
4283
4284         drm_gem_object_unreference(&obj->base);
4285 unlock:
4286         mutex_unlock(&dev->struct_mutex);
4287         return ret;
4288 }
4289
4290 int
4291 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4292                         struct drm_file *file_priv)
4293 {
4294         return i915_gem_ring_throttle(dev, file_priv);
4295 }
4296
4297 int
4298 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4299                        struct drm_file *file_priv)
4300 {
4301         struct drm_i915_gem_madvise *args = data;
4302         struct drm_i915_gem_object *obj;
4303         int ret;
4304
4305         switch (args->madv) {
4306         case I915_MADV_DONTNEED:
4307         case I915_MADV_WILLNEED:
4308             break;
4309         default:
4310             return -EINVAL;
4311         }
4312
4313         ret = i915_mutex_lock_interruptible(dev);
4314         if (ret)
4315                 return ret;
4316
4317         obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
4318         if (&obj->base == NULL) {
4319                 ret = -ENOENT;
4320                 goto unlock;
4321         }
4322
4323         if (i915_gem_obj_is_pinned(obj)) {
4324                 ret = -EINVAL;
4325                 goto out;
4326         }
4327
4328         if (obj->madv != __I915_MADV_PURGED)
4329                 obj->madv = args->madv;
4330
4331         /* if the object is no longer attached, discard its backing storage */
4332         if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL)
4333                 i915_gem_object_truncate(obj);
4334
4335         args->retained = obj->madv != __I915_MADV_PURGED;
4336
4337 out:
4338         drm_gem_object_unreference(&obj->base);
4339 unlock:
4340         mutex_unlock(&dev->struct_mutex);
4341         return ret;
4342 }
4343
4344 void i915_gem_object_init(struct drm_i915_gem_object *obj,
4345                           const struct drm_i915_gem_object_ops *ops)
4346 {
4347         INIT_LIST_HEAD(&obj->global_list);
4348         INIT_LIST_HEAD(&obj->ring_list);
4349         INIT_LIST_HEAD(&obj->obj_exec_link);
4350         INIT_LIST_HEAD(&obj->vma_list);
4351
4352         obj->ops = ops;
4353
4354         obj->fence_reg = I915_FENCE_REG_NONE;
4355         obj->madv = I915_MADV_WILLNEED;
4356
4357         i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
4358 }
4359
4360 static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
4361         .get_pages = i915_gem_object_get_pages_gtt,
4362         .put_pages = i915_gem_object_put_pages_gtt,
4363 };
4364
4365 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
4366                                                   size_t size)
4367 {
4368         struct drm_i915_gem_object *obj;
4369         struct address_space *mapping;
4370         gfp_t mask;
4371
4372         obj = i915_gem_object_alloc(dev);
4373         if (obj == NULL)
4374                 return NULL;
4375
4376         if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4377                 i915_gem_object_free(obj);
4378                 return NULL;
4379         }
4380
4381         mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
4382         if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) {
4383                 /* 965gm cannot relocate objects above 4GiB. */
4384                 mask &= ~__GFP_HIGHMEM;
4385                 mask |= __GFP_DMA32;
4386         }
4387
4388         mapping = file_inode(obj->base.filp)->i_mapping;
4389         mapping_set_gfp_mask(mapping, mask);
4390
4391         i915_gem_object_init(obj, &i915_gem_object_ops);
4392
4393         obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4394         obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4395
4396         if (HAS_LLC(dev)) {
4397                 /* On some devices, we can have the GPU use the LLC (the CPU
4398                  * cache) for about a 10% performance improvement
4399                  * compared to uncached.  Graphics requests other than
4400                  * display scanout are coherent with the CPU in
4401                  * accessing this cache.  This means in this mode we
4402                  * don't need to clflush on the CPU side, and on the
4403                  * GPU side we only need to flush internal caches to
4404                  * get data visible to the CPU.
4405                  *
4406                  * However, we maintain the display planes as UC, and so
4407                  * need to rebind when first used as such.
4408                  */
4409                 obj->cache_level = I915_CACHE_LLC;
4410         } else
4411                 obj->cache_level = I915_CACHE_NONE;
4412
4413         trace_i915_gem_object_create(obj);
4414
4415         return obj;
4416 }
4417
4418 static bool discard_backing_storage(struct drm_i915_gem_object *obj)
4419 {
4420         /* If we are the last user of the backing storage (be it shmemfs
4421          * pages or stolen etc), we know that the pages are going to be
4422          * immediately released. In this case, we can then skip copying
4423          * back the contents from the GPU.
4424          */
4425
4426         if (obj->madv != I915_MADV_WILLNEED)
4427                 return false;
4428
4429         if (obj->base.filp == NULL)
4430                 return true;
4431
4432         /* At first glance, this looks racy, but then again so would be
4433          * userspace racing mmap against close. However, the first external
4434          * reference to the filp can only be obtained through the
4435          * i915_gem_mmap_ioctl() which safeguards us against the user
4436          * acquiring such a reference whilst we are in the middle of
4437          * freeing the object.
4438          */
4439         return atomic_long_read(&obj->base.filp->f_count) == 1;
4440 }
4441
4442 void i915_gem_free_object(struct drm_gem_object *gem_obj)
4443 {
4444         struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
4445         struct drm_device *dev = obj->base.dev;
4446         struct drm_i915_private *dev_priv = dev->dev_private;
4447         struct i915_vma *vma, *next;
4448
4449         intel_runtime_pm_get(dev_priv);
4450
4451         trace_i915_gem_object_destroy(obj);
4452
4453         list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) {
4454                 int ret;
4455
4456                 vma->pin_count = 0;
4457                 ret = i915_vma_unbind(vma);
4458                 if (WARN_ON(ret == -ERESTARTSYS)) {
4459                         bool was_interruptible;
4460
4461                         was_interruptible = dev_priv->mm.interruptible;
4462                         dev_priv->mm.interruptible = false;
4463
4464                         WARN_ON(i915_vma_unbind(vma));
4465
4466                         dev_priv->mm.interruptible = was_interruptible;
4467                 }
4468         }
4469
4470         i915_gem_object_detach_phys(obj);
4471
4472         /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4473          * before progressing. */
4474         if (obj->stolen)
4475                 i915_gem_object_unpin_pages(obj);
4476
4477         WARN_ON(obj->frontbuffer_bits);
4478
4479         if (WARN_ON(obj->pages_pin_count))
4480                 obj->pages_pin_count = 0;
4481         if (discard_backing_storage(obj))
4482                 obj->madv = I915_MADV_DONTNEED;
4483         i915_gem_object_put_pages(obj);
4484         i915_gem_object_free_mmap_offset(obj);
4485
4486         BUG_ON(obj->pages);
4487
4488         if (obj->base.import_attach)
4489                 drm_prime_gem_destroy(&obj->base, NULL);
4490
4491         if (obj->ops->release)
4492                 obj->ops->release(obj);
4493
4494         drm_gem_object_release(&obj->base);
4495         i915_gem_info_remove_obj(dev_priv, obj->base.size);
4496
4497         kfree(obj->bit_17);
4498         i915_gem_object_free(obj);
4499
4500         intel_runtime_pm_put(dev_priv);
4501 }
4502
4503 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
4504                                      struct i915_address_space *vm)
4505 {
4506         struct i915_vma *vma;
4507         list_for_each_entry(vma, &obj->vma_list, vma_link)
4508                 if (vma->vm == vm)
4509                         return vma;
4510
4511         return NULL;
4512 }
4513
4514 void i915_gem_vma_destroy(struct i915_vma *vma)
4515 {
4516         struct i915_address_space *vm = NULL;
4517         WARN_ON(vma->node.allocated);
4518
4519         /* Keep the vma as a placeholder in the execbuffer reservation lists */
4520         if (!list_empty(&vma->exec_list))
4521                 return;
4522
4523         vm = vma->vm;
4524
4525         if (!i915_is_ggtt(vm))
4526                 i915_ppgtt_put(i915_vm_to_ppgtt(vm));
4527
4528         list_del(&vma->vma_link);
4529
4530         kfree(vma);
4531 }
4532
4533 static void
4534 i915_gem_stop_ringbuffers(struct drm_device *dev)
4535 {
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         struct intel_engine_cs *ring;
4538         int i;
4539
4540         for_each_ring(ring, dev_priv, i)
4541                 dev_priv->gt.stop_ring(ring);
4542 }
4543
4544 int
4545 i915_gem_suspend(struct drm_device *dev)
4546 {
4547         struct drm_i915_private *dev_priv = dev->dev_private;
4548         int ret = 0;
4549
4550         mutex_lock(&dev->struct_mutex);
4551         if (dev_priv->ums.mm_suspended)
4552                 goto err;
4553
4554         ret = i915_gpu_idle(dev);
4555         if (ret)
4556                 goto err;
4557
4558         i915_gem_retire_requests(dev);
4559
4560         /* Under UMS, be paranoid and evict. */
4561         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4562                 i915_gem_evict_everything(dev);
4563
4564         i915_kernel_lost_context(dev);
4565         i915_gem_stop_ringbuffers(dev);
4566
4567         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
4568          * We need to replace this with a semaphore, or something.
4569          * And not confound ums.mm_suspended!
4570          */
4571         dev_priv->ums.mm_suspended = !drm_core_check_feature(dev,
4572                                                              DRIVER_MODESET);
4573         mutex_unlock(&dev->struct_mutex);
4574
4575         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
4576         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4577         flush_delayed_work(&dev_priv->mm.idle_work);
4578
4579         return 0;
4580
4581 err:
4582         mutex_unlock(&dev->struct_mutex);
4583         return ret;
4584 }
4585
4586 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice)
4587 {
4588         struct drm_device *dev = ring->dev;
4589         struct drm_i915_private *dev_priv = dev->dev_private;
4590         u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200);
4591         u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
4592         int i, ret;
4593
4594         if (!HAS_L3_DPF(dev) || !remap_info)
4595                 return 0;
4596
4597         ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3);
4598         if (ret)
4599                 return ret;
4600
4601         /*
4602          * Note: We do not worry about the concurrent register cacheline hang
4603          * here because no other code should access these registers other than
4604          * at initialization time.
4605          */
4606         for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
4607                 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
4608                 intel_ring_emit(ring, reg_base + i);
4609                 intel_ring_emit(ring, remap_info[i/4]);
4610         }
4611
4612         intel_ring_advance(ring);
4613
4614         return ret;
4615 }
4616
4617 void i915_gem_init_swizzling(struct drm_device *dev)
4618 {
4619         struct drm_i915_private *dev_priv = dev->dev_private;
4620
4621         if (INTEL_INFO(dev)->gen < 5 ||
4622             dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE)
4623                 return;
4624
4625         I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
4626                                  DISP_TILE_SURFACE_SWIZZLING);
4627
4628         if (IS_GEN5(dev))
4629                 return;
4630
4631         I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL);
4632         if (IS_GEN6(dev))
4633                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4634         else if (IS_GEN7(dev))
4635                 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4636         else if (IS_GEN8(dev))
4637                 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
4638         else
4639                 BUG();
4640 }
4641
4642 static bool
4643 intel_enable_blt(struct drm_device *dev)
4644 {
4645         if (!HAS_BLT(dev))
4646                 return false;
4647
4648         /* The blitter was dysfunctional on early prototypes */
4649         if (IS_GEN6(dev) && dev->pdev->revision < 8) {
4650                 DRM_INFO("BLT not supported on this pre-production hardware;"
4651                          " graphics performance will be degraded.\n");
4652                 return false;
4653         }
4654
4655         return true;
4656 }
4657
4658 int i915_gem_init_rings(struct drm_device *dev)
4659 {
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         int ret;
4662
4663         ret = intel_init_render_ring_buffer(dev);
4664         if (ret)
4665                 return ret;
4666
4667         if (HAS_BSD(dev)) {
4668                 ret = intel_init_bsd_ring_buffer(dev);
4669                 if (ret)
4670                         goto cleanup_render_ring;
4671         }
4672
4673         if (intel_enable_blt(dev)) {
4674                 ret = intel_init_blt_ring_buffer(dev);
4675                 if (ret)
4676                         goto cleanup_bsd_ring;
4677         }
4678
4679         if (HAS_VEBOX(dev)) {
4680                 ret = intel_init_vebox_ring_buffer(dev);
4681                 if (ret)
4682                         goto cleanup_blt_ring;
4683         }
4684
4685         if (HAS_BSD2(dev)) {
4686                 ret = intel_init_bsd2_ring_buffer(dev);
4687                 if (ret)
4688                         goto cleanup_vebox_ring;
4689         }
4690
4691         ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000));
4692         if (ret)
4693                 goto cleanup_bsd2_ring;
4694
4695         return 0;
4696
4697 cleanup_bsd2_ring:
4698         intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]);
4699 cleanup_vebox_ring:
4700         intel_cleanup_ring_buffer(&dev_priv->ring[VECS]);
4701 cleanup_blt_ring:
4702         intel_cleanup_ring_buffer(&dev_priv->ring[BCS]);
4703 cleanup_bsd_ring:
4704         intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
4705 cleanup_render_ring:
4706         intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
4707
4708         return ret;
4709 }
4710
4711 int
4712 i915_gem_init_hw(struct drm_device *dev)
4713 {
4714         struct drm_i915_private *dev_priv = dev->dev_private;
4715         int ret, i;
4716
4717         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
4718                 return -EIO;
4719
4720         if (dev_priv->ellc_size)
4721                 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
4722
4723         if (IS_HASWELL(dev))
4724                 I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ?
4725                            LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED);
4726
4727         if (HAS_PCH_NOP(dev)) {
4728                 if (IS_IVYBRIDGE(dev)) {
4729                         u32 temp = I915_READ(GEN7_MSG_CTL);
4730                         temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
4731                         I915_WRITE(GEN7_MSG_CTL, temp);
4732                 } else if (INTEL_INFO(dev)->gen >= 7) {
4733                         u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT);
4734                         temp &= ~RESET_PCH_HANDSHAKE_ENABLE;
4735                         I915_WRITE(HSW_NDE_RSTWRN_OPT, temp);
4736                 }
4737         }
4738
4739         i915_gem_init_swizzling(dev);
4740
4741         ret = dev_priv->gt.init_rings(dev);
4742         if (ret)
4743                 return ret;
4744
4745         for (i = 0; i < NUM_L3_SLICES(dev); i++)
4746                 i915_gem_l3_remap(&dev_priv->ring[RCS], i);
4747
4748         /*
4749          * XXX: Contexts should only be initialized once. Doing a switch to the
4750          * default context switch however is something we'd like to do after
4751          * reset or thaw (the latter may not actually be necessary for HW, but
4752          * goes with our code better). Context switching requires rings (for
4753          * the do_switch), but before enabling PPGTT. So don't move this.
4754          */
4755         ret = i915_gem_context_enable(dev_priv);
4756         if (ret && ret != -EIO) {
4757                 DRM_ERROR("Context enable failed %d\n", ret);
4758                 i915_gem_cleanup_ringbuffer(dev);
4759
4760                 return ret;
4761         }
4762
4763         ret = i915_ppgtt_init_hw(dev);
4764         if (ret && ret != -EIO) {
4765                 DRM_ERROR("PPGTT enable failed %d\n", ret);
4766                 i915_gem_cleanup_ringbuffer(dev);
4767         }
4768
4769         return ret;
4770 }
4771
4772 int i915_gem_init(struct drm_device *dev)
4773 {
4774         struct drm_i915_private *dev_priv = dev->dev_private;
4775         int ret;
4776
4777         i915.enable_execlists = intel_sanitize_enable_execlists(dev,
4778                         i915.enable_execlists);
4779
4780         mutex_lock(&dev->struct_mutex);
4781
4782         if (IS_VALLEYVIEW(dev)) {
4783                 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4784                 I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ);
4785                 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) &
4786                               VLV_GTLC_ALLOWWAKEACK), 10))
4787                         DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4788         }
4789
4790         if (!i915.enable_execlists) {
4791                 dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission;
4792                 dev_priv->gt.init_rings = i915_gem_init_rings;
4793                 dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer;
4794                 dev_priv->gt.stop_ring = intel_stop_ring_buffer;
4795         } else {
4796                 dev_priv->gt.do_execbuf = intel_execlists_submission;
4797                 dev_priv->gt.init_rings = intel_logical_rings_init;
4798                 dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup;
4799                 dev_priv->gt.stop_ring = intel_logical_ring_stop;
4800         }
4801
4802         ret = i915_gem_init_userptr(dev);
4803         if (ret) {
4804                 mutex_unlock(&dev->struct_mutex);
4805                 return ret;
4806         }
4807
4808         i915_gem_init_global_gtt(dev);
4809
4810         ret = i915_gem_context_init(dev);
4811         if (ret) {
4812                 mutex_unlock(&dev->struct_mutex);
4813                 return ret;
4814         }
4815
4816         ret = i915_gem_init_hw(dev);
4817         if (ret == -EIO) {
4818                 /* Allow ring initialisation to fail by marking the GPU as
4819                  * wedged. But we only want to do this where the GPU is angry,
4820                  * for all other failure, such as an allocation failure, bail.
4821                  */
4822                 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4823                 atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter);
4824                 ret = 0;
4825         }
4826         mutex_unlock(&dev->struct_mutex);
4827
4828         /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4829         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4830                 dev_priv->dri1.allow_batchbuffer = 1;
4831         return ret;
4832 }
4833
4834 void
4835 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4836 {
4837         struct drm_i915_private *dev_priv = dev->dev_private;
4838         struct intel_engine_cs *ring;
4839         int i;
4840
4841         for_each_ring(ring, dev_priv, i)
4842                 dev_priv->gt.cleanup_ring(ring);
4843 }
4844
4845 int
4846 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4847                        struct drm_file *file_priv)
4848 {
4849         struct drm_i915_private *dev_priv = dev->dev_private;
4850         int ret;
4851
4852         if (drm_core_check_feature(dev, DRIVER_MODESET))
4853                 return 0;
4854
4855         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
4856                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4857                 atomic_set(&dev_priv->gpu_error.reset_counter, 0);
4858         }
4859
4860         mutex_lock(&dev->struct_mutex);
4861         dev_priv->ums.mm_suspended = 0;
4862
4863         ret = i915_gem_init_hw(dev);
4864         if (ret != 0) {
4865                 mutex_unlock(&dev->struct_mutex);
4866                 return ret;
4867         }
4868
4869         BUG_ON(!list_empty(&dev_priv->gtt.base.active_list));
4870
4871         ret = drm_irq_install(dev, dev->pdev->irq);
4872         if (ret)
4873                 goto cleanup_ringbuffer;
4874         mutex_unlock(&dev->struct_mutex);
4875
4876         return 0;
4877
4878 cleanup_ringbuffer:
4879         i915_gem_cleanup_ringbuffer(dev);
4880         dev_priv->ums.mm_suspended = 1;
4881         mutex_unlock(&dev->struct_mutex);
4882
4883         return ret;
4884 }
4885
4886 int
4887 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4888                        struct drm_file *file_priv)
4889 {
4890         if (drm_core_check_feature(dev, DRIVER_MODESET))
4891                 return 0;
4892
4893         mutex_lock(&dev->struct_mutex);
4894         drm_irq_uninstall(dev);
4895         mutex_unlock(&dev->struct_mutex);
4896
4897         return i915_gem_suspend(dev);
4898 }
4899
4900 void
4901 i915_gem_lastclose(struct drm_device *dev)
4902 {
4903         int ret;
4904
4905         if (drm_core_check_feature(dev, DRIVER_MODESET))
4906                 return;
4907
4908         ret = i915_gem_suspend(dev);
4909         if (ret)
4910                 DRM_ERROR("failed to idle hardware: %d\n", ret);
4911 }
4912
4913 static void
4914 init_ring_lists(struct intel_engine_cs *ring)
4915 {
4916         INIT_LIST_HEAD(&ring->active_list);
4917         INIT_LIST_HEAD(&ring->request_list);
4918 }
4919
4920 void i915_init_vm(struct drm_i915_private *dev_priv,
4921                   struct i915_address_space *vm)
4922 {
4923         if (!i915_is_ggtt(vm))
4924                 drm_mm_init(&vm->mm, vm->start, vm->total);
4925         vm->dev = dev_priv->dev;
4926         INIT_LIST_HEAD(&vm->active_list);
4927         INIT_LIST_HEAD(&vm->inactive_list);
4928         INIT_LIST_HEAD(&vm->global_link);
4929         list_add_tail(&vm->global_link, &dev_priv->vm_list);
4930 }
4931
4932 void
4933 i915_gem_load(struct drm_device *dev)
4934 {
4935         struct drm_i915_private *dev_priv = dev->dev_private;
4936         int i;
4937
4938         dev_priv->slab =
4939                 kmem_cache_create("i915_gem_object",
4940                                   sizeof(struct drm_i915_gem_object), 0,
4941                                   SLAB_HWCACHE_ALIGN,
4942                                   NULL);
4943
4944         INIT_LIST_HEAD(&dev_priv->vm_list);
4945         i915_init_vm(dev_priv, &dev_priv->gtt.base);
4946
4947         INIT_LIST_HEAD(&dev_priv->context_list);
4948         INIT_LIST_HEAD(&dev_priv->mm.unbound_list);
4949         INIT_LIST_HEAD(&dev_priv->mm.bound_list);
4950         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4951         for (i = 0; i < I915_NUM_RINGS; i++)
4952                 init_ring_lists(&dev_priv->ring[i]);
4953         for (i = 0; i < I915_MAX_NUM_FENCES; i++)
4954                 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4955         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4956                           i915_gem_retire_work_handler);
4957         INIT_DELAYED_WORK(&dev_priv->mm.idle_work,
4958                           i915_gem_idle_work_handler);
4959         init_waitqueue_head(&dev_priv->gpu_error.reset_queue);
4960
4961         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4962         if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) {
4963                 I915_WRITE(MI_ARB_STATE,
4964                            _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
4965         }
4966
4967         dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
4968
4969         /* Old X drivers will take 0-2 for front, back, depth buffers */
4970         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4971                 dev_priv->fence_reg_start = 3;
4972
4973         if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev))
4974                 dev_priv->num_fence_regs = 32;
4975         else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4976                 dev_priv->num_fence_regs = 16;
4977         else
4978                 dev_priv->num_fence_regs = 8;
4979
4980         /* Initialize fence registers to zero */
4981         INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4982         i915_gem_restore_fences(dev);
4983
4984         i915_gem_detect_bit_6_swizzle(dev);
4985         init_waitqueue_head(&dev_priv->pending_flip_queue);
4986
4987         dev_priv->mm.interruptible = true;
4988
4989         dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan;
4990         dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count;
4991         dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS;
4992         register_shrinker(&dev_priv->mm.shrinker);
4993
4994         dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom;
4995         register_oom_notifier(&dev_priv->mm.oom_notifier);
4996
4997         mutex_init(&dev_priv->fb_tracking.lock);
4998 }
4999
5000 void i915_gem_release(struct drm_device *dev, struct drm_file *file)
5001 {
5002         struct drm_i915_file_private *file_priv = file->driver_priv;
5003
5004         cancel_delayed_work_sync(&file_priv->mm.idle_work);
5005
5006         /* Clean up our request list when the client is going away, so that
5007          * later retire_requests won't dereference our soon-to-be-gone
5008          * file_priv.
5009          */
5010         spin_lock(&file_priv->mm.lock);
5011         while (!list_empty(&file_priv->mm.request_list)) {
5012                 struct drm_i915_gem_request *request;
5013
5014                 request = list_first_entry(&file_priv->mm.request_list,
5015                                            struct drm_i915_gem_request,
5016                                            client_list);
5017                 list_del(&request->client_list);
5018                 request->file_priv = NULL;
5019         }
5020         spin_unlock(&file_priv->mm.lock);
5021 }
5022
5023 static void
5024 i915_gem_file_idle_work_handler(struct work_struct *work)
5025 {
5026         struct drm_i915_file_private *file_priv =
5027                 container_of(work, typeof(*file_priv), mm.idle_work.work);
5028
5029         atomic_set(&file_priv->rps_wait_boost, false);
5030 }
5031
5032 int i915_gem_open(struct drm_device *dev, struct drm_file *file)
5033 {
5034         struct drm_i915_file_private *file_priv;
5035         int ret;
5036
5037         DRM_DEBUG_DRIVER("\n");
5038
5039         file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL);
5040         if (!file_priv)
5041                 return -ENOMEM;
5042
5043         file->driver_priv = file_priv;
5044         file_priv->dev_priv = dev->dev_private;
5045         file_priv->file = file;
5046
5047         spin_lock_init(&file_priv->mm.lock);
5048         INIT_LIST_HEAD(&file_priv->mm.request_list);
5049         INIT_DELAYED_WORK(&file_priv->mm.idle_work,
5050                           i915_gem_file_idle_work_handler);
5051
5052         ret = i915_gem_context_open(dev, file);
5053         if (ret)
5054                 kfree(file_priv);
5055
5056         return ret;
5057 }
5058
5059 void i915_gem_track_fb(struct drm_i915_gem_object *old,
5060                        struct drm_i915_gem_object *new,
5061                        unsigned frontbuffer_bits)
5062 {
5063         if (old) {
5064                 WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex));
5065                 WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits));
5066                 old->frontbuffer_bits &= ~frontbuffer_bits;
5067         }
5068
5069         if (new) {
5070                 WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex));
5071                 WARN_ON(new->frontbuffer_bits & frontbuffer_bits);
5072                 new->frontbuffer_bits |= frontbuffer_bits;
5073         }
5074 }
5075
5076 static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task)
5077 {
5078         if (!mutex_is_locked(mutex))
5079                 return false;
5080
5081 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5082         return mutex->owner == task;
5083 #else
5084         /* Since UP may be pre-empted, we cannot assume that we own the lock */
5085         return false;
5086 #endif
5087 }
5088
5089 static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock)
5090 {
5091         if (!mutex_trylock(&dev->struct_mutex)) {
5092                 if (!mutex_is_locked_by(&dev->struct_mutex, current))
5093                         return false;
5094
5095                 if (to_i915(dev)->mm.shrinker_no_lock_stealing)
5096                         return false;
5097
5098                 *unlock = false;
5099         } else
5100                 *unlock = true;
5101
5102         return true;
5103 }
5104
5105 static int num_vma_bound(struct drm_i915_gem_object *obj)
5106 {
5107         struct i915_vma *vma;
5108         int count = 0;
5109
5110         list_for_each_entry(vma, &obj->vma_list, vma_link)
5111                 if (drm_mm_node_allocated(&vma->node))
5112                         count++;
5113
5114         return count;
5115 }
5116
5117 static unsigned long
5118 i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc)
5119 {
5120         struct drm_i915_private *dev_priv =
5121                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5122         struct drm_device *dev = dev_priv->dev;
5123         struct drm_i915_gem_object *obj;
5124         unsigned long count;
5125         bool unlock;
5126
5127         if (!i915_gem_shrinker_lock(dev, &unlock))
5128                 return 0;
5129
5130         count = 0;
5131         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list)
5132                 if (obj->pages_pin_count == 0)
5133                         count += obj->base.size >> PAGE_SHIFT;
5134
5135         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5136                 if (!i915_gem_obj_is_pinned(obj) &&
5137                     obj->pages_pin_count == num_vma_bound(obj))
5138                         count += obj->base.size >> PAGE_SHIFT;
5139         }
5140
5141         if (unlock)
5142                 mutex_unlock(&dev->struct_mutex);
5143
5144         return count;
5145 }
5146
5147 /* All the new VM stuff */
5148 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
5149                                   struct i915_address_space *vm)
5150 {
5151         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5152         struct i915_vma *vma;
5153
5154         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5155
5156         list_for_each_entry(vma, &o->vma_list, vma_link) {
5157                 if (vma->vm == vm)
5158                         return vma->node.start;
5159
5160         }
5161         WARN(1, "%s vma for this object not found.\n",
5162              i915_is_ggtt(vm) ? "global" : "ppgtt");
5163         return -1;
5164 }
5165
5166 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
5167                         struct i915_address_space *vm)
5168 {
5169         struct i915_vma *vma;
5170
5171         list_for_each_entry(vma, &o->vma_list, vma_link)
5172                 if (vma->vm == vm && drm_mm_node_allocated(&vma->node))
5173                         return true;
5174
5175         return false;
5176 }
5177
5178 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o)
5179 {
5180         struct i915_vma *vma;
5181
5182         list_for_each_entry(vma, &o->vma_list, vma_link)
5183                 if (drm_mm_node_allocated(&vma->node))
5184                         return true;
5185
5186         return false;
5187 }
5188
5189 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
5190                                 struct i915_address_space *vm)
5191 {
5192         struct drm_i915_private *dev_priv = o->base.dev->dev_private;
5193         struct i915_vma *vma;
5194
5195         WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base);
5196
5197         BUG_ON(list_empty(&o->vma_list));
5198
5199         list_for_each_entry(vma, &o->vma_list, vma_link)
5200                 if (vma->vm == vm)
5201                         return vma->node.size;
5202
5203         return 0;
5204 }
5205
5206 static unsigned long
5207 i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc)
5208 {
5209         struct drm_i915_private *dev_priv =
5210                 container_of(shrinker, struct drm_i915_private, mm.shrinker);
5211         struct drm_device *dev = dev_priv->dev;
5212         unsigned long freed;
5213         bool unlock;
5214
5215         if (!i915_gem_shrinker_lock(dev, &unlock))
5216                 return SHRINK_STOP;
5217
5218         freed = i915_gem_purge(dev_priv, sc->nr_to_scan);
5219         if (freed < sc->nr_to_scan)
5220                 freed += __i915_gem_shrink(dev_priv,
5221                                            sc->nr_to_scan - freed,
5222                                            false);
5223         if (unlock)
5224                 mutex_unlock(&dev->struct_mutex);
5225
5226         return freed;
5227 }
5228
5229 static int
5230 i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr)
5231 {
5232         struct drm_i915_private *dev_priv =
5233                 container_of(nb, struct drm_i915_private, mm.oom_notifier);
5234         struct drm_device *dev = dev_priv->dev;
5235         struct drm_i915_gem_object *obj;
5236         unsigned long timeout = msecs_to_jiffies(5000) + 1;
5237         unsigned long pinned, bound, unbound, freed;
5238         bool was_interruptible;
5239         bool unlock;
5240
5241         while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) {
5242                 schedule_timeout_killable(1);
5243                 if (fatal_signal_pending(current))
5244                         return NOTIFY_DONE;
5245         }
5246         if (timeout == 0) {
5247                 pr_err("Unable to purge GPU memory due lock contention.\n");
5248                 return NOTIFY_DONE;
5249         }
5250
5251         was_interruptible = dev_priv->mm.interruptible;
5252         dev_priv->mm.interruptible = false;
5253
5254         freed = i915_gem_shrink_all(dev_priv);
5255
5256         dev_priv->mm.interruptible = was_interruptible;
5257
5258         /* Because we may be allocating inside our own driver, we cannot
5259          * assert that there are no objects with pinned pages that are not
5260          * being pointed to by hardware.
5261          */
5262         unbound = bound = pinned = 0;
5263         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
5264                 if (!obj->base.filp) /* not backed by a freeable object */
5265                         continue;
5266
5267                 if (obj->pages_pin_count)
5268                         pinned += obj->base.size;
5269                 else
5270                         unbound += obj->base.size;
5271         }
5272         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
5273                 if (!obj->base.filp)
5274                         continue;
5275
5276                 if (obj->pages_pin_count)
5277                         pinned += obj->base.size;
5278                 else
5279                         bound += obj->base.size;
5280         }
5281
5282         if (unlock)
5283                 mutex_unlock(&dev->struct_mutex);
5284
5285         pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5286                 freed, pinned);
5287         if (unbound || bound)
5288                 pr_err("%lu and %lu bytes still available in the "
5289                        "bound and unbound GPU page lists.\n",
5290                        bound, unbound);
5291
5292         *(unsigned long *)ptr += freed;
5293         return NOTIFY_DONE;
5294 }
5295
5296 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
5297 {
5298         struct i915_vma *vma;
5299
5300         vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link);
5301         if (vma->vm != i915_obj_to_ggtt(obj))
5302                 return NULL;
5303
5304         return vma;
5305 }