2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private *dev_priv)
104 if (IS_GEN6(dev_priv))
105 return GEN6_CONTEXT_ALIGN;
107 return GEN7_CONTEXT_ALIGN;
110 static int get_context_size(struct drm_i915_private *dev_priv)
115 switch (INTEL_GEN(dev_priv)) {
117 reg = I915_READ(CXT_SIZE);
118 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
121 reg = I915_READ(GEN7_CXT_SIZE);
122 if (IS_HASWELL(dev_priv))
123 ret = HSW_CXT_TOTAL_SIZE;
125 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 ret = GEN8_CXT_TOTAL_SIZE;
137 void i915_gem_context_free(struct kref *ctx_ref)
139 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
142 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
143 trace_i915_context_free(ctx);
144 GEM_BUG_ON(!ctx->closed);
146 i915_ppgtt_put(ctx->ppgtt);
148 for (i = 0; i < I915_NUM_ENGINES; i++) {
149 struct intel_context *ce = &ctx->engine[i];
154 WARN_ON(ce->pin_count);
156 intel_ring_free(ce->ring);
158 i915_gem_object_put(ce->state);
161 list_del(&ctx->link);
163 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
167 struct drm_i915_gem_object *
168 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
170 struct drm_i915_gem_object *obj;
173 lockdep_assert_held(&dev->struct_mutex);
175 obj = i915_gem_object_create(dev, size);
180 * Try to make the context utilize L3 as well as LLC.
182 * On VLV we don't have L3 controls in the PTEs so we
183 * shouldn't touch the cache level, especially as that
184 * would make the object snooped which might have a
185 * negative performance impact.
187 * Snooping is required on non-llc platforms in execlist
188 * mode, but since all GGTT accesses use PAT entry 0 we
189 * get snooping anyway regardless of cache_level.
191 * This is only applicable for Ivy Bridge devices since
192 * later platforms don't have L3 control bits in the PTE.
194 if (IS_IVYBRIDGE(dev)) {
195 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
196 /* Failure shouldn't ever happen this early */
198 i915_gem_object_put(obj);
206 static void i915_ppgtt_close(struct i915_address_space *vm)
208 struct list_head *phases[] = {
215 GEM_BUG_ON(vm->closed);
218 for (phase = phases; *phase; phase++) {
219 struct i915_vma *vma, *vn;
221 list_for_each_entry_safe(vma, vn, *phase, vm_link)
222 if (!i915_vma_is_closed(vma))
227 static void context_close(struct i915_gem_context *ctx)
229 GEM_BUG_ON(ctx->closed);
232 i915_ppgtt_close(&ctx->ppgtt->base);
233 ctx->file_priv = ERR_PTR(-EBADF);
234 i915_gem_context_put(ctx);
237 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
241 ret = ida_simple_get(&dev_priv->context_hw_ida,
242 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
244 /* Contexts are only released when no longer active.
245 * Flush any pending retires to hopefully release some
246 * stale contexts and try again.
248 i915_gem_retire_requests(dev_priv);
249 ret = ida_simple_get(&dev_priv->context_hw_ida,
250 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
259 static struct i915_gem_context *
260 __create_hw_context(struct drm_device *dev,
261 struct drm_i915_file_private *file_priv)
263 struct drm_i915_private *dev_priv = to_i915(dev);
264 struct i915_gem_context *ctx;
267 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
269 return ERR_PTR(-ENOMEM);
271 ret = assign_hw_id(dev_priv, &ctx->hw_id);
277 kref_init(&ctx->ref);
278 list_add_tail(&ctx->link, &dev_priv->context_list);
279 ctx->i915 = dev_priv;
281 ctx->ggtt_alignment = get_context_alignment(dev_priv);
283 if (dev_priv->hw_context_size) {
284 struct drm_i915_gem_object *obj =
285 i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
290 ctx->engine[RCS].state = obj;
293 /* Default context will never have a file_priv */
294 if (file_priv != NULL) {
295 ret = idr_alloc(&file_priv->context_idr, ctx,
296 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
300 ret = DEFAULT_CONTEXT_HANDLE;
302 ctx->file_priv = file_priv;
303 ctx->user_handle = ret;
304 /* NB: Mark all slices as needing a remap so that when the context first
305 * loads it will restore whatever remap state already exists. If there
306 * is no remap info, it will be a NOP. */
307 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
309 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
310 ctx->ring_size = 4 * PAGE_SIZE;
311 ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
312 GEN8_CTX_ADDRESSING_MODE_SHIFT;
313 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
323 * The default context needs to exist per ring that uses contexts. It stores the
324 * context state of the GPU for applications that don't utilize HW contexts, as
325 * well as an idle case.
327 static struct i915_gem_context *
328 i915_gem_create_context(struct drm_device *dev,
329 struct drm_i915_file_private *file_priv)
331 struct i915_gem_context *ctx;
333 lockdep_assert_held(&dev->struct_mutex);
335 ctx = __create_hw_context(dev, file_priv);
339 if (USES_FULL_PPGTT(dev)) {
340 struct i915_hw_ppgtt *ppgtt =
341 i915_ppgtt_create(to_i915(dev), file_priv);
344 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
346 idr_remove(&file_priv->context_idr, ctx->user_handle);
348 return ERR_CAST(ppgtt);
354 trace_i915_context_create(ctx);
360 * i915_gem_context_create_gvt - create a GVT GEM context
363 * This function is used to create a GVT specific GEM context.
366 * pointer to i915_gem_context on success, error pointer if failed
369 struct i915_gem_context *
370 i915_gem_context_create_gvt(struct drm_device *dev)
372 struct i915_gem_context *ctx;
375 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
376 return ERR_PTR(-ENODEV);
378 ret = i915_mutex_lock_interruptible(dev);
382 ctx = i915_gem_create_context(dev, NULL);
386 ctx->execlists_force_single_submission = true;
387 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
389 mutex_unlock(&dev->struct_mutex);
393 static void i915_gem_context_unpin(struct i915_gem_context *ctx,
394 struct intel_engine_cs *engine)
396 if (i915.enable_execlists) {
397 intel_lr_context_unpin(ctx, engine);
399 struct intel_context *ce = &ctx->engine[engine->id];
402 i915_gem_object_ggtt_unpin(ce->state);
404 i915_gem_context_put(ctx);
408 void i915_gem_context_reset(struct drm_device *dev)
410 struct drm_i915_private *dev_priv = to_i915(dev);
412 lockdep_assert_held(&dev->struct_mutex);
414 if (i915.enable_execlists) {
415 struct i915_gem_context *ctx;
417 list_for_each_entry(ctx, &dev_priv->context_list, link)
418 intel_lr_context_reset(dev_priv, ctx);
421 i915_gem_context_lost(dev_priv);
424 int i915_gem_context_init(struct drm_device *dev)
426 struct drm_i915_private *dev_priv = to_i915(dev);
427 struct i915_gem_context *ctx;
429 /* Init should only be called once per module load. Eventually the
430 * restriction on the context_disabled check can be loosened. */
431 if (WARN_ON(dev_priv->kernel_context))
434 if (intel_vgpu_active(dev_priv) &&
435 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
436 if (!i915.enable_execlists) {
437 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
442 /* Using the simple ida interface, the max is limited by sizeof(int) */
443 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
444 ida_init(&dev_priv->context_hw_ida);
446 if (i915.enable_execlists) {
447 /* NB: intentionally left blank. We will allocate our own
448 * backing objects as we need them, thank you very much */
449 dev_priv->hw_context_size = 0;
450 } else if (HAS_HW_CONTEXTS(dev_priv)) {
451 dev_priv->hw_context_size =
452 round_up(get_context_size(dev_priv), 4096);
453 if (dev_priv->hw_context_size > (1<<20)) {
454 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
455 dev_priv->hw_context_size);
456 dev_priv->hw_context_size = 0;
460 ctx = i915_gem_create_context(dev, NULL);
462 DRM_ERROR("Failed to create default global context (error %ld)\n",
467 dev_priv->kernel_context = ctx;
469 DRM_DEBUG_DRIVER("%s context support initialized\n",
470 i915.enable_execlists ? "LR" :
471 dev_priv->hw_context_size ? "HW" : "fake");
475 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
477 struct intel_engine_cs *engine;
479 lockdep_assert_held(&dev_priv->drm.struct_mutex);
481 for_each_engine(engine, dev_priv) {
482 if (engine->last_context) {
483 i915_gem_context_unpin(engine->last_context, engine);
484 engine->last_context = NULL;
488 /* Force the GPU state to be restored on enabling */
489 if (!i915.enable_execlists) {
490 struct i915_gem_context *ctx;
492 list_for_each_entry(ctx, &dev_priv->context_list, link) {
493 if (!i915_gem_context_is_default(ctx))
496 for_each_engine(engine, dev_priv)
497 ctx->engine[engine->id].initialised = false;
499 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
502 for_each_engine(engine, dev_priv) {
503 struct intel_context *kce =
504 &dev_priv->kernel_context->engine[engine->id];
506 kce->initialised = true;
511 void i915_gem_context_fini(struct drm_device *dev)
513 struct drm_i915_private *dev_priv = to_i915(dev);
514 struct i915_gem_context *dctx = dev_priv->kernel_context;
516 lockdep_assert_held(&dev->struct_mutex);
519 dev_priv->kernel_context = NULL;
521 ida_destroy(&dev_priv->context_hw_ida);
524 static int context_idr_cleanup(int id, void *p, void *data)
526 struct i915_gem_context *ctx = p;
532 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
534 struct drm_i915_file_private *file_priv = file->driver_priv;
535 struct i915_gem_context *ctx;
537 idr_init(&file_priv->context_idr);
539 mutex_lock(&dev->struct_mutex);
540 ctx = i915_gem_create_context(dev, file_priv);
541 mutex_unlock(&dev->struct_mutex);
544 idr_destroy(&file_priv->context_idr);
551 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
553 struct drm_i915_file_private *file_priv = file->driver_priv;
555 lockdep_assert_held(&dev->struct_mutex);
557 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
558 idr_destroy(&file_priv->context_idr);
562 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
564 struct drm_i915_private *dev_priv = req->i915;
565 struct intel_ring *ring = req->ring;
566 struct intel_engine_cs *engine = req->engine;
567 u32 flags = hw_flags | MI_MM_SPACE_GTT;
568 const int num_rings =
569 /* Use an extended w/a on ivb+ if signalling from other rings */
571 hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
575 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
576 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
577 * explicitly, so we rely on the value at ring init, stored in
578 * itlb_before_ctx_switch.
580 if (IS_GEN6(dev_priv)) {
581 ret = engine->emit_flush(req, EMIT_INVALIDATE);
586 /* These flags are for resource streamer on HSW+ */
587 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
588 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
589 else if (INTEL_GEN(dev_priv) < 8)
590 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
594 if (INTEL_GEN(dev_priv) >= 7)
595 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
597 ret = intel_ring_begin(req, len);
601 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
602 if (INTEL_GEN(dev_priv) >= 7) {
603 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
605 struct intel_engine_cs *signaller;
607 intel_ring_emit(ring,
608 MI_LOAD_REGISTER_IMM(num_rings));
609 for_each_engine(signaller, dev_priv) {
610 if (signaller == engine)
613 intel_ring_emit_reg(ring,
614 RING_PSMI_CTL(signaller->mmio_base));
615 intel_ring_emit(ring,
616 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
621 intel_ring_emit(ring, MI_NOOP);
622 intel_ring_emit(ring, MI_SET_CONTEXT);
623 intel_ring_emit(ring,
624 i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
627 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
628 * WaMiSetContext_Hang:snb,ivb,vlv
630 intel_ring_emit(ring, MI_NOOP);
632 if (INTEL_GEN(dev_priv) >= 7) {
634 struct intel_engine_cs *signaller;
635 i915_reg_t last_reg = {}; /* keep gcc quiet */
637 intel_ring_emit(ring,
638 MI_LOAD_REGISTER_IMM(num_rings));
639 for_each_engine(signaller, dev_priv) {
640 if (signaller == engine)
643 last_reg = RING_PSMI_CTL(signaller->mmio_base);
644 intel_ring_emit_reg(ring, last_reg);
645 intel_ring_emit(ring,
646 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
649 /* Insert a delay before the next switch! */
650 intel_ring_emit(ring,
651 MI_STORE_REGISTER_MEM |
652 MI_SRM_LRM_GLOBAL_GTT);
653 intel_ring_emit_reg(ring, last_reg);
654 intel_ring_emit(ring, engine->scratch.gtt_offset);
655 intel_ring_emit(ring, MI_NOOP);
657 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
660 intel_ring_advance(ring);
665 static int remap_l3(struct drm_i915_gem_request *req, int slice)
667 u32 *remap_info = req->i915->l3_parity.remap_info[slice];
668 struct intel_ring *ring = req->ring;
674 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
679 * Note: We do not worry about the concurrent register cacheline hang
680 * here because no other code should access these registers other than
681 * at initialization time.
683 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
684 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
685 intel_ring_emit_reg(ring, GEN7_L3LOG(slice, i));
686 intel_ring_emit(ring, remap_info[i]);
688 intel_ring_emit(ring, MI_NOOP);
689 intel_ring_advance(ring);
694 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
695 struct intel_engine_cs *engine,
696 struct i915_gem_context *to)
701 if (!to->engine[RCS].initialised)
704 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
707 return to == engine->last_context;
711 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
712 struct intel_engine_cs *engine,
713 struct i915_gem_context *to)
718 /* Always load the ppgtt on first use */
719 if (!engine->last_context)
722 /* Same context without new entries, skip */
723 if (engine->last_context == to &&
724 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
727 if (engine->id != RCS)
730 if (INTEL_GEN(engine->i915) < 8)
737 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
738 struct i915_gem_context *to,
744 if (!IS_GEN8(to->i915))
747 if (hw_flags & MI_RESTORE_INHIBIT)
753 static int do_rcs_switch(struct drm_i915_gem_request *req)
755 struct i915_gem_context *to = req->ctx;
756 struct intel_engine_cs *engine = req->engine;
757 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
758 struct i915_gem_context *from;
762 if (skip_rcs_switch(ppgtt, engine, to))
765 /* Trying to pin first makes error handling easier. */
766 ret = i915_gem_object_ggtt_pin(to->engine[RCS].state, NULL, 0,
767 to->ggtt_alignment, 0);
772 * Pin can switch back to the default context if we end up calling into
773 * evict_everything - as a last ditch gtt defrag effort that also
774 * switches to the default context. Hence we need to reload from here.
776 * XXX: Doing so is painfully broken!
778 from = engine->last_context;
781 * Clear this page out of any CPU caches for coherent swap-in/out. Note
782 * that thanks to write = false in this call and us not setting any gpu
783 * write domains when putting a context object onto the active list
784 * (when switching away from it), this won't block.
786 * XXX: We need a real interface to do this instead of trickery.
788 ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false);
792 if (needs_pd_load_pre(ppgtt, engine, to)) {
793 /* Older GENs and non render rings still want the load first,
794 * "PP_DCLV followed by PP_DIR_BASE register through Load
795 * Register Immediate commands in Ring Buffer before submitting
797 trace_switch_mm(engine, to);
798 ret = ppgtt->switch_mm(ppgtt, req);
803 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
804 /* NB: If we inhibit the restore, the context is not allowed to
805 * die because future work may end up depending on valid address
806 * space. This means we must enforce that a page table load
807 * occur when this occurs. */
808 hw_flags = MI_RESTORE_INHIBIT;
809 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
810 hw_flags = MI_FORCE_RESTORE;
814 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
815 ret = mi_set_context(req, hw_flags);
820 /* The backing object for the context is done after switching to the
821 * *next* context. Therefore we cannot retire the previous context until
822 * the next context has already started running. In fact, the below code
823 * is a bit suboptimal because the retiring can occur simply after the
824 * MI_SET_CONTEXT instead of when the next seqno has completed.
827 struct drm_i915_gem_object *obj = from->engine[RCS].state;
829 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
830 * whole damn pipeline, we don't need to explicitly mark the
831 * object dirty. The only exception is that the context must be
832 * correct in case the object gets swapped out. Ideally we'd be
833 * able to defer doing this until we know the object would be
834 * swapped, but there is no way to do that yet.
836 obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
837 i915_vma_move_to_active(i915_gem_obj_to_ggtt(obj), req, 0);
839 /* obj is kept alive until the next request by its active ref */
840 i915_gem_object_ggtt_unpin(obj);
841 i915_gem_context_put(from);
843 engine->last_context = i915_gem_context_get(to);
845 /* GEN8 does *not* require an explicit reload if the PDPs have been
846 * setup, and we do not wish to move them.
848 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
849 trace_switch_mm(engine, to);
850 ret = ppgtt->switch_mm(ppgtt, req);
851 /* The hardware context switch is emitted, but we haven't
852 * actually changed the state - so it's probably safe to bail
853 * here. Still, let the user know something dangerous has
861 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
863 for (i = 0; i < MAX_L3_SLICES; i++) {
864 if (!(to->remap_slice & (1<<i)))
867 ret = remap_l3(req, i);
871 to->remap_slice &= ~(1<<i);
874 if (!to->engine[RCS].initialised) {
875 if (engine->init_context) {
876 ret = engine->init_context(req);
880 to->engine[RCS].initialised = true;
886 i915_gem_object_ggtt_unpin(to->engine[RCS].state);
891 * i915_switch_context() - perform a GPU context switch.
892 * @req: request for which we'll execute the context switch
894 * The context life cycle is simple. The context refcount is incremented and
895 * decremented by 1 and create and destroy. If the context is in use by the GPU,
896 * it will have a refcount > 1. This allows us to destroy the context abstract
897 * object while letting the normal object tracking destroy the backing BO.
899 * This function should not be used in execlists mode. Instead the context is
900 * switched by writing to the ELSP and requests keep a reference to their
903 int i915_switch_context(struct drm_i915_gem_request *req)
905 struct intel_engine_cs *engine = req->engine;
907 lockdep_assert_held(&req->i915->drm.struct_mutex);
908 if (i915.enable_execlists)
911 if (!req->ctx->engine[engine->id].state) {
912 struct i915_gem_context *to = req->ctx;
913 struct i915_hw_ppgtt *ppgtt =
914 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
916 if (needs_pd_load_pre(ppgtt, engine, to)) {
919 trace_switch_mm(engine, to);
920 ret = ppgtt->switch_mm(ppgtt, req);
924 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
927 if (to != engine->last_context) {
928 if (engine->last_context)
929 i915_gem_context_put(engine->last_context);
930 engine->last_context = i915_gem_context_get(to);
936 return do_rcs_switch(req);
939 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
941 struct intel_engine_cs *engine;
943 for_each_engine(engine, dev_priv) {
944 struct drm_i915_gem_request *req;
947 if (engine->last_context == NULL)
950 if (engine->last_context == dev_priv->kernel_context)
953 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
957 ret = i915_switch_context(req);
958 i915_add_request_no_flush(req);
966 static bool contexts_enabled(struct drm_device *dev)
968 return i915.enable_execlists || to_i915(dev)->hw_context_size;
971 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
972 struct drm_file *file)
974 struct drm_i915_gem_context_create *args = data;
975 struct drm_i915_file_private *file_priv = file->driver_priv;
976 struct i915_gem_context *ctx;
979 if (!contexts_enabled(dev))
985 ret = i915_mutex_lock_interruptible(dev);
989 ctx = i915_gem_create_context(dev, file_priv);
990 mutex_unlock(&dev->struct_mutex);
994 args->ctx_id = ctx->user_handle;
995 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
1000 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *file)
1003 struct drm_i915_gem_context_destroy *args = data;
1004 struct drm_i915_file_private *file_priv = file->driver_priv;
1005 struct i915_gem_context *ctx;
1011 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
1014 ret = i915_mutex_lock_interruptible(dev);
1018 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1020 mutex_unlock(&dev->struct_mutex);
1021 return PTR_ERR(ctx);
1024 idr_remove(&file_priv->context_idr, ctx->user_handle);
1026 mutex_unlock(&dev->struct_mutex);
1028 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
1032 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1033 struct drm_file *file)
1035 struct drm_i915_file_private *file_priv = file->driver_priv;
1036 struct drm_i915_gem_context_param *args = data;
1037 struct i915_gem_context *ctx;
1040 ret = i915_mutex_lock_interruptible(dev);
1044 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1046 mutex_unlock(&dev->struct_mutex);
1047 return PTR_ERR(ctx);
1051 switch (args->param) {
1052 case I915_CONTEXT_PARAM_BAN_PERIOD:
1053 args->value = ctx->hang_stats.ban_period_seconds;
1055 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1056 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1058 case I915_CONTEXT_PARAM_GTT_SIZE:
1060 args->value = ctx->ppgtt->base.total;
1061 else if (to_i915(dev)->mm.aliasing_ppgtt)
1062 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1064 args->value = to_i915(dev)->ggtt.base.total;
1066 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1067 args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
1073 mutex_unlock(&dev->struct_mutex);
1078 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1079 struct drm_file *file)
1081 struct drm_i915_file_private *file_priv = file->driver_priv;
1082 struct drm_i915_gem_context_param *args = data;
1083 struct i915_gem_context *ctx;
1086 ret = i915_mutex_lock_interruptible(dev);
1090 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1092 mutex_unlock(&dev->struct_mutex);
1093 return PTR_ERR(ctx);
1096 switch (args->param) {
1097 case I915_CONTEXT_PARAM_BAN_PERIOD:
1100 else if (args->value < ctx->hang_stats.ban_period_seconds &&
1101 !capable(CAP_SYS_ADMIN))
1104 ctx->hang_stats.ban_period_seconds = args->value;
1106 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1110 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1111 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1114 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1119 ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
1121 ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
1128 mutex_unlock(&dev->struct_mutex);
1133 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1134 void *data, struct drm_file *file)
1136 struct drm_i915_private *dev_priv = to_i915(dev);
1137 struct drm_i915_reset_stats *args = data;
1138 struct i915_ctx_hang_stats *hs;
1139 struct i915_gem_context *ctx;
1142 if (args->flags || args->pad)
1145 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1148 ret = i915_mutex_lock_interruptible(dev);
1152 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1154 mutex_unlock(&dev->struct_mutex);
1155 return PTR_ERR(ctx);
1157 hs = &ctx->hang_stats;
1159 if (capable(CAP_SYS_ADMIN))
1160 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1162 args->reset_count = 0;
1164 args->batch_active = hs->batch_active;
1165 args->batch_pending = hs->batch_pending;
1167 mutex_unlock(&dev->struct_mutex);