2 * Copyright © 2011-2012 Intel Corporation
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
89 #include <drm/i915_drm.h>
91 #include "i915_trace.h"
93 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
95 /* This is a HW constraint. The value below is the largest known requirement
96 * I've seen in a spec to date, and that was a workaround for a non-shipping
97 * part. It should be safe to decrease this, but it's more future proof as is.
99 #define GEN6_CONTEXT_ALIGN (64<<10)
100 #define GEN7_CONTEXT_ALIGN 4096
102 static size_t get_context_alignment(struct drm_i915_private *dev_priv)
104 if (IS_GEN6(dev_priv))
105 return GEN6_CONTEXT_ALIGN;
107 return GEN7_CONTEXT_ALIGN;
110 static int get_context_size(struct drm_i915_private *dev_priv)
115 switch (INTEL_GEN(dev_priv)) {
117 reg = I915_READ(CXT_SIZE);
118 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
121 reg = I915_READ(GEN7_CXT_SIZE);
122 if (IS_HASWELL(dev_priv))
123 ret = HSW_CXT_TOTAL_SIZE;
125 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
128 ret = GEN8_CXT_TOTAL_SIZE;
137 static void i915_gem_context_clean(struct i915_gem_context *ctx)
139 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
140 struct i915_vma *vma, *next;
145 list_for_each_entry_safe(vma, next, &ppgtt->base.inactive_list,
147 if (WARN_ON(__i915_vma_unbind_no_wait(vma)))
152 void i915_gem_context_free(struct kref *ctx_ref)
154 struct i915_gem_context *ctx = container_of(ctx_ref, typeof(*ctx), ref);
157 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
158 trace_i915_context_free(ctx);
161 * This context is going away and we need to remove all VMAs still
162 * around. This is to handle imported shared objects for which
163 * destructor did not run when their handles were closed.
165 i915_gem_context_clean(ctx);
167 i915_ppgtt_put(ctx->ppgtt);
169 for (i = 0; i < I915_NUM_ENGINES; i++) {
170 struct intel_context *ce = &ctx->engine[i];
175 WARN_ON(ce->pin_count);
177 intel_ringbuffer_free(ce->ringbuf);
179 drm_gem_object_unreference(&ce->state->base);
182 list_del(&ctx->link);
184 ida_simple_remove(&ctx->i915->context_hw_ida, ctx->hw_id);
188 struct drm_i915_gem_object *
189 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size)
191 struct drm_i915_gem_object *obj;
194 lockdep_assert_held(&dev->struct_mutex);
196 obj = i915_gem_object_create(dev, size);
201 * Try to make the context utilize L3 as well as LLC.
203 * On VLV we don't have L3 controls in the PTEs so we
204 * shouldn't touch the cache level, especially as that
205 * would make the object snooped which might have a
206 * negative performance impact.
208 * Snooping is required on non-llc platforms in execlist
209 * mode, but since all GGTT accesses use PAT entry 0 we
210 * get snooping anyway regardless of cache_level.
212 * This is only applicable for Ivy Bridge devices since
213 * later platforms don't have L3 control bits in the PTE.
215 if (IS_IVYBRIDGE(dev)) {
216 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
217 /* Failure shouldn't ever happen this early */
219 drm_gem_object_unreference(&obj->base);
227 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
231 ret = ida_simple_get(&dev_priv->context_hw_ida,
232 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
234 /* Contexts are only released when no longer active.
235 * Flush any pending retires to hopefully release some
236 * stale contexts and try again.
238 i915_gem_retire_requests(dev_priv);
239 ret = ida_simple_get(&dev_priv->context_hw_ida,
240 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
249 static struct i915_gem_context *
250 __create_hw_context(struct drm_device *dev,
251 struct drm_i915_file_private *file_priv)
253 struct drm_i915_private *dev_priv = to_i915(dev);
254 struct i915_gem_context *ctx;
257 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
259 return ERR_PTR(-ENOMEM);
261 ret = assign_hw_id(dev_priv, &ctx->hw_id);
267 kref_init(&ctx->ref);
268 list_add_tail(&ctx->link, &dev_priv->context_list);
269 ctx->i915 = dev_priv;
271 ctx->ggtt_alignment = get_context_alignment(dev_priv);
273 if (dev_priv->hw_context_size) {
274 struct drm_i915_gem_object *obj =
275 i915_gem_alloc_context_obj(dev, dev_priv->hw_context_size);
280 ctx->engine[RCS].state = obj;
283 /* Default context will never have a file_priv */
284 if (file_priv != NULL) {
285 ret = idr_alloc(&file_priv->context_idr, ctx,
286 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
290 ret = DEFAULT_CONTEXT_HANDLE;
292 ctx->file_priv = file_priv;
293 ctx->user_handle = ret;
294 /* NB: Mark all slices as needing a remap so that when the context first
295 * loads it will restore whatever remap state already exists. If there
296 * is no remap info, it will be a NOP. */
297 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
299 ctx->hang_stats.ban_period_seconds = DRM_I915_CTX_BAN_PERIOD;
300 ctx->ring_size = 4 * PAGE_SIZE;
301 ctx->desc_template = GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
302 GEN8_CTX_ADDRESSING_MODE_SHIFT;
303 ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
308 i915_gem_context_unreference(ctx);
313 * The default context needs to exist per ring that uses contexts. It stores the
314 * context state of the GPU for applications that don't utilize HW contexts, as
315 * well as an idle case.
317 static struct i915_gem_context *
318 i915_gem_create_context(struct drm_device *dev,
319 struct drm_i915_file_private *file_priv)
321 struct i915_gem_context *ctx;
323 lockdep_assert_held(&dev->struct_mutex);
325 ctx = __create_hw_context(dev, file_priv);
329 if (USES_FULL_PPGTT(dev)) {
330 struct i915_hw_ppgtt *ppgtt = i915_ppgtt_create(dev, file_priv);
333 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
335 idr_remove(&file_priv->context_idr, ctx->user_handle);
336 i915_gem_context_unreference(ctx);
337 return ERR_CAST(ppgtt);
343 trace_i915_context_create(ctx);
349 * i915_gem_context_create_gvt - create a GVT GEM context
352 * This function is used to create a GVT specific GEM context.
355 * pointer to i915_gem_context on success, error pointer if failed
358 struct i915_gem_context *
359 i915_gem_context_create_gvt(struct drm_device *dev)
361 struct i915_gem_context *ctx;
364 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
365 return ERR_PTR(-ENODEV);
367 ret = i915_mutex_lock_interruptible(dev);
371 ctx = i915_gem_create_context(dev, NULL);
375 ctx->execlists_force_single_submission = true;
376 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
378 mutex_unlock(&dev->struct_mutex);
382 static void i915_gem_context_unpin(struct i915_gem_context *ctx,
383 struct intel_engine_cs *engine)
385 if (i915.enable_execlists) {
386 intel_lr_context_unpin(ctx, engine);
388 struct intel_context *ce = &ctx->engine[engine->id];
391 i915_gem_object_ggtt_unpin(ce->state);
393 i915_gem_context_unreference(ctx);
397 void i915_gem_context_reset(struct drm_device *dev)
399 struct drm_i915_private *dev_priv = to_i915(dev);
401 lockdep_assert_held(&dev->struct_mutex);
403 if (i915.enable_execlists) {
404 struct i915_gem_context *ctx;
406 list_for_each_entry(ctx, &dev_priv->context_list, link)
407 intel_lr_context_reset(dev_priv, ctx);
410 i915_gem_context_lost(dev_priv);
413 int i915_gem_context_init(struct drm_device *dev)
415 struct drm_i915_private *dev_priv = to_i915(dev);
416 struct i915_gem_context *ctx;
418 /* Init should only be called once per module load. Eventually the
419 * restriction on the context_disabled check can be loosened. */
420 if (WARN_ON(dev_priv->kernel_context))
423 if (intel_vgpu_active(dev_priv) &&
424 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
425 if (!i915.enable_execlists) {
426 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
431 /* Using the simple ida interface, the max is limited by sizeof(int) */
432 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
433 ida_init(&dev_priv->context_hw_ida);
435 if (i915.enable_execlists) {
436 /* NB: intentionally left blank. We will allocate our own
437 * backing objects as we need them, thank you very much */
438 dev_priv->hw_context_size = 0;
439 } else if (HAS_HW_CONTEXTS(dev_priv)) {
440 dev_priv->hw_context_size =
441 round_up(get_context_size(dev_priv), 4096);
442 if (dev_priv->hw_context_size > (1<<20)) {
443 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size %d\n",
444 dev_priv->hw_context_size);
445 dev_priv->hw_context_size = 0;
449 ctx = i915_gem_create_context(dev, NULL);
451 DRM_ERROR("Failed to create default global context (error %ld)\n",
456 dev_priv->kernel_context = ctx;
458 DRM_DEBUG_DRIVER("%s context support initialized\n",
459 i915.enable_execlists ? "LR" :
460 dev_priv->hw_context_size ? "HW" : "fake");
464 void i915_gem_context_lost(struct drm_i915_private *dev_priv)
466 struct intel_engine_cs *engine;
468 lockdep_assert_held(&dev_priv->drm.struct_mutex);
470 for_each_engine(engine, dev_priv) {
471 if (engine->last_context) {
472 i915_gem_context_unpin(engine->last_context, engine);
473 engine->last_context = NULL;
477 /* Force the GPU state to be restored on enabling */
478 if (!i915.enable_execlists) {
479 struct i915_gem_context *ctx;
481 list_for_each_entry(ctx, &dev_priv->context_list, link) {
482 if (!i915_gem_context_is_default(ctx))
485 for_each_engine(engine, dev_priv)
486 ctx->engine[engine->id].initialised = false;
488 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
491 for_each_engine(engine, dev_priv) {
492 struct intel_context *kce =
493 &dev_priv->kernel_context->engine[engine->id];
495 kce->initialised = true;
500 void i915_gem_context_fini(struct drm_device *dev)
502 struct drm_i915_private *dev_priv = to_i915(dev);
503 struct i915_gem_context *dctx = dev_priv->kernel_context;
505 lockdep_assert_held(&dev->struct_mutex);
507 i915_gem_context_unreference(dctx);
508 dev_priv->kernel_context = NULL;
510 ida_destroy(&dev_priv->context_hw_ida);
513 static int context_idr_cleanup(int id, void *p, void *data)
515 struct i915_gem_context *ctx = p;
517 ctx->file_priv = ERR_PTR(-EBADF);
518 i915_gem_context_unreference(ctx);
522 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file)
524 struct drm_i915_file_private *file_priv = file->driver_priv;
525 struct i915_gem_context *ctx;
527 idr_init(&file_priv->context_idr);
529 mutex_lock(&dev->struct_mutex);
530 ctx = i915_gem_create_context(dev, file_priv);
531 mutex_unlock(&dev->struct_mutex);
534 idr_destroy(&file_priv->context_idr);
541 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
543 struct drm_i915_file_private *file_priv = file->driver_priv;
545 lockdep_assert_held(&dev->struct_mutex);
547 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
548 idr_destroy(&file_priv->context_idr);
552 mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
554 struct drm_i915_private *dev_priv = req->i915;
555 struct intel_engine_cs *engine = req->engine;
556 u32 flags = hw_flags | MI_MM_SPACE_GTT;
557 const int num_rings =
558 /* Use an extended w/a on ivb+ if signalling from other rings */
559 i915_semaphore_is_enabled(dev_priv) ?
560 hweight32(INTEL_INFO(dev_priv)->ring_mask) - 1 :
564 /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
565 * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
566 * explicitly, so we rely on the value at ring init, stored in
567 * itlb_before_ctx_switch.
569 if (IS_GEN6(dev_priv)) {
570 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
575 /* These flags are for resource streamer on HSW+ */
576 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
577 flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
578 else if (INTEL_GEN(dev_priv) < 8)
579 flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
583 if (INTEL_GEN(dev_priv) >= 7)
584 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
586 ret = intel_ring_begin(req, len);
590 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
591 if (INTEL_GEN(dev_priv) >= 7) {
592 intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
594 struct intel_engine_cs *signaller;
596 intel_ring_emit(engine,
597 MI_LOAD_REGISTER_IMM(num_rings));
598 for_each_engine(signaller, dev_priv) {
599 if (signaller == engine)
602 intel_ring_emit_reg(engine,
603 RING_PSMI_CTL(signaller->mmio_base));
604 intel_ring_emit(engine,
605 _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
610 intel_ring_emit(engine, MI_NOOP);
611 intel_ring_emit(engine, MI_SET_CONTEXT);
612 intel_ring_emit(engine,
613 i915_gem_obj_ggtt_offset(req->ctx->engine[RCS].state) |
616 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
617 * WaMiSetContext_Hang:snb,ivb,vlv
619 intel_ring_emit(engine, MI_NOOP);
621 if (INTEL_GEN(dev_priv) >= 7) {
623 struct intel_engine_cs *signaller;
624 i915_reg_t last_reg = {}; /* keep gcc quiet */
626 intel_ring_emit(engine,
627 MI_LOAD_REGISTER_IMM(num_rings));
628 for_each_engine(signaller, dev_priv) {
629 if (signaller == engine)
632 last_reg = RING_PSMI_CTL(signaller->mmio_base);
633 intel_ring_emit_reg(engine, last_reg);
634 intel_ring_emit(engine,
635 _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE));
638 /* Insert a delay before the next switch! */
639 intel_ring_emit(engine,
640 MI_STORE_REGISTER_MEM |
641 MI_SRM_LRM_GLOBAL_GTT);
642 intel_ring_emit_reg(engine, last_reg);
643 intel_ring_emit(engine, engine->scratch.gtt_offset);
644 intel_ring_emit(engine, MI_NOOP);
646 intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_ENABLE);
649 intel_ring_advance(engine);
654 static int remap_l3(struct drm_i915_gem_request *req, int slice)
656 u32 *remap_info = req->i915->l3_parity.remap_info[slice];
657 struct intel_engine_cs *engine = req->engine;
663 ret = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
668 * Note: We do not worry about the concurrent register cacheline hang
669 * here because no other code should access these registers other than
670 * at initialization time.
672 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4));
673 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
674 intel_ring_emit_reg(engine, GEN7_L3LOG(slice, i));
675 intel_ring_emit(engine, remap_info[i]);
677 intel_ring_emit(engine, MI_NOOP);
678 intel_ring_advance(engine);
683 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
684 struct intel_engine_cs *engine,
685 struct i915_gem_context *to)
690 if (!to->engine[RCS].initialised)
693 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
696 return to == engine->last_context;
700 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt,
701 struct intel_engine_cs *engine,
702 struct i915_gem_context *to)
707 /* Always load the ppgtt on first use */
708 if (!engine->last_context)
711 /* Same context without new entries, skip */
712 if (engine->last_context == to &&
713 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
716 if (engine->id != RCS)
719 if (INTEL_GEN(engine->i915) < 8)
726 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
727 struct i915_gem_context *to,
733 if (!IS_GEN8(to->i915))
736 if (hw_flags & MI_RESTORE_INHIBIT)
742 static int do_rcs_switch(struct drm_i915_gem_request *req)
744 struct i915_gem_context *to = req->ctx;
745 struct intel_engine_cs *engine = req->engine;
746 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
747 struct i915_gem_context *from;
751 if (skip_rcs_switch(ppgtt, engine, to))
754 /* Trying to pin first makes error handling easier. */
755 ret = i915_gem_obj_ggtt_pin(to->engine[RCS].state,
762 * Pin can switch back to the default context if we end up calling into
763 * evict_everything - as a last ditch gtt defrag effort that also
764 * switches to the default context. Hence we need to reload from here.
766 * XXX: Doing so is painfully broken!
768 from = engine->last_context;
771 * Clear this page out of any CPU caches for coherent swap-in/out. Note
772 * that thanks to write = false in this call and us not setting any gpu
773 * write domains when putting a context object onto the active list
774 * (when switching away from it), this won't block.
776 * XXX: We need a real interface to do this instead of trickery.
778 ret = i915_gem_object_set_to_gtt_domain(to->engine[RCS].state, false);
782 if (needs_pd_load_pre(ppgtt, engine, to)) {
783 /* Older GENs and non render rings still want the load first,
784 * "PP_DCLV followed by PP_DIR_BASE register through Load
785 * Register Immediate commands in Ring Buffer before submitting
787 trace_switch_mm(engine, to);
788 ret = ppgtt->switch_mm(ppgtt, req);
793 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
794 /* NB: If we inhibit the restore, the context is not allowed to
795 * die because future work may end up depending on valid address
796 * space. This means we must enforce that a page table load
797 * occur when this occurs. */
798 hw_flags = MI_RESTORE_INHIBIT;
799 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
800 hw_flags = MI_FORCE_RESTORE;
804 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
805 ret = mi_set_context(req, hw_flags);
810 /* The backing object for the context is done after switching to the
811 * *next* context. Therefore we cannot retire the previous context until
812 * the next context has already started running. In fact, the below code
813 * is a bit suboptimal because the retiring can occur simply after the
814 * MI_SET_CONTEXT instead of when the next seqno has completed.
817 from->engine[RCS].state->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
818 i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->engine[RCS].state), req);
819 /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
820 * whole damn pipeline, we don't need to explicitly mark the
821 * object dirty. The only exception is that the context must be
822 * correct in case the object gets swapped out. Ideally we'd be
823 * able to defer doing this until we know the object would be
824 * swapped, but there is no way to do that yet.
826 from->engine[RCS].state->dirty = 1;
828 /* obj is kept alive until the next request by its active ref */
829 i915_gem_object_ggtt_unpin(from->engine[RCS].state);
830 i915_gem_context_unreference(from);
832 i915_gem_context_reference(to);
833 engine->last_context = to;
835 /* GEN8 does *not* require an explicit reload if the PDPs have been
836 * setup, and we do not wish to move them.
838 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
839 trace_switch_mm(engine, to);
840 ret = ppgtt->switch_mm(ppgtt, req);
841 /* The hardware context switch is emitted, but we haven't
842 * actually changed the state - so it's probably safe to bail
843 * here. Still, let the user know something dangerous has
851 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
853 for (i = 0; i < MAX_L3_SLICES; i++) {
854 if (!(to->remap_slice & (1<<i)))
857 ret = remap_l3(req, i);
861 to->remap_slice &= ~(1<<i);
864 if (!to->engine[RCS].initialised) {
865 if (engine->init_context) {
866 ret = engine->init_context(req);
870 to->engine[RCS].initialised = true;
876 i915_gem_object_ggtt_unpin(to->engine[RCS].state);
881 * i915_switch_context() - perform a GPU context switch.
882 * @req: request for which we'll execute the context switch
884 * The context life cycle is simple. The context refcount is incremented and
885 * decremented by 1 and create and destroy. If the context is in use by the GPU,
886 * it will have a refcount > 1. This allows us to destroy the context abstract
887 * object while letting the normal object tracking destroy the backing BO.
889 * This function should not be used in execlists mode. Instead the context is
890 * switched by writing to the ELSP and requests keep a reference to their
893 int i915_switch_context(struct drm_i915_gem_request *req)
895 struct intel_engine_cs *engine = req->engine;
897 WARN_ON(i915.enable_execlists);
898 lockdep_assert_held(&req->i915->drm.struct_mutex);
900 if (!req->ctx->engine[engine->id].state) {
901 struct i915_gem_context *to = req->ctx;
902 struct i915_hw_ppgtt *ppgtt =
903 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
905 if (needs_pd_load_pre(ppgtt, engine, to)) {
908 trace_switch_mm(engine, to);
909 ret = ppgtt->switch_mm(ppgtt, req);
913 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
916 if (to != engine->last_context) {
917 i915_gem_context_reference(to);
918 if (engine->last_context)
919 i915_gem_context_unreference(engine->last_context);
920 engine->last_context = to;
926 return do_rcs_switch(req);
929 static bool contexts_enabled(struct drm_device *dev)
931 return i915.enable_execlists || to_i915(dev)->hw_context_size;
934 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
935 struct drm_file *file)
937 struct drm_i915_gem_context_create *args = data;
938 struct drm_i915_file_private *file_priv = file->driver_priv;
939 struct i915_gem_context *ctx;
942 if (!contexts_enabled(dev))
948 ret = i915_mutex_lock_interruptible(dev);
952 ctx = i915_gem_create_context(dev, file_priv);
953 mutex_unlock(&dev->struct_mutex);
957 args->ctx_id = ctx->user_handle;
958 DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
963 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
964 struct drm_file *file)
966 struct drm_i915_gem_context_destroy *args = data;
967 struct drm_i915_file_private *file_priv = file->driver_priv;
968 struct i915_gem_context *ctx;
974 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
977 ret = i915_mutex_lock_interruptible(dev);
981 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
983 mutex_unlock(&dev->struct_mutex);
987 idr_remove(&file_priv->context_idr, ctx->user_handle);
988 i915_gem_context_unreference(ctx);
989 mutex_unlock(&dev->struct_mutex);
991 DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
995 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
996 struct drm_file *file)
998 struct drm_i915_file_private *file_priv = file->driver_priv;
999 struct drm_i915_gem_context_param *args = data;
1000 struct i915_gem_context *ctx;
1003 ret = i915_mutex_lock_interruptible(dev);
1007 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1009 mutex_unlock(&dev->struct_mutex);
1010 return PTR_ERR(ctx);
1014 switch (args->param) {
1015 case I915_CONTEXT_PARAM_BAN_PERIOD:
1016 args->value = ctx->hang_stats.ban_period_seconds;
1018 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1019 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1021 case I915_CONTEXT_PARAM_GTT_SIZE:
1023 args->value = ctx->ppgtt->base.total;
1024 else if (to_i915(dev)->mm.aliasing_ppgtt)
1025 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1027 args->value = to_i915(dev)->ggtt.base.total;
1029 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1030 args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE);
1036 mutex_unlock(&dev->struct_mutex);
1041 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1042 struct drm_file *file)
1044 struct drm_i915_file_private *file_priv = file->driver_priv;
1045 struct drm_i915_gem_context_param *args = data;
1046 struct i915_gem_context *ctx;
1049 ret = i915_mutex_lock_interruptible(dev);
1053 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1055 mutex_unlock(&dev->struct_mutex);
1056 return PTR_ERR(ctx);
1059 switch (args->param) {
1060 case I915_CONTEXT_PARAM_BAN_PERIOD:
1063 else if (args->value < ctx->hang_stats.ban_period_seconds &&
1064 !capable(CAP_SYS_ADMIN))
1067 ctx->hang_stats.ban_period_seconds = args->value;
1069 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1073 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1074 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1077 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1082 ctx->flags |= CONTEXT_NO_ERROR_CAPTURE;
1084 ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE;
1091 mutex_unlock(&dev->struct_mutex);
1096 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1097 void *data, struct drm_file *file)
1099 struct drm_i915_private *dev_priv = to_i915(dev);
1100 struct drm_i915_reset_stats *args = data;
1101 struct i915_ctx_hang_stats *hs;
1102 struct i915_gem_context *ctx;
1105 if (args->flags || args->pad)
1108 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1111 ret = i915_mutex_lock_interruptible(dev);
1115 ctx = i915_gem_context_lookup(file->driver_priv, args->ctx_id);
1117 mutex_unlock(&dev->struct_mutex);
1118 return PTR_ERR(ctx);
1120 hs = &ctx->hang_stats;
1122 if (capable(CAP_SYS_ADMIN))
1123 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1125 args->reset_count = 0;
1127 args->batch_active = hs->batch_active;
1128 args->batch_pending = hs->batch_pending;
1130 mutex_unlock(&dev->struct_mutex);