drivers/gpu/drm/i915/i915_gem_execbuffer.c

   1 /*
   2  * Copyright © 2008,2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Chris Wilson <chris@chris-wilson.co.uk>
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34 #include <linux/dma_remapping.h>
  35 #include <linux/uaccess.h>
  36
  37 #define  __EXEC_OBJECT_HAS_PIN (1<<31)
  38 #define  __EXEC_OBJECT_HAS_FENCE (1<<30)
  39 #define  __EXEC_OBJECT_NEEDS_MAP (1<<29)
  40 #define  __EXEC_OBJECT_NEEDS_BIAS (1<<28)
  41
  42 #define BATCH_OFFSET_BIAS (256*1024)
  43
  44 struct eb_vmas {
  45         struct list_head vmas;
  46         int and;
  47         union {
  48                 struct i915_vma *lut[0];
  49                 struct hlist_head buckets[0];
  50         };
  51 };
  52
  53 static struct eb_vmas *
  54 eb_create(struct drm_i915_gem_execbuffer2 *args)
  55 {
  56         struct eb_vmas *eb = NULL;
  57
  58         if (args->flags & I915_EXEC_HANDLE_LUT) {
  59                 unsigned size = args->buffer_count;
  60                 size *= sizeof(struct i915_vma *);
  61                 size += sizeof(struct eb_vmas);
  62                 eb = kmalloc(size, GFP_TEMPORARY | __GFP_NOWARN | __GFP_NORETRY);
  63         }
  64
  65         if (eb == NULL) {
  66                 unsigned size = args->buffer_count;
  67                 unsigned count = PAGE_SIZE / sizeof(struct hlist_head) / 2;
  68                 BUILD_BUG_ON_NOT_POWER_OF_2(PAGE_SIZE / sizeof(struct hlist_head));
  69                 while (count > 2*size)
  70                         count >>= 1;
  71                 eb = kzalloc(count*sizeof(struct hlist_head) +
  72                              sizeof(struct eb_vmas),
  73                              GFP_TEMPORARY);
  74                 if (eb == NULL)
  75                         return eb;
  76
  77                 eb->and = count - 1;
  78         } else
  79                 eb->and = -args->buffer_count;
  80
  81         INIT_LIST_HEAD(&eb->vmas);
  82         return eb;
  83 }
  84
  85 static void
  86 eb_reset(struct eb_vmas *eb)
  87 {
  88         if (eb->and >= 0)
  89                 memset(eb->buckets, 0, (eb->and+1)*sizeof(struct hlist_head));
  90 }
  91
  92 static int
  93 eb_lookup_vmas(struct eb_vmas *eb,
  94                struct drm_i915_gem_exec_object2 *exec,
  95                const struct drm_i915_gem_execbuffer2 *args,
  96                struct i915_address_space *vm,
  97                struct drm_file *file)
  98 {
  99         struct drm_i915_gem_object *obj;
 100         struct list_head objects;
 101         int i, ret;
 102
 103         INIT_LIST_HEAD(&objects);
 104         spin_lock(&file->table_lock);
 105         /* Grab a reference to the object and release the lock so we can lookup
 106          * or create the VMA without using GFP_ATOMIC */
 107         for (i = 0; i < args->buffer_count; i++) {
 108                 obj = to_intel_bo(idr_find(&file->object_idr, exec[i].handle));
 109                 if (obj == NULL) {
 110                         spin_unlock(&file->table_lock);
 111                         DRM_DEBUG("Invalid object handle %d at index %d\n",
 112                                    exec[i].handle, i);
 113                         ret = -ENOENT;
 114                         goto err;
 115                 }
 116
 117                 if (!list_empty(&obj->obj_exec_link)) {
 118                         spin_unlock(&file->table_lock);
 119                         DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
 120                                    obj, exec[i].handle, i);
 121                         ret = -EINVAL;
 122                         goto err;
 123                 }
 124
 125                 drm_gem_object_reference(&obj->base);
 126                 list_add_tail(&obj->obj_exec_link, &objects);
 127         }
 128         spin_unlock(&file->table_lock);
 129
 130         i = 0;
 131         while (!list_empty(&objects)) {
 132                 struct i915_vma *vma;
 133
 134                 obj = list_first_entry(&objects,
 135                                        struct drm_i915_gem_object,
 136                                        obj_exec_link);
 137
 138                 /*
 139                  * NOTE: We can leak any vmas created here when something fails
 140                  * later on. But that's no issue since vma_unbind can deal with
 141                  * vmas which are not actually bound. And since only
 142                  * lookup_or_create exists as an interface to get at the vma
 143                  * from the (obj, vm) we don't run the risk of creating
 144                  * duplicated vmas for the same vm.
 145                  */
 146                 vma = i915_gem_obj_lookup_or_create_vma(obj, vm);
 147                 if (IS_ERR(vma)) {
 148                         DRM_DEBUG("Failed to lookup VMA\n");
 149                         ret = PTR_ERR(vma);
 150                         goto err;
 151                 }
 152
 153                 /* Transfer ownership from the objects list to the vmas list. */
 154                 list_add_tail(&vma->exec_list, &eb->vmas);
 155                 list_del_init(&obj->obj_exec_link);
 156
 157                 vma->exec_entry = &exec[i];
 158                 if (eb->and < 0) {
 159                         eb->lut[i] = vma;
 160                 } else {
 161                         uint32_t handle = args->flags & I915_EXEC_HANDLE_LUT ? i : exec[i].handle;
 162                         vma->exec_handle = handle;
 163                         hlist_add_head(&vma->exec_node,
 164                                        &eb->buckets[handle & eb->and]);
 165                 }
 166                 ++i;
 167         }
 168
 169         return 0;
 170
 171
 172 err:
 173         while (!list_empty(&objects)) {
 174                 obj = list_first_entry(&objects,
 175                                        struct drm_i915_gem_object,
 176                                        obj_exec_link);
 177                 list_del_init(&obj->obj_exec_link);
 178                 drm_gem_object_unreference(&obj->base);
 179         }
 180         /*
 181          * Objects already transfered to the vmas list will be unreferenced by
 182          * eb_destroy.
 183          */
 184
 185         return ret;
 186 }
 187
 188 static struct i915_vma *eb_get_vma(struct eb_vmas *eb, unsigned long handle)
 189 {
 190         if (eb->and < 0) {
 191                 if (handle >= -eb->and)
 192                         return NULL;
 193                 return eb->lut[handle];
 194         } else {
 195                 struct hlist_head *head;
 196                 struct i915_vma *vma;
 197
 198                 head = &eb->buckets[handle & eb->and];
 199                 hlist_for_each_entry(vma, head, exec_node) {
 200                         if (vma->exec_handle == handle)
 201                                 return vma;
 202                 }
 203                 return NULL;
 204         }
 205 }
 206
 207 static void
 208 i915_gem_execbuffer_unreserve_vma(struct i915_vma *vma)
 209 {
 210         struct drm_i915_gem_exec_object2 *entry;
 211         struct drm_i915_gem_object *obj = vma->obj;
 212
 213         if (!drm_mm_node_allocated(&vma->node))
 214                 return;
 215
 216         entry = vma->exec_entry;
 217
 218         if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
 219                 i915_gem_object_unpin_fence(obj);
 220
 221         if (entry->flags & __EXEC_OBJECT_HAS_PIN)
 222                 vma->pin_count--;
 223
 224         entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
 225 }
 226
 227 static void eb_destroy(struct eb_vmas *eb)
 228 {
 229         while (!list_empty(&eb->vmas)) {
 230                 struct i915_vma *vma;
 231
 232                 vma = list_first_entry(&eb->vmas,
 233                                        struct i915_vma,
 234                                        exec_list);
 235                 list_del_init(&vma->exec_list);
 236                 i915_gem_execbuffer_unreserve_vma(vma);
 237                 drm_gem_object_unreference(&vma->obj->base);
 238         }
 239         kfree(eb);
 240 }
 241
 242 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
 243 {
 244         return (HAS_LLC(obj->base.dev) ||
 245                 obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
 246                 obj->cache_level != I915_CACHE_NONE);
 247 }
 248
 249 /* Used to convert any address to canonical form.
 250  * Starting from gen8, some commands (e.g. STATE_BASE_ADDRESS,
 251  * MI_LOAD_REGISTER_MEM and others, see Broadwell PRM Vol2a) require the
 252  * addresses to be in a canonical form:
 253  * "GraphicsAddress[63:48] are ignored by the HW and assumed to be in correct
 254  * canonical form [63:48] == [47]."
 255  */
 256 #define GEN8_HIGH_ADDRESS_BIT 47
 257 static inline uint64_t gen8_canonical_addr(uint64_t address)
 258 {
 259         return sign_extend64(address, GEN8_HIGH_ADDRESS_BIT);
 260 }
 261
 262 static inline uint64_t gen8_noncanonical_addr(uint64_t address)
 263 {
 264         return address & ((1ULL << (GEN8_HIGH_ADDRESS_BIT + 1)) - 1);
 265 }
 266
 267 static inline uint64_t
 268 relocation_target(struct drm_i915_gem_relocation_entry *reloc,
 269                   uint64_t target_offset)
 270 {
 271         return gen8_canonical_addr((int)reloc->delta + target_offset);
 272 }
 273
 274 static int
 275 relocate_entry_cpu(struct drm_i915_gem_object *obj,
 276                    struct drm_i915_gem_relocation_entry *reloc,
 277                    uint64_t target_offset)
 278 {
 279         struct drm_device *dev = obj->base.dev;
 280         uint32_t page_offset = offset_in_page(reloc->offset);
 281         uint64_t delta = relocation_target(reloc, target_offset);
 282         char *vaddr;
 283         int ret;
 284
 285         ret = i915_gem_object_set_to_cpu_domain(obj, true);
 286         if (ret)
 287                 return ret;
 288
 289         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 290                                 reloc->offset >> PAGE_SHIFT));
 291         *(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
 292
 293         if (INTEL_INFO(dev)->gen >= 8) {
 294                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 295
 296                 if (page_offset == 0) {
 297                         kunmap_atomic(vaddr);
 298                         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 299                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 300                 }
 301
 302                 *(uint32_t *)(vaddr + page_offset) = upper_32_bits(delta);
 303         }
 304
 305         kunmap_atomic(vaddr);
 306
 307         return 0;
 308 }
 309
 310 static int
 311 relocate_entry_gtt(struct drm_i915_gem_object *obj,
 312                    struct drm_i915_gem_relocation_entry *reloc,
 313                    uint64_t target_offset)
 314 {
 315         struct drm_device *dev = obj->base.dev;
 316         struct drm_i915_private *dev_priv = to_i915(dev);
 317         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 318         uint64_t delta = relocation_target(reloc, target_offset);
 319         uint64_t offset;
 320         void __iomem *reloc_page;
 321         int ret;
 322
 323         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 324         if (ret)
 325                 return ret;
 326
 327         ret = i915_gem_object_put_fence(obj);
 328         if (ret)
 329                 return ret;
 330
 331         /* Map the page containing the relocation we're going to perform.  */
 332         offset = i915_gem_obj_ggtt_offset(obj);
 333         offset += reloc->offset;
 334         reloc_page = io_mapping_map_atomic_wc(ggtt->mappable,
 335                                               offset & PAGE_MASK);
 336         iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
 337
 338         if (INTEL_INFO(dev)->gen >= 8) {
 339                 offset += sizeof(uint32_t);
 340
 341                 if (offset_in_page(offset) == 0) {
 342                         io_mapping_unmap_atomic(reloc_page);
 343                         reloc_page =
 344                                 io_mapping_map_atomic_wc(ggtt->mappable,
 345                                                          offset);
 346                 }
 347
 348                 iowrite32(upper_32_bits(delta),
 349                           reloc_page + offset_in_page(offset));
 350         }
 351
 352         io_mapping_unmap_atomic(reloc_page);
 353
 354         return 0;
 355 }
 356
 357 static void
 358 clflush_write32(void *addr, uint32_t value)
 359 {
 360         /* This is not a fast path, so KISS. */
 361         drm_clflush_virt_range(addr, sizeof(uint32_t));
 362         *(uint32_t *)addr = value;
 363         drm_clflush_virt_range(addr, sizeof(uint32_t));
 364 }
 365
 366 static int
 367 relocate_entry_clflush(struct drm_i915_gem_object *obj,
 368                        struct drm_i915_gem_relocation_entry *reloc,
 369                        uint64_t target_offset)
 370 {
 371         struct drm_device *dev = obj->base.dev;
 372         uint32_t page_offset = offset_in_page(reloc->offset);
 373         uint64_t delta = relocation_target(reloc, target_offset);
 374         char *vaddr;
 375         int ret;
 376
 377         ret = i915_gem_object_set_to_gtt_domain(obj, true);
 378         if (ret)
 379                 return ret;
 380
 381         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 382                                 reloc->offset >> PAGE_SHIFT));
 383         clflush_write32(vaddr + page_offset, lower_32_bits(delta));
 384
 385         if (INTEL_INFO(dev)->gen >= 8) {
 386                 page_offset = offset_in_page(page_offset + sizeof(uint32_t));
 387
 388                 if (page_offset == 0) {
 389                         kunmap_atomic(vaddr);
 390                         vaddr = kmap_atomic(i915_gem_object_get_dirty_page(obj,
 391                             (reloc->offset + sizeof(uint32_t)) >> PAGE_SHIFT));
 392                 }
 393
 394                 clflush_write32(vaddr + page_offset, upper_32_bits(delta));
 395         }
 396
 397         kunmap_atomic(vaddr);
 398
 399         return 0;
 400 }
 401
 402 static int
 403 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
 404                                    struct eb_vmas *eb,
 405                                    struct drm_i915_gem_relocation_entry *reloc)
 406 {
 407         struct drm_device *dev = obj->base.dev;
 408         struct drm_gem_object *target_obj;
 409         struct drm_i915_gem_object *target_i915_obj;
 410         struct i915_vma *target_vma;
 411         uint64_t target_offset;
 412         int ret;
 413
 414         /* we've already hold a reference to all valid objects */
 415         target_vma = eb_get_vma(eb, reloc->target_handle);
 416         if (unlikely(target_vma == NULL))
 417                 return -ENOENT;
 418         target_i915_obj = target_vma->obj;
 419         target_obj = &target_vma->obj->base;
 420
 421         target_offset = gen8_canonical_addr(target_vma->node.start);
 422
 423         /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
 424          * pipe_control writes because the gpu doesn't properly redirect them
 425          * through the ppgtt for non_secure batchbuffers. */
 426         if (unlikely(IS_GEN6(dev) &&
 427             reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
 428                 ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
 429                                     PIN_GLOBAL);
 430                 if (WARN_ONCE(ret, "Unexpected failure to bind target VMA!"))
 431                         return ret;
 432         }
 433
 434         /* Validate that the target is in a valid r/w GPU domain */
 435         if (unlikely(reloc->write_domain & (reloc->write_domain - 1))) {
 436                 DRM_DEBUG("reloc with multiple write domains: "
 437                           "obj %p target %d offset %d "
 438                           "read %08x write %08x",
 439                           obj, reloc->target_handle,
 440                           (int) reloc->offset,
 441                           reloc->read_domains,
 442                           reloc->write_domain);
 443                 return -EINVAL;
 444         }
 445         if (unlikely((reloc->write_domain | reloc->read_domains)
 446                      & ~I915_GEM_GPU_DOMAINS)) {
 447                 DRM_DEBUG("reloc with read/write non-GPU domains: "
 448                           "obj %p target %d offset %d "
 449                           "read %08x write %08x",
 450                           obj, reloc->target_handle,
 451                           (int) reloc->offset,
 452                           reloc->read_domains,
 453                           reloc->write_domain);
 454                 return -EINVAL;
 455         }
 456
 457         target_obj->pending_read_domains |= reloc->read_domains;
 458         target_obj->pending_write_domain |= reloc->write_domain;
 459
 460         /* If the relocation already has the right value in it, no
 461          * more work needs to be done.
 462          */
 463         if (target_offset == reloc->presumed_offset)
 464                 return 0;
 465
 466         /* Check that the relocation address is valid... */
 467         if (unlikely(reloc->offset >
 468                 obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
 469                 DRM_DEBUG("Relocation beyond object bounds: "
 470                           "obj %p target %d offset %d size %d.\n",
 471                           obj, reloc->target_handle,
 472                           (int) reloc->offset,
 473                           (int) obj->base.size);
 474                 return -EINVAL;
 475         }
 476         if (unlikely(reloc->offset & 3)) {
 477                 DRM_DEBUG("Relocation not 4-byte aligned: "
 478                           "obj %p target %d offset %d.\n",
 479                           obj, reloc->target_handle,
 480                           (int) reloc->offset);
 481                 return -EINVAL;
 482         }
 483
 484         /* We can't wait for rendering with pagefaults disabled */
 485         if (obj->active && pagefault_disabled())
 486                 return -EFAULT;
 487
 488         if (use_cpu_reloc(obj))
 489                 ret = relocate_entry_cpu(obj, reloc, target_offset);
 490         else if (obj->map_and_fenceable)
 491                 ret = relocate_entry_gtt(obj, reloc, target_offset);
 492         else if (cpu_has_clflush)
 493                 ret = relocate_entry_clflush(obj, reloc, target_offset);
 494         else {
 495                 WARN_ONCE(1, "Impossible case in relocation handling\n");
 496                 ret = -ENODEV;
 497         }
 498
 499         if (ret)
 500                 return ret;
 501
 502         /* and update the user's relocation entry */
 503         reloc->presumed_offset = target_offset;
 504
 505         return 0;
 506 }
 507
 508 static int
 509 i915_gem_execbuffer_relocate_vma(struct i915_vma *vma,
 510                                  struct eb_vmas *eb)
 511 {
 512 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
 513         struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
 514         struct drm_i915_gem_relocation_entry __user *user_relocs;
 515         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 516         int remain, ret;
 517
 518         user_relocs = to_user_ptr(entry->relocs_ptr);
 519
 520         remain = entry->relocation_count;
 521         while (remain) {
 522                 struct drm_i915_gem_relocation_entry *r = stack_reloc;
 523                 int count = remain;
 524                 if (count > ARRAY_SIZE(stack_reloc))
 525                         count = ARRAY_SIZE(stack_reloc);
 526                 remain -= count;
 527
 528                 if (__copy_from_user_inatomic(r, user_relocs, count*sizeof(r[0])))
 529                         return -EFAULT;
 530
 531                 do {
 532                         u64 offset = r->presumed_offset;
 533
 534                         ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, r);
 535                         if (ret)
 536                                 return ret;
 537
 538                         if (r->presumed_offset != offset &&
 539                             __copy_to_user_inatomic(&user_relocs->presumed_offset,
 540                                                     &r->presumed_offset,
 541                                                     sizeof(r->presumed_offset))) {
 542                                 return -EFAULT;
 543                         }
 544
 545                         user_relocs++;
 546                         r++;
 547                 } while (--count);
 548         }
 549
 550         return 0;
 551 #undef N_RELOC
 552 }
 553
 554 static int
 555 i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
 556                                       struct eb_vmas *eb,
 557                                       struct drm_i915_gem_relocation_entry *relocs)
 558 {
 559         const struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 560         int i, ret;
 561
 562         for (i = 0; i < entry->relocation_count; i++) {
 563                 ret = i915_gem_execbuffer_relocate_entry(vma->obj, eb, &relocs[i]);
 564                 if (ret)
 565                         return ret;
 566         }
 567
 568         return 0;
 569 }
 570
 571 static int
 572 i915_gem_execbuffer_relocate(struct eb_vmas *eb)
 573 {
 574         struct i915_vma *vma;
 575         int ret = 0;
 576
 577         /* This is the fast path and we cannot handle a pagefault whilst
 578          * holding the struct mutex lest the user pass in the relocations
 579          * contained within a mmaped bo. For in such a case we, the page
 580          * fault handler would call i915_gem_fault() and we would try to
 581          * acquire the struct mutex again. Obviously this is bad and so
 582          * lockdep complains vehemently.
 583          */
 584         pagefault_disable();
 585         list_for_each_entry(vma, &eb->vmas, exec_list) {
 586                 ret = i915_gem_execbuffer_relocate_vma(vma, eb);
 587                 if (ret)
 588                         break;
 589         }
 590         pagefault_enable();
 591
 592         return ret;
 593 }
 594
 595 static bool only_mappable_for_reloc(unsigned int flags)
 596 {
 597         return (flags & (EXEC_OBJECT_NEEDS_FENCE | __EXEC_OBJECT_NEEDS_MAP)) ==
 598                 __EXEC_OBJECT_NEEDS_MAP;
 599 }
 600
 601 static int
 602 i915_gem_execbuffer_reserve_vma(struct i915_vma *vma,
 603                                 struct intel_engine_cs *engine,
 604                                 bool *need_reloc)
 605 {
 606         struct drm_i915_gem_object *obj = vma->obj;
 607         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 608         uint64_t flags;
 609         int ret;
 610
 611         flags = PIN_USER;
 612         if (entry->flags & EXEC_OBJECT_NEEDS_GTT)
 613                 flags |= PIN_GLOBAL;
 614
 615         if (!drm_mm_node_allocated(&vma->node)) {
 616                 /* Wa32bitGeneralStateOffset & Wa32bitInstructionBaseOffset,
 617                  * limit address to the first 4GBs for unflagged objects.
 618                  */
 619                 if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0)
 620                         flags |= PIN_ZONE_4G;
 621                 if (entry->flags & __EXEC_OBJECT_NEEDS_MAP)
 622                         flags |= PIN_GLOBAL | PIN_MAPPABLE;
 623                 if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS)
 624                         flags |= BATCH_OFFSET_BIAS | PIN_OFFSET_BIAS;
 625                 if (entry->flags & EXEC_OBJECT_PINNED)
 626                         flags |= entry->offset | PIN_OFFSET_FIXED;
 627                 if ((flags & PIN_MAPPABLE) == 0)
 628                         flags |= PIN_HIGH;
 629         }
 630
 631         ret = i915_gem_object_pin(obj, vma->vm, entry->alignment, flags);
 632         if ((ret == -ENOSPC  || ret == -E2BIG) &&
 633             only_mappable_for_reloc(entry->flags))
 634                 ret = i915_gem_object_pin(obj, vma->vm,
 635                                           entry->alignment,
 636                                           flags & ~PIN_MAPPABLE);
 637         if (ret)
 638                 return ret;
 639
 640         entry->flags |= __EXEC_OBJECT_HAS_PIN;
 641
 642         if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
 643                 ret = i915_gem_object_get_fence(obj);
 644                 if (ret)
 645                         return ret;
 646
 647                 if (i915_gem_object_pin_fence(obj))
 648                         entry->flags |= __EXEC_OBJECT_HAS_FENCE;
 649         }
 650
 651         if (entry->offset != vma->node.start) {
 652                 entry->offset = vma->node.start;
 653                 *need_reloc = true;
 654         }
 655
 656         if (entry->flags & EXEC_OBJECT_WRITE) {
 657                 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
 658                 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
 659         }
 660
 661         return 0;
 662 }
 663
 664 static bool
 665 need_reloc_mappable(struct i915_vma *vma)
 666 {
 667         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 668
 669         if (entry->relocation_count == 0)
 670                 return false;
 671
 672         if (!vma->is_ggtt)
 673                 return false;
 674
 675         /* See also use_cpu_reloc() */
 676         if (HAS_LLC(vma->obj->base.dev))
 677                 return false;
 678
 679         if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
 680                 return false;
 681
 682         return true;
 683 }
 684
 685 static bool
 686 eb_vma_misplaced(struct i915_vma *vma)
 687 {
 688         struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
 689         struct drm_i915_gem_object *obj = vma->obj;
 690
 691         WARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !vma->is_ggtt);
 692
 693         if (entry->alignment &&
 694             vma->node.start & (entry->alignment - 1))
 695                 return true;
 696
 697         if (entry->flags & EXEC_OBJECT_PINNED &&
 698             vma->node.start != entry->offset)
 699                 return true;
 700
 701         if (entry->flags & __EXEC_OBJECT_NEEDS_BIAS &&
 702             vma->node.start < BATCH_OFFSET_BIAS)
 703                 return true;
 704
 705         /* avoid costly ping-pong once a batch bo ended up non-mappable */
 706         if (entry->flags & __EXEC_OBJECT_NEEDS_MAP && !obj->map_and_fenceable)
 707                 return !only_mappable_for_reloc(entry->flags);
 708
 709         if ((entry->flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) == 0 &&
 710             (vma->node.start + vma->node.size - 1) >> 32)
 711                 return true;
 712
 713         return false;
 714 }
 715
 716 static int
 717 i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
 718                             struct list_head *vmas,
 719                             struct i915_gem_context *ctx,
 720                             bool *need_relocs)
 721 {
 722         struct drm_i915_gem_object *obj;
 723         struct i915_vma *vma;
 724         struct i915_address_space *vm;
 725         struct list_head ordered_vmas;
 726         struct list_head pinned_vmas;
 727         bool has_fenced_gpu_access = INTEL_GEN(engine->i915) < 4;
 728         int retry;
 729
 730         i915_gem_retire_requests_ring(engine);
 731
 732         vm = list_first_entry(vmas, struct i915_vma, exec_list)->vm;
 733
 734         INIT_LIST_HEAD(&ordered_vmas);
 735         INIT_LIST_HEAD(&pinned_vmas);
 736         while (!list_empty(vmas)) {
 737                 struct drm_i915_gem_exec_object2 *entry;
 738                 bool need_fence, need_mappable;
 739
 740                 vma = list_first_entry(vmas, struct i915_vma, exec_list);
 741                 obj = vma->obj;
 742                 entry = vma->exec_entry;
 743
 744                 if (ctx->flags & CONTEXT_NO_ZEROMAP)
 745                         entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
 746
 747                 if (!has_fenced_gpu_access)
 748                         entry->flags &= ~EXEC_OBJECT_NEEDS_FENCE;
 749                 need_fence =
 750                         entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
 751                         obj->tiling_mode != I915_TILING_NONE;
 752                 need_mappable = need_fence || need_reloc_mappable(vma);
 753
 754                 if (entry->flags & EXEC_OBJECT_PINNED)
 755                         list_move_tail(&vma->exec_list, &pinned_vmas);
 756                 else if (need_mappable) {
 757                         entry->flags |= __EXEC_OBJECT_NEEDS_MAP;
 758                         list_move(&vma->exec_list, &ordered_vmas);
 759                 } else
 760                         list_move_tail(&vma->exec_list, &ordered_vmas);
 761
 762                 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
 763                 obj->base.pending_write_domain = 0;
 764         }
 765         list_splice(&ordered_vmas, vmas);
 766         list_splice(&pinned_vmas, vmas);
 767
 768         /* Attempt to pin all of the buffers into the GTT.
 769          * This is done in 3 phases:
 770          *
 771          * 1a. Unbind all objects that do not match the GTT constraints for
 772          *     the execbuffer (fenceable, mappable, alignment etc).
 773          * 1b. Increment pin count for already bound objects.
 774          * 2.  Bind new objects.
 775          * 3.  Decrement pin count.
 776          *
 777          * This avoid unnecessary unbinding of later objects in order to make
 778          * room for the earlier objects *unless* we need to defragment.
 779          */
 780         retry = 0;
 781         do {
 782                 int ret = 0;
 783
 784                 /* Unbind any ill-fitting objects or pin. */
 785                 list_for_each_entry(vma, vmas, exec_list) {
 786                         if (!drm_mm_node_allocated(&vma->node))
 787                                 continue;
 788
 789                         if (eb_vma_misplaced(vma))
 790                                 ret = i915_vma_unbind(vma);
 791                         else
 792                                 ret = i915_gem_execbuffer_reserve_vma(vma,
 793                                                                       engine,
 794                                                                       need_relocs);
 795                         if (ret)
 796                                 goto err;
 797                 }
 798
 799                 /* Bind fresh objects */
 800                 list_for_each_entry(vma, vmas, exec_list) {
 801                         if (drm_mm_node_allocated(&vma->node))
 802                                 continue;
 803
 804                         ret = i915_gem_execbuffer_reserve_vma(vma, engine,
 805                                                               need_relocs);
 806                         if (ret)
 807                                 goto err;
 808                 }
 809
 810 err:
 811                 if (ret != -ENOSPC || retry++)
 812                         return ret;
 813
 814                 /* Decrement pin count for bound objects */
 815                 list_for_each_entry(vma, vmas, exec_list)
 816                         i915_gem_execbuffer_unreserve_vma(vma);
 817
 818                 ret = i915_gem_evict_vm(vm, true);
 819                 if (ret)
 820                         return ret;
 821         } while (1);
 822 }
 823
 824 static int
 825 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
 826                                   struct drm_i915_gem_execbuffer2 *args,
 827                                   struct drm_file *file,
 828                                   struct intel_engine_cs *engine,
 829                                   struct eb_vmas *eb,
 830                                   struct drm_i915_gem_exec_object2 *exec,
 831                                   struct i915_gem_context *ctx)
 832 {
 833         struct drm_i915_gem_relocation_entry *reloc;
 834         struct i915_address_space *vm;
 835         struct i915_vma *vma;
 836         bool need_relocs;
 837         int *reloc_offset;
 838         int i, total, ret;
 839         unsigned count = args->buffer_count;
 840
 841         vm = list_first_entry(&eb->vmas, struct i915_vma, exec_list)->vm;
 842
 843         /* We may process another execbuffer during the unlock... */
 844         while (!list_empty(&eb->vmas)) {
 845                 vma = list_first_entry(&eb->vmas, struct i915_vma, exec_list);
 846                 list_del_init(&vma->exec_list);
 847                 i915_gem_execbuffer_unreserve_vma(vma);
 848                 drm_gem_object_unreference(&vma->obj->base);
 849         }
 850
 851         mutex_unlock(&dev->struct_mutex);
 852
 853         total = 0;
 854         for (i = 0; i < count; i++)
 855                 total += exec[i].relocation_count;
 856
 857         reloc_offset = drm_malloc_ab(count, sizeof(*reloc_offset));
 858         reloc = drm_malloc_ab(total, sizeof(*reloc));
 859         if (reloc == NULL || reloc_offset == NULL) {
 860                 drm_free_large(reloc);
 861                 drm_free_large(reloc_offset);
 862                 mutex_lock(&dev->struct_mutex);
 863                 return -ENOMEM;
 864         }
 865
 866         total = 0;
 867         for (i = 0; i < count; i++) {
 868                 struct drm_i915_gem_relocation_entry __user *user_relocs;
 869                 u64 invalid_offset = (u64)-1;
 870                 int j;
 871
 872                 user_relocs = to_user_ptr(exec[i].relocs_ptr);
 873
 874                 if (copy_from_user(reloc+total, user_relocs,
 875                                    exec[i].relocation_count * sizeof(*reloc))) {
 876                         ret = -EFAULT;
 877                         mutex_lock(&dev->struct_mutex);
 878                         goto err;
 879                 }
 880
 881                 /* As we do not update the known relocation offsets after
 882                  * relocating (due to the complexities in lock handling),
 883                  * we need to mark them as invalid now so that we force the
 884                  * relocation processing next time. Just in case the target
 885                  * object is evicted and then rebound into its old
 886                  * presumed_offset before the next execbuffer - if that
 887                  * happened we would make the mistake of assuming that the
 888                  * relocations were valid.
 889                  */
 890                 for (j = 0; j < exec[i].relocation_count; j++) {
 891                         if (__copy_to_user(&user_relocs[j].presumed_offset,
 892                                            &invalid_offset,
 893                                            sizeof(invalid_offset))) {
 894                                 ret = -EFAULT;
 895                                 mutex_lock(&dev->struct_mutex);
 896                                 goto err;
 897                         }
 898                 }
 899
 900                 reloc_offset[i] = total;
 901                 total += exec[i].relocation_count;
 902         }
 903
 904         ret = i915_mutex_lock_interruptible(dev);
 905         if (ret) {
 906                 mutex_lock(&dev->struct_mutex);
 907                 goto err;
 908         }
 909
 910         /* reacquire the objects */
 911         eb_reset(eb);
 912         ret = eb_lookup_vmas(eb, exec, args, vm, file);
 913         if (ret)
 914                 goto err;
 915
 916         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
 917         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
 918                                           &need_relocs);
 919         if (ret)
 920                 goto err;
 921
 922         list_for_each_entry(vma, &eb->vmas, exec_list) {
 923                 int offset = vma->exec_entry - exec;
 924                 ret = i915_gem_execbuffer_relocate_vma_slow(vma, eb,
 925                                                             reloc + reloc_offset[offset]);
 926                 if (ret)
 927                         goto err;
 928         }
 929
 930         /* Leave the user relocations as are, this is the painfully slow path,
 931          * and we want to avoid the complication of dropping the lock whilst
 932          * having buffers reserved in the aperture and so causing spurious
 933          * ENOSPC for random operations.
 934          */
 935
 936 err:
 937         drm_free_large(reloc);
 938         drm_free_large(reloc_offset);
 939         return ret;
 940 }
 941
 942 static int
 943 i915_gem_execbuffer_move_to_gpu(struct drm_i915_gem_request *req,
 944                                 struct list_head *vmas)
 945 {
 946         const unsigned other_rings = ~intel_engine_flag(req->engine);
 947         struct i915_vma *vma;
 948         uint32_t flush_domains = 0;
 949         bool flush_chipset = false;
 950         int ret;
 951
 952         list_for_each_entry(vma, vmas, exec_list) {
 953                 struct drm_i915_gem_object *obj = vma->obj;
 954
 955                 if (obj->active & other_rings) {
 956                         ret = i915_gem_object_sync(obj, req->engine, &req);
 957                         if (ret)
 958                                 return ret;
 959                 }
 960
 961                 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
 962                         flush_chipset |= i915_gem_clflush_object(obj, false);
 963
 964                 flush_domains |= obj->base.write_domain;
 965         }
 966
 967         if (flush_chipset)
 968                 i915_gem_chipset_flush(req->engine->i915);
 969
 970         if (flush_domains & I915_GEM_DOMAIN_GTT)
 971                 wmb();
 972
 973         /* Unconditionally invalidate gpu caches and ensure that we do flush
 974          * any residual writes from the previous batch.
 975          */
 976         return intel_ring_invalidate_all_caches(req);
 977 }
 978
 979 static bool
 980 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
 981 {
 982         if (exec->flags & __I915_EXEC_UNKNOWN_FLAGS)
 983                 return false;
 984
 985         /* Kernel clipping was a DRI1 misfeature */
 986         if (exec->num_cliprects || exec->cliprects_ptr)
 987                 return false;
 988
 989         if (exec->DR4 == 0xffffffff) {
 990                 DRM_DEBUG("UXA submitting garbage DR4, fixing up\n");
 991                 exec->DR4 = 0;
 992         }
 993         if (exec->DR1 || exec->DR4)
 994                 return false;
 995
 996         if ((exec->batch_start_offset | exec->batch_len) & 0x7)
 997                 return false;
 998
 999         return true;
1000 }
1001
1002 static int
1003 validate_exec_list(struct drm_device *dev,
1004                    struct drm_i915_gem_exec_object2 *exec,
1005                    int count)
1006 {
1007         unsigned relocs_total = 0;
1008         unsigned relocs_max = UINT_MAX / sizeof(struct drm_i915_gem_relocation_entry);
1009         unsigned invalid_flags;
1010         int i;
1011
1012         invalid_flags = __EXEC_OBJECT_UNKNOWN_FLAGS;
1013         if (USES_FULL_PPGTT(dev))
1014                 invalid_flags |= EXEC_OBJECT_NEEDS_GTT;
1015
1016         for (i = 0; i < count; i++) {
1017                 char __user *ptr = to_user_ptr(exec[i].relocs_ptr);
1018                 int length; /* limited by fault_in_pages_readable() */
1019
1020                 if (exec[i].flags & invalid_flags)
1021                         return -EINVAL;
1022
1023                 /* Offset can be used as input (EXEC_OBJECT_PINNED), reject
1024                  * any non-page-aligned or non-canonical addresses.
1025                  */
1026                 if (exec[i].flags & EXEC_OBJECT_PINNED) {
1027                         if (exec[i].offset !=
1028                             gen8_canonical_addr(exec[i].offset & PAGE_MASK))
1029                                 return -EINVAL;
1030
1031                         /* From drm_mm perspective address space is continuous,
1032                          * so from this point we're always using non-canonical
1033                          * form internally.
1034                          */
1035                         exec[i].offset = gen8_noncanonical_addr(exec[i].offset);
1036                 }
1037
1038                 if (exec[i].alignment && !is_power_of_2(exec[i].alignment))
1039                         return -EINVAL;
1040
1041                 /* First check for malicious input causing overflow in
1042                  * the worst case where we need to allocate the entire
1043                  * relocation tree as a single array.
1044                  */
1045                 if (exec[i].relocation_count > relocs_max - relocs_total)
1046                         return -EINVAL;
1047                 relocs_total += exec[i].relocation_count;
1048
1049                 length = exec[i].relocation_count *
1050                         sizeof(struct drm_i915_gem_relocation_entry);
1051                 /*
1052                  * We must check that the entire relocation array is safe
1053                  * to read, but since we may need to update the presumed
1054                  * offsets during execution, check for full write access.
1055                  */
1056                 if (!access_ok(VERIFY_WRITE, ptr, length))
1057                         return -EFAULT;
1058
1059                 if (likely(!i915.prefault_disable)) {
1060                         if (fault_in_multipages_readable(ptr, length))
1061                                 return -EFAULT;
1062                 }
1063         }
1064
1065         return 0;
1066 }
1067
1068 static struct i915_gem_context *
1069 i915_gem_validate_context(struct drm_device *dev, struct drm_file *file,
1070                           struct intel_engine_cs *engine, const u32 ctx_id)
1071 {
1072         struct i915_gem_context *ctx = NULL;
1073         struct i915_ctx_hang_stats *hs;
1074
1075         if (engine->id != RCS && ctx_id != DEFAULT_CONTEXT_HANDLE)
1076                 return ERR_PTR(-EINVAL);
1077
1078         ctx = i915_gem_context_lookup(file->driver_priv, ctx_id);
1079         if (IS_ERR(ctx))
1080                 return ctx;
1081
1082         hs = &ctx->hang_stats;
1083         if (hs->banned) {
1084                 DRM_DEBUG("Context %u tried to submit while banned\n", ctx_id);
1085                 return ERR_PTR(-EIO);
1086         }
1087
1088         return ctx;
1089 }
1090
1091 void
1092 i915_gem_execbuffer_move_to_active(struct list_head *vmas,
1093                                    struct drm_i915_gem_request *req)
1094 {
1095         struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
1096         struct i915_vma *vma;
1097
1098         list_for_each_entry(vma, vmas, exec_list) {
1099                 struct drm_i915_gem_exec_object2 *entry = vma->exec_entry;
1100                 struct drm_i915_gem_object *obj = vma->obj;
1101                 u32 old_read = obj->base.read_domains;
1102                 u32 old_write = obj->base.write_domain;
1103
1104                 obj->dirty = 1; /* be paranoid  */
1105                 obj->base.write_domain = obj->base.pending_write_domain;
1106                 if (obj->base.write_domain == 0)
1107                         obj->base.pending_read_domains |= obj->base.read_domains;
1108                 obj->base.read_domains = obj->base.pending_read_domains;
1109
1110                 i915_vma_move_to_active(vma, req);
1111                 if (obj->base.write_domain) {
1112                         i915_gem_request_assign(&obj->last_write_req, req);
1113
1114                         intel_fb_obj_invalidate(obj, ORIGIN_CS);
1115
1116                         /* update for the implicit flush after a batch */
1117                         obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS;
1118                 }
1119                 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
1120                         i915_gem_request_assign(&obj->last_fenced_req, req);
1121                         if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
1122                                 struct drm_i915_private *dev_priv = engine->i915;
1123                                 list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
1124                                                &dev_priv->mm.fence_list);
1125                         }
1126                 }
1127
1128                 trace_i915_gem_object_change_domain(obj, old_read, old_write);
1129         }
1130 }
1131
1132 static void
1133 i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params)
1134 {
1135         /* Unconditionally force add_request to emit a full flush. */
1136         params->engine->gpu_caches_dirty = true;
1137
1138         /* Add a breadcrumb for the completion of the batch buffer */
1139         __i915_add_request(params->request, params->batch_obj, true);
1140 }
1141
1142 static int
1143 i915_reset_gen7_sol_offsets(struct drm_device *dev,
1144                             struct drm_i915_gem_request *req)
1145 {
1146         struct intel_engine_cs *engine = req->engine;
1147         struct drm_i915_private *dev_priv = dev->dev_private;
1148         int ret, i;
1149
1150         if (!IS_GEN7(dev) || engine != &dev_priv->engine[RCS]) {
1151                 DRM_DEBUG("sol reset is gen7/rcs only\n");
1152                 return -EINVAL;
1153         }
1154
1155         ret = intel_ring_begin(req, 4 * 3);
1156         if (ret)
1157                 return ret;
1158
1159         for (i = 0; i < 4; i++) {
1160                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
1161                 intel_ring_emit_reg(engine, GEN7_SO_WRITE_OFFSET(i));
1162                 intel_ring_emit(engine, 0);
1163         }
1164
1165         intel_ring_advance(engine);
1166
1167         return 0;
1168 }
1169
1170 static struct drm_i915_gem_object*
1171 i915_gem_execbuffer_parse(struct intel_engine_cs *engine,
1172                           struct drm_i915_gem_exec_object2 *shadow_exec_entry,
1173                           struct eb_vmas *eb,
1174                           struct drm_i915_gem_object *batch_obj,
1175                           u32 batch_start_offset,
1176                           u32 batch_len,
1177                           bool is_master)
1178 {
1179         struct drm_i915_gem_object *shadow_batch_obj;
1180         struct i915_vma *vma;
1181         int ret;
1182
1183         shadow_batch_obj = i915_gem_batch_pool_get(&engine->batch_pool,
1184                                                    PAGE_ALIGN(batch_len));
1185         if (IS_ERR(shadow_batch_obj))
1186                 return shadow_batch_obj;
1187
1188         ret = i915_parse_cmds(engine,
1189                               batch_obj,
1190                               shadow_batch_obj,
1191                               batch_start_offset,
1192                               batch_len,
1193                               is_master);
1194         if (ret)
1195                 goto err;
1196
1197         ret = i915_gem_obj_ggtt_pin(shadow_batch_obj, 0, 0);
1198         if (ret)
1199                 goto err;
1200
1201         i915_gem_object_unpin_pages(shadow_batch_obj);
1202
1203         memset(shadow_exec_entry, 0, sizeof(*shadow_exec_entry));
1204
1205         vma = i915_gem_obj_to_ggtt(shadow_batch_obj);
1206         vma->exec_entry = shadow_exec_entry;
1207         vma->exec_entry->flags = __EXEC_OBJECT_HAS_PIN;
1208         drm_gem_object_reference(&shadow_batch_obj->base);
1209         list_add_tail(&vma->exec_list, &eb->vmas);
1210
1211         shadow_batch_obj->base.pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1212
1213         return shadow_batch_obj;
1214
1215 err:
1216         i915_gem_object_unpin_pages(shadow_batch_obj);
1217         if (ret == -EACCES) /* unhandled chained batch */
1218                 return batch_obj;
1219         else
1220                 return ERR_PTR(ret);
1221 }
1222
1223 int
1224 i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
1225                                struct drm_i915_gem_execbuffer2 *args,
1226                                struct list_head *vmas)
1227 {
1228         struct drm_device *dev = params->dev;
1229         struct intel_engine_cs *engine = params->engine;
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         u64 exec_start, exec_len;
1232         int instp_mode;
1233         u32 instp_mask;
1234         int ret;
1235
1236         ret = i915_gem_execbuffer_move_to_gpu(params->request, vmas);
1237         if (ret)
1238                 return ret;
1239
1240         ret = i915_switch_context(params->request);
1241         if (ret)
1242                 return ret;
1243
1244         WARN(params->ctx->ppgtt && params->ctx->ppgtt->pd_dirty_rings & (1<<engine->id),
1245              "%s didn't clear reload\n", engine->name);
1246
1247         instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK;
1248         instp_mask = I915_EXEC_CONSTANTS_MASK;
1249         switch (instp_mode) {
1250         case I915_EXEC_CONSTANTS_REL_GENERAL:
1251         case I915_EXEC_CONSTANTS_ABSOLUTE:
1252         case I915_EXEC_CONSTANTS_REL_SURFACE:
1253                 if (instp_mode != 0 && engine != &dev_priv->engine[RCS]) {
1254                         DRM_DEBUG("non-0 rel constants mode on non-RCS\n");
1255                         return -EINVAL;
1256                 }
1257
1258                 if (instp_mode != dev_priv->relative_constants_mode) {
1259                         if (INTEL_INFO(dev)->gen < 4) {
1260                                 DRM_DEBUG("no rel constants on pre-gen4\n");
1261                                 return -EINVAL;
1262                         }
1263
1264                         if (INTEL_INFO(dev)->gen > 5 &&
1265                             instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) {
1266                                 DRM_DEBUG("rel surface constants mode invalid on gen5+\n");
1267                                 return -EINVAL;
1268                         }
1269
1270                         /* The HW changed the meaning on this bit on gen6 */
1271                         if (INTEL_INFO(dev)->gen >= 6)
1272                                 instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
1273                 }
1274                 break;
1275         default:
1276                 DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode);
1277                 return -EINVAL;
1278         }
1279
1280         if (engine == &dev_priv->engine[RCS] &&
1281             instp_mode != dev_priv->relative_constants_mode) {
1282                 ret = intel_ring_begin(params->request, 4);
1283                 if (ret)
1284                         return ret;
1285
1286                 intel_ring_emit(engine, MI_NOOP);
1287                 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
1288                 intel_ring_emit_reg(engine, INSTPM);
1289                 intel_ring_emit(engine, instp_mask << 16 | instp_mode);
1290                 intel_ring_advance(engine);
1291
1292                 dev_priv->relative_constants_mode = instp_mode;
1293         }
1294
1295         if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1296                 ret = i915_reset_gen7_sol_offsets(dev, params->request);
1297                 if (ret)
1298                         return ret;
1299         }
1300
1301         exec_len   = args->batch_len;
1302         exec_start = params->batch_obj_vm_offset +
1303                      params->args_batch_start_offset;
1304
1305         if (exec_len == 0)
1306                 exec_len = params->batch_obj->base.size;
1307
1308         ret = engine->dispatch_execbuffer(params->request,
1309                                         exec_start, exec_len,
1310                                         params->dispatch_flags);
1311         if (ret)
1312                 return ret;
1313
1314         trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags);
1315
1316         i915_gem_execbuffer_move_to_active(vmas, params->request);
1317
1318         return 0;
1319 }
1320
1321 /**
1322  * Find one BSD ring to dispatch the corresponding BSD command.
1323  * The ring index is returned.
1324  */
1325 static unsigned int
1326 gen8_dispatch_bsd_ring(struct drm_i915_private *dev_priv, struct drm_file *file)
1327 {
1328         struct drm_i915_file_private *file_priv = file->driver_priv;
1329
1330         /* Check whether the file_priv has already selected one ring. */
1331         if ((int)file_priv->bsd_ring < 0) {
1332                 /* If not, use the ping-pong mechanism to select one. */
1333                 mutex_lock(&dev_priv->dev->struct_mutex);
1334                 file_priv->bsd_ring = dev_priv->mm.bsd_ring_dispatch_index;
1335                 dev_priv->mm.bsd_ring_dispatch_index ^= 1;
1336                 mutex_unlock(&dev_priv->dev->struct_mutex);
1337         }
1338
1339         return file_priv->bsd_ring;
1340 }
1341
1342 static struct drm_i915_gem_object *
1343 eb_get_batch(struct eb_vmas *eb)
1344 {
1345         struct i915_vma *vma = list_entry(eb->vmas.prev, typeof(*vma), exec_list);
1346
1347         /*
1348          * SNA is doing fancy tricks with compressing batch buffers, which leads
1349          * to negative relocation deltas. Usually that works out ok since the
1350          * relocate address is still positive, except when the batch is placed
1351          * very low in the GTT. Ensure this doesn't happen.
1352          *
1353          * Note that actual hangs have only been observed on gen7, but for
1354          * paranoia do it everywhere.
1355          */
1356         if ((vma->exec_entry->flags & EXEC_OBJECT_PINNED) == 0)
1357                 vma->exec_entry->flags |= __EXEC_OBJECT_NEEDS_BIAS;
1358
1359         return vma->obj;
1360 }
1361
1362 #define I915_USER_RINGS (4)
1363
1364 static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = {
1365         [I915_EXEC_DEFAULT]     = RCS,
1366         [I915_EXEC_RENDER]      = RCS,
1367         [I915_EXEC_BLT]         = BCS,
1368         [I915_EXEC_BSD]         = VCS,
1369         [I915_EXEC_VEBOX]       = VECS
1370 };
1371
1372 static int
1373 eb_select_ring(struct drm_i915_private *dev_priv,
1374                struct drm_file *file,
1375                struct drm_i915_gem_execbuffer2 *args,
1376                struct intel_engine_cs **ring)
1377 {
1378         unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK;
1379
1380         if (user_ring_id > I915_USER_RINGS) {
1381                 DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id);
1382                 return -EINVAL;
1383         }
1384
1385         if ((user_ring_id != I915_EXEC_BSD) &&
1386             ((args->flags & I915_EXEC_BSD_MASK) != 0)) {
1387                 DRM_DEBUG("execbuf with non bsd ring but with invalid "
1388                           "bsd dispatch flags: %d\n", (int)(args->flags));
1389                 return -EINVAL;
1390         }
1391
1392         if (user_ring_id == I915_EXEC_BSD && HAS_BSD2(dev_priv)) {
1393                 unsigned int bsd_idx = args->flags & I915_EXEC_BSD_MASK;
1394
1395                 if (bsd_idx == I915_EXEC_BSD_DEFAULT) {
1396                         bsd_idx = gen8_dispatch_bsd_ring(dev_priv, file);
1397                 } else if (bsd_idx >= I915_EXEC_BSD_RING1 &&
1398                            bsd_idx <= I915_EXEC_BSD_RING2) {
1399                         bsd_idx >>= I915_EXEC_BSD_SHIFT;
1400                         bsd_idx--;
1401                 } else {
1402                         DRM_DEBUG("execbuf with unknown bsd ring: %u\n",
1403                                   bsd_idx);
1404                         return -EINVAL;
1405                 }
1406
1407                 *ring = &dev_priv->engine[_VCS(bsd_idx)];
1408         } else {
1409                 *ring = &dev_priv->engine[user_ring_map[user_ring_id]];
1410         }
1411
1412         if (!intel_engine_initialized(*ring)) {
1413                 DRM_DEBUG("execbuf with invalid ring: %u\n", user_ring_id);
1414                 return -EINVAL;
1415         }
1416
1417         return 0;
1418 }
1419
1420 static int
1421 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1422                        struct drm_file *file,
1423                        struct drm_i915_gem_execbuffer2 *args,
1424                        struct drm_i915_gem_exec_object2 *exec)
1425 {
1426         struct drm_i915_private *dev_priv = to_i915(dev);
1427         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1428         struct drm_i915_gem_request *req = NULL;
1429         struct eb_vmas *eb;
1430         struct drm_i915_gem_object *batch_obj;
1431         struct drm_i915_gem_exec_object2 shadow_exec_entry;
1432         struct intel_engine_cs *engine;
1433         struct i915_gem_context *ctx;
1434         struct i915_address_space *vm;
1435         struct i915_execbuffer_params params_master; /* XXX: will be removed later */
1436         struct i915_execbuffer_params *params = &params_master;
1437         const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1438         u32 dispatch_flags;
1439         int ret;
1440         bool need_relocs;
1441
1442         if (!i915_gem_check_execbuffer(args))
1443                 return -EINVAL;
1444
1445         ret = validate_exec_list(dev, exec, args->buffer_count);
1446         if (ret)
1447                 return ret;
1448
1449         dispatch_flags = 0;
1450         if (args->flags & I915_EXEC_SECURE) {
1451                 if (!file->is_master || !capable(CAP_SYS_ADMIN))
1452                     return -EPERM;
1453
1454                 dispatch_flags |= I915_DISPATCH_SECURE;
1455         }
1456         if (args->flags & I915_EXEC_IS_PINNED)
1457                 dispatch_flags |= I915_DISPATCH_PINNED;
1458
1459         ret = eb_select_ring(dev_priv, file, args, &engine);
1460         if (ret)
1461                 return ret;
1462
1463         if (args->buffer_count < 1) {
1464                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1465                 return -EINVAL;
1466         }
1467
1468         if (args->flags & I915_EXEC_RESOURCE_STREAMER) {
1469                 if (!HAS_RESOURCE_STREAMER(dev)) {
1470                         DRM_DEBUG("RS is only allowed for Haswell, Gen8 and above\n");
1471                         return -EINVAL;
1472                 }
1473                 if (engine->id != RCS) {
1474                         DRM_DEBUG("RS is not available on %s\n",
1475                                  engine->name);
1476                         return -EINVAL;
1477                 }
1478
1479                 dispatch_flags |= I915_DISPATCH_RS;
1480         }
1481
1482         intel_runtime_pm_get(dev_priv);
1483
1484         ret = i915_mutex_lock_interruptible(dev);
1485         if (ret)
1486                 goto pre_mutex_err;
1487
1488         ctx = i915_gem_validate_context(dev, file, engine, ctx_id);
1489         if (IS_ERR(ctx)) {
1490                 mutex_unlock(&dev->struct_mutex);
1491                 ret = PTR_ERR(ctx);
1492                 goto pre_mutex_err;
1493         }
1494
1495         i915_gem_context_reference(ctx);
1496
1497         if (ctx->ppgtt)
1498                 vm = &ctx->ppgtt->base;
1499         else
1500                 vm = &ggtt->base;
1501
1502         memset(&params_master, 0x00, sizeof(params_master));
1503
1504         eb = eb_create(args);
1505         if (eb == NULL) {
1506                 i915_gem_context_unreference(ctx);
1507                 mutex_unlock(&dev->struct_mutex);
1508                 ret = -ENOMEM;
1509                 goto pre_mutex_err;
1510         }
1511
1512         /* Look up object handles */
1513         ret = eb_lookup_vmas(eb, exec, args, vm, file);
1514         if (ret)
1515                 goto err;
1516
1517         /* take note of the batch buffer before we might reorder the lists */
1518         batch_obj = eb_get_batch(eb);
1519
1520         /* Move the objects en-masse into the GTT, evicting if necessary. */
1521         need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
1522         ret = i915_gem_execbuffer_reserve(engine, &eb->vmas, ctx,
1523                                           &need_relocs);
1524         if (ret)
1525                 goto err;
1526
1527         /* The objects are in their final locations, apply the relocations. */
1528         if (need_relocs)
1529                 ret = i915_gem_execbuffer_relocate(eb);
1530         if (ret) {
1531                 if (ret == -EFAULT) {
1532                         ret = i915_gem_execbuffer_relocate_slow(dev, args, file,
1533                                                                 engine,
1534                                                                 eb, exec, ctx);
1535                         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
1536                 }
1537                 if (ret)
1538                         goto err;
1539         }
1540
1541         /* Set the pending read domains for the batch buffer to COMMAND */
1542         if (batch_obj->base.pending_write_domain) {
1543                 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
1544                 ret = -EINVAL;
1545                 goto err;
1546         }
1547
1548         params->args_batch_start_offset = args->batch_start_offset;
1549         if (i915_needs_cmd_parser(engine) && args->batch_len) {
1550                 struct drm_i915_gem_object *parsed_batch_obj;
1551
1552                 parsed_batch_obj = i915_gem_execbuffer_parse(engine,
1553                                                              &shadow_exec_entry,
1554                                                              eb,
1555                                                              batch_obj,
1556                                                              args->batch_start_offset,
1557                                                              args->batch_len,
1558                                                              file->is_master);
1559                 if (IS_ERR(parsed_batch_obj)) {
1560                         ret = PTR_ERR(parsed_batch_obj);
1561                         goto err;
1562                 }
1563
1564                 /*
1565                  * parsed_batch_obj == batch_obj means batch not fully parsed:
1566                  * Accept, but don't promote to secure.
1567                  */
1568
1569                 if (parsed_batch_obj != batch_obj) {
1570                         /*
1571                          * Batch parsed and accepted:
1572                          *
1573                          * Set the DISPATCH_SECURE bit to remove the NON_SECURE
1574                          * bit from MI_BATCH_BUFFER_START commands issued in
1575                          * the dispatch_execbuffer implementations. We
1576                          * specifically don't want that set on batches the
1577                          * command parser has accepted.
1578                          */
1579                         dispatch_flags |= I915_DISPATCH_SECURE;
1580                         params->args_batch_start_offset = 0;
1581                         batch_obj = parsed_batch_obj;
1582                 }
1583         }
1584
1585         batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
1586
1587         /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
1588          * batch" bit. Hence we need to pin secure batches into the global gtt.
1589          * hsw should have this fixed, but bdw mucks it up again. */
1590         if (dispatch_flags & I915_DISPATCH_SECURE) {
1591                 /*
1592                  * So on first glance it looks freaky that we pin the batch here
1593                  * outside of the reservation loop. But:
1594                  * - The batch is already pinned into the relevant ppgtt, so we
1595                  *   already have the backing storage fully allocated.
1596                  * - No other BO uses the global gtt (well contexts, but meh),
1597                  *   so we don't really have issues with multiple objects not
1598                  *   fitting due to fragmentation.
1599                  * So this is actually safe.
1600                  */
1601                 ret = i915_gem_obj_ggtt_pin(batch_obj, 0, 0);
1602                 if (ret)
1603                         goto err;
1604
1605                 params->batch_obj_vm_offset = i915_gem_obj_ggtt_offset(batch_obj);
1606         } else
1607                 params->batch_obj_vm_offset = i915_gem_obj_offset(batch_obj, vm);
1608
1609         /* Allocate a request for this batch buffer nice and early. */
1610         req = i915_gem_request_alloc(engine, ctx);
1611         if (IS_ERR(req)) {
1612                 ret = PTR_ERR(req);
1613                 goto err_batch_unpin;
1614         }
1615
1616         ret = i915_gem_request_add_to_client(req, file);
1617         if (ret)
1618                 goto err_request;
1619
1620         /*
1621          * Save assorted stuff away to pass through to *_submission().
1622          * NB: This data should be 'persistent' and not local as it will
1623          * kept around beyond the duration of the IOCTL once the GPU
1624          * scheduler arrives.
1625          */
1626         params->dev                     = dev;
1627         params->file                    = file;
1628         params->engine                    = engine;
1629         params->dispatch_flags          = dispatch_flags;
1630         params->batch_obj               = batch_obj;
1631         params->ctx                     = ctx;
1632         params->request                 = req;
1633
1634         ret = dev_priv->gt.execbuf_submit(params, args, &eb->vmas);
1635 err_request:
1636         i915_gem_execbuffer_retire_commands(params);
1637
1638 err_batch_unpin:
1639         /*
1640          * FIXME: We crucially rely upon the active tracking for the (ppgtt)
1641          * batch vma for correctness. For less ugly and less fragility this
1642          * needs to be adjusted to also track the ggtt batch vma properly as
1643          * active.
1644          */
1645         if (dispatch_flags & I915_DISPATCH_SECURE)
1646                 i915_gem_object_ggtt_unpin(batch_obj);
1647
1648 err:
1649         /* the request owns the ref now */
1650         i915_gem_context_unreference(ctx);
1651         eb_destroy(eb);
1652
1653         mutex_unlock(&dev->struct_mutex);
1654
1655 pre_mutex_err:
1656         /* intel_gpu_busy should also get a ref, so it will free when the device
1657          * is really idle. */
1658         intel_runtime_pm_put(dev_priv);
1659         return ret;
1660 }
1661
1662 /*
1663  * Legacy execbuffer just creates an exec2 list from the original exec object
1664  * list array and passes it to the real function.
1665  */
1666 int
1667 i915_gem_execbuffer(struct drm_device *dev, void *data,
1668                     struct drm_file *file)
1669 {
1670         struct drm_i915_gem_execbuffer *args = data;
1671         struct drm_i915_gem_execbuffer2 exec2;
1672         struct drm_i915_gem_exec_object *exec_list = NULL;
1673         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1674         int ret, i;
1675
1676         if (args->buffer_count < 1) {
1677                 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1678                 return -EINVAL;
1679         }
1680
1681         /* Copy in the exec list from userland */
1682         exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
1683         exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
1684         if (exec_list == NULL || exec2_list == NULL) {
1685                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1686                           args->buffer_count);
1687                 drm_free_large(exec_list);
1688                 drm_free_large(exec2_list);
1689                 return -ENOMEM;
1690         }
1691         ret = copy_from_user(exec_list,
1692                              to_user_ptr(args->buffers_ptr),
1693                              sizeof(*exec_list) * args->buffer_count);
1694         if (ret != 0) {
1695                 DRM_DEBUG("copy %d exec entries failed %d\n",
1696                           args->buffer_count, ret);
1697                 drm_free_large(exec_list);
1698                 drm_free_large(exec2_list);
1699                 return -EFAULT;
1700         }
1701
1702         for (i = 0; i < args->buffer_count; i++) {
1703                 exec2_list[i].handle = exec_list[i].handle;
1704                 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1705                 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1706                 exec2_list[i].alignment = exec_list[i].alignment;
1707                 exec2_list[i].offset = exec_list[i].offset;
1708                 if (INTEL_INFO(dev)->gen < 4)
1709                         exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1710                 else
1711                         exec2_list[i].flags = 0;
1712         }
1713
1714         exec2.buffers_ptr = args->buffers_ptr;
1715         exec2.buffer_count = args->buffer_count;
1716         exec2.batch_start_offset = args->batch_start_offset;
1717         exec2.batch_len = args->batch_len;
1718         exec2.DR1 = args->DR1;
1719         exec2.DR4 = args->DR4;
1720         exec2.num_cliprects = args->num_cliprects;
1721         exec2.cliprects_ptr = args->cliprects_ptr;
1722         exec2.flags = I915_EXEC_RENDER;
1723         i915_execbuffer2_set_context_id(exec2, 0);
1724
1725         ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1726         if (!ret) {
1727                 struct drm_i915_gem_exec_object __user *user_exec_list =
1728                         to_user_ptr(args->buffers_ptr);
1729
1730                 /* Copy the new buffer offsets back to the user's exec list. */
1731                 for (i = 0; i < args->buffer_count; i++) {
1732                         exec2_list[i].offset =
1733                                 gen8_canonical_addr(exec2_list[i].offset);
1734                         ret = __copy_to_user(&user_exec_list[i].offset,
1735                                              &exec2_list[i].offset,
1736                                              sizeof(user_exec_list[i].offset));
1737                         if (ret) {
1738                                 ret = -EFAULT;
1739                                 DRM_DEBUG("failed to copy %d exec entries "
1740                                           "back to user (%d)\n",
1741                                           args->buffer_count, ret);
1742                                 break;
1743                         }
1744                 }
1745         }
1746
1747         drm_free_large(exec_list);
1748         drm_free_large(exec2_list);
1749         return ret;
1750 }
1751
1752 int
1753 i915_gem_execbuffer2(struct drm_device *dev, void *data,
1754                      struct drm_file *file)
1755 {
1756         struct drm_i915_gem_execbuffer2 *args = data;
1757         struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1758         int ret;
1759
1760         if (args->buffer_count < 1 ||
1761             args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1762                 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1763                 return -EINVAL;
1764         }
1765
1766         if (args->rsvd2 != 0) {
1767                 DRM_DEBUG("dirty rvsd2 field\n");
1768                 return -EINVAL;
1769         }
1770
1771         exec2_list = drm_malloc_gfp(args->buffer_count,
1772                                     sizeof(*exec2_list),
1773                                     GFP_TEMPORARY);
1774         if (exec2_list == NULL) {
1775                 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1776                           args->buffer_count);
1777                 return -ENOMEM;
1778         }
1779         ret = copy_from_user(exec2_list,
1780                              to_user_ptr(args->buffers_ptr),
1781                              sizeof(*exec2_list) * args->buffer_count);
1782         if (ret != 0) {
1783                 DRM_DEBUG("copy %d exec entries failed %d\n",
1784                           args->buffer_count, ret);
1785                 drm_free_large(exec2_list);
1786                 return -EFAULT;
1787         }
1788
1789         ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1790         if (!ret) {
1791                 /* Copy the new buffer offsets back to the user's exec list. */
1792                 struct drm_i915_gem_exec_object2 __user *user_exec_list =
1793                                    to_user_ptr(args->buffers_ptr);
1794                 int i;
1795
1796                 for (i = 0; i < args->buffer_count; i++) {
1797                         exec2_list[i].offset =
1798                                 gen8_canonical_addr(exec2_list[i].offset);
1799                         ret = __copy_to_user(&user_exec_list[i].offset,
1800                                              &exec2_list[i].offset,
1801                                              sizeof(user_exec_list[i].offset));
1802                         if (ret) {
1803                                 ret = -EFAULT;
1804                                 DRM_DEBUG("failed to copy %d exec entries "
1805                                           "back to user\n",
1806                                           args->buffer_count);
1807                                 break;
1808                         }
1809                 }
1810         }
1811
1812         drm_free_large(exec2_list);
1813         return ret;
1814 }