drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/stop_machine.h>
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_vgpu.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: Global GTT views
  37  *
  38  * Background and previous state
  39  *
  40  * Historically objects could exists (be bound) in global GTT space only as
  41  * singular instances with a view representing all of the object's backing pages
  42  * in a linear fashion. This view will be called a normal view.
  43  *
  44  * To support multiple views of the same object, where the number of mapped
  45  * pages is not equal to the backing store, or where the layout of the pages
  46  * is not linear, concept of a GGTT view was added.
  47  *
  48  * One example of an alternative view is a stereo display driven by a single
  49  * image. In this case we would have a framebuffer looking like this
  50  * (2x2 pages):
  51  *
  52  *    12
  53  *    34
  54  *
  55  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  56  * rendering. In contrast, fed to the display engine would be an alternative
  57  * view which could look something like this:
  58  *
  59  *   1212
  60  *   3434
  61  *
  62  * In this example both the size and layout of pages in the alternative view is
  63  * different from the normal view.
  64  *
  65  * Implementation and usage
  66  *
  67  * GGTT views are implemented using VMAs and are distinguished via enum
  68  * i915_ggtt_view_type and struct i915_ggtt_view.
  69  *
  70  * A new flavour of core GEM functions which work with GGTT bound objects were
  71  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  72  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  73  * parameter encapsulating all metadata required to implement a view.
  74  *
  75  * As a helper for callers which are only interested in the normal view,
  76  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  77  * GEM API functions, the ones not taking the view parameter, are operating on,
  78  * or with the normal GGTT view.
  79  *
  80  * Code wanting to add or use a new GGTT view needs to:
  81  *
  82  * 1. Add a new enum with a suitable name.
  83  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  84  * 3. Add support to i915_get_vma_pages().
  85  *
  86  * New views are required to build a scatter-gather table from within the
  87  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  88  * exists for the lifetime of an VMA.
  89  *
  90  * Core API is designed to have copy semantics which means that passed in
  91  * struct i915_ggtt_view does not need to be persistent (left around after
  92  * calling the core API functions).
  93  *
  94  */
  95
  96 static int
  97 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  98
  99 const struct i915_ggtt_view i915_ggtt_view_normal = {
 100         .type = I915_GGTT_VIEW_NORMAL,
 101 };
 102 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 103         .type = I915_GGTT_VIEW_ROTATED,
 104 };
 105
 106 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 107 {
 108         bool has_aliasing_ppgtt;
 109         bool has_full_ppgtt;
 110         bool has_full_48bit_ppgtt;
 111
 112         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 113         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 114         has_full_48bit_ppgtt = IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9;
 115
 116         if (intel_vgpu_active(dev))
 117                 has_full_ppgtt = false; /* emulation is too hard */
 118
 119         /*
 120          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 121          * execlists, the sole mechanism available to submit work.
 122          */
 123         if (INTEL_INFO(dev)->gen < 9 &&
 124             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 125                 return 0;
 126
 127         if (enable_ppgtt == 1)
 128                 return 1;
 129
 130         if (enable_ppgtt == 2 && has_full_ppgtt)
 131                 return 2;
 132
 133         if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
 134                 return 3;
 135
 136 #ifdef CONFIG_INTEL_IOMMU
 137         /* Disable ppgtt on SNB if VT-d is on. */
 138         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 139                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 140                 return 0;
 141         }
 142 #endif
 143
 144         /* Early VLV doesn't have this */
 145         if (IS_VALLEYVIEW(dev) && dev->pdev->revision < 0xb) {
 146                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 147                 return 0;
 148         }
 149
 150         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 151                 return has_full_48bit_ppgtt ? 3 : 2;
 152         else
 153                 return has_aliasing_ppgtt ? 1 : 0;
 154 }
 155
 156 static int ppgtt_bind_vma(struct i915_vma *vma,
 157                           enum i915_cache_level cache_level,
 158                           u32 unused)
 159 {
 160         u32 pte_flags = 0;
 161
 162         /* Currently applicable only to VLV */
 163         if (vma->obj->gt_ro)
 164                 pte_flags |= PTE_READ_ONLY;
 165
 166         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 167                                 cache_level, pte_flags);
 168
 169         return 0;
 170 }
 171
 172 static void ppgtt_unbind_vma(struct i915_vma *vma)
 173 {
 174         vma->vm->clear_range(vma->vm,
 175                              vma->node.start,
 176                              vma->obj->base.size,
 177                              true);
 178 }
 179
 180 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 181                                   enum i915_cache_level level,
 182                                   bool valid)
 183 {
 184         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 185         pte |= addr;
 186
 187         switch (level) {
 188         case I915_CACHE_NONE:
 189                 pte |= PPAT_UNCACHED_INDEX;
 190                 break;
 191         case I915_CACHE_WT:
 192                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 193                 break;
 194         default:
 195                 pte |= PPAT_CACHED_INDEX;
 196                 break;
 197         }
 198
 199         return pte;
 200 }
 201
 202 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 203                                   const enum i915_cache_level level)
 204 {
 205         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 206         pde |= addr;
 207         if (level != I915_CACHE_NONE)
 208                 pde |= PPAT_CACHED_PDE_INDEX;
 209         else
 210                 pde |= PPAT_UNCACHED_INDEX;
 211         return pde;
 212 }
 213
 214 #define gen8_pdpe_encode gen8_pde_encode
 215 #define gen8_pml4e_encode gen8_pde_encode
 216
 217 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 218                                  enum i915_cache_level level,
 219                                  bool valid, u32 unused)
 220 {
 221         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 222         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 223
 224         switch (level) {
 225         case I915_CACHE_L3_LLC:
 226         case I915_CACHE_LLC:
 227                 pte |= GEN6_PTE_CACHE_LLC;
 228                 break;
 229         case I915_CACHE_NONE:
 230                 pte |= GEN6_PTE_UNCACHED;
 231                 break;
 232         default:
 233                 MISSING_CASE(level);
 234         }
 235
 236         return pte;
 237 }
 238
 239 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 240                                  enum i915_cache_level level,
 241                                  bool valid, u32 unused)
 242 {
 243         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 244         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 245
 246         switch (level) {
 247         case I915_CACHE_L3_LLC:
 248                 pte |= GEN7_PTE_CACHE_L3_LLC;
 249                 break;
 250         case I915_CACHE_LLC:
 251                 pte |= GEN6_PTE_CACHE_LLC;
 252                 break;
 253         case I915_CACHE_NONE:
 254                 pte |= GEN6_PTE_UNCACHED;
 255                 break;
 256         default:
 257                 MISSING_CASE(level);
 258         }
 259
 260         return pte;
 261 }
 262
 263 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 264                                  enum i915_cache_level level,
 265                                  bool valid, u32 flags)
 266 {
 267         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 268         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 269
 270         if (!(flags & PTE_READ_ONLY))
 271                 pte |= BYT_PTE_WRITEABLE;
 272
 273         if (level != I915_CACHE_NONE)
 274                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 275
 276         return pte;
 277 }
 278
 279 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 280                                  enum i915_cache_level level,
 281                                  bool valid, u32 unused)
 282 {
 283         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 284         pte |= HSW_PTE_ADDR_ENCODE(addr);
 285
 286         if (level != I915_CACHE_NONE)
 287                 pte |= HSW_WB_LLC_AGE3;
 288
 289         return pte;
 290 }
 291
 292 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 293                                   enum i915_cache_level level,
 294                                   bool valid, u32 unused)
 295 {
 296         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 297         pte |= HSW_PTE_ADDR_ENCODE(addr);
 298
 299         switch (level) {
 300         case I915_CACHE_NONE:
 301                 break;
 302         case I915_CACHE_WT:
 303                 pte |= HSW_WT_ELLC_LLC_AGE3;
 304                 break;
 305         default:
 306                 pte |= HSW_WB_ELLC_LLC_AGE3;
 307                 break;
 308         }
 309
 310         return pte;
 311 }
 312
 313 static int __setup_page_dma(struct drm_device *dev,
 314                             struct i915_page_dma *p, gfp_t flags)
 315 {
 316         struct device *device = &dev->pdev->dev;
 317
 318         p->page = alloc_page(flags);
 319         if (!p->page)
 320                 return -ENOMEM;
 321
 322         p->daddr = dma_map_page(device,
 323                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 324
 325         if (dma_mapping_error(device, p->daddr)) {
 326                 __free_page(p->page);
 327                 return -EINVAL;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 334 {
 335         return __setup_page_dma(dev, p, GFP_KERNEL);
 336 }
 337
 338 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 339 {
 340         if (WARN_ON(!p->page))
 341                 return;
 342
 343         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 344         __free_page(p->page);
 345         memset(p, 0, sizeof(*p));
 346 }
 347
 348 static void *kmap_page_dma(struct i915_page_dma *p)
 349 {
 350         return kmap_atomic(p->page);
 351 }
 352
 353 /* We use the flushing unmap only with ppgtt structures:
 354  * page directories, page tables and scratch pages.
 355  */
 356 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 357 {
 358         /* There are only few exceptions for gen >=6. chv and bxt.
 359          * And we are not sure about the latter so play safe for now.
 360          */
 361         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 362                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 363
 364         kunmap_atomic(vaddr);
 365 }
 366
 367 #define kmap_px(px) kmap_page_dma(px_base(px))
 368 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 369
 370 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 371 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 372 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 373 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 374
 375 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 376                           const uint64_t val)
 377 {
 378         int i;
 379         uint64_t * const vaddr = kmap_page_dma(p);
 380
 381         for (i = 0; i < 512; i++)
 382                 vaddr[i] = val;
 383
 384         kunmap_page_dma(dev, vaddr);
 385 }
 386
 387 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 388                              const uint32_t val32)
 389 {
 390         uint64_t v = val32;
 391
 392         v = v << 32 | val32;
 393
 394         fill_page_dma(dev, p, v);
 395 }
 396
 397 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 398 {
 399         struct i915_page_scratch *sp;
 400         int ret;
 401
 402         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 403         if (sp == NULL)
 404                 return ERR_PTR(-ENOMEM);
 405
 406         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 407         if (ret) {
 408                 kfree(sp);
 409                 return ERR_PTR(ret);
 410         }
 411
 412         set_pages_uc(px_page(sp), 1);
 413
 414         return sp;
 415 }
 416
 417 static void free_scratch_page(struct drm_device *dev,
 418                               struct i915_page_scratch *sp)
 419 {
 420         set_pages_wb(px_page(sp), 1);
 421
 422         cleanup_px(dev, sp);
 423         kfree(sp);
 424 }
 425
 426 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 427 {
 428         struct i915_page_table *pt;
 429         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 430                 GEN8_PTES : GEN6_PTES;
 431         int ret = -ENOMEM;
 432
 433         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 434         if (!pt)
 435                 return ERR_PTR(-ENOMEM);
 436
 437         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 438                                 GFP_KERNEL);
 439
 440         if (!pt->used_ptes)
 441                 goto fail_bitmap;
 442
 443         ret = setup_px(dev, pt);
 444         if (ret)
 445                 goto fail_page_m;
 446
 447         return pt;
 448
 449 fail_page_m:
 450         kfree(pt->used_ptes);
 451 fail_bitmap:
 452         kfree(pt);
 453
 454         return ERR_PTR(ret);
 455 }
 456
 457 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 458 {
 459         cleanup_px(dev, pt);
 460         kfree(pt->used_ptes);
 461         kfree(pt);
 462 }
 463
 464 static void gen8_initialize_pt(struct i915_address_space *vm,
 465                                struct i915_page_table *pt)
 466 {
 467         gen8_pte_t scratch_pte;
 468
 469         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 470                                       I915_CACHE_LLC, true);
 471
 472         fill_px(vm->dev, pt, scratch_pte);
 473 }
 474
 475 static void gen6_initialize_pt(struct i915_address_space *vm,
 476                                struct i915_page_table *pt)
 477 {
 478         gen6_pte_t scratch_pte;
 479
 480         WARN_ON(px_dma(vm->scratch_page) == 0);
 481
 482         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 483                                      I915_CACHE_LLC, true, 0);
 484
 485         fill32_px(vm->dev, pt, scratch_pte);
 486 }
 487
 488 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 489 {
 490         struct i915_page_directory *pd;
 491         int ret = -ENOMEM;
 492
 493         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 494         if (!pd)
 495                 return ERR_PTR(-ENOMEM);
 496
 497         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 498                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 499         if (!pd->used_pdes)
 500                 goto fail_bitmap;
 501
 502         ret = setup_px(dev, pd);
 503         if (ret)
 504                 goto fail_page_m;
 505
 506         return pd;
 507
 508 fail_page_m:
 509         kfree(pd->used_pdes);
 510 fail_bitmap:
 511         kfree(pd);
 512
 513         return ERR_PTR(ret);
 514 }
 515
 516 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 517 {
 518         if (px_page(pd)) {
 519                 cleanup_px(dev, pd);
 520                 kfree(pd->used_pdes);
 521                 kfree(pd);
 522         }
 523 }
 524
 525 static void gen8_initialize_pd(struct i915_address_space *vm,
 526                                struct i915_page_directory *pd)
 527 {
 528         gen8_pde_t scratch_pde;
 529
 530         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 531
 532         fill_px(vm->dev, pd, scratch_pde);
 533 }
 534
 535 static int __pdp_init(struct drm_device *dev,
 536                       struct i915_page_directory_pointer *pdp)
 537 {
 538         size_t pdpes = I915_PDPES_PER_PDP(dev);
 539
 540         pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
 541                                   sizeof(unsigned long),
 542                                   GFP_KERNEL);
 543         if (!pdp->used_pdpes)
 544                 return -ENOMEM;
 545
 546         pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
 547                                       GFP_KERNEL);
 548         if (!pdp->page_directory) {
 549                 kfree(pdp->used_pdpes);
 550                 /* the PDP might be the statically allocated top level. Keep it
 551                  * as clean as possible */
 552                 pdp->used_pdpes = NULL;
 553                 return -ENOMEM;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 560 {
 561         kfree(pdp->used_pdpes);
 562         kfree(pdp->page_directory);
 563         pdp->page_directory = NULL;
 564 }
 565
 566 static struct
 567 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
 568 {
 569         struct i915_page_directory_pointer *pdp;
 570         int ret = -ENOMEM;
 571
 572         WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
 573
 574         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 575         if (!pdp)
 576                 return ERR_PTR(-ENOMEM);
 577
 578         ret = __pdp_init(dev, pdp);
 579         if (ret)
 580                 goto fail_bitmap;
 581
 582         ret = setup_px(dev, pdp);
 583         if (ret)
 584                 goto fail_page_m;
 585
 586         return pdp;
 587
 588 fail_page_m:
 589         __pdp_fini(pdp);
 590 fail_bitmap:
 591         kfree(pdp);
 592
 593         return ERR_PTR(ret);
 594 }
 595
 596 static void free_pdp(struct drm_device *dev,
 597                      struct i915_page_directory_pointer *pdp)
 598 {
 599         __pdp_fini(pdp);
 600         if (USES_FULL_48BIT_PPGTT(dev)) {
 601                 cleanup_px(dev, pdp);
 602                 kfree(pdp);
 603         }
 604 }
 605
 606 static void gen8_initialize_pdp(struct i915_address_space *vm,
 607                                 struct i915_page_directory_pointer *pdp)
 608 {
 609         gen8_ppgtt_pdpe_t scratch_pdpe;
 610
 611         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 612
 613         fill_px(vm->dev, pdp, scratch_pdpe);
 614 }
 615
 616 static void gen8_initialize_pml4(struct i915_address_space *vm,
 617                                  struct i915_pml4 *pml4)
 618 {
 619         gen8_ppgtt_pml4e_t scratch_pml4e;
 620
 621         scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
 622                                           I915_CACHE_LLC);
 623
 624         fill_px(vm->dev, pml4, scratch_pml4e);
 625 }
 626
 627 static void
 628 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
 629                           struct i915_page_directory_pointer *pdp,
 630                           struct i915_page_directory *pd,
 631                           int index)
 632 {
 633         gen8_ppgtt_pdpe_t *page_directorypo;
 634
 635         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 636                 return;
 637
 638         page_directorypo = kmap_px(pdp);
 639         page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 640         kunmap_px(ppgtt, page_directorypo);
 641 }
 642
 643 static void
 644 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
 645                                   struct i915_pml4 *pml4,
 646                                   struct i915_page_directory_pointer *pdp,
 647                                   int index)
 648 {
 649         gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 650
 651         WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
 652         pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 653         kunmap_px(ppgtt, pagemap);
 654 }
 655
 656 /* Broadwell Page Directory Pointer Descriptors */
 657 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 658                           unsigned entry,
 659                           dma_addr_t addr)
 660 {
 661         struct intel_engine_cs *engine = req->engine;
 662         int ret;
 663
 664         BUG_ON(entry >= 4);
 665
 666         ret = intel_ring_begin(req, 6);
 667         if (ret)
 668                 return ret;
 669
 670         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
 671         intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
 672         intel_ring_emit(engine, upper_32_bits(addr));
 673         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
 674         intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
 675         intel_ring_emit(engine, lower_32_bits(addr));
 676         intel_ring_advance(engine);
 677
 678         return 0;
 679 }
 680
 681 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
 682                                  struct drm_i915_gem_request *req)
 683 {
 684         int i, ret;
 685
 686         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 687                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 688
 689                 ret = gen8_write_pdp(req, i, pd_daddr);
 690                 if (ret)
 691                         return ret;
 692         }
 693
 694         return 0;
 695 }
 696
 697 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
 698                               struct drm_i915_gem_request *req)
 699 {
 700         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
 701 }
 702
 703 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
 704                                        struct i915_page_directory_pointer *pdp,
 705                                        uint64_t start,
 706                                        uint64_t length,
 707                                        gen8_pte_t scratch_pte)
 708 {
 709         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 710         gen8_pte_t *pt_vaddr;
 711         unsigned pdpe = gen8_pdpe_index(start);
 712         unsigned pde = gen8_pde_index(start);
 713         unsigned pte = gen8_pte_index(start);
 714         unsigned num_entries = length >> PAGE_SHIFT;
 715         unsigned last_pte, i;
 716
 717         if (WARN_ON(!pdp))
 718                 return;
 719
 720         while (num_entries) {
 721                 struct i915_page_directory *pd;
 722                 struct i915_page_table *pt;
 723
 724                 if (WARN_ON(!pdp->page_directory[pdpe]))
 725                         break;
 726
 727                 pd = pdp->page_directory[pdpe];
 728
 729                 if (WARN_ON(!pd->page_table[pde]))
 730                         break;
 731
 732                 pt = pd->page_table[pde];
 733
 734                 if (WARN_ON(!px_page(pt)))
 735                         break;
 736
 737                 last_pte = pte + num_entries;
 738                 if (last_pte > GEN8_PTES)
 739                         last_pte = GEN8_PTES;
 740
 741                 pt_vaddr = kmap_px(pt);
 742
 743                 for (i = pte; i < last_pte; i++) {
 744                         pt_vaddr[i] = scratch_pte;
 745                         num_entries--;
 746                 }
 747
 748                 kunmap_px(ppgtt, pt_vaddr);
 749
 750                 pte = 0;
 751                 if (++pde == I915_PDES) {
 752                         if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 753                                 break;
 754                         pde = 0;
 755                 }
 756         }
 757 }
 758
 759 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 760                                    uint64_t start,
 761                                    uint64_t length,
 762                                    bool use_scratch)
 763 {
 764         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 765         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 766                                                  I915_CACHE_LLC, use_scratch);
 767
 768         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 769                 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
 770                                            scratch_pte);
 771         } else {
 772                 uint64_t pml4e;
 773                 struct i915_page_directory_pointer *pdp;
 774
 775                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 776                         gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
 777                                                    scratch_pte);
 778                 }
 779         }
 780 }
 781
 782 static void
 783 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
 784                               struct i915_page_directory_pointer *pdp,
 785                               struct sg_page_iter *sg_iter,
 786                               uint64_t start,
 787                               enum i915_cache_level cache_level)
 788 {
 789         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 790         gen8_pte_t *pt_vaddr;
 791         unsigned pdpe = gen8_pdpe_index(start);
 792         unsigned pde = gen8_pde_index(start);
 793         unsigned pte = gen8_pte_index(start);
 794
 795         pt_vaddr = NULL;
 796
 797         while (__sg_page_iter_next(sg_iter)) {
 798                 if (pt_vaddr == NULL) {
 799                         struct i915_page_directory *pd = pdp->page_directory[pdpe];
 800                         struct i915_page_table *pt = pd->page_table[pde];
 801                         pt_vaddr = kmap_px(pt);
 802                 }
 803
 804                 pt_vaddr[pte] =
 805                         gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
 806                                         cache_level, true);
 807                 if (++pte == GEN8_PTES) {
 808                         kunmap_px(ppgtt, pt_vaddr);
 809                         pt_vaddr = NULL;
 810                         if (++pde == I915_PDES) {
 811                                 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 812                                         break;
 813                                 pde = 0;
 814                         }
 815                         pte = 0;
 816                 }
 817         }
 818
 819         if (pt_vaddr)
 820                 kunmap_px(ppgtt, pt_vaddr);
 821 }
 822
 823 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 824                                       struct sg_table *pages,
 825                                       uint64_t start,
 826                                       enum i915_cache_level cache_level,
 827                                       u32 unused)
 828 {
 829         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 830         struct sg_page_iter sg_iter;
 831
 832         __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
 833
 834         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 835                 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
 836                                               cache_level);
 837         } else {
 838                 struct i915_page_directory_pointer *pdp;
 839                 uint64_t pml4e;
 840                 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
 841
 842                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 843                         gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
 844                                                       start, cache_level);
 845                 }
 846         }
 847 }
 848
 849 static void gen8_free_page_tables(struct drm_device *dev,
 850                                   struct i915_page_directory *pd)
 851 {
 852         int i;
 853
 854         if (!px_page(pd))
 855                 return;
 856
 857         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 858                 if (WARN_ON(!pd->page_table[i]))
 859                         continue;
 860
 861                 free_pt(dev, pd->page_table[i]);
 862                 pd->page_table[i] = NULL;
 863         }
 864 }
 865
 866 static int gen8_init_scratch(struct i915_address_space *vm)
 867 {
 868         struct drm_device *dev = vm->dev;
 869
 870         vm->scratch_page = alloc_scratch_page(dev);
 871         if (IS_ERR(vm->scratch_page))
 872                 return PTR_ERR(vm->scratch_page);
 873
 874         vm->scratch_pt = alloc_pt(dev);
 875         if (IS_ERR(vm->scratch_pt)) {
 876                 free_scratch_page(dev, vm->scratch_page);
 877                 return PTR_ERR(vm->scratch_pt);
 878         }
 879
 880         vm->scratch_pd = alloc_pd(dev);
 881         if (IS_ERR(vm->scratch_pd)) {
 882                 free_pt(dev, vm->scratch_pt);
 883                 free_scratch_page(dev, vm->scratch_page);
 884                 return PTR_ERR(vm->scratch_pd);
 885         }
 886
 887         if (USES_FULL_48BIT_PPGTT(dev)) {
 888                 vm->scratch_pdp = alloc_pdp(dev);
 889                 if (IS_ERR(vm->scratch_pdp)) {
 890                         free_pd(dev, vm->scratch_pd);
 891                         free_pt(dev, vm->scratch_pt);
 892                         free_scratch_page(dev, vm->scratch_page);
 893                         return PTR_ERR(vm->scratch_pdp);
 894                 }
 895         }
 896
 897         gen8_initialize_pt(vm, vm->scratch_pt);
 898         gen8_initialize_pd(vm, vm->scratch_pd);
 899         if (USES_FULL_48BIT_PPGTT(dev))
 900                 gen8_initialize_pdp(vm, vm->scratch_pdp);
 901
 902         return 0;
 903 }
 904
 905 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
 906 {
 907         enum vgt_g2v_type msg;
 908         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
 909         int i;
 910
 911         if (USES_FULL_48BIT_PPGTT(dev_priv)) {
 912                 u64 daddr = px_dma(&ppgtt->pml4);
 913
 914                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
 915                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
 916
 917                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 918                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 919         } else {
 920                 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 921                         u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
 922
 923                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
 924                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
 925                 }
 926
 927                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 928                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
 929         }
 930
 931         I915_WRITE(vgtif_reg(g2v_notify), msg);
 932
 933         return 0;
 934 }
 935
 936 static void gen8_free_scratch(struct i915_address_space *vm)
 937 {
 938         struct drm_device *dev = vm->dev;
 939
 940         if (USES_FULL_48BIT_PPGTT(dev))
 941                 free_pdp(dev, vm->scratch_pdp);
 942         free_pd(dev, vm->scratch_pd);
 943         free_pt(dev, vm->scratch_pt);
 944         free_scratch_page(dev, vm->scratch_page);
 945 }
 946
 947 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
 948                                     struct i915_page_directory_pointer *pdp)
 949 {
 950         int i;
 951
 952         for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
 953                 if (WARN_ON(!pdp->page_directory[i]))
 954                         continue;
 955
 956                 gen8_free_page_tables(dev, pdp->page_directory[i]);
 957                 free_pd(dev, pdp->page_directory[i]);
 958         }
 959
 960         free_pdp(dev, pdp);
 961 }
 962
 963 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
 964 {
 965         int i;
 966
 967         for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
 968                 if (WARN_ON(!ppgtt->pml4.pdps[i]))
 969                         continue;
 970
 971                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
 972         }
 973
 974         cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
 975 }
 976
 977 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 978 {
 979         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 980
 981         if (intel_vgpu_active(vm->dev))
 982                 gen8_ppgtt_notify_vgt(ppgtt, false);
 983
 984         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 985                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
 986         else
 987                 gen8_ppgtt_cleanup_4lvl(ppgtt);
 988
 989         gen8_free_scratch(vm);
 990 }
 991
 992 /**
 993  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 994  * @vm: Master vm structure.
 995  * @pd: Page directory for this address range.
 996  * @start:      Starting virtual address to begin allocations.
 997  * @length:     Size of the allocations.
 998  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 999  *              caller to free on error.
1000  *
1001  * Allocate the required number of page tables. Extremely similar to
1002  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1003  * the page directory boundary (instead of the page directory pointer). That
1004  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1005  * possible, and likely that the caller will need to use multiple calls of this
1006  * function to achieve the appropriate allocation.
1007  *
1008  * Return: 0 if success; negative error code otherwise.
1009  */
1010 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1011                                      struct i915_page_directory *pd,
1012                                      uint64_t start,
1013                                      uint64_t length,
1014                                      unsigned long *new_pts)
1015 {
1016         struct drm_device *dev = vm->dev;
1017         struct i915_page_table *pt;
1018         uint32_t pde;
1019
1020         gen8_for_each_pde(pt, pd, start, length, pde) {
1021                 /* Don't reallocate page tables */
1022                 if (test_bit(pde, pd->used_pdes)) {
1023                         /* Scratch is never allocated this way */
1024                         WARN_ON(pt == vm->scratch_pt);
1025                         continue;
1026                 }
1027
1028                 pt = alloc_pt(dev);
1029                 if (IS_ERR(pt))
1030                         goto unwind_out;
1031
1032                 gen8_initialize_pt(vm, pt);
1033                 pd->page_table[pde] = pt;
1034                 __set_bit(pde, new_pts);
1035                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1036         }
1037
1038         return 0;
1039
1040 unwind_out:
1041         for_each_set_bit(pde, new_pts, I915_PDES)
1042                 free_pt(dev, pd->page_table[pde]);
1043
1044         return -ENOMEM;
1045 }
1046
1047 /**
1048  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1049  * @vm: Master vm structure.
1050  * @pdp:        Page directory pointer for this address range.
1051  * @start:      Starting virtual address to begin allocations.
1052  * @length:     Size of the allocations.
1053  * @new_pds:    Bitmap set by function with new allocations. Likely used by the
1054  *              caller to free on error.
1055  *
1056  * Allocate the required number of page directories starting at the pde index of
1057  * @start, and ending at the pde index @start + @length. This function will skip
1058  * over already allocated page directories within the range, and only allocate
1059  * new ones, setting the appropriate pointer within the pdp as well as the
1060  * correct position in the bitmap @new_pds.
1061  *
1062  * The function will only allocate the pages within the range for a give page
1063  * directory pointer. In other words, if @start + @length straddles a virtually
1064  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1065  * required by the caller, This is not currently possible, and the BUG in the
1066  * code will prevent it.
1067  *
1068  * Return: 0 if success; negative error code otherwise.
1069  */
1070 static int
1071 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1072                                   struct i915_page_directory_pointer *pdp,
1073                                   uint64_t start,
1074                                   uint64_t length,
1075                                   unsigned long *new_pds)
1076 {
1077         struct drm_device *dev = vm->dev;
1078         struct i915_page_directory *pd;
1079         uint32_t pdpe;
1080         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1081
1082         WARN_ON(!bitmap_empty(new_pds, pdpes));
1083
1084         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1085                 if (test_bit(pdpe, pdp->used_pdpes))
1086                         continue;
1087
1088                 pd = alloc_pd(dev);
1089                 if (IS_ERR(pd))
1090                         goto unwind_out;
1091
1092                 gen8_initialize_pd(vm, pd);
1093                 pdp->page_directory[pdpe] = pd;
1094                 __set_bit(pdpe, new_pds);
1095                 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1096         }
1097
1098         return 0;
1099
1100 unwind_out:
1101         for_each_set_bit(pdpe, new_pds, pdpes)
1102                 free_pd(dev, pdp->page_directory[pdpe]);
1103
1104         return -ENOMEM;
1105 }
1106
1107 /**
1108  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1109  * @vm: Master vm structure.
1110  * @pml4:       Page map level 4 for this address range.
1111  * @start:      Starting virtual address to begin allocations.
1112  * @length:     Size of the allocations.
1113  * @new_pdps:   Bitmap set by function with new allocations. Likely used by the
1114  *              caller to free on error.
1115  *
1116  * Allocate the required number of page directory pointers. Extremely similar to
1117  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1118  * The main difference is here we are limited by the pml4 boundary (instead of
1119  * the page directory pointer).
1120  *
1121  * Return: 0 if success; negative error code otherwise.
1122  */
1123 static int
1124 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1125                                   struct i915_pml4 *pml4,
1126                                   uint64_t start,
1127                                   uint64_t length,
1128                                   unsigned long *new_pdps)
1129 {
1130         struct drm_device *dev = vm->dev;
1131         struct i915_page_directory_pointer *pdp;
1132         uint32_t pml4e;
1133
1134         WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1135
1136         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1137                 if (!test_bit(pml4e, pml4->used_pml4es)) {
1138                         pdp = alloc_pdp(dev);
1139                         if (IS_ERR(pdp))
1140                                 goto unwind_out;
1141
1142                         gen8_initialize_pdp(vm, pdp);
1143                         pml4->pdps[pml4e] = pdp;
1144                         __set_bit(pml4e, new_pdps);
1145                         trace_i915_page_directory_pointer_entry_alloc(vm,
1146                                                                       pml4e,
1147                                                                       start,
1148                                                                       GEN8_PML4E_SHIFT);
1149                 }
1150         }
1151
1152         return 0;
1153
1154 unwind_out:
1155         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1156                 free_pdp(dev, pml4->pdps[pml4e]);
1157
1158         return -ENOMEM;
1159 }
1160
1161 static void
1162 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1163 {
1164         kfree(new_pts);
1165         kfree(new_pds);
1166 }
1167
1168 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1169  * of these are based on the number of PDPEs in the system.
1170  */
1171 static
1172 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1173                                          unsigned long **new_pts,
1174                                          uint32_t pdpes)
1175 {
1176         unsigned long *pds;
1177         unsigned long *pts;
1178
1179         pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1180         if (!pds)
1181                 return -ENOMEM;
1182
1183         pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1184                       GFP_TEMPORARY);
1185         if (!pts)
1186                 goto err_out;
1187
1188         *new_pds = pds;
1189         *new_pts = pts;
1190
1191         return 0;
1192
1193 err_out:
1194         free_gen8_temp_bitmaps(pds, pts);
1195         return -ENOMEM;
1196 }
1197
1198 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1199  * the page table structures, we mark them dirty so that
1200  * context switching/execlist queuing code takes extra steps
1201  * to ensure that tlbs are flushed.
1202  */
1203 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1204 {
1205         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1206 }
1207
1208 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1209                                     struct i915_page_directory_pointer *pdp,
1210                                     uint64_t start,
1211                                     uint64_t length)
1212 {
1213         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1214         unsigned long *new_page_dirs, *new_page_tables;
1215         struct drm_device *dev = vm->dev;
1216         struct i915_page_directory *pd;
1217         const uint64_t orig_start = start;
1218         const uint64_t orig_length = length;
1219         uint32_t pdpe;
1220         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1221         int ret;
1222
1223         /* Wrap is never okay since we can only represent 48b, and we don't
1224          * actually use the other side of the canonical address space.
1225          */
1226         if (WARN_ON(start + length < start))
1227                 return -ENODEV;
1228
1229         if (WARN_ON(start + length > vm->total))
1230                 return -ENODEV;
1231
1232         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1233         if (ret)
1234                 return ret;
1235
1236         /* Do the allocations first so we can easily bail out */
1237         ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1238                                                 new_page_dirs);
1239         if (ret) {
1240                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1241                 return ret;
1242         }
1243
1244         /* For every page directory referenced, allocate page tables */
1245         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1246                 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1247                                                 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1248                 if (ret)
1249                         goto err_out;
1250         }
1251
1252         start = orig_start;
1253         length = orig_length;
1254
1255         /* Allocations have completed successfully, so set the bitmaps, and do
1256          * the mappings. */
1257         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1258                 gen8_pde_t *const page_directory = kmap_px(pd);
1259                 struct i915_page_table *pt;
1260                 uint64_t pd_len = length;
1261                 uint64_t pd_start = start;
1262                 uint32_t pde;
1263
1264                 /* Every pd should be allocated, we just did that above. */
1265                 WARN_ON(!pd);
1266
1267                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1268                         /* Same reasoning as pd */
1269                         WARN_ON(!pt);
1270                         WARN_ON(!pd_len);
1271                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
1272
1273                         /* Set our used ptes within the page table */
1274                         bitmap_set(pt->used_ptes,
1275                                    gen8_pte_index(pd_start),
1276                                    gen8_pte_count(pd_start, pd_len));
1277
1278                         /* Our pde is now pointing to the pagetable, pt */
1279                         __set_bit(pde, pd->used_pdes);
1280
1281                         /* Map the PDE to the page table */
1282                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
1283                                                               I915_CACHE_LLC);
1284                         trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1285                                                         gen8_pte_index(start),
1286                                                         gen8_pte_count(start, length),
1287                                                         GEN8_PTES);
1288
1289                         /* NB: We haven't yet mapped ptes to pages. At this
1290                          * point we're still relying on insert_entries() */
1291                 }
1292
1293                 kunmap_px(ppgtt, page_directory);
1294                 __set_bit(pdpe, pdp->used_pdpes);
1295                 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1296         }
1297
1298         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1299         mark_tlbs_dirty(ppgtt);
1300         return 0;
1301
1302 err_out:
1303         while (pdpe--) {
1304                 unsigned long temp;
1305
1306                 for_each_set_bit(temp, new_page_tables + pdpe *
1307                                 BITS_TO_LONGS(I915_PDES), I915_PDES)
1308                         free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1309         }
1310
1311         for_each_set_bit(pdpe, new_page_dirs, pdpes)
1312                 free_pd(dev, pdp->page_directory[pdpe]);
1313
1314         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1315         mark_tlbs_dirty(ppgtt);
1316         return ret;
1317 }
1318
1319 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1320                                     struct i915_pml4 *pml4,
1321                                     uint64_t start,
1322                                     uint64_t length)
1323 {
1324         DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1325         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1326         struct i915_page_directory_pointer *pdp;
1327         uint64_t pml4e;
1328         int ret = 0;
1329
1330         /* Do the pml4 allocations first, so we don't need to track the newly
1331          * allocated tables below the pdp */
1332         bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1333
1334         /* The pagedirectory and pagetable allocations are done in the shared 3
1335          * and 4 level code. Just allocate the pdps.
1336          */
1337         ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1338                                                 new_pdps);
1339         if (ret)
1340                 return ret;
1341
1342         WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1343              "The allocation has spanned more than 512GB. "
1344              "It is highly likely this is incorrect.");
1345
1346         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1347                 WARN_ON(!pdp);
1348
1349                 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1350                 if (ret)
1351                         goto err_out;
1352
1353                 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1354         }
1355
1356         bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1357                   GEN8_PML4ES_PER_PML4);
1358
1359         return 0;
1360
1361 err_out:
1362         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1363                 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1364
1365         return ret;
1366 }
1367
1368 static int gen8_alloc_va_range(struct i915_address_space *vm,
1369                                uint64_t start, uint64_t length)
1370 {
1371         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1372
1373         if (USES_FULL_48BIT_PPGTT(vm->dev))
1374                 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1375         else
1376                 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1377 }
1378
1379 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1380                           uint64_t start, uint64_t length,
1381                           gen8_pte_t scratch_pte,
1382                           struct seq_file *m)
1383 {
1384         struct i915_page_directory *pd;
1385         uint32_t pdpe;
1386
1387         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1388                 struct i915_page_table *pt;
1389                 uint64_t pd_len = length;
1390                 uint64_t pd_start = start;
1391                 uint32_t pde;
1392
1393                 if (!test_bit(pdpe, pdp->used_pdpes))
1394                         continue;
1395
1396                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1397                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1398                         uint32_t  pte;
1399                         gen8_pte_t *pt_vaddr;
1400
1401                         if (!test_bit(pde, pd->used_pdes))
1402                                 continue;
1403
1404                         pt_vaddr = kmap_px(pt);
1405                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1406                                 uint64_t va =
1407                                         (pdpe << GEN8_PDPE_SHIFT) |
1408                                         (pde << GEN8_PDE_SHIFT) |
1409                                         (pte << GEN8_PTE_SHIFT);
1410                                 int i;
1411                                 bool found = false;
1412
1413                                 for (i = 0; i < 4; i++)
1414                                         if (pt_vaddr[pte + i] != scratch_pte)
1415                                                 found = true;
1416                                 if (!found)
1417                                         continue;
1418
1419                                 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1420                                 for (i = 0; i < 4; i++) {
1421                                         if (pt_vaddr[pte + i] != scratch_pte)
1422                                                 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1423                                         else
1424                                                 seq_puts(m, "  SCRATCH ");
1425                                 }
1426                                 seq_puts(m, "\n");
1427                         }
1428                         /* don't use kunmap_px, it could trigger
1429                          * an unnecessary flush.
1430                          */
1431                         kunmap_atomic(pt_vaddr);
1432                 }
1433         }
1434 }
1435
1436 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1437 {
1438         struct i915_address_space *vm = &ppgtt->base;
1439         uint64_t start = ppgtt->base.start;
1440         uint64_t length = ppgtt->base.total;
1441         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1442                                                  I915_CACHE_LLC, true);
1443
1444         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1445                 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1446         } else {
1447                 uint64_t pml4e;
1448                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1449                 struct i915_page_directory_pointer *pdp;
1450
1451                 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1452                         if (!test_bit(pml4e, pml4->used_pml4es))
1453                                 continue;
1454
1455                         seq_printf(m, "    PML4E #%llu\n", pml4e);
1456                         gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1457                 }
1458         }
1459 }
1460
1461 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1462 {
1463         unsigned long *new_page_dirs, *new_page_tables;
1464         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1465         int ret;
1466
1467         /* We allocate temp bitmap for page tables for no gain
1468          * but as this is for init only, lets keep the things simple
1469          */
1470         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1471         if (ret)
1472                 return ret;
1473
1474         /* Allocate for all pdps regardless of how the ppgtt
1475          * was defined.
1476          */
1477         ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1478                                                 0, 1ULL << 32,
1479                                                 new_page_dirs);
1480         if (!ret)
1481                 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1482
1483         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1484
1485         return ret;
1486 }
1487
1488 /*
1489  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1490  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1491  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1492  * space.
1493  *
1494  */
1495 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1496 {
1497         int ret;
1498
1499         ret = gen8_init_scratch(&ppgtt->base);
1500         if (ret)
1501                 return ret;
1502
1503         ppgtt->base.start = 0;
1504         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1505         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1506         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1507         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1508         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1509         ppgtt->base.bind_vma = ppgtt_bind_vma;
1510         ppgtt->debug_dump = gen8_dump_ppgtt;
1511
1512         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1513                 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1514                 if (ret)
1515                         goto free_scratch;
1516
1517                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1518
1519                 ppgtt->base.total = 1ULL << 48;
1520                 ppgtt->switch_mm = gen8_48b_mm_switch;
1521         } else {
1522                 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1523                 if (ret)
1524                         goto free_scratch;
1525
1526                 ppgtt->base.total = 1ULL << 32;
1527                 ppgtt->switch_mm = gen8_legacy_mm_switch;
1528                 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1529                                                               0, 0,
1530                                                               GEN8_PML4E_SHIFT);
1531
1532                 if (intel_vgpu_active(ppgtt->base.dev)) {
1533                         ret = gen8_preallocate_top_level_pdps(ppgtt);
1534                         if (ret)
1535                                 goto free_scratch;
1536                 }
1537         }
1538
1539         if (intel_vgpu_active(ppgtt->base.dev))
1540                 gen8_ppgtt_notify_vgt(ppgtt, true);
1541
1542         return 0;
1543
1544 free_scratch:
1545         gen8_free_scratch(&ppgtt->base);
1546         return ret;
1547 }
1548
1549 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1550 {
1551         struct i915_address_space *vm = &ppgtt->base;
1552         struct i915_page_table *unused;
1553         gen6_pte_t scratch_pte;
1554         uint32_t pd_entry;
1555         uint32_t  pte, pde, temp;
1556         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1557
1558         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1559                                      I915_CACHE_LLC, true, 0);
1560
1561         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1562                 u32 expected;
1563                 gen6_pte_t *pt_vaddr;
1564                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1565                 pd_entry = readl(ppgtt->pd_addr + pde);
1566                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1567
1568                 if (pd_entry != expected)
1569                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1570                                    pde,
1571                                    pd_entry,
1572                                    expected);
1573                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1574
1575                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1576
1577                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1578                         unsigned long va =
1579                                 (pde * PAGE_SIZE * GEN6_PTES) +
1580                                 (pte * PAGE_SIZE);
1581                         int i;
1582                         bool found = false;
1583                         for (i = 0; i < 4; i++)
1584                                 if (pt_vaddr[pte + i] != scratch_pte)
1585                                         found = true;
1586                         if (!found)
1587                                 continue;
1588
1589                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1590                         for (i = 0; i < 4; i++) {
1591                                 if (pt_vaddr[pte + i] != scratch_pte)
1592                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1593                                 else
1594                                         seq_puts(m, "  SCRATCH ");
1595                         }
1596                         seq_puts(m, "\n");
1597                 }
1598                 kunmap_px(ppgtt, pt_vaddr);
1599         }
1600 }
1601
1602 /* Write pde (index) from the page directory @pd to the page table @pt */
1603 static void gen6_write_pde(struct i915_page_directory *pd,
1604                             const int pde, struct i915_page_table *pt)
1605 {
1606         /* Caller needs to make sure the write completes if necessary */
1607         struct i915_hw_ppgtt *ppgtt =
1608                 container_of(pd, struct i915_hw_ppgtt, pd);
1609         u32 pd_entry;
1610
1611         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1612         pd_entry |= GEN6_PDE_VALID;
1613
1614         writel(pd_entry, ppgtt->pd_addr + pde);
1615 }
1616
1617 /* Write all the page tables found in the ppgtt structure to incrementing page
1618  * directories. */
1619 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1620                                   struct i915_page_directory *pd,
1621                                   uint32_t start, uint32_t length)
1622 {
1623         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1624         struct i915_page_table *pt;
1625         uint32_t pde, temp;
1626
1627         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1628                 gen6_write_pde(pd, pde, pt);
1629
1630         /* Make sure write is complete before other code can use this page
1631          * table. Also require for WC mapped PTEs */
1632         readl(ggtt->gsm);
1633 }
1634
1635 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1636 {
1637         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1638
1639         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1640 }
1641
1642 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1643                          struct drm_i915_gem_request *req)
1644 {
1645         struct intel_engine_cs *engine = req->engine;
1646         int ret;
1647
1648         /* NB: TLBs must be flushed and invalidated before a switch */
1649         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1650         if (ret)
1651                 return ret;
1652
1653         ret = intel_ring_begin(req, 6);
1654         if (ret)
1655                 return ret;
1656
1657         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1658         intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1659         intel_ring_emit(engine, PP_DIR_DCLV_2G);
1660         intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1661         intel_ring_emit(engine, get_pd_offset(ppgtt));
1662         intel_ring_emit(engine, MI_NOOP);
1663         intel_ring_advance(engine);
1664
1665         return 0;
1666 }
1667
1668 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1669                           struct drm_i915_gem_request *req)
1670 {
1671         struct intel_engine_cs *engine = req->engine;
1672         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1673
1674         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1675         I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1676         return 0;
1677 }
1678
1679 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1680                           struct drm_i915_gem_request *req)
1681 {
1682         struct intel_engine_cs *engine = req->engine;
1683         int ret;
1684
1685         /* NB: TLBs must be flushed and invalidated before a switch */
1686         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1687         if (ret)
1688                 return ret;
1689
1690         ret = intel_ring_begin(req, 6);
1691         if (ret)
1692                 return ret;
1693
1694         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1695         intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1696         intel_ring_emit(engine, PP_DIR_DCLV_2G);
1697         intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1698         intel_ring_emit(engine, get_pd_offset(ppgtt));
1699         intel_ring_emit(engine, MI_NOOP);
1700         intel_ring_advance(engine);
1701
1702         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1703         if (engine->id != RCS) {
1704                 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1705                 if (ret)
1706                         return ret;
1707         }
1708
1709         return 0;
1710 }
1711
1712 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1713                           struct drm_i915_gem_request *req)
1714 {
1715         struct intel_engine_cs *engine = req->engine;
1716         struct drm_device *dev = ppgtt->base.dev;
1717         struct drm_i915_private *dev_priv = dev->dev_private;
1718
1719
1720         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1721         I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1722
1723         POSTING_READ(RING_PP_DIR_DCLV(engine));
1724
1725         return 0;
1726 }
1727
1728 static void gen8_ppgtt_enable(struct drm_device *dev)
1729 {
1730         struct drm_i915_private *dev_priv = dev->dev_private;
1731         struct intel_engine_cs *engine;
1732
1733         for_each_engine(engine, dev_priv) {
1734                 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1735                 I915_WRITE(RING_MODE_GEN7(engine),
1736                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1737         }
1738 }
1739
1740 static void gen7_ppgtt_enable(struct drm_device *dev)
1741 {
1742         struct drm_i915_private *dev_priv = dev->dev_private;
1743         struct intel_engine_cs *engine;
1744         uint32_t ecochk, ecobits;
1745
1746         ecobits = I915_READ(GAC_ECO_BITS);
1747         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1748
1749         ecochk = I915_READ(GAM_ECOCHK);
1750         if (IS_HASWELL(dev)) {
1751                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1752         } else {
1753                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1754                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1755         }
1756         I915_WRITE(GAM_ECOCHK, ecochk);
1757
1758         for_each_engine(engine, dev_priv) {
1759                 /* GFX_MODE is per-ring on gen7+ */
1760                 I915_WRITE(RING_MODE_GEN7(engine),
1761                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1762         }
1763 }
1764
1765 static void gen6_ppgtt_enable(struct drm_device *dev)
1766 {
1767         struct drm_i915_private *dev_priv = dev->dev_private;
1768         uint32_t ecochk, gab_ctl, ecobits;
1769
1770         ecobits = I915_READ(GAC_ECO_BITS);
1771         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1772                    ECOBITS_PPGTT_CACHE64B);
1773
1774         gab_ctl = I915_READ(GAB_CTL);
1775         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1776
1777         ecochk = I915_READ(GAM_ECOCHK);
1778         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1779
1780         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1781 }
1782
1783 /* PPGTT support for Sandybdrige/Gen6 and later */
1784 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1785                                    uint64_t start,
1786                                    uint64_t length,
1787                                    bool use_scratch)
1788 {
1789         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1790         gen6_pte_t *pt_vaddr, scratch_pte;
1791         unsigned first_entry = start >> PAGE_SHIFT;
1792         unsigned num_entries = length >> PAGE_SHIFT;
1793         unsigned act_pt = first_entry / GEN6_PTES;
1794         unsigned first_pte = first_entry % GEN6_PTES;
1795         unsigned last_pte, i;
1796
1797         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1798                                      I915_CACHE_LLC, true, 0);
1799
1800         while (num_entries) {
1801                 last_pte = first_pte + num_entries;
1802                 if (last_pte > GEN6_PTES)
1803                         last_pte = GEN6_PTES;
1804
1805                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1806
1807                 for (i = first_pte; i < last_pte; i++)
1808                         pt_vaddr[i] = scratch_pte;
1809
1810                 kunmap_px(ppgtt, pt_vaddr);
1811
1812                 num_entries -= last_pte - first_pte;
1813                 first_pte = 0;
1814                 act_pt++;
1815         }
1816 }
1817
1818 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1819                                       struct sg_table *pages,
1820                                       uint64_t start,
1821                                       enum i915_cache_level cache_level, u32 flags)
1822 {
1823         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1824         gen6_pte_t *pt_vaddr;
1825         unsigned first_entry = start >> PAGE_SHIFT;
1826         unsigned act_pt = first_entry / GEN6_PTES;
1827         unsigned act_pte = first_entry % GEN6_PTES;
1828         struct sg_page_iter sg_iter;
1829
1830         pt_vaddr = NULL;
1831         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1832                 if (pt_vaddr == NULL)
1833                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1834
1835                 pt_vaddr[act_pte] =
1836                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1837                                        cache_level, true, flags);
1838
1839                 if (++act_pte == GEN6_PTES) {
1840                         kunmap_px(ppgtt, pt_vaddr);
1841                         pt_vaddr = NULL;
1842                         act_pt++;
1843                         act_pte = 0;
1844                 }
1845         }
1846         if (pt_vaddr)
1847                 kunmap_px(ppgtt, pt_vaddr);
1848 }
1849
1850 static int gen6_alloc_va_range(struct i915_address_space *vm,
1851                                uint64_t start_in, uint64_t length_in)
1852 {
1853         DECLARE_BITMAP(new_page_tables, I915_PDES);
1854         struct drm_device *dev = vm->dev;
1855         struct drm_i915_private *dev_priv = to_i915(dev);
1856         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1857         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1858         struct i915_page_table *pt;
1859         uint32_t start, length, start_save, length_save;
1860         uint32_t pde, temp;
1861         int ret;
1862
1863         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1864                 return -ENODEV;
1865
1866         start = start_save = start_in;
1867         length = length_save = length_in;
1868
1869         bitmap_zero(new_page_tables, I915_PDES);
1870
1871         /* The allocation is done in two stages so that we can bail out with
1872          * minimal amount of pain. The first stage finds new page tables that
1873          * need allocation. The second stage marks use ptes within the page
1874          * tables.
1875          */
1876         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1877                 if (pt != vm->scratch_pt) {
1878                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1879                         continue;
1880                 }
1881
1882                 /* We've already allocated a page table */
1883                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1884
1885                 pt = alloc_pt(dev);
1886                 if (IS_ERR(pt)) {
1887                         ret = PTR_ERR(pt);
1888                         goto unwind_out;
1889                 }
1890
1891                 gen6_initialize_pt(vm, pt);
1892
1893                 ppgtt->pd.page_table[pde] = pt;
1894                 __set_bit(pde, new_page_tables);
1895                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1896         }
1897
1898         start = start_save;
1899         length = length_save;
1900
1901         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1902                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1903
1904                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1905                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1906                            gen6_pte_count(start, length));
1907
1908                 if (__test_and_clear_bit(pde, new_page_tables))
1909                         gen6_write_pde(&ppgtt->pd, pde, pt);
1910
1911                 trace_i915_page_table_entry_map(vm, pde, pt,
1912                                          gen6_pte_index(start),
1913                                          gen6_pte_count(start, length),
1914                                          GEN6_PTES);
1915                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1916                                 GEN6_PTES);
1917         }
1918
1919         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1920
1921         /* Make sure write is complete before other code can use this page
1922          * table. Also require for WC mapped PTEs */
1923         readl(ggtt->gsm);
1924
1925         mark_tlbs_dirty(ppgtt);
1926         return 0;
1927
1928 unwind_out:
1929         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1930                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1931
1932                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1933                 free_pt(vm->dev, pt);
1934         }
1935
1936         mark_tlbs_dirty(ppgtt);
1937         return ret;
1938 }
1939
1940 static int gen6_init_scratch(struct i915_address_space *vm)
1941 {
1942         struct drm_device *dev = vm->dev;
1943
1944         vm->scratch_page = alloc_scratch_page(dev);
1945         if (IS_ERR(vm->scratch_page))
1946                 return PTR_ERR(vm->scratch_page);
1947
1948         vm->scratch_pt = alloc_pt(dev);
1949         if (IS_ERR(vm->scratch_pt)) {
1950                 free_scratch_page(dev, vm->scratch_page);
1951                 return PTR_ERR(vm->scratch_pt);
1952         }
1953
1954         gen6_initialize_pt(vm, vm->scratch_pt);
1955
1956         return 0;
1957 }
1958
1959 static void gen6_free_scratch(struct i915_address_space *vm)
1960 {
1961         struct drm_device *dev = vm->dev;
1962
1963         free_pt(dev, vm->scratch_pt);
1964         free_scratch_page(dev, vm->scratch_page);
1965 }
1966
1967 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1968 {
1969         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1970         struct i915_page_table *pt;
1971         uint32_t pde;
1972
1973         drm_mm_remove_node(&ppgtt->node);
1974
1975         gen6_for_all_pdes(pt, ppgtt, pde) {
1976                 if (pt != vm->scratch_pt)
1977                         free_pt(ppgtt->base.dev, pt);
1978         }
1979
1980         gen6_free_scratch(vm);
1981 }
1982
1983 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1984 {
1985         struct i915_address_space *vm = &ppgtt->base;
1986         struct drm_device *dev = ppgtt->base.dev;
1987         struct drm_i915_private *dev_priv = to_i915(dev);
1988         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1989         bool retried = false;
1990         int ret;
1991
1992         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1993          * allocator works in address space sizes, so it's multiplied by page
1994          * size. We allocate at the top of the GTT to avoid fragmentation.
1995          */
1996         BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
1997
1998         ret = gen6_init_scratch(vm);
1999         if (ret)
2000                 return ret;
2001
2002 alloc:
2003         ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
2004                                                   &ppgtt->node, GEN6_PD_SIZE,
2005                                                   GEN6_PD_ALIGN, 0,
2006                                                   0, ggtt->base.total,
2007                                                   DRM_MM_TOPDOWN);
2008         if (ret == -ENOSPC && !retried) {
2009                 ret = i915_gem_evict_something(dev, &ggtt->base,
2010                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
2011                                                I915_CACHE_NONE,
2012                                                0, ggtt->base.total,
2013                                                0);
2014                 if (ret)
2015                         goto err_out;
2016
2017                 retried = true;
2018                 goto alloc;
2019         }
2020
2021         if (ret)
2022                 goto err_out;
2023
2024
2025         if (ppgtt->node.start < ggtt->mappable_end)
2026                 DRM_DEBUG("Forced to use aperture for PDEs\n");
2027
2028         return 0;
2029
2030 err_out:
2031         gen6_free_scratch(vm);
2032         return ret;
2033 }
2034
2035 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2036 {
2037         return gen6_ppgtt_allocate_page_directories(ppgtt);
2038 }
2039
2040 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2041                                   uint64_t start, uint64_t length)
2042 {
2043         struct i915_page_table *unused;
2044         uint32_t pde, temp;
2045
2046         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2047                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2048 }
2049
2050 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2051 {
2052         struct drm_device *dev = ppgtt->base.dev;
2053         struct drm_i915_private *dev_priv = to_i915(dev);
2054         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2055         int ret;
2056
2057         ppgtt->base.pte_encode = ggtt->base.pte_encode;
2058         if (IS_GEN6(dev)) {
2059                 ppgtt->switch_mm = gen6_mm_switch;
2060         } else if (IS_HASWELL(dev)) {
2061                 ppgtt->switch_mm = hsw_mm_switch;
2062         } else if (IS_GEN7(dev)) {
2063                 ppgtt->switch_mm = gen7_mm_switch;
2064         } else
2065                 BUG();
2066
2067         if (intel_vgpu_active(dev))
2068                 ppgtt->switch_mm = vgpu_mm_switch;
2069
2070         ret = gen6_ppgtt_alloc(ppgtt);
2071         if (ret)
2072                 return ret;
2073
2074         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2075         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2076         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2077         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2078         ppgtt->base.bind_vma = ppgtt_bind_vma;
2079         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2080         ppgtt->base.start = 0;
2081         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2082         ppgtt->debug_dump = gen6_dump_ppgtt;
2083
2084         ppgtt->pd.base.ggtt_offset =
2085                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2086
2087         ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
2088                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2089
2090         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2091
2092         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2093
2094         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2095                          ppgtt->node.size >> 20,
2096                          ppgtt->node.start / PAGE_SIZE);
2097
2098         DRM_DEBUG("Adding PPGTT at offset %x\n",
2099                   ppgtt->pd.base.ggtt_offset << 10);
2100
2101         return 0;
2102 }
2103
2104 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2105 {
2106         ppgtt->base.dev = dev;
2107
2108         if (INTEL_INFO(dev)->gen < 8)
2109                 return gen6_ppgtt_init(ppgtt);
2110         else
2111                 return gen8_ppgtt_init(ppgtt);
2112 }
2113
2114 static void i915_address_space_init(struct i915_address_space *vm,
2115                                     struct drm_i915_private *dev_priv)
2116 {
2117         drm_mm_init(&vm->mm, vm->start, vm->total);
2118         vm->dev = dev_priv->dev;
2119         INIT_LIST_HEAD(&vm->active_list);
2120         INIT_LIST_HEAD(&vm->inactive_list);
2121         list_add_tail(&vm->global_link, &dev_priv->vm_list);
2122 }
2123
2124 static void gtt_write_workarounds(struct drm_device *dev)
2125 {
2126         struct drm_i915_private *dev_priv = dev->dev_private;
2127
2128         /* This function is for gtt related workarounds. This function is
2129          * called on driver load and after a GPU reset, so you can place
2130          * workarounds here even if they get overwritten by GPU reset.
2131          */
2132         /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2133         if (IS_BROADWELL(dev))
2134                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2135         else if (IS_CHERRYVIEW(dev))
2136                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2137         else if (IS_SKYLAKE(dev))
2138                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2139         else if (IS_BROXTON(dev))
2140                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2141 }
2142
2143 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2144 {
2145         struct drm_i915_private *dev_priv = dev->dev_private;
2146         int ret = 0;
2147
2148         ret = __hw_ppgtt_init(dev, ppgtt);
2149         if (ret == 0) {
2150                 kref_init(&ppgtt->ref);
2151                 i915_address_space_init(&ppgtt->base, dev_priv);
2152         }
2153
2154         return ret;
2155 }
2156
2157 int i915_ppgtt_init_hw(struct drm_device *dev)
2158 {
2159         gtt_write_workarounds(dev);
2160
2161         /* In the case of execlists, PPGTT is enabled by the context descriptor
2162          * and the PDPs are contained within the context itself.  We don't
2163          * need to do anything here. */
2164         if (i915.enable_execlists)
2165                 return 0;
2166
2167         if (!USES_PPGTT(dev))
2168                 return 0;
2169
2170         if (IS_GEN6(dev))
2171                 gen6_ppgtt_enable(dev);
2172         else if (IS_GEN7(dev))
2173                 gen7_ppgtt_enable(dev);
2174         else if (INTEL_INFO(dev)->gen >= 8)
2175                 gen8_ppgtt_enable(dev);
2176         else
2177                 MISSING_CASE(INTEL_INFO(dev)->gen);
2178
2179         return 0;
2180 }
2181
2182 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2183 {
2184         struct drm_i915_private *dev_priv = req->i915;
2185         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2186
2187         if (i915.enable_execlists)
2188                 return 0;
2189
2190         if (!ppgtt)
2191                 return 0;
2192
2193         return ppgtt->switch_mm(ppgtt, req);
2194 }
2195
2196 struct i915_hw_ppgtt *
2197 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2198 {
2199         struct i915_hw_ppgtt *ppgtt;
2200         int ret;
2201
2202         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2203         if (!ppgtt)
2204                 return ERR_PTR(-ENOMEM);
2205
2206         ret = i915_ppgtt_init(dev, ppgtt);
2207         if (ret) {
2208                 kfree(ppgtt);
2209                 return ERR_PTR(ret);
2210         }
2211
2212         ppgtt->file_priv = fpriv;
2213
2214         trace_i915_ppgtt_create(&ppgtt->base);
2215
2216         return ppgtt;
2217 }
2218
2219 void  i915_ppgtt_release(struct kref *kref)
2220 {
2221         struct i915_hw_ppgtt *ppgtt =
2222                 container_of(kref, struct i915_hw_ppgtt, ref);
2223
2224         trace_i915_ppgtt_release(&ppgtt->base);
2225
2226         /* vmas should already be unbound */
2227         WARN_ON(!list_empty(&ppgtt->base.active_list));
2228         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2229
2230         list_del(&ppgtt->base.global_link);
2231         drm_mm_takedown(&ppgtt->base.mm);
2232
2233         ppgtt->base.cleanup(&ppgtt->base);
2234         kfree(ppgtt);
2235 }
2236
2237 extern int intel_iommu_gfx_mapped;
2238 /* Certain Gen5 chipsets require require idling the GPU before
2239  * unmapping anything from the GTT when VT-d is enabled.
2240  */
2241 static bool needs_idle_maps(struct drm_device *dev)
2242 {
2243 #ifdef CONFIG_INTEL_IOMMU
2244         /* Query intel_iommu to see if we need the workaround. Presumably that
2245          * was loaded first.
2246          */
2247         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2248                 return true;
2249 #endif
2250         return false;
2251 }
2252
2253 static bool do_idling(struct drm_i915_private *dev_priv)
2254 {
2255         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2256         bool ret = dev_priv->mm.interruptible;
2257
2258         if (unlikely(ggtt->do_idle_maps)) {
2259                 dev_priv->mm.interruptible = false;
2260                 if (i915_gpu_idle(dev_priv->dev)) {
2261                         DRM_ERROR("Couldn't idle GPU\n");
2262                         /* Wait a bit, in hopes it avoids the hang */
2263                         udelay(10);
2264                 }
2265         }
2266
2267         return ret;
2268 }
2269
2270 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2271 {
2272         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2273
2274         if (unlikely(ggtt->do_idle_maps))
2275                 dev_priv->mm.interruptible = interruptible;
2276 }
2277
2278 void i915_check_and_clear_faults(struct drm_device *dev)
2279 {
2280         struct drm_i915_private *dev_priv = dev->dev_private;
2281         struct intel_engine_cs *engine;
2282
2283         if (INTEL_INFO(dev)->gen < 6)
2284                 return;
2285
2286         for_each_engine(engine, dev_priv) {
2287                 u32 fault_reg;
2288                 fault_reg = I915_READ(RING_FAULT_REG(engine));
2289                 if (fault_reg & RING_FAULT_VALID) {
2290                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2291                                          "\tAddr: 0x%08lx\n"
2292                                          "\tAddress space: %s\n"
2293                                          "\tSource ID: %d\n"
2294                                          "\tType: %d\n",
2295                                          fault_reg & PAGE_MASK,
2296                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2297                                          RING_FAULT_SRCID(fault_reg),
2298                                          RING_FAULT_FAULT_TYPE(fault_reg));
2299                         I915_WRITE(RING_FAULT_REG(engine),
2300                                    fault_reg & ~RING_FAULT_VALID);
2301                 }
2302         }
2303         POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
2304 }
2305
2306 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2307 {
2308         if (INTEL_INFO(dev_priv)->gen < 6) {
2309                 intel_gtt_chipset_flush();
2310         } else {
2311                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2312                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2313         }
2314 }
2315
2316 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2317 {
2318         struct drm_i915_private *dev_priv = to_i915(dev);
2319         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2320
2321         /* Don't bother messing with faults pre GEN6 as we have little
2322          * documentation supporting that it's a good idea.
2323          */
2324         if (INTEL_INFO(dev)->gen < 6)
2325                 return;
2326
2327         i915_check_and_clear_faults(dev);
2328
2329         ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2330                              true);
2331
2332         i915_ggtt_flush(dev_priv);
2333 }
2334
2335 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2336 {
2337         if (!dma_map_sg(&obj->base.dev->pdev->dev,
2338                         obj->pages->sgl, obj->pages->nents,
2339                         PCI_DMA_BIDIRECTIONAL))
2340                 return -ENOSPC;
2341
2342         return 0;
2343 }
2344
2345 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2346 {
2347 #ifdef writeq
2348         writeq(pte, addr);
2349 #else
2350         iowrite32((u32)pte, addr);
2351         iowrite32(pte >> 32, addr + 4);
2352 #endif
2353 }
2354
2355 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2356                                      struct sg_table *st,
2357                                      uint64_t start,
2358                                      enum i915_cache_level level, u32 unused)
2359 {
2360         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2361         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2362         unsigned first_entry = start >> PAGE_SHIFT;
2363         gen8_pte_t __iomem *gtt_entries =
2364                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2365         int i = 0;
2366         struct sg_page_iter sg_iter;
2367         dma_addr_t addr = 0; /* shut up gcc */
2368         int rpm_atomic_seq;
2369
2370         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2371
2372         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2373                 addr = sg_dma_address(sg_iter.sg) +
2374                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
2375                 gen8_set_pte(&gtt_entries[i],
2376                              gen8_pte_encode(addr, level, true));
2377                 i++;
2378         }
2379
2380         /*
2381          * XXX: This serves as a posting read to make sure that the PTE has
2382          * actually been updated. There is some concern that even though
2383          * registers and PTEs are within the same BAR that they are potentially
2384          * of NUMA access patterns. Therefore, even with the way we assume
2385          * hardware should work, we must keep this posting read for paranoia.
2386          */
2387         if (i != 0)
2388                 WARN_ON(readq(&gtt_entries[i-1])
2389                         != gen8_pte_encode(addr, level, true));
2390
2391         /* This next bit makes the above posting read even more important. We
2392          * want to flush the TLBs only after we're certain all the PTE updates
2393          * have finished.
2394          */
2395         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2396         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2397
2398         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2399 }
2400
2401 struct insert_entries {
2402         struct i915_address_space *vm;
2403         struct sg_table *st;
2404         uint64_t start;
2405         enum i915_cache_level level;
2406         u32 flags;
2407 };
2408
2409 static int gen8_ggtt_insert_entries__cb(void *_arg)
2410 {
2411         struct insert_entries *arg = _arg;
2412         gen8_ggtt_insert_entries(arg->vm, arg->st,
2413                                  arg->start, arg->level, arg->flags);
2414         return 0;
2415 }
2416
2417 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2418                                           struct sg_table *st,
2419                                           uint64_t start,
2420                                           enum i915_cache_level level,
2421                                           u32 flags)
2422 {
2423         struct insert_entries arg = { vm, st, start, level, flags };
2424         stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2425 }
2426
2427 /*
2428  * Binds an object into the global gtt with the specified cache level. The object
2429  * will be accessible to the GPU via commands whose operands reference offsets
2430  * within the global GTT as well as accessible by the GPU through the GMADR
2431  * mapped BAR (dev_priv->mm.gtt->gtt).
2432  */
2433 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2434                                      struct sg_table *st,
2435                                      uint64_t start,
2436                                      enum i915_cache_level level, u32 flags)
2437 {
2438         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2439         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2440         unsigned first_entry = start >> PAGE_SHIFT;
2441         gen6_pte_t __iomem *gtt_entries =
2442                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2443         int i = 0;
2444         struct sg_page_iter sg_iter;
2445         dma_addr_t addr = 0;
2446         int rpm_atomic_seq;
2447
2448         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2449
2450         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2451                 addr = sg_page_iter_dma_address(&sg_iter);
2452                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
2453                 i++;
2454         }
2455
2456         /* XXX: This serves as a posting read to make sure that the PTE has
2457          * actually been updated. There is some concern that even though
2458          * registers and PTEs are within the same BAR that they are potentially
2459          * of NUMA access patterns. Therefore, even with the way we assume
2460          * hardware should work, we must keep this posting read for paranoia.
2461          */
2462         if (i != 0) {
2463                 unsigned long gtt = readl(&gtt_entries[i-1]);
2464                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2465         }
2466
2467         /* This next bit makes the above posting read even more important. We
2468          * want to flush the TLBs only after we're certain all the PTE updates
2469          * have finished.
2470          */
2471         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2472         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2473
2474         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2475 }
2476
2477 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2478                                   uint64_t start,
2479                                   uint64_t length,
2480                                   bool use_scratch)
2481 {
2482         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2483         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2484         unsigned first_entry = start >> PAGE_SHIFT;
2485         unsigned num_entries = length >> PAGE_SHIFT;
2486         gen8_pte_t scratch_pte, __iomem *gtt_base =
2487                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2488         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2489         int i;
2490         int rpm_atomic_seq;
2491
2492         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2493
2494         if (WARN(num_entries > max_entries,
2495                  "First entry = %d; Num entries = %d (max=%d)\n",
2496                  first_entry, num_entries, max_entries))
2497                 num_entries = max_entries;
2498
2499         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2500                                       I915_CACHE_LLC,
2501                                       use_scratch);
2502         for (i = 0; i < num_entries; i++)
2503                 gen8_set_pte(&gtt_base[i], scratch_pte);
2504         readl(gtt_base);
2505
2506         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2507 }
2508
2509 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2510                                   uint64_t start,
2511                                   uint64_t length,
2512                                   bool use_scratch)
2513 {
2514         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2515         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2516         unsigned first_entry = start >> PAGE_SHIFT;
2517         unsigned num_entries = length >> PAGE_SHIFT;
2518         gen6_pte_t scratch_pte, __iomem *gtt_base =
2519                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2520         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2521         int i;
2522         int rpm_atomic_seq;
2523
2524         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2525
2526         if (WARN(num_entries > max_entries,
2527                  "First entry = %d; Num entries = %d (max=%d)\n",
2528                  first_entry, num_entries, max_entries))
2529                 num_entries = max_entries;
2530
2531         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2532                                      I915_CACHE_LLC, use_scratch, 0);
2533
2534         for (i = 0; i < num_entries; i++)
2535                 iowrite32(scratch_pte, &gtt_base[i]);
2536         readl(gtt_base);
2537
2538         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2539 }
2540
2541 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2542                                      struct sg_table *pages,
2543                                      uint64_t start,
2544                                      enum i915_cache_level cache_level, u32 unused)
2545 {
2546         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2547         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2548                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2549         int rpm_atomic_seq;
2550
2551         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2552
2553         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2554
2555         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2556
2557 }
2558
2559 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2560                                   uint64_t start,
2561                                   uint64_t length,
2562                                   bool unused)
2563 {
2564         struct drm_i915_private *dev_priv = vm->dev->dev_private;
2565         unsigned first_entry = start >> PAGE_SHIFT;
2566         unsigned num_entries = length >> PAGE_SHIFT;
2567         int rpm_atomic_seq;
2568
2569         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2570
2571         intel_gtt_clear_range(first_entry, num_entries);
2572
2573         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2574 }
2575
2576 static int ggtt_bind_vma(struct i915_vma *vma,
2577                          enum i915_cache_level cache_level,
2578                          u32 flags)
2579 {
2580         struct drm_i915_gem_object *obj = vma->obj;
2581         u32 pte_flags = 0;
2582         int ret;
2583
2584         ret = i915_get_ggtt_vma_pages(vma);
2585         if (ret)
2586                 return ret;
2587
2588         /* Currently applicable only to VLV */
2589         if (obj->gt_ro)
2590                 pte_flags |= PTE_READ_ONLY;
2591
2592         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2593                                 vma->node.start,
2594                                 cache_level, pte_flags);
2595
2596         /*
2597          * Without aliasing PPGTT there's no difference between
2598          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2599          * upgrade to both bound if we bind either to avoid double-binding.
2600          */
2601         vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2602
2603         return 0;
2604 }
2605
2606 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2607                                  enum i915_cache_level cache_level,
2608                                  u32 flags)
2609 {
2610         u32 pte_flags;
2611         int ret;
2612
2613         ret = i915_get_ggtt_vma_pages(vma);
2614         if (ret)
2615                 return ret;
2616
2617         /* Currently applicable only to VLV */
2618         pte_flags = 0;
2619         if (vma->obj->gt_ro)
2620                 pte_flags |= PTE_READ_ONLY;
2621
2622
2623         if (flags & GLOBAL_BIND) {
2624                 vma->vm->insert_entries(vma->vm,
2625                                         vma->ggtt_view.pages,
2626                                         vma->node.start,
2627                                         cache_level, pte_flags);
2628         }
2629
2630         if (flags & LOCAL_BIND) {
2631                 struct i915_hw_ppgtt *appgtt =
2632                         to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2633                 appgtt->base.insert_entries(&appgtt->base,
2634                                             vma->ggtt_view.pages,
2635                                             vma->node.start,
2636                                             cache_level, pte_flags);
2637         }
2638
2639         return 0;
2640 }
2641
2642 static void ggtt_unbind_vma(struct i915_vma *vma)
2643 {
2644         struct drm_device *dev = vma->vm->dev;
2645         struct drm_i915_private *dev_priv = dev->dev_private;
2646         struct drm_i915_gem_object *obj = vma->obj;
2647         const uint64_t size = min_t(uint64_t,
2648                                     obj->base.size,
2649                                     vma->node.size);
2650
2651         if (vma->bound & GLOBAL_BIND) {
2652                 vma->vm->clear_range(vma->vm,
2653                                      vma->node.start,
2654                                      size,
2655                                      true);
2656         }
2657
2658         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2659                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2660
2661                 appgtt->base.clear_range(&appgtt->base,
2662                                          vma->node.start,
2663                                          size,
2664                                          true);
2665         }
2666 }
2667
2668 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2669 {
2670         struct drm_device *dev = obj->base.dev;
2671         struct drm_i915_private *dev_priv = dev->dev_private;
2672         bool interruptible;
2673
2674         interruptible = do_idling(dev_priv);
2675
2676         dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2677                      PCI_DMA_BIDIRECTIONAL);
2678
2679         undo_idling(dev_priv, interruptible);
2680 }
2681
2682 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2683                                   unsigned long color,
2684                                   u64 *start,
2685                                   u64 *end)
2686 {
2687         if (node->color != color)
2688                 *start += 4096;
2689
2690         if (!list_empty(&node->node_list)) {
2691                 node = list_entry(node->node_list.next,
2692                                   struct drm_mm_node,
2693                                   node_list);
2694                 if (node->allocated && node->color != color)
2695                         *end -= 4096;
2696         }
2697 }
2698
2699 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2700                                      u64 start,
2701                                      u64 mappable_end,
2702                                      u64 end)
2703 {
2704         /* Let GEM Manage all of the aperture.
2705          *
2706          * However, leave one page at the end still bound to the scratch page.
2707          * There are a number of places where the hardware apparently prefetches
2708          * past the end of the object, and we've seen multiple hangs with the
2709          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2710          * aperture.  One page should be enough to keep any prefetching inside
2711          * of the aperture.
2712          */
2713         struct drm_i915_private *dev_priv = to_i915(dev);
2714         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2715         struct drm_mm_node *entry;
2716         struct drm_i915_gem_object *obj;
2717         unsigned long hole_start, hole_end;
2718         int ret;
2719
2720         BUG_ON(mappable_end > end);
2721
2722         ggtt->base.start = start;
2723
2724         /* Subtract the guard page before address space initialization to
2725          * shrink the range used by drm_mm */
2726         ggtt->base.total = end - start - PAGE_SIZE;
2727         i915_address_space_init(&ggtt->base, dev_priv);
2728         ggtt->base.total += PAGE_SIZE;
2729
2730         if (intel_vgpu_active(dev)) {
2731                 ret = intel_vgt_balloon(dev);
2732                 if (ret)
2733                         return ret;
2734         }
2735
2736         if (!HAS_LLC(dev))
2737                 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
2738
2739         /* Mark any preallocated objects as occupied */
2740         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2741                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base);
2742
2743                 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2744                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2745
2746                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2747                 ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
2748                 if (ret) {
2749                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2750                         return ret;
2751                 }
2752                 vma->bound |= GLOBAL_BIND;
2753                 __i915_vma_set_map_and_fenceable(vma);
2754                 list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
2755         }
2756
2757         /* Clear any non-preallocated blocks */
2758         drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
2759                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2760                               hole_start, hole_end);
2761                 ggtt->base.clear_range(&ggtt->base, hole_start,
2762                                      hole_end - hole_start, true);
2763         }
2764
2765         /* And finally clear the reserved guard page */
2766         ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true);
2767
2768         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2769                 struct i915_hw_ppgtt *ppgtt;
2770
2771                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2772                 if (!ppgtt)
2773                         return -ENOMEM;
2774
2775                 ret = __hw_ppgtt_init(dev, ppgtt);
2776                 if (ret) {
2777                         ppgtt->base.cleanup(&ppgtt->base);
2778                         kfree(ppgtt);
2779                         return ret;
2780                 }
2781
2782                 if (ppgtt->base.allocate_va_range)
2783                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2784                                                             ppgtt->base.total);
2785                 if (ret) {
2786                         ppgtt->base.cleanup(&ppgtt->base);
2787                         kfree(ppgtt);
2788                         return ret;
2789                 }
2790
2791                 ppgtt->base.clear_range(&ppgtt->base,
2792                                         ppgtt->base.start,
2793                                         ppgtt->base.total,
2794                                         true);
2795
2796                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2797                 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2798                 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
2799         }
2800
2801         return 0;
2802 }
2803
2804 /**
2805  * i915_gem_init_ggtt - Initialize GEM for Global GTT
2806  * @dev: DRM device
2807  */
2808 void i915_gem_init_ggtt(struct drm_device *dev)
2809 {
2810         struct drm_i915_private *dev_priv = to_i915(dev);
2811         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2812
2813         i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
2814 }
2815
2816 /**
2817  * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2818  * @dev: DRM device
2819  */
2820 void i915_ggtt_cleanup_hw(struct drm_device *dev)
2821 {
2822         struct drm_i915_private *dev_priv = to_i915(dev);
2823         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2824
2825         if (dev_priv->mm.aliasing_ppgtt) {
2826                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2827
2828                 ppgtt->base.cleanup(&ppgtt->base);
2829         }
2830
2831         i915_gem_cleanup_stolen(dev);
2832
2833         if (drm_mm_initialized(&ggtt->base.mm)) {
2834                 if (intel_vgpu_active(dev))
2835                         intel_vgt_deballoon();
2836
2837                 drm_mm_takedown(&ggtt->base.mm);
2838                 list_del(&ggtt->base.global_link);
2839         }
2840
2841         ggtt->base.cleanup(&ggtt->base);
2842 }
2843
2844 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2845 {
2846         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2847         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2848         return snb_gmch_ctl << 20;
2849 }
2850
2851 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2852 {
2853         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2854         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2855         if (bdw_gmch_ctl)
2856                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2857
2858 #ifdef CONFIG_X86_32
2859         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2860         if (bdw_gmch_ctl > 4)
2861                 bdw_gmch_ctl = 4;
2862 #endif
2863
2864         return bdw_gmch_ctl << 20;
2865 }
2866
2867 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2868 {
2869         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2870         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2871
2872         if (gmch_ctrl)
2873                 return 1 << (20 + gmch_ctrl);
2874
2875         return 0;
2876 }
2877
2878 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2879 {
2880         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2881         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2882         return snb_gmch_ctl << 25; /* 32 MB units */
2883 }
2884
2885 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2886 {
2887         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2888         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2889         return bdw_gmch_ctl << 25; /* 32 MB units */
2890 }
2891
2892 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2893 {
2894         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2895         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2896
2897         /*
2898          * 0x0  to 0x10: 32MB increments starting at 0MB
2899          * 0x11 to 0x16: 4MB increments starting at 8MB
2900          * 0x17 to 0x1d: 4MB increments start at 36MB
2901          */
2902         if (gmch_ctrl < 0x11)
2903                 return gmch_ctrl << 25;
2904         else if (gmch_ctrl < 0x17)
2905                 return (gmch_ctrl - 0x11 + 2) << 22;
2906         else
2907                 return (gmch_ctrl - 0x17 + 9) << 22;
2908 }
2909
2910 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2911 {
2912         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2913         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2914
2915         if (gen9_gmch_ctl < 0xf0)
2916                 return gen9_gmch_ctl << 25; /* 32 MB units */
2917         else
2918                 /* 4MB increments starting at 0xf0 for 4MB */
2919                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2920 }
2921
2922 static int ggtt_probe_common(struct drm_device *dev,
2923                              size_t gtt_size)
2924 {
2925         struct drm_i915_private *dev_priv = to_i915(dev);
2926         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2927         struct i915_page_scratch *scratch_page;
2928         phys_addr_t ggtt_phys_addr;
2929
2930         /* For Modern GENs the PTEs and register space are split in the BAR */
2931         ggtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2932                          (pci_resource_len(dev->pdev, 0) / 2);
2933
2934         /*
2935          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2936          * dropped. For WC mappings in general we have 64 byte burst writes
2937          * when the WC buffer is flushed, so we can't use it, but have to
2938          * resort to an uncached mapping. The WC issue is easily caught by the
2939          * readback check when writing GTT PTE entries.
2940          */
2941         if (IS_BROXTON(dev))
2942                 ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size);
2943         else
2944                 ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size);
2945         if (!ggtt->gsm) {
2946                 DRM_ERROR("Failed to map the gtt page table\n");
2947                 return -ENOMEM;
2948         }
2949
2950         scratch_page = alloc_scratch_page(dev);
2951         if (IS_ERR(scratch_page)) {
2952                 DRM_ERROR("Scratch setup failed\n");
2953                 /* iounmap will also get called at remove, but meh */
2954                 iounmap(ggtt->gsm);
2955                 return PTR_ERR(scratch_page);
2956         }
2957
2958         ggtt->base.scratch_page = scratch_page;
2959
2960         return 0;
2961 }
2962
2963 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2964  * bits. When using advanced contexts each context stores its own PAT, but
2965  * writing this data shouldn't be harmful even in those cases. */
2966 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2967 {
2968         uint64_t pat;
2969
2970         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2971               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2972               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2973               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2974               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2975               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2976               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2977               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2978
2979         if (!USES_PPGTT(dev_priv))
2980                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2981                  * so RTL will always use the value corresponding to
2982                  * pat_sel = 000".
2983                  * So let's disable cache for GGTT to avoid screen corruptions.
2984                  * MOCS still can be used though.
2985                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2986                  * before this patch, i.e. the same uncached + snooping access
2987                  * like on gen6/7 seems to be in effect.
2988                  * - So this just fixes blitter/render access. Again it looks
2989                  * like it's not just uncached access, but uncached + snooping.
2990                  * So we can still hold onto all our assumptions wrt cpu
2991                  * clflushing on LLC machines.
2992                  */
2993                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2994
2995         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2996          * write would work. */
2997         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2998         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2999 }
3000
3001 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3002 {
3003         uint64_t pat;
3004
3005         /*
3006          * Map WB on BDW to snooped on CHV.
3007          *
3008          * Only the snoop bit has meaning for CHV, the rest is
3009          * ignored.
3010          *
3011          * The hardware will never snoop for certain types of accesses:
3012          * - CPU GTT (GMADR->GGTT->no snoop->memory)
3013          * - PPGTT page tables
3014          * - some other special cycles
3015          *
3016          * As with BDW, we also need to consider the following for GT accesses:
3017          * "For GGTT, there is NO pat_sel[2:0] from the entry,
3018          * so RTL will always use the value corresponding to
3019          * pat_sel = 000".
3020          * Which means we must set the snoop bit in PAT entry 0
3021          * in order to keep the global status page working.
3022          */
3023         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3024               GEN8_PPAT(1, 0) |
3025               GEN8_PPAT(2, 0) |
3026               GEN8_PPAT(3, 0) |
3027               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3028               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3029               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3030               GEN8_PPAT(7, CHV_PPAT_SNOOP);
3031
3032         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3033         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
3034 }
3035
3036 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
3037 {
3038         struct drm_device *dev = ggtt->base.dev;
3039         struct drm_i915_private *dev_priv = to_i915(dev);
3040         u16 snb_gmch_ctl;
3041         int ret;
3042
3043         /* TODO: We're not aware of mappable constraints on gen8 yet */
3044         ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3045         ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
3046
3047         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3048                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3049
3050         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3051
3052         if (INTEL_INFO(dev)->gen >= 9) {
3053                 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3054                 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
3055         } else if (IS_CHERRYVIEW(dev)) {
3056                 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3057                 ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
3058         } else {
3059                 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3060                 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
3061         }
3062
3063         ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3064
3065         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3066                 chv_setup_private_ppat(dev_priv);
3067         else
3068                 bdw_setup_private_ppat(dev_priv);
3069
3070         ret = ggtt_probe_common(dev, ggtt->size);
3071
3072         ggtt->base.clear_range = gen8_ggtt_clear_range;
3073         if (IS_CHERRYVIEW(dev_priv))
3074                 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3075         else
3076                 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3077         ggtt->base.bind_vma = ggtt_bind_vma;
3078         ggtt->base.unbind_vma = ggtt_unbind_vma;
3079
3080         return ret;
3081 }
3082
3083 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
3084 {
3085         struct drm_device *dev = ggtt->base.dev;
3086         u16 snb_gmch_ctl;
3087         int ret;
3088
3089         ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3090         ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
3091
3092         /* 64/512MB is the current min/max we actually know of, but this is just
3093          * a coarse sanity check.
3094          */
3095         if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
3096                 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
3097                 return -ENXIO;
3098         }
3099
3100         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3101                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3102         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3103
3104         ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3105         ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
3106         ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3107
3108         ret = ggtt_probe_common(dev, ggtt->size);
3109
3110         ggtt->base.clear_range = gen6_ggtt_clear_range;
3111         ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3112         ggtt->base.bind_vma = ggtt_bind_vma;
3113         ggtt->base.unbind_vma = ggtt_unbind_vma;
3114
3115         return ret;
3116 }
3117
3118 static void gen6_gmch_remove(struct i915_address_space *vm)
3119 {
3120         struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
3121
3122         iounmap(ggtt->gsm);
3123         free_scratch_page(vm->dev, vm->scratch_page);
3124 }
3125
3126 static int i915_gmch_probe(struct i915_ggtt *ggtt)
3127 {
3128         struct drm_device *dev = ggtt->base.dev;
3129         struct drm_i915_private *dev_priv = to_i915(dev);
3130         int ret;
3131
3132         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3133         if (!ret) {
3134                 DRM_ERROR("failed to set up gmch\n");
3135                 return -EIO;
3136         }
3137
3138         intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3139                       &ggtt->mappable_base, &ggtt->mappable_end);
3140
3141         ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
3142         ggtt->base.insert_entries = i915_ggtt_insert_entries;
3143         ggtt->base.clear_range = i915_ggtt_clear_range;
3144         ggtt->base.bind_vma = ggtt_bind_vma;
3145         ggtt->base.unbind_vma = ggtt_unbind_vma;
3146
3147         if (unlikely(ggtt->do_idle_maps))
3148                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3149
3150         return 0;
3151 }
3152
3153 static void i915_gmch_remove(struct i915_address_space *vm)
3154 {
3155         intel_gmch_remove();
3156 }
3157
3158 /**
3159  * i915_ggtt_init_hw - Initialize GGTT hardware
3160  * @dev: DRM device
3161  */
3162 int i915_ggtt_init_hw(struct drm_device *dev)
3163 {
3164         struct drm_i915_private *dev_priv = to_i915(dev);
3165         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3166         int ret;
3167
3168         if (INTEL_INFO(dev)->gen <= 5) {
3169                 ggtt->probe = i915_gmch_probe;
3170                 ggtt->base.cleanup = i915_gmch_remove;
3171         } else if (INTEL_INFO(dev)->gen < 8) {
3172                 ggtt->probe = gen6_gmch_probe;
3173                 ggtt->base.cleanup = gen6_gmch_remove;
3174
3175                 if (HAS_EDRAM(dev))
3176                         ggtt->base.pte_encode = iris_pte_encode;
3177                 else if (IS_HASWELL(dev))
3178                         ggtt->base.pte_encode = hsw_pte_encode;
3179                 else if (IS_VALLEYVIEW(dev))
3180                         ggtt->base.pte_encode = byt_pte_encode;
3181                 else if (INTEL_INFO(dev)->gen >= 7)
3182                         ggtt->base.pte_encode = ivb_pte_encode;
3183                 else
3184                         ggtt->base.pte_encode = snb_pte_encode;
3185         } else {
3186                 ggtt->probe = gen8_gmch_probe;
3187                 ggtt->base.cleanup = gen6_gmch_remove;
3188         }
3189
3190         ggtt->base.dev = dev;
3191         ggtt->base.is_ggtt = true;
3192
3193         ret = ggtt->probe(ggtt);
3194         if (ret)
3195                 return ret;
3196
3197         if ((ggtt->base.total - 1) >> 32) {
3198                 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3199                           "of address space! Found %lldM!\n",
3200                           ggtt->base.total >> 20);
3201                 ggtt->base.total = 1ULL << 32;
3202                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3203         }
3204
3205         /*
3206          * Initialise stolen early so that we may reserve preallocated
3207          * objects for the BIOS to KMS transition.
3208          */
3209         ret = i915_gem_init_stolen(dev);
3210         if (ret)
3211                 goto out_gtt_cleanup;
3212
3213         /* GMADR is the PCI mmio aperture into the global GTT. */
3214         DRM_INFO("Memory usable by graphics device = %lluM\n",
3215                  ggtt->base.total >> 20);
3216         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3217         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
3218 #ifdef CONFIG_INTEL_IOMMU
3219         if (intel_iommu_gfx_mapped)
3220                 DRM_INFO("VT-d active for gfx access\n");
3221 #endif
3222         /*
3223          * i915.enable_ppgtt is read-only, so do an early pass to validate the
3224          * user's requested state against the hardware/driver capabilities.  We
3225          * do this now so that we can print out any log messages once rather
3226          * than every time we check intel_enable_ppgtt().
3227          */
3228         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3229         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3230
3231         return 0;
3232
3233 out_gtt_cleanup:
3234         ggtt->base.cleanup(&ggtt->base);
3235
3236         return ret;
3237 }
3238
3239 int i915_ggtt_enable_hw(struct drm_device *dev)
3240 {
3241         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3242                 return -EIO;
3243
3244         return 0;
3245 }
3246
3247 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3248 {
3249         struct drm_i915_private *dev_priv = to_i915(dev);
3250         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3251         struct drm_i915_gem_object *obj;
3252         struct i915_vma *vma;
3253         bool flush;
3254
3255         i915_check_and_clear_faults(dev);
3256
3257         /* First fill our portion of the GTT with scratch pages */
3258         ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3259                                true);
3260
3261         /* Cache flush objects bound into GGTT and rebind them. */
3262         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3263                 flush = false;
3264                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3265                         if (vma->vm != &ggtt->base)
3266                                 continue;
3267
3268                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
3269                                               PIN_UPDATE));
3270
3271                         flush = true;
3272                 }
3273
3274                 if (flush)
3275                         i915_gem_clflush_object(obj, obj->pin_display);
3276         }
3277
3278         if (INTEL_INFO(dev)->gen >= 8) {
3279                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3280                         chv_setup_private_ppat(dev_priv);
3281                 else
3282                         bdw_setup_private_ppat(dev_priv);
3283
3284                 return;
3285         }
3286
3287         if (USES_PPGTT(dev)) {
3288                 struct i915_address_space *vm;
3289
3290                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3291                         /* TODO: Perhaps it shouldn't be gen6 specific */
3292
3293                         struct i915_hw_ppgtt *ppgtt;
3294
3295                         if (vm->is_ggtt)
3296                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3297                         else
3298                                 ppgtt = i915_vm_to_ppgtt(vm);
3299
3300                         gen6_write_page_range(dev_priv, &ppgtt->pd,
3301                                               0, ppgtt->base.total);
3302                 }
3303         }
3304
3305         i915_ggtt_flush(dev_priv);
3306 }
3307
3308 static struct i915_vma *
3309 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3310                       struct i915_address_space *vm,
3311                       const struct i915_ggtt_view *ggtt_view)
3312 {
3313         struct i915_vma *vma;
3314
3315         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3316                 return ERR_PTR(-EINVAL);
3317
3318         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3319         if (vma == NULL)
3320                 return ERR_PTR(-ENOMEM);
3321
3322         INIT_LIST_HEAD(&vma->vm_link);
3323         INIT_LIST_HEAD(&vma->obj_link);
3324         INIT_LIST_HEAD(&vma->exec_list);
3325         vma->vm = vm;
3326         vma->obj = obj;
3327         vma->is_ggtt = i915_is_ggtt(vm);
3328
3329         if (i915_is_ggtt(vm))
3330                 vma->ggtt_view = *ggtt_view;
3331         else
3332                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3333
3334         list_add_tail(&vma->obj_link, &obj->vma_list);
3335
3336         return vma;
3337 }
3338
3339 struct i915_vma *
3340 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3341                                   struct i915_address_space *vm)
3342 {
3343         struct i915_vma *vma;
3344
3345         vma = i915_gem_obj_to_vma(obj, vm);
3346         if (!vma)
3347                 vma = __i915_gem_vma_create(obj, vm,
3348                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3349
3350         return vma;
3351 }
3352
3353 struct i915_vma *
3354 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3355                                        const struct i915_ggtt_view *view)
3356 {
3357         struct drm_device *dev = obj->base.dev;
3358         struct drm_i915_private *dev_priv = to_i915(dev);
3359         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3360         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
3361
3362         if (!vma)
3363                 vma = __i915_gem_vma_create(obj, &ggtt->base, view);
3364
3365         return vma;
3366
3367 }
3368
3369 static struct scatterlist *
3370 rotate_pages(const dma_addr_t *in, unsigned int offset,
3371              unsigned int width, unsigned int height,
3372              unsigned int stride,
3373              struct sg_table *st, struct scatterlist *sg)
3374 {
3375         unsigned int column, row;
3376         unsigned int src_idx;
3377
3378         for (column = 0; column < width; column++) {
3379                 src_idx = stride * (height - 1) + column;
3380                 for (row = 0; row < height; row++) {
3381                         st->nents++;
3382                         /* We don't need the pages, but need to initialize
3383                          * the entries so the sg list can be happily traversed.
3384                          * The only thing we need are DMA addresses.
3385                          */
3386                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3387                         sg_dma_address(sg) = in[offset + src_idx];
3388                         sg_dma_len(sg) = PAGE_SIZE;
3389                         sg = sg_next(sg);
3390                         src_idx -= stride;
3391                 }
3392         }
3393
3394         return sg;
3395 }
3396
3397 static struct sg_table *
3398 intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
3399                           struct drm_i915_gem_object *obj)
3400 {
3401         unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
3402         unsigned int size_pages_uv;
3403         struct sg_page_iter sg_iter;
3404         unsigned long i;
3405         dma_addr_t *page_addr_list;
3406         struct sg_table *st;
3407         unsigned int uv_start_page;
3408         struct scatterlist *sg;
3409         int ret = -ENOMEM;
3410
3411         /* Allocate a temporary list of source pages for random access. */
3412         page_addr_list = drm_malloc_gfp(obj->base.size / PAGE_SIZE,
3413                                         sizeof(dma_addr_t),
3414                                         GFP_TEMPORARY);
3415         if (!page_addr_list)
3416                 return ERR_PTR(ret);
3417
3418         /* Account for UV plane with NV12. */
3419         if (rot_info->pixel_format == DRM_FORMAT_NV12)
3420                 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
3421         else
3422                 size_pages_uv = 0;
3423
3424         /* Allocate target SG list. */
3425         st = kmalloc(sizeof(*st), GFP_KERNEL);
3426         if (!st)
3427                 goto err_st_alloc;
3428
3429         ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3430         if (ret)
3431                 goto err_sg_alloc;
3432
3433         /* Populate source page list from the object. */
3434         i = 0;
3435         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3436                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3437                 i++;
3438         }
3439
3440         st->nents = 0;
3441         sg = st->sgl;
3442
3443         /* Rotate the pages. */
3444         sg = rotate_pages(page_addr_list, 0,
3445                           rot_info->plane[0].width, rot_info->plane[0].height,
3446                           rot_info->plane[0].width,
3447                           st, sg);
3448
3449         /* Append the UV plane if NV12. */
3450         if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3451                 uv_start_page = size_pages;
3452
3453                 /* Check for tile-row un-alignment. */
3454                 if (offset_in_page(rot_info->uv_offset))
3455                         uv_start_page--;
3456
3457                 rot_info->uv_start_page = uv_start_page;
3458
3459                 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3460                                   rot_info->plane[1].width, rot_info->plane[1].height,
3461                                   rot_info->plane[1].width,
3462                                   st, sg);
3463         }
3464
3465         DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3466                       obj->base.size, rot_info->plane[0].width,
3467                       rot_info->plane[0].height, size_pages + size_pages_uv,
3468                       size_pages);
3469
3470         drm_free_large(page_addr_list);
3471
3472         return st;
3473
3474 err_sg_alloc:
3475         kfree(st);
3476 err_st_alloc:
3477         drm_free_large(page_addr_list);
3478
3479         DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3480                       obj->base.size, ret, rot_info->plane[0].width,
3481                       rot_info->plane[0].height, size_pages + size_pages_uv,
3482                       size_pages);
3483         return ERR_PTR(ret);
3484 }
3485
3486 static struct sg_table *
3487 intel_partial_pages(const struct i915_ggtt_view *view,
3488                     struct drm_i915_gem_object *obj)
3489 {
3490         struct sg_table *st;
3491         struct scatterlist *sg;
3492         struct sg_page_iter obj_sg_iter;
3493         int ret = -ENOMEM;
3494
3495         st = kmalloc(sizeof(*st), GFP_KERNEL);
3496         if (!st)
3497                 goto err_st_alloc;
3498
3499         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3500         if (ret)
3501                 goto err_sg_alloc;
3502
3503         sg = st->sgl;
3504         st->nents = 0;
3505         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3506                 view->params.partial.offset)
3507         {
3508                 if (st->nents >= view->params.partial.size)
3509                         break;
3510
3511                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3512                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3513                 sg_dma_len(sg) = PAGE_SIZE;
3514
3515                 sg = sg_next(sg);
3516                 st->nents++;
3517         }
3518
3519         return st;
3520
3521 err_sg_alloc:
3522         kfree(st);
3523 err_st_alloc:
3524         return ERR_PTR(ret);
3525 }
3526
3527 static int
3528 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3529 {
3530         int ret = 0;
3531
3532         if (vma->ggtt_view.pages)
3533                 return 0;
3534
3535         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3536                 vma->ggtt_view.pages = vma->obj->pages;
3537         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3538                 vma->ggtt_view.pages =
3539                         intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
3540         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3541                 vma->ggtt_view.pages =
3542                         intel_partial_pages(&vma->ggtt_view, vma->obj);
3543         else
3544                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3545                           vma->ggtt_view.type);
3546
3547         if (!vma->ggtt_view.pages) {
3548                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3549                           vma->ggtt_view.type);
3550                 ret = -EINVAL;
3551         } else if (IS_ERR(vma->ggtt_view.pages)) {
3552                 ret = PTR_ERR(vma->ggtt_view.pages);
3553                 vma->ggtt_view.pages = NULL;
3554                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3555                           vma->ggtt_view.type, ret);
3556         }
3557
3558         return ret;
3559 }
3560
3561 /**
3562  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3563  * @vma: VMA to map
3564  * @cache_level: mapping cache level
3565  * @flags: flags like global or local mapping
3566  *
3567  * DMA addresses are taken from the scatter-gather table of this object (or of
3568  * this VMA in case of non-default GGTT views) and PTE entries set up.
3569  * Note that DMA addresses are also the only part of the SG table we care about.
3570  */
3571 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3572                   u32 flags)
3573 {
3574         int ret;
3575         u32 bind_flags;
3576
3577         if (WARN_ON(flags == 0))
3578                 return -EINVAL;
3579
3580         bind_flags = 0;
3581         if (flags & PIN_GLOBAL)
3582                 bind_flags |= GLOBAL_BIND;
3583         if (flags & PIN_USER)
3584                 bind_flags |= LOCAL_BIND;
3585
3586         if (flags & PIN_UPDATE)
3587                 bind_flags |= vma->bound;
3588         else
3589                 bind_flags &= ~vma->bound;
3590
3591         if (bind_flags == 0)
3592                 return 0;
3593
3594         if (vma->bound == 0 && vma->vm->allocate_va_range) {
3595                 /* XXX: i915_vma_pin() will fix this +- hack */
3596                 vma->pin_count++;
3597                 trace_i915_va_alloc(vma);
3598                 ret = vma->vm->allocate_va_range(vma->vm,
3599                                                  vma->node.start,
3600                                                  vma->node.size);
3601                 vma->pin_count--;
3602                 if (ret)
3603                         return ret;
3604         }
3605
3606         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3607         if (ret)
3608                 return ret;
3609
3610         vma->bound |= bind_flags;
3611
3612         return 0;
3613 }
3614
3615 /**
3616  * i915_ggtt_view_size - Get the size of a GGTT view.
3617  * @obj: Object the view is of.
3618  * @view: The view in question.
3619  *
3620  * @return The size of the GGTT view in bytes.
3621  */
3622 size_t
3623 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3624                     const struct i915_ggtt_view *view)
3625 {
3626         if (view->type == I915_GGTT_VIEW_NORMAL) {
3627                 return obj->base.size;
3628         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3629                 return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
3630         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3631                 return view->params.partial.size << PAGE_SHIFT;
3632         } else {
3633                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3634                 return obj->base.size;
3635         }
3636 }