drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_vgpu.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  71  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  72  * parameter encapsulating all metadata required to implement a view.
  73  *
  74  * As a helper for callers which are only interested in the normal view,
  75  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  76  * GEM API functions, the ones not taking the view parameter, are operating on,
  77  * or with the normal GGTT view.
  78  *
  79  * Code wanting to add or use a new GGTT view needs to:
  80  *
  81  * 1. Add a new enum with a suitable name.
  82  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  83  * 3. Add support to i915_get_vma_pages().
  84  *
  85  * New views are required to build a scatter-gather table from within the
  86  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  87  * exists for the lifetime of an VMA.
  88  *
  89  * Core API is designed to have copy semantics which means that passed in
  90  * struct i915_ggtt_view does not need to be persistent (left around after
  91  * calling the core API functions).
  92  *
  93  */
  94
  95 static int
  96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  97
  98 const struct i915_ggtt_view i915_ggtt_view_normal;
  99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 100         .type = I915_GGTT_VIEW_ROTATED
 101 };
 102
 103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 104 {
 105         bool has_aliasing_ppgtt;
 106         bool has_full_ppgtt;
 107
 108         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 109         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 110
 111         if (intel_vgpu_active(dev))
 112                 has_full_ppgtt = false; /* emulation is too hard */
 113
 114         /*
 115          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 116          * execlists, the sole mechanism available to submit work.
 117          */
 118         if (INTEL_INFO(dev)->gen < 9 &&
 119             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 120                 return 0;
 121
 122         if (enable_ppgtt == 1)
 123                 return 1;
 124
 125         if (enable_ppgtt == 2 && has_full_ppgtt)
 126                 return 2;
 127
 128 #ifdef CONFIG_INTEL_IOMMU
 129         /* Disable ppgtt on SNB if VT-d is on. */
 130         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 131                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 132                 return 0;
 133         }
 134 #endif
 135
 136         /* Early VLV doesn't have this */
 137         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 138             dev->pdev->revision < 0xb) {
 139                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 140                 return 0;
 141         }
 142
 143         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 144                 return 2;
 145         else
 146                 return has_aliasing_ppgtt ? 1 : 0;
 147 }
 148
 149 static int ppgtt_bind_vma(struct i915_vma *vma,
 150                           enum i915_cache_level cache_level,
 151                           u32 unused)
 152 {
 153         u32 pte_flags = 0;
 154
 155         /* Currently applicable only to VLV */
 156         if (vma->obj->gt_ro)
 157                 pte_flags |= PTE_READ_ONLY;
 158
 159         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 160                                 cache_level, pte_flags);
 161
 162         return 0;
 163 }
 164
 165 static void ppgtt_unbind_vma(struct i915_vma *vma)
 166 {
 167         vma->vm->clear_range(vma->vm,
 168                              vma->node.start,
 169                              vma->obj->base.size,
 170                              true);
 171 }
 172
 173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 174                                   enum i915_cache_level level,
 175                                   bool valid)
 176 {
 177         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 178         pte |= addr;
 179
 180         switch (level) {
 181         case I915_CACHE_NONE:
 182                 pte |= PPAT_UNCACHED_INDEX;
 183                 break;
 184         case I915_CACHE_WT:
 185                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 186                 break;
 187         default:
 188                 pte |= PPAT_CACHED_INDEX;
 189                 break;
 190         }
 191
 192         return pte;
 193 }
 194
 195 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 196                                   const enum i915_cache_level level)
 197 {
 198         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 199         pde |= addr;
 200         if (level != I915_CACHE_NONE)
 201                 pde |= PPAT_CACHED_PDE_INDEX;
 202         else
 203                 pde |= PPAT_UNCACHED_INDEX;
 204         return pde;
 205 }
 206
 207 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 208                                  enum i915_cache_level level,
 209                                  bool valid, u32 unused)
 210 {
 211         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 212         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 213
 214         switch (level) {
 215         case I915_CACHE_L3_LLC:
 216         case I915_CACHE_LLC:
 217                 pte |= GEN6_PTE_CACHE_LLC;
 218                 break;
 219         case I915_CACHE_NONE:
 220                 pte |= GEN6_PTE_UNCACHED;
 221                 break;
 222         default:
 223                 MISSING_CASE(level);
 224         }
 225
 226         return pte;
 227 }
 228
 229 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 230                                  enum i915_cache_level level,
 231                                  bool valid, u32 unused)
 232 {
 233         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 234         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 235
 236         switch (level) {
 237         case I915_CACHE_L3_LLC:
 238                 pte |= GEN7_PTE_CACHE_L3_LLC;
 239                 break;
 240         case I915_CACHE_LLC:
 241                 pte |= GEN6_PTE_CACHE_LLC;
 242                 break;
 243         case I915_CACHE_NONE:
 244                 pte |= GEN6_PTE_UNCACHED;
 245                 break;
 246         default:
 247                 MISSING_CASE(level);
 248         }
 249
 250         return pte;
 251 }
 252
 253 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 254                                  enum i915_cache_level level,
 255                                  bool valid, u32 flags)
 256 {
 257         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 258         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 259
 260         if (!(flags & PTE_READ_ONLY))
 261                 pte |= BYT_PTE_WRITEABLE;
 262
 263         if (level != I915_CACHE_NONE)
 264                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 265
 266         return pte;
 267 }
 268
 269 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 270                                  enum i915_cache_level level,
 271                                  bool valid, u32 unused)
 272 {
 273         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 274         pte |= HSW_PTE_ADDR_ENCODE(addr);
 275
 276         if (level != I915_CACHE_NONE)
 277                 pte |= HSW_WB_LLC_AGE3;
 278
 279         return pte;
 280 }
 281
 282 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 283                                   enum i915_cache_level level,
 284                                   bool valid, u32 unused)
 285 {
 286         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 287         pte |= HSW_PTE_ADDR_ENCODE(addr);
 288
 289         switch (level) {
 290         case I915_CACHE_NONE:
 291                 break;
 292         case I915_CACHE_WT:
 293                 pte |= HSW_WT_ELLC_LLC_AGE3;
 294                 break;
 295         default:
 296                 pte |= HSW_WB_ELLC_LLC_AGE3;
 297                 break;
 298         }
 299
 300         return pte;
 301 }
 302
 303 static int __setup_page_dma(struct drm_device *dev,
 304                             struct i915_page_dma *p, gfp_t flags)
 305 {
 306         struct device *device = &dev->pdev->dev;
 307
 308         p->page = alloc_page(flags);
 309         if (!p->page)
 310                 return -ENOMEM;
 311
 312         p->daddr = dma_map_page(device,
 313                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 314
 315         if (dma_mapping_error(device, p->daddr)) {
 316                 __free_page(p->page);
 317                 return -EINVAL;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 324 {
 325         return __setup_page_dma(dev, p, GFP_KERNEL);
 326 }
 327
 328 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 329 {
 330         if (WARN_ON(!p->page))
 331                 return;
 332
 333         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 334         __free_page(p->page);
 335         memset(p, 0, sizeof(*p));
 336 }
 337
 338 static void *kmap_page_dma(struct i915_page_dma *p)
 339 {
 340         return kmap_atomic(p->page);
 341 }
 342
 343 /* We use the flushing unmap only with ppgtt structures:
 344  * page directories, page tables and scratch pages.
 345  */
 346 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 347 {
 348         /* There are only few exceptions for gen >=6. chv and bxt.
 349          * And we are not sure about the latter so play safe for now.
 350          */
 351         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 352                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 353
 354         kunmap_atomic(vaddr);
 355 }
 356
 357 #define kmap_px(px) kmap_page_dma(px_base(px))
 358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 359
 360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 364
 365 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 366                           const uint64_t val)
 367 {
 368         int i;
 369         uint64_t * const vaddr = kmap_page_dma(p);
 370
 371         for (i = 0; i < 512; i++)
 372                 vaddr[i] = val;
 373
 374         kunmap_page_dma(dev, vaddr);
 375 }
 376
 377 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 378                              const uint32_t val32)
 379 {
 380         uint64_t v = val32;
 381
 382         v = v << 32 | val32;
 383
 384         fill_page_dma(dev, p, v);
 385 }
 386
 387 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 388 {
 389         struct i915_page_scratch *sp;
 390         int ret;
 391
 392         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 393         if (sp == NULL)
 394                 return ERR_PTR(-ENOMEM);
 395
 396         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 397         if (ret) {
 398                 kfree(sp);
 399                 return ERR_PTR(ret);
 400         }
 401
 402         set_pages_uc(px_page(sp), 1);
 403
 404         return sp;
 405 }
 406
 407 static void free_scratch_page(struct drm_device *dev,
 408                               struct i915_page_scratch *sp)
 409 {
 410         set_pages_wb(px_page(sp), 1);
 411
 412         cleanup_px(dev, sp);
 413         kfree(sp);
 414 }
 415
 416 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 417 {
 418         struct i915_page_table *pt;
 419         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 420                 GEN8_PTES : GEN6_PTES;
 421         int ret = -ENOMEM;
 422
 423         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 424         if (!pt)
 425                 return ERR_PTR(-ENOMEM);
 426
 427         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 428                                 GFP_KERNEL);
 429
 430         if (!pt->used_ptes)
 431                 goto fail_bitmap;
 432
 433         ret = setup_px(dev, pt);
 434         if (ret)
 435                 goto fail_page_m;
 436
 437         return pt;
 438
 439 fail_page_m:
 440         kfree(pt->used_ptes);
 441 fail_bitmap:
 442         kfree(pt);
 443
 444         return ERR_PTR(ret);
 445 }
 446
 447 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 448 {
 449         cleanup_px(dev, pt);
 450         kfree(pt->used_ptes);
 451         kfree(pt);
 452 }
 453
 454 static void gen8_initialize_pt(struct i915_address_space *vm,
 455                                struct i915_page_table *pt)
 456 {
 457         gen8_pte_t scratch_pte;
 458
 459         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 460                                       I915_CACHE_LLC, true);
 461
 462         fill_px(vm->dev, pt, scratch_pte);
 463 }
 464
 465 static void gen6_initialize_pt(struct i915_address_space *vm,
 466                                struct i915_page_table *pt)
 467 {
 468         gen6_pte_t scratch_pte;
 469
 470         WARN_ON(px_dma(vm->scratch_page) == 0);
 471
 472         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 473                                      I915_CACHE_LLC, true, 0);
 474
 475         fill32_px(vm->dev, pt, scratch_pte);
 476 }
 477
 478 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 479 {
 480         struct i915_page_directory *pd;
 481         int ret = -ENOMEM;
 482
 483         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 484         if (!pd)
 485                 return ERR_PTR(-ENOMEM);
 486
 487         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 488                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 489         if (!pd->used_pdes)
 490                 goto fail_bitmap;
 491
 492         ret = setup_px(dev, pd);
 493         if (ret)
 494                 goto fail_page_m;
 495
 496         return pd;
 497
 498 fail_page_m:
 499         kfree(pd->used_pdes);
 500 fail_bitmap:
 501         kfree(pd);
 502
 503         return ERR_PTR(ret);
 504 }
 505
 506 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 507 {
 508         if (px_page(pd)) {
 509                 cleanup_px(dev, pd);
 510                 kfree(pd->used_pdes);
 511                 kfree(pd);
 512         }
 513 }
 514
 515 static void gen8_initialize_pd(struct i915_address_space *vm,
 516                                struct i915_page_directory *pd)
 517 {
 518         gen8_pde_t scratch_pde;
 519
 520         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 521
 522         fill_px(vm->dev, pd, scratch_pde);
 523 }
 524
 525 /* Broadwell Page Directory Pointer Descriptors */
 526 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 527                           unsigned entry,
 528                           dma_addr_t addr)
 529 {
 530         struct intel_engine_cs *ring = req->ring;
 531         int ret;
 532
 533         BUG_ON(entry >= 4);
 534
 535         ret = intel_ring_begin(req, 6);
 536         if (ret)
 537                 return ret;
 538
 539         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 540         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 541         intel_ring_emit(ring, upper_32_bits(addr));
 542         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 543         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 544         intel_ring_emit(ring, lower_32_bits(addr));
 545         intel_ring_advance(ring);
 546
 547         return 0;
 548 }
 549
 550 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 551                           struct drm_i915_gem_request *req)
 552 {
 553         int i, ret;
 554
 555         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 556                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 557
 558                 ret = gen8_write_pdp(req, i, pd_daddr);
 559                 if (ret)
 560                         return ret;
 561         }
 562
 563         return 0;
 564 }
 565
 566 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 567                                    uint64_t start,
 568                                    uint64_t length,
 569                                    bool use_scratch)
 570 {
 571         struct i915_hw_ppgtt *ppgtt =
 572                 container_of(vm, struct i915_hw_ppgtt, base);
 573         gen8_pte_t *pt_vaddr, scratch_pte;
 574         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 575         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 576         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 577         unsigned num_entries = length >> PAGE_SHIFT;
 578         unsigned last_pte, i;
 579
 580         scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page),
 581                                       I915_CACHE_LLC, use_scratch);
 582
 583         while (num_entries) {
 584                 struct i915_page_directory *pd;
 585                 struct i915_page_table *pt;
 586
 587                 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
 588                         continue;
 589
 590                 pd = ppgtt->pdp.page_directory[pdpe];
 591
 592                 if (WARN_ON(!pd->page_table[pde]))
 593                         continue;
 594
 595                 pt = pd->page_table[pde];
 596
 597                 if (WARN_ON(!px_page(pt)))
 598                         continue;
 599
 600                 last_pte = pte + num_entries;
 601                 if (last_pte > GEN8_PTES)
 602                         last_pte = GEN8_PTES;
 603
 604                 pt_vaddr = kmap_px(pt);
 605
 606                 for (i = pte; i < last_pte; i++) {
 607                         pt_vaddr[i] = scratch_pte;
 608                         num_entries--;
 609                 }
 610
 611                 kunmap_px(ppgtt, pt);
 612
 613                 pte = 0;
 614                 if (++pde == I915_PDES) {
 615                         pdpe++;
 616                         pde = 0;
 617                 }
 618         }
 619 }
 620
 621 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 622                                       struct sg_table *pages,
 623                                       uint64_t start,
 624                                       enum i915_cache_level cache_level, u32 unused)
 625 {
 626         struct i915_hw_ppgtt *ppgtt =
 627                 container_of(vm, struct i915_hw_ppgtt, base);
 628         gen8_pte_t *pt_vaddr;
 629         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 630         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 631         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 632         struct sg_page_iter sg_iter;
 633
 634         pt_vaddr = NULL;
 635
 636         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 637                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
 638                         break;
 639
 640                 if (pt_vaddr == NULL) {
 641                         struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
 642                         struct i915_page_table *pt = pd->page_table[pde];
 643                         pt_vaddr = kmap_px(pt);
 644                 }
 645
 646                 pt_vaddr[pte] =
 647                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 648                                         cache_level, true);
 649                 if (++pte == GEN8_PTES) {
 650                         kunmap_px(ppgtt, pt_vaddr);
 651                         pt_vaddr = NULL;
 652                         if (++pde == I915_PDES) {
 653                                 pdpe++;
 654                                 pde = 0;
 655                         }
 656                         pte = 0;
 657                 }
 658         }
 659
 660         if (pt_vaddr)
 661                 kunmap_px(ppgtt, pt_vaddr);
 662 }
 663
 664 static void gen8_free_page_tables(struct drm_device *dev,
 665                                   struct i915_page_directory *pd)
 666 {
 667         int i;
 668
 669         if (!px_page(pd))
 670                 return;
 671
 672         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 673                 if (WARN_ON(!pd->page_table[i]))
 674                         continue;
 675
 676                 free_pt(dev, pd->page_table[i]);
 677                 pd->page_table[i] = NULL;
 678         }
 679 }
 680
 681 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 682 {
 683         struct i915_hw_ppgtt *ppgtt =
 684                 container_of(vm, struct i915_hw_ppgtt, base);
 685         int i;
 686
 687         for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
 688                 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
 689                         continue;
 690
 691                 gen8_free_page_tables(ppgtt->base.dev,
 692                                       ppgtt->pdp.page_directory[i]);
 693                 free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]);
 694         }
 695
 696         free_pd(vm->dev, vm->scratch_pd);
 697         free_pt(vm->dev, vm->scratch_pt);
 698 }
 699
 700 /**
 701  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 702  * @ppgtt:      Master ppgtt structure.
 703  * @pd:         Page directory for this address range.
 704  * @start:      Starting virtual address to begin allocations.
 705  * @length      Size of the allocations.
 706  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 707  *              caller to free on error.
 708  *
 709  * Allocate the required number of page tables. Extremely similar to
 710  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
 711  * the page directory boundary (instead of the page directory pointer). That
 712  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
 713  * possible, and likely that the caller will need to use multiple calls of this
 714  * function to achieve the appropriate allocation.
 715  *
 716  * Return: 0 if success; negative error code otherwise.
 717  */
 718 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
 719                                      struct i915_page_directory *pd,
 720                                      uint64_t start,
 721                                      uint64_t length,
 722                                      unsigned long *new_pts)
 723 {
 724         struct drm_device *dev = ppgtt->base.dev;
 725         struct i915_page_table *pt;
 726         uint64_t temp;
 727         uint32_t pde;
 728
 729         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 730                 /* Don't reallocate page tables */
 731                 if (pt) {
 732                         /* Scratch is never allocated this way */
 733                         WARN_ON(pt == ppgtt->base.scratch_pt);
 734                         continue;
 735                 }
 736
 737                 pt = alloc_pt(dev);
 738                 if (IS_ERR(pt))
 739                         goto unwind_out;
 740
 741                 gen8_initialize_pt(&ppgtt->base, pt);
 742                 pd->page_table[pde] = pt;
 743                 __set_bit(pde, new_pts);
 744         }
 745
 746         return 0;
 747
 748 unwind_out:
 749         for_each_set_bit(pde, new_pts, I915_PDES)
 750                 free_pt(dev, pd->page_table[pde]);
 751
 752         return -ENOMEM;
 753 }
 754
 755 /**
 756  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
 757  * @ppgtt:      Master ppgtt structure.
 758  * @pdp:        Page directory pointer for this address range.
 759  * @start:      Starting virtual address to begin allocations.
 760  * @length      Size of the allocations.
 761  * @new_pds     Bitmap set by function with new allocations. Likely used by the
 762  *              caller to free on error.
 763  *
 764  * Allocate the required number of page directories starting at the pde index of
 765  * @start, and ending at the pde index @start + @length. This function will skip
 766  * over already allocated page directories within the range, and only allocate
 767  * new ones, setting the appropriate pointer within the pdp as well as the
 768  * correct position in the bitmap @new_pds.
 769  *
 770  * The function will only allocate the pages within the range for a give page
 771  * directory pointer. In other words, if @start + @length straddles a virtually
 772  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
 773  * required by the caller, This is not currently possible, and the BUG in the
 774  * code will prevent it.
 775  *
 776  * Return: 0 if success; negative error code otherwise.
 777  */
 778 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
 779                                      struct i915_page_directory_pointer *pdp,
 780                                      uint64_t start,
 781                                      uint64_t length,
 782                                      unsigned long *new_pds)
 783 {
 784         struct drm_device *dev = ppgtt->base.dev;
 785         struct i915_page_directory *pd;
 786         uint64_t temp;
 787         uint32_t pdpe;
 788
 789         WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
 790
 791         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 792                 if (pd)
 793                         continue;
 794
 795                 pd = alloc_pd(dev);
 796                 if (IS_ERR(pd))
 797                         goto unwind_out;
 798
 799                 gen8_initialize_pd(&ppgtt->base, pd);
 800                 pdp->page_directory[pdpe] = pd;
 801                 __set_bit(pdpe, new_pds);
 802         }
 803
 804         return 0;
 805
 806 unwind_out:
 807         for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
 808                 free_pd(dev, pdp->page_directory[pdpe]);
 809
 810         return -ENOMEM;
 811 }
 812
 813 static void
 814 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 815 {
 816         int i;
 817
 818         for (i = 0; i < GEN8_LEGACY_PDPES; i++)
 819                 kfree(new_pts[i]);
 820         kfree(new_pts);
 821         kfree(new_pds);
 822 }
 823
 824 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
 825  * of these are based on the number of PDPEs in the system.
 826  */
 827 static
 828 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 829                                          unsigned long ***new_pts)
 830 {
 831         int i;
 832         unsigned long *pds;
 833         unsigned long **pts;
 834
 835         pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
 836         if (!pds)
 837                 return -ENOMEM;
 838
 839         pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
 840         if (!pts) {
 841                 kfree(pds);
 842                 return -ENOMEM;
 843         }
 844
 845         for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 846                 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
 847                                  sizeof(unsigned long), GFP_KERNEL);
 848                 if (!pts[i])
 849                         goto err_out;
 850         }
 851
 852         *new_pds = pds;
 853         *new_pts = pts;
 854
 855         return 0;
 856
 857 err_out:
 858         free_gen8_temp_bitmaps(pds, pts);
 859         return -ENOMEM;
 860 }
 861
 862 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
 863  * the page table structures, we mark them dirty so that
 864  * context switching/execlist queuing code takes extra steps
 865  * to ensure that tlbs are flushed.
 866  */
 867 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 868 {
 869         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
 870 }
 871
 872 static int gen8_alloc_va_range(struct i915_address_space *vm,
 873                                uint64_t start,
 874                                uint64_t length)
 875 {
 876         struct i915_hw_ppgtt *ppgtt =
 877                 container_of(vm, struct i915_hw_ppgtt, base);
 878         unsigned long *new_page_dirs, **new_page_tables;
 879         struct i915_page_directory *pd;
 880         const uint64_t orig_start = start;
 881         const uint64_t orig_length = length;
 882         uint64_t temp;
 883         uint32_t pdpe;
 884         int ret;
 885
 886         /* Wrap is never okay since we can only represent 48b, and we don't
 887          * actually use the other side of the canonical address space.
 888          */
 889         if (WARN_ON(start + length < start))
 890                 return -ENODEV;
 891
 892         if (WARN_ON(start + length > ppgtt->base.total))
 893                 return -ENODEV;
 894
 895         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
 896         if (ret)
 897                 return ret;
 898
 899         /* Do the allocations first so we can easily bail out */
 900         ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
 901                                         new_page_dirs);
 902         if (ret) {
 903                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 904                 return ret;
 905         }
 906
 907         /* For every page directory referenced, allocate page tables */
 908         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 909                 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
 910                                                 new_page_tables[pdpe]);
 911                 if (ret)
 912                         goto err_out;
 913         }
 914
 915         start = orig_start;
 916         length = orig_length;
 917
 918         /* Allocations have completed successfully, so set the bitmaps, and do
 919          * the mappings. */
 920         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 921                 gen8_pde_t *const page_directory = kmap_px(pd);
 922                 struct i915_page_table *pt;
 923                 uint64_t pd_len = gen8_clamp_pd(start, length);
 924                 uint64_t pd_start = start;
 925                 uint32_t pde;
 926
 927                 /* Every pd should be allocated, we just did that above. */
 928                 WARN_ON(!pd);
 929
 930                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 931                         /* Same reasoning as pd */
 932                         WARN_ON(!pt);
 933                         WARN_ON(!pd_len);
 934                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
 935
 936                         /* Set our used ptes within the page table */
 937                         bitmap_set(pt->used_ptes,
 938                                    gen8_pte_index(pd_start),
 939                                    gen8_pte_count(pd_start, pd_len));
 940
 941                         /* Our pde is now pointing to the pagetable, pt */
 942                         __set_bit(pde, pd->used_pdes);
 943
 944                         /* Map the PDE to the page table */
 945                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
 946                                                               I915_CACHE_LLC);
 947
 948                         /* NB: We haven't yet mapped ptes to pages. At this
 949                          * point we're still relying on insert_entries() */
 950                 }
 951
 952                 kunmap_px(ppgtt, page_directory);
 953
 954                 __set_bit(pdpe, ppgtt->pdp.used_pdpes);
 955         }
 956
 957         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 958         mark_tlbs_dirty(ppgtt);
 959         return 0;
 960
 961 err_out:
 962         while (pdpe--) {
 963                 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
 964                         free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]);
 965         }
 966
 967         for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
 968                 free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]);
 969
 970         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 971         mark_tlbs_dirty(ppgtt);
 972         return ret;
 973 }
 974
 975 /*
 976  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 977  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 978  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 979  * space.
 980  *
 981  */
 982 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 983 {
 984         ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev);
 985         if (IS_ERR(ppgtt->base.scratch_pt))
 986                 return PTR_ERR(ppgtt->base.scratch_pt);
 987
 988         ppgtt->base.scratch_pd = alloc_pd(ppgtt->base.dev);
 989         if (IS_ERR(ppgtt->base.scratch_pd))
 990                 return PTR_ERR(ppgtt->base.scratch_pd);
 991
 992         gen8_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt);
 993         gen8_initialize_pd(&ppgtt->base, ppgtt->base.scratch_pd);
 994
 995         ppgtt->base.start = 0;
 996         ppgtt->base.total = 1ULL << 32;
 997         if (IS_ENABLED(CONFIG_X86_32))
 998                 /* While we have a proliferation of size_t variables
 999                  * we cannot represent the full ppgtt size on 32bit,
1000                  * so limit it to the same size as the GGTT (currently
1001                  * 2GiB).
1002                  */
1003                 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
1004         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1005         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1006         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1007         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1008         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1009         ppgtt->base.bind_vma = ppgtt_bind_vma;
1010
1011         ppgtt->switch_mm = gen8_mm_switch;
1012
1013         return 0;
1014 }
1015
1016 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1017 {
1018         struct i915_address_space *vm = &ppgtt->base;
1019         struct i915_page_table *unused;
1020         gen6_pte_t scratch_pte;
1021         uint32_t pd_entry;
1022         uint32_t  pte, pde, temp;
1023         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1024
1025         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1026                                      I915_CACHE_LLC, true, 0);
1027
1028         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1029                 u32 expected;
1030                 gen6_pte_t *pt_vaddr;
1031                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1032                 pd_entry = readl(ppgtt->pd_addr + pde);
1033                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1034
1035                 if (pd_entry != expected)
1036                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1037                                    pde,
1038                                    pd_entry,
1039                                    expected);
1040                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1041
1042                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1043
1044                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1045                         unsigned long va =
1046                                 (pde * PAGE_SIZE * GEN6_PTES) +
1047                                 (pte * PAGE_SIZE);
1048                         int i;
1049                         bool found = false;
1050                         for (i = 0; i < 4; i++)
1051                                 if (pt_vaddr[pte + i] != scratch_pte)
1052                                         found = true;
1053                         if (!found)
1054                                 continue;
1055
1056                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1057                         for (i = 0; i < 4; i++) {
1058                                 if (pt_vaddr[pte + i] != scratch_pte)
1059                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1060                                 else
1061                                         seq_puts(m, "  SCRATCH ");
1062                         }
1063                         seq_puts(m, "\n");
1064                 }
1065                 kunmap_px(ppgtt, pt_vaddr);
1066         }
1067 }
1068
1069 /* Write pde (index) from the page directory @pd to the page table @pt */
1070 static void gen6_write_pde(struct i915_page_directory *pd,
1071                             const int pde, struct i915_page_table *pt)
1072 {
1073         /* Caller needs to make sure the write completes if necessary */
1074         struct i915_hw_ppgtt *ppgtt =
1075                 container_of(pd, struct i915_hw_ppgtt, pd);
1076         u32 pd_entry;
1077
1078         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1079         pd_entry |= GEN6_PDE_VALID;
1080
1081         writel(pd_entry, ppgtt->pd_addr + pde);
1082 }
1083
1084 /* Write all the page tables found in the ppgtt structure to incrementing page
1085  * directories. */
1086 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1087                                   struct i915_page_directory *pd,
1088                                   uint32_t start, uint32_t length)
1089 {
1090         struct i915_page_table *pt;
1091         uint32_t pde, temp;
1092
1093         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1094                 gen6_write_pde(pd, pde, pt);
1095
1096         /* Make sure write is complete before other code can use this page
1097          * table. Also require for WC mapped PTEs */
1098         readl(dev_priv->gtt.gsm);
1099 }
1100
1101 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1102 {
1103         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1104
1105         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1106 }
1107
1108 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1109                          struct drm_i915_gem_request *req)
1110 {
1111         struct intel_engine_cs *ring = req->ring;
1112         int ret;
1113
1114         /* NB: TLBs must be flushed and invalidated before a switch */
1115         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1116         if (ret)
1117                 return ret;
1118
1119         ret = intel_ring_begin(req, 6);
1120         if (ret)
1121                 return ret;
1122
1123         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1124         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1125         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1126         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1127         intel_ring_emit(ring, get_pd_offset(ppgtt));
1128         intel_ring_emit(ring, MI_NOOP);
1129         intel_ring_advance(ring);
1130
1131         return 0;
1132 }
1133
1134 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1135                           struct drm_i915_gem_request *req)
1136 {
1137         struct intel_engine_cs *ring = req->ring;
1138         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1139
1140         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1141         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1142         return 0;
1143 }
1144
1145 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1146                           struct drm_i915_gem_request *req)
1147 {
1148         struct intel_engine_cs *ring = req->ring;
1149         int ret;
1150
1151         /* NB: TLBs must be flushed and invalidated before a switch */
1152         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1153         if (ret)
1154                 return ret;
1155
1156         ret = intel_ring_begin(req, 6);
1157         if (ret)
1158                 return ret;
1159
1160         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1161         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1162         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1163         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1164         intel_ring_emit(ring, get_pd_offset(ppgtt));
1165         intel_ring_emit(ring, MI_NOOP);
1166         intel_ring_advance(ring);
1167
1168         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1169         if (ring->id != RCS) {
1170                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1171                 if (ret)
1172                         return ret;
1173         }
1174
1175         return 0;
1176 }
1177
1178 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1179                           struct drm_i915_gem_request *req)
1180 {
1181         struct intel_engine_cs *ring = req->ring;
1182         struct drm_device *dev = ppgtt->base.dev;
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184
1185
1186         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1187         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1188
1189         POSTING_READ(RING_PP_DIR_DCLV(ring));
1190
1191         return 0;
1192 }
1193
1194 static void gen8_ppgtt_enable(struct drm_device *dev)
1195 {
1196         struct drm_i915_private *dev_priv = dev->dev_private;
1197         struct intel_engine_cs *ring;
1198         int j;
1199
1200         for_each_ring(ring, dev_priv, j) {
1201                 I915_WRITE(RING_MODE_GEN7(ring),
1202                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1203         }
1204 }
1205
1206 static void gen7_ppgtt_enable(struct drm_device *dev)
1207 {
1208         struct drm_i915_private *dev_priv = dev->dev_private;
1209         struct intel_engine_cs *ring;
1210         uint32_t ecochk, ecobits;
1211         int i;
1212
1213         ecobits = I915_READ(GAC_ECO_BITS);
1214         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1215
1216         ecochk = I915_READ(GAM_ECOCHK);
1217         if (IS_HASWELL(dev)) {
1218                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1219         } else {
1220                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1221                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1222         }
1223         I915_WRITE(GAM_ECOCHK, ecochk);
1224
1225         for_each_ring(ring, dev_priv, i) {
1226                 /* GFX_MODE is per-ring on gen7+ */
1227                 I915_WRITE(RING_MODE_GEN7(ring),
1228                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1229         }
1230 }
1231
1232 static void gen6_ppgtt_enable(struct drm_device *dev)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         uint32_t ecochk, gab_ctl, ecobits;
1236
1237         ecobits = I915_READ(GAC_ECO_BITS);
1238         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1239                    ECOBITS_PPGTT_CACHE64B);
1240
1241         gab_ctl = I915_READ(GAB_CTL);
1242         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1243
1244         ecochk = I915_READ(GAM_ECOCHK);
1245         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1246
1247         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1248 }
1249
1250 /* PPGTT support for Sandybdrige/Gen6 and later */
1251 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1252                                    uint64_t start,
1253                                    uint64_t length,
1254                                    bool use_scratch)
1255 {
1256         struct i915_hw_ppgtt *ppgtt =
1257                 container_of(vm, struct i915_hw_ppgtt, base);
1258         gen6_pte_t *pt_vaddr, scratch_pte;
1259         unsigned first_entry = start >> PAGE_SHIFT;
1260         unsigned num_entries = length >> PAGE_SHIFT;
1261         unsigned act_pt = first_entry / GEN6_PTES;
1262         unsigned first_pte = first_entry % GEN6_PTES;
1263         unsigned last_pte, i;
1264
1265         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1266                                      I915_CACHE_LLC, true, 0);
1267
1268         while (num_entries) {
1269                 last_pte = first_pte + num_entries;
1270                 if (last_pte > GEN6_PTES)
1271                         last_pte = GEN6_PTES;
1272
1273                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1274
1275                 for (i = first_pte; i < last_pte; i++)
1276                         pt_vaddr[i] = scratch_pte;
1277
1278                 kunmap_px(ppgtt, pt_vaddr);
1279
1280                 num_entries -= last_pte - first_pte;
1281                 first_pte = 0;
1282                 act_pt++;
1283         }
1284 }
1285
1286 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1287                                       struct sg_table *pages,
1288                                       uint64_t start,
1289                                       enum i915_cache_level cache_level, u32 flags)
1290 {
1291         struct i915_hw_ppgtt *ppgtt =
1292                 container_of(vm, struct i915_hw_ppgtt, base);
1293         gen6_pte_t *pt_vaddr;
1294         unsigned first_entry = start >> PAGE_SHIFT;
1295         unsigned act_pt = first_entry / GEN6_PTES;
1296         unsigned act_pte = first_entry % GEN6_PTES;
1297         struct sg_page_iter sg_iter;
1298
1299         pt_vaddr = NULL;
1300         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1301                 if (pt_vaddr == NULL)
1302                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1303
1304                 pt_vaddr[act_pte] =
1305                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1306                                        cache_level, true, flags);
1307
1308                 if (++act_pte == GEN6_PTES) {
1309                         kunmap_px(ppgtt, pt_vaddr);
1310                         pt_vaddr = NULL;
1311                         act_pt++;
1312                         act_pte = 0;
1313                 }
1314         }
1315         if (pt_vaddr)
1316                 kunmap_px(ppgtt, pt_vaddr);
1317 }
1318
1319 static int gen6_alloc_va_range(struct i915_address_space *vm,
1320                                uint64_t start_in, uint64_t length_in)
1321 {
1322         DECLARE_BITMAP(new_page_tables, I915_PDES);
1323         struct drm_device *dev = vm->dev;
1324         struct drm_i915_private *dev_priv = dev->dev_private;
1325         struct i915_hw_ppgtt *ppgtt =
1326                                 container_of(vm, struct i915_hw_ppgtt, base);
1327         struct i915_page_table *pt;
1328         uint32_t start, length, start_save, length_save;
1329         uint32_t pde, temp;
1330         int ret;
1331
1332         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1333                 return -ENODEV;
1334
1335         start = start_save = start_in;
1336         length = length_save = length_in;
1337
1338         bitmap_zero(new_page_tables, I915_PDES);
1339
1340         /* The allocation is done in two stages so that we can bail out with
1341          * minimal amount of pain. The first stage finds new page tables that
1342          * need allocation. The second stage marks use ptes within the page
1343          * tables.
1344          */
1345         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1346                 if (pt != vm->scratch_pt) {
1347                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1348                         continue;
1349                 }
1350
1351                 /* We've already allocated a page table */
1352                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1353
1354                 pt = alloc_pt(dev);
1355                 if (IS_ERR(pt)) {
1356                         ret = PTR_ERR(pt);
1357                         goto unwind_out;
1358                 }
1359
1360                 gen6_initialize_pt(vm, pt);
1361
1362                 ppgtt->pd.page_table[pde] = pt;
1363                 __set_bit(pde, new_page_tables);
1364                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1365         }
1366
1367         start = start_save;
1368         length = length_save;
1369
1370         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1371                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1372
1373                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1374                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1375                            gen6_pte_count(start, length));
1376
1377                 if (__test_and_clear_bit(pde, new_page_tables))
1378                         gen6_write_pde(&ppgtt->pd, pde, pt);
1379
1380                 trace_i915_page_table_entry_map(vm, pde, pt,
1381                                          gen6_pte_index(start),
1382                                          gen6_pte_count(start, length),
1383                                          GEN6_PTES);
1384                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1385                                 GEN6_PTES);
1386         }
1387
1388         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1389
1390         /* Make sure write is complete before other code can use this page
1391          * table. Also require for WC mapped PTEs */
1392         readl(dev_priv->gtt.gsm);
1393
1394         mark_tlbs_dirty(ppgtt);
1395         return 0;
1396
1397 unwind_out:
1398         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1399                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1400
1401                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1402                 free_pt(vm->dev, pt);
1403         }
1404
1405         mark_tlbs_dirty(ppgtt);
1406         return ret;
1407 }
1408
1409 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1410 {
1411         struct i915_hw_ppgtt *ppgtt =
1412                 container_of(vm, struct i915_hw_ppgtt, base);
1413         struct i915_page_table *pt;
1414         uint32_t pde;
1415
1416         drm_mm_remove_node(&ppgtt->node);
1417
1418         gen6_for_all_pdes(pt, ppgtt, pde) {
1419                 if (pt != vm->scratch_pt)
1420                         free_pt(ppgtt->base.dev, pt);
1421         }
1422
1423         free_pt(vm->dev, vm->scratch_pt);
1424 }
1425
1426 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1427 {
1428         struct drm_device *dev = ppgtt->base.dev;
1429         struct drm_i915_private *dev_priv = dev->dev_private;
1430         bool retried = false;
1431         int ret;
1432
1433         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1434          * allocator works in address space sizes, so it's multiplied by page
1435          * size. We allocate at the top of the GTT to avoid fragmentation.
1436          */
1437         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1438         ppgtt->base.scratch_pt = alloc_pt(ppgtt->base.dev);
1439         if (IS_ERR(ppgtt->base.scratch_pt))
1440                 return PTR_ERR(ppgtt->base.scratch_pt);
1441
1442         gen6_initialize_pt(&ppgtt->base, ppgtt->base.scratch_pt);
1443
1444 alloc:
1445         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1446                                                   &ppgtt->node, GEN6_PD_SIZE,
1447                                                   GEN6_PD_ALIGN, 0,
1448                                                   0, dev_priv->gtt.base.total,
1449                                                   DRM_MM_TOPDOWN);
1450         if (ret == -ENOSPC && !retried) {
1451                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1452                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1453                                                I915_CACHE_NONE,
1454                                                0, dev_priv->gtt.base.total,
1455                                                0);
1456                 if (ret)
1457                         goto err_out;
1458
1459                 retried = true;
1460                 goto alloc;
1461         }
1462
1463         if (ret)
1464                 goto err_out;
1465
1466
1467         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1468                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1469
1470         return 0;
1471
1472 err_out:
1473         free_pt(ppgtt->base.dev, ppgtt->base.scratch_pt);
1474         return ret;
1475 }
1476
1477 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1478 {
1479         return gen6_ppgtt_allocate_page_directories(ppgtt);
1480 }
1481
1482 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1483                                   uint64_t start, uint64_t length)
1484 {
1485         struct i915_page_table *unused;
1486         uint32_t pde, temp;
1487
1488         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1489                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
1490 }
1491
1492 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1493 {
1494         struct drm_device *dev = ppgtt->base.dev;
1495         struct drm_i915_private *dev_priv = dev->dev_private;
1496         int ret;
1497
1498         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1499         if (IS_GEN6(dev)) {
1500                 ppgtt->switch_mm = gen6_mm_switch;
1501         } else if (IS_HASWELL(dev)) {
1502                 ppgtt->switch_mm = hsw_mm_switch;
1503         } else if (IS_GEN7(dev)) {
1504                 ppgtt->switch_mm = gen7_mm_switch;
1505         } else
1506                 BUG();
1507
1508         if (intel_vgpu_active(dev))
1509                 ppgtt->switch_mm = vgpu_mm_switch;
1510
1511         ret = gen6_ppgtt_alloc(ppgtt);
1512         if (ret)
1513                 return ret;
1514
1515         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1516         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1517         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1518         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1519         ppgtt->base.bind_vma = ppgtt_bind_vma;
1520         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1521         ppgtt->base.start = 0;
1522         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1523         ppgtt->debug_dump = gen6_dump_ppgtt;
1524
1525         ppgtt->pd.base.ggtt_offset =
1526                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1527
1528         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1529                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1530
1531         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1532
1533         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1534
1535         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1536                          ppgtt->node.size >> 20,
1537                          ppgtt->node.start / PAGE_SIZE);
1538
1539         DRM_DEBUG("Adding PPGTT at offset %x\n",
1540                   ppgtt->pd.base.ggtt_offset << 10);
1541
1542         return 0;
1543 }
1544
1545 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1546 {
1547         struct drm_i915_private *dev_priv = dev->dev_private;
1548
1549         ppgtt->base.dev = dev;
1550         ppgtt->base.scratch_page = dev_priv->gtt.base.scratch_page;
1551
1552         if (INTEL_INFO(dev)->gen < 8)
1553                 return gen6_ppgtt_init(ppgtt);
1554         else
1555                 return gen8_ppgtt_init(ppgtt);
1556 }
1557
1558 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1559 {
1560         struct drm_i915_private *dev_priv = dev->dev_private;
1561         int ret = 0;
1562
1563         ret = __hw_ppgtt_init(dev, ppgtt);
1564         if (ret == 0) {
1565                 kref_init(&ppgtt->ref);
1566                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1567                             ppgtt->base.total);
1568                 i915_init_vm(dev_priv, &ppgtt->base);
1569         }
1570
1571         return ret;
1572 }
1573
1574 int i915_ppgtt_init_hw(struct drm_device *dev)
1575 {
1576         /* In the case of execlists, PPGTT is enabled by the context descriptor
1577          * and the PDPs are contained within the context itself.  We don't
1578          * need to do anything here. */
1579         if (i915.enable_execlists)
1580                 return 0;
1581
1582         if (!USES_PPGTT(dev))
1583                 return 0;
1584
1585         if (IS_GEN6(dev))
1586                 gen6_ppgtt_enable(dev);
1587         else if (IS_GEN7(dev))
1588                 gen7_ppgtt_enable(dev);
1589         else if (INTEL_INFO(dev)->gen >= 8)
1590                 gen8_ppgtt_enable(dev);
1591         else
1592                 MISSING_CASE(INTEL_INFO(dev)->gen);
1593
1594         return 0;
1595 }
1596
1597 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
1598 {
1599         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
1600         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1601
1602         if (i915.enable_execlists)
1603                 return 0;
1604
1605         if (!ppgtt)
1606                 return 0;
1607
1608         return ppgtt->switch_mm(ppgtt, req);
1609 }
1610
1611 struct i915_hw_ppgtt *
1612 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1613 {
1614         struct i915_hw_ppgtt *ppgtt;
1615         int ret;
1616
1617         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1618         if (!ppgtt)
1619                 return ERR_PTR(-ENOMEM);
1620
1621         ret = i915_ppgtt_init(dev, ppgtt);
1622         if (ret) {
1623                 kfree(ppgtt);
1624                 return ERR_PTR(ret);
1625         }
1626
1627         ppgtt->file_priv = fpriv;
1628
1629         trace_i915_ppgtt_create(&ppgtt->base);
1630
1631         return ppgtt;
1632 }
1633
1634 void  i915_ppgtt_release(struct kref *kref)
1635 {
1636         struct i915_hw_ppgtt *ppgtt =
1637                 container_of(kref, struct i915_hw_ppgtt, ref);
1638
1639         trace_i915_ppgtt_release(&ppgtt->base);
1640
1641         /* vmas should already be unbound */
1642         WARN_ON(!list_empty(&ppgtt->base.active_list));
1643         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1644
1645         list_del(&ppgtt->base.global_link);
1646         drm_mm_takedown(&ppgtt->base.mm);
1647
1648         ppgtt->base.cleanup(&ppgtt->base);
1649         kfree(ppgtt);
1650 }
1651
1652 extern int intel_iommu_gfx_mapped;
1653 /* Certain Gen5 chipsets require require idling the GPU before
1654  * unmapping anything from the GTT when VT-d is enabled.
1655  */
1656 static bool needs_idle_maps(struct drm_device *dev)
1657 {
1658 #ifdef CONFIG_INTEL_IOMMU
1659         /* Query intel_iommu to see if we need the workaround. Presumably that
1660          * was loaded first.
1661          */
1662         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1663                 return true;
1664 #endif
1665         return false;
1666 }
1667
1668 static bool do_idling(struct drm_i915_private *dev_priv)
1669 {
1670         bool ret = dev_priv->mm.interruptible;
1671
1672         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1673                 dev_priv->mm.interruptible = false;
1674                 if (i915_gpu_idle(dev_priv->dev)) {
1675                         DRM_ERROR("Couldn't idle GPU\n");
1676                         /* Wait a bit, in hopes it avoids the hang */
1677                         udelay(10);
1678                 }
1679         }
1680
1681         return ret;
1682 }
1683
1684 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1685 {
1686         if (unlikely(dev_priv->gtt.do_idle_maps))
1687                 dev_priv->mm.interruptible = interruptible;
1688 }
1689
1690 void i915_check_and_clear_faults(struct drm_device *dev)
1691 {
1692         struct drm_i915_private *dev_priv = dev->dev_private;
1693         struct intel_engine_cs *ring;
1694         int i;
1695
1696         if (INTEL_INFO(dev)->gen < 6)
1697                 return;
1698
1699         for_each_ring(ring, dev_priv, i) {
1700                 u32 fault_reg;
1701                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1702                 if (fault_reg & RING_FAULT_VALID) {
1703                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1704                                          "\tAddr: 0x%08lx\n"
1705                                          "\tAddress space: %s\n"
1706                                          "\tSource ID: %d\n"
1707                                          "\tType: %d\n",
1708                                          fault_reg & PAGE_MASK,
1709                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1710                                          RING_FAULT_SRCID(fault_reg),
1711                                          RING_FAULT_FAULT_TYPE(fault_reg));
1712                         I915_WRITE(RING_FAULT_REG(ring),
1713                                    fault_reg & ~RING_FAULT_VALID);
1714                 }
1715         }
1716         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1717 }
1718
1719 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1720 {
1721         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1722                 intel_gtt_chipset_flush();
1723         } else {
1724                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1725                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1726         }
1727 }
1728
1729 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1730 {
1731         struct drm_i915_private *dev_priv = dev->dev_private;
1732
1733         /* Don't bother messing with faults pre GEN6 as we have little
1734          * documentation supporting that it's a good idea.
1735          */
1736         if (INTEL_INFO(dev)->gen < 6)
1737                 return;
1738
1739         i915_check_and_clear_faults(dev);
1740
1741         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1742                                        dev_priv->gtt.base.start,
1743                                        dev_priv->gtt.base.total,
1744                                        true);
1745
1746         i915_ggtt_flush(dev_priv);
1747 }
1748
1749 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1750 {
1751         if (obj->has_dma_mapping)
1752                 return 0;
1753
1754         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1755                         obj->pages->sgl, obj->pages->nents,
1756                         PCI_DMA_BIDIRECTIONAL))
1757                 return -ENOSPC;
1758
1759         return 0;
1760 }
1761
1762 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1763 {
1764 #ifdef writeq
1765         writeq(pte, addr);
1766 #else
1767         iowrite32((u32)pte, addr);
1768         iowrite32(pte >> 32, addr + 4);
1769 #endif
1770 }
1771
1772 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1773                                      struct sg_table *st,
1774                                      uint64_t start,
1775                                      enum i915_cache_level level, u32 unused)
1776 {
1777         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1778         unsigned first_entry = start >> PAGE_SHIFT;
1779         gen8_pte_t __iomem *gtt_entries =
1780                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1781         int i = 0;
1782         struct sg_page_iter sg_iter;
1783         dma_addr_t addr = 0; /* shut up gcc */
1784
1785         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1786                 addr = sg_dma_address(sg_iter.sg) +
1787                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1788                 gen8_set_pte(&gtt_entries[i],
1789                              gen8_pte_encode(addr, level, true));
1790                 i++;
1791         }
1792
1793         /*
1794          * XXX: This serves as a posting read to make sure that the PTE has
1795          * actually been updated. There is some concern that even though
1796          * registers and PTEs are within the same BAR that they are potentially
1797          * of NUMA access patterns. Therefore, even with the way we assume
1798          * hardware should work, we must keep this posting read for paranoia.
1799          */
1800         if (i != 0)
1801                 WARN_ON(readq(&gtt_entries[i-1])
1802                         != gen8_pte_encode(addr, level, true));
1803
1804         /* This next bit makes the above posting read even more important. We
1805          * want to flush the TLBs only after we're certain all the PTE updates
1806          * have finished.
1807          */
1808         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1809         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1810 }
1811
1812 /*
1813  * Binds an object into the global gtt with the specified cache level. The object
1814  * will be accessible to the GPU via commands whose operands reference offsets
1815  * within the global GTT as well as accessible by the GPU through the GMADR
1816  * mapped BAR (dev_priv->mm.gtt->gtt).
1817  */
1818 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1819                                      struct sg_table *st,
1820                                      uint64_t start,
1821                                      enum i915_cache_level level, u32 flags)
1822 {
1823         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1824         unsigned first_entry = start >> PAGE_SHIFT;
1825         gen6_pte_t __iomem *gtt_entries =
1826                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1827         int i = 0;
1828         struct sg_page_iter sg_iter;
1829         dma_addr_t addr = 0;
1830
1831         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1832                 addr = sg_page_iter_dma_address(&sg_iter);
1833                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1834                 i++;
1835         }
1836
1837         /* XXX: This serves as a posting read to make sure that the PTE has
1838          * actually been updated. There is some concern that even though
1839          * registers and PTEs are within the same BAR that they are potentially
1840          * of NUMA access patterns. Therefore, even with the way we assume
1841          * hardware should work, we must keep this posting read for paranoia.
1842          */
1843         if (i != 0) {
1844                 unsigned long gtt = readl(&gtt_entries[i-1]);
1845                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1846         }
1847
1848         /* This next bit makes the above posting read even more important. We
1849          * want to flush the TLBs only after we're certain all the PTE updates
1850          * have finished.
1851          */
1852         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1853         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1854 }
1855
1856 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1857                                   uint64_t start,
1858                                   uint64_t length,
1859                                   bool use_scratch)
1860 {
1861         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1862         unsigned first_entry = start >> PAGE_SHIFT;
1863         unsigned num_entries = length >> PAGE_SHIFT;
1864         gen8_pte_t scratch_pte, __iomem *gtt_base =
1865                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1866         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1867         int i;
1868
1869         if (WARN(num_entries > max_entries,
1870                  "First entry = %d; Num entries = %d (max=%d)\n",
1871                  first_entry, num_entries, max_entries))
1872                 num_entries = max_entries;
1873
1874         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1875                                       I915_CACHE_LLC,
1876                                       use_scratch);
1877         for (i = 0; i < num_entries; i++)
1878                 gen8_set_pte(&gtt_base[i], scratch_pte);
1879         readl(gtt_base);
1880 }
1881
1882 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1883                                   uint64_t start,
1884                                   uint64_t length,
1885                                   bool use_scratch)
1886 {
1887         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1888         unsigned first_entry = start >> PAGE_SHIFT;
1889         unsigned num_entries = length >> PAGE_SHIFT;
1890         gen6_pte_t scratch_pte, __iomem *gtt_base =
1891                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1892         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1893         int i;
1894
1895         if (WARN(num_entries > max_entries,
1896                  "First entry = %d; Num entries = %d (max=%d)\n",
1897                  first_entry, num_entries, max_entries))
1898                 num_entries = max_entries;
1899
1900         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1901                                      I915_CACHE_LLC, use_scratch, 0);
1902
1903         for (i = 0; i < num_entries; i++)
1904                 iowrite32(scratch_pte, &gtt_base[i]);
1905         readl(gtt_base);
1906 }
1907
1908 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1909                                      struct sg_table *pages,
1910                                      uint64_t start,
1911                                      enum i915_cache_level cache_level, u32 unused)
1912 {
1913         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1914                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1915
1916         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1917
1918 }
1919
1920 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1921                                   uint64_t start,
1922                                   uint64_t length,
1923                                   bool unused)
1924 {
1925         unsigned first_entry = start >> PAGE_SHIFT;
1926         unsigned num_entries = length >> PAGE_SHIFT;
1927         intel_gtt_clear_range(first_entry, num_entries);
1928 }
1929
1930 static int ggtt_bind_vma(struct i915_vma *vma,
1931                          enum i915_cache_level cache_level,
1932                          u32 flags)
1933 {
1934         struct drm_device *dev = vma->vm->dev;
1935         struct drm_i915_private *dev_priv = dev->dev_private;
1936         struct drm_i915_gem_object *obj = vma->obj;
1937         struct sg_table *pages = obj->pages;
1938         u32 pte_flags = 0;
1939         int ret;
1940
1941         ret = i915_get_ggtt_vma_pages(vma);
1942         if (ret)
1943                 return ret;
1944         pages = vma->ggtt_view.pages;
1945
1946         /* Currently applicable only to VLV */
1947         if (obj->gt_ro)
1948                 pte_flags |= PTE_READ_ONLY;
1949
1950
1951         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1952                 vma->vm->insert_entries(vma->vm, pages,
1953                                         vma->node.start,
1954                                         cache_level, pte_flags);
1955         }
1956
1957         if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1958                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1959                 appgtt->base.insert_entries(&appgtt->base, pages,
1960                                             vma->node.start,
1961                                             cache_level, pte_flags);
1962         }
1963
1964         return 0;
1965 }
1966
1967 static void ggtt_unbind_vma(struct i915_vma *vma)
1968 {
1969         struct drm_device *dev = vma->vm->dev;
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971         struct drm_i915_gem_object *obj = vma->obj;
1972         const uint64_t size = min_t(uint64_t,
1973                                     obj->base.size,
1974                                     vma->node.size);
1975
1976         if (vma->bound & GLOBAL_BIND) {
1977                 vma->vm->clear_range(vma->vm,
1978                                      vma->node.start,
1979                                      size,
1980                                      true);
1981         }
1982
1983         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1984                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1985
1986                 appgtt->base.clear_range(&appgtt->base,
1987                                          vma->node.start,
1988                                          size,
1989                                          true);
1990         }
1991 }
1992
1993 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1994 {
1995         struct drm_device *dev = obj->base.dev;
1996         struct drm_i915_private *dev_priv = dev->dev_private;
1997         bool interruptible;
1998
1999         interruptible = do_idling(dev_priv);
2000
2001         if (!obj->has_dma_mapping)
2002                 dma_unmap_sg(&dev->pdev->dev,
2003                              obj->pages->sgl, obj->pages->nents,
2004                              PCI_DMA_BIDIRECTIONAL);
2005
2006         undo_idling(dev_priv, interruptible);
2007 }
2008
2009 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2010                                   unsigned long color,
2011                                   u64 *start,
2012                                   u64 *end)
2013 {
2014         if (node->color != color)
2015                 *start += 4096;
2016
2017         if (!list_empty(&node->node_list)) {
2018                 node = list_entry(node->node_list.next,
2019                                   struct drm_mm_node,
2020                                   node_list);
2021                 if (node->allocated && node->color != color)
2022                         *end -= 4096;
2023         }
2024 }
2025
2026 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2027                                      unsigned long start,
2028                                      unsigned long mappable_end,
2029                                      unsigned long end)
2030 {
2031         /* Let GEM Manage all of the aperture.
2032          *
2033          * However, leave one page at the end still bound to the scratch page.
2034          * There are a number of places where the hardware apparently prefetches
2035          * past the end of the object, and we've seen multiple hangs with the
2036          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2037          * aperture.  One page should be enough to keep any prefetching inside
2038          * of the aperture.
2039          */
2040         struct drm_i915_private *dev_priv = dev->dev_private;
2041         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2042         struct drm_mm_node *entry;
2043         struct drm_i915_gem_object *obj;
2044         unsigned long hole_start, hole_end;
2045         int ret;
2046
2047         BUG_ON(mappable_end > end);
2048
2049         /* Subtract the guard page ... */
2050         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2051
2052         dev_priv->gtt.base.start = start;
2053         dev_priv->gtt.base.total = end - start;
2054
2055         if (intel_vgpu_active(dev)) {
2056                 ret = intel_vgt_balloon(dev);
2057                 if (ret)
2058                         return ret;
2059         }
2060
2061         if (!HAS_LLC(dev))
2062                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2063
2064         /* Mark any preallocated objects as occupied */
2065         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2066                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2067
2068                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2069                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2070
2071                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2072                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2073                 if (ret) {
2074                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2075                         return ret;
2076                 }
2077                 vma->bound |= GLOBAL_BIND;
2078         }
2079
2080         /* Clear any non-preallocated blocks */
2081         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2082                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2083                               hole_start, hole_end);
2084                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2085                                      hole_end - hole_start, true);
2086         }
2087
2088         /* And finally clear the reserved guard page */
2089         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2090
2091         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2092                 struct i915_hw_ppgtt *ppgtt;
2093
2094                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2095                 if (!ppgtt)
2096                         return -ENOMEM;
2097
2098                 ret = __hw_ppgtt_init(dev, ppgtt);
2099                 if (ret) {
2100                         ppgtt->base.cleanup(&ppgtt->base);
2101                         kfree(ppgtt);
2102                         return ret;
2103                 }
2104
2105                 if (ppgtt->base.allocate_va_range)
2106                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2107                                                             ppgtt->base.total);
2108                 if (ret) {
2109                         ppgtt->base.cleanup(&ppgtt->base);
2110                         kfree(ppgtt);
2111                         return ret;
2112                 }
2113
2114                 ppgtt->base.clear_range(&ppgtt->base,
2115                                         ppgtt->base.start,
2116                                         ppgtt->base.total,
2117                                         true);
2118
2119                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2120         }
2121
2122         return 0;
2123 }
2124
2125 void i915_gem_init_global_gtt(struct drm_device *dev)
2126 {
2127         struct drm_i915_private *dev_priv = dev->dev_private;
2128         u64 gtt_size, mappable_size;
2129
2130         gtt_size = dev_priv->gtt.base.total;
2131         mappable_size = dev_priv->gtt.mappable_end;
2132
2133         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2134 }
2135
2136 void i915_global_gtt_cleanup(struct drm_device *dev)
2137 {
2138         struct drm_i915_private *dev_priv = dev->dev_private;
2139         struct i915_address_space *vm = &dev_priv->gtt.base;
2140
2141         if (dev_priv->mm.aliasing_ppgtt) {
2142                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2143
2144                 ppgtt->base.cleanup(&ppgtt->base);
2145         }
2146
2147         if (drm_mm_initialized(&vm->mm)) {
2148                 if (intel_vgpu_active(dev))
2149                         intel_vgt_deballoon();
2150
2151                 drm_mm_takedown(&vm->mm);
2152                 list_del(&vm->global_link);
2153         }
2154
2155         vm->cleanup(vm);
2156 }
2157
2158 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2159 {
2160         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2161         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2162         return snb_gmch_ctl << 20;
2163 }
2164
2165 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2166 {
2167         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2168         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2169         if (bdw_gmch_ctl)
2170                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2171
2172 #ifdef CONFIG_X86_32
2173         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2174         if (bdw_gmch_ctl > 4)
2175                 bdw_gmch_ctl = 4;
2176 #endif
2177
2178         return bdw_gmch_ctl << 20;
2179 }
2180
2181 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2182 {
2183         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2184         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2185
2186         if (gmch_ctrl)
2187                 return 1 << (20 + gmch_ctrl);
2188
2189         return 0;
2190 }
2191
2192 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2193 {
2194         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2195         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2196         return snb_gmch_ctl << 25; /* 32 MB units */
2197 }
2198
2199 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2200 {
2201         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2202         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2203         return bdw_gmch_ctl << 25; /* 32 MB units */
2204 }
2205
2206 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2207 {
2208         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2209         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2210
2211         /*
2212          * 0x0  to 0x10: 32MB increments starting at 0MB
2213          * 0x11 to 0x16: 4MB increments starting at 8MB
2214          * 0x17 to 0x1d: 4MB increments start at 36MB
2215          */
2216         if (gmch_ctrl < 0x11)
2217                 return gmch_ctrl << 25;
2218         else if (gmch_ctrl < 0x17)
2219                 return (gmch_ctrl - 0x11 + 2) << 22;
2220         else
2221                 return (gmch_ctrl - 0x17 + 9) << 22;
2222 }
2223
2224 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2225 {
2226         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2227         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2228
2229         if (gen9_gmch_ctl < 0xf0)
2230                 return gen9_gmch_ctl << 25; /* 32 MB units */
2231         else
2232                 /* 4MB increments starting at 0xf0 for 4MB */
2233                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2234 }
2235
2236 static int ggtt_probe_common(struct drm_device *dev,
2237                              size_t gtt_size)
2238 {
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct i915_page_scratch *scratch_page;
2241         phys_addr_t gtt_phys_addr;
2242
2243         /* For Modern GENs the PTEs and register space are split in the BAR */
2244         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2245                 (pci_resource_len(dev->pdev, 0) / 2);
2246
2247         /*
2248          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2249          * dropped. For WC mappings in general we have 64 byte burst writes
2250          * when the WC buffer is flushed, so we can't use it, but have to
2251          * resort to an uncached mapping. The WC issue is easily caught by the
2252          * readback check when writing GTT PTE entries.
2253          */
2254         if (IS_BROXTON(dev))
2255                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2256         else
2257                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2258         if (!dev_priv->gtt.gsm) {
2259                 DRM_ERROR("Failed to map the gtt page table\n");
2260                 return -ENOMEM;
2261         }
2262
2263         scratch_page = alloc_scratch_page(dev);
2264         if (IS_ERR(scratch_page)) {
2265                 DRM_ERROR("Scratch setup failed\n");
2266                 /* iounmap will also get called at remove, but meh */
2267                 iounmap(dev_priv->gtt.gsm);
2268                 return PTR_ERR(scratch_page);
2269         }
2270
2271         dev_priv->gtt.base.scratch_page = scratch_page;
2272
2273         return 0;
2274 }
2275
2276 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2277  * bits. When using advanced contexts each context stores its own PAT, but
2278  * writing this data shouldn't be harmful even in those cases. */
2279 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2280 {
2281         uint64_t pat;
2282
2283         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2284               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2285               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2286               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2287               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2288               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2289               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2290               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2291
2292         if (!USES_PPGTT(dev_priv->dev))
2293                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2294                  * so RTL will always use the value corresponding to
2295                  * pat_sel = 000".
2296                  * So let's disable cache for GGTT to avoid screen corruptions.
2297                  * MOCS still can be used though.
2298                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2299                  * before this patch, i.e. the same uncached + snooping access
2300                  * like on gen6/7 seems to be in effect.
2301                  * - So this just fixes blitter/render access. Again it looks
2302                  * like it's not just uncached access, but uncached + snooping.
2303                  * So we can still hold onto all our assumptions wrt cpu
2304                  * clflushing on LLC machines.
2305                  */
2306                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2307
2308         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2309          * write would work. */
2310         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2311         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2312 }
2313
2314 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2315 {
2316         uint64_t pat;
2317
2318         /*
2319          * Map WB on BDW to snooped on CHV.
2320          *
2321          * Only the snoop bit has meaning for CHV, the rest is
2322          * ignored.
2323          *
2324          * The hardware will never snoop for certain types of accesses:
2325          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2326          * - PPGTT page tables
2327          * - some other special cycles
2328          *
2329          * As with BDW, we also need to consider the following for GT accesses:
2330          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2331          * so RTL will always use the value corresponding to
2332          * pat_sel = 000".
2333          * Which means we must set the snoop bit in PAT entry 0
2334          * in order to keep the global status page working.
2335          */
2336         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2337               GEN8_PPAT(1, 0) |
2338               GEN8_PPAT(2, 0) |
2339               GEN8_PPAT(3, 0) |
2340               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2341               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2342               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2343               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2344
2345         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2346         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2347 }
2348
2349 static int gen8_gmch_probe(struct drm_device *dev,
2350                            u64 *gtt_total,
2351                            size_t *stolen,
2352                            phys_addr_t *mappable_base,
2353                            u64 *mappable_end)
2354 {
2355         struct drm_i915_private *dev_priv = dev->dev_private;
2356         u64 gtt_size;
2357         u16 snb_gmch_ctl;
2358         int ret;
2359
2360         /* TODO: We're not aware of mappable constraints on gen8 yet */
2361         *mappable_base = pci_resource_start(dev->pdev, 2);
2362         *mappable_end = pci_resource_len(dev->pdev, 2);
2363
2364         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2365                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2366
2367         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2368
2369         if (INTEL_INFO(dev)->gen >= 9) {
2370                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2371                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2372         } else if (IS_CHERRYVIEW(dev)) {
2373                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2374                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2375         } else {
2376                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2377                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2378         }
2379
2380         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2381
2382         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2383                 chv_setup_private_ppat(dev_priv);
2384         else
2385                 bdw_setup_private_ppat(dev_priv);
2386
2387         ret = ggtt_probe_common(dev, gtt_size);
2388
2389         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2390         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2391         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2392         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2393
2394         return ret;
2395 }
2396
2397 static int gen6_gmch_probe(struct drm_device *dev,
2398                            u64 *gtt_total,
2399                            size_t *stolen,
2400                            phys_addr_t *mappable_base,
2401                            u64 *mappable_end)
2402 {
2403         struct drm_i915_private *dev_priv = dev->dev_private;
2404         unsigned int gtt_size;
2405         u16 snb_gmch_ctl;
2406         int ret;
2407
2408         *mappable_base = pci_resource_start(dev->pdev, 2);
2409         *mappable_end = pci_resource_len(dev->pdev, 2);
2410
2411         /* 64/512MB is the current min/max we actually know of, but this is just
2412          * a coarse sanity check.
2413          */
2414         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2415                 DRM_ERROR("Unknown GMADR size (%llx)\n",
2416                           dev_priv->gtt.mappable_end);
2417                 return -ENXIO;
2418         }
2419
2420         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2421                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2422         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2423
2424         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2425
2426         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2427         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2428
2429         ret = ggtt_probe_common(dev, gtt_size);
2430
2431         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2432         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2433         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2434         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2435
2436         return ret;
2437 }
2438
2439 static void gen6_gmch_remove(struct i915_address_space *vm)
2440 {
2441
2442         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2443
2444         iounmap(gtt->gsm);
2445         free_scratch_page(vm->dev, vm->scratch_page);
2446 }
2447
2448 static int i915_gmch_probe(struct drm_device *dev,
2449                            u64 *gtt_total,
2450                            size_t *stolen,
2451                            phys_addr_t *mappable_base,
2452                            u64 *mappable_end)
2453 {
2454         struct drm_i915_private *dev_priv = dev->dev_private;
2455         int ret;
2456
2457         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2458         if (!ret) {
2459                 DRM_ERROR("failed to set up gmch\n");
2460                 return -EIO;
2461         }
2462
2463         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2464
2465         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2466         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2467         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2468         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2469         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2470
2471         if (unlikely(dev_priv->gtt.do_idle_maps))
2472                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2473
2474         return 0;
2475 }
2476
2477 static void i915_gmch_remove(struct i915_address_space *vm)
2478 {
2479         intel_gmch_remove();
2480 }
2481
2482 int i915_gem_gtt_init(struct drm_device *dev)
2483 {
2484         struct drm_i915_private *dev_priv = dev->dev_private;
2485         struct i915_gtt *gtt = &dev_priv->gtt;
2486         int ret;
2487
2488         if (INTEL_INFO(dev)->gen <= 5) {
2489                 gtt->gtt_probe = i915_gmch_probe;
2490                 gtt->base.cleanup = i915_gmch_remove;
2491         } else if (INTEL_INFO(dev)->gen < 8) {
2492                 gtt->gtt_probe = gen6_gmch_probe;
2493                 gtt->base.cleanup = gen6_gmch_remove;
2494                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2495                         gtt->base.pte_encode = iris_pte_encode;
2496                 else if (IS_HASWELL(dev))
2497                         gtt->base.pte_encode = hsw_pte_encode;
2498                 else if (IS_VALLEYVIEW(dev))
2499                         gtt->base.pte_encode = byt_pte_encode;
2500                 else if (INTEL_INFO(dev)->gen >= 7)
2501                         gtt->base.pte_encode = ivb_pte_encode;
2502                 else
2503                         gtt->base.pte_encode = snb_pte_encode;
2504         } else {
2505                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2506                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2507         }
2508
2509         gtt->base.dev = dev;
2510
2511         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2512                              &gtt->mappable_base, &gtt->mappable_end);
2513         if (ret)
2514                 return ret;
2515
2516         /* GMADR is the PCI mmio aperture into the global GTT. */
2517         DRM_INFO("Memory usable by graphics device = %lluM\n",
2518                  gtt->base.total >> 20);
2519         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
2520         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2521 #ifdef CONFIG_INTEL_IOMMU
2522         if (intel_iommu_gfx_mapped)
2523                 DRM_INFO("VT-d active for gfx access\n");
2524 #endif
2525         /*
2526          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2527          * user's requested state against the hardware/driver capabilities.  We
2528          * do this now so that we can print out any log messages once rather
2529          * than every time we check intel_enable_ppgtt().
2530          */
2531         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2532         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2533
2534         return 0;
2535 }
2536
2537 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2538 {
2539         struct drm_i915_private *dev_priv = dev->dev_private;
2540         struct drm_i915_gem_object *obj;
2541         struct i915_address_space *vm;
2542
2543         i915_check_and_clear_faults(dev);
2544
2545         /* First fill our portion of the GTT with scratch pages */
2546         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2547                                        dev_priv->gtt.base.start,
2548                                        dev_priv->gtt.base.total,
2549                                        true);
2550
2551         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2552                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2553                                                            &dev_priv->gtt.base);
2554                 if (!vma)
2555                         continue;
2556
2557                 i915_gem_clflush_object(obj, obj->pin_display);
2558                 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2559         }
2560
2561
2562         if (INTEL_INFO(dev)->gen >= 8) {
2563                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2564                         chv_setup_private_ppat(dev_priv);
2565                 else
2566                         bdw_setup_private_ppat(dev_priv);
2567
2568                 return;
2569         }
2570
2571         if (USES_PPGTT(dev)) {
2572                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2573                         /* TODO: Perhaps it shouldn't be gen6 specific */
2574
2575                         struct i915_hw_ppgtt *ppgtt =
2576                                         container_of(vm, struct i915_hw_ppgtt,
2577                                                      base);
2578
2579                         if (i915_is_ggtt(vm))
2580                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
2581
2582                         gen6_write_page_range(dev_priv, &ppgtt->pd,
2583                                               0, ppgtt->base.total);
2584                 }
2585         }
2586
2587         i915_ggtt_flush(dev_priv);
2588 }
2589
2590 static struct i915_vma *
2591 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2592                       struct i915_address_space *vm,
2593                       const struct i915_ggtt_view *ggtt_view)
2594 {
2595         struct i915_vma *vma;
2596
2597         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2598                 return ERR_PTR(-EINVAL);
2599
2600         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2601         if (vma == NULL)
2602                 return ERR_PTR(-ENOMEM);
2603
2604         INIT_LIST_HEAD(&vma->vma_link);
2605         INIT_LIST_HEAD(&vma->mm_list);
2606         INIT_LIST_HEAD(&vma->exec_list);
2607         vma->vm = vm;
2608         vma->obj = obj;
2609
2610         if (i915_is_ggtt(vm))
2611                 vma->ggtt_view = *ggtt_view;
2612
2613         list_add_tail(&vma->vma_link, &obj->vma_list);
2614         if (!i915_is_ggtt(vm))
2615                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2616
2617         return vma;
2618 }
2619
2620 struct i915_vma *
2621 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2622                                   struct i915_address_space *vm)
2623 {
2624         struct i915_vma *vma;
2625
2626         vma = i915_gem_obj_to_vma(obj, vm);
2627         if (!vma)
2628                 vma = __i915_gem_vma_create(obj, vm,
2629                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2630
2631         return vma;
2632 }
2633
2634 struct i915_vma *
2635 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2636                                        const struct i915_ggtt_view *view)
2637 {
2638         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2639         struct i915_vma *vma;
2640
2641         if (WARN_ON(!view))
2642                 return ERR_PTR(-EINVAL);
2643
2644         vma = i915_gem_obj_to_ggtt_view(obj, view);
2645
2646         if (IS_ERR(vma))
2647                 return vma;
2648
2649         if (!vma)
2650                 vma = __i915_gem_vma_create(obj, ggtt, view);
2651
2652         return vma;
2653
2654 }
2655
2656 static void
2657 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2658              struct sg_table *st)
2659 {
2660         unsigned int column, row;
2661         unsigned int src_idx;
2662         struct scatterlist *sg = st->sgl;
2663
2664         st->nents = 0;
2665
2666         for (column = 0; column < width; column++) {
2667                 src_idx = width * (height - 1) + column;
2668                 for (row = 0; row < height; row++) {
2669                         st->nents++;
2670                         /* We don't need the pages, but need to initialize
2671                          * the entries so the sg list can be happily traversed.
2672                          * The only thing we need are DMA addresses.
2673                          */
2674                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
2675                         sg_dma_address(sg) = in[src_idx];
2676                         sg_dma_len(sg) = PAGE_SIZE;
2677                         sg = sg_next(sg);
2678                         src_idx -= width;
2679                 }
2680         }
2681 }
2682
2683 static struct sg_table *
2684 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2685                           struct drm_i915_gem_object *obj)
2686 {
2687         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2688         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
2689         struct sg_page_iter sg_iter;
2690         unsigned long i;
2691         dma_addr_t *page_addr_list;
2692         struct sg_table *st;
2693         int ret = -ENOMEM;
2694
2695         /* Allocate a temporary list of source pages for random access. */
2696         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2697                                        sizeof(dma_addr_t));
2698         if (!page_addr_list)
2699                 return ERR_PTR(ret);
2700
2701         /* Allocate target SG list. */
2702         st = kmalloc(sizeof(*st), GFP_KERNEL);
2703         if (!st)
2704                 goto err_st_alloc;
2705
2706         ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
2707         if (ret)
2708                 goto err_sg_alloc;
2709
2710         /* Populate source page list from the object. */
2711         i = 0;
2712         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2713                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2714                 i++;
2715         }
2716
2717         /* Rotate the pages. */
2718         rotate_pages(page_addr_list,
2719                      rot_info->width_pages, rot_info->height_pages,
2720                      st);
2721
2722         DRM_DEBUG_KMS(
2723                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2724                       obj->base.size, rot_info->pitch, rot_info->height,
2725                       rot_info->pixel_format, rot_info->width_pages,
2726                       rot_info->height_pages, size_pages);
2727
2728         drm_free_large(page_addr_list);
2729
2730         return st;
2731
2732 err_sg_alloc:
2733         kfree(st);
2734 err_st_alloc:
2735         drm_free_large(page_addr_list);
2736
2737         DRM_DEBUG_KMS(
2738                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2739                       obj->base.size, ret, rot_info->pitch, rot_info->height,
2740                       rot_info->pixel_format, rot_info->width_pages,
2741                       rot_info->height_pages, size_pages);
2742         return ERR_PTR(ret);
2743 }
2744
2745 static struct sg_table *
2746 intel_partial_pages(const struct i915_ggtt_view *view,
2747                     struct drm_i915_gem_object *obj)
2748 {
2749         struct sg_table *st;
2750         struct scatterlist *sg;
2751         struct sg_page_iter obj_sg_iter;
2752         int ret = -ENOMEM;
2753
2754         st = kmalloc(sizeof(*st), GFP_KERNEL);
2755         if (!st)
2756                 goto err_st_alloc;
2757
2758         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2759         if (ret)
2760                 goto err_sg_alloc;
2761
2762         sg = st->sgl;
2763         st->nents = 0;
2764         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2765                 view->params.partial.offset)
2766         {
2767                 if (st->nents >= view->params.partial.size)
2768                         break;
2769
2770                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2771                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2772                 sg_dma_len(sg) = PAGE_SIZE;
2773
2774                 sg = sg_next(sg);
2775                 st->nents++;
2776         }
2777
2778         return st;
2779
2780 err_sg_alloc:
2781         kfree(st);
2782 err_st_alloc:
2783         return ERR_PTR(ret);
2784 }
2785
2786 static int
2787 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2788 {
2789         int ret = 0;
2790
2791         if (vma->ggtt_view.pages)
2792                 return 0;
2793
2794         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2795                 vma->ggtt_view.pages = vma->obj->pages;
2796         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2797                 vma->ggtt_view.pages =
2798                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2799         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2800                 vma->ggtt_view.pages =
2801                         intel_partial_pages(&vma->ggtt_view, vma->obj);
2802         else
2803                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2804                           vma->ggtt_view.type);
2805
2806         if (!vma->ggtt_view.pages) {
2807                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2808                           vma->ggtt_view.type);
2809                 ret = -EINVAL;
2810         } else if (IS_ERR(vma->ggtt_view.pages)) {
2811                 ret = PTR_ERR(vma->ggtt_view.pages);
2812                 vma->ggtt_view.pages = NULL;
2813                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2814                           vma->ggtt_view.type, ret);
2815         }
2816
2817         return ret;
2818 }
2819
2820 /**
2821  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2822  * @vma: VMA to map
2823  * @cache_level: mapping cache level
2824  * @flags: flags like global or local mapping
2825  *
2826  * DMA addresses are taken from the scatter-gather table of this object (or of
2827  * this VMA in case of non-default GGTT views) and PTE entries set up.
2828  * Note that DMA addresses are also the only part of the SG table we care about.
2829  */
2830 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2831                   u32 flags)
2832 {
2833         int ret;
2834         u32 bind_flags;
2835
2836         if (WARN_ON(flags == 0))
2837                 return -EINVAL;
2838
2839         bind_flags = 0;
2840         if (flags & PIN_GLOBAL)
2841                 bind_flags |= GLOBAL_BIND;
2842         if (flags & PIN_USER)
2843                 bind_flags |= LOCAL_BIND;
2844
2845         if (flags & PIN_UPDATE)
2846                 bind_flags |= vma->bound;
2847         else
2848                 bind_flags &= ~vma->bound;
2849
2850         if (bind_flags == 0)
2851                 return 0;
2852
2853         if (vma->bound == 0 && vma->vm->allocate_va_range) {
2854                 trace_i915_va_alloc(vma->vm,
2855                                     vma->node.start,
2856                                     vma->node.size,
2857                                     VM_TO_TRACE_NAME(vma->vm));
2858
2859                 /* XXX: i915_vma_pin() will fix this +- hack */
2860                 vma->pin_count++;
2861                 ret = vma->vm->allocate_va_range(vma->vm,
2862                                                  vma->node.start,
2863                                                  vma->node.size);
2864                 vma->pin_count--;
2865                 if (ret)
2866                         return ret;
2867         }
2868
2869         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2870         if (ret)
2871                 return ret;
2872
2873         vma->bound |= bind_flags;
2874
2875         return 0;
2876 }
2877
2878 /**
2879  * i915_ggtt_view_size - Get the size of a GGTT view.
2880  * @obj: Object the view is of.
2881  * @view: The view in question.
2882  *
2883  * @return The size of the GGTT view in bytes.
2884  */
2885 size_t
2886 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2887                     const struct i915_ggtt_view *view)
2888 {
2889         if (view->type == I915_GGTT_VIEW_NORMAL) {
2890                 return obj->base.size;
2891         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
2892                 return view->rotation_info.size;
2893         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2894                 return view->params.partial.size << PAGE_SHIFT;
2895         } else {
2896                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2897                 return obj->base.size;
2898         }
2899 }