drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_vgpu.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  71  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  72  * parameter encapsulating all metadata required to implement a view.
  73  *
  74  * As a helper for callers which are only interested in the normal view,
  75  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  76  * GEM API functions, the ones not taking the view parameter, are operating on,
  77  * or with the normal GGTT view.
  78  *
  79  * Code wanting to add or use a new GGTT view needs to:
  80  *
  81  * 1. Add a new enum with a suitable name.
  82  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  83  * 3. Add support to i915_get_vma_pages().
  84  *
  85  * New views are required to build a scatter-gather table from within the
  86  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  87  * exists for the lifetime of an VMA.
  88  *
  89  * Core API is designed to have copy semantics which means that passed in
  90  * struct i915_ggtt_view does not need to be persistent (left around after
  91  * calling the core API functions).
  92  *
  93  */
  94
  95 static int
  96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  97
  98 const struct i915_ggtt_view i915_ggtt_view_normal;
  99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 100         .type = I915_GGTT_VIEW_ROTATED
 101 };
 102
 103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 104 {
 105         bool has_aliasing_ppgtt;
 106         bool has_full_ppgtt;
 107
 108         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 109         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 110
 111         if (intel_vgpu_active(dev))
 112                 has_full_ppgtt = false; /* emulation is too hard */
 113
 114         /*
 115          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 116          * execlists, the sole mechanism available to submit work.
 117          */
 118         if (INTEL_INFO(dev)->gen < 9 &&
 119             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 120                 return 0;
 121
 122         if (enable_ppgtt == 1)
 123                 return 1;
 124
 125         if (enable_ppgtt == 2 && has_full_ppgtt)
 126                 return 2;
 127
 128 #ifdef CONFIG_INTEL_IOMMU
 129         /* Disable ppgtt on SNB if VT-d is on. */
 130         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 131                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 132                 return 0;
 133         }
 134 #endif
 135
 136         /* Early VLV doesn't have this */
 137         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 138             dev->pdev->revision < 0xb) {
 139                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 140                 return 0;
 141         }
 142
 143         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 144                 return 2;
 145         else
 146                 return has_aliasing_ppgtt ? 1 : 0;
 147 }
 148
 149 static int ppgtt_bind_vma(struct i915_vma *vma,
 150                           enum i915_cache_level cache_level,
 151                           u32 unused)
 152 {
 153         u32 pte_flags = 0;
 154
 155         /* Currently applicable only to VLV */
 156         if (vma->obj->gt_ro)
 157                 pte_flags |= PTE_READ_ONLY;
 158
 159         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 160                                 cache_level, pte_flags);
 161
 162         return 0;
 163 }
 164
 165 static void ppgtt_unbind_vma(struct i915_vma *vma)
 166 {
 167         vma->vm->clear_range(vma->vm,
 168                              vma->node.start,
 169                              vma->obj->base.size,
 170                              true);
 171 }
 172
 173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 174                                   enum i915_cache_level level,
 175                                   bool valid)
 176 {
 177         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 178         pte |= addr;
 179
 180         switch (level) {
 181         case I915_CACHE_NONE:
 182                 pte |= PPAT_UNCACHED_INDEX;
 183                 break;
 184         case I915_CACHE_WT:
 185                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 186                 break;
 187         default:
 188                 pte |= PPAT_CACHED_INDEX;
 189                 break;
 190         }
 191
 192         return pte;
 193 }
 194
 195 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 196                                   const enum i915_cache_level level)
 197 {
 198         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 199         pde |= addr;
 200         if (level != I915_CACHE_NONE)
 201                 pde |= PPAT_CACHED_PDE_INDEX;
 202         else
 203                 pde |= PPAT_UNCACHED_INDEX;
 204         return pde;
 205 }
 206
 207 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 208                                  enum i915_cache_level level,
 209                                  bool valid, u32 unused)
 210 {
 211         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 212         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 213
 214         switch (level) {
 215         case I915_CACHE_L3_LLC:
 216         case I915_CACHE_LLC:
 217                 pte |= GEN6_PTE_CACHE_LLC;
 218                 break;
 219         case I915_CACHE_NONE:
 220                 pte |= GEN6_PTE_UNCACHED;
 221                 break;
 222         default:
 223                 MISSING_CASE(level);
 224         }
 225
 226         return pte;
 227 }
 228
 229 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 230                                  enum i915_cache_level level,
 231                                  bool valid, u32 unused)
 232 {
 233         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 234         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 235
 236         switch (level) {
 237         case I915_CACHE_L3_LLC:
 238                 pte |= GEN7_PTE_CACHE_L3_LLC;
 239                 break;
 240         case I915_CACHE_LLC:
 241                 pte |= GEN6_PTE_CACHE_LLC;
 242                 break;
 243         case I915_CACHE_NONE:
 244                 pte |= GEN6_PTE_UNCACHED;
 245                 break;
 246         default:
 247                 MISSING_CASE(level);
 248         }
 249
 250         return pte;
 251 }
 252
 253 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 254                                  enum i915_cache_level level,
 255                                  bool valid, u32 flags)
 256 {
 257         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 258         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 259
 260         if (!(flags & PTE_READ_ONLY))
 261                 pte |= BYT_PTE_WRITEABLE;
 262
 263         if (level != I915_CACHE_NONE)
 264                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 265
 266         return pte;
 267 }
 268
 269 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 270                                  enum i915_cache_level level,
 271                                  bool valid, u32 unused)
 272 {
 273         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 274         pte |= HSW_PTE_ADDR_ENCODE(addr);
 275
 276         if (level != I915_CACHE_NONE)
 277                 pte |= HSW_WB_LLC_AGE3;
 278
 279         return pte;
 280 }
 281
 282 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 283                                   enum i915_cache_level level,
 284                                   bool valid, u32 unused)
 285 {
 286         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 287         pte |= HSW_PTE_ADDR_ENCODE(addr);
 288
 289         switch (level) {
 290         case I915_CACHE_NONE:
 291                 break;
 292         case I915_CACHE_WT:
 293                 pte |= HSW_WT_ELLC_LLC_AGE3;
 294                 break;
 295         default:
 296                 pte |= HSW_WB_ELLC_LLC_AGE3;
 297                 break;
 298         }
 299
 300         return pte;
 301 }
 302
 303 static int __setup_page_dma(struct drm_device *dev,
 304                             struct i915_page_dma *p, gfp_t flags)
 305 {
 306         struct device *device = &dev->pdev->dev;
 307
 308         p->page = alloc_page(flags);
 309         if (!p->page)
 310                 return -ENOMEM;
 311
 312         p->daddr = dma_map_page(device,
 313                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 314
 315         if (dma_mapping_error(device, p->daddr)) {
 316                 __free_page(p->page);
 317                 return -EINVAL;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 324 {
 325         return __setup_page_dma(dev, p, GFP_KERNEL);
 326 }
 327
 328 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 329 {
 330         if (WARN_ON(!p->page))
 331                 return;
 332
 333         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 334         __free_page(p->page);
 335         memset(p, 0, sizeof(*p));
 336 }
 337
 338 static void *kmap_page_dma(struct i915_page_dma *p)
 339 {
 340         return kmap_atomic(p->page);
 341 }
 342
 343 /* We use the flushing unmap only with ppgtt structures:
 344  * page directories, page tables and scratch pages.
 345  */
 346 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 347 {
 348         /* There are only few exceptions for gen >=6. chv and bxt.
 349          * And we are not sure about the latter so play safe for now.
 350          */
 351         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 352                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 353
 354         kunmap_atomic(vaddr);
 355 }
 356
 357 #define kmap_px(px) kmap_page_dma(px_base(px))
 358 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 359
 360 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 361 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 362 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 363 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 364
 365 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 366                           const uint64_t val)
 367 {
 368         int i;
 369         uint64_t * const vaddr = kmap_page_dma(p);
 370
 371         for (i = 0; i < 512; i++)
 372                 vaddr[i] = val;
 373
 374         kunmap_page_dma(dev, vaddr);
 375 }
 376
 377 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 378                              const uint32_t val32)
 379 {
 380         uint64_t v = val32;
 381
 382         v = v << 32 | val32;
 383
 384         fill_page_dma(dev, p, v);
 385 }
 386
 387 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 388 {
 389         struct i915_page_scratch *sp;
 390         int ret;
 391
 392         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 393         if (sp == NULL)
 394                 return ERR_PTR(-ENOMEM);
 395
 396         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 397         if (ret) {
 398                 kfree(sp);
 399                 return ERR_PTR(ret);
 400         }
 401
 402         set_pages_uc(px_page(sp), 1);
 403
 404         return sp;
 405 }
 406
 407 static void free_scratch_page(struct drm_device *dev,
 408                               struct i915_page_scratch *sp)
 409 {
 410         set_pages_wb(px_page(sp), 1);
 411
 412         cleanup_px(dev, sp);
 413         kfree(sp);
 414 }
 415
 416 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 417 {
 418         struct i915_page_table *pt;
 419         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 420                 GEN8_PTES : GEN6_PTES;
 421         int ret = -ENOMEM;
 422
 423         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 424         if (!pt)
 425                 return ERR_PTR(-ENOMEM);
 426
 427         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 428                                 GFP_KERNEL);
 429
 430         if (!pt->used_ptes)
 431                 goto fail_bitmap;
 432
 433         ret = setup_px(dev, pt);
 434         if (ret)
 435                 goto fail_page_m;
 436
 437         return pt;
 438
 439 fail_page_m:
 440         kfree(pt->used_ptes);
 441 fail_bitmap:
 442         kfree(pt);
 443
 444         return ERR_PTR(ret);
 445 }
 446
 447 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 448 {
 449         cleanup_px(dev, pt);
 450         kfree(pt->used_ptes);
 451         kfree(pt);
 452 }
 453
 454 static void gen8_initialize_pt(struct i915_address_space *vm,
 455                                struct i915_page_table *pt)
 456 {
 457         gen8_pte_t scratch_pte;
 458
 459         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 460                                       I915_CACHE_LLC, true);
 461
 462         fill_px(vm->dev, pt, scratch_pte);
 463 }
 464
 465 static void gen6_initialize_pt(struct i915_address_space *vm,
 466                                struct i915_page_table *pt)
 467 {
 468         gen6_pte_t scratch_pte;
 469
 470         WARN_ON(px_dma(vm->scratch_page) == 0);
 471
 472         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 473                                      I915_CACHE_LLC, true, 0);
 474
 475         fill32_px(vm->dev, pt, scratch_pte);
 476 }
 477
 478 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 479 {
 480         struct i915_page_directory *pd;
 481         int ret = -ENOMEM;
 482
 483         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 484         if (!pd)
 485                 return ERR_PTR(-ENOMEM);
 486
 487         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 488                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 489         if (!pd->used_pdes)
 490                 goto fail_bitmap;
 491
 492         ret = setup_px(dev, pd);
 493         if (ret)
 494                 goto fail_page_m;
 495
 496         return pd;
 497
 498 fail_page_m:
 499         kfree(pd->used_pdes);
 500 fail_bitmap:
 501         kfree(pd);
 502
 503         return ERR_PTR(ret);
 504 }
 505
 506 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 507 {
 508         if (px_page(pd)) {
 509                 cleanup_px(dev, pd);
 510                 kfree(pd->used_pdes);
 511                 kfree(pd);
 512         }
 513 }
 514
 515 static void gen8_initialize_pd(struct i915_address_space *vm,
 516                                struct i915_page_directory *pd)
 517 {
 518         gen8_pde_t scratch_pde;
 519
 520         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 521
 522         fill_px(vm->dev, pd, scratch_pde);
 523 }
 524
 525 /* Broadwell Page Directory Pointer Descriptors */
 526 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 527                           unsigned entry,
 528                           dma_addr_t addr)
 529 {
 530         struct intel_engine_cs *ring = req->ring;
 531         int ret;
 532
 533         BUG_ON(entry >= 4);
 534
 535         ret = intel_ring_begin(req, 6);
 536         if (ret)
 537                 return ret;
 538
 539         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 540         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 541         intel_ring_emit(ring, upper_32_bits(addr));
 542         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 543         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 544         intel_ring_emit(ring, lower_32_bits(addr));
 545         intel_ring_advance(ring);
 546
 547         return 0;
 548 }
 549
 550 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 551                           struct drm_i915_gem_request *req)
 552 {
 553         int i, ret;
 554
 555         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 556                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 557
 558                 ret = gen8_write_pdp(req, i, pd_daddr);
 559                 if (ret)
 560                         return ret;
 561         }
 562
 563         return 0;
 564 }
 565
 566 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 567                                    uint64_t start,
 568                                    uint64_t length,
 569                                    bool use_scratch)
 570 {
 571         struct i915_hw_ppgtt *ppgtt =
 572                 container_of(vm, struct i915_hw_ppgtt, base);
 573         gen8_pte_t *pt_vaddr, scratch_pte;
 574         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 575         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 576         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 577         unsigned num_entries = length >> PAGE_SHIFT;
 578         unsigned last_pte, i;
 579
 580         scratch_pte = gen8_pte_encode(px_dma(ppgtt->base.scratch_page),
 581                                       I915_CACHE_LLC, use_scratch);
 582
 583         while (num_entries) {
 584                 struct i915_page_directory *pd;
 585                 struct i915_page_table *pt;
 586
 587                 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
 588                         break;
 589
 590                 pd = ppgtt->pdp.page_directory[pdpe];
 591
 592                 if (WARN_ON(!pd->page_table[pde]))
 593                         break;
 594
 595                 pt = pd->page_table[pde];
 596
 597                 if (WARN_ON(!px_page(pt)))
 598                         break;
 599
 600                 last_pte = pte + num_entries;
 601                 if (last_pte > GEN8_PTES)
 602                         last_pte = GEN8_PTES;
 603
 604                 pt_vaddr = kmap_px(pt);
 605
 606                 for (i = pte; i < last_pte; i++) {
 607                         pt_vaddr[i] = scratch_pte;
 608                         num_entries--;
 609                 }
 610
 611                 kunmap_px(ppgtt, pt);
 612
 613                 pte = 0;
 614                 if (++pde == I915_PDES) {
 615                         pdpe++;
 616                         pde = 0;
 617                 }
 618         }
 619 }
 620
 621 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 622                                       struct sg_table *pages,
 623                                       uint64_t start,
 624                                       enum i915_cache_level cache_level, u32 unused)
 625 {
 626         struct i915_hw_ppgtt *ppgtt =
 627                 container_of(vm, struct i915_hw_ppgtt, base);
 628         gen8_pte_t *pt_vaddr;
 629         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 630         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 631         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 632         struct sg_page_iter sg_iter;
 633
 634         pt_vaddr = NULL;
 635
 636         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 637                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
 638                         break;
 639
 640                 if (pt_vaddr == NULL) {
 641                         struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
 642                         struct i915_page_table *pt = pd->page_table[pde];
 643                         pt_vaddr = kmap_px(pt);
 644                 }
 645
 646                 pt_vaddr[pte] =
 647                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 648                                         cache_level, true);
 649                 if (++pte == GEN8_PTES) {
 650                         kunmap_px(ppgtt, pt_vaddr);
 651                         pt_vaddr = NULL;
 652                         if (++pde == I915_PDES) {
 653                                 pdpe++;
 654                                 pde = 0;
 655                         }
 656                         pte = 0;
 657                 }
 658         }
 659
 660         if (pt_vaddr)
 661                 kunmap_px(ppgtt, pt_vaddr);
 662 }
 663
 664 static void gen8_free_page_tables(struct drm_device *dev,
 665                                   struct i915_page_directory *pd)
 666 {
 667         int i;
 668
 669         if (!px_page(pd))
 670                 return;
 671
 672         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 673                 if (WARN_ON(!pd->page_table[i]))
 674                         continue;
 675
 676                 free_pt(dev, pd->page_table[i]);
 677                 pd->page_table[i] = NULL;
 678         }
 679 }
 680
 681 static int gen8_init_scratch(struct i915_address_space *vm)
 682 {
 683         struct drm_device *dev = vm->dev;
 684
 685         vm->scratch_page = alloc_scratch_page(dev);
 686         if (IS_ERR(vm->scratch_page))
 687                 return PTR_ERR(vm->scratch_page);
 688
 689         vm->scratch_pt = alloc_pt(dev);
 690         if (IS_ERR(vm->scratch_pt)) {
 691                 free_scratch_page(dev, vm->scratch_page);
 692                 return PTR_ERR(vm->scratch_pt);
 693         }
 694
 695         vm->scratch_pd = alloc_pd(dev);
 696         if (IS_ERR(vm->scratch_pd)) {
 697                 free_pt(dev, vm->scratch_pt);
 698                 free_scratch_page(dev, vm->scratch_page);
 699                 return PTR_ERR(vm->scratch_pd);
 700         }
 701
 702         gen8_initialize_pt(vm, vm->scratch_pt);
 703         gen8_initialize_pd(vm, vm->scratch_pd);
 704
 705         return 0;
 706 }
 707
 708 static void gen8_free_scratch(struct i915_address_space *vm)
 709 {
 710         struct drm_device *dev = vm->dev;
 711
 712         free_pd(dev, vm->scratch_pd);
 713         free_pt(dev, vm->scratch_pt);
 714         free_scratch_page(dev, vm->scratch_page);
 715 }
 716
 717 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 718 {
 719         struct i915_hw_ppgtt *ppgtt =
 720                 container_of(vm, struct i915_hw_ppgtt, base);
 721         int i;
 722
 723         for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
 724                 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
 725                         continue;
 726
 727                 gen8_free_page_tables(ppgtt->base.dev,
 728                                       ppgtt->pdp.page_directory[i]);
 729                 free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]);
 730         }
 731
 732         gen8_free_scratch(vm);
 733 }
 734
 735 /**
 736  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 737  * @ppgtt:      Master ppgtt structure.
 738  * @pd:         Page directory for this address range.
 739  * @start:      Starting virtual address to begin allocations.
 740  * @length      Size of the allocations.
 741  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 742  *              caller to free on error.
 743  *
 744  * Allocate the required number of page tables. Extremely similar to
 745  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
 746  * the page directory boundary (instead of the page directory pointer). That
 747  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
 748  * possible, and likely that the caller will need to use multiple calls of this
 749  * function to achieve the appropriate allocation.
 750  *
 751  * Return: 0 if success; negative error code otherwise.
 752  */
 753 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
 754                                      struct i915_page_directory *pd,
 755                                      uint64_t start,
 756                                      uint64_t length,
 757                                      unsigned long *new_pts)
 758 {
 759         struct drm_device *dev = ppgtt->base.dev;
 760         struct i915_page_table *pt;
 761         uint64_t temp;
 762         uint32_t pde;
 763
 764         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 765                 /* Don't reallocate page tables */
 766                 if (pt) {
 767                         /* Scratch is never allocated this way */
 768                         WARN_ON(pt == ppgtt->base.scratch_pt);
 769                         continue;
 770                 }
 771
 772                 pt = alloc_pt(dev);
 773                 if (IS_ERR(pt))
 774                         goto unwind_out;
 775
 776                 gen8_initialize_pt(&ppgtt->base, pt);
 777                 pd->page_table[pde] = pt;
 778                 __set_bit(pde, new_pts);
 779         }
 780
 781         return 0;
 782
 783 unwind_out:
 784         for_each_set_bit(pde, new_pts, I915_PDES)
 785                 free_pt(dev, pd->page_table[pde]);
 786
 787         return -ENOMEM;
 788 }
 789
 790 /**
 791  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
 792  * @ppgtt:      Master ppgtt structure.
 793  * @pdp:        Page directory pointer for this address range.
 794  * @start:      Starting virtual address to begin allocations.
 795  * @length      Size of the allocations.
 796  * @new_pds     Bitmap set by function with new allocations. Likely used by the
 797  *              caller to free on error.
 798  *
 799  * Allocate the required number of page directories starting at the pde index of
 800  * @start, and ending at the pde index @start + @length. This function will skip
 801  * over already allocated page directories within the range, and only allocate
 802  * new ones, setting the appropriate pointer within the pdp as well as the
 803  * correct position in the bitmap @new_pds.
 804  *
 805  * The function will only allocate the pages within the range for a give page
 806  * directory pointer. In other words, if @start + @length straddles a virtually
 807  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
 808  * required by the caller, This is not currently possible, and the BUG in the
 809  * code will prevent it.
 810  *
 811  * Return: 0 if success; negative error code otherwise.
 812  */
 813 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
 814                                      struct i915_page_directory_pointer *pdp,
 815                                      uint64_t start,
 816                                      uint64_t length,
 817                                      unsigned long *new_pds)
 818 {
 819         struct drm_device *dev = ppgtt->base.dev;
 820         struct i915_page_directory *pd;
 821         uint64_t temp;
 822         uint32_t pdpe;
 823
 824         WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
 825
 826         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 827                 if (pd)
 828                         continue;
 829
 830                 pd = alloc_pd(dev);
 831                 if (IS_ERR(pd))
 832                         goto unwind_out;
 833
 834                 gen8_initialize_pd(&ppgtt->base, pd);
 835                 pdp->page_directory[pdpe] = pd;
 836                 __set_bit(pdpe, new_pds);
 837         }
 838
 839         return 0;
 840
 841 unwind_out:
 842         for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
 843                 free_pd(dev, pdp->page_directory[pdpe]);
 844
 845         return -ENOMEM;
 846 }
 847
 848 static void
 849 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 850 {
 851         int i;
 852
 853         for (i = 0; i < GEN8_LEGACY_PDPES; i++)
 854                 kfree(new_pts[i]);
 855         kfree(new_pts);
 856         kfree(new_pds);
 857 }
 858
 859 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
 860  * of these are based on the number of PDPEs in the system.
 861  */
 862 static
 863 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 864                                          unsigned long ***new_pts)
 865 {
 866         int i;
 867         unsigned long *pds;
 868         unsigned long **pts;
 869
 870         pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
 871         if (!pds)
 872                 return -ENOMEM;
 873
 874         pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
 875         if (!pts) {
 876                 kfree(pds);
 877                 return -ENOMEM;
 878         }
 879
 880         for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 881                 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
 882                                  sizeof(unsigned long), GFP_KERNEL);
 883                 if (!pts[i])
 884                         goto err_out;
 885         }
 886
 887         *new_pds = pds;
 888         *new_pts = pts;
 889
 890         return 0;
 891
 892 err_out:
 893         free_gen8_temp_bitmaps(pds, pts);
 894         return -ENOMEM;
 895 }
 896
 897 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
 898  * the page table structures, we mark them dirty so that
 899  * context switching/execlist queuing code takes extra steps
 900  * to ensure that tlbs are flushed.
 901  */
 902 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 903 {
 904         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
 905 }
 906
 907 static int gen8_alloc_va_range(struct i915_address_space *vm,
 908                                uint64_t start,
 909                                uint64_t length)
 910 {
 911         struct i915_hw_ppgtt *ppgtt =
 912                 container_of(vm, struct i915_hw_ppgtt, base);
 913         unsigned long *new_page_dirs, **new_page_tables;
 914         struct i915_page_directory *pd;
 915         const uint64_t orig_start = start;
 916         const uint64_t orig_length = length;
 917         uint64_t temp;
 918         uint32_t pdpe;
 919         int ret;
 920
 921         /* Wrap is never okay since we can only represent 48b, and we don't
 922          * actually use the other side of the canonical address space.
 923          */
 924         if (WARN_ON(start + length < start))
 925                 return -ENODEV;
 926
 927         if (WARN_ON(start + length > ppgtt->base.total))
 928                 return -ENODEV;
 929
 930         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
 931         if (ret)
 932                 return ret;
 933
 934         /* Do the allocations first so we can easily bail out */
 935         ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
 936                                         new_page_dirs);
 937         if (ret) {
 938                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 939                 return ret;
 940         }
 941
 942         /* For every page directory referenced, allocate page tables */
 943         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 944                 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
 945                                                 new_page_tables[pdpe]);
 946                 if (ret)
 947                         goto err_out;
 948         }
 949
 950         start = orig_start;
 951         length = orig_length;
 952
 953         /* Allocations have completed successfully, so set the bitmaps, and do
 954          * the mappings. */
 955         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 956                 gen8_pde_t *const page_directory = kmap_px(pd);
 957                 struct i915_page_table *pt;
 958                 uint64_t pd_len = gen8_clamp_pd(start, length);
 959                 uint64_t pd_start = start;
 960                 uint32_t pde;
 961
 962                 /* Every pd should be allocated, we just did that above. */
 963                 WARN_ON(!pd);
 964
 965                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 966                         /* Same reasoning as pd */
 967                         WARN_ON(!pt);
 968                         WARN_ON(!pd_len);
 969                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
 970
 971                         /* Set our used ptes within the page table */
 972                         bitmap_set(pt->used_ptes,
 973                                    gen8_pte_index(pd_start),
 974                                    gen8_pte_count(pd_start, pd_len));
 975
 976                         /* Our pde is now pointing to the pagetable, pt */
 977                         __set_bit(pde, pd->used_pdes);
 978
 979                         /* Map the PDE to the page table */
 980                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
 981                                                               I915_CACHE_LLC);
 982
 983                         /* NB: We haven't yet mapped ptes to pages. At this
 984                          * point we're still relying on insert_entries() */
 985                 }
 986
 987                 kunmap_px(ppgtt, page_directory);
 988
 989                 __set_bit(pdpe, ppgtt->pdp.used_pdpes);
 990         }
 991
 992         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 993         mark_tlbs_dirty(ppgtt);
 994         return 0;
 995
 996 err_out:
 997         while (pdpe--) {
 998                 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
 999                         free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]);
1000         }
1001
1002         for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
1003                 free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]);
1004
1005         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1006         mark_tlbs_dirty(ppgtt);
1007         return ret;
1008 }
1009
1010 /*
1011  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1012  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1013  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1014  * space.
1015  *
1016  */
1017 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1018 {
1019         int ret;
1020
1021         ret = gen8_init_scratch(&ppgtt->base);
1022         if (ret)
1023                 return ret;
1024
1025         ppgtt->base.start = 0;
1026         ppgtt->base.total = 1ULL << 32;
1027         if (IS_ENABLED(CONFIG_X86_32))
1028                 /* While we have a proliferation of size_t variables
1029                  * we cannot represent the full ppgtt size on 32bit,
1030                  * so limit it to the same size as the GGTT (currently
1031                  * 2GiB).
1032                  */
1033                 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
1034         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1035         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1036         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1037         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1038         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1039         ppgtt->base.bind_vma = ppgtt_bind_vma;
1040
1041         ppgtt->switch_mm = gen8_mm_switch;
1042
1043         return 0;
1044 }
1045
1046 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1047 {
1048         struct i915_address_space *vm = &ppgtt->base;
1049         struct i915_page_table *unused;
1050         gen6_pte_t scratch_pte;
1051         uint32_t pd_entry;
1052         uint32_t  pte, pde, temp;
1053         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1054
1055         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1056                                      I915_CACHE_LLC, true, 0);
1057
1058         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1059                 u32 expected;
1060                 gen6_pte_t *pt_vaddr;
1061                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1062                 pd_entry = readl(ppgtt->pd_addr + pde);
1063                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1064
1065                 if (pd_entry != expected)
1066                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1067                                    pde,
1068                                    pd_entry,
1069                                    expected);
1070                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1071
1072                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1073
1074                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1075                         unsigned long va =
1076                                 (pde * PAGE_SIZE * GEN6_PTES) +
1077                                 (pte * PAGE_SIZE);
1078                         int i;
1079                         bool found = false;
1080                         for (i = 0; i < 4; i++)
1081                                 if (pt_vaddr[pte + i] != scratch_pte)
1082                                         found = true;
1083                         if (!found)
1084                                 continue;
1085
1086                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1087                         for (i = 0; i < 4; i++) {
1088                                 if (pt_vaddr[pte + i] != scratch_pte)
1089                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1090                                 else
1091                                         seq_puts(m, "  SCRATCH ");
1092                         }
1093                         seq_puts(m, "\n");
1094                 }
1095                 kunmap_px(ppgtt, pt_vaddr);
1096         }
1097 }
1098
1099 /* Write pde (index) from the page directory @pd to the page table @pt */
1100 static void gen6_write_pde(struct i915_page_directory *pd,
1101                             const int pde, struct i915_page_table *pt)
1102 {
1103         /* Caller needs to make sure the write completes if necessary */
1104         struct i915_hw_ppgtt *ppgtt =
1105                 container_of(pd, struct i915_hw_ppgtt, pd);
1106         u32 pd_entry;
1107
1108         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1109         pd_entry |= GEN6_PDE_VALID;
1110
1111         writel(pd_entry, ppgtt->pd_addr + pde);
1112 }
1113
1114 /* Write all the page tables found in the ppgtt structure to incrementing page
1115  * directories. */
1116 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1117                                   struct i915_page_directory *pd,
1118                                   uint32_t start, uint32_t length)
1119 {
1120         struct i915_page_table *pt;
1121         uint32_t pde, temp;
1122
1123         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1124                 gen6_write_pde(pd, pde, pt);
1125
1126         /* Make sure write is complete before other code can use this page
1127          * table. Also require for WC mapped PTEs */
1128         readl(dev_priv->gtt.gsm);
1129 }
1130
1131 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1132 {
1133         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1134
1135         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1136 }
1137
1138 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1139                          struct drm_i915_gem_request *req)
1140 {
1141         struct intel_engine_cs *ring = req->ring;
1142         int ret;
1143
1144         /* NB: TLBs must be flushed and invalidated before a switch */
1145         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1146         if (ret)
1147                 return ret;
1148
1149         ret = intel_ring_begin(req, 6);
1150         if (ret)
1151                 return ret;
1152
1153         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1154         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1155         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1156         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1157         intel_ring_emit(ring, get_pd_offset(ppgtt));
1158         intel_ring_emit(ring, MI_NOOP);
1159         intel_ring_advance(ring);
1160
1161         return 0;
1162 }
1163
1164 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1165                           struct drm_i915_gem_request *req)
1166 {
1167         struct intel_engine_cs *ring = req->ring;
1168         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1169
1170         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1171         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1172         return 0;
1173 }
1174
1175 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1176                           struct drm_i915_gem_request *req)
1177 {
1178         struct intel_engine_cs *ring = req->ring;
1179         int ret;
1180
1181         /* NB: TLBs must be flushed and invalidated before a switch */
1182         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1183         if (ret)
1184                 return ret;
1185
1186         ret = intel_ring_begin(req, 6);
1187         if (ret)
1188                 return ret;
1189
1190         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1191         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1192         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1193         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1194         intel_ring_emit(ring, get_pd_offset(ppgtt));
1195         intel_ring_emit(ring, MI_NOOP);
1196         intel_ring_advance(ring);
1197
1198         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1199         if (ring->id != RCS) {
1200                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1201                 if (ret)
1202                         return ret;
1203         }
1204
1205         return 0;
1206 }
1207
1208 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1209                           struct drm_i915_gem_request *req)
1210 {
1211         struct intel_engine_cs *ring = req->ring;
1212         struct drm_device *dev = ppgtt->base.dev;
1213         struct drm_i915_private *dev_priv = dev->dev_private;
1214
1215
1216         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1217         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1218
1219         POSTING_READ(RING_PP_DIR_DCLV(ring));
1220
1221         return 0;
1222 }
1223
1224 static void gen8_ppgtt_enable(struct drm_device *dev)
1225 {
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         struct intel_engine_cs *ring;
1228         int j;
1229
1230         for_each_ring(ring, dev_priv, j) {
1231                 I915_WRITE(RING_MODE_GEN7(ring),
1232                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1233         }
1234 }
1235
1236 static void gen7_ppgtt_enable(struct drm_device *dev)
1237 {
1238         struct drm_i915_private *dev_priv = dev->dev_private;
1239         struct intel_engine_cs *ring;
1240         uint32_t ecochk, ecobits;
1241         int i;
1242
1243         ecobits = I915_READ(GAC_ECO_BITS);
1244         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1245
1246         ecochk = I915_READ(GAM_ECOCHK);
1247         if (IS_HASWELL(dev)) {
1248                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1249         } else {
1250                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1251                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1252         }
1253         I915_WRITE(GAM_ECOCHK, ecochk);
1254
1255         for_each_ring(ring, dev_priv, i) {
1256                 /* GFX_MODE is per-ring on gen7+ */
1257                 I915_WRITE(RING_MODE_GEN7(ring),
1258                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1259         }
1260 }
1261
1262 static void gen6_ppgtt_enable(struct drm_device *dev)
1263 {
1264         struct drm_i915_private *dev_priv = dev->dev_private;
1265         uint32_t ecochk, gab_ctl, ecobits;
1266
1267         ecobits = I915_READ(GAC_ECO_BITS);
1268         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1269                    ECOBITS_PPGTT_CACHE64B);
1270
1271         gab_ctl = I915_READ(GAB_CTL);
1272         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1273
1274         ecochk = I915_READ(GAM_ECOCHK);
1275         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1276
1277         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1278 }
1279
1280 /* PPGTT support for Sandybdrige/Gen6 and later */
1281 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1282                                    uint64_t start,
1283                                    uint64_t length,
1284                                    bool use_scratch)
1285 {
1286         struct i915_hw_ppgtt *ppgtt =
1287                 container_of(vm, struct i915_hw_ppgtt, base);
1288         gen6_pte_t *pt_vaddr, scratch_pte;
1289         unsigned first_entry = start >> PAGE_SHIFT;
1290         unsigned num_entries = length >> PAGE_SHIFT;
1291         unsigned act_pt = first_entry / GEN6_PTES;
1292         unsigned first_pte = first_entry % GEN6_PTES;
1293         unsigned last_pte, i;
1294
1295         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1296                                      I915_CACHE_LLC, true, 0);
1297
1298         while (num_entries) {
1299                 last_pte = first_pte + num_entries;
1300                 if (last_pte > GEN6_PTES)
1301                         last_pte = GEN6_PTES;
1302
1303                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1304
1305                 for (i = first_pte; i < last_pte; i++)
1306                         pt_vaddr[i] = scratch_pte;
1307
1308                 kunmap_px(ppgtt, pt_vaddr);
1309
1310                 num_entries -= last_pte - first_pte;
1311                 first_pte = 0;
1312                 act_pt++;
1313         }
1314 }
1315
1316 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1317                                       struct sg_table *pages,
1318                                       uint64_t start,
1319                                       enum i915_cache_level cache_level, u32 flags)
1320 {
1321         struct i915_hw_ppgtt *ppgtt =
1322                 container_of(vm, struct i915_hw_ppgtt, base);
1323         gen6_pte_t *pt_vaddr;
1324         unsigned first_entry = start >> PAGE_SHIFT;
1325         unsigned act_pt = first_entry / GEN6_PTES;
1326         unsigned act_pte = first_entry % GEN6_PTES;
1327         struct sg_page_iter sg_iter;
1328
1329         pt_vaddr = NULL;
1330         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1331                 if (pt_vaddr == NULL)
1332                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1333
1334                 pt_vaddr[act_pte] =
1335                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1336                                        cache_level, true, flags);
1337
1338                 if (++act_pte == GEN6_PTES) {
1339                         kunmap_px(ppgtt, pt_vaddr);
1340                         pt_vaddr = NULL;
1341                         act_pt++;
1342                         act_pte = 0;
1343                 }
1344         }
1345         if (pt_vaddr)
1346                 kunmap_px(ppgtt, pt_vaddr);
1347 }
1348
1349 static int gen6_alloc_va_range(struct i915_address_space *vm,
1350                                uint64_t start_in, uint64_t length_in)
1351 {
1352         DECLARE_BITMAP(new_page_tables, I915_PDES);
1353         struct drm_device *dev = vm->dev;
1354         struct drm_i915_private *dev_priv = dev->dev_private;
1355         struct i915_hw_ppgtt *ppgtt =
1356                                 container_of(vm, struct i915_hw_ppgtt, base);
1357         struct i915_page_table *pt;
1358         uint32_t start, length, start_save, length_save;
1359         uint32_t pde, temp;
1360         int ret;
1361
1362         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1363                 return -ENODEV;
1364
1365         start = start_save = start_in;
1366         length = length_save = length_in;
1367
1368         bitmap_zero(new_page_tables, I915_PDES);
1369
1370         /* The allocation is done in two stages so that we can bail out with
1371          * minimal amount of pain. The first stage finds new page tables that
1372          * need allocation. The second stage marks use ptes within the page
1373          * tables.
1374          */
1375         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1376                 if (pt != vm->scratch_pt) {
1377                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1378                         continue;
1379                 }
1380
1381                 /* We've already allocated a page table */
1382                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1383
1384                 pt = alloc_pt(dev);
1385                 if (IS_ERR(pt)) {
1386                         ret = PTR_ERR(pt);
1387                         goto unwind_out;
1388                 }
1389
1390                 gen6_initialize_pt(vm, pt);
1391
1392                 ppgtt->pd.page_table[pde] = pt;
1393                 __set_bit(pde, new_page_tables);
1394                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1395         }
1396
1397         start = start_save;
1398         length = length_save;
1399
1400         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1401                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1402
1403                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1404                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1405                            gen6_pte_count(start, length));
1406
1407                 if (__test_and_clear_bit(pde, new_page_tables))
1408                         gen6_write_pde(&ppgtt->pd, pde, pt);
1409
1410                 trace_i915_page_table_entry_map(vm, pde, pt,
1411                                          gen6_pte_index(start),
1412                                          gen6_pte_count(start, length),
1413                                          GEN6_PTES);
1414                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1415                                 GEN6_PTES);
1416         }
1417
1418         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1419
1420         /* Make sure write is complete before other code can use this page
1421          * table. Also require for WC mapped PTEs */
1422         readl(dev_priv->gtt.gsm);
1423
1424         mark_tlbs_dirty(ppgtt);
1425         return 0;
1426
1427 unwind_out:
1428         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1429                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1430
1431                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1432                 free_pt(vm->dev, pt);
1433         }
1434
1435         mark_tlbs_dirty(ppgtt);
1436         return ret;
1437 }
1438
1439 static int gen6_init_scratch(struct i915_address_space *vm)
1440 {
1441         struct drm_device *dev = vm->dev;
1442
1443         vm->scratch_page = alloc_scratch_page(dev);
1444         if (IS_ERR(vm->scratch_page))
1445                 return PTR_ERR(vm->scratch_page);
1446
1447         vm->scratch_pt = alloc_pt(dev);
1448         if (IS_ERR(vm->scratch_pt)) {
1449                 free_scratch_page(dev, vm->scratch_page);
1450                 return PTR_ERR(vm->scratch_pt);
1451         }
1452
1453         gen6_initialize_pt(vm, vm->scratch_pt);
1454
1455         return 0;
1456 }
1457
1458 static void gen6_free_scratch(struct i915_address_space *vm)
1459 {
1460         struct drm_device *dev = vm->dev;
1461
1462         free_pt(dev, vm->scratch_pt);
1463         free_scratch_page(dev, vm->scratch_page);
1464 }
1465
1466 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1467 {
1468         struct i915_hw_ppgtt *ppgtt =
1469                 container_of(vm, struct i915_hw_ppgtt, base);
1470         struct i915_page_table *pt;
1471         uint32_t pde;
1472
1473         drm_mm_remove_node(&ppgtt->node);
1474
1475         gen6_for_all_pdes(pt, ppgtt, pde) {
1476                 if (pt != vm->scratch_pt)
1477                         free_pt(ppgtt->base.dev, pt);
1478         }
1479
1480         gen6_free_scratch(vm);
1481 }
1482
1483 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1484 {
1485         struct i915_address_space *vm = &ppgtt->base;
1486         struct drm_device *dev = ppgtt->base.dev;
1487         struct drm_i915_private *dev_priv = dev->dev_private;
1488         bool retried = false;
1489         int ret;
1490
1491         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1492          * allocator works in address space sizes, so it's multiplied by page
1493          * size. We allocate at the top of the GTT to avoid fragmentation.
1494          */
1495         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1496
1497         ret = gen6_init_scratch(vm);
1498         if (ret)
1499                 return ret;
1500
1501 alloc:
1502         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1503                                                   &ppgtt->node, GEN6_PD_SIZE,
1504                                                   GEN6_PD_ALIGN, 0,
1505                                                   0, dev_priv->gtt.base.total,
1506                                                   DRM_MM_TOPDOWN);
1507         if (ret == -ENOSPC && !retried) {
1508                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1509                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1510                                                I915_CACHE_NONE,
1511                                                0, dev_priv->gtt.base.total,
1512                                                0);
1513                 if (ret)
1514                         goto err_out;
1515
1516                 retried = true;
1517                 goto alloc;
1518         }
1519
1520         if (ret)
1521                 goto err_out;
1522
1523
1524         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1525                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1526
1527         return 0;
1528
1529 err_out:
1530         gen6_free_scratch(vm);
1531         return ret;
1532 }
1533
1534 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1535 {
1536         return gen6_ppgtt_allocate_page_directories(ppgtt);
1537 }
1538
1539 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1540                                   uint64_t start, uint64_t length)
1541 {
1542         struct i915_page_table *unused;
1543         uint32_t pde, temp;
1544
1545         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1546                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
1547 }
1548
1549 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1550 {
1551         struct drm_device *dev = ppgtt->base.dev;
1552         struct drm_i915_private *dev_priv = dev->dev_private;
1553         int ret;
1554
1555         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1556         if (IS_GEN6(dev)) {
1557                 ppgtt->switch_mm = gen6_mm_switch;
1558         } else if (IS_HASWELL(dev)) {
1559                 ppgtt->switch_mm = hsw_mm_switch;
1560         } else if (IS_GEN7(dev)) {
1561                 ppgtt->switch_mm = gen7_mm_switch;
1562         } else
1563                 BUG();
1564
1565         if (intel_vgpu_active(dev))
1566                 ppgtt->switch_mm = vgpu_mm_switch;
1567
1568         ret = gen6_ppgtt_alloc(ppgtt);
1569         if (ret)
1570                 return ret;
1571
1572         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1573         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1574         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1575         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1576         ppgtt->base.bind_vma = ppgtt_bind_vma;
1577         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1578         ppgtt->base.start = 0;
1579         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1580         ppgtt->debug_dump = gen6_dump_ppgtt;
1581
1582         ppgtt->pd.base.ggtt_offset =
1583                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1584
1585         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1586                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1587
1588         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1589
1590         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1591
1592         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1593                          ppgtt->node.size >> 20,
1594                          ppgtt->node.start / PAGE_SIZE);
1595
1596         DRM_DEBUG("Adding PPGTT at offset %x\n",
1597                   ppgtt->pd.base.ggtt_offset << 10);
1598
1599         return 0;
1600 }
1601
1602 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1603 {
1604         ppgtt->base.dev = dev;
1605
1606         if (INTEL_INFO(dev)->gen < 8)
1607                 return gen6_ppgtt_init(ppgtt);
1608         else
1609                 return gen8_ppgtt_init(ppgtt);
1610 }
1611
1612 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1613 {
1614         struct drm_i915_private *dev_priv = dev->dev_private;
1615         int ret = 0;
1616
1617         ret = __hw_ppgtt_init(dev, ppgtt);
1618         if (ret == 0) {
1619                 kref_init(&ppgtt->ref);
1620                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1621                             ppgtt->base.total);
1622                 i915_init_vm(dev_priv, &ppgtt->base);
1623         }
1624
1625         return ret;
1626 }
1627
1628 int i915_ppgtt_init_hw(struct drm_device *dev)
1629 {
1630         /* In the case of execlists, PPGTT is enabled by the context descriptor
1631          * and the PDPs are contained within the context itself.  We don't
1632          * need to do anything here. */
1633         if (i915.enable_execlists)
1634                 return 0;
1635
1636         if (!USES_PPGTT(dev))
1637                 return 0;
1638
1639         if (IS_GEN6(dev))
1640                 gen6_ppgtt_enable(dev);
1641         else if (IS_GEN7(dev))
1642                 gen7_ppgtt_enable(dev);
1643         else if (INTEL_INFO(dev)->gen >= 8)
1644                 gen8_ppgtt_enable(dev);
1645         else
1646                 MISSING_CASE(INTEL_INFO(dev)->gen);
1647
1648         return 0;
1649 }
1650
1651 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
1652 {
1653         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
1654         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1655
1656         if (i915.enable_execlists)
1657                 return 0;
1658
1659         if (!ppgtt)
1660                 return 0;
1661
1662         return ppgtt->switch_mm(ppgtt, req);
1663 }
1664
1665 struct i915_hw_ppgtt *
1666 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1667 {
1668         struct i915_hw_ppgtt *ppgtt;
1669         int ret;
1670
1671         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1672         if (!ppgtt)
1673                 return ERR_PTR(-ENOMEM);
1674
1675         ret = i915_ppgtt_init(dev, ppgtt);
1676         if (ret) {
1677                 kfree(ppgtt);
1678                 return ERR_PTR(ret);
1679         }
1680
1681         ppgtt->file_priv = fpriv;
1682
1683         trace_i915_ppgtt_create(&ppgtt->base);
1684
1685         return ppgtt;
1686 }
1687
1688 void  i915_ppgtt_release(struct kref *kref)
1689 {
1690         struct i915_hw_ppgtt *ppgtt =
1691                 container_of(kref, struct i915_hw_ppgtt, ref);
1692
1693         trace_i915_ppgtt_release(&ppgtt->base);
1694
1695         /* vmas should already be unbound */
1696         WARN_ON(!list_empty(&ppgtt->base.active_list));
1697         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1698
1699         list_del(&ppgtt->base.global_link);
1700         drm_mm_takedown(&ppgtt->base.mm);
1701
1702         ppgtt->base.cleanup(&ppgtt->base);
1703         kfree(ppgtt);
1704 }
1705
1706 extern int intel_iommu_gfx_mapped;
1707 /* Certain Gen5 chipsets require require idling the GPU before
1708  * unmapping anything from the GTT when VT-d is enabled.
1709  */
1710 static bool needs_idle_maps(struct drm_device *dev)
1711 {
1712 #ifdef CONFIG_INTEL_IOMMU
1713         /* Query intel_iommu to see if we need the workaround. Presumably that
1714          * was loaded first.
1715          */
1716         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1717                 return true;
1718 #endif
1719         return false;
1720 }
1721
1722 static bool do_idling(struct drm_i915_private *dev_priv)
1723 {
1724         bool ret = dev_priv->mm.interruptible;
1725
1726         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1727                 dev_priv->mm.interruptible = false;
1728                 if (i915_gpu_idle(dev_priv->dev)) {
1729                         DRM_ERROR("Couldn't idle GPU\n");
1730                         /* Wait a bit, in hopes it avoids the hang */
1731                         udelay(10);
1732                 }
1733         }
1734
1735         return ret;
1736 }
1737
1738 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1739 {
1740         if (unlikely(dev_priv->gtt.do_idle_maps))
1741                 dev_priv->mm.interruptible = interruptible;
1742 }
1743
1744 void i915_check_and_clear_faults(struct drm_device *dev)
1745 {
1746         struct drm_i915_private *dev_priv = dev->dev_private;
1747         struct intel_engine_cs *ring;
1748         int i;
1749
1750         if (INTEL_INFO(dev)->gen < 6)
1751                 return;
1752
1753         for_each_ring(ring, dev_priv, i) {
1754                 u32 fault_reg;
1755                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1756                 if (fault_reg & RING_FAULT_VALID) {
1757                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1758                                          "\tAddr: 0x%08lx\n"
1759                                          "\tAddress space: %s\n"
1760                                          "\tSource ID: %d\n"
1761                                          "\tType: %d\n",
1762                                          fault_reg & PAGE_MASK,
1763                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1764                                          RING_FAULT_SRCID(fault_reg),
1765                                          RING_FAULT_FAULT_TYPE(fault_reg));
1766                         I915_WRITE(RING_FAULT_REG(ring),
1767                                    fault_reg & ~RING_FAULT_VALID);
1768                 }
1769         }
1770         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1771 }
1772
1773 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1774 {
1775         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1776                 intel_gtt_chipset_flush();
1777         } else {
1778                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1779                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1780         }
1781 }
1782
1783 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1784 {
1785         struct drm_i915_private *dev_priv = dev->dev_private;
1786
1787         /* Don't bother messing with faults pre GEN6 as we have little
1788          * documentation supporting that it's a good idea.
1789          */
1790         if (INTEL_INFO(dev)->gen < 6)
1791                 return;
1792
1793         i915_check_and_clear_faults(dev);
1794
1795         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1796                                        dev_priv->gtt.base.start,
1797                                        dev_priv->gtt.base.total,
1798                                        true);
1799
1800         i915_ggtt_flush(dev_priv);
1801 }
1802
1803 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1804 {
1805         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1806                         obj->pages->sgl, obj->pages->nents,
1807                         PCI_DMA_BIDIRECTIONAL))
1808                 return -ENOSPC;
1809
1810         return 0;
1811 }
1812
1813 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1814 {
1815 #ifdef writeq
1816         writeq(pte, addr);
1817 #else
1818         iowrite32((u32)pte, addr);
1819         iowrite32(pte >> 32, addr + 4);
1820 #endif
1821 }
1822
1823 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1824                                      struct sg_table *st,
1825                                      uint64_t start,
1826                                      enum i915_cache_level level, u32 unused)
1827 {
1828         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1829         unsigned first_entry = start >> PAGE_SHIFT;
1830         gen8_pte_t __iomem *gtt_entries =
1831                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1832         int i = 0;
1833         struct sg_page_iter sg_iter;
1834         dma_addr_t addr = 0; /* shut up gcc */
1835
1836         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1837                 addr = sg_dma_address(sg_iter.sg) +
1838                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1839                 gen8_set_pte(&gtt_entries[i],
1840                              gen8_pte_encode(addr, level, true));
1841                 i++;
1842         }
1843
1844         /*
1845          * XXX: This serves as a posting read to make sure that the PTE has
1846          * actually been updated. There is some concern that even though
1847          * registers and PTEs are within the same BAR that they are potentially
1848          * of NUMA access patterns. Therefore, even with the way we assume
1849          * hardware should work, we must keep this posting read for paranoia.
1850          */
1851         if (i != 0)
1852                 WARN_ON(readq(&gtt_entries[i-1])
1853                         != gen8_pte_encode(addr, level, true));
1854
1855         /* This next bit makes the above posting read even more important. We
1856          * want to flush the TLBs only after we're certain all the PTE updates
1857          * have finished.
1858          */
1859         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1860         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1861 }
1862
1863 /*
1864  * Binds an object into the global gtt with the specified cache level. The object
1865  * will be accessible to the GPU via commands whose operands reference offsets
1866  * within the global GTT as well as accessible by the GPU through the GMADR
1867  * mapped BAR (dev_priv->mm.gtt->gtt).
1868  */
1869 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1870                                      struct sg_table *st,
1871                                      uint64_t start,
1872                                      enum i915_cache_level level, u32 flags)
1873 {
1874         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1875         unsigned first_entry = start >> PAGE_SHIFT;
1876         gen6_pte_t __iomem *gtt_entries =
1877                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1878         int i = 0;
1879         struct sg_page_iter sg_iter;
1880         dma_addr_t addr = 0;
1881
1882         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1883                 addr = sg_page_iter_dma_address(&sg_iter);
1884                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1885                 i++;
1886         }
1887
1888         /* XXX: This serves as a posting read to make sure that the PTE has
1889          * actually been updated. There is some concern that even though
1890          * registers and PTEs are within the same BAR that they are potentially
1891          * of NUMA access patterns. Therefore, even with the way we assume
1892          * hardware should work, we must keep this posting read for paranoia.
1893          */
1894         if (i != 0) {
1895                 unsigned long gtt = readl(&gtt_entries[i-1]);
1896                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1897         }
1898
1899         /* This next bit makes the above posting read even more important. We
1900          * want to flush the TLBs only after we're certain all the PTE updates
1901          * have finished.
1902          */
1903         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1904         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1905 }
1906
1907 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1908                                   uint64_t start,
1909                                   uint64_t length,
1910                                   bool use_scratch)
1911 {
1912         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1913         unsigned first_entry = start >> PAGE_SHIFT;
1914         unsigned num_entries = length >> PAGE_SHIFT;
1915         gen8_pte_t scratch_pte, __iomem *gtt_base =
1916                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1917         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1918         int i;
1919
1920         if (WARN(num_entries > max_entries,
1921                  "First entry = %d; Num entries = %d (max=%d)\n",
1922                  first_entry, num_entries, max_entries))
1923                 num_entries = max_entries;
1924
1925         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1926                                       I915_CACHE_LLC,
1927                                       use_scratch);
1928         for (i = 0; i < num_entries; i++)
1929                 gen8_set_pte(&gtt_base[i], scratch_pte);
1930         readl(gtt_base);
1931 }
1932
1933 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1934                                   uint64_t start,
1935                                   uint64_t length,
1936                                   bool use_scratch)
1937 {
1938         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1939         unsigned first_entry = start >> PAGE_SHIFT;
1940         unsigned num_entries = length >> PAGE_SHIFT;
1941         gen6_pte_t scratch_pte, __iomem *gtt_base =
1942                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1943         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1944         int i;
1945
1946         if (WARN(num_entries > max_entries,
1947                  "First entry = %d; Num entries = %d (max=%d)\n",
1948                  first_entry, num_entries, max_entries))
1949                 num_entries = max_entries;
1950
1951         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1952                                      I915_CACHE_LLC, use_scratch, 0);
1953
1954         for (i = 0; i < num_entries; i++)
1955                 iowrite32(scratch_pte, &gtt_base[i]);
1956         readl(gtt_base);
1957 }
1958
1959 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1960                                      struct sg_table *pages,
1961                                      uint64_t start,
1962                                      enum i915_cache_level cache_level, u32 unused)
1963 {
1964         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1965                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1966
1967         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1968
1969 }
1970
1971 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1972                                   uint64_t start,
1973                                   uint64_t length,
1974                                   bool unused)
1975 {
1976         unsigned first_entry = start >> PAGE_SHIFT;
1977         unsigned num_entries = length >> PAGE_SHIFT;
1978         intel_gtt_clear_range(first_entry, num_entries);
1979 }
1980
1981 static int ggtt_bind_vma(struct i915_vma *vma,
1982                          enum i915_cache_level cache_level,
1983                          u32 flags)
1984 {
1985         struct drm_device *dev = vma->vm->dev;
1986         struct drm_i915_private *dev_priv = dev->dev_private;
1987         struct drm_i915_gem_object *obj = vma->obj;
1988         struct sg_table *pages = obj->pages;
1989         u32 pte_flags = 0;
1990         int ret;
1991
1992         ret = i915_get_ggtt_vma_pages(vma);
1993         if (ret)
1994                 return ret;
1995         pages = vma->ggtt_view.pages;
1996
1997         /* Currently applicable only to VLV */
1998         if (obj->gt_ro)
1999                 pte_flags |= PTE_READ_ONLY;
2000
2001
2002         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
2003                 vma->vm->insert_entries(vma->vm, pages,
2004                                         vma->node.start,
2005                                         cache_level, pte_flags);
2006         }
2007
2008         if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
2009                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2010                 appgtt->base.insert_entries(&appgtt->base, pages,
2011                                             vma->node.start,
2012                                             cache_level, pte_flags);
2013         }
2014
2015         return 0;
2016 }
2017
2018 static void ggtt_unbind_vma(struct i915_vma *vma)
2019 {
2020         struct drm_device *dev = vma->vm->dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         struct drm_i915_gem_object *obj = vma->obj;
2023         const uint64_t size = min_t(uint64_t,
2024                                     obj->base.size,
2025                                     vma->node.size);
2026
2027         if (vma->bound & GLOBAL_BIND) {
2028                 vma->vm->clear_range(vma->vm,
2029                                      vma->node.start,
2030                                      size,
2031                                      true);
2032         }
2033
2034         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2035                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2036
2037                 appgtt->base.clear_range(&appgtt->base,
2038                                          vma->node.start,
2039                                          size,
2040                                          true);
2041         }
2042 }
2043
2044 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2045 {
2046         struct drm_device *dev = obj->base.dev;
2047         struct drm_i915_private *dev_priv = dev->dev_private;
2048         bool interruptible;
2049
2050         interruptible = do_idling(dev_priv);
2051
2052         dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2053                      PCI_DMA_BIDIRECTIONAL);
2054
2055         undo_idling(dev_priv, interruptible);
2056 }
2057
2058 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2059                                   unsigned long color,
2060                                   u64 *start,
2061                                   u64 *end)
2062 {
2063         if (node->color != color)
2064                 *start += 4096;
2065
2066         if (!list_empty(&node->node_list)) {
2067                 node = list_entry(node->node_list.next,
2068                                   struct drm_mm_node,
2069                                   node_list);
2070                 if (node->allocated && node->color != color)
2071                         *end -= 4096;
2072         }
2073 }
2074
2075 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2076                                      unsigned long start,
2077                                      unsigned long mappable_end,
2078                                      unsigned long end)
2079 {
2080         /* Let GEM Manage all of the aperture.
2081          *
2082          * However, leave one page at the end still bound to the scratch page.
2083          * There are a number of places where the hardware apparently prefetches
2084          * past the end of the object, and we've seen multiple hangs with the
2085          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2086          * aperture.  One page should be enough to keep any prefetching inside
2087          * of the aperture.
2088          */
2089         struct drm_i915_private *dev_priv = dev->dev_private;
2090         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2091         struct drm_mm_node *entry;
2092         struct drm_i915_gem_object *obj;
2093         unsigned long hole_start, hole_end;
2094         int ret;
2095
2096         BUG_ON(mappable_end > end);
2097
2098         /* Subtract the guard page ... */
2099         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2100
2101         dev_priv->gtt.base.start = start;
2102         dev_priv->gtt.base.total = end - start;
2103
2104         if (intel_vgpu_active(dev)) {
2105                 ret = intel_vgt_balloon(dev);
2106                 if (ret)
2107                         return ret;
2108         }
2109
2110         if (!HAS_LLC(dev))
2111                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2112
2113         /* Mark any preallocated objects as occupied */
2114         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2115                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2116
2117                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2118                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2119
2120                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2121                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2122                 if (ret) {
2123                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2124                         return ret;
2125                 }
2126                 vma->bound |= GLOBAL_BIND;
2127         }
2128
2129         /* Clear any non-preallocated blocks */
2130         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2131                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2132                               hole_start, hole_end);
2133                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2134                                      hole_end - hole_start, true);
2135         }
2136
2137         /* And finally clear the reserved guard page */
2138         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2139
2140         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2141                 struct i915_hw_ppgtt *ppgtt;
2142
2143                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2144                 if (!ppgtt)
2145                         return -ENOMEM;
2146
2147                 ret = __hw_ppgtt_init(dev, ppgtt);
2148                 if (ret) {
2149                         ppgtt->base.cleanup(&ppgtt->base);
2150                         kfree(ppgtt);
2151                         return ret;
2152                 }
2153
2154                 if (ppgtt->base.allocate_va_range)
2155                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2156                                                             ppgtt->base.total);
2157                 if (ret) {
2158                         ppgtt->base.cleanup(&ppgtt->base);
2159                         kfree(ppgtt);
2160                         return ret;
2161                 }
2162
2163                 ppgtt->base.clear_range(&ppgtt->base,
2164                                         ppgtt->base.start,
2165                                         ppgtt->base.total,
2166                                         true);
2167
2168                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2169         }
2170
2171         return 0;
2172 }
2173
2174 void i915_gem_init_global_gtt(struct drm_device *dev)
2175 {
2176         struct drm_i915_private *dev_priv = dev->dev_private;
2177         u64 gtt_size, mappable_size;
2178
2179         gtt_size = dev_priv->gtt.base.total;
2180         mappable_size = dev_priv->gtt.mappable_end;
2181
2182         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2183 }
2184
2185 void i915_global_gtt_cleanup(struct drm_device *dev)
2186 {
2187         struct drm_i915_private *dev_priv = dev->dev_private;
2188         struct i915_address_space *vm = &dev_priv->gtt.base;
2189
2190         if (dev_priv->mm.aliasing_ppgtt) {
2191                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2192
2193                 ppgtt->base.cleanup(&ppgtt->base);
2194         }
2195
2196         if (drm_mm_initialized(&vm->mm)) {
2197                 if (intel_vgpu_active(dev))
2198                         intel_vgt_deballoon();
2199
2200                 drm_mm_takedown(&vm->mm);
2201                 list_del(&vm->global_link);
2202         }
2203
2204         vm->cleanup(vm);
2205 }
2206
2207 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2208 {
2209         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2210         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2211         return snb_gmch_ctl << 20;
2212 }
2213
2214 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2215 {
2216         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2217         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2218         if (bdw_gmch_ctl)
2219                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2220
2221 #ifdef CONFIG_X86_32
2222         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2223         if (bdw_gmch_ctl > 4)
2224                 bdw_gmch_ctl = 4;
2225 #endif
2226
2227         return bdw_gmch_ctl << 20;
2228 }
2229
2230 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2231 {
2232         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2233         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2234
2235         if (gmch_ctrl)
2236                 return 1 << (20 + gmch_ctrl);
2237
2238         return 0;
2239 }
2240
2241 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2242 {
2243         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2244         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2245         return snb_gmch_ctl << 25; /* 32 MB units */
2246 }
2247
2248 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2249 {
2250         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2251         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2252         return bdw_gmch_ctl << 25; /* 32 MB units */
2253 }
2254
2255 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2256 {
2257         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2258         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2259
2260         /*
2261          * 0x0  to 0x10: 32MB increments starting at 0MB
2262          * 0x11 to 0x16: 4MB increments starting at 8MB
2263          * 0x17 to 0x1d: 4MB increments start at 36MB
2264          */
2265         if (gmch_ctrl < 0x11)
2266                 return gmch_ctrl << 25;
2267         else if (gmch_ctrl < 0x17)
2268                 return (gmch_ctrl - 0x11 + 2) << 22;
2269         else
2270                 return (gmch_ctrl - 0x17 + 9) << 22;
2271 }
2272
2273 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2274 {
2275         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2276         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2277
2278         if (gen9_gmch_ctl < 0xf0)
2279                 return gen9_gmch_ctl << 25; /* 32 MB units */
2280         else
2281                 /* 4MB increments starting at 0xf0 for 4MB */
2282                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2283 }
2284
2285 static int ggtt_probe_common(struct drm_device *dev,
2286                              size_t gtt_size)
2287 {
2288         struct drm_i915_private *dev_priv = dev->dev_private;
2289         struct i915_page_scratch *scratch_page;
2290         phys_addr_t gtt_phys_addr;
2291
2292         /* For Modern GENs the PTEs and register space are split in the BAR */
2293         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2294                 (pci_resource_len(dev->pdev, 0) / 2);
2295
2296         /*
2297          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2298          * dropped. For WC mappings in general we have 64 byte burst writes
2299          * when the WC buffer is flushed, so we can't use it, but have to
2300          * resort to an uncached mapping. The WC issue is easily caught by the
2301          * readback check when writing GTT PTE entries.
2302          */
2303         if (IS_BROXTON(dev))
2304                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2305         else
2306                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2307         if (!dev_priv->gtt.gsm) {
2308                 DRM_ERROR("Failed to map the gtt page table\n");
2309                 return -ENOMEM;
2310         }
2311
2312         scratch_page = alloc_scratch_page(dev);
2313         if (IS_ERR(scratch_page)) {
2314                 DRM_ERROR("Scratch setup failed\n");
2315                 /* iounmap will also get called at remove, but meh */
2316                 iounmap(dev_priv->gtt.gsm);
2317                 return PTR_ERR(scratch_page);
2318         }
2319
2320         dev_priv->gtt.base.scratch_page = scratch_page;
2321
2322         return 0;
2323 }
2324
2325 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2326  * bits. When using advanced contexts each context stores its own PAT, but
2327  * writing this data shouldn't be harmful even in those cases. */
2328 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2329 {
2330         uint64_t pat;
2331
2332         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2333               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2334               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2335               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2336               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2337               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2338               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2339               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2340
2341         if (!USES_PPGTT(dev_priv->dev))
2342                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2343                  * so RTL will always use the value corresponding to
2344                  * pat_sel = 000".
2345                  * So let's disable cache for GGTT to avoid screen corruptions.
2346                  * MOCS still can be used though.
2347                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2348                  * before this patch, i.e. the same uncached + snooping access
2349                  * like on gen6/7 seems to be in effect.
2350                  * - So this just fixes blitter/render access. Again it looks
2351                  * like it's not just uncached access, but uncached + snooping.
2352                  * So we can still hold onto all our assumptions wrt cpu
2353                  * clflushing on LLC machines.
2354                  */
2355                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2356
2357         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2358          * write would work. */
2359         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2360         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2361 }
2362
2363 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2364 {
2365         uint64_t pat;
2366
2367         /*
2368          * Map WB on BDW to snooped on CHV.
2369          *
2370          * Only the snoop bit has meaning for CHV, the rest is
2371          * ignored.
2372          *
2373          * The hardware will never snoop for certain types of accesses:
2374          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2375          * - PPGTT page tables
2376          * - some other special cycles
2377          *
2378          * As with BDW, we also need to consider the following for GT accesses:
2379          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2380          * so RTL will always use the value corresponding to
2381          * pat_sel = 000".
2382          * Which means we must set the snoop bit in PAT entry 0
2383          * in order to keep the global status page working.
2384          */
2385         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2386               GEN8_PPAT(1, 0) |
2387               GEN8_PPAT(2, 0) |
2388               GEN8_PPAT(3, 0) |
2389               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2390               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2391               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2392               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2393
2394         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2395         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2396 }
2397
2398 static int gen8_gmch_probe(struct drm_device *dev,
2399                            u64 *gtt_total,
2400                            size_t *stolen,
2401                            phys_addr_t *mappable_base,
2402                            u64 *mappable_end)
2403 {
2404         struct drm_i915_private *dev_priv = dev->dev_private;
2405         u64 gtt_size;
2406         u16 snb_gmch_ctl;
2407         int ret;
2408
2409         /* TODO: We're not aware of mappable constraints on gen8 yet */
2410         *mappable_base = pci_resource_start(dev->pdev, 2);
2411         *mappable_end = pci_resource_len(dev->pdev, 2);
2412
2413         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2414                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2415
2416         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2417
2418         if (INTEL_INFO(dev)->gen >= 9) {
2419                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2420                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2421         } else if (IS_CHERRYVIEW(dev)) {
2422                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2423                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2424         } else {
2425                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2426                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2427         }
2428
2429         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2430
2431         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2432                 chv_setup_private_ppat(dev_priv);
2433         else
2434                 bdw_setup_private_ppat(dev_priv);
2435
2436         ret = ggtt_probe_common(dev, gtt_size);
2437
2438         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2439         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2440         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2441         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2442
2443         return ret;
2444 }
2445
2446 static int gen6_gmch_probe(struct drm_device *dev,
2447                            u64 *gtt_total,
2448                            size_t *stolen,
2449                            phys_addr_t *mappable_base,
2450                            u64 *mappable_end)
2451 {
2452         struct drm_i915_private *dev_priv = dev->dev_private;
2453         unsigned int gtt_size;
2454         u16 snb_gmch_ctl;
2455         int ret;
2456
2457         *mappable_base = pci_resource_start(dev->pdev, 2);
2458         *mappable_end = pci_resource_len(dev->pdev, 2);
2459
2460         /* 64/512MB is the current min/max we actually know of, but this is just
2461          * a coarse sanity check.
2462          */
2463         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2464                 DRM_ERROR("Unknown GMADR size (%llx)\n",
2465                           dev_priv->gtt.mappable_end);
2466                 return -ENXIO;
2467         }
2468
2469         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2470                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2471         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2472
2473         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2474
2475         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2476         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2477
2478         ret = ggtt_probe_common(dev, gtt_size);
2479
2480         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2481         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2482         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2483         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2484
2485         return ret;
2486 }
2487
2488 static void gen6_gmch_remove(struct i915_address_space *vm)
2489 {
2490
2491         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2492
2493         iounmap(gtt->gsm);
2494         free_scratch_page(vm->dev, vm->scratch_page);
2495 }
2496
2497 static int i915_gmch_probe(struct drm_device *dev,
2498                            u64 *gtt_total,
2499                            size_t *stolen,
2500                            phys_addr_t *mappable_base,
2501                            u64 *mappable_end)
2502 {
2503         struct drm_i915_private *dev_priv = dev->dev_private;
2504         int ret;
2505
2506         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2507         if (!ret) {
2508                 DRM_ERROR("failed to set up gmch\n");
2509                 return -EIO;
2510         }
2511
2512         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2513
2514         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2515         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2516         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2517         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2518         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2519
2520         if (unlikely(dev_priv->gtt.do_idle_maps))
2521                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2522
2523         return 0;
2524 }
2525
2526 static void i915_gmch_remove(struct i915_address_space *vm)
2527 {
2528         intel_gmch_remove();
2529 }
2530
2531 int i915_gem_gtt_init(struct drm_device *dev)
2532 {
2533         struct drm_i915_private *dev_priv = dev->dev_private;
2534         struct i915_gtt *gtt = &dev_priv->gtt;
2535         int ret;
2536
2537         if (INTEL_INFO(dev)->gen <= 5) {
2538                 gtt->gtt_probe = i915_gmch_probe;
2539                 gtt->base.cleanup = i915_gmch_remove;
2540         } else if (INTEL_INFO(dev)->gen < 8) {
2541                 gtt->gtt_probe = gen6_gmch_probe;
2542                 gtt->base.cleanup = gen6_gmch_remove;
2543                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2544                         gtt->base.pte_encode = iris_pte_encode;
2545                 else if (IS_HASWELL(dev))
2546                         gtt->base.pte_encode = hsw_pte_encode;
2547                 else if (IS_VALLEYVIEW(dev))
2548                         gtt->base.pte_encode = byt_pte_encode;
2549                 else if (INTEL_INFO(dev)->gen >= 7)
2550                         gtt->base.pte_encode = ivb_pte_encode;
2551                 else
2552                         gtt->base.pte_encode = snb_pte_encode;
2553         } else {
2554                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2555                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2556         }
2557
2558         gtt->base.dev = dev;
2559
2560         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2561                              &gtt->mappable_base, &gtt->mappable_end);
2562         if (ret)
2563                 return ret;
2564
2565         /* GMADR is the PCI mmio aperture into the global GTT. */
2566         DRM_INFO("Memory usable by graphics device = %lluM\n",
2567                  gtt->base.total >> 20);
2568         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
2569         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2570 #ifdef CONFIG_INTEL_IOMMU
2571         if (intel_iommu_gfx_mapped)
2572                 DRM_INFO("VT-d active for gfx access\n");
2573 #endif
2574         /*
2575          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2576          * user's requested state against the hardware/driver capabilities.  We
2577          * do this now so that we can print out any log messages once rather
2578          * than every time we check intel_enable_ppgtt().
2579          */
2580         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2581         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2582
2583         return 0;
2584 }
2585
2586 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2587 {
2588         struct drm_i915_private *dev_priv = dev->dev_private;
2589         struct drm_i915_gem_object *obj;
2590         struct i915_address_space *vm;
2591         struct i915_vma *vma;
2592         bool flush;
2593
2594         i915_check_and_clear_faults(dev);
2595
2596         /* First fill our portion of the GTT with scratch pages */
2597         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2598                                        dev_priv->gtt.base.start,
2599                                        dev_priv->gtt.base.total,
2600                                        true);
2601
2602         /* Cache flush objects bound into GGTT and rebind them. */
2603         vm = &dev_priv->gtt.base;
2604         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2605                 flush = false;
2606                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
2607                         if (vma->vm != vm)
2608                                 continue;
2609
2610                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
2611                                               PIN_UPDATE));
2612
2613                         flush = true;
2614                 }
2615
2616                 if (flush)
2617                         i915_gem_clflush_object(obj, obj->pin_display);
2618         }
2619
2620         if (INTEL_INFO(dev)->gen >= 8) {
2621                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2622                         chv_setup_private_ppat(dev_priv);
2623                 else
2624                         bdw_setup_private_ppat(dev_priv);
2625
2626                 return;
2627         }
2628
2629         if (USES_PPGTT(dev)) {
2630                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2631                         /* TODO: Perhaps it shouldn't be gen6 specific */
2632
2633                         struct i915_hw_ppgtt *ppgtt =
2634                                         container_of(vm, struct i915_hw_ppgtt,
2635                                                      base);
2636
2637                         if (i915_is_ggtt(vm))
2638                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
2639
2640                         gen6_write_page_range(dev_priv, &ppgtt->pd,
2641                                               0, ppgtt->base.total);
2642                 }
2643         }
2644
2645         i915_ggtt_flush(dev_priv);
2646 }
2647
2648 static struct i915_vma *
2649 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2650                       struct i915_address_space *vm,
2651                       const struct i915_ggtt_view *ggtt_view)
2652 {
2653         struct i915_vma *vma;
2654
2655         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2656                 return ERR_PTR(-EINVAL);
2657
2658         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2659         if (vma == NULL)
2660                 return ERR_PTR(-ENOMEM);
2661
2662         INIT_LIST_HEAD(&vma->vma_link);
2663         INIT_LIST_HEAD(&vma->mm_list);
2664         INIT_LIST_HEAD(&vma->exec_list);
2665         vma->vm = vm;
2666         vma->obj = obj;
2667
2668         if (i915_is_ggtt(vm))
2669                 vma->ggtt_view = *ggtt_view;
2670
2671         list_add_tail(&vma->vma_link, &obj->vma_list);
2672         if (!i915_is_ggtt(vm))
2673                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2674
2675         return vma;
2676 }
2677
2678 struct i915_vma *
2679 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2680                                   struct i915_address_space *vm)
2681 {
2682         struct i915_vma *vma;
2683
2684         vma = i915_gem_obj_to_vma(obj, vm);
2685         if (!vma)
2686                 vma = __i915_gem_vma_create(obj, vm,
2687                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2688
2689         return vma;
2690 }
2691
2692 struct i915_vma *
2693 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2694                                        const struct i915_ggtt_view *view)
2695 {
2696         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2697         struct i915_vma *vma;
2698
2699         if (WARN_ON(!view))
2700                 return ERR_PTR(-EINVAL);
2701
2702         vma = i915_gem_obj_to_ggtt_view(obj, view);
2703
2704         if (IS_ERR(vma))
2705                 return vma;
2706
2707         if (!vma)
2708                 vma = __i915_gem_vma_create(obj, ggtt, view);
2709
2710         return vma;
2711
2712 }
2713
2714 static void
2715 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2716              struct sg_table *st)
2717 {
2718         unsigned int column, row;
2719         unsigned int src_idx;
2720         struct scatterlist *sg = st->sgl;
2721
2722         st->nents = 0;
2723
2724         for (column = 0; column < width; column++) {
2725                 src_idx = width * (height - 1) + column;
2726                 for (row = 0; row < height; row++) {
2727                         st->nents++;
2728                         /* We don't need the pages, but need to initialize
2729                          * the entries so the sg list can be happily traversed.
2730                          * The only thing we need are DMA addresses.
2731                          */
2732                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
2733                         sg_dma_address(sg) = in[src_idx];
2734                         sg_dma_len(sg) = PAGE_SIZE;
2735                         sg = sg_next(sg);
2736                         src_idx -= width;
2737                 }
2738         }
2739 }
2740
2741 static struct sg_table *
2742 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2743                           struct drm_i915_gem_object *obj)
2744 {
2745         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2746         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
2747         struct sg_page_iter sg_iter;
2748         unsigned long i;
2749         dma_addr_t *page_addr_list;
2750         struct sg_table *st;
2751         int ret = -ENOMEM;
2752
2753         /* Allocate a temporary list of source pages for random access. */
2754         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2755                                        sizeof(dma_addr_t));
2756         if (!page_addr_list)
2757                 return ERR_PTR(ret);
2758
2759         /* Allocate target SG list. */
2760         st = kmalloc(sizeof(*st), GFP_KERNEL);
2761         if (!st)
2762                 goto err_st_alloc;
2763
2764         ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
2765         if (ret)
2766                 goto err_sg_alloc;
2767
2768         /* Populate source page list from the object. */
2769         i = 0;
2770         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2771                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2772                 i++;
2773         }
2774
2775         /* Rotate the pages. */
2776         rotate_pages(page_addr_list,
2777                      rot_info->width_pages, rot_info->height_pages,
2778                      st);
2779
2780         DRM_DEBUG_KMS(
2781                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2782                       obj->base.size, rot_info->pitch, rot_info->height,
2783                       rot_info->pixel_format, rot_info->width_pages,
2784                       rot_info->height_pages, size_pages);
2785
2786         drm_free_large(page_addr_list);
2787
2788         return st;
2789
2790 err_sg_alloc:
2791         kfree(st);
2792 err_st_alloc:
2793         drm_free_large(page_addr_list);
2794
2795         DRM_DEBUG_KMS(
2796                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2797                       obj->base.size, ret, rot_info->pitch, rot_info->height,
2798                       rot_info->pixel_format, rot_info->width_pages,
2799                       rot_info->height_pages, size_pages);
2800         return ERR_PTR(ret);
2801 }
2802
2803 static struct sg_table *
2804 intel_partial_pages(const struct i915_ggtt_view *view,
2805                     struct drm_i915_gem_object *obj)
2806 {
2807         struct sg_table *st;
2808         struct scatterlist *sg;
2809         struct sg_page_iter obj_sg_iter;
2810         int ret = -ENOMEM;
2811
2812         st = kmalloc(sizeof(*st), GFP_KERNEL);
2813         if (!st)
2814                 goto err_st_alloc;
2815
2816         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2817         if (ret)
2818                 goto err_sg_alloc;
2819
2820         sg = st->sgl;
2821         st->nents = 0;
2822         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2823                 view->params.partial.offset)
2824         {
2825                 if (st->nents >= view->params.partial.size)
2826                         break;
2827
2828                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2829                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2830                 sg_dma_len(sg) = PAGE_SIZE;
2831
2832                 sg = sg_next(sg);
2833                 st->nents++;
2834         }
2835
2836         return st;
2837
2838 err_sg_alloc:
2839         kfree(st);
2840 err_st_alloc:
2841         return ERR_PTR(ret);
2842 }
2843
2844 static int
2845 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2846 {
2847         int ret = 0;
2848
2849         if (vma->ggtt_view.pages)
2850                 return 0;
2851
2852         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2853                 vma->ggtt_view.pages = vma->obj->pages;
2854         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2855                 vma->ggtt_view.pages =
2856                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2857         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2858                 vma->ggtt_view.pages =
2859                         intel_partial_pages(&vma->ggtt_view, vma->obj);
2860         else
2861                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2862                           vma->ggtt_view.type);
2863
2864         if (!vma->ggtt_view.pages) {
2865                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2866                           vma->ggtt_view.type);
2867                 ret = -EINVAL;
2868         } else if (IS_ERR(vma->ggtt_view.pages)) {
2869                 ret = PTR_ERR(vma->ggtt_view.pages);
2870                 vma->ggtt_view.pages = NULL;
2871                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2872                           vma->ggtt_view.type, ret);
2873         }
2874
2875         return ret;
2876 }
2877
2878 /**
2879  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2880  * @vma: VMA to map
2881  * @cache_level: mapping cache level
2882  * @flags: flags like global or local mapping
2883  *
2884  * DMA addresses are taken from the scatter-gather table of this object (or of
2885  * this VMA in case of non-default GGTT views) and PTE entries set up.
2886  * Note that DMA addresses are also the only part of the SG table we care about.
2887  */
2888 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2889                   u32 flags)
2890 {
2891         int ret;
2892         u32 bind_flags;
2893
2894         if (WARN_ON(flags == 0))
2895                 return -EINVAL;
2896
2897         bind_flags = 0;
2898         if (flags & PIN_GLOBAL)
2899                 bind_flags |= GLOBAL_BIND;
2900         if (flags & PIN_USER)
2901                 bind_flags |= LOCAL_BIND;
2902
2903         if (flags & PIN_UPDATE)
2904                 bind_flags |= vma->bound;
2905         else
2906                 bind_flags &= ~vma->bound;
2907
2908         if (bind_flags == 0)
2909                 return 0;
2910
2911         if (vma->bound == 0 && vma->vm->allocate_va_range) {
2912                 trace_i915_va_alloc(vma->vm,
2913                                     vma->node.start,
2914                                     vma->node.size,
2915                                     VM_TO_TRACE_NAME(vma->vm));
2916
2917                 /* XXX: i915_vma_pin() will fix this +- hack */
2918                 vma->pin_count++;
2919                 ret = vma->vm->allocate_va_range(vma->vm,
2920                                                  vma->node.start,
2921                                                  vma->node.size);
2922                 vma->pin_count--;
2923                 if (ret)
2924                         return ret;
2925         }
2926
2927         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2928         if (ret)
2929                 return ret;
2930
2931         vma->bound |= bind_flags;
2932
2933         return 0;
2934 }
2935
2936 /**
2937  * i915_ggtt_view_size - Get the size of a GGTT view.
2938  * @obj: Object the view is of.
2939  * @view: The view in question.
2940  *
2941  * @return The size of the GGTT view in bytes.
2942  */
2943 size_t
2944 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2945                     const struct i915_ggtt_view *view)
2946 {
2947         if (view->type == I915_GGTT_VIEW_NORMAL) {
2948                 return obj->base.size;
2949         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
2950                 return view->rotation_info.size;
2951         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2952                 return view->params.partial.size << PAGE_SHIFT;
2953         } else {
2954                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2955                 return obj->base.size;
2956         }
2957 }