drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <linux/stop_machine.h>
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_vgpu.h"
  32 #include "i915_trace.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: Global GTT views
  37  *
  38  * Background and previous state
  39  *
  40  * Historically objects could exists (be bound) in global GTT space only as
  41  * singular instances with a view representing all of the object's backing pages
  42  * in a linear fashion. This view will be called a normal view.
  43  *
  44  * To support multiple views of the same object, where the number of mapped
  45  * pages is not equal to the backing store, or where the layout of the pages
  46  * is not linear, concept of a GGTT view was added.
  47  *
  48  * One example of an alternative view is a stereo display driven by a single
  49  * image. In this case we would have a framebuffer looking like this
  50  * (2x2 pages):
  51  *
  52  *    12
  53  *    34
  54  *
  55  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  56  * rendering. In contrast, fed to the display engine would be an alternative
  57  * view which could look something like this:
  58  *
  59  *   1212
  60  *   3434
  61  *
  62  * In this example both the size and layout of pages in the alternative view is
  63  * different from the normal view.
  64  *
  65  * Implementation and usage
  66  *
  67  * GGTT views are implemented using VMAs and are distinguished via enum
  68  * i915_ggtt_view_type and struct i915_ggtt_view.
  69  *
  70  * A new flavour of core GEM functions which work with GGTT bound objects were
  71  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  72  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  73  * parameter encapsulating all metadata required to implement a view.
  74  *
  75  * As a helper for callers which are only interested in the normal view,
  76  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  77  * GEM API functions, the ones not taking the view parameter, are operating on,
  78  * or with the normal GGTT view.
  79  *
  80  * Code wanting to add or use a new GGTT view needs to:
  81  *
  82  * 1. Add a new enum with a suitable name.
  83  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  84  * 3. Add support to i915_get_vma_pages().
  85  *
  86  * New views are required to build a scatter-gather table from within the
  87  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  88  * exists for the lifetime of an VMA.
  89  *
  90  * Core API is designed to have copy semantics which means that passed in
  91  * struct i915_ggtt_view does not need to be persistent (left around after
  92  * calling the core API functions).
  93  *
  94  */
  95
  96 static inline struct i915_ggtt *
  97 i915_vm_to_ggtt(struct i915_address_space *vm)
  98 {
  99         GEM_BUG_ON(!i915_is_ggtt(vm));
 100         return container_of(vm, struct i915_ggtt, base);
 101 }
 102
 103 static int
 104 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 105
 106 const struct i915_ggtt_view i915_ggtt_view_normal = {
 107         .type = I915_GGTT_VIEW_NORMAL,
 108 };
 109 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 110         .type = I915_GGTT_VIEW_ROTATED,
 111 };
 112
 113 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
 114                                 int enable_ppgtt)
 115 {
 116         bool has_aliasing_ppgtt;
 117         bool has_full_ppgtt;
 118         bool has_full_48bit_ppgtt;
 119
 120         has_aliasing_ppgtt = INTEL_GEN(dev_priv) >= 6;
 121         has_full_ppgtt = INTEL_GEN(dev_priv) >= 7;
 122         has_full_48bit_ppgtt =
 123                 IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9;
 124
 125         if (intel_vgpu_active(dev_priv))
 126                 has_full_ppgtt = false; /* emulation is too hard */
 127
 128         if (!has_aliasing_ppgtt)
 129                 return 0;
 130
 131         /*
 132          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 133          * execlists, the sole mechanism available to submit work.
 134          */
 135         if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
 136                 return 0;
 137
 138         if (enable_ppgtt == 1)
 139                 return 1;
 140
 141         if (enable_ppgtt == 2 && has_full_ppgtt)
 142                 return 2;
 143
 144         if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
 145                 return 3;
 146
 147 #ifdef CONFIG_INTEL_IOMMU
 148         /* Disable ppgtt on SNB if VT-d is on. */
 149         if (IS_GEN6(dev_priv) && intel_iommu_gfx_mapped) {
 150                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 151                 return 0;
 152         }
 153 #endif
 154
 155         /* Early VLV doesn't have this */
 156         if (IS_VALLEYVIEW(dev_priv) && dev_priv->dev->pdev->revision < 0xb) {
 157                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 158                 return 0;
 159         }
 160
 161         if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists)
 162                 return has_full_48bit_ppgtt ? 3 : 2;
 163         else
 164                 return has_aliasing_ppgtt ? 1 : 0;
 165 }
 166
 167 static int ppgtt_bind_vma(struct i915_vma *vma,
 168                           enum i915_cache_level cache_level,
 169                           u32 unused)
 170 {
 171         u32 pte_flags = 0;
 172
 173         /* Currently applicable only to VLV */
 174         if (vma->obj->gt_ro)
 175                 pte_flags |= PTE_READ_ONLY;
 176
 177         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 178                                 cache_level, pte_flags);
 179
 180         return 0;
 181 }
 182
 183 static void ppgtt_unbind_vma(struct i915_vma *vma)
 184 {
 185         vma->vm->clear_range(vma->vm,
 186                              vma->node.start,
 187                              vma->obj->base.size,
 188                              true);
 189 }
 190
 191 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 192                                   enum i915_cache_level level,
 193                                   bool valid)
 194 {
 195         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 196         pte |= addr;
 197
 198         switch (level) {
 199         case I915_CACHE_NONE:
 200                 pte |= PPAT_UNCACHED_INDEX;
 201                 break;
 202         case I915_CACHE_WT:
 203                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 204                 break;
 205         default:
 206                 pte |= PPAT_CACHED_INDEX;
 207                 break;
 208         }
 209
 210         return pte;
 211 }
 212
 213 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
 214                                   const enum i915_cache_level level)
 215 {
 216         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 217         pde |= addr;
 218         if (level != I915_CACHE_NONE)
 219                 pde |= PPAT_CACHED_PDE_INDEX;
 220         else
 221                 pde |= PPAT_UNCACHED_INDEX;
 222         return pde;
 223 }
 224
 225 #define gen8_pdpe_encode gen8_pde_encode
 226 #define gen8_pml4e_encode gen8_pde_encode
 227
 228 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 229                                  enum i915_cache_level level,
 230                                  bool valid, u32 unused)
 231 {
 232         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 233         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 234
 235         switch (level) {
 236         case I915_CACHE_L3_LLC:
 237         case I915_CACHE_LLC:
 238                 pte |= GEN6_PTE_CACHE_LLC;
 239                 break;
 240         case I915_CACHE_NONE:
 241                 pte |= GEN6_PTE_UNCACHED;
 242                 break;
 243         default:
 244                 MISSING_CASE(level);
 245         }
 246
 247         return pte;
 248 }
 249
 250 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 251                                  enum i915_cache_level level,
 252                                  bool valid, u32 unused)
 253 {
 254         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 255         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 256
 257         switch (level) {
 258         case I915_CACHE_L3_LLC:
 259                 pte |= GEN7_PTE_CACHE_L3_LLC;
 260                 break;
 261         case I915_CACHE_LLC:
 262                 pte |= GEN6_PTE_CACHE_LLC;
 263                 break;
 264         case I915_CACHE_NONE:
 265                 pte |= GEN6_PTE_UNCACHED;
 266                 break;
 267         default:
 268                 MISSING_CASE(level);
 269         }
 270
 271         return pte;
 272 }
 273
 274 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 275                                  enum i915_cache_level level,
 276                                  bool valid, u32 flags)
 277 {
 278         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 279         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 280
 281         if (!(flags & PTE_READ_ONLY))
 282                 pte |= BYT_PTE_WRITEABLE;
 283
 284         if (level != I915_CACHE_NONE)
 285                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 286
 287         return pte;
 288 }
 289
 290 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 291                                  enum i915_cache_level level,
 292                                  bool valid, u32 unused)
 293 {
 294         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 295         pte |= HSW_PTE_ADDR_ENCODE(addr);
 296
 297         if (level != I915_CACHE_NONE)
 298                 pte |= HSW_WB_LLC_AGE3;
 299
 300         return pte;
 301 }
 302
 303 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 304                                   enum i915_cache_level level,
 305                                   bool valid, u32 unused)
 306 {
 307         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 308         pte |= HSW_PTE_ADDR_ENCODE(addr);
 309
 310         switch (level) {
 311         case I915_CACHE_NONE:
 312                 break;
 313         case I915_CACHE_WT:
 314                 pte |= HSW_WT_ELLC_LLC_AGE3;
 315                 break;
 316         default:
 317                 pte |= HSW_WB_ELLC_LLC_AGE3;
 318                 break;
 319         }
 320
 321         return pte;
 322 }
 323
 324 static int __setup_page_dma(struct drm_device *dev,
 325                             struct i915_page_dma *p, gfp_t flags)
 326 {
 327         struct device *device = &dev->pdev->dev;
 328
 329         p->page = alloc_page(flags);
 330         if (!p->page)
 331                 return -ENOMEM;
 332
 333         p->daddr = dma_map_page(device,
 334                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 335
 336         if (dma_mapping_error(device, p->daddr)) {
 337                 __free_page(p->page);
 338                 return -EINVAL;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 345 {
 346         return __setup_page_dma(dev, p, GFP_KERNEL);
 347 }
 348
 349 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 350 {
 351         if (WARN_ON(!p->page))
 352                 return;
 353
 354         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 355         __free_page(p->page);
 356         memset(p, 0, sizeof(*p));
 357 }
 358
 359 static void *kmap_page_dma(struct i915_page_dma *p)
 360 {
 361         return kmap_atomic(p->page);
 362 }
 363
 364 /* We use the flushing unmap only with ppgtt structures:
 365  * page directories, page tables and scratch pages.
 366  */
 367 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 368 {
 369         /* There are only few exceptions for gen >=6. chv and bxt.
 370          * And we are not sure about the latter so play safe for now.
 371          */
 372         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 373                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 374
 375         kunmap_atomic(vaddr);
 376 }
 377
 378 #define kmap_px(px) kmap_page_dma(px_base(px))
 379 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 380
 381 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 382 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 383 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 384 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 385
 386 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 387                           const uint64_t val)
 388 {
 389         int i;
 390         uint64_t * const vaddr = kmap_page_dma(p);
 391
 392         for (i = 0; i < 512; i++)
 393                 vaddr[i] = val;
 394
 395         kunmap_page_dma(dev, vaddr);
 396 }
 397
 398 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 399                              const uint32_t val32)
 400 {
 401         uint64_t v = val32;
 402
 403         v = v << 32 | val32;
 404
 405         fill_page_dma(dev, p, v);
 406 }
 407
 408 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
 409 {
 410         struct i915_page_scratch *sp;
 411         int ret;
 412
 413         sp = kzalloc(sizeof(*sp), GFP_KERNEL);
 414         if (sp == NULL)
 415                 return ERR_PTR(-ENOMEM);
 416
 417         ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
 418         if (ret) {
 419                 kfree(sp);
 420                 return ERR_PTR(ret);
 421         }
 422
 423         set_pages_uc(px_page(sp), 1);
 424
 425         return sp;
 426 }
 427
 428 static void free_scratch_page(struct drm_device *dev,
 429                               struct i915_page_scratch *sp)
 430 {
 431         set_pages_wb(px_page(sp), 1);
 432
 433         cleanup_px(dev, sp);
 434         kfree(sp);
 435 }
 436
 437 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 438 {
 439         struct i915_page_table *pt;
 440         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 441                 GEN8_PTES : GEN6_PTES;
 442         int ret = -ENOMEM;
 443
 444         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 445         if (!pt)
 446                 return ERR_PTR(-ENOMEM);
 447
 448         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 449                                 GFP_KERNEL);
 450
 451         if (!pt->used_ptes)
 452                 goto fail_bitmap;
 453
 454         ret = setup_px(dev, pt);
 455         if (ret)
 456                 goto fail_page_m;
 457
 458         return pt;
 459
 460 fail_page_m:
 461         kfree(pt->used_ptes);
 462 fail_bitmap:
 463         kfree(pt);
 464
 465         return ERR_PTR(ret);
 466 }
 467
 468 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 469 {
 470         cleanup_px(dev, pt);
 471         kfree(pt->used_ptes);
 472         kfree(pt);
 473 }
 474
 475 static void gen8_initialize_pt(struct i915_address_space *vm,
 476                                struct i915_page_table *pt)
 477 {
 478         gen8_pte_t scratch_pte;
 479
 480         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 481                                       I915_CACHE_LLC, true);
 482
 483         fill_px(vm->dev, pt, scratch_pte);
 484 }
 485
 486 static void gen6_initialize_pt(struct i915_address_space *vm,
 487                                struct i915_page_table *pt)
 488 {
 489         gen6_pte_t scratch_pte;
 490
 491         WARN_ON(px_dma(vm->scratch_page) == 0);
 492
 493         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
 494                                      I915_CACHE_LLC, true, 0);
 495
 496         fill32_px(vm->dev, pt, scratch_pte);
 497 }
 498
 499 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 500 {
 501         struct i915_page_directory *pd;
 502         int ret = -ENOMEM;
 503
 504         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 505         if (!pd)
 506                 return ERR_PTR(-ENOMEM);
 507
 508         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 509                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 510         if (!pd->used_pdes)
 511                 goto fail_bitmap;
 512
 513         ret = setup_px(dev, pd);
 514         if (ret)
 515                 goto fail_page_m;
 516
 517         return pd;
 518
 519 fail_page_m:
 520         kfree(pd->used_pdes);
 521 fail_bitmap:
 522         kfree(pd);
 523
 524         return ERR_PTR(ret);
 525 }
 526
 527 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 528 {
 529         if (px_page(pd)) {
 530                 cleanup_px(dev, pd);
 531                 kfree(pd->used_pdes);
 532                 kfree(pd);
 533         }
 534 }
 535
 536 static void gen8_initialize_pd(struct i915_address_space *vm,
 537                                struct i915_page_directory *pd)
 538 {
 539         gen8_pde_t scratch_pde;
 540
 541         scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
 542
 543         fill_px(vm->dev, pd, scratch_pde);
 544 }
 545
 546 static int __pdp_init(struct drm_device *dev,
 547                       struct i915_page_directory_pointer *pdp)
 548 {
 549         size_t pdpes = I915_PDPES_PER_PDP(dev);
 550
 551         pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
 552                                   sizeof(unsigned long),
 553                                   GFP_KERNEL);
 554         if (!pdp->used_pdpes)
 555                 return -ENOMEM;
 556
 557         pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
 558                                       GFP_KERNEL);
 559         if (!pdp->page_directory) {
 560                 kfree(pdp->used_pdpes);
 561                 /* the PDP might be the statically allocated top level. Keep it
 562                  * as clean as possible */
 563                 pdp->used_pdpes = NULL;
 564                 return -ENOMEM;
 565         }
 566
 567         return 0;
 568 }
 569
 570 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
 571 {
 572         kfree(pdp->used_pdpes);
 573         kfree(pdp->page_directory);
 574         pdp->page_directory = NULL;
 575 }
 576
 577 static struct
 578 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
 579 {
 580         struct i915_page_directory_pointer *pdp;
 581         int ret = -ENOMEM;
 582
 583         WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
 584
 585         pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
 586         if (!pdp)
 587                 return ERR_PTR(-ENOMEM);
 588
 589         ret = __pdp_init(dev, pdp);
 590         if (ret)
 591                 goto fail_bitmap;
 592
 593         ret = setup_px(dev, pdp);
 594         if (ret)
 595                 goto fail_page_m;
 596
 597         return pdp;
 598
 599 fail_page_m:
 600         __pdp_fini(pdp);
 601 fail_bitmap:
 602         kfree(pdp);
 603
 604         return ERR_PTR(ret);
 605 }
 606
 607 static void free_pdp(struct drm_device *dev,
 608                      struct i915_page_directory_pointer *pdp)
 609 {
 610         __pdp_fini(pdp);
 611         if (USES_FULL_48BIT_PPGTT(dev)) {
 612                 cleanup_px(dev, pdp);
 613                 kfree(pdp);
 614         }
 615 }
 616
 617 static void gen8_initialize_pdp(struct i915_address_space *vm,
 618                                 struct i915_page_directory_pointer *pdp)
 619 {
 620         gen8_ppgtt_pdpe_t scratch_pdpe;
 621
 622         scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
 623
 624         fill_px(vm->dev, pdp, scratch_pdpe);
 625 }
 626
 627 static void gen8_initialize_pml4(struct i915_address_space *vm,
 628                                  struct i915_pml4 *pml4)
 629 {
 630         gen8_ppgtt_pml4e_t scratch_pml4e;
 631
 632         scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
 633                                           I915_CACHE_LLC);
 634
 635         fill_px(vm->dev, pml4, scratch_pml4e);
 636 }
 637
 638 static void
 639 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
 640                           struct i915_page_directory_pointer *pdp,
 641                           struct i915_page_directory *pd,
 642                           int index)
 643 {
 644         gen8_ppgtt_pdpe_t *page_directorypo;
 645
 646         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
 647                 return;
 648
 649         page_directorypo = kmap_px(pdp);
 650         page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
 651         kunmap_px(ppgtt, page_directorypo);
 652 }
 653
 654 static void
 655 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
 656                                   struct i915_pml4 *pml4,
 657                                   struct i915_page_directory_pointer *pdp,
 658                                   int index)
 659 {
 660         gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
 661
 662         WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
 663         pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
 664         kunmap_px(ppgtt, pagemap);
 665 }
 666
 667 /* Broadwell Page Directory Pointer Descriptors */
 668 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 669                           unsigned entry,
 670                           dma_addr_t addr)
 671 {
 672         struct intel_engine_cs *engine = req->engine;
 673         int ret;
 674
 675         BUG_ON(entry >= 4);
 676
 677         ret = intel_ring_begin(req, 6);
 678         if (ret)
 679                 return ret;
 680
 681         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
 682         intel_ring_emit_reg(engine, GEN8_RING_PDP_UDW(engine, entry));
 683         intel_ring_emit(engine, upper_32_bits(addr));
 684         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
 685         intel_ring_emit_reg(engine, GEN8_RING_PDP_LDW(engine, entry));
 686         intel_ring_emit(engine, lower_32_bits(addr));
 687         intel_ring_advance(engine);
 688
 689         return 0;
 690 }
 691
 692 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
 693                                  struct drm_i915_gem_request *req)
 694 {
 695         int i, ret;
 696
 697         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 698                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 699
 700                 ret = gen8_write_pdp(req, i, pd_daddr);
 701                 if (ret)
 702                         return ret;
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
 709                               struct drm_i915_gem_request *req)
 710 {
 711         return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
 712 }
 713
 714 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
 715                                        struct i915_page_directory_pointer *pdp,
 716                                        uint64_t start,
 717                                        uint64_t length,
 718                                        gen8_pte_t scratch_pte)
 719 {
 720         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 721         gen8_pte_t *pt_vaddr;
 722         unsigned pdpe = gen8_pdpe_index(start);
 723         unsigned pde = gen8_pde_index(start);
 724         unsigned pte = gen8_pte_index(start);
 725         unsigned num_entries = length >> PAGE_SHIFT;
 726         unsigned last_pte, i;
 727
 728         if (WARN_ON(!pdp))
 729                 return;
 730
 731         while (num_entries) {
 732                 struct i915_page_directory *pd;
 733                 struct i915_page_table *pt;
 734
 735                 if (WARN_ON(!pdp->page_directory[pdpe]))
 736                         break;
 737
 738                 pd = pdp->page_directory[pdpe];
 739
 740                 if (WARN_ON(!pd->page_table[pde]))
 741                         break;
 742
 743                 pt = pd->page_table[pde];
 744
 745                 if (WARN_ON(!px_page(pt)))
 746                         break;
 747
 748                 last_pte = pte + num_entries;
 749                 if (last_pte > GEN8_PTES)
 750                         last_pte = GEN8_PTES;
 751
 752                 pt_vaddr = kmap_px(pt);
 753
 754                 for (i = pte; i < last_pte; i++) {
 755                         pt_vaddr[i] = scratch_pte;
 756                         num_entries--;
 757                 }
 758
 759                 kunmap_px(ppgtt, pt_vaddr);
 760
 761                 pte = 0;
 762                 if (++pde == I915_PDES) {
 763                         if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 764                                 break;
 765                         pde = 0;
 766                 }
 767         }
 768 }
 769
 770 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 771                                    uint64_t start,
 772                                    uint64_t length,
 773                                    bool use_scratch)
 774 {
 775         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 776         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
 777                                                  I915_CACHE_LLC, use_scratch);
 778
 779         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 780                 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
 781                                            scratch_pte);
 782         } else {
 783                 uint64_t pml4e;
 784                 struct i915_page_directory_pointer *pdp;
 785
 786                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 787                         gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
 788                                                    scratch_pte);
 789                 }
 790         }
 791 }
 792
 793 static void
 794 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
 795                               struct i915_page_directory_pointer *pdp,
 796                               struct sg_page_iter *sg_iter,
 797                               uint64_t start,
 798                               enum i915_cache_level cache_level)
 799 {
 800         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 801         gen8_pte_t *pt_vaddr;
 802         unsigned pdpe = gen8_pdpe_index(start);
 803         unsigned pde = gen8_pde_index(start);
 804         unsigned pte = gen8_pte_index(start);
 805
 806         pt_vaddr = NULL;
 807
 808         while (__sg_page_iter_next(sg_iter)) {
 809                 if (pt_vaddr == NULL) {
 810                         struct i915_page_directory *pd = pdp->page_directory[pdpe];
 811                         struct i915_page_table *pt = pd->page_table[pde];
 812                         pt_vaddr = kmap_px(pt);
 813                 }
 814
 815                 pt_vaddr[pte] =
 816                         gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
 817                                         cache_level, true);
 818                 if (++pte == GEN8_PTES) {
 819                         kunmap_px(ppgtt, pt_vaddr);
 820                         pt_vaddr = NULL;
 821                         if (++pde == I915_PDES) {
 822                                 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
 823                                         break;
 824                                 pde = 0;
 825                         }
 826                         pte = 0;
 827                 }
 828         }
 829
 830         if (pt_vaddr)
 831                 kunmap_px(ppgtt, pt_vaddr);
 832 }
 833
 834 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 835                                       struct sg_table *pages,
 836                                       uint64_t start,
 837                                       enum i915_cache_level cache_level,
 838                                       u32 unused)
 839 {
 840         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 841         struct sg_page_iter sg_iter;
 842
 843         __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
 844
 845         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
 846                 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
 847                                               cache_level);
 848         } else {
 849                 struct i915_page_directory_pointer *pdp;
 850                 uint64_t pml4e;
 851                 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
 852
 853                 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, pml4e) {
 854                         gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
 855                                                       start, cache_level);
 856                 }
 857         }
 858 }
 859
 860 static void gen8_free_page_tables(struct drm_device *dev,
 861                                   struct i915_page_directory *pd)
 862 {
 863         int i;
 864
 865         if (!px_page(pd))
 866                 return;
 867
 868         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 869                 if (WARN_ON(!pd->page_table[i]))
 870                         continue;
 871
 872                 free_pt(dev, pd->page_table[i]);
 873                 pd->page_table[i] = NULL;
 874         }
 875 }
 876
 877 static int gen8_init_scratch(struct i915_address_space *vm)
 878 {
 879         struct drm_device *dev = vm->dev;
 880         int ret;
 881
 882         vm->scratch_page = alloc_scratch_page(dev);
 883         if (IS_ERR(vm->scratch_page))
 884                 return PTR_ERR(vm->scratch_page);
 885
 886         vm->scratch_pt = alloc_pt(dev);
 887         if (IS_ERR(vm->scratch_pt)) {
 888                 ret = PTR_ERR(vm->scratch_pt);
 889                 goto free_scratch_page;
 890         }
 891
 892         vm->scratch_pd = alloc_pd(dev);
 893         if (IS_ERR(vm->scratch_pd)) {
 894                 ret = PTR_ERR(vm->scratch_pd);
 895                 goto free_pt;
 896         }
 897
 898         if (USES_FULL_48BIT_PPGTT(dev)) {
 899                 vm->scratch_pdp = alloc_pdp(dev);
 900                 if (IS_ERR(vm->scratch_pdp)) {
 901                         ret = PTR_ERR(vm->scratch_pdp);
 902                         goto free_pd;
 903                 }
 904         }
 905
 906         gen8_initialize_pt(vm, vm->scratch_pt);
 907         gen8_initialize_pd(vm, vm->scratch_pd);
 908         if (USES_FULL_48BIT_PPGTT(dev))
 909                 gen8_initialize_pdp(vm, vm->scratch_pdp);
 910
 911         return 0;
 912
 913 free_pd:
 914         free_pd(dev, vm->scratch_pd);
 915 free_pt:
 916         free_pt(dev, vm->scratch_pt);
 917 free_scratch_page:
 918         free_scratch_page(dev, vm->scratch_page);
 919
 920         return ret;
 921 }
 922
 923 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
 924 {
 925         enum vgt_g2v_type msg;
 926         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
 927         int i;
 928
 929         if (USES_FULL_48BIT_PPGTT(dev_priv)) {
 930                 u64 daddr = px_dma(&ppgtt->pml4);
 931
 932                 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
 933                 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
 934
 935                 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
 936                                 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
 937         } else {
 938                 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 939                         u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
 940
 941                         I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
 942                         I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
 943                 }
 944
 945                 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
 946                                 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
 947         }
 948
 949         I915_WRITE(vgtif_reg(g2v_notify), msg);
 950
 951         return 0;
 952 }
 953
 954 static void gen8_free_scratch(struct i915_address_space *vm)
 955 {
 956         struct drm_device *dev = vm->dev;
 957
 958         if (USES_FULL_48BIT_PPGTT(dev))
 959                 free_pdp(dev, vm->scratch_pdp);
 960         free_pd(dev, vm->scratch_pd);
 961         free_pt(dev, vm->scratch_pt);
 962         free_scratch_page(dev, vm->scratch_page);
 963 }
 964
 965 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
 966                                     struct i915_page_directory_pointer *pdp)
 967 {
 968         int i;
 969
 970         for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
 971                 if (WARN_ON(!pdp->page_directory[i]))
 972                         continue;
 973
 974                 gen8_free_page_tables(dev, pdp->page_directory[i]);
 975                 free_pd(dev, pdp->page_directory[i]);
 976         }
 977
 978         free_pdp(dev, pdp);
 979 }
 980
 981 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
 982 {
 983         int i;
 984
 985         for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
 986                 if (WARN_ON(!ppgtt->pml4.pdps[i]))
 987                         continue;
 988
 989                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
 990         }
 991
 992         cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
 993 }
 994
 995 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 996 {
 997         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
 998
 999         if (intel_vgpu_active(to_i915(vm->dev)))
1000                 gen8_ppgtt_notify_vgt(ppgtt, false);
1001
1002         if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
1003                 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
1004         else
1005                 gen8_ppgtt_cleanup_4lvl(ppgtt);
1006
1007         gen8_free_scratch(vm);
1008 }
1009
1010 /**
1011  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1012  * @vm: Master vm structure.
1013  * @pd: Page directory for this address range.
1014  * @start:      Starting virtual address to begin allocations.
1015  * @length:     Size of the allocations.
1016  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
1017  *              caller to free on error.
1018  *
1019  * Allocate the required number of page tables. Extremely similar to
1020  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1021  * the page directory boundary (instead of the page directory pointer). That
1022  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1023  * possible, and likely that the caller will need to use multiple calls of this
1024  * function to achieve the appropriate allocation.
1025  *
1026  * Return: 0 if success; negative error code otherwise.
1027  */
1028 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1029                                      struct i915_page_directory *pd,
1030                                      uint64_t start,
1031                                      uint64_t length,
1032                                      unsigned long *new_pts)
1033 {
1034         struct drm_device *dev = vm->dev;
1035         struct i915_page_table *pt;
1036         uint32_t pde;
1037
1038         gen8_for_each_pde(pt, pd, start, length, pde) {
1039                 /* Don't reallocate page tables */
1040                 if (test_bit(pde, pd->used_pdes)) {
1041                         /* Scratch is never allocated this way */
1042                         WARN_ON(pt == vm->scratch_pt);
1043                         continue;
1044                 }
1045
1046                 pt = alloc_pt(dev);
1047                 if (IS_ERR(pt))
1048                         goto unwind_out;
1049
1050                 gen8_initialize_pt(vm, pt);
1051                 pd->page_table[pde] = pt;
1052                 __set_bit(pde, new_pts);
1053                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1054         }
1055
1056         return 0;
1057
1058 unwind_out:
1059         for_each_set_bit(pde, new_pts, I915_PDES)
1060                 free_pt(dev, pd->page_table[pde]);
1061
1062         return -ENOMEM;
1063 }
1064
1065 /**
1066  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1067  * @vm: Master vm structure.
1068  * @pdp:        Page directory pointer for this address range.
1069  * @start:      Starting virtual address to begin allocations.
1070  * @length:     Size of the allocations.
1071  * @new_pds:    Bitmap set by function with new allocations. Likely used by the
1072  *              caller to free on error.
1073  *
1074  * Allocate the required number of page directories starting at the pde index of
1075  * @start, and ending at the pde index @start + @length. This function will skip
1076  * over already allocated page directories within the range, and only allocate
1077  * new ones, setting the appropriate pointer within the pdp as well as the
1078  * correct position in the bitmap @new_pds.
1079  *
1080  * The function will only allocate the pages within the range for a give page
1081  * directory pointer. In other words, if @start + @length straddles a virtually
1082  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1083  * required by the caller, This is not currently possible, and the BUG in the
1084  * code will prevent it.
1085  *
1086  * Return: 0 if success; negative error code otherwise.
1087  */
1088 static int
1089 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1090                                   struct i915_page_directory_pointer *pdp,
1091                                   uint64_t start,
1092                                   uint64_t length,
1093                                   unsigned long *new_pds)
1094 {
1095         struct drm_device *dev = vm->dev;
1096         struct i915_page_directory *pd;
1097         uint32_t pdpe;
1098         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1099
1100         WARN_ON(!bitmap_empty(new_pds, pdpes));
1101
1102         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1103                 if (test_bit(pdpe, pdp->used_pdpes))
1104                         continue;
1105
1106                 pd = alloc_pd(dev);
1107                 if (IS_ERR(pd))
1108                         goto unwind_out;
1109
1110                 gen8_initialize_pd(vm, pd);
1111                 pdp->page_directory[pdpe] = pd;
1112                 __set_bit(pdpe, new_pds);
1113                 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1114         }
1115
1116         return 0;
1117
1118 unwind_out:
1119         for_each_set_bit(pdpe, new_pds, pdpes)
1120                 free_pd(dev, pdp->page_directory[pdpe]);
1121
1122         return -ENOMEM;
1123 }
1124
1125 /**
1126  * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1127  * @vm: Master vm structure.
1128  * @pml4:       Page map level 4 for this address range.
1129  * @start:      Starting virtual address to begin allocations.
1130  * @length:     Size of the allocations.
1131  * @new_pdps:   Bitmap set by function with new allocations. Likely used by the
1132  *              caller to free on error.
1133  *
1134  * Allocate the required number of page directory pointers. Extremely similar to
1135  * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1136  * The main difference is here we are limited by the pml4 boundary (instead of
1137  * the page directory pointer).
1138  *
1139  * Return: 0 if success; negative error code otherwise.
1140  */
1141 static int
1142 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1143                                   struct i915_pml4 *pml4,
1144                                   uint64_t start,
1145                                   uint64_t length,
1146                                   unsigned long *new_pdps)
1147 {
1148         struct drm_device *dev = vm->dev;
1149         struct i915_page_directory_pointer *pdp;
1150         uint32_t pml4e;
1151
1152         WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1153
1154         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1155                 if (!test_bit(pml4e, pml4->used_pml4es)) {
1156                         pdp = alloc_pdp(dev);
1157                         if (IS_ERR(pdp))
1158                                 goto unwind_out;
1159
1160                         gen8_initialize_pdp(vm, pdp);
1161                         pml4->pdps[pml4e] = pdp;
1162                         __set_bit(pml4e, new_pdps);
1163                         trace_i915_page_directory_pointer_entry_alloc(vm,
1164                                                                       pml4e,
1165                                                                       start,
1166                                                                       GEN8_PML4E_SHIFT);
1167                 }
1168         }
1169
1170         return 0;
1171
1172 unwind_out:
1173         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1174                 free_pdp(dev, pml4->pdps[pml4e]);
1175
1176         return -ENOMEM;
1177 }
1178
1179 static void
1180 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1181 {
1182         kfree(new_pts);
1183         kfree(new_pds);
1184 }
1185
1186 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1187  * of these are based on the number of PDPEs in the system.
1188  */
1189 static
1190 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1191                                          unsigned long **new_pts,
1192                                          uint32_t pdpes)
1193 {
1194         unsigned long *pds;
1195         unsigned long *pts;
1196
1197         pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1198         if (!pds)
1199                 return -ENOMEM;
1200
1201         pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1202                       GFP_TEMPORARY);
1203         if (!pts)
1204                 goto err_out;
1205
1206         *new_pds = pds;
1207         *new_pts = pts;
1208
1209         return 0;
1210
1211 err_out:
1212         free_gen8_temp_bitmaps(pds, pts);
1213         return -ENOMEM;
1214 }
1215
1216 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1217  * the page table structures, we mark them dirty so that
1218  * context switching/execlist queuing code takes extra steps
1219  * to ensure that tlbs are flushed.
1220  */
1221 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1222 {
1223         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1224 }
1225
1226 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1227                                     struct i915_page_directory_pointer *pdp,
1228                                     uint64_t start,
1229                                     uint64_t length)
1230 {
1231         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1232         unsigned long *new_page_dirs, *new_page_tables;
1233         struct drm_device *dev = vm->dev;
1234         struct i915_page_directory *pd;
1235         const uint64_t orig_start = start;
1236         const uint64_t orig_length = length;
1237         uint32_t pdpe;
1238         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1239         int ret;
1240
1241         /* Wrap is never okay since we can only represent 48b, and we don't
1242          * actually use the other side of the canonical address space.
1243          */
1244         if (WARN_ON(start + length < start))
1245                 return -ENODEV;
1246
1247         if (WARN_ON(start + length > vm->total))
1248                 return -ENODEV;
1249
1250         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1251         if (ret)
1252                 return ret;
1253
1254         /* Do the allocations first so we can easily bail out */
1255         ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1256                                                 new_page_dirs);
1257         if (ret) {
1258                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1259                 return ret;
1260         }
1261
1262         /* For every page directory referenced, allocate page tables */
1263         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1264                 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1265                                                 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1266                 if (ret)
1267                         goto err_out;
1268         }
1269
1270         start = orig_start;
1271         length = orig_length;
1272
1273         /* Allocations have completed successfully, so set the bitmaps, and do
1274          * the mappings. */
1275         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1276                 gen8_pde_t *const page_directory = kmap_px(pd);
1277                 struct i915_page_table *pt;
1278                 uint64_t pd_len = length;
1279                 uint64_t pd_start = start;
1280                 uint32_t pde;
1281
1282                 /* Every pd should be allocated, we just did that above. */
1283                 WARN_ON(!pd);
1284
1285                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1286                         /* Same reasoning as pd */
1287                         WARN_ON(!pt);
1288                         WARN_ON(!pd_len);
1289                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
1290
1291                         /* Set our used ptes within the page table */
1292                         bitmap_set(pt->used_ptes,
1293                                    gen8_pte_index(pd_start),
1294                                    gen8_pte_count(pd_start, pd_len));
1295
1296                         /* Our pde is now pointing to the pagetable, pt */
1297                         __set_bit(pde, pd->used_pdes);
1298
1299                         /* Map the PDE to the page table */
1300                         page_directory[pde] = gen8_pde_encode(px_dma(pt),
1301                                                               I915_CACHE_LLC);
1302                         trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1303                                                         gen8_pte_index(start),
1304                                                         gen8_pte_count(start, length),
1305                                                         GEN8_PTES);
1306
1307                         /* NB: We haven't yet mapped ptes to pages. At this
1308                          * point we're still relying on insert_entries() */
1309                 }
1310
1311                 kunmap_px(ppgtt, page_directory);
1312                 __set_bit(pdpe, pdp->used_pdpes);
1313                 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1314         }
1315
1316         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1317         mark_tlbs_dirty(ppgtt);
1318         return 0;
1319
1320 err_out:
1321         while (pdpe--) {
1322                 unsigned long temp;
1323
1324                 for_each_set_bit(temp, new_page_tables + pdpe *
1325                                 BITS_TO_LONGS(I915_PDES), I915_PDES)
1326                         free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1327         }
1328
1329         for_each_set_bit(pdpe, new_page_dirs, pdpes)
1330                 free_pd(dev, pdp->page_directory[pdpe]);
1331
1332         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1333         mark_tlbs_dirty(ppgtt);
1334         return ret;
1335 }
1336
1337 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1338                                     struct i915_pml4 *pml4,
1339                                     uint64_t start,
1340                                     uint64_t length)
1341 {
1342         DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1343         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1344         struct i915_page_directory_pointer *pdp;
1345         uint64_t pml4e;
1346         int ret = 0;
1347
1348         /* Do the pml4 allocations first, so we don't need to track the newly
1349          * allocated tables below the pdp */
1350         bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1351
1352         /* The pagedirectory and pagetable allocations are done in the shared 3
1353          * and 4 level code. Just allocate the pdps.
1354          */
1355         ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1356                                                 new_pdps);
1357         if (ret)
1358                 return ret;
1359
1360         WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1361              "The allocation has spanned more than 512GB. "
1362              "It is highly likely this is incorrect.");
1363
1364         gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1365                 WARN_ON(!pdp);
1366
1367                 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1368                 if (ret)
1369                         goto err_out;
1370
1371                 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1372         }
1373
1374         bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1375                   GEN8_PML4ES_PER_PML4);
1376
1377         return 0;
1378
1379 err_out:
1380         for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1381                 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1382
1383         return ret;
1384 }
1385
1386 static int gen8_alloc_va_range(struct i915_address_space *vm,
1387                                uint64_t start, uint64_t length)
1388 {
1389         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1390
1391         if (USES_FULL_48BIT_PPGTT(vm->dev))
1392                 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1393         else
1394                 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1395 }
1396
1397 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1398                           uint64_t start, uint64_t length,
1399                           gen8_pte_t scratch_pte,
1400                           struct seq_file *m)
1401 {
1402         struct i915_page_directory *pd;
1403         uint32_t pdpe;
1404
1405         gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1406                 struct i915_page_table *pt;
1407                 uint64_t pd_len = length;
1408                 uint64_t pd_start = start;
1409                 uint32_t pde;
1410
1411                 if (!test_bit(pdpe, pdp->used_pdpes))
1412                         continue;
1413
1414                 seq_printf(m, "\tPDPE #%d\n", pdpe);
1415                 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1416                         uint32_t  pte;
1417                         gen8_pte_t *pt_vaddr;
1418
1419                         if (!test_bit(pde, pd->used_pdes))
1420                                 continue;
1421
1422                         pt_vaddr = kmap_px(pt);
1423                         for (pte = 0; pte < GEN8_PTES; pte += 4) {
1424                                 uint64_t va =
1425                                         (pdpe << GEN8_PDPE_SHIFT) |
1426                                         (pde << GEN8_PDE_SHIFT) |
1427                                         (pte << GEN8_PTE_SHIFT);
1428                                 int i;
1429                                 bool found = false;
1430
1431                                 for (i = 0; i < 4; i++)
1432                                         if (pt_vaddr[pte + i] != scratch_pte)
1433                                                 found = true;
1434                                 if (!found)
1435                                         continue;
1436
1437                                 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1438                                 for (i = 0; i < 4; i++) {
1439                                         if (pt_vaddr[pte + i] != scratch_pte)
1440                                                 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1441                                         else
1442                                                 seq_puts(m, "  SCRATCH ");
1443                                 }
1444                                 seq_puts(m, "\n");
1445                         }
1446                         /* don't use kunmap_px, it could trigger
1447                          * an unnecessary flush.
1448                          */
1449                         kunmap_atomic(pt_vaddr);
1450                 }
1451         }
1452 }
1453
1454 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1455 {
1456         struct i915_address_space *vm = &ppgtt->base;
1457         uint64_t start = ppgtt->base.start;
1458         uint64_t length = ppgtt->base.total;
1459         gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1460                                                  I915_CACHE_LLC, true);
1461
1462         if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1463                 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1464         } else {
1465                 uint64_t pml4e;
1466                 struct i915_pml4 *pml4 = &ppgtt->pml4;
1467                 struct i915_page_directory_pointer *pdp;
1468
1469                 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1470                         if (!test_bit(pml4e, pml4->used_pml4es))
1471                                 continue;
1472
1473                         seq_printf(m, "    PML4E #%llu\n", pml4e);
1474                         gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1475                 }
1476         }
1477 }
1478
1479 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1480 {
1481         unsigned long *new_page_dirs, *new_page_tables;
1482         uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1483         int ret;
1484
1485         /* We allocate temp bitmap for page tables for no gain
1486          * but as this is for init only, lets keep the things simple
1487          */
1488         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1489         if (ret)
1490                 return ret;
1491
1492         /* Allocate for all pdps regardless of how the ppgtt
1493          * was defined.
1494          */
1495         ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1496                                                 0, 1ULL << 32,
1497                                                 new_page_dirs);
1498         if (!ret)
1499                 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1500
1501         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1502
1503         return ret;
1504 }
1505
1506 /*
1507  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1508  * with a net effect resembling a 2-level page table in normal x86 terms. Each
1509  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1510  * space.
1511  *
1512  */
1513 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1514 {
1515         int ret;
1516
1517         ret = gen8_init_scratch(&ppgtt->base);
1518         if (ret)
1519                 return ret;
1520
1521         ppgtt->base.start = 0;
1522         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1523         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1524         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1525         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1526         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1527         ppgtt->base.bind_vma = ppgtt_bind_vma;
1528         ppgtt->debug_dump = gen8_dump_ppgtt;
1529
1530         if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1531                 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1532                 if (ret)
1533                         goto free_scratch;
1534
1535                 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1536
1537                 ppgtt->base.total = 1ULL << 48;
1538                 ppgtt->switch_mm = gen8_48b_mm_switch;
1539         } else {
1540                 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1541                 if (ret)
1542                         goto free_scratch;
1543
1544                 ppgtt->base.total = 1ULL << 32;
1545                 ppgtt->switch_mm = gen8_legacy_mm_switch;
1546                 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1547                                                               0, 0,
1548                                                               GEN8_PML4E_SHIFT);
1549
1550                 if (intel_vgpu_active(to_i915(ppgtt->base.dev))) {
1551                         ret = gen8_preallocate_top_level_pdps(ppgtt);
1552                         if (ret)
1553                                 goto free_scratch;
1554                 }
1555         }
1556
1557         if (intel_vgpu_active(to_i915(ppgtt->base.dev)))
1558                 gen8_ppgtt_notify_vgt(ppgtt, true);
1559
1560         return 0;
1561
1562 free_scratch:
1563         gen8_free_scratch(&ppgtt->base);
1564         return ret;
1565 }
1566
1567 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1568 {
1569         struct i915_address_space *vm = &ppgtt->base;
1570         struct i915_page_table *unused;
1571         gen6_pte_t scratch_pte;
1572         uint32_t pd_entry;
1573         uint32_t  pte, pde;
1574         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1575
1576         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1577                                      I915_CACHE_LLC, true, 0);
1578
1579         gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
1580                 u32 expected;
1581                 gen6_pte_t *pt_vaddr;
1582                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1583                 pd_entry = readl(ppgtt->pd_addr + pde);
1584                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1585
1586                 if (pd_entry != expected)
1587                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1588                                    pde,
1589                                    pd_entry,
1590                                    expected);
1591                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1592
1593                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1594
1595                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1596                         unsigned long va =
1597                                 (pde * PAGE_SIZE * GEN6_PTES) +
1598                                 (pte * PAGE_SIZE);
1599                         int i;
1600                         bool found = false;
1601                         for (i = 0; i < 4; i++)
1602                                 if (pt_vaddr[pte + i] != scratch_pte)
1603                                         found = true;
1604                         if (!found)
1605                                 continue;
1606
1607                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1608                         for (i = 0; i < 4; i++) {
1609                                 if (pt_vaddr[pte + i] != scratch_pte)
1610                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1611                                 else
1612                                         seq_puts(m, "  SCRATCH ");
1613                         }
1614                         seq_puts(m, "\n");
1615                 }
1616                 kunmap_px(ppgtt, pt_vaddr);
1617         }
1618 }
1619
1620 /* Write pde (index) from the page directory @pd to the page table @pt */
1621 static void gen6_write_pde(struct i915_page_directory *pd,
1622                             const int pde, struct i915_page_table *pt)
1623 {
1624         /* Caller needs to make sure the write completes if necessary */
1625         struct i915_hw_ppgtt *ppgtt =
1626                 container_of(pd, struct i915_hw_ppgtt, pd);
1627         u32 pd_entry;
1628
1629         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1630         pd_entry |= GEN6_PDE_VALID;
1631
1632         writel(pd_entry, ppgtt->pd_addr + pde);
1633 }
1634
1635 /* Write all the page tables found in the ppgtt structure to incrementing page
1636  * directories. */
1637 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1638                                   struct i915_page_directory *pd,
1639                                   uint32_t start, uint32_t length)
1640 {
1641         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1642         struct i915_page_table *pt;
1643         uint32_t pde;
1644
1645         gen6_for_each_pde(pt, pd, start, length, pde)
1646                 gen6_write_pde(pd, pde, pt);
1647
1648         /* Make sure write is complete before other code can use this page
1649          * table. Also require for WC mapped PTEs */
1650         readl(ggtt->gsm);
1651 }
1652
1653 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1654 {
1655         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1656
1657         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1658 }
1659
1660 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1661                          struct drm_i915_gem_request *req)
1662 {
1663         struct intel_engine_cs *engine = req->engine;
1664         int ret;
1665
1666         /* NB: TLBs must be flushed and invalidated before a switch */
1667         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1668         if (ret)
1669                 return ret;
1670
1671         ret = intel_ring_begin(req, 6);
1672         if (ret)
1673                 return ret;
1674
1675         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1676         intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1677         intel_ring_emit(engine, PP_DIR_DCLV_2G);
1678         intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1679         intel_ring_emit(engine, get_pd_offset(ppgtt));
1680         intel_ring_emit(engine, MI_NOOP);
1681         intel_ring_advance(engine);
1682
1683         return 0;
1684 }
1685
1686 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1687                           struct drm_i915_gem_request *req)
1688 {
1689         struct intel_engine_cs *engine = req->engine;
1690         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1691
1692         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1693         I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1694         return 0;
1695 }
1696
1697 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1698                           struct drm_i915_gem_request *req)
1699 {
1700         struct intel_engine_cs *engine = req->engine;
1701         int ret;
1702
1703         /* NB: TLBs must be flushed and invalidated before a switch */
1704         ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1705         if (ret)
1706                 return ret;
1707
1708         ret = intel_ring_begin(req, 6);
1709         if (ret)
1710                 return ret;
1711
1712         intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(2));
1713         intel_ring_emit_reg(engine, RING_PP_DIR_DCLV(engine));
1714         intel_ring_emit(engine, PP_DIR_DCLV_2G);
1715         intel_ring_emit_reg(engine, RING_PP_DIR_BASE(engine));
1716         intel_ring_emit(engine, get_pd_offset(ppgtt));
1717         intel_ring_emit(engine, MI_NOOP);
1718         intel_ring_advance(engine);
1719
1720         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1721         if (engine->id != RCS) {
1722                 ret = engine->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1723                 if (ret)
1724                         return ret;
1725         }
1726
1727         return 0;
1728 }
1729
1730 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1731                           struct drm_i915_gem_request *req)
1732 {
1733         struct intel_engine_cs *engine = req->engine;
1734         struct drm_device *dev = ppgtt->base.dev;
1735         struct drm_i915_private *dev_priv = to_i915(dev);
1736
1737
1738         I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1739         I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1740
1741         POSTING_READ(RING_PP_DIR_DCLV(engine));
1742
1743         return 0;
1744 }
1745
1746 static void gen8_ppgtt_enable(struct drm_device *dev)
1747 {
1748         struct drm_i915_private *dev_priv = to_i915(dev);
1749         struct intel_engine_cs *engine;
1750
1751         for_each_engine(engine, dev_priv) {
1752                 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1753                 I915_WRITE(RING_MODE_GEN7(engine),
1754                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1755         }
1756 }
1757
1758 static void gen7_ppgtt_enable(struct drm_device *dev)
1759 {
1760         struct drm_i915_private *dev_priv = to_i915(dev);
1761         struct intel_engine_cs *engine;
1762         uint32_t ecochk, ecobits;
1763
1764         ecobits = I915_READ(GAC_ECO_BITS);
1765         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1766
1767         ecochk = I915_READ(GAM_ECOCHK);
1768         if (IS_HASWELL(dev)) {
1769                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1770         } else {
1771                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1772                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1773         }
1774         I915_WRITE(GAM_ECOCHK, ecochk);
1775
1776         for_each_engine(engine, dev_priv) {
1777                 /* GFX_MODE is per-ring on gen7+ */
1778                 I915_WRITE(RING_MODE_GEN7(engine),
1779                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1780         }
1781 }
1782
1783 static void gen6_ppgtt_enable(struct drm_device *dev)
1784 {
1785         struct drm_i915_private *dev_priv = to_i915(dev);
1786         uint32_t ecochk, gab_ctl, ecobits;
1787
1788         ecobits = I915_READ(GAC_ECO_BITS);
1789         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1790                    ECOBITS_PPGTT_CACHE64B);
1791
1792         gab_ctl = I915_READ(GAB_CTL);
1793         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1794
1795         ecochk = I915_READ(GAM_ECOCHK);
1796         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1797
1798         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1799 }
1800
1801 /* PPGTT support for Sandybdrige/Gen6 and later */
1802 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1803                                    uint64_t start,
1804                                    uint64_t length,
1805                                    bool use_scratch)
1806 {
1807         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1808         gen6_pte_t *pt_vaddr, scratch_pte;
1809         unsigned first_entry = start >> PAGE_SHIFT;
1810         unsigned num_entries = length >> PAGE_SHIFT;
1811         unsigned act_pt = first_entry / GEN6_PTES;
1812         unsigned first_pte = first_entry % GEN6_PTES;
1813         unsigned last_pte, i;
1814
1815         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1816                                      I915_CACHE_LLC, true, 0);
1817
1818         while (num_entries) {
1819                 last_pte = first_pte + num_entries;
1820                 if (last_pte > GEN6_PTES)
1821                         last_pte = GEN6_PTES;
1822
1823                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1824
1825                 for (i = first_pte; i < last_pte; i++)
1826                         pt_vaddr[i] = scratch_pte;
1827
1828                 kunmap_px(ppgtt, pt_vaddr);
1829
1830                 num_entries -= last_pte - first_pte;
1831                 first_pte = 0;
1832                 act_pt++;
1833         }
1834 }
1835
1836 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1837                                       struct sg_table *pages,
1838                                       uint64_t start,
1839                                       enum i915_cache_level cache_level, u32 flags)
1840 {
1841         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1842         unsigned first_entry = start >> PAGE_SHIFT;
1843         unsigned act_pt = first_entry / GEN6_PTES;
1844         unsigned act_pte = first_entry % GEN6_PTES;
1845         gen6_pte_t *pt_vaddr = NULL;
1846         struct sgt_iter sgt_iter;
1847         dma_addr_t addr;
1848
1849         for_each_sgt_dma(addr, sgt_iter, pages) {
1850                 if (pt_vaddr == NULL)
1851                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1852
1853                 pt_vaddr[act_pte] =
1854                         vm->pte_encode(addr, cache_level, true, flags);
1855
1856                 if (++act_pte == GEN6_PTES) {
1857                         kunmap_px(ppgtt, pt_vaddr);
1858                         pt_vaddr = NULL;
1859                         act_pt++;
1860                         act_pte = 0;
1861                 }
1862         }
1863
1864         if (pt_vaddr)
1865                 kunmap_px(ppgtt, pt_vaddr);
1866 }
1867
1868 static int gen6_alloc_va_range(struct i915_address_space *vm,
1869                                uint64_t start_in, uint64_t length_in)
1870 {
1871         DECLARE_BITMAP(new_page_tables, I915_PDES);
1872         struct drm_device *dev = vm->dev;
1873         struct drm_i915_private *dev_priv = to_i915(dev);
1874         struct i915_ggtt *ggtt = &dev_priv->ggtt;
1875         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1876         struct i915_page_table *pt;
1877         uint32_t start, length, start_save, length_save;
1878         uint32_t pde;
1879         int ret;
1880
1881         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1882                 return -ENODEV;
1883
1884         start = start_save = start_in;
1885         length = length_save = length_in;
1886
1887         bitmap_zero(new_page_tables, I915_PDES);
1888
1889         /* The allocation is done in two stages so that we can bail out with
1890          * minimal amount of pain. The first stage finds new page tables that
1891          * need allocation. The second stage marks use ptes within the page
1892          * tables.
1893          */
1894         gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1895                 if (pt != vm->scratch_pt) {
1896                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1897                         continue;
1898                 }
1899
1900                 /* We've already allocated a page table */
1901                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1902
1903                 pt = alloc_pt(dev);
1904                 if (IS_ERR(pt)) {
1905                         ret = PTR_ERR(pt);
1906                         goto unwind_out;
1907                 }
1908
1909                 gen6_initialize_pt(vm, pt);
1910
1911                 ppgtt->pd.page_table[pde] = pt;
1912                 __set_bit(pde, new_page_tables);
1913                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1914         }
1915
1916         start = start_save;
1917         length = length_save;
1918
1919         gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1920                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1921
1922                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1923                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1924                            gen6_pte_count(start, length));
1925
1926                 if (__test_and_clear_bit(pde, new_page_tables))
1927                         gen6_write_pde(&ppgtt->pd, pde, pt);
1928
1929                 trace_i915_page_table_entry_map(vm, pde, pt,
1930                                          gen6_pte_index(start),
1931                                          gen6_pte_count(start, length),
1932                                          GEN6_PTES);
1933                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1934                                 GEN6_PTES);
1935         }
1936
1937         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1938
1939         /* Make sure write is complete before other code can use this page
1940          * table. Also require for WC mapped PTEs */
1941         readl(ggtt->gsm);
1942
1943         mark_tlbs_dirty(ppgtt);
1944         return 0;
1945
1946 unwind_out:
1947         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1948                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1949
1950                 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1951                 free_pt(vm->dev, pt);
1952         }
1953
1954         mark_tlbs_dirty(ppgtt);
1955         return ret;
1956 }
1957
1958 static int gen6_init_scratch(struct i915_address_space *vm)
1959 {
1960         struct drm_device *dev = vm->dev;
1961
1962         vm->scratch_page = alloc_scratch_page(dev);
1963         if (IS_ERR(vm->scratch_page))
1964                 return PTR_ERR(vm->scratch_page);
1965
1966         vm->scratch_pt = alloc_pt(dev);
1967         if (IS_ERR(vm->scratch_pt)) {
1968                 free_scratch_page(dev, vm->scratch_page);
1969                 return PTR_ERR(vm->scratch_pt);
1970         }
1971
1972         gen6_initialize_pt(vm, vm->scratch_pt);
1973
1974         return 0;
1975 }
1976
1977 static void gen6_free_scratch(struct i915_address_space *vm)
1978 {
1979         struct drm_device *dev = vm->dev;
1980
1981         free_pt(dev, vm->scratch_pt);
1982         free_scratch_page(dev, vm->scratch_page);
1983 }
1984
1985 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1986 {
1987         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1988         struct i915_page_directory *pd = &ppgtt->pd;
1989         struct drm_device *dev = vm->dev;
1990         struct i915_page_table *pt;
1991         uint32_t pde;
1992
1993         drm_mm_remove_node(&ppgtt->node);
1994
1995         gen6_for_all_pdes(pt, pd, pde)
1996                 if (pt != vm->scratch_pt)
1997                         free_pt(dev, pt);
1998
1999         gen6_free_scratch(vm);
2000 }
2001
2002 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
2003 {
2004         struct i915_address_space *vm = &ppgtt->base;
2005         struct drm_device *dev = ppgtt->base.dev;
2006         struct drm_i915_private *dev_priv = to_i915(dev);
2007         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2008         bool retried = false;
2009         int ret;
2010
2011         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2012          * allocator works in address space sizes, so it's multiplied by page
2013          * size. We allocate at the top of the GTT to avoid fragmentation.
2014          */
2015         BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
2016
2017         ret = gen6_init_scratch(vm);
2018         if (ret)
2019                 return ret;
2020
2021 alloc:
2022         ret = drm_mm_insert_node_in_range_generic(&ggtt->base.mm,
2023                                                   &ppgtt->node, GEN6_PD_SIZE,
2024                                                   GEN6_PD_ALIGN, 0,
2025                                                   0, ggtt->base.total,
2026                                                   DRM_MM_TOPDOWN);
2027         if (ret == -ENOSPC && !retried) {
2028                 ret = i915_gem_evict_something(dev, &ggtt->base,
2029                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
2030                                                I915_CACHE_NONE,
2031                                                0, ggtt->base.total,
2032                                                0);
2033                 if (ret)
2034                         goto err_out;
2035
2036                 retried = true;
2037                 goto alloc;
2038         }
2039
2040         if (ret)
2041                 goto err_out;
2042
2043
2044         if (ppgtt->node.start < ggtt->mappable_end)
2045                 DRM_DEBUG("Forced to use aperture for PDEs\n");
2046
2047         return 0;
2048
2049 err_out:
2050         gen6_free_scratch(vm);
2051         return ret;
2052 }
2053
2054 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2055 {
2056         return gen6_ppgtt_allocate_page_directories(ppgtt);
2057 }
2058
2059 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2060                                   uint64_t start, uint64_t length)
2061 {
2062         struct i915_page_table *unused;
2063         uint32_t pde;
2064
2065         gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
2066                 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2067 }
2068
2069 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2070 {
2071         struct drm_device *dev = ppgtt->base.dev;
2072         struct drm_i915_private *dev_priv = to_i915(dev);
2073         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2074         int ret;
2075
2076         ppgtt->base.pte_encode = ggtt->base.pte_encode;
2077         if (IS_GEN6(dev)) {
2078                 ppgtt->switch_mm = gen6_mm_switch;
2079         } else if (IS_HASWELL(dev)) {
2080                 ppgtt->switch_mm = hsw_mm_switch;
2081         } else if (IS_GEN7(dev)) {
2082                 ppgtt->switch_mm = gen7_mm_switch;
2083         } else
2084                 BUG();
2085
2086         if (intel_vgpu_active(dev_priv))
2087                 ppgtt->switch_mm = vgpu_mm_switch;
2088
2089         ret = gen6_ppgtt_alloc(ppgtt);
2090         if (ret)
2091                 return ret;
2092
2093         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2094         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2095         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2096         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2097         ppgtt->base.bind_vma = ppgtt_bind_vma;
2098         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2099         ppgtt->base.start = 0;
2100         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2101         ppgtt->debug_dump = gen6_dump_ppgtt;
2102
2103         ppgtt->pd.base.ggtt_offset =
2104                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2105
2106         ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
2107                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2108
2109         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2110
2111         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2112
2113         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2114                          ppgtt->node.size >> 20,
2115                          ppgtt->node.start / PAGE_SIZE);
2116
2117         DRM_DEBUG("Adding PPGTT at offset %x\n",
2118                   ppgtt->pd.base.ggtt_offset << 10);
2119
2120         return 0;
2121 }
2122
2123 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2124 {
2125         ppgtt->base.dev = dev;
2126
2127         if (INTEL_INFO(dev)->gen < 8)
2128                 return gen6_ppgtt_init(ppgtt);
2129         else
2130                 return gen8_ppgtt_init(ppgtt);
2131 }
2132
2133 static void i915_address_space_init(struct i915_address_space *vm,
2134                                     struct drm_i915_private *dev_priv)
2135 {
2136         drm_mm_init(&vm->mm, vm->start, vm->total);
2137         vm->dev = dev_priv->dev;
2138         INIT_LIST_HEAD(&vm->active_list);
2139         INIT_LIST_HEAD(&vm->inactive_list);
2140         list_add_tail(&vm->global_link, &dev_priv->vm_list);
2141 }
2142
2143 static void gtt_write_workarounds(struct drm_device *dev)
2144 {
2145         struct drm_i915_private *dev_priv = to_i915(dev);
2146
2147         /* This function is for gtt related workarounds. This function is
2148          * called on driver load and after a GPU reset, so you can place
2149          * workarounds here even if they get overwritten by GPU reset.
2150          */
2151         /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt */
2152         if (IS_BROADWELL(dev))
2153                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
2154         else if (IS_CHERRYVIEW(dev))
2155                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
2156         else if (IS_SKYLAKE(dev))
2157                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
2158         else if (IS_BROXTON(dev))
2159                 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
2160 }
2161
2162 static int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2163 {
2164         struct drm_i915_private *dev_priv = to_i915(dev);
2165         int ret = 0;
2166
2167         ret = __hw_ppgtt_init(dev, ppgtt);
2168         if (ret == 0) {
2169                 kref_init(&ppgtt->ref);
2170                 i915_address_space_init(&ppgtt->base, dev_priv);
2171         }
2172
2173         return ret;
2174 }
2175
2176 int i915_ppgtt_init_hw(struct drm_device *dev)
2177 {
2178         gtt_write_workarounds(dev);
2179
2180         /* In the case of execlists, PPGTT is enabled by the context descriptor
2181          * and the PDPs are contained within the context itself.  We don't
2182          * need to do anything here. */
2183         if (i915.enable_execlists)
2184                 return 0;
2185
2186         if (!USES_PPGTT(dev))
2187                 return 0;
2188
2189         if (IS_GEN6(dev))
2190                 gen6_ppgtt_enable(dev);
2191         else if (IS_GEN7(dev))
2192                 gen7_ppgtt_enable(dev);
2193         else if (INTEL_INFO(dev)->gen >= 8)
2194                 gen8_ppgtt_enable(dev);
2195         else
2196                 MISSING_CASE(INTEL_INFO(dev)->gen);
2197
2198         return 0;
2199 }
2200
2201 struct i915_hw_ppgtt *
2202 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2203 {
2204         struct i915_hw_ppgtt *ppgtt;
2205         int ret;
2206
2207         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2208         if (!ppgtt)
2209                 return ERR_PTR(-ENOMEM);
2210
2211         ret = i915_ppgtt_init(dev, ppgtt);
2212         if (ret) {
2213                 kfree(ppgtt);
2214                 return ERR_PTR(ret);
2215         }
2216
2217         ppgtt->file_priv = fpriv;
2218
2219         trace_i915_ppgtt_create(&ppgtt->base);
2220
2221         return ppgtt;
2222 }
2223
2224 void  i915_ppgtt_release(struct kref *kref)
2225 {
2226         struct i915_hw_ppgtt *ppgtt =
2227                 container_of(kref, struct i915_hw_ppgtt, ref);
2228
2229         trace_i915_ppgtt_release(&ppgtt->base);
2230
2231         /* vmas should already be unbound */
2232         WARN_ON(!list_empty(&ppgtt->base.active_list));
2233         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2234
2235         list_del(&ppgtt->base.global_link);
2236         drm_mm_takedown(&ppgtt->base.mm);
2237
2238         ppgtt->base.cleanup(&ppgtt->base);
2239         kfree(ppgtt);
2240 }
2241
2242 extern int intel_iommu_gfx_mapped;
2243 /* Certain Gen5 chipsets require require idling the GPU before
2244  * unmapping anything from the GTT when VT-d is enabled.
2245  */
2246 static bool needs_idle_maps(struct drm_device *dev)
2247 {
2248 #ifdef CONFIG_INTEL_IOMMU
2249         /* Query intel_iommu to see if we need the workaround. Presumably that
2250          * was loaded first.
2251          */
2252         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2253                 return true;
2254 #endif
2255         return false;
2256 }
2257
2258 static bool do_idling(struct drm_i915_private *dev_priv)
2259 {
2260         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2261         bool ret = dev_priv->mm.interruptible;
2262
2263         if (unlikely(ggtt->do_idle_maps)) {
2264                 dev_priv->mm.interruptible = false;
2265                 if (i915_gem_wait_for_idle(dev_priv)) {
2266                         DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2267                         /* Wait a bit, in hopes it avoids the hang */
2268                         udelay(10);
2269                 }
2270         }
2271
2272         return ret;
2273 }
2274
2275 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2276 {
2277         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2278
2279         if (unlikely(ggtt->do_idle_maps))
2280                 dev_priv->mm.interruptible = interruptible;
2281 }
2282
2283 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
2284 {
2285         struct intel_engine_cs *engine;
2286
2287         if (INTEL_INFO(dev_priv)->gen < 6)
2288                 return;
2289
2290         for_each_engine(engine, dev_priv) {
2291                 u32 fault_reg;
2292                 fault_reg = I915_READ(RING_FAULT_REG(engine));
2293                 if (fault_reg & RING_FAULT_VALID) {
2294                         DRM_DEBUG_DRIVER("Unexpected fault\n"
2295                                          "\tAddr: 0x%08lx\n"
2296                                          "\tAddress space: %s\n"
2297                                          "\tSource ID: %d\n"
2298                                          "\tType: %d\n",
2299                                          fault_reg & PAGE_MASK,
2300                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2301                                          RING_FAULT_SRCID(fault_reg),
2302                                          RING_FAULT_FAULT_TYPE(fault_reg));
2303                         I915_WRITE(RING_FAULT_REG(engine),
2304                                    fault_reg & ~RING_FAULT_VALID);
2305                 }
2306         }
2307         POSTING_READ(RING_FAULT_REG(&dev_priv->engine[RCS]));
2308 }
2309
2310 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2311 {
2312         if (INTEL_INFO(dev_priv)->gen < 6) {
2313                 intel_gtt_chipset_flush();
2314         } else {
2315                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2316                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2317         }
2318 }
2319
2320 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2321 {
2322         struct drm_i915_private *dev_priv = to_i915(dev);
2323         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2324
2325         /* Don't bother messing with faults pre GEN6 as we have little
2326          * documentation supporting that it's a good idea.
2327          */
2328         if (INTEL_INFO(dev)->gen < 6)
2329                 return;
2330
2331         i915_check_and_clear_faults(dev_priv);
2332
2333         ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
2334                              true);
2335
2336         i915_ggtt_flush(dev_priv);
2337 }
2338
2339 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2340 {
2341         if (!dma_map_sg(&obj->base.dev->pdev->dev,
2342                         obj->pages->sgl, obj->pages->nents,
2343                         PCI_DMA_BIDIRECTIONAL))
2344                 return -ENOSPC;
2345
2346         return 0;
2347 }
2348
2349 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2350 {
2351 #ifdef writeq
2352         writeq(pte, addr);
2353 #else
2354         iowrite32((u32)pte, addr);
2355         iowrite32(pte >> 32, addr + 4);
2356 #endif
2357 }
2358
2359 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2360                                   dma_addr_t addr,
2361                                   uint64_t offset,
2362                                   enum i915_cache_level level,
2363                                   u32 unused)
2364 {
2365         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2366         gen8_pte_t __iomem *pte =
2367                 (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
2368                 (offset >> PAGE_SHIFT);
2369         int rpm_atomic_seq;
2370
2371         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2372
2373         gen8_set_pte(pte, gen8_pte_encode(addr, level, true));
2374
2375         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2376         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2377
2378         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2379 }
2380
2381 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2382                                      struct sg_table *st,
2383                                      uint64_t start,
2384                                      enum i915_cache_level level, u32 unused)
2385 {
2386         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2387         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2388         struct sgt_iter sgt_iter;
2389         gen8_pte_t __iomem *gtt_entries;
2390         gen8_pte_t gtt_entry;
2391         dma_addr_t addr;
2392         int rpm_atomic_seq;
2393         int i = 0;
2394
2395         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2396
2397         gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2398
2399         for_each_sgt_dma(addr, sgt_iter, st) {
2400                 gtt_entry = gen8_pte_encode(addr, level, true);
2401                 gen8_set_pte(&gtt_entries[i++], gtt_entry);
2402         }
2403
2404         /*
2405          * XXX: This serves as a posting read to make sure that the PTE has
2406          * actually been updated. There is some concern that even though
2407          * registers and PTEs are within the same BAR that they are potentially
2408          * of NUMA access patterns. Therefore, even with the way we assume
2409          * hardware should work, we must keep this posting read for paranoia.
2410          */
2411         if (i != 0)
2412                 WARN_ON(readq(&gtt_entries[i-1]) != gtt_entry);
2413
2414         /* This next bit makes the above posting read even more important. We
2415          * want to flush the TLBs only after we're certain all the PTE updates
2416          * have finished.
2417          */
2418         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2419         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2420
2421         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2422 }
2423
2424 struct insert_entries {
2425         struct i915_address_space *vm;
2426         struct sg_table *st;
2427         uint64_t start;
2428         enum i915_cache_level level;
2429         u32 flags;
2430 };
2431
2432 static int gen8_ggtt_insert_entries__cb(void *_arg)
2433 {
2434         struct insert_entries *arg = _arg;
2435         gen8_ggtt_insert_entries(arg->vm, arg->st,
2436                                  arg->start, arg->level, arg->flags);
2437         return 0;
2438 }
2439
2440 static void gen8_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2441                                           struct sg_table *st,
2442                                           uint64_t start,
2443                                           enum i915_cache_level level,
2444                                           u32 flags)
2445 {
2446         struct insert_entries arg = { vm, st, start, level, flags };
2447         stop_machine(gen8_ggtt_insert_entries__cb, &arg, NULL);
2448 }
2449
2450 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2451                                   dma_addr_t addr,
2452                                   uint64_t offset,
2453                                   enum i915_cache_level level,
2454                                   u32 flags)
2455 {
2456         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2457         gen6_pte_t __iomem *pte =
2458                 (gen6_pte_t __iomem *)dev_priv->ggtt.gsm +
2459                 (offset >> PAGE_SHIFT);
2460         int rpm_atomic_seq;
2461
2462         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2463
2464         iowrite32(vm->pte_encode(addr, level, true, flags), pte);
2465
2466         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2467         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2468
2469         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2470 }
2471
2472 /*
2473  * Binds an object into the global gtt with the specified cache level. The object
2474  * will be accessible to the GPU via commands whose operands reference offsets
2475  * within the global GTT as well as accessible by the GPU through the GMADR
2476  * mapped BAR (dev_priv->mm.gtt->gtt).
2477  */
2478 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2479                                      struct sg_table *st,
2480                                      uint64_t start,
2481                                      enum i915_cache_level level, u32 flags)
2482 {
2483         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2484         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2485         struct sgt_iter sgt_iter;
2486         gen6_pte_t __iomem *gtt_entries;
2487         gen6_pte_t gtt_entry;
2488         dma_addr_t addr;
2489         int rpm_atomic_seq;
2490         int i = 0;
2491
2492         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2493
2494         gtt_entries = (gen6_pte_t __iomem *)ggtt->gsm + (start >> PAGE_SHIFT);
2495
2496         for_each_sgt_dma(addr, sgt_iter, st) {
2497                 gtt_entry = vm->pte_encode(addr, level, true, flags);
2498                 iowrite32(gtt_entry, &gtt_entries[i++]);
2499         }
2500
2501         /* XXX: This serves as a posting read to make sure that the PTE has
2502          * actually been updated. There is some concern that even though
2503          * registers and PTEs are within the same BAR that they are potentially
2504          * of NUMA access patterns. Therefore, even with the way we assume
2505          * hardware should work, we must keep this posting read for paranoia.
2506          */
2507         if (i != 0)
2508                 WARN_ON(readl(&gtt_entries[i-1]) != gtt_entry);
2509
2510         /* This next bit makes the above posting read even more important. We
2511          * want to flush the TLBs only after we're certain all the PTE updates
2512          * have finished.
2513          */
2514         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2515         POSTING_READ(GFX_FLSH_CNTL_GEN6);
2516
2517         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2518 }
2519
2520 static void nop_clear_range(struct i915_address_space *vm,
2521                             uint64_t start,
2522                             uint64_t length,
2523                             bool use_scratch)
2524 {
2525 }
2526
2527 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2528                                   uint64_t start,
2529                                   uint64_t length,
2530                                   bool use_scratch)
2531 {
2532         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2533         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2534         unsigned first_entry = start >> PAGE_SHIFT;
2535         unsigned num_entries = length >> PAGE_SHIFT;
2536         gen8_pte_t scratch_pte, __iomem *gtt_base =
2537                 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2538         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2539         int i;
2540         int rpm_atomic_seq;
2541
2542         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2543
2544         if (WARN(num_entries > max_entries,
2545                  "First entry = %d; Num entries = %d (max=%d)\n",
2546                  first_entry, num_entries, max_entries))
2547                 num_entries = max_entries;
2548
2549         scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2550                                       I915_CACHE_LLC,
2551                                       use_scratch);
2552         for (i = 0; i < num_entries; i++)
2553                 gen8_set_pte(&gtt_base[i], scratch_pte);
2554         readl(gtt_base);
2555
2556         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2557 }
2558
2559 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2560                                   uint64_t start,
2561                                   uint64_t length,
2562                                   bool use_scratch)
2563 {
2564         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2565         struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2566         unsigned first_entry = start >> PAGE_SHIFT;
2567         unsigned num_entries = length >> PAGE_SHIFT;
2568         gen6_pte_t scratch_pte, __iomem *gtt_base =
2569                 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2570         const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2571         int i;
2572         int rpm_atomic_seq;
2573
2574         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2575
2576         if (WARN(num_entries > max_entries,
2577                  "First entry = %d; Num entries = %d (max=%d)\n",
2578                  first_entry, num_entries, max_entries))
2579                 num_entries = max_entries;
2580
2581         scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2582                                      I915_CACHE_LLC, use_scratch, 0);
2583
2584         for (i = 0; i < num_entries; i++)
2585                 iowrite32(scratch_pte, &gtt_base[i]);
2586         readl(gtt_base);
2587
2588         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2589 }
2590
2591 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2592                                   dma_addr_t addr,
2593                                   uint64_t offset,
2594                                   enum i915_cache_level cache_level,
2595                                   u32 unused)
2596 {
2597         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2598         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2599                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2600         int rpm_atomic_seq;
2601
2602         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2603
2604         intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2605
2606         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2607 }
2608
2609 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2610                                      struct sg_table *pages,
2611                                      uint64_t start,
2612                                      enum i915_cache_level cache_level, u32 unused)
2613 {
2614         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2615         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2616                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2617         int rpm_atomic_seq;
2618
2619         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2620
2621         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2622
2623         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2624
2625 }
2626
2627 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2628                                   uint64_t start,
2629                                   uint64_t length,
2630                                   bool unused)
2631 {
2632         struct drm_i915_private *dev_priv = to_i915(vm->dev);
2633         unsigned first_entry = start >> PAGE_SHIFT;
2634         unsigned num_entries = length >> PAGE_SHIFT;
2635         int rpm_atomic_seq;
2636
2637         rpm_atomic_seq = assert_rpm_atomic_begin(dev_priv);
2638
2639         intel_gtt_clear_range(first_entry, num_entries);
2640
2641         assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
2642 }
2643
2644 static int ggtt_bind_vma(struct i915_vma *vma,
2645                          enum i915_cache_level cache_level,
2646                          u32 flags)
2647 {
2648         struct drm_i915_gem_object *obj = vma->obj;
2649         u32 pte_flags = 0;
2650         int ret;
2651
2652         ret = i915_get_ggtt_vma_pages(vma);
2653         if (ret)
2654                 return ret;
2655
2656         /* Currently applicable only to VLV */
2657         if (obj->gt_ro)
2658                 pte_flags |= PTE_READ_ONLY;
2659
2660         vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2661                                 vma->node.start,
2662                                 cache_level, pte_flags);
2663
2664         /*
2665          * Without aliasing PPGTT there's no difference between
2666          * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2667          * upgrade to both bound if we bind either to avoid double-binding.
2668          */
2669         vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2670
2671         return 0;
2672 }
2673
2674 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2675                                  enum i915_cache_level cache_level,
2676                                  u32 flags)
2677 {
2678         u32 pte_flags;
2679         int ret;
2680
2681         ret = i915_get_ggtt_vma_pages(vma);
2682         if (ret)
2683                 return ret;
2684
2685         /* Currently applicable only to VLV */
2686         pte_flags = 0;
2687         if (vma->obj->gt_ro)
2688                 pte_flags |= PTE_READ_ONLY;
2689
2690
2691         if (flags & GLOBAL_BIND) {
2692                 vma->vm->insert_entries(vma->vm,
2693                                         vma->ggtt_view.pages,
2694                                         vma->node.start,
2695                                         cache_level, pte_flags);
2696         }
2697
2698         if (flags & LOCAL_BIND) {
2699                 struct i915_hw_ppgtt *appgtt =
2700                         to_i915(vma->vm->dev)->mm.aliasing_ppgtt;
2701                 appgtt->base.insert_entries(&appgtt->base,
2702                                             vma->ggtt_view.pages,
2703                                             vma->node.start,
2704                                             cache_level, pte_flags);
2705         }
2706
2707         return 0;
2708 }
2709
2710 static void ggtt_unbind_vma(struct i915_vma *vma)
2711 {
2712         struct drm_device *dev = vma->vm->dev;
2713         struct drm_i915_private *dev_priv = to_i915(dev);
2714         struct drm_i915_gem_object *obj = vma->obj;
2715         const uint64_t size = min_t(uint64_t,
2716                                     obj->base.size,
2717                                     vma->node.size);
2718
2719         if (vma->bound & GLOBAL_BIND) {
2720                 vma->vm->clear_range(vma->vm,
2721                                      vma->node.start,
2722                                      size,
2723                                      true);
2724         }
2725
2726         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2727                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2728
2729                 appgtt->base.clear_range(&appgtt->base,
2730                                          vma->node.start,
2731                                          size,
2732                                          true);
2733         }
2734 }
2735
2736 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2737 {
2738         struct drm_device *dev = obj->base.dev;
2739         struct drm_i915_private *dev_priv = to_i915(dev);
2740         bool interruptible;
2741
2742         interruptible = do_idling(dev_priv);
2743
2744         dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2745                      PCI_DMA_BIDIRECTIONAL);
2746
2747         undo_idling(dev_priv, interruptible);
2748 }
2749
2750 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2751                                   unsigned long color,
2752                                   u64 *start,
2753                                   u64 *end)
2754 {
2755         if (node->color != color)
2756                 *start += 4096;
2757
2758         if (!list_empty(&node->node_list)) {
2759                 node = list_entry(node->node_list.next,
2760                                   struct drm_mm_node,
2761                                   node_list);
2762                 if (node->allocated && node->color != color)
2763                         *end -= 4096;
2764         }
2765 }
2766
2767 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2768                                      u64 start,
2769                                      u64 mappable_end,
2770                                      u64 end)
2771 {
2772         /* Let GEM Manage all of the aperture.
2773          *
2774          * However, leave one page at the end still bound to the scratch page.
2775          * There are a number of places where the hardware apparently prefetches
2776          * past the end of the object, and we've seen multiple hangs with the
2777          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2778          * aperture.  One page should be enough to keep any prefetching inside
2779          * of the aperture.
2780          */
2781         struct drm_i915_private *dev_priv = to_i915(dev);
2782         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2783         struct drm_mm_node *entry;
2784         struct drm_i915_gem_object *obj;
2785         unsigned long hole_start, hole_end;
2786         int ret;
2787
2788         BUG_ON(mappable_end > end);
2789
2790         ggtt->base.start = start;
2791
2792         /* Subtract the guard page before address space initialization to
2793          * shrink the range used by drm_mm */
2794         ggtt->base.total = end - start - PAGE_SIZE;
2795         i915_address_space_init(&ggtt->base, dev_priv);
2796         ggtt->base.total += PAGE_SIZE;
2797
2798         ret = intel_vgt_balloon(dev_priv);
2799         if (ret)
2800                 return ret;
2801
2802         if (!HAS_LLC(dev))
2803                 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
2804
2805         /* Mark any preallocated objects as occupied */
2806         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2807                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, &ggtt->base);
2808
2809                 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2810                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2811
2812                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2813                 ret = drm_mm_reserve_node(&ggtt->base.mm, &vma->node);
2814                 if (ret) {
2815                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2816                         return ret;
2817                 }
2818                 vma->bound |= GLOBAL_BIND;
2819                 __i915_vma_set_map_and_fenceable(vma);
2820                 list_add_tail(&vma->vm_link, &ggtt->base.inactive_list);
2821         }
2822
2823         /* Clear any non-preallocated blocks */
2824         drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
2825                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2826                               hole_start, hole_end);
2827                 ggtt->base.clear_range(&ggtt->base, hole_start,
2828                                      hole_end - hole_start, true);
2829         }
2830
2831         /* And finally clear the reserved guard page */
2832         ggtt->base.clear_range(&ggtt->base, end - PAGE_SIZE, PAGE_SIZE, true);
2833
2834         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2835                 struct i915_hw_ppgtt *ppgtt;
2836
2837                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2838                 if (!ppgtt)
2839                         return -ENOMEM;
2840
2841                 ret = __hw_ppgtt_init(dev, ppgtt);
2842                 if (ret) {
2843                         ppgtt->base.cleanup(&ppgtt->base);
2844                         kfree(ppgtt);
2845                         return ret;
2846                 }
2847
2848                 if (ppgtt->base.allocate_va_range)
2849                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2850                                                             ppgtt->base.total);
2851                 if (ret) {
2852                         ppgtt->base.cleanup(&ppgtt->base);
2853                         kfree(ppgtt);
2854                         return ret;
2855                 }
2856
2857                 ppgtt->base.clear_range(&ppgtt->base,
2858                                         ppgtt->base.start,
2859                                         ppgtt->base.total,
2860                                         true);
2861
2862                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2863                 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2864                 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
2865         }
2866
2867         return 0;
2868 }
2869
2870 /**
2871  * i915_gem_init_ggtt - Initialize GEM for Global GTT
2872  * @dev: DRM device
2873  */
2874 void i915_gem_init_ggtt(struct drm_device *dev)
2875 {
2876         struct drm_i915_private *dev_priv = to_i915(dev);
2877         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2878
2879         i915_gem_setup_global_gtt(dev, 0, ggtt->mappable_end, ggtt->base.total);
2880 }
2881
2882 /**
2883  * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2884  * @dev: DRM device
2885  */
2886 void i915_ggtt_cleanup_hw(struct drm_device *dev)
2887 {
2888         struct drm_i915_private *dev_priv = to_i915(dev);
2889         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2890
2891         if (dev_priv->mm.aliasing_ppgtt) {
2892                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2893
2894                 ppgtt->base.cleanup(&ppgtt->base);
2895         }
2896
2897         i915_gem_cleanup_stolen(dev);
2898
2899         if (drm_mm_initialized(&ggtt->base.mm)) {
2900                 intel_vgt_deballoon(dev_priv);
2901
2902                 drm_mm_takedown(&ggtt->base.mm);
2903                 list_del(&ggtt->base.global_link);
2904         }
2905
2906         ggtt->base.cleanup(&ggtt->base);
2907 }
2908
2909 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2910 {
2911         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2912         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2913         return snb_gmch_ctl << 20;
2914 }
2915
2916 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2917 {
2918         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2919         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2920         if (bdw_gmch_ctl)
2921                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2922
2923 #ifdef CONFIG_X86_32
2924         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2925         if (bdw_gmch_ctl > 4)
2926                 bdw_gmch_ctl = 4;
2927 #endif
2928
2929         return bdw_gmch_ctl << 20;
2930 }
2931
2932 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2933 {
2934         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2935         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2936
2937         if (gmch_ctrl)
2938                 return 1 << (20 + gmch_ctrl);
2939
2940         return 0;
2941 }
2942
2943 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2944 {
2945         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2946         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2947         return snb_gmch_ctl << 25; /* 32 MB units */
2948 }
2949
2950 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2951 {
2952         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2953         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2954         return bdw_gmch_ctl << 25; /* 32 MB units */
2955 }
2956
2957 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2958 {
2959         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2960         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2961
2962         /*
2963          * 0x0  to 0x10: 32MB increments starting at 0MB
2964          * 0x11 to 0x16: 4MB increments starting at 8MB
2965          * 0x17 to 0x1d: 4MB increments start at 36MB
2966          */
2967         if (gmch_ctrl < 0x11)
2968                 return gmch_ctrl << 25;
2969         else if (gmch_ctrl < 0x17)
2970                 return (gmch_ctrl - 0x11 + 2) << 22;
2971         else
2972                 return (gmch_ctrl - 0x17 + 9) << 22;
2973 }
2974
2975 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2976 {
2977         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2978         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2979
2980         if (gen9_gmch_ctl < 0xf0)
2981                 return gen9_gmch_ctl << 25; /* 32 MB units */
2982         else
2983                 /* 4MB increments starting at 0xf0 for 4MB */
2984                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2985 }
2986
2987 static int ggtt_probe_common(struct drm_device *dev,
2988                              size_t gtt_size)
2989 {
2990         struct drm_i915_private *dev_priv = to_i915(dev);
2991         struct i915_ggtt *ggtt = &dev_priv->ggtt;
2992         struct i915_page_scratch *scratch_page;
2993         phys_addr_t ggtt_phys_addr;
2994
2995         /* For Modern GENs the PTEs and register space are split in the BAR */
2996         ggtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2997                          (pci_resource_len(dev->pdev, 0) / 2);
2998
2999         /*
3000          * On BXT writes larger than 64 bit to the GTT pagetable range will be
3001          * dropped. For WC mappings in general we have 64 byte burst writes
3002          * when the WC buffer is flushed, so we can't use it, but have to
3003          * resort to an uncached mapping. The WC issue is easily caught by the
3004          * readback check when writing GTT PTE entries.
3005          */
3006         if (IS_BROXTON(dev))
3007                 ggtt->gsm = ioremap_nocache(ggtt_phys_addr, gtt_size);
3008         else
3009                 ggtt->gsm = ioremap_wc(ggtt_phys_addr, gtt_size);
3010         if (!ggtt->gsm) {
3011                 DRM_ERROR("Failed to map the gtt page table\n");
3012                 return -ENOMEM;
3013         }
3014
3015         scratch_page = alloc_scratch_page(dev);
3016         if (IS_ERR(scratch_page)) {
3017                 DRM_ERROR("Scratch setup failed\n");
3018                 /* iounmap will also get called at remove, but meh */
3019                 iounmap(ggtt->gsm);
3020                 return PTR_ERR(scratch_page);
3021         }
3022
3023         ggtt->base.scratch_page = scratch_page;
3024
3025         return 0;
3026 }
3027
3028 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3029  * bits. When using advanced contexts each context stores its own PAT, but
3030  * writing this data shouldn't be harmful even in those cases. */
3031 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
3032 {
3033         uint64_t pat;
3034
3035         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
3036               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
3037               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
3038               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
3039               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
3040               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
3041               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
3042               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
3043
3044         if (!USES_PPGTT(dev_priv))
3045                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3046                  * so RTL will always use the value corresponding to
3047                  * pat_sel = 000".
3048                  * So let's disable cache for GGTT to avoid screen corruptions.
3049                  * MOCS still can be used though.
3050                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3051                  * before this patch, i.e. the same uncached + snooping access
3052                  * like on gen6/7 seems to be in effect.
3053                  * - So this just fixes blitter/render access. Again it looks
3054                  * like it's not just uncached access, but uncached + snooping.
3055                  * So we can still hold onto all our assumptions wrt cpu
3056                  * clflushing on LLC machines.
3057                  */
3058                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
3059
3060         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
3061          * write would work. */
3062         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3063         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
3064 }
3065
3066 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
3067 {
3068         uint64_t pat;
3069
3070         /*
3071          * Map WB on BDW to snooped on CHV.
3072          *
3073          * Only the snoop bit has meaning for CHV, the rest is
3074          * ignored.
3075          *
3076          * The hardware will never snoop for certain types of accesses:
3077          * - CPU GTT (GMADR->GGTT->no snoop->memory)
3078          * - PPGTT page tables
3079          * - some other special cycles
3080          *
3081          * As with BDW, we also need to consider the following for GT accesses:
3082          * "For GGTT, there is NO pat_sel[2:0] from the entry,
3083          * so RTL will always use the value corresponding to
3084          * pat_sel = 000".
3085          * Which means we must set the snoop bit in PAT entry 0
3086          * in order to keep the global status page working.
3087          */
3088         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
3089               GEN8_PPAT(1, 0) |
3090               GEN8_PPAT(2, 0) |
3091               GEN8_PPAT(3, 0) |
3092               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
3093               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
3094               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
3095               GEN8_PPAT(7, CHV_PPAT_SNOOP);
3096
3097         I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
3098         I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
3099 }
3100
3101 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
3102 {
3103         struct drm_device *dev = ggtt->base.dev;
3104         struct drm_i915_private *dev_priv = to_i915(dev);
3105         u16 snb_gmch_ctl;
3106         int ret;
3107
3108         /* TODO: We're not aware of mappable constraints on gen8 yet */
3109         ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3110         ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
3111
3112         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
3113                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
3114
3115         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3116
3117         if (INTEL_INFO(dev)->gen >= 9) {
3118                 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
3119                 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
3120         } else if (IS_CHERRYVIEW(dev)) {
3121                 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
3122                 ggtt->size = chv_get_total_gtt_size(snb_gmch_ctl);
3123         } else {
3124                 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
3125                 ggtt->size = gen8_get_total_gtt_size(snb_gmch_ctl);
3126         }
3127
3128         ggtt->base.total = (ggtt->size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3129
3130         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3131                 chv_setup_private_ppat(dev_priv);
3132         else
3133                 bdw_setup_private_ppat(dev_priv);
3134
3135         ret = ggtt_probe_common(dev, ggtt->size);
3136
3137         ggtt->base.bind_vma = ggtt_bind_vma;
3138         ggtt->base.unbind_vma = ggtt_unbind_vma;
3139         ggtt->base.insert_page = gen8_ggtt_insert_page;
3140         ggtt->base.clear_range = nop_clear_range;
3141         if (!USES_FULL_PPGTT(dev_priv))
3142                 ggtt->base.clear_range = gen8_ggtt_clear_range;
3143
3144         ggtt->base.insert_entries = gen8_ggtt_insert_entries;
3145         if (IS_CHERRYVIEW(dev_priv))
3146                 ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
3147
3148         return ret;
3149 }
3150
3151 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
3152 {
3153         struct drm_device *dev = ggtt->base.dev;
3154         u16 snb_gmch_ctl;
3155         int ret;
3156
3157         ggtt->mappable_base = pci_resource_start(dev->pdev, 2);
3158         ggtt->mappable_end = pci_resource_len(dev->pdev, 2);
3159
3160         /* 64/512MB is the current min/max we actually know of, but this is just
3161          * a coarse sanity check.
3162          */
3163         if ((ggtt->mappable_end < (64<<20) || (ggtt->mappable_end > (512<<20)))) {
3164                 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
3165                 return -ENXIO;
3166         }
3167
3168         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3169                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3170         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3171
3172         ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
3173         ggtt->size = gen6_get_total_gtt_size(snb_gmch_ctl);
3174         ggtt->base.total = (ggtt->size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3175
3176         ret = ggtt_probe_common(dev, ggtt->size);
3177
3178         ggtt->base.clear_range = gen6_ggtt_clear_range;
3179         ggtt->base.insert_page = gen6_ggtt_insert_page;
3180         ggtt->base.insert_entries = gen6_ggtt_insert_entries;
3181         ggtt->base.bind_vma = ggtt_bind_vma;
3182         ggtt->base.unbind_vma = ggtt_unbind_vma;
3183
3184         return ret;
3185 }
3186
3187 static void gen6_gmch_remove(struct i915_address_space *vm)
3188 {
3189         struct i915_ggtt *ggtt = container_of(vm, struct i915_ggtt, base);
3190
3191         iounmap(ggtt->gsm);
3192         free_scratch_page(vm->dev, vm->scratch_page);
3193 }
3194
3195 static int i915_gmch_probe(struct i915_ggtt *ggtt)
3196 {
3197         struct drm_device *dev = ggtt->base.dev;
3198         struct drm_i915_private *dev_priv = to_i915(dev);
3199         int ret;
3200
3201         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3202         if (!ret) {
3203                 DRM_ERROR("failed to set up gmch\n");
3204                 return -EIO;
3205         }
3206
3207         intel_gtt_get(&ggtt->base.total, &ggtt->stolen_size,
3208                       &ggtt->mappable_base, &ggtt->mappable_end);
3209
3210         ggtt->do_idle_maps = needs_idle_maps(dev_priv->dev);
3211         ggtt->base.insert_page = i915_ggtt_insert_page;
3212         ggtt->base.insert_entries = i915_ggtt_insert_entries;
3213         ggtt->base.clear_range = i915_ggtt_clear_range;
3214         ggtt->base.bind_vma = ggtt_bind_vma;
3215         ggtt->base.unbind_vma = ggtt_unbind_vma;
3216
3217         if (unlikely(ggtt->do_idle_maps))
3218                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3219
3220         return 0;
3221 }
3222
3223 static void i915_gmch_remove(struct i915_address_space *vm)
3224 {
3225         intel_gmch_remove();
3226 }
3227
3228 /**
3229  * i915_ggtt_init_hw - Initialize GGTT hardware
3230  * @dev: DRM device
3231  */
3232 int i915_ggtt_init_hw(struct drm_device *dev)
3233 {
3234         struct drm_i915_private *dev_priv = to_i915(dev);
3235         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3236         int ret;
3237
3238         if (INTEL_INFO(dev)->gen <= 5) {
3239                 ggtt->probe = i915_gmch_probe;
3240                 ggtt->base.cleanup = i915_gmch_remove;
3241         } else if (INTEL_INFO(dev)->gen < 8) {
3242                 ggtt->probe = gen6_gmch_probe;
3243                 ggtt->base.cleanup = gen6_gmch_remove;
3244
3245                 if (HAS_EDRAM(dev))
3246                         ggtt->base.pte_encode = iris_pte_encode;
3247                 else if (IS_HASWELL(dev))
3248                         ggtt->base.pte_encode = hsw_pte_encode;
3249                 else if (IS_VALLEYVIEW(dev))
3250                         ggtt->base.pte_encode = byt_pte_encode;
3251                 else if (INTEL_INFO(dev)->gen >= 7)
3252                         ggtt->base.pte_encode = ivb_pte_encode;
3253                 else
3254                         ggtt->base.pte_encode = snb_pte_encode;
3255         } else {
3256                 ggtt->probe = gen8_gmch_probe;
3257                 ggtt->base.cleanup = gen6_gmch_remove;
3258         }
3259
3260         ggtt->base.dev = dev;
3261         ggtt->base.is_ggtt = true;
3262
3263         ret = ggtt->probe(ggtt);
3264         if (ret)
3265                 return ret;
3266
3267         if ((ggtt->base.total - 1) >> 32) {
3268                 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3269                           "of address space! Found %lldM!\n",
3270                           ggtt->base.total >> 20);
3271                 ggtt->base.total = 1ULL << 32;
3272                 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3273         }
3274
3275         /*
3276          * Initialise stolen early so that we may reserve preallocated
3277          * objects for the BIOS to KMS transition.
3278          */
3279         ret = i915_gem_init_stolen(dev);
3280         if (ret)
3281                 goto out_gtt_cleanup;
3282
3283         /* GMADR is the PCI mmio aperture into the global GTT. */
3284         DRM_INFO("Memory usable by graphics device = %lluM\n",
3285                  ggtt->base.total >> 20);
3286         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3287         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", ggtt->stolen_size >> 20);
3288 #ifdef CONFIG_INTEL_IOMMU
3289         if (intel_iommu_gfx_mapped)
3290                 DRM_INFO("VT-d active for gfx access\n");
3291 #endif
3292
3293         return 0;
3294
3295 out_gtt_cleanup:
3296         ggtt->base.cleanup(&ggtt->base);
3297
3298         return ret;
3299 }
3300
3301 int i915_ggtt_enable_hw(struct drm_device *dev)
3302 {
3303         if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
3304                 return -EIO;
3305
3306         return 0;
3307 }
3308
3309 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3310 {
3311         struct drm_i915_private *dev_priv = to_i915(dev);
3312         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3313         struct drm_i915_gem_object *obj;
3314         struct i915_vma *vma;
3315
3316         i915_check_and_clear_faults(dev_priv);
3317
3318         /* First fill our portion of the GTT with scratch pages */
3319         ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total,
3320                                true);
3321
3322         /* Cache flush objects bound into GGTT and rebind them. */
3323         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3324                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3325                         if (vma->vm != &ggtt->base)
3326                                 continue;
3327
3328                         WARN_ON(i915_vma_bind(vma, obj->cache_level,
3329                                               PIN_UPDATE));
3330                 }
3331
3332                 if (obj->pin_display)
3333                         WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
3334         }
3335
3336         if (INTEL_INFO(dev)->gen >= 8) {
3337                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3338                         chv_setup_private_ppat(dev_priv);
3339                 else
3340                         bdw_setup_private_ppat(dev_priv);
3341
3342                 return;
3343         }
3344
3345         if (USES_PPGTT(dev)) {
3346                 struct i915_address_space *vm;
3347
3348                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3349                         /* TODO: Perhaps it shouldn't be gen6 specific */
3350
3351                         struct i915_hw_ppgtt *ppgtt;
3352
3353                         if (vm->is_ggtt)
3354                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
3355                         else
3356                                 ppgtt = i915_vm_to_ppgtt(vm);
3357
3358                         gen6_write_page_range(dev_priv, &ppgtt->pd,
3359                                               0, ppgtt->base.total);
3360                 }
3361         }
3362
3363         i915_ggtt_flush(dev_priv);
3364 }
3365
3366 static struct i915_vma *
3367 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3368                       struct i915_address_space *vm,
3369                       const struct i915_ggtt_view *ggtt_view)
3370 {
3371         struct i915_vma *vma;
3372
3373         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3374                 return ERR_PTR(-EINVAL);
3375
3376         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3377         if (vma == NULL)
3378                 return ERR_PTR(-ENOMEM);
3379
3380         INIT_LIST_HEAD(&vma->vm_link);
3381         INIT_LIST_HEAD(&vma->obj_link);
3382         INIT_LIST_HEAD(&vma->exec_list);
3383         vma->vm = vm;
3384         vma->obj = obj;
3385         vma->is_ggtt = i915_is_ggtt(vm);
3386
3387         if (i915_is_ggtt(vm))
3388                 vma->ggtt_view = *ggtt_view;
3389         else
3390                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3391
3392         list_add_tail(&vma->obj_link, &obj->vma_list);
3393
3394         return vma;
3395 }
3396
3397 struct i915_vma *
3398 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3399                                   struct i915_address_space *vm)
3400 {
3401         struct i915_vma *vma;
3402
3403         vma = i915_gem_obj_to_vma(obj, vm);
3404         if (!vma)
3405                 vma = __i915_gem_vma_create(obj, vm,
3406                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3407
3408         return vma;
3409 }
3410
3411 struct i915_vma *
3412 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3413                                        const struct i915_ggtt_view *view)
3414 {
3415         struct drm_device *dev = obj->base.dev;
3416         struct drm_i915_private *dev_priv = to_i915(dev);
3417         struct i915_ggtt *ggtt = &dev_priv->ggtt;
3418         struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
3419
3420         if (!vma)
3421                 vma = __i915_gem_vma_create(obj, &ggtt->base, view);
3422
3423         return vma;
3424
3425 }
3426
3427 static struct scatterlist *
3428 rotate_pages(const dma_addr_t *in, unsigned int offset,
3429              unsigned int width, unsigned int height,
3430              unsigned int stride,
3431              struct sg_table *st, struct scatterlist *sg)
3432 {
3433         unsigned int column, row;
3434         unsigned int src_idx;
3435
3436         for (column = 0; column < width; column++) {
3437                 src_idx = stride * (height - 1) + column;
3438                 for (row = 0; row < height; row++) {
3439                         st->nents++;
3440                         /* We don't need the pages, but need to initialize
3441                          * the entries so the sg list can be happily traversed.
3442                          * The only thing we need are DMA addresses.
3443                          */
3444                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
3445                         sg_dma_address(sg) = in[offset + src_idx];
3446                         sg_dma_len(sg) = PAGE_SIZE;
3447                         sg = sg_next(sg);
3448                         src_idx -= stride;
3449                 }
3450         }
3451
3452         return sg;
3453 }
3454
3455 static struct sg_table *
3456 intel_rotate_fb_obj_pages(struct intel_rotation_info *rot_info,
3457                           struct drm_i915_gem_object *obj)
3458 {
3459         const size_t n_pages = obj->base.size / PAGE_SIZE;
3460         unsigned int size_pages = rot_info->plane[0].width * rot_info->plane[0].height;
3461         unsigned int size_pages_uv;
3462         struct sgt_iter sgt_iter;
3463         dma_addr_t dma_addr;
3464         unsigned long i;
3465         dma_addr_t *page_addr_list;
3466         struct sg_table *st;
3467         unsigned int uv_start_page;
3468         struct scatterlist *sg;
3469         int ret = -ENOMEM;
3470
3471         /* Allocate a temporary list of source pages for random access. */
3472         page_addr_list = drm_malloc_gfp(n_pages,
3473                                         sizeof(dma_addr_t),
3474                                         GFP_TEMPORARY);
3475         if (!page_addr_list)
3476                 return ERR_PTR(ret);
3477
3478         /* Account for UV plane with NV12. */
3479         if (rot_info->pixel_format == DRM_FORMAT_NV12)
3480                 size_pages_uv = rot_info->plane[1].width * rot_info->plane[1].height;
3481         else
3482                 size_pages_uv = 0;
3483
3484         /* Allocate target SG list. */
3485         st = kmalloc(sizeof(*st), GFP_KERNEL);
3486         if (!st)
3487                 goto err_st_alloc;
3488
3489         ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3490         if (ret)
3491                 goto err_sg_alloc;
3492
3493         /* Populate source page list from the object. */
3494         i = 0;
3495         for_each_sgt_dma(dma_addr, sgt_iter, obj->pages)
3496                 page_addr_list[i++] = dma_addr;
3497
3498         GEM_BUG_ON(i != n_pages);
3499         st->nents = 0;
3500         sg = st->sgl;
3501
3502         /* Rotate the pages. */
3503         sg = rotate_pages(page_addr_list, 0,
3504                           rot_info->plane[0].width, rot_info->plane[0].height,
3505                           rot_info->plane[0].width,
3506                           st, sg);
3507
3508         /* Append the UV plane if NV12. */
3509         if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3510                 uv_start_page = size_pages;
3511
3512                 /* Check for tile-row un-alignment. */
3513                 if (offset_in_page(rot_info->uv_offset))
3514                         uv_start_page--;
3515
3516                 rot_info->uv_start_page = uv_start_page;
3517
3518                 sg = rotate_pages(page_addr_list, rot_info->uv_start_page,
3519                                   rot_info->plane[1].width, rot_info->plane[1].height,
3520                                   rot_info->plane[1].width,
3521                                   st, sg);
3522         }
3523
3524         DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages (%u plane 0)).\n",
3525                       obj->base.size, rot_info->plane[0].width,
3526                       rot_info->plane[0].height, size_pages + size_pages_uv,
3527                       size_pages);
3528
3529         drm_free_large(page_addr_list);
3530
3531         return st;
3532
3533 err_sg_alloc:
3534         kfree(st);
3535 err_st_alloc:
3536         drm_free_large(page_addr_list);
3537
3538         DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%d) (%ux%u tiles, %u pages (%u plane 0))\n",
3539                       obj->base.size, ret, rot_info->plane[0].width,
3540                       rot_info->plane[0].height, size_pages + size_pages_uv,
3541                       size_pages);
3542         return ERR_PTR(ret);
3543 }
3544
3545 static struct sg_table *
3546 intel_partial_pages(const struct i915_ggtt_view *view,
3547                     struct drm_i915_gem_object *obj)
3548 {
3549         struct sg_table *st;
3550         struct scatterlist *sg;
3551         struct sg_page_iter obj_sg_iter;
3552         int ret = -ENOMEM;
3553
3554         st = kmalloc(sizeof(*st), GFP_KERNEL);
3555         if (!st)
3556                 goto err_st_alloc;
3557
3558         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3559         if (ret)
3560                 goto err_sg_alloc;
3561
3562         sg = st->sgl;
3563         st->nents = 0;
3564         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3565                 view->params.partial.offset)
3566         {
3567                 if (st->nents >= view->params.partial.size)
3568                         break;
3569
3570                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3571                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3572                 sg_dma_len(sg) = PAGE_SIZE;
3573
3574                 sg = sg_next(sg);
3575                 st->nents++;
3576         }
3577
3578         return st;
3579
3580 err_sg_alloc:
3581         kfree(st);
3582 err_st_alloc:
3583         return ERR_PTR(ret);
3584 }
3585
3586 static int
3587 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3588 {
3589         int ret = 0;
3590
3591         if (vma->ggtt_view.pages)
3592                 return 0;
3593
3594         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3595                 vma->ggtt_view.pages = vma->obj->pages;
3596         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3597                 vma->ggtt_view.pages =
3598                         intel_rotate_fb_obj_pages(&vma->ggtt_view.params.rotated, vma->obj);
3599         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3600                 vma->ggtt_view.pages =
3601                         intel_partial_pages(&vma->ggtt_view, vma->obj);
3602         else
3603                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3604                           vma->ggtt_view.type);
3605
3606         if (!vma->ggtt_view.pages) {
3607                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3608                           vma->ggtt_view.type);
3609                 ret = -EINVAL;
3610         } else if (IS_ERR(vma->ggtt_view.pages)) {
3611                 ret = PTR_ERR(vma->ggtt_view.pages);
3612                 vma->ggtt_view.pages = NULL;
3613                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3614                           vma->ggtt_view.type, ret);
3615         }
3616
3617         return ret;
3618 }
3619
3620 /**
3621  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3622  * @vma: VMA to map
3623  * @cache_level: mapping cache level
3624  * @flags: flags like global or local mapping
3625  *
3626  * DMA addresses are taken from the scatter-gather table of this object (or of
3627  * this VMA in case of non-default GGTT views) and PTE entries set up.
3628  * Note that DMA addresses are also the only part of the SG table we care about.
3629  */
3630 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3631                   u32 flags)
3632 {
3633         int ret;
3634         u32 bind_flags;
3635
3636         if (WARN_ON(flags == 0))
3637                 return -EINVAL;
3638
3639         bind_flags = 0;
3640         if (flags & PIN_GLOBAL)
3641                 bind_flags |= GLOBAL_BIND;
3642         if (flags & PIN_USER)
3643                 bind_flags |= LOCAL_BIND;
3644
3645         if (flags & PIN_UPDATE)
3646                 bind_flags |= vma->bound;
3647         else
3648                 bind_flags &= ~vma->bound;
3649
3650         if (bind_flags == 0)
3651                 return 0;
3652
3653         if (vma->bound == 0 && vma->vm->allocate_va_range) {
3654                 /* XXX: i915_vma_pin() will fix this +- hack */
3655                 vma->pin_count++;
3656                 trace_i915_va_alloc(vma);
3657                 ret = vma->vm->allocate_va_range(vma->vm,
3658                                                  vma->node.start,
3659                                                  vma->node.size);
3660                 vma->pin_count--;
3661                 if (ret)
3662                         return ret;
3663         }
3664
3665         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3666         if (ret)
3667                 return ret;
3668
3669         vma->bound |= bind_flags;
3670
3671         return 0;
3672 }
3673
3674 /**
3675  * i915_ggtt_view_size - Get the size of a GGTT view.
3676  * @obj: Object the view is of.
3677  * @view: The view in question.
3678  *
3679  * @return The size of the GGTT view in bytes.
3680  */
3681 size_t
3682 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3683                     const struct i915_ggtt_view *view)
3684 {
3685         if (view->type == I915_GGTT_VIEW_NORMAL) {
3686                 return obj->base.size;
3687         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3688                 return intel_rotation_info_size(&view->params.rotated) << PAGE_SHIFT;
3689         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3690                 return view->params.partial.size << PAGE_SHIFT;
3691         } else {
3692                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3693                 return obj->base.size;
3694         }
3695 }
3696
3697 void __iomem *i915_vma_pin_iomap(struct i915_vma *vma)
3698 {
3699         void __iomem *ptr;
3700
3701         lockdep_assert_held(&vma->vm->dev->struct_mutex);
3702         if (WARN_ON(!vma->obj->map_and_fenceable))
3703                 return ERR_PTR(-ENODEV);
3704
3705         GEM_BUG_ON(!vma->is_ggtt);
3706         GEM_BUG_ON((vma->bound & GLOBAL_BIND) == 0);
3707
3708         ptr = vma->iomap;
3709         if (ptr == NULL) {
3710                 ptr = io_mapping_map_wc(i915_vm_to_ggtt(vma->vm)->mappable,
3711                                         vma->node.start,
3712                                         vma->node.size);
3713                 if (ptr == NULL)
3714                         return ERR_PTR(-ENOMEM);
3715
3716                 vma->iomap = ptr;
3717         }
3718
3719         vma->pin_count++;
3720         return ptr;
3721 }