drivers/gpu/drm/i915/i915_gem_gtt.c

   1 /*
   2  * Copyright © 2010 Daniel Vetter
   3  * Copyright © 2011-2014 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <linux/seq_file.h>
  27 #include <drm/drmP.h>
  28 #include <drm/i915_drm.h>
  29 #include "i915_drv.h"
  30 #include "i915_vgpu.h"
  31 #include "i915_trace.h"
  32 #include "intel_drv.h"
  33
  34 /**
  35  * DOC: Global GTT views
  36  *
  37  * Background and previous state
  38  *
  39  * Historically objects could exists (be bound) in global GTT space only as
  40  * singular instances with a view representing all of the object's backing pages
  41  * in a linear fashion. This view will be called a normal view.
  42  *
  43  * To support multiple views of the same object, where the number of mapped
  44  * pages is not equal to the backing store, or where the layout of the pages
  45  * is not linear, concept of a GGTT view was added.
  46  *
  47  * One example of an alternative view is a stereo display driven by a single
  48  * image. In this case we would have a framebuffer looking like this
  49  * (2x2 pages):
  50  *
  51  *    12
  52  *    34
  53  *
  54  * Above would represent a normal GGTT view as normally mapped for GPU or CPU
  55  * rendering. In contrast, fed to the display engine would be an alternative
  56  * view which could look something like this:
  57  *
  58  *   1212
  59  *   3434
  60  *
  61  * In this example both the size and layout of pages in the alternative view is
  62  * different from the normal view.
  63  *
  64  * Implementation and usage
  65  *
  66  * GGTT views are implemented using VMAs and are distinguished via enum
  67  * i915_ggtt_view_type and struct i915_ggtt_view.
  68  *
  69  * A new flavour of core GEM functions which work with GGTT bound objects were
  70  * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
  71  * renaming  in large amounts of code. They take the struct i915_ggtt_view
  72  * parameter encapsulating all metadata required to implement a view.
  73  *
  74  * As a helper for callers which are only interested in the normal view,
  75  * globally const i915_ggtt_view_normal singleton instance exists. All old core
  76  * GEM API functions, the ones not taking the view parameter, are operating on,
  77  * or with the normal GGTT view.
  78  *
  79  * Code wanting to add or use a new GGTT view needs to:
  80  *
  81  * 1. Add a new enum with a suitable name.
  82  * 2. Extend the metadata in the i915_ggtt_view structure if required.
  83  * 3. Add support to i915_get_vma_pages().
  84  *
  85  * New views are required to build a scatter-gather table from within the
  86  * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
  87  * exists for the lifetime of an VMA.
  88  *
  89  * Core API is designed to have copy semantics which means that passed in
  90  * struct i915_ggtt_view does not need to be persistent (left around after
  91  * calling the core API functions).
  92  *
  93  */
  94
  95 static int
  96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
  97
  98 const struct i915_ggtt_view i915_ggtt_view_normal;
  99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
 100         .type = I915_GGTT_VIEW_ROTATED
 101 };
 102
 103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
 104 {
 105         bool has_aliasing_ppgtt;
 106         bool has_full_ppgtt;
 107
 108         has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
 109         has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
 110
 111         if (intel_vgpu_active(dev))
 112                 has_full_ppgtt = false; /* emulation is too hard */
 113
 114         /*
 115          * We don't allow disabling PPGTT for gen9+ as it's a requirement for
 116          * execlists, the sole mechanism available to submit work.
 117          */
 118         if (INTEL_INFO(dev)->gen < 9 &&
 119             (enable_ppgtt == 0 || !has_aliasing_ppgtt))
 120                 return 0;
 121
 122         if (enable_ppgtt == 1)
 123                 return 1;
 124
 125         if (enable_ppgtt == 2 && has_full_ppgtt)
 126                 return 2;
 127
 128 #ifdef CONFIG_INTEL_IOMMU
 129         /* Disable ppgtt on SNB if VT-d is on. */
 130         if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
 131                 DRM_INFO("Disabling PPGTT because VT-d is on\n");
 132                 return 0;
 133         }
 134 #endif
 135
 136         /* Early VLV doesn't have this */
 137         if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
 138             dev->pdev->revision < 0xb) {
 139                 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
 140                 return 0;
 141         }
 142
 143         if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
 144                 return 2;
 145         else
 146                 return has_aliasing_ppgtt ? 1 : 0;
 147 }
 148
 149 static int ppgtt_bind_vma(struct i915_vma *vma,
 150                           enum i915_cache_level cache_level,
 151                           u32 unused)
 152 {
 153         u32 pte_flags = 0;
 154
 155         /* Currently applicable only to VLV */
 156         if (vma->obj->gt_ro)
 157                 pte_flags |= PTE_READ_ONLY;
 158
 159         vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
 160                                 cache_level, pte_flags);
 161
 162         return 0;
 163 }
 164
 165 static void ppgtt_unbind_vma(struct i915_vma *vma)
 166 {
 167         vma->vm->clear_range(vma->vm,
 168                              vma->node.start,
 169                              vma->obj->base.size,
 170                              true);
 171 }
 172
 173 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
 174                                   enum i915_cache_level level,
 175                                   bool valid)
 176 {
 177         gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
 178         pte |= addr;
 179
 180         switch (level) {
 181         case I915_CACHE_NONE:
 182                 pte |= PPAT_UNCACHED_INDEX;
 183                 break;
 184         case I915_CACHE_WT:
 185                 pte |= PPAT_DISPLAY_ELLC_INDEX;
 186                 break;
 187         default:
 188                 pte |= PPAT_CACHED_INDEX;
 189                 break;
 190         }
 191
 192         return pte;
 193 }
 194
 195 static gen8_pde_t gen8_pde_encode(struct drm_device *dev,
 196                                   dma_addr_t addr,
 197                                   enum i915_cache_level level)
 198 {
 199         gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
 200         pde |= addr;
 201         if (level != I915_CACHE_NONE)
 202                 pde |= PPAT_CACHED_PDE_INDEX;
 203         else
 204                 pde |= PPAT_UNCACHED_INDEX;
 205         return pde;
 206 }
 207
 208 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
 209                                  enum i915_cache_level level,
 210                                  bool valid, u32 unused)
 211 {
 212         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 213         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 214
 215         switch (level) {
 216         case I915_CACHE_L3_LLC:
 217         case I915_CACHE_LLC:
 218                 pte |= GEN6_PTE_CACHE_LLC;
 219                 break;
 220         case I915_CACHE_NONE:
 221                 pte |= GEN6_PTE_UNCACHED;
 222                 break;
 223         default:
 224                 MISSING_CASE(level);
 225         }
 226
 227         return pte;
 228 }
 229
 230 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
 231                                  enum i915_cache_level level,
 232                                  bool valid, u32 unused)
 233 {
 234         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 235         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 236
 237         switch (level) {
 238         case I915_CACHE_L3_LLC:
 239                 pte |= GEN7_PTE_CACHE_L3_LLC;
 240                 break;
 241         case I915_CACHE_LLC:
 242                 pte |= GEN6_PTE_CACHE_LLC;
 243                 break;
 244         case I915_CACHE_NONE:
 245                 pte |= GEN6_PTE_UNCACHED;
 246                 break;
 247         default:
 248                 MISSING_CASE(level);
 249         }
 250
 251         return pte;
 252 }
 253
 254 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
 255                                  enum i915_cache_level level,
 256                                  bool valid, u32 flags)
 257 {
 258         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 259         pte |= GEN6_PTE_ADDR_ENCODE(addr);
 260
 261         if (!(flags & PTE_READ_ONLY))
 262                 pte |= BYT_PTE_WRITEABLE;
 263
 264         if (level != I915_CACHE_NONE)
 265                 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
 266
 267         return pte;
 268 }
 269
 270 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
 271                                  enum i915_cache_level level,
 272                                  bool valid, u32 unused)
 273 {
 274         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 275         pte |= HSW_PTE_ADDR_ENCODE(addr);
 276
 277         if (level != I915_CACHE_NONE)
 278                 pte |= HSW_WB_LLC_AGE3;
 279
 280         return pte;
 281 }
 282
 283 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
 284                                   enum i915_cache_level level,
 285                                   bool valid, u32 unused)
 286 {
 287         gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
 288         pte |= HSW_PTE_ADDR_ENCODE(addr);
 289
 290         switch (level) {
 291         case I915_CACHE_NONE:
 292                 break;
 293         case I915_CACHE_WT:
 294                 pte |= HSW_WT_ELLC_LLC_AGE3;
 295                 break;
 296         default:
 297                 pte |= HSW_WB_ELLC_LLC_AGE3;
 298                 break;
 299         }
 300
 301         return pte;
 302 }
 303
 304 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 305 {
 306         struct device *device = &dev->pdev->dev;
 307
 308         p->page = alloc_page(GFP_KERNEL);
 309         if (!p->page)
 310                 return -ENOMEM;
 311
 312         p->daddr = dma_map_page(device,
 313                                 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
 314
 315         if (dma_mapping_error(device, p->daddr)) {
 316                 __free_page(p->page);
 317                 return -EINVAL;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
 324 {
 325         if (WARN_ON(!p->page))
 326                 return;
 327
 328         dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
 329         __free_page(p->page);
 330         memset(p, 0, sizeof(*p));
 331 }
 332
 333 static void *kmap_page_dma(struct i915_page_dma *p)
 334 {
 335         return kmap_atomic(p->page);
 336 }
 337
 338 /* We use the flushing unmap only with ppgtt structures:
 339  * page directories, page tables and scratch pages.
 340  */
 341 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
 342 {
 343         /* There are only few exceptions for gen >=6. chv and bxt.
 344          * And we are not sure about the latter so play safe for now.
 345          */
 346         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
 347                 drm_clflush_virt_range(vaddr, PAGE_SIZE);
 348
 349         kunmap_atomic(vaddr);
 350 }
 351
 352 #define kmap_px(px) kmap_page_dma(px_base(px))
 353 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
 354
 355 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
 356 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
 357 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
 358 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
 359
 360 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
 361                           const uint64_t val)
 362 {
 363         int i;
 364         uint64_t * const vaddr = kmap_page_dma(p);
 365
 366         for (i = 0; i < 512; i++)
 367                 vaddr[i] = val;
 368
 369         kunmap_page_dma(dev, vaddr);
 370 }
 371
 372 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
 373                              const uint32_t val32)
 374 {
 375         uint64_t v = val32;
 376
 377         v = v << 32 | val32;
 378
 379         fill_page_dma(dev, p, v);
 380 }
 381
 382 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
 383 {
 384         cleanup_px(dev, pt);
 385         kfree(pt->used_ptes);
 386         kfree(pt);
 387 }
 388
 389 static void gen8_initialize_pt(struct i915_address_space *vm,
 390                                struct i915_page_table *pt)
 391 {
 392         gen8_pte_t scratch_pte;
 393
 394         scratch_pte = gen8_pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
 395
 396         fill_px(vm->dev, pt, scratch_pte);
 397 }
 398
 399 static struct i915_page_table *alloc_pt(struct drm_device *dev)
 400 {
 401         struct i915_page_table *pt;
 402         const size_t count = INTEL_INFO(dev)->gen >= 8 ?
 403                 GEN8_PTES : GEN6_PTES;
 404         int ret = -ENOMEM;
 405
 406         pt = kzalloc(sizeof(*pt), GFP_KERNEL);
 407         if (!pt)
 408                 return ERR_PTR(-ENOMEM);
 409
 410         pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
 411                                 GFP_KERNEL);
 412
 413         if (!pt->used_ptes)
 414                 goto fail_bitmap;
 415
 416         ret = setup_px(dev, pt);
 417         if (ret)
 418                 goto fail_page_m;
 419
 420         return pt;
 421
 422 fail_page_m:
 423         kfree(pt->used_ptes);
 424 fail_bitmap:
 425         kfree(pt);
 426
 427         return ERR_PTR(ret);
 428 }
 429
 430 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
 431 {
 432         if (px_page(pd)) {
 433                 cleanup_px(dev, pd);
 434                 kfree(pd->used_pdes);
 435                 kfree(pd);
 436         }
 437 }
 438
 439 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
 440 {
 441         struct i915_page_directory *pd;
 442         int ret = -ENOMEM;
 443
 444         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 445         if (!pd)
 446                 return ERR_PTR(-ENOMEM);
 447
 448         pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
 449                                 sizeof(*pd->used_pdes), GFP_KERNEL);
 450         if (!pd->used_pdes)
 451                 goto fail_bitmap;
 452
 453         ret = setup_px(dev, pd);
 454         if (ret)
 455                 goto fail_page_m;
 456
 457         return pd;
 458
 459 fail_page_m:
 460         kfree(pd->used_pdes);
 461 fail_bitmap:
 462         kfree(pd);
 463
 464         return ERR_PTR(ret);
 465 }
 466
 467 /* Broadwell Page Directory Pointer Descriptors */
 468 static int gen8_write_pdp(struct drm_i915_gem_request *req,
 469                           unsigned entry,
 470                           dma_addr_t addr)
 471 {
 472         struct intel_engine_cs *ring = req->ring;
 473         int ret;
 474
 475         BUG_ON(entry >= 4);
 476
 477         ret = intel_ring_begin(req, 6);
 478         if (ret)
 479                 return ret;
 480
 481         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 482         intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
 483         intel_ring_emit(ring, upper_32_bits(addr));
 484         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 485         intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
 486         intel_ring_emit(ring, lower_32_bits(addr));
 487         intel_ring_advance(ring);
 488
 489         return 0;
 490 }
 491
 492 static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt,
 493                           struct drm_i915_gem_request *req)
 494 {
 495         int i, ret;
 496
 497         for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
 498                 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
 499
 500                 ret = gen8_write_pdp(req, i, pd_daddr);
 501                 if (ret)
 502                         return ret;
 503         }
 504
 505         return 0;
 506 }
 507
 508 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
 509                                    uint64_t start,
 510                                    uint64_t length,
 511                                    bool use_scratch)
 512 {
 513         struct i915_hw_ppgtt *ppgtt =
 514                 container_of(vm, struct i915_hw_ppgtt, base);
 515         gen8_pte_t *pt_vaddr, scratch_pte;
 516         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 517         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 518         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 519         unsigned num_entries = length >> PAGE_SHIFT;
 520         unsigned last_pte, i;
 521
 522         scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr,
 523                                       I915_CACHE_LLC, use_scratch);
 524
 525         while (num_entries) {
 526                 struct i915_page_directory *pd;
 527                 struct i915_page_table *pt;
 528
 529                 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe]))
 530                         continue;
 531
 532                 pd = ppgtt->pdp.page_directory[pdpe];
 533
 534                 if (WARN_ON(!pd->page_table[pde]))
 535                         continue;
 536
 537                 pt = pd->page_table[pde];
 538
 539                 if (WARN_ON(!px_page(pt)))
 540                         continue;
 541
 542                 last_pte = pte + num_entries;
 543                 if (last_pte > GEN8_PTES)
 544                         last_pte = GEN8_PTES;
 545
 546                 pt_vaddr = kmap_px(pt);
 547
 548                 for (i = pte; i < last_pte; i++) {
 549                         pt_vaddr[i] = scratch_pte;
 550                         num_entries--;
 551                 }
 552
 553                 kunmap_px(ppgtt, pt);
 554
 555                 pte = 0;
 556                 if (++pde == I915_PDES) {
 557                         pdpe++;
 558                         pde = 0;
 559                 }
 560         }
 561 }
 562
 563 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
 564                                       struct sg_table *pages,
 565                                       uint64_t start,
 566                                       enum i915_cache_level cache_level, u32 unused)
 567 {
 568         struct i915_hw_ppgtt *ppgtt =
 569                 container_of(vm, struct i915_hw_ppgtt, base);
 570         gen8_pte_t *pt_vaddr;
 571         unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK;
 572         unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK;
 573         unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK;
 574         struct sg_page_iter sg_iter;
 575
 576         pt_vaddr = NULL;
 577
 578         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
 579                 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES))
 580                         break;
 581
 582                 if (pt_vaddr == NULL) {
 583                         struct i915_page_directory *pd = ppgtt->pdp.page_directory[pdpe];
 584                         struct i915_page_table *pt = pd->page_table[pde];
 585                         pt_vaddr = kmap_px(pt);
 586                 }
 587
 588                 pt_vaddr[pte] =
 589                         gen8_pte_encode(sg_page_iter_dma_address(&sg_iter),
 590                                         cache_level, true);
 591                 if (++pte == GEN8_PTES) {
 592                         kunmap_px(ppgtt, pt_vaddr);
 593                         pt_vaddr = NULL;
 594                         if (++pde == I915_PDES) {
 595                                 pdpe++;
 596                                 pde = 0;
 597                         }
 598                         pte = 0;
 599                 }
 600         }
 601
 602         if (pt_vaddr)
 603                 kunmap_px(ppgtt, pt_vaddr);
 604 }
 605
 606 static void __gen8_do_map_pt(gen8_pde_t * const pde,
 607                              struct i915_page_table *pt,
 608                              struct drm_device *dev)
 609 {
 610         gen8_pde_t entry =
 611                 gen8_pde_encode(dev, px_dma(pt), I915_CACHE_LLC);
 612         *pde = entry;
 613 }
 614
 615 static void gen8_initialize_pd(struct i915_address_space *vm,
 616                                struct i915_page_directory *pd)
 617 {
 618         struct i915_hw_ppgtt *ppgtt =
 619                 container_of(vm, struct i915_hw_ppgtt, base);
 620         gen8_pde_t scratch_pde;
 621
 622         scratch_pde = gen8_pde_encode(vm->dev, px_dma(ppgtt->scratch_pt),
 623                                       I915_CACHE_LLC);
 624
 625         fill_px(vm->dev, pd, scratch_pde);
 626 }
 627
 628 static void gen8_free_page_tables(struct i915_page_directory *pd, struct drm_device *dev)
 629 {
 630         int i;
 631
 632         if (!px_page(pd))
 633                 return;
 634
 635         for_each_set_bit(i, pd->used_pdes, I915_PDES) {
 636                 if (WARN_ON(!pd->page_table[i]))
 637                         continue;
 638
 639                 free_pt(dev, pd->page_table[i]);
 640                 pd->page_table[i] = NULL;
 641         }
 642 }
 643
 644 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
 645 {
 646         struct i915_hw_ppgtt *ppgtt =
 647                 container_of(vm, struct i915_hw_ppgtt, base);
 648         int i;
 649
 650         for_each_set_bit(i, ppgtt->pdp.used_pdpes, GEN8_LEGACY_PDPES) {
 651                 if (WARN_ON(!ppgtt->pdp.page_directory[i]))
 652                         continue;
 653
 654                 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev);
 655                 free_pd(ppgtt->base.dev, ppgtt->pdp.page_directory[i]);
 656         }
 657
 658         free_pd(ppgtt->base.dev, ppgtt->scratch_pd);
 659         free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
 660 }
 661
 662 /**
 663  * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
 664  * @ppgtt:      Master ppgtt structure.
 665  * @pd:         Page directory for this address range.
 666  * @start:      Starting virtual address to begin allocations.
 667  * @length      Size of the allocations.
 668  * @new_pts:    Bitmap set by function with new allocations. Likely used by the
 669  *              caller to free on error.
 670  *
 671  * Allocate the required number of page tables. Extremely similar to
 672  * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
 673  * the page directory boundary (instead of the page directory pointer). That
 674  * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
 675  * possible, and likely that the caller will need to use multiple calls of this
 676  * function to achieve the appropriate allocation.
 677  *
 678  * Return: 0 if success; negative error code otherwise.
 679  */
 680 static int gen8_ppgtt_alloc_pagetabs(struct i915_hw_ppgtt *ppgtt,
 681                                      struct i915_page_directory *pd,
 682                                      uint64_t start,
 683                                      uint64_t length,
 684                                      unsigned long *new_pts)
 685 {
 686         struct drm_device *dev = ppgtt->base.dev;
 687         struct i915_page_table *pt;
 688         uint64_t temp;
 689         uint32_t pde;
 690
 691         gen8_for_each_pde(pt, pd, start, length, temp, pde) {
 692                 /* Don't reallocate page tables */
 693                 if (pt) {
 694                         /* Scratch is never allocated this way */
 695                         WARN_ON(pt == ppgtt->scratch_pt);
 696                         continue;
 697                 }
 698
 699                 pt = alloc_pt(dev);
 700                 if (IS_ERR(pt))
 701                         goto unwind_out;
 702
 703                 gen8_initialize_pt(&ppgtt->base, pt);
 704                 pd->page_table[pde] = pt;
 705                 set_bit(pde, new_pts);
 706         }
 707
 708         return 0;
 709
 710 unwind_out:
 711         for_each_set_bit(pde, new_pts, I915_PDES)
 712                 free_pt(dev, pd->page_table[pde]);
 713
 714         return -ENOMEM;
 715 }
 716
 717 /**
 718  * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
 719  * @ppgtt:      Master ppgtt structure.
 720  * @pdp:        Page directory pointer for this address range.
 721  * @start:      Starting virtual address to begin allocations.
 722  * @length      Size of the allocations.
 723  * @new_pds     Bitmap set by function with new allocations. Likely used by the
 724  *              caller to free on error.
 725  *
 726  * Allocate the required number of page directories starting at the pde index of
 727  * @start, and ending at the pde index @start + @length. This function will skip
 728  * over already allocated page directories within the range, and only allocate
 729  * new ones, setting the appropriate pointer within the pdp as well as the
 730  * correct position in the bitmap @new_pds.
 731  *
 732  * The function will only allocate the pages within the range for a give page
 733  * directory pointer. In other words, if @start + @length straddles a virtually
 734  * addressed PDP boundary (512GB for 4k pages), there will be more allocations
 735  * required by the caller, This is not currently possible, and the BUG in the
 736  * code will prevent it.
 737  *
 738  * Return: 0 if success; negative error code otherwise.
 739  */
 740 static int gen8_ppgtt_alloc_page_directories(struct i915_hw_ppgtt *ppgtt,
 741                                      struct i915_page_directory_pointer *pdp,
 742                                      uint64_t start,
 743                                      uint64_t length,
 744                                      unsigned long *new_pds)
 745 {
 746         struct drm_device *dev = ppgtt->base.dev;
 747         struct i915_page_directory *pd;
 748         uint64_t temp;
 749         uint32_t pdpe;
 750
 751         WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES));
 752
 753         gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
 754                 if (pd)
 755                         continue;
 756
 757                 pd = alloc_pd(dev);
 758                 if (IS_ERR(pd))
 759                         goto unwind_out;
 760
 761                 gen8_initialize_pd(&ppgtt->base, pd);
 762                 pdp->page_directory[pdpe] = pd;
 763                 set_bit(pdpe, new_pds);
 764         }
 765
 766         return 0;
 767
 768 unwind_out:
 769         for_each_set_bit(pdpe, new_pds, GEN8_LEGACY_PDPES)
 770                 free_pd(dev, pdp->page_directory[pdpe]);
 771
 772         return -ENOMEM;
 773 }
 774
 775 static void
 776 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long **new_pts)
 777 {
 778         int i;
 779
 780         for (i = 0; i < GEN8_LEGACY_PDPES; i++)
 781                 kfree(new_pts[i]);
 782         kfree(new_pts);
 783         kfree(new_pds);
 784 }
 785
 786 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
 787  * of these are based on the number of PDPEs in the system.
 788  */
 789 static
 790 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
 791                                          unsigned long ***new_pts)
 792 {
 793         int i;
 794         unsigned long *pds;
 795         unsigned long **pts;
 796
 797         pds = kcalloc(BITS_TO_LONGS(GEN8_LEGACY_PDPES), sizeof(unsigned long), GFP_KERNEL);
 798         if (!pds)
 799                 return -ENOMEM;
 800
 801         pts = kcalloc(GEN8_LEGACY_PDPES, sizeof(unsigned long *), GFP_KERNEL);
 802         if (!pts) {
 803                 kfree(pds);
 804                 return -ENOMEM;
 805         }
 806
 807         for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
 808                 pts[i] = kcalloc(BITS_TO_LONGS(I915_PDES),
 809                                  sizeof(unsigned long), GFP_KERNEL);
 810                 if (!pts[i])
 811                         goto err_out;
 812         }
 813
 814         *new_pds = pds;
 815         *new_pts = pts;
 816
 817         return 0;
 818
 819 err_out:
 820         free_gen8_temp_bitmaps(pds, pts);
 821         return -ENOMEM;
 822 }
 823
 824 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
 825  * the page table structures, we mark them dirty so that
 826  * context switching/execlist queuing code takes extra steps
 827  * to ensure that tlbs are flushed.
 828  */
 829 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
 830 {
 831         ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
 832 }
 833
 834 static int gen8_alloc_va_range(struct i915_address_space *vm,
 835                                uint64_t start,
 836                                uint64_t length)
 837 {
 838         struct i915_hw_ppgtt *ppgtt =
 839                 container_of(vm, struct i915_hw_ppgtt, base);
 840         unsigned long *new_page_dirs, **new_page_tables;
 841         struct i915_page_directory *pd;
 842         const uint64_t orig_start = start;
 843         const uint64_t orig_length = length;
 844         uint64_t temp;
 845         uint32_t pdpe;
 846         int ret;
 847
 848         /* Wrap is never okay since we can only represent 48b, and we don't
 849          * actually use the other side of the canonical address space.
 850          */
 851         if (WARN_ON(start + length < start))
 852                 return -ENODEV;
 853
 854         if (WARN_ON(start + length > ppgtt->base.total))
 855                 return -ENODEV;
 856
 857         ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables);
 858         if (ret)
 859                 return ret;
 860
 861         /* Do the allocations first so we can easily bail out */
 862         ret = gen8_ppgtt_alloc_page_directories(ppgtt, &ppgtt->pdp, start, length,
 863                                         new_page_dirs);
 864         if (ret) {
 865                 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 866                 return ret;
 867         }
 868
 869         /* For every page directory referenced, allocate page tables */
 870         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 871                 ret = gen8_ppgtt_alloc_pagetabs(ppgtt, pd, start, length,
 872                                                 new_page_tables[pdpe]);
 873                 if (ret)
 874                         goto err_out;
 875         }
 876
 877         start = orig_start;
 878         length = orig_length;
 879
 880         /* Allocations have completed successfully, so set the bitmaps, and do
 881          * the mappings. */
 882         gen8_for_each_pdpe(pd, &ppgtt->pdp, start, length, temp, pdpe) {
 883                 gen8_pde_t *const page_directory = kmap_px(pd);
 884                 struct i915_page_table *pt;
 885                 uint64_t pd_len = gen8_clamp_pd(start, length);
 886                 uint64_t pd_start = start;
 887                 uint32_t pde;
 888
 889                 /* Every pd should be allocated, we just did that above. */
 890                 WARN_ON(!pd);
 891
 892                 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
 893                         /* Same reasoning as pd */
 894                         WARN_ON(!pt);
 895                         WARN_ON(!pd_len);
 896                         WARN_ON(!gen8_pte_count(pd_start, pd_len));
 897
 898                         /* Set our used ptes within the page table */
 899                         bitmap_set(pt->used_ptes,
 900                                    gen8_pte_index(pd_start),
 901                                    gen8_pte_count(pd_start, pd_len));
 902
 903                         /* Our pde is now pointing to the pagetable, pt */
 904                         set_bit(pde, pd->used_pdes);
 905
 906                         /* Map the PDE to the page table */
 907                         __gen8_do_map_pt(page_directory + pde, pt, vm->dev);
 908
 909                         /* NB: We haven't yet mapped ptes to pages. At this
 910                          * point we're still relying on insert_entries() */
 911                 }
 912
 913                 kunmap_px(ppgtt, page_directory);
 914
 915                 set_bit(pdpe, ppgtt->pdp.used_pdpes);
 916         }
 917
 918         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 919         mark_tlbs_dirty(ppgtt);
 920         return 0;
 921
 922 err_out:
 923         while (pdpe--) {
 924                 for_each_set_bit(temp, new_page_tables[pdpe], I915_PDES)
 925                         free_pt(vm->dev, ppgtt->pdp.page_directory[pdpe]->page_table[temp]);
 926         }
 927
 928         for_each_set_bit(pdpe, new_page_dirs, GEN8_LEGACY_PDPES)
 929                 free_pd(vm->dev, ppgtt->pdp.page_directory[pdpe]);
 930
 931         free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
 932         mark_tlbs_dirty(ppgtt);
 933         return ret;
 934 }
 935
 936 /*
 937  * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
 938  * with a net effect resembling a 2-level page table in normal x86 terms. Each
 939  * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
 940  * space.
 941  *
 942  */
 943 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
 944 {
 945         ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
 946         if (IS_ERR(ppgtt->scratch_pt))
 947                 return PTR_ERR(ppgtt->scratch_pt);
 948
 949         ppgtt->scratch_pd = alloc_pd(ppgtt->base.dev);
 950         if (IS_ERR(ppgtt->scratch_pd))
 951                 return PTR_ERR(ppgtt->scratch_pd);
 952
 953         gen8_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
 954         gen8_initialize_pd(&ppgtt->base, ppgtt->scratch_pd);
 955
 956         ppgtt->base.start = 0;
 957         ppgtt->base.total = 1ULL << 32;
 958         if (IS_ENABLED(CONFIG_X86_32))
 959                 /* While we have a proliferation of size_t variables
 960                  * we cannot represent the full ppgtt size on 32bit,
 961                  * so limit it to the same size as the GGTT (currently
 962                  * 2GiB).
 963                  */
 964                 ppgtt->base.total = to_i915(ppgtt->base.dev)->gtt.base.total;
 965         ppgtt->base.cleanup = gen8_ppgtt_cleanup;
 966         ppgtt->base.allocate_va_range = gen8_alloc_va_range;
 967         ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
 968         ppgtt->base.clear_range = gen8_ppgtt_clear_range;
 969         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
 970         ppgtt->base.bind_vma = ppgtt_bind_vma;
 971
 972         ppgtt->switch_mm = gen8_mm_switch;
 973
 974         return 0;
 975 }
 976
 977 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
 978 {
 979         struct i915_address_space *vm = &ppgtt->base;
 980         struct i915_page_table *unused;
 981         gen6_pte_t scratch_pte;
 982         uint32_t pd_entry;
 983         uint32_t  pte, pde, temp;
 984         uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
 985
 986         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
 987
 988         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
 989                 u32 expected;
 990                 gen6_pte_t *pt_vaddr;
 991                 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
 992                 pd_entry = readl(ppgtt->pd_addr + pde);
 993                 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
 994
 995                 if (pd_entry != expected)
 996                         seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
 997                                    pde,
 998                                    pd_entry,
 999                                    expected);
1000                 seq_printf(m, "\tPDE: %x\n", pd_entry);
1001
1002                 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1003
1004                 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1005                         unsigned long va =
1006                                 (pde * PAGE_SIZE * GEN6_PTES) +
1007                                 (pte * PAGE_SIZE);
1008                         int i;
1009                         bool found = false;
1010                         for (i = 0; i < 4; i++)
1011                                 if (pt_vaddr[pte + i] != scratch_pte)
1012                                         found = true;
1013                         if (!found)
1014                                 continue;
1015
1016                         seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1017                         for (i = 0; i < 4; i++) {
1018                                 if (pt_vaddr[pte + i] != scratch_pte)
1019                                         seq_printf(m, " %08x", pt_vaddr[pte + i]);
1020                                 else
1021                                         seq_puts(m, "  SCRATCH ");
1022                         }
1023                         seq_puts(m, "\n");
1024                 }
1025                 kunmap_px(ppgtt, pt_vaddr);
1026         }
1027 }
1028
1029 /* Write pde (index) from the page directory @pd to the page table @pt */
1030 static void gen6_write_pde(struct i915_page_directory *pd,
1031                             const int pde, struct i915_page_table *pt)
1032 {
1033         /* Caller needs to make sure the write completes if necessary */
1034         struct i915_hw_ppgtt *ppgtt =
1035                 container_of(pd, struct i915_hw_ppgtt, pd);
1036         u32 pd_entry;
1037
1038         pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1039         pd_entry |= GEN6_PDE_VALID;
1040
1041         writel(pd_entry, ppgtt->pd_addr + pde);
1042 }
1043
1044 /* Write all the page tables found in the ppgtt structure to incrementing page
1045  * directories. */
1046 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1047                                   struct i915_page_directory *pd,
1048                                   uint32_t start, uint32_t length)
1049 {
1050         struct i915_page_table *pt;
1051         uint32_t pde, temp;
1052
1053         gen6_for_each_pde(pt, pd, start, length, temp, pde)
1054                 gen6_write_pde(pd, pde, pt);
1055
1056         /* Make sure write is complete before other code can use this page
1057          * table. Also require for WC mapped PTEs */
1058         readl(dev_priv->gtt.gsm);
1059 }
1060
1061 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1062 {
1063         BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1064
1065         return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1066 }
1067
1068 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1069                          struct drm_i915_gem_request *req)
1070 {
1071         struct intel_engine_cs *ring = req->ring;
1072         int ret;
1073
1074         /* NB: TLBs must be flushed and invalidated before a switch */
1075         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1076         if (ret)
1077                 return ret;
1078
1079         ret = intel_ring_begin(req, 6);
1080         if (ret)
1081                 return ret;
1082
1083         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1084         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1085         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1086         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1087         intel_ring_emit(ring, get_pd_offset(ppgtt));
1088         intel_ring_emit(ring, MI_NOOP);
1089         intel_ring_advance(ring);
1090
1091         return 0;
1092 }
1093
1094 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1095                           struct drm_i915_gem_request *req)
1096 {
1097         struct intel_engine_cs *ring = req->ring;
1098         struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1099
1100         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1101         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1102         return 0;
1103 }
1104
1105 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1106                           struct drm_i915_gem_request *req)
1107 {
1108         struct intel_engine_cs *ring = req->ring;
1109         int ret;
1110
1111         /* NB: TLBs must be flushed and invalidated before a switch */
1112         ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1113         if (ret)
1114                 return ret;
1115
1116         ret = intel_ring_begin(req, 6);
1117         if (ret)
1118                 return ret;
1119
1120         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1121         intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1122         intel_ring_emit(ring, PP_DIR_DCLV_2G);
1123         intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1124         intel_ring_emit(ring, get_pd_offset(ppgtt));
1125         intel_ring_emit(ring, MI_NOOP);
1126         intel_ring_advance(ring);
1127
1128         /* XXX: RCS is the only one to auto invalidate the TLBs? */
1129         if (ring->id != RCS) {
1130                 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1131                 if (ret)
1132                         return ret;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1139                           struct drm_i915_gem_request *req)
1140 {
1141         struct intel_engine_cs *ring = req->ring;
1142         struct drm_device *dev = ppgtt->base.dev;
1143         struct drm_i915_private *dev_priv = dev->dev_private;
1144
1145
1146         I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1147         I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1148
1149         POSTING_READ(RING_PP_DIR_DCLV(ring));
1150
1151         return 0;
1152 }
1153
1154 static void gen8_ppgtt_enable(struct drm_device *dev)
1155 {
1156         struct drm_i915_private *dev_priv = dev->dev_private;
1157         struct intel_engine_cs *ring;
1158         int j;
1159
1160         for_each_ring(ring, dev_priv, j) {
1161                 I915_WRITE(RING_MODE_GEN7(ring),
1162                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1163         }
1164 }
1165
1166 static void gen7_ppgtt_enable(struct drm_device *dev)
1167 {
1168         struct drm_i915_private *dev_priv = dev->dev_private;
1169         struct intel_engine_cs *ring;
1170         uint32_t ecochk, ecobits;
1171         int i;
1172
1173         ecobits = I915_READ(GAC_ECO_BITS);
1174         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1175
1176         ecochk = I915_READ(GAM_ECOCHK);
1177         if (IS_HASWELL(dev)) {
1178                 ecochk |= ECOCHK_PPGTT_WB_HSW;
1179         } else {
1180                 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1181                 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1182         }
1183         I915_WRITE(GAM_ECOCHK, ecochk);
1184
1185         for_each_ring(ring, dev_priv, i) {
1186                 /* GFX_MODE is per-ring on gen7+ */
1187                 I915_WRITE(RING_MODE_GEN7(ring),
1188                            _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1189         }
1190 }
1191
1192 static void gen6_ppgtt_enable(struct drm_device *dev)
1193 {
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         uint32_t ecochk, gab_ctl, ecobits;
1196
1197         ecobits = I915_READ(GAC_ECO_BITS);
1198         I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1199                    ECOBITS_PPGTT_CACHE64B);
1200
1201         gab_ctl = I915_READ(GAB_CTL);
1202         I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1203
1204         ecochk = I915_READ(GAM_ECOCHK);
1205         I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1206
1207         I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1208 }
1209
1210 /* PPGTT support for Sandybdrige/Gen6 and later */
1211 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1212                                    uint64_t start,
1213                                    uint64_t length,
1214                                    bool use_scratch)
1215 {
1216         struct i915_hw_ppgtt *ppgtt =
1217                 container_of(vm, struct i915_hw_ppgtt, base);
1218         gen6_pte_t *pt_vaddr, scratch_pte;
1219         unsigned first_entry = start >> PAGE_SHIFT;
1220         unsigned num_entries = length >> PAGE_SHIFT;
1221         unsigned act_pt = first_entry / GEN6_PTES;
1222         unsigned first_pte = first_entry % GEN6_PTES;
1223         unsigned last_pte, i;
1224
1225         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1226
1227         while (num_entries) {
1228                 last_pte = first_pte + num_entries;
1229                 if (last_pte > GEN6_PTES)
1230                         last_pte = GEN6_PTES;
1231
1232                 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1233
1234                 for (i = first_pte; i < last_pte; i++)
1235                         pt_vaddr[i] = scratch_pte;
1236
1237                 kunmap_px(ppgtt, pt_vaddr);
1238
1239                 num_entries -= last_pte - first_pte;
1240                 first_pte = 0;
1241                 act_pt++;
1242         }
1243 }
1244
1245 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1246                                       struct sg_table *pages,
1247                                       uint64_t start,
1248                                       enum i915_cache_level cache_level, u32 flags)
1249 {
1250         struct i915_hw_ppgtt *ppgtt =
1251                 container_of(vm, struct i915_hw_ppgtt, base);
1252         gen6_pte_t *pt_vaddr;
1253         unsigned first_entry = start >> PAGE_SHIFT;
1254         unsigned act_pt = first_entry / GEN6_PTES;
1255         unsigned act_pte = first_entry % GEN6_PTES;
1256         struct sg_page_iter sg_iter;
1257
1258         pt_vaddr = NULL;
1259         for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1260                 if (pt_vaddr == NULL)
1261                         pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1262
1263                 pt_vaddr[act_pte] =
1264                         vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1265                                        cache_level, true, flags);
1266
1267                 if (++act_pte == GEN6_PTES) {
1268                         kunmap_px(ppgtt, pt_vaddr);
1269                         pt_vaddr = NULL;
1270                         act_pt++;
1271                         act_pte = 0;
1272                 }
1273         }
1274         if (pt_vaddr)
1275                 kunmap_px(ppgtt, pt_vaddr);
1276 }
1277
1278 static void gen6_initialize_pt(struct i915_address_space *vm,
1279                                struct i915_page_table *pt)
1280 {
1281         gen6_pte_t scratch_pte;
1282
1283         WARN_ON(vm->scratch.addr == 0);
1284
1285         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0);
1286
1287         fill32_px(vm->dev, pt, scratch_pte);
1288 }
1289
1290 static int gen6_alloc_va_range(struct i915_address_space *vm,
1291                                uint64_t start_in, uint64_t length_in)
1292 {
1293         DECLARE_BITMAP(new_page_tables, I915_PDES);
1294         struct drm_device *dev = vm->dev;
1295         struct drm_i915_private *dev_priv = dev->dev_private;
1296         struct i915_hw_ppgtt *ppgtt =
1297                                 container_of(vm, struct i915_hw_ppgtt, base);
1298         struct i915_page_table *pt;
1299         uint32_t start, length, start_save, length_save;
1300         uint32_t pde, temp;
1301         int ret;
1302
1303         if (WARN_ON(start_in + length_in > ppgtt->base.total))
1304                 return -ENODEV;
1305
1306         start = start_save = start_in;
1307         length = length_save = length_in;
1308
1309         bitmap_zero(new_page_tables, I915_PDES);
1310
1311         /* The allocation is done in two stages so that we can bail out with
1312          * minimal amount of pain. The first stage finds new page tables that
1313          * need allocation. The second stage marks use ptes within the page
1314          * tables.
1315          */
1316         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1317                 if (pt != ppgtt->scratch_pt) {
1318                         WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1319                         continue;
1320                 }
1321
1322                 /* We've already allocated a page table */
1323                 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1324
1325                 pt = alloc_pt(dev);
1326                 if (IS_ERR(pt)) {
1327                         ret = PTR_ERR(pt);
1328                         goto unwind_out;
1329                 }
1330
1331                 gen6_initialize_pt(vm, pt);
1332
1333                 ppgtt->pd.page_table[pde] = pt;
1334                 set_bit(pde, new_page_tables);
1335                 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1336         }
1337
1338         start = start_save;
1339         length = length_save;
1340
1341         gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1342                 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1343
1344                 bitmap_zero(tmp_bitmap, GEN6_PTES);
1345                 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1346                            gen6_pte_count(start, length));
1347
1348                 if (test_and_clear_bit(pde, new_page_tables))
1349                         gen6_write_pde(&ppgtt->pd, pde, pt);
1350
1351                 trace_i915_page_table_entry_map(vm, pde, pt,
1352                                          gen6_pte_index(start),
1353                                          gen6_pte_count(start, length),
1354                                          GEN6_PTES);
1355                 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1356                                 GEN6_PTES);
1357         }
1358
1359         WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1360
1361         /* Make sure write is complete before other code can use this page
1362          * table. Also require for WC mapped PTEs */
1363         readl(dev_priv->gtt.gsm);
1364
1365         mark_tlbs_dirty(ppgtt);
1366         return 0;
1367
1368 unwind_out:
1369         for_each_set_bit(pde, new_page_tables, I915_PDES) {
1370                 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1371
1372                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1373                 free_pt(vm->dev, pt);
1374         }
1375
1376         mark_tlbs_dirty(ppgtt);
1377         return ret;
1378 }
1379
1380 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1381 {
1382         struct i915_hw_ppgtt *ppgtt =
1383                 container_of(vm, struct i915_hw_ppgtt, base);
1384         struct i915_page_table *pt;
1385         uint32_t pde;
1386
1387
1388         drm_mm_remove_node(&ppgtt->node);
1389
1390         gen6_for_all_pdes(pt, ppgtt, pde) {
1391                 if (pt != ppgtt->scratch_pt)
1392                         free_pt(ppgtt->base.dev, pt);
1393         }
1394
1395         free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
1396 }
1397
1398 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1399 {
1400         struct drm_device *dev = ppgtt->base.dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402         bool retried = false;
1403         int ret;
1404
1405         /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1406          * allocator works in address space sizes, so it's multiplied by page
1407          * size. We allocate at the top of the GTT to avoid fragmentation.
1408          */
1409         BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
1410         ppgtt->scratch_pt = alloc_pt(ppgtt->base.dev);
1411         if (IS_ERR(ppgtt->scratch_pt))
1412                 return PTR_ERR(ppgtt->scratch_pt);
1413
1414         gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt);
1415
1416 alloc:
1417         ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
1418                                                   &ppgtt->node, GEN6_PD_SIZE,
1419                                                   GEN6_PD_ALIGN, 0,
1420                                                   0, dev_priv->gtt.base.total,
1421                                                   DRM_MM_TOPDOWN);
1422         if (ret == -ENOSPC && !retried) {
1423                 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
1424                                                GEN6_PD_SIZE, GEN6_PD_ALIGN,
1425                                                I915_CACHE_NONE,
1426                                                0, dev_priv->gtt.base.total,
1427                                                0);
1428                 if (ret)
1429                         goto err_out;
1430
1431                 retried = true;
1432                 goto alloc;
1433         }
1434
1435         if (ret)
1436                 goto err_out;
1437
1438
1439         if (ppgtt->node.start < dev_priv->gtt.mappable_end)
1440                 DRM_DEBUG("Forced to use aperture for PDEs\n");
1441
1442         return 0;
1443
1444 err_out:
1445         free_pt(ppgtt->base.dev, ppgtt->scratch_pt);
1446         return ret;
1447 }
1448
1449 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1450 {
1451         return gen6_ppgtt_allocate_page_directories(ppgtt);
1452 }
1453
1454 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1455                                   uint64_t start, uint64_t length)
1456 {
1457         struct i915_page_table *unused;
1458         uint32_t pde, temp;
1459
1460         gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
1461                 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt;
1462 }
1463
1464 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1465 {
1466         struct drm_device *dev = ppgtt->base.dev;
1467         struct drm_i915_private *dev_priv = dev->dev_private;
1468         int ret;
1469
1470         ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
1471         if (IS_GEN6(dev)) {
1472                 ppgtt->switch_mm = gen6_mm_switch;
1473         } else if (IS_HASWELL(dev)) {
1474                 ppgtt->switch_mm = hsw_mm_switch;
1475         } else if (IS_GEN7(dev)) {
1476                 ppgtt->switch_mm = gen7_mm_switch;
1477         } else
1478                 BUG();
1479
1480         if (intel_vgpu_active(dev))
1481                 ppgtt->switch_mm = vgpu_mm_switch;
1482
1483         ret = gen6_ppgtt_alloc(ppgtt);
1484         if (ret)
1485                 return ret;
1486
1487         ppgtt->base.allocate_va_range = gen6_alloc_va_range;
1488         ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1489         ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1490         ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1491         ppgtt->base.bind_vma = ppgtt_bind_vma;
1492         ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1493         ppgtt->base.start = 0;
1494         ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1495         ppgtt->debug_dump = gen6_dump_ppgtt;
1496
1497         ppgtt->pd.base.ggtt_offset =
1498                 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1499
1500         ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
1501                 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1502
1503         gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1504
1505         gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
1506
1507         DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1508                          ppgtt->node.size >> 20,
1509                          ppgtt->node.start / PAGE_SIZE);
1510
1511         DRM_DEBUG("Adding PPGTT at offset %x\n",
1512                   ppgtt->pd.base.ggtt_offset << 10);
1513
1514         return 0;
1515 }
1516
1517 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1518 {
1519         struct drm_i915_private *dev_priv = dev->dev_private;
1520
1521         ppgtt->base.dev = dev;
1522         ppgtt->base.scratch = dev_priv->gtt.base.scratch;
1523
1524         if (INTEL_INFO(dev)->gen < 8)
1525                 return gen6_ppgtt_init(ppgtt);
1526         else
1527                 return gen8_ppgtt_init(ppgtt);
1528 }
1529 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
1530 {
1531         struct drm_i915_private *dev_priv = dev->dev_private;
1532         int ret = 0;
1533
1534         ret = __hw_ppgtt_init(dev, ppgtt);
1535         if (ret == 0) {
1536                 kref_init(&ppgtt->ref);
1537                 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start,
1538                             ppgtt->base.total);
1539                 i915_init_vm(dev_priv, &ppgtt->base);
1540         }
1541
1542         return ret;
1543 }
1544
1545 int i915_ppgtt_init_hw(struct drm_device *dev)
1546 {
1547         /* In the case of execlists, PPGTT is enabled by the context descriptor
1548          * and the PDPs are contained within the context itself.  We don't
1549          * need to do anything here. */
1550         if (i915.enable_execlists)
1551                 return 0;
1552
1553         if (!USES_PPGTT(dev))
1554                 return 0;
1555
1556         if (IS_GEN6(dev))
1557                 gen6_ppgtt_enable(dev);
1558         else if (IS_GEN7(dev))
1559                 gen7_ppgtt_enable(dev);
1560         else if (INTEL_INFO(dev)->gen >= 8)
1561                 gen8_ppgtt_enable(dev);
1562         else
1563                 MISSING_CASE(INTEL_INFO(dev)->gen);
1564
1565         return 0;
1566 }
1567
1568 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
1569 {
1570         struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
1571         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1572
1573         if (i915.enable_execlists)
1574                 return 0;
1575
1576         if (!ppgtt)
1577                 return 0;
1578
1579         return ppgtt->switch_mm(ppgtt, req);
1580 }
1581
1582 struct i915_hw_ppgtt *
1583 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
1584 {
1585         struct i915_hw_ppgtt *ppgtt;
1586         int ret;
1587
1588         ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1589         if (!ppgtt)
1590                 return ERR_PTR(-ENOMEM);
1591
1592         ret = i915_ppgtt_init(dev, ppgtt);
1593         if (ret) {
1594                 kfree(ppgtt);
1595                 return ERR_PTR(ret);
1596         }
1597
1598         ppgtt->file_priv = fpriv;
1599
1600         trace_i915_ppgtt_create(&ppgtt->base);
1601
1602         return ppgtt;
1603 }
1604
1605 void  i915_ppgtt_release(struct kref *kref)
1606 {
1607         struct i915_hw_ppgtt *ppgtt =
1608                 container_of(kref, struct i915_hw_ppgtt, ref);
1609
1610         trace_i915_ppgtt_release(&ppgtt->base);
1611
1612         /* vmas should already be unbound */
1613         WARN_ON(!list_empty(&ppgtt->base.active_list));
1614         WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1615
1616         list_del(&ppgtt->base.global_link);
1617         drm_mm_takedown(&ppgtt->base.mm);
1618
1619         ppgtt->base.cleanup(&ppgtt->base);
1620         kfree(ppgtt);
1621 }
1622
1623 extern int intel_iommu_gfx_mapped;
1624 /* Certain Gen5 chipsets require require idling the GPU before
1625  * unmapping anything from the GTT when VT-d is enabled.
1626  */
1627 static bool needs_idle_maps(struct drm_device *dev)
1628 {
1629 #ifdef CONFIG_INTEL_IOMMU
1630         /* Query intel_iommu to see if we need the workaround. Presumably that
1631          * was loaded first.
1632          */
1633         if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
1634                 return true;
1635 #endif
1636         return false;
1637 }
1638
1639 static bool do_idling(struct drm_i915_private *dev_priv)
1640 {
1641         bool ret = dev_priv->mm.interruptible;
1642
1643         if (unlikely(dev_priv->gtt.do_idle_maps)) {
1644                 dev_priv->mm.interruptible = false;
1645                 if (i915_gpu_idle(dev_priv->dev)) {
1646                         DRM_ERROR("Couldn't idle GPU\n");
1647                         /* Wait a bit, in hopes it avoids the hang */
1648                         udelay(10);
1649                 }
1650         }
1651
1652         return ret;
1653 }
1654
1655 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
1656 {
1657         if (unlikely(dev_priv->gtt.do_idle_maps))
1658                 dev_priv->mm.interruptible = interruptible;
1659 }
1660
1661 void i915_check_and_clear_faults(struct drm_device *dev)
1662 {
1663         struct drm_i915_private *dev_priv = dev->dev_private;
1664         struct intel_engine_cs *ring;
1665         int i;
1666
1667         if (INTEL_INFO(dev)->gen < 6)
1668                 return;
1669
1670         for_each_ring(ring, dev_priv, i) {
1671                 u32 fault_reg;
1672                 fault_reg = I915_READ(RING_FAULT_REG(ring));
1673                 if (fault_reg & RING_FAULT_VALID) {
1674                         DRM_DEBUG_DRIVER("Unexpected fault\n"
1675                                          "\tAddr: 0x%08lx\n"
1676                                          "\tAddress space: %s\n"
1677                                          "\tSource ID: %d\n"
1678                                          "\tType: %d\n",
1679                                          fault_reg & PAGE_MASK,
1680                                          fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
1681                                          RING_FAULT_SRCID(fault_reg),
1682                                          RING_FAULT_FAULT_TYPE(fault_reg));
1683                         I915_WRITE(RING_FAULT_REG(ring),
1684                                    fault_reg & ~RING_FAULT_VALID);
1685                 }
1686         }
1687         POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
1688 }
1689
1690 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
1691 {
1692         if (INTEL_INFO(dev_priv->dev)->gen < 6) {
1693                 intel_gtt_chipset_flush();
1694         } else {
1695                 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1696                 POSTING_READ(GFX_FLSH_CNTL_GEN6);
1697         }
1698 }
1699
1700 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
1701 {
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703
1704         /* Don't bother messing with faults pre GEN6 as we have little
1705          * documentation supporting that it's a good idea.
1706          */
1707         if (INTEL_INFO(dev)->gen < 6)
1708                 return;
1709
1710         i915_check_and_clear_faults(dev);
1711
1712         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
1713                                        dev_priv->gtt.base.start,
1714                                        dev_priv->gtt.base.total,
1715                                        true);
1716
1717         i915_ggtt_flush(dev_priv);
1718 }
1719
1720 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
1721 {
1722         if (obj->has_dma_mapping)
1723                 return 0;
1724
1725         if (!dma_map_sg(&obj->base.dev->pdev->dev,
1726                         obj->pages->sgl, obj->pages->nents,
1727                         PCI_DMA_BIDIRECTIONAL))
1728                 return -ENOSPC;
1729
1730         return 0;
1731 }
1732
1733 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
1734 {
1735 #ifdef writeq
1736         writeq(pte, addr);
1737 #else
1738         iowrite32((u32)pte, addr);
1739         iowrite32(pte >> 32, addr + 4);
1740 #endif
1741 }
1742
1743 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
1744                                      struct sg_table *st,
1745                                      uint64_t start,
1746                                      enum i915_cache_level level, u32 unused)
1747 {
1748         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1749         unsigned first_entry = start >> PAGE_SHIFT;
1750         gen8_pte_t __iomem *gtt_entries =
1751                 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1752         int i = 0;
1753         struct sg_page_iter sg_iter;
1754         dma_addr_t addr = 0; /* shut up gcc */
1755
1756         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1757                 addr = sg_dma_address(sg_iter.sg) +
1758                         (sg_iter.sg_pgoffset << PAGE_SHIFT);
1759                 gen8_set_pte(&gtt_entries[i],
1760                              gen8_pte_encode(addr, level, true));
1761                 i++;
1762         }
1763
1764         /*
1765          * XXX: This serves as a posting read to make sure that the PTE has
1766          * actually been updated. There is some concern that even though
1767          * registers and PTEs are within the same BAR that they are potentially
1768          * of NUMA access patterns. Therefore, even with the way we assume
1769          * hardware should work, we must keep this posting read for paranoia.
1770          */
1771         if (i != 0)
1772                 WARN_ON(readq(&gtt_entries[i-1])
1773                         != gen8_pte_encode(addr, level, true));
1774
1775         /* This next bit makes the above posting read even more important. We
1776          * want to flush the TLBs only after we're certain all the PTE updates
1777          * have finished.
1778          */
1779         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1780         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1781 }
1782
1783 /*
1784  * Binds an object into the global gtt with the specified cache level. The object
1785  * will be accessible to the GPU via commands whose operands reference offsets
1786  * within the global GTT as well as accessible by the GPU through the GMADR
1787  * mapped BAR (dev_priv->mm.gtt->gtt).
1788  */
1789 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
1790                                      struct sg_table *st,
1791                                      uint64_t start,
1792                                      enum i915_cache_level level, u32 flags)
1793 {
1794         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1795         unsigned first_entry = start >> PAGE_SHIFT;
1796         gen6_pte_t __iomem *gtt_entries =
1797                 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
1798         int i = 0;
1799         struct sg_page_iter sg_iter;
1800         dma_addr_t addr = 0;
1801
1802         for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
1803                 addr = sg_page_iter_dma_address(&sg_iter);
1804                 iowrite32(vm->pte_encode(addr, level, true, flags), &gtt_entries[i]);
1805                 i++;
1806         }
1807
1808         /* XXX: This serves as a posting read to make sure that the PTE has
1809          * actually been updated. There is some concern that even though
1810          * registers and PTEs are within the same BAR that they are potentially
1811          * of NUMA access patterns. Therefore, even with the way we assume
1812          * hardware should work, we must keep this posting read for paranoia.
1813          */
1814         if (i != 0) {
1815                 unsigned long gtt = readl(&gtt_entries[i-1]);
1816                 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
1817         }
1818
1819         /* This next bit makes the above posting read even more important. We
1820          * want to flush the TLBs only after we're certain all the PTE updates
1821          * have finished.
1822          */
1823         I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
1824         POSTING_READ(GFX_FLSH_CNTL_GEN6);
1825 }
1826
1827 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
1828                                   uint64_t start,
1829                                   uint64_t length,
1830                                   bool use_scratch)
1831 {
1832         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1833         unsigned first_entry = start >> PAGE_SHIFT;
1834         unsigned num_entries = length >> PAGE_SHIFT;
1835         gen8_pte_t scratch_pte, __iomem *gtt_base =
1836                 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1837         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1838         int i;
1839
1840         if (WARN(num_entries > max_entries,
1841                  "First entry = %d; Num entries = %d (max=%d)\n",
1842                  first_entry, num_entries, max_entries))
1843                 num_entries = max_entries;
1844
1845         scratch_pte = gen8_pte_encode(vm->scratch.addr,
1846                                       I915_CACHE_LLC,
1847                                       use_scratch);
1848         for (i = 0; i < num_entries; i++)
1849                 gen8_set_pte(&gtt_base[i], scratch_pte);
1850         readl(gtt_base);
1851 }
1852
1853 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
1854                                   uint64_t start,
1855                                   uint64_t length,
1856                                   bool use_scratch)
1857 {
1858         struct drm_i915_private *dev_priv = vm->dev->dev_private;
1859         unsigned first_entry = start >> PAGE_SHIFT;
1860         unsigned num_entries = length >> PAGE_SHIFT;
1861         gen6_pte_t scratch_pte, __iomem *gtt_base =
1862                 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
1863         const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
1864         int i;
1865
1866         if (WARN(num_entries > max_entries,
1867                  "First entry = %d; Num entries = %d (max=%d)\n",
1868                  first_entry, num_entries, max_entries))
1869                 num_entries = max_entries;
1870
1871         scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0);
1872
1873         for (i = 0; i < num_entries; i++)
1874                 iowrite32(scratch_pte, &gtt_base[i]);
1875         readl(gtt_base);
1876 }
1877
1878 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
1879                                      struct sg_table *pages,
1880                                      uint64_t start,
1881                                      enum i915_cache_level cache_level, u32 unused)
1882 {
1883         unsigned int flags = (cache_level == I915_CACHE_NONE) ?
1884                 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
1885
1886         intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
1887
1888 }
1889
1890 static void i915_ggtt_clear_range(struct i915_address_space *vm,
1891                                   uint64_t start,
1892                                   uint64_t length,
1893                                   bool unused)
1894 {
1895         unsigned first_entry = start >> PAGE_SHIFT;
1896         unsigned num_entries = length >> PAGE_SHIFT;
1897         intel_gtt_clear_range(first_entry, num_entries);
1898 }
1899
1900 static int ggtt_bind_vma(struct i915_vma *vma,
1901                          enum i915_cache_level cache_level,
1902                          u32 flags)
1903 {
1904         struct drm_device *dev = vma->vm->dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct drm_i915_gem_object *obj = vma->obj;
1907         struct sg_table *pages = obj->pages;
1908         u32 pte_flags = 0;
1909         int ret;
1910
1911         ret = i915_get_ggtt_vma_pages(vma);
1912         if (ret)
1913                 return ret;
1914         pages = vma->ggtt_view.pages;
1915
1916         /* Currently applicable only to VLV */
1917         if (obj->gt_ro)
1918                 pte_flags |= PTE_READ_ONLY;
1919
1920
1921         if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) {
1922                 vma->vm->insert_entries(vma->vm, pages,
1923                                         vma->node.start,
1924                                         cache_level, pte_flags);
1925         }
1926
1927         if (dev_priv->mm.aliasing_ppgtt && flags & LOCAL_BIND) {
1928                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1929                 appgtt->base.insert_entries(&appgtt->base, pages,
1930                                             vma->node.start,
1931                                             cache_level, pte_flags);
1932         }
1933
1934         return 0;
1935 }
1936
1937 static void ggtt_unbind_vma(struct i915_vma *vma)
1938 {
1939         struct drm_device *dev = vma->vm->dev;
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         struct drm_i915_gem_object *obj = vma->obj;
1942         const uint64_t size = min_t(uint64_t,
1943                                     obj->base.size,
1944                                     vma->node.size);
1945
1946         if (vma->bound & GLOBAL_BIND) {
1947                 vma->vm->clear_range(vma->vm,
1948                                      vma->node.start,
1949                                      size,
1950                                      true);
1951         }
1952
1953         if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
1954                 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
1955
1956                 appgtt->base.clear_range(&appgtt->base,
1957                                          vma->node.start,
1958                                          size,
1959                                          true);
1960         }
1961 }
1962
1963 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
1964 {
1965         struct drm_device *dev = obj->base.dev;
1966         struct drm_i915_private *dev_priv = dev->dev_private;
1967         bool interruptible;
1968
1969         interruptible = do_idling(dev_priv);
1970
1971         if (!obj->has_dma_mapping)
1972                 dma_unmap_sg(&dev->pdev->dev,
1973                              obj->pages->sgl, obj->pages->nents,
1974                              PCI_DMA_BIDIRECTIONAL);
1975
1976         undo_idling(dev_priv, interruptible);
1977 }
1978
1979 static void i915_gtt_color_adjust(struct drm_mm_node *node,
1980                                   unsigned long color,
1981                                   u64 *start,
1982                                   u64 *end)
1983 {
1984         if (node->color != color)
1985                 *start += 4096;
1986
1987         if (!list_empty(&node->node_list)) {
1988                 node = list_entry(node->node_list.next,
1989                                   struct drm_mm_node,
1990                                   node_list);
1991                 if (node->allocated && node->color != color)
1992                         *end -= 4096;
1993         }
1994 }
1995
1996 static int i915_gem_setup_global_gtt(struct drm_device *dev,
1997                                      unsigned long start,
1998                                      unsigned long mappable_end,
1999                                      unsigned long end)
2000 {
2001         /* Let GEM Manage all of the aperture.
2002          *
2003          * However, leave one page at the end still bound to the scratch page.
2004          * There are a number of places where the hardware apparently prefetches
2005          * past the end of the object, and we've seen multiple hangs with the
2006          * GPU head pointer stuck in a batchbuffer bound at the last page of the
2007          * aperture.  One page should be enough to keep any prefetching inside
2008          * of the aperture.
2009          */
2010         struct drm_i915_private *dev_priv = dev->dev_private;
2011         struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2012         struct drm_mm_node *entry;
2013         struct drm_i915_gem_object *obj;
2014         unsigned long hole_start, hole_end;
2015         int ret;
2016
2017         BUG_ON(mappable_end > end);
2018
2019         /* Subtract the guard page ... */
2020         drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE);
2021
2022         dev_priv->gtt.base.start = start;
2023         dev_priv->gtt.base.total = end - start;
2024
2025         if (intel_vgpu_active(dev)) {
2026                 ret = intel_vgt_balloon(dev);
2027                 if (ret)
2028                         return ret;
2029         }
2030
2031         if (!HAS_LLC(dev))
2032                 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust;
2033
2034         /* Mark any preallocated objects as occupied */
2035         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2036                 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2037
2038                 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n",
2039                               i915_gem_obj_ggtt_offset(obj), obj->base.size);
2040
2041                 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2042                 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2043                 if (ret) {
2044                         DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2045                         return ret;
2046                 }
2047                 vma->bound |= GLOBAL_BIND;
2048         }
2049
2050         /* Clear any non-preallocated blocks */
2051         drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2052                 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2053                               hole_start, hole_end);
2054                 ggtt_vm->clear_range(ggtt_vm, hole_start,
2055                                      hole_end - hole_start, true);
2056         }
2057
2058         /* And finally clear the reserved guard page */
2059         ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2060
2061         if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2062                 struct i915_hw_ppgtt *ppgtt;
2063
2064                 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2065                 if (!ppgtt)
2066                         return -ENOMEM;
2067
2068                 ret = __hw_ppgtt_init(dev, ppgtt);
2069                 if (ret) {
2070                         ppgtt->base.cleanup(&ppgtt->base);
2071                         kfree(ppgtt);
2072                         return ret;
2073                 }
2074
2075                 if (ppgtt->base.allocate_va_range)
2076                         ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2077                                                             ppgtt->base.total);
2078                 if (ret) {
2079                         ppgtt->base.cleanup(&ppgtt->base);
2080                         kfree(ppgtt);
2081                         return ret;
2082                 }
2083
2084                 ppgtt->base.clear_range(&ppgtt->base,
2085                                         ppgtt->base.start,
2086                                         ppgtt->base.total,
2087                                         true);
2088
2089                 dev_priv->mm.aliasing_ppgtt = ppgtt;
2090         }
2091
2092         return 0;
2093 }
2094
2095 void i915_gem_init_global_gtt(struct drm_device *dev)
2096 {
2097         struct drm_i915_private *dev_priv = dev->dev_private;
2098         u64 gtt_size, mappable_size;
2099
2100         gtt_size = dev_priv->gtt.base.total;
2101         mappable_size = dev_priv->gtt.mappable_end;
2102
2103         i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2104 }
2105
2106 void i915_global_gtt_cleanup(struct drm_device *dev)
2107 {
2108         struct drm_i915_private *dev_priv = dev->dev_private;
2109         struct i915_address_space *vm = &dev_priv->gtt.base;
2110
2111         if (dev_priv->mm.aliasing_ppgtt) {
2112                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2113
2114                 ppgtt->base.cleanup(&ppgtt->base);
2115         }
2116
2117         if (drm_mm_initialized(&vm->mm)) {
2118                 if (intel_vgpu_active(dev))
2119                         intel_vgt_deballoon();
2120
2121                 drm_mm_takedown(&vm->mm);
2122                 list_del(&vm->global_link);
2123         }
2124
2125         vm->cleanup(vm);
2126 }
2127
2128 static int setup_scratch_page(struct drm_device *dev)
2129 {
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         struct page *page;
2132         dma_addr_t dma_addr;
2133
2134         page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO);
2135         if (page == NULL)
2136                 return -ENOMEM;
2137         set_pages_uc(page, 1);
2138
2139 #ifdef CONFIG_INTEL_IOMMU
2140         dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE,
2141                                 PCI_DMA_BIDIRECTIONAL);
2142         if (pci_dma_mapping_error(dev->pdev, dma_addr)) {
2143                 __free_page(page);
2144                 return -EINVAL;
2145         }
2146 #else
2147         dma_addr = page_to_phys(page);
2148 #endif
2149         dev_priv->gtt.base.scratch.page = page;
2150         dev_priv->gtt.base.scratch.addr = dma_addr;
2151
2152         return 0;
2153 }
2154
2155 static void teardown_scratch_page(struct drm_device *dev)
2156 {
2157         struct drm_i915_private *dev_priv = dev->dev_private;
2158         struct page *page = dev_priv->gtt.base.scratch.page;
2159
2160         set_pages_wb(page, 1);
2161         pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr,
2162                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
2163         __free_page(page);
2164 }
2165
2166 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2167 {
2168         snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2169         snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2170         return snb_gmch_ctl << 20;
2171 }
2172
2173 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2174 {
2175         bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2176         bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2177         if (bdw_gmch_ctl)
2178                 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2179
2180 #ifdef CONFIG_X86_32
2181         /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2182         if (bdw_gmch_ctl > 4)
2183                 bdw_gmch_ctl = 4;
2184 #endif
2185
2186         return bdw_gmch_ctl << 20;
2187 }
2188
2189 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2190 {
2191         gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2192         gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2193
2194         if (gmch_ctrl)
2195                 return 1 << (20 + gmch_ctrl);
2196
2197         return 0;
2198 }
2199
2200 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2201 {
2202         snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2203         snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2204         return snb_gmch_ctl << 25; /* 32 MB units */
2205 }
2206
2207 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2208 {
2209         bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2210         bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2211         return bdw_gmch_ctl << 25; /* 32 MB units */
2212 }
2213
2214 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2215 {
2216         gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2217         gmch_ctrl &= SNB_GMCH_GMS_MASK;
2218
2219         /*
2220          * 0x0  to 0x10: 32MB increments starting at 0MB
2221          * 0x11 to 0x16: 4MB increments starting at 8MB
2222          * 0x17 to 0x1d: 4MB increments start at 36MB
2223          */
2224         if (gmch_ctrl < 0x11)
2225                 return gmch_ctrl << 25;
2226         else if (gmch_ctrl < 0x17)
2227                 return (gmch_ctrl - 0x11 + 2) << 22;
2228         else
2229                 return (gmch_ctrl - 0x17 + 9) << 22;
2230 }
2231
2232 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2233 {
2234         gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2235         gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2236
2237         if (gen9_gmch_ctl < 0xf0)
2238                 return gen9_gmch_ctl << 25; /* 32 MB units */
2239         else
2240                 /* 4MB increments starting at 0xf0 for 4MB */
2241                 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2242 }
2243
2244 static int ggtt_probe_common(struct drm_device *dev,
2245                              size_t gtt_size)
2246 {
2247         struct drm_i915_private *dev_priv = dev->dev_private;
2248         phys_addr_t gtt_phys_addr;
2249         int ret;
2250
2251         /* For Modern GENs the PTEs and register space are split in the BAR */
2252         gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2253                 (pci_resource_len(dev->pdev, 0) / 2);
2254
2255         /*
2256          * On BXT writes larger than 64 bit to the GTT pagetable range will be
2257          * dropped. For WC mappings in general we have 64 byte burst writes
2258          * when the WC buffer is flushed, so we can't use it, but have to
2259          * resort to an uncached mapping. The WC issue is easily caught by the
2260          * readback check when writing GTT PTE entries.
2261          */
2262         if (IS_BROXTON(dev))
2263                 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2264         else
2265                 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2266         if (!dev_priv->gtt.gsm) {
2267                 DRM_ERROR("Failed to map the gtt page table\n");
2268                 return -ENOMEM;
2269         }
2270
2271         ret = setup_scratch_page(dev);
2272         if (ret) {
2273                 DRM_ERROR("Scratch setup failed\n");
2274                 /* iounmap will also get called at remove, but meh */
2275                 iounmap(dev_priv->gtt.gsm);
2276         }
2277
2278         return ret;
2279 }
2280
2281 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2282  * bits. When using advanced contexts each context stores its own PAT, but
2283  * writing this data shouldn't be harmful even in those cases. */
2284 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2285 {
2286         uint64_t pat;
2287
2288         pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC)     | /* for normal objects, no eLLC */
2289               GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2290               GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2291               GEN8_PPAT(3, GEN8_PPAT_UC)                     | /* Uncached objects, mostly for scanout */
2292               GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2293               GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2294               GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2295               GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2296
2297         if (!USES_PPGTT(dev_priv->dev))
2298                 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2299                  * so RTL will always use the value corresponding to
2300                  * pat_sel = 000".
2301                  * So let's disable cache for GGTT to avoid screen corruptions.
2302                  * MOCS still can be used though.
2303                  * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2304                  * before this patch, i.e. the same uncached + snooping access
2305                  * like on gen6/7 seems to be in effect.
2306                  * - So this just fixes blitter/render access. Again it looks
2307                  * like it's not just uncached access, but uncached + snooping.
2308                  * So we can still hold onto all our assumptions wrt cpu
2309                  * clflushing on LLC machines.
2310                  */
2311                 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2312
2313         /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2314          * write would work. */
2315         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2316         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2317 }
2318
2319 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2320 {
2321         uint64_t pat;
2322
2323         /*
2324          * Map WB on BDW to snooped on CHV.
2325          *
2326          * Only the snoop bit has meaning for CHV, the rest is
2327          * ignored.
2328          *
2329          * The hardware will never snoop for certain types of accesses:
2330          * - CPU GTT (GMADR->GGTT->no snoop->memory)
2331          * - PPGTT page tables
2332          * - some other special cycles
2333          *
2334          * As with BDW, we also need to consider the following for GT accesses:
2335          * "For GGTT, there is NO pat_sel[2:0] from the entry,
2336          * so RTL will always use the value corresponding to
2337          * pat_sel = 000".
2338          * Which means we must set the snoop bit in PAT entry 0
2339          * in order to keep the global status page working.
2340          */
2341         pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2342               GEN8_PPAT(1, 0) |
2343               GEN8_PPAT(2, 0) |
2344               GEN8_PPAT(3, 0) |
2345               GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2346               GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2347               GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2348               GEN8_PPAT(7, CHV_PPAT_SNOOP);
2349
2350         I915_WRITE(GEN8_PRIVATE_PAT, pat);
2351         I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32);
2352 }
2353
2354 static int gen8_gmch_probe(struct drm_device *dev,
2355                            u64 *gtt_total,
2356                            size_t *stolen,
2357                            phys_addr_t *mappable_base,
2358                            u64 *mappable_end)
2359 {
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         u64 gtt_size;
2362         u16 snb_gmch_ctl;
2363         int ret;
2364
2365         /* TODO: We're not aware of mappable constraints on gen8 yet */
2366         *mappable_base = pci_resource_start(dev->pdev, 2);
2367         *mappable_end = pci_resource_len(dev->pdev, 2);
2368
2369         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2370                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2371
2372         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2373
2374         if (INTEL_INFO(dev)->gen >= 9) {
2375                 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2376                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2377         } else if (IS_CHERRYVIEW(dev)) {
2378                 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2379                 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
2380         } else {
2381                 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
2382                 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2383         }
2384
2385         *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2386
2387         if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2388                 chv_setup_private_ppat(dev_priv);
2389         else
2390                 bdw_setup_private_ppat(dev_priv);
2391
2392         ret = ggtt_probe_common(dev, gtt_size);
2393
2394         dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
2395         dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
2396         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2397         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2398
2399         return ret;
2400 }
2401
2402 static int gen6_gmch_probe(struct drm_device *dev,
2403                            u64 *gtt_total,
2404                            size_t *stolen,
2405                            phys_addr_t *mappable_base,
2406                            u64 *mappable_end)
2407 {
2408         struct drm_i915_private *dev_priv = dev->dev_private;
2409         unsigned int gtt_size;
2410         u16 snb_gmch_ctl;
2411         int ret;
2412
2413         *mappable_base = pci_resource_start(dev->pdev, 2);
2414         *mappable_end = pci_resource_len(dev->pdev, 2);
2415
2416         /* 64/512MB is the current min/max we actually know of, but this is just
2417          * a coarse sanity check.
2418          */
2419         if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
2420                 DRM_ERROR("Unknown GMADR size (%llx)\n",
2421                           dev_priv->gtt.mappable_end);
2422                 return -ENXIO;
2423         }
2424
2425         if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
2426                 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
2427         pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2428
2429         *stolen = gen6_get_stolen_size(snb_gmch_ctl);
2430
2431         gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
2432         *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2433
2434         ret = ggtt_probe_common(dev, gtt_size);
2435
2436         dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
2437         dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
2438         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2439         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2440
2441         return ret;
2442 }
2443
2444 static void gen6_gmch_remove(struct i915_address_space *vm)
2445 {
2446
2447         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
2448
2449         iounmap(gtt->gsm);
2450         teardown_scratch_page(vm->dev);
2451 }
2452
2453 static int i915_gmch_probe(struct drm_device *dev,
2454                            u64 *gtt_total,
2455                            size_t *stolen,
2456                            phys_addr_t *mappable_base,
2457                            u64 *mappable_end)
2458 {
2459         struct drm_i915_private *dev_priv = dev->dev_private;
2460         int ret;
2461
2462         ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
2463         if (!ret) {
2464                 DRM_ERROR("failed to set up gmch\n");
2465                 return -EIO;
2466         }
2467
2468         intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
2469
2470         dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
2471         dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
2472         dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
2473         dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
2474         dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
2475
2476         if (unlikely(dev_priv->gtt.do_idle_maps))
2477                 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
2478
2479         return 0;
2480 }
2481
2482 static void i915_gmch_remove(struct i915_address_space *vm)
2483 {
2484         intel_gmch_remove();
2485 }
2486
2487 int i915_gem_gtt_init(struct drm_device *dev)
2488 {
2489         struct drm_i915_private *dev_priv = dev->dev_private;
2490         struct i915_gtt *gtt = &dev_priv->gtt;
2491         int ret;
2492
2493         if (INTEL_INFO(dev)->gen <= 5) {
2494                 gtt->gtt_probe = i915_gmch_probe;
2495                 gtt->base.cleanup = i915_gmch_remove;
2496         } else if (INTEL_INFO(dev)->gen < 8) {
2497                 gtt->gtt_probe = gen6_gmch_probe;
2498                 gtt->base.cleanup = gen6_gmch_remove;
2499                 if (IS_HASWELL(dev) && dev_priv->ellc_size)
2500                         gtt->base.pte_encode = iris_pte_encode;
2501                 else if (IS_HASWELL(dev))
2502                         gtt->base.pte_encode = hsw_pte_encode;
2503                 else if (IS_VALLEYVIEW(dev))
2504                         gtt->base.pte_encode = byt_pte_encode;
2505                 else if (INTEL_INFO(dev)->gen >= 7)
2506                         gtt->base.pte_encode = ivb_pte_encode;
2507                 else
2508                         gtt->base.pte_encode = snb_pte_encode;
2509         } else {
2510                 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
2511                 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
2512         }
2513
2514         ret = gtt->gtt_probe(dev, &gtt->base.total, &gtt->stolen_size,
2515                              &gtt->mappable_base, &gtt->mappable_end);
2516         if (ret)
2517                 return ret;
2518
2519         gtt->base.dev = dev;
2520
2521         /* GMADR is the PCI mmio aperture into the global GTT. */
2522         DRM_INFO("Memory usable by graphics device = %lluM\n",
2523                  gtt->base.total >> 20);
2524         DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
2525         DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
2526 #ifdef CONFIG_INTEL_IOMMU
2527         if (intel_iommu_gfx_mapped)
2528                 DRM_INFO("VT-d active for gfx access\n");
2529 #endif
2530         /*
2531          * i915.enable_ppgtt is read-only, so do an early pass to validate the
2532          * user's requested state against the hardware/driver capabilities.  We
2533          * do this now so that we can print out any log messages once rather
2534          * than every time we check intel_enable_ppgtt().
2535          */
2536         i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
2537         DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
2538
2539         return 0;
2540 }
2541
2542 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
2543 {
2544         struct drm_i915_private *dev_priv = dev->dev_private;
2545         struct drm_i915_gem_object *obj;
2546         struct i915_address_space *vm;
2547
2548         i915_check_and_clear_faults(dev);
2549
2550         /* First fill our portion of the GTT with scratch pages */
2551         dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2552                                        dev_priv->gtt.base.start,
2553                                        dev_priv->gtt.base.total,
2554                                        true);
2555
2556         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2557                 struct i915_vma *vma = i915_gem_obj_to_vma(obj,
2558                                                            &dev_priv->gtt.base);
2559                 if (!vma)
2560                         continue;
2561
2562                 i915_gem_clflush_object(obj, obj->pin_display);
2563                 WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
2564         }
2565
2566
2567         if (INTEL_INFO(dev)->gen >= 8) {
2568                 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
2569                         chv_setup_private_ppat(dev_priv);
2570                 else
2571                         bdw_setup_private_ppat(dev_priv);
2572
2573                 return;
2574         }
2575
2576         if (USES_PPGTT(dev)) {
2577                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
2578                         /* TODO: Perhaps it shouldn't be gen6 specific */
2579
2580                         struct i915_hw_ppgtt *ppgtt =
2581                                         container_of(vm, struct i915_hw_ppgtt,
2582                                                      base);
2583
2584                         if (i915_is_ggtt(vm))
2585                                 ppgtt = dev_priv->mm.aliasing_ppgtt;
2586
2587                         gen6_write_page_range(dev_priv, &ppgtt->pd,
2588                                               0, ppgtt->base.total);
2589                 }
2590         }
2591
2592         i915_ggtt_flush(dev_priv);
2593 }
2594
2595 static struct i915_vma *
2596 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
2597                       struct i915_address_space *vm,
2598                       const struct i915_ggtt_view *ggtt_view)
2599 {
2600         struct i915_vma *vma;
2601
2602         if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
2603                 return ERR_PTR(-EINVAL);
2604
2605         vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
2606         if (vma == NULL)
2607                 return ERR_PTR(-ENOMEM);
2608
2609         INIT_LIST_HEAD(&vma->vma_link);
2610         INIT_LIST_HEAD(&vma->mm_list);
2611         INIT_LIST_HEAD(&vma->exec_list);
2612         vma->vm = vm;
2613         vma->obj = obj;
2614
2615         if (i915_is_ggtt(vm))
2616                 vma->ggtt_view = *ggtt_view;
2617
2618         list_add_tail(&vma->vma_link, &obj->vma_list);
2619         if (!i915_is_ggtt(vm))
2620                 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
2621
2622         return vma;
2623 }
2624
2625 struct i915_vma *
2626 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2627                                   struct i915_address_space *vm)
2628 {
2629         struct i915_vma *vma;
2630
2631         vma = i915_gem_obj_to_vma(obj, vm);
2632         if (!vma)
2633                 vma = __i915_gem_vma_create(obj, vm,
2634                                             i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
2635
2636         return vma;
2637 }
2638
2639 struct i915_vma *
2640 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
2641                                        const struct i915_ggtt_view *view)
2642 {
2643         struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
2644         struct i915_vma *vma;
2645
2646         if (WARN_ON(!view))
2647                 return ERR_PTR(-EINVAL);
2648
2649         vma = i915_gem_obj_to_ggtt_view(obj, view);
2650
2651         if (IS_ERR(vma))
2652                 return vma;
2653
2654         if (!vma)
2655                 vma = __i915_gem_vma_create(obj, ggtt, view);
2656
2657         return vma;
2658
2659 }
2660
2661 static void
2662 rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height,
2663              struct sg_table *st)
2664 {
2665         unsigned int column, row;
2666         unsigned int src_idx;
2667         struct scatterlist *sg = st->sgl;
2668
2669         st->nents = 0;
2670
2671         for (column = 0; column < width; column++) {
2672                 src_idx = width * (height - 1) + column;
2673                 for (row = 0; row < height; row++) {
2674                         st->nents++;
2675                         /* We don't need the pages, but need to initialize
2676                          * the entries so the sg list can be happily traversed.
2677                          * The only thing we need are DMA addresses.
2678                          */
2679                         sg_set_page(sg, NULL, PAGE_SIZE, 0);
2680                         sg_dma_address(sg) = in[src_idx];
2681                         sg_dma_len(sg) = PAGE_SIZE;
2682                         sg = sg_next(sg);
2683                         src_idx -= width;
2684                 }
2685         }
2686 }
2687
2688 static struct sg_table *
2689 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
2690                           struct drm_i915_gem_object *obj)
2691 {
2692         struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
2693         unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
2694         struct sg_page_iter sg_iter;
2695         unsigned long i;
2696         dma_addr_t *page_addr_list;
2697         struct sg_table *st;
2698         int ret = -ENOMEM;
2699
2700         /* Allocate a temporary list of source pages for random access. */
2701         page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
2702                                        sizeof(dma_addr_t));
2703         if (!page_addr_list)
2704                 return ERR_PTR(ret);
2705
2706         /* Allocate target SG list. */
2707         st = kmalloc(sizeof(*st), GFP_KERNEL);
2708         if (!st)
2709                 goto err_st_alloc;
2710
2711         ret = sg_alloc_table(st, size_pages, GFP_KERNEL);
2712         if (ret)
2713                 goto err_sg_alloc;
2714
2715         /* Populate source page list from the object. */
2716         i = 0;
2717         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
2718                 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
2719                 i++;
2720         }
2721
2722         /* Rotate the pages. */
2723         rotate_pages(page_addr_list,
2724                      rot_info->width_pages, rot_info->height_pages,
2725                      st);
2726
2727         DRM_DEBUG_KMS(
2728                       "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages).\n",
2729                       obj->base.size, rot_info->pitch, rot_info->height,
2730                       rot_info->pixel_format, rot_info->width_pages,
2731                       rot_info->height_pages, size_pages);
2732
2733         drm_free_large(page_addr_list);
2734
2735         return st;
2736
2737 err_sg_alloc:
2738         kfree(st);
2739 err_st_alloc:
2740         drm_free_large(page_addr_list);
2741
2742         DRM_DEBUG_KMS(
2743                       "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages)\n",
2744                       obj->base.size, ret, rot_info->pitch, rot_info->height,
2745                       rot_info->pixel_format, rot_info->width_pages,
2746                       rot_info->height_pages, size_pages);
2747         return ERR_PTR(ret);
2748 }
2749
2750 static struct sg_table *
2751 intel_partial_pages(const struct i915_ggtt_view *view,
2752                     struct drm_i915_gem_object *obj)
2753 {
2754         struct sg_table *st;
2755         struct scatterlist *sg;
2756         struct sg_page_iter obj_sg_iter;
2757         int ret = -ENOMEM;
2758
2759         st = kmalloc(sizeof(*st), GFP_KERNEL);
2760         if (!st)
2761                 goto err_st_alloc;
2762
2763         ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
2764         if (ret)
2765                 goto err_sg_alloc;
2766
2767         sg = st->sgl;
2768         st->nents = 0;
2769         for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
2770                 view->params.partial.offset)
2771         {
2772                 if (st->nents >= view->params.partial.size)
2773                         break;
2774
2775                 sg_set_page(sg, NULL, PAGE_SIZE, 0);
2776                 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
2777                 sg_dma_len(sg) = PAGE_SIZE;
2778
2779                 sg = sg_next(sg);
2780                 st->nents++;
2781         }
2782
2783         return st;
2784
2785 err_sg_alloc:
2786         kfree(st);
2787 err_st_alloc:
2788         return ERR_PTR(ret);
2789 }
2790
2791 static int
2792 i915_get_ggtt_vma_pages(struct i915_vma *vma)
2793 {
2794         int ret = 0;
2795
2796         if (vma->ggtt_view.pages)
2797                 return 0;
2798
2799         if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
2800                 vma->ggtt_view.pages = vma->obj->pages;
2801         else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
2802                 vma->ggtt_view.pages =
2803                         intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
2804         else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
2805                 vma->ggtt_view.pages =
2806                         intel_partial_pages(&vma->ggtt_view, vma->obj);
2807         else
2808                 WARN_ONCE(1, "GGTT view %u not implemented!\n",
2809                           vma->ggtt_view.type);
2810
2811         if (!vma->ggtt_view.pages) {
2812                 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
2813                           vma->ggtt_view.type);
2814                 ret = -EINVAL;
2815         } else if (IS_ERR(vma->ggtt_view.pages)) {
2816                 ret = PTR_ERR(vma->ggtt_view.pages);
2817                 vma->ggtt_view.pages = NULL;
2818                 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
2819                           vma->ggtt_view.type, ret);
2820         }
2821
2822         return ret;
2823 }
2824
2825 /**
2826  * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
2827  * @vma: VMA to map
2828  * @cache_level: mapping cache level
2829  * @flags: flags like global or local mapping
2830  *
2831  * DMA addresses are taken from the scatter-gather table of this object (or of
2832  * this VMA in case of non-default GGTT views) and PTE entries set up.
2833  * Note that DMA addresses are also the only part of the SG table we care about.
2834  */
2835 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2836                   u32 flags)
2837 {
2838         int ret;
2839         u32 bind_flags;
2840
2841         if (WARN_ON(flags == 0))
2842                 return -EINVAL;
2843
2844         bind_flags = 0;
2845         if (flags & PIN_GLOBAL)
2846                 bind_flags |= GLOBAL_BIND;
2847         if (flags & PIN_USER)
2848                 bind_flags |= LOCAL_BIND;
2849
2850         if (flags & PIN_UPDATE)
2851                 bind_flags |= vma->bound;
2852         else
2853                 bind_flags &= ~vma->bound;
2854
2855         if (bind_flags == 0)
2856                 return 0;
2857
2858         if (vma->bound == 0 && vma->vm->allocate_va_range) {
2859                 trace_i915_va_alloc(vma->vm,
2860                                     vma->node.start,
2861                                     vma->node.size,
2862                                     VM_TO_TRACE_NAME(vma->vm));
2863
2864                 ret = vma->vm->allocate_va_range(vma->vm,
2865                                                  vma->node.start,
2866                                                  vma->node.size);
2867                 if (ret)
2868                         return ret;
2869         }
2870
2871         ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
2872         if (ret)
2873                 return ret;
2874
2875         vma->bound |= bind_flags;
2876
2877         return 0;
2878 }
2879
2880 /**
2881  * i915_ggtt_view_size - Get the size of a GGTT view.
2882  * @obj: Object the view is of.
2883  * @view: The view in question.
2884  *
2885  * @return The size of the GGTT view in bytes.
2886  */
2887 size_t
2888 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
2889                     const struct i915_ggtt_view *view)
2890 {
2891         if (view->type == I915_GGTT_VIEW_NORMAL) {
2892                 return obj->base.size;
2893         } else if (view->type == I915_GGTT_VIEW_ROTATED) {
2894                 return view->rotation_info.size;
2895         } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
2896                 return view->params.partial.size << PAGE_SHIFT;
2897         } else {
2898                 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
2899                 return obj->base.size;
2900         }
2901 }