drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *    Mika Kuoppala <mika.kuoppala@intel.com>
  27  *
  28  */
  29
  30 #include <generated/utsrelease.h>
  31 #include "i915_drv.h"
  32
  33 static const char *yesno(int v)
  34 {
  35         return v ? "yes" : "no";
  36 }
  37
  38 static const char *ring_str(int ring)
  39 {
  40         switch (ring) {
  41         case RCS: return "render";
  42         case VCS: return "bsd";
  43         case BCS: return "blt";
  44         case VECS: return "vebox";
  45         default: return "";
  46         }
  47 }
  48
  49 static const char *pin_flag(int pinned)
  50 {
  51         if (pinned > 0)
  52                 return " P";
  53         else if (pinned < 0)
  54                 return " p";
  55         else
  56                 return "";
  57 }
  58
  59 static const char *tiling_flag(int tiling)
  60 {
  61         switch (tiling) {
  62         default:
  63         case I915_TILING_NONE: return "";
  64         case I915_TILING_X: return " X";
  65         case I915_TILING_Y: return " Y";
  66         }
  67 }
  68
  69 static const char *dirty_flag(int dirty)
  70 {
  71         return dirty ? " dirty" : "";
  72 }
  73
  74 static const char *purgeable_flag(int purgeable)
  75 {
  76         return purgeable ? " purgeable" : "";
  77 }
  78
  79 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  80 {
  81
  82         if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  83                 e->err = -ENOSPC;
  84                 return false;
  85         }
  86
  87         if (e->bytes == e->size - 1 || e->err)
  88                 return false;
  89
  90         return true;
  91 }
  92
  93 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  94                               unsigned len)
  95 {
  96         if (e->pos + len <= e->start) {
  97                 e->pos += len;
  98                 return false;
  99         }
 100
 101         /* First vsnprintf needs to fit in its entirety for memmove */
 102         if (len >= e->size) {
 103                 e->err = -EIO;
 104                 return false;
 105         }
 106
 107         return true;
 108 }
 109
 110 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
 111                                  unsigned len)
 112 {
 113         /* If this is first printf in this window, adjust it so that
 114          * start position matches start of the buffer
 115          */
 116
 117         if (e->pos < e->start) {
 118                 const size_t off = e->start - e->pos;
 119
 120                 /* Should not happen but be paranoid */
 121                 if (off > len || e->bytes) {
 122                         e->err = -EIO;
 123                         return;
 124                 }
 125
 126                 memmove(e->buf, e->buf + off, len - off);
 127                 e->bytes = len - off;
 128                 e->pos = e->start;
 129                 return;
 130         }
 131
 132         e->bytes += len;
 133         e->pos += len;
 134 }
 135
 136 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 137                                const char *f, va_list args)
 138 {
 139         unsigned len;
 140
 141         if (!__i915_error_ok(e))
 142                 return;
 143
 144         /* Seek the first printf which is hits start position */
 145         if (e->pos < e->start) {
 146                 va_list tmp;
 147
 148                 va_copy(tmp, args);
 149                 len = vsnprintf(NULL, 0, f, tmp);
 150                 va_end(tmp);
 151
 152                 if (!__i915_error_seek(e, len))
 153                         return;
 154         }
 155
 156         len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
 157         if (len >= e->size - e->bytes)
 158                 len = e->size - e->bytes - 1;
 159
 160         __i915_error_advance(e, len);
 161 }
 162
 163 static void i915_error_puts(struct drm_i915_error_state_buf *e,
 164                             const char *str)
 165 {
 166         unsigned len;
 167
 168         if (!__i915_error_ok(e))
 169                 return;
 170
 171         len = strlen(str);
 172
 173         /* Seek the first printf which is hits start position */
 174         if (e->pos < e->start) {
 175                 if (!__i915_error_seek(e, len))
 176                         return;
 177         }
 178
 179         if (len >= e->size - e->bytes)
 180                 len = e->size - e->bytes - 1;
 181         memcpy(e->buf + e->bytes, str, len);
 182
 183         __i915_error_advance(e, len);
 184 }
 185
 186 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 187 #define err_puts(e, s) i915_error_puts(e, s)
 188
 189 static void print_error_buffers(struct drm_i915_error_state_buf *m,
 190                                 const char *name,
 191                                 struct drm_i915_error_buffer *err,
 192                                 int count)
 193 {
 194         err_printf(m, "%s [%d]:\n", name, count);
 195
 196         while (count--) {
 197                 err_printf(m, "  %08x %8u %02x %02x %x %x",
 198                            err->gtt_offset,
 199                            err->size,
 200                            err->read_domains,
 201                            err->write_domain,
 202                            err->rseqno, err->wseqno);
 203                 err_puts(m, pin_flag(err->pinned));
 204                 err_puts(m, tiling_flag(err->tiling));
 205                 err_puts(m, dirty_flag(err->dirty));
 206                 err_puts(m, purgeable_flag(err->purgeable));
 207                 err_puts(m, err->ring != -1 ? " " : "");
 208                 err_puts(m, ring_str(err->ring));
 209                 err_puts(m, i915_cache_level_str(err->cache_level));
 210
 211                 if (err->name)
 212                         err_printf(m, " (name: %d)", err->name);
 213                 if (err->fence_reg != I915_FENCE_REG_NONE)
 214                         err_printf(m, " (fence: %d)", err->fence_reg);
 215
 216                 err_puts(m, "\n");
 217                 err++;
 218         }
 219 }
 220
 221 static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
 222 {
 223         switch (a) {
 224         case HANGCHECK_IDLE:
 225                 return "idle";
 226         case HANGCHECK_WAIT:
 227                 return "wait";
 228         case HANGCHECK_ACTIVE:
 229                 return "active";
 230         case HANGCHECK_KICK:
 231                 return "kick";
 232         case HANGCHECK_HUNG:
 233                 return "hung";
 234         }
 235
 236         return "unknown";
 237 }
 238
 239 static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
 240                                   struct drm_device *dev,
 241                                   struct drm_i915_error_ring *ring)
 242 {
 243         if (!ring->valid)
 244                 return;
 245
 246         err_printf(m, "  HEAD: 0x%08x\n", ring->head);
 247         err_printf(m, "  TAIL: 0x%08x\n", ring->tail);
 248         err_printf(m, "  CTL: 0x%08x\n", ring->ctl);
 249         err_printf(m, "  HWS: 0x%08x\n", ring->hws);
 250         err_printf(m, "  ACTHD: 0x%08x\n", ring->acthd);
 251         err_printf(m, "  IPEIR: 0x%08x\n", ring->ipeir);
 252         err_printf(m, "  IPEHR: 0x%08x\n", ring->ipehr);
 253         err_printf(m, "  INSTDONE: 0x%08x\n", ring->instdone);
 254         if (INTEL_INFO(dev)->gen >= 4) {
 255                 err_printf(m, "  BBADDR: 0x%08llx\n", ring->bbaddr);
 256                 err_printf(m, "  BB_STATE: 0x%08x\n", ring->bbstate);
 257                 err_printf(m, "  INSTPS: 0x%08x\n", ring->instps);
 258         }
 259         err_printf(m, "  INSTPM: 0x%08x\n", ring->instpm);
 260         err_printf(m, "  FADDR: 0x%08x\n", ring->faddr);
 261         if (INTEL_INFO(dev)->gen >= 6) {
 262                 err_printf(m, "  RC PSMI: 0x%08x\n", ring->rc_psmi);
 263                 err_printf(m, "  FAULT_REG: 0x%08x\n", ring->fault_reg);
 264                 err_printf(m, "  SYNC_0: 0x%08x [last synced 0x%08x]\n",
 265                            ring->semaphore_mboxes[0],
 266                            ring->semaphore_seqno[0]);
 267                 err_printf(m, "  SYNC_1: 0x%08x [last synced 0x%08x]\n",
 268                            ring->semaphore_mboxes[1],
 269                            ring->semaphore_seqno[1]);
 270                 if (HAS_VEBOX(dev)) {
 271                         err_printf(m, "  SYNC_2: 0x%08x [last synced 0x%08x]\n",
 272                                    ring->semaphore_mboxes[2],
 273                                    ring->semaphore_seqno[2]);
 274                 }
 275         }
 276         if (USES_PPGTT(dev)) {
 277                 err_printf(m, "  GFX_MODE: 0x%08x\n", ring->vm_info.gfx_mode);
 278
 279                 if (INTEL_INFO(dev)->gen >= 8) {
 280                         int i;
 281                         for (i = 0; i < 4; i++)
 282                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 283                                            i, ring->vm_info.pdp[i]);
 284                 } else {
 285                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 286                                    ring->vm_info.pp_dir_base);
 287                 }
 288         }
 289         err_printf(m, "  seqno: 0x%08x\n", ring->seqno);
 290         err_printf(m, "  waiting: %s\n", yesno(ring->waiting));
 291         err_printf(m, "  ring->head: 0x%08x\n", ring->cpu_ring_head);
 292         err_printf(m, "  ring->tail: 0x%08x\n", ring->cpu_ring_tail);
 293         err_printf(m, "  hangcheck: %s [%d]\n",
 294                    hangcheck_action_to_str(ring->hangcheck_action),
 295                    ring->hangcheck_score);
 296 }
 297
 298 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 299 {
 300         va_list args;
 301
 302         va_start(args, f);
 303         i915_error_vprintf(e, f, args);
 304         va_end(args);
 305 }
 306
 307 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
 308                             const struct i915_error_state_file_priv *error_priv)
 309 {
 310         struct drm_device *dev = error_priv->dev;
 311         drm_i915_private_t *dev_priv = dev->dev_private;
 312         struct drm_i915_error_state *error = error_priv->error;
 313         int i, j, page, offset, elt;
 314
 315         if (!error) {
 316                 err_printf(m, "no error state collected\n");
 317                 goto out;
 318         }
 319
 320         err_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec,
 321                    error->time.tv_usec);
 322         err_printf(m, "Kernel: " UTS_RELEASE "\n");
 323         err_printf(m, "PCI ID: 0x%04x\n", dev->pdev->device);
 324         err_printf(m, "EIR: 0x%08x\n", error->eir);
 325         err_printf(m, "IER: 0x%08x\n", error->ier);
 326         err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 327         err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
 328         err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
 329         err_printf(m, "CCID: 0x%08x\n", error->ccid);
 330         err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
 331
 332         for (i = 0; i < dev_priv->num_fence_regs; i++)
 333                 err_printf(m, "  fence[%d] = %08llx\n", i, error->fence[i]);
 334
 335         for (i = 0; i < ARRAY_SIZE(error->extra_instdone); i++)
 336                 err_printf(m, "  INSTDONE_%d: 0x%08x\n", i,
 337                            error->extra_instdone[i]);
 338
 339         if (INTEL_INFO(dev)->gen >= 6) {
 340                 err_printf(m, "ERROR: 0x%08x\n", error->error);
 341                 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 342         }
 343
 344         if (INTEL_INFO(dev)->gen == 7)
 345                 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
 346
 347         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 348                 err_printf(m, "%s command stream:\n", ring_str(i));
 349                 i915_ring_error_state(m, dev, &error->ring[i]);
 350         }
 351
 352         if (error->active_bo)
 353                 print_error_buffers(m, "Active",
 354                                     error->active_bo[0],
 355                                     error->active_bo_count[0]);
 356
 357         if (error->pinned_bo)
 358                 print_error_buffers(m, "Pinned",
 359                                     error->pinned_bo[0],
 360                                     error->pinned_bo_count[0]);
 361
 362         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 363                 struct drm_i915_error_object *obj;
 364
 365                 if ((obj = error->ring[i].batchbuffer)) {
 366                         err_printf(m, "%s --- gtt_offset = 0x%08x\n",
 367                                    dev_priv->ring[i].name,
 368                                    obj->gtt_offset);
 369                         offset = 0;
 370                         for (page = 0; page < obj->page_count; page++) {
 371                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 372                                         err_printf(m, "%08x :  %08x\n", offset,
 373                                                    obj->pages[page][elt]);
 374                                         offset += 4;
 375                                 }
 376                         }
 377                 }
 378
 379                 if (error->ring[i].num_requests) {
 380                         err_printf(m, "%s --- %d requests\n",
 381                                    dev_priv->ring[i].name,
 382                                    error->ring[i].num_requests);
 383                         for (j = 0; j < error->ring[i].num_requests; j++) {
 384                                 err_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 385                                            error->ring[i].requests[j].seqno,
 386                                            error->ring[i].requests[j].jiffies,
 387                                            error->ring[i].requests[j].tail);
 388                         }
 389                 }
 390
 391                 if ((obj = error->ring[i].ringbuffer)) {
 392                         err_printf(m, "%s --- ringbuffer = 0x%08x\n",
 393                                    dev_priv->ring[i].name,
 394                                    obj->gtt_offset);
 395                         offset = 0;
 396                         for (page = 0; page < obj->page_count; page++) {
 397                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 398                                         err_printf(m, "%08x :  %08x\n",
 399                                                    offset,
 400                                                    obj->pages[page][elt]);
 401                                         offset += 4;
 402                                 }
 403                         }
 404                 }
 405
 406                 if ((obj = error->ring[i].hws_page)) {
 407                         err_printf(m, "%s --- HW Status = 0x%08x\n",
 408                                    dev_priv->ring[i].name,
 409                                    obj->gtt_offset);
 410                         offset = 0;
 411                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 412                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 413                                            offset,
 414                                            obj->pages[0][elt],
 415                                            obj->pages[0][elt+1],
 416                                            obj->pages[0][elt+2],
 417                                            obj->pages[0][elt+3]);
 418                                         offset += 16;
 419                         }
 420                 }
 421
 422                 if ((obj = error->ring[i].ctx)) {
 423                         err_printf(m, "%s --- HW Context = 0x%08x\n",
 424                                    dev_priv->ring[i].name,
 425                                    obj->gtt_offset);
 426                         offset = 0;
 427                         for (elt = 0; elt < PAGE_SIZE/16; elt += 4) {
 428                                 err_printf(m, "[%04x] %08x %08x %08x %08x\n",
 429                                            offset,
 430                                            obj->pages[0][elt],
 431                                            obj->pages[0][elt+1],
 432                                            obj->pages[0][elt+2],
 433                                            obj->pages[0][elt+3]);
 434                                         offset += 16;
 435                         }
 436                 }
 437         }
 438
 439         if (error->overlay)
 440                 intel_overlay_print_error_state(m, error->overlay);
 441
 442         if (error->display)
 443                 intel_display_print_error_state(m, dev, error->display);
 444
 445 out:
 446         if (m->bytes == 0 && m->err)
 447                 return m->err;
 448
 449         return 0;
 450 }
 451
 452 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
 453                               size_t count, loff_t pos)
 454 {
 455         memset(ebuf, 0, sizeof(*ebuf));
 456
 457         /* We need to have enough room to store any i915_error_state printf
 458          * so that we can move it to start position.
 459          */
 460         ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
 461         ebuf->buf = kmalloc(ebuf->size,
 462                                 GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
 463
 464         if (ebuf->buf == NULL) {
 465                 ebuf->size = PAGE_SIZE;
 466                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 467         }
 468
 469         if (ebuf->buf == NULL) {
 470                 ebuf->size = 128;
 471                 ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
 472         }
 473
 474         if (ebuf->buf == NULL)
 475                 return -ENOMEM;
 476
 477         ebuf->start = pos;
 478
 479         return 0;
 480 }
 481
 482 static void i915_error_object_free(struct drm_i915_error_object *obj)
 483 {
 484         int page;
 485
 486         if (obj == NULL)
 487                 return;
 488
 489         for (page = 0; page < obj->page_count; page++)
 490                 kfree(obj->pages[page]);
 491
 492         kfree(obj);
 493 }
 494
 495 static void i915_error_state_free(struct kref *error_ref)
 496 {
 497         struct drm_i915_error_state *error = container_of(error_ref,
 498                                                           typeof(*error), ref);
 499         int i;
 500
 501         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
 502                 i915_error_object_free(error->ring[i].batchbuffer);
 503                 i915_error_object_free(error->ring[i].ringbuffer);
 504                 i915_error_object_free(error->ring[i].hws_page);
 505                 i915_error_object_free(error->ring[i].ctx);
 506                 kfree(error->ring[i].requests);
 507         }
 508
 509         kfree(error->active_bo);
 510         kfree(error->overlay);
 511         kfree(error->display);
 512         kfree(error);
 513 }
 514
 515 static struct drm_i915_error_object *
 516 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
 517                                struct drm_i915_gem_object *src,
 518                                struct i915_address_space *vm,
 519                                const int num_pages)
 520 {
 521         struct drm_i915_error_object *dst;
 522         int i;
 523         u32 reloc_offset;
 524
 525         if (src == NULL || src->pages == NULL)
 526                 return NULL;
 527
 528         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
 529         if (dst == NULL)
 530                 return NULL;
 531
 532         reloc_offset = dst->gtt_offset = i915_gem_obj_offset(src, vm);
 533         for (i = 0; i < num_pages; i++) {
 534                 unsigned long flags;
 535                 void *d;
 536
 537                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 538                 if (d == NULL)
 539                         goto unwind;
 540
 541                 local_irq_save(flags);
 542                 if (src->cache_level == I915_CACHE_NONE &&
 543                     reloc_offset < dev_priv->gtt.mappable_end &&
 544                     src->has_global_gtt_mapping &&
 545                     i915_is_ggtt(vm)) {
 546                         void __iomem *s;
 547
 548                         /* Simply ignore tiling or any overlapping fence.
 549                          * It's part of the error state, and this hopefully
 550                          * captures what the GPU read.
 551                          */
 552
 553                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 554                                                      reloc_offset);
 555                         memcpy_fromio(d, s, PAGE_SIZE);
 556                         io_mapping_unmap_atomic(s);
 557                 } else if (src->stolen) {
 558                         unsigned long offset;
 559
 560                         offset = dev_priv->mm.stolen_base;
 561                         offset += src->stolen->start;
 562                         offset += i << PAGE_SHIFT;
 563
 564                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
 565                 } else {
 566                         struct page *page;
 567                         void *s;
 568
 569                         page = i915_gem_object_get_page(src, i);
 570
 571                         drm_clflush_pages(&page, 1);
 572
 573                         s = kmap_atomic(page);
 574                         memcpy(d, s, PAGE_SIZE);
 575                         kunmap_atomic(s);
 576
 577                         drm_clflush_pages(&page, 1);
 578                 }
 579                 local_irq_restore(flags);
 580
 581                 dst->pages[i] = d;
 582
 583                 reloc_offset += PAGE_SIZE;
 584         }
 585         dst->page_count = num_pages;
 586
 587         return dst;
 588
 589 unwind:
 590         while (i--)
 591                 kfree(dst->pages[i]);
 592         kfree(dst);
 593         return NULL;
 594 }
 595 #define i915_error_object_create(dev_priv, src, vm) \
 596         i915_error_object_create_sized((dev_priv), (src), (vm), \
 597                                        (src)->base.size>>PAGE_SHIFT)
 598
 599 #define i915_error_ggtt_object_create(dev_priv, src) \
 600         i915_error_object_create_sized((dev_priv), (src), &(dev_priv)->gtt.base, \
 601                                        (src)->base.size>>PAGE_SHIFT)
 602
 603 static void capture_bo(struct drm_i915_error_buffer *err,
 604                        struct drm_i915_gem_object *obj)
 605 {
 606         err->size = obj->base.size;
 607         err->name = obj->base.name;
 608         err->rseqno = obj->last_read_seqno;
 609         err->wseqno = obj->last_write_seqno;
 610         err->gtt_offset = i915_gem_obj_ggtt_offset(obj);
 611         err->read_domains = obj->base.read_domains;
 612         err->write_domain = obj->base.write_domain;
 613         err->fence_reg = obj->fence_reg;
 614         err->pinned = 0;
 615         if (i915_gem_obj_is_pinned(obj))
 616                 err->pinned = 1;
 617         if (obj->user_pin_count > 0)
 618                 err->pinned = -1;
 619         err->tiling = obj->tiling_mode;
 620         err->dirty = obj->dirty;
 621         err->purgeable = obj->madv != I915_MADV_WILLNEED;
 622         err->ring = obj->ring ? obj->ring->id : -1;
 623         err->cache_level = obj->cache_level;
 624 }
 625
 626 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
 627                              int count, struct list_head *head)
 628 {
 629         struct i915_vma *vma;
 630         int i = 0;
 631
 632         list_for_each_entry(vma, head, mm_list) {
 633                 capture_bo(err++, vma->obj);
 634                 if (++i == count)
 635                         break;
 636         }
 637
 638         return i;
 639 }
 640
 641 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
 642                              int count, struct list_head *head)
 643 {
 644         struct drm_i915_gem_object *obj;
 645         int i = 0;
 646
 647         list_for_each_entry(obj, head, global_list) {
 648                 if (!i915_gem_obj_is_pinned(obj))
 649                         continue;
 650
 651                 capture_bo(err++, obj);
 652                 if (++i == count)
 653                         break;
 654         }
 655
 656         return i;
 657 }
 658
 659 /* Generate a semi-unique error code. The code is not meant to have meaning, The
 660  * code's only purpose is to try to prevent false duplicated bug reports by
 661  * grossly estimating a GPU error state.
 662  *
 663  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
 664  * the hang if we could strip the GTT offset information from it.
 665  *
 666  * It's only a small step better than a random number in its current form.
 667  */
 668 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
 669                                          struct drm_i915_error_state *error)
 670 {
 671         uint32_t error_code = 0;
 672         int i;
 673
 674         /* IPEHR would be an ideal way to detect errors, as it's the gross
 675          * measure of "the command that hung." However, has some very common
 676          * synchronization commands which almost always appear in the case
 677          * strictly a client bug. Use instdone to differentiate those some.
 678          */
 679         for (i = 0; i < I915_NUM_RINGS; i++)
 680                 if (error->ring[i].hangcheck_action == HANGCHECK_HUNG)
 681                         return error->ring[i].ipehr ^ error->ring[i].instdone;
 682
 683         return error_code;
 684 }
 685
 686 static void i915_gem_record_fences(struct drm_device *dev,
 687                                    struct drm_i915_error_state *error)
 688 {
 689         struct drm_i915_private *dev_priv = dev->dev_private;
 690         int i;
 691
 692         /* Fences */
 693         switch (INTEL_INFO(dev)->gen) {
 694         case 8:
 695         case 7:
 696         case 6:
 697                 for (i = 0; i < dev_priv->num_fence_regs; i++)
 698                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
 699                 break;
 700         case 5:
 701         case 4:
 702                 for (i = 0; i < 16; i++)
 703                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
 704                 break;
 705         case 3:
 706                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
 707                         for (i = 0; i < 8; i++)
 708                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
 709         case 2:
 710                 for (i = 0; i < 8; i++)
 711                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
 712                 break;
 713
 714         default:
 715                 BUG();
 716         }
 717 }
 718
 719 /* This assumes all batchbuffers are executed from the PPGTT. It might have to
 720  * change in the future. */
 721 static bool is_active_vm(struct i915_address_space *vm,
 722                          struct intel_ring_buffer *ring)
 723 {
 724         struct drm_device *dev = vm->dev;
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         struct i915_hw_ppgtt *ppgtt;
 727
 728         if (INTEL_INFO(dev)->gen < 7)
 729                 return i915_is_ggtt(vm);
 730
 731         /* FIXME: This ignores that the global gtt vm is also on this list. */
 732         ppgtt = container_of(vm, struct i915_hw_ppgtt, base);
 733
 734         if (INTEL_INFO(dev)->gen >= 8) {
 735                 u64 pdp0 = (u64)I915_READ(GEN8_RING_PDP_UDW(ring, 0)) << 32;
 736                 pdp0 |=  I915_READ(GEN8_RING_PDP_LDW(ring, 0));
 737                 return pdp0 == ppgtt->pd_dma_addr[0];
 738         } else {
 739                 u32 pp_db;
 740                 pp_db = I915_READ(RING_PP_DIR_BASE(ring));
 741                 return (pp_db >> 10) == ppgtt->pd_offset;
 742         }
 743 }
 744
 745 static struct drm_i915_error_object *
 746 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
 747                              struct intel_ring_buffer *ring)
 748 {
 749         struct i915_address_space *vm;
 750         struct i915_vma *vma;
 751         struct drm_i915_gem_object *obj;
 752         bool found_active = false;
 753         u32 seqno;
 754
 755         if (!ring->get_seqno)
 756                 return NULL;
 757
 758         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
 759                 u32 acthd = I915_READ(ACTHD);
 760
 761                 if (WARN_ON(ring->id != RCS))
 762                         return NULL;
 763
 764                 obj = ring->scratch.obj;
 765                 if (obj != NULL &&
 766                     acthd >= i915_gem_obj_ggtt_offset(obj) &&
 767                     acthd < i915_gem_obj_ggtt_offset(obj) + obj->base.size)
 768                         return i915_error_ggtt_object_create(dev_priv, obj);
 769         }
 770
 771         seqno = ring->get_seqno(ring, false);
 772         list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
 773                 if (!is_active_vm(vm, ring))
 774                         continue;
 775
 776                 found_active = true;
 777
 778                 list_for_each_entry(vma, &vm->active_list, mm_list) {
 779                         obj = vma->obj;
 780                         if (obj->ring != ring)
 781                                 continue;
 782
 783                         if (i915_seqno_passed(seqno, obj->last_read_seqno))
 784                                 continue;
 785
 786                         if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
 787                                 continue;
 788
 789                         /* We need to copy these to an anonymous buffer as the simplest
 790                          * method to avoid being overwritten by userspace.
 791                          */
 792                         return i915_error_object_create(dev_priv, obj, vm);
 793                 }
 794         }
 795
 796         WARN_ON(!found_active);
 797         return NULL;
 798 }
 799
 800 static void i915_record_ring_state(struct drm_device *dev,
 801                                    struct intel_ring_buffer *ring,
 802                                    struct drm_i915_error_ring *ering)
 803 {
 804         struct drm_i915_private *dev_priv = dev->dev_private;
 805
 806         if (INTEL_INFO(dev)->gen >= 6) {
 807                 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50);
 808                 ering->fault_reg = I915_READ(RING_FAULT_REG(ring));
 809                 ering->semaphore_mboxes[0]
 810                         = I915_READ(RING_SYNC_0(ring->mmio_base));
 811                 ering->semaphore_mboxes[1]
 812                         = I915_READ(RING_SYNC_1(ring->mmio_base));
 813                 ering->semaphore_seqno[0] = ring->sync_seqno[0];
 814                 ering->semaphore_seqno[1] = ring->sync_seqno[1];
 815         }
 816
 817         if (HAS_VEBOX(dev)) {
 818                 ering->semaphore_mboxes[2] =
 819                         I915_READ(RING_SYNC_2(ring->mmio_base));
 820                 ering->semaphore_seqno[2] = ring->sync_seqno[2];
 821         }
 822
 823         if (INTEL_INFO(dev)->gen >= 4) {
 824                 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base));
 825                 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base));
 826                 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
 827                 ering->instdone = I915_READ(RING_INSTDONE(ring->mmio_base));
 828                 ering->instps = I915_READ(RING_INSTPS(ring->mmio_base));
 829                 ering->bbaddr = I915_READ(RING_BBADDR(ring->mmio_base));
 830                 if (INTEL_INFO(dev)->gen >= 8)
 831                         ering->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(ring->mmio_base)) << 32;
 832                 ering->bbstate = I915_READ(RING_BBSTATE(ring->mmio_base));
 833         } else {
 834                 ering->faddr = I915_READ(DMA_FADD_I8XX);
 835                 ering->ipeir = I915_READ(IPEIR);
 836                 ering->ipehr = I915_READ(IPEHR);
 837                 ering->instdone = I915_READ(INSTDONE);
 838         }
 839
 840         ering->waiting = waitqueue_active(&ring->irq_queue);
 841         ering->instpm = I915_READ(RING_INSTPM(ring->mmio_base));
 842         ering->seqno = ring->get_seqno(ring, false);
 843         ering->acthd = intel_ring_get_active_head(ring);
 844         ering->head = I915_READ_HEAD(ring);
 845         ering->tail = I915_READ_TAIL(ring);
 846         ering->ctl = I915_READ_CTL(ring);
 847
 848         if (I915_NEED_GFX_HWS(dev)) {
 849                 int mmio;
 850
 851                 if (IS_GEN7(dev)) {
 852                         switch (ring->id) {
 853                         default:
 854                         case RCS:
 855                                 mmio = RENDER_HWS_PGA_GEN7;
 856                                 break;
 857                         case BCS:
 858                                 mmio = BLT_HWS_PGA_GEN7;
 859                                 break;
 860                         case VCS:
 861                                 mmio = BSD_HWS_PGA_GEN7;
 862                                 break;
 863                         case VECS:
 864                                 mmio = VEBOX_HWS_PGA_GEN7;
 865                                 break;
 866                         }
 867                 } else if (IS_GEN6(ring->dev)) {
 868                         mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 869                 } else {
 870                         /* XXX: gen8 returns to sanity */
 871                         mmio = RING_HWS_PGA(ring->mmio_base);
 872                 }
 873
 874                 ering->hws = I915_READ(mmio);
 875         }
 876
 877         ering->cpu_ring_head = ring->head;
 878         ering->cpu_ring_tail = ring->tail;
 879
 880         ering->hangcheck_score = ring->hangcheck.score;
 881         ering->hangcheck_action = ring->hangcheck.action;
 882
 883         if (USES_PPGTT(dev)) {
 884                 int i;
 885
 886                 ering->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(ring));
 887
 888                 switch (INTEL_INFO(dev)->gen) {
 889                 case 8:
 890                         for (i = 0; i < 4; i++) {
 891                                 ering->vm_info.pdp[i] =
 892                                         I915_READ(GEN8_RING_PDP_UDW(ring, i));
 893                                 ering->vm_info.pdp[i] <<= 32;
 894                                 ering->vm_info.pdp[i] |=
 895                                         I915_READ(GEN8_RING_PDP_LDW(ring, i));
 896                         }
 897                         break;
 898                 case 7:
 899                         ering->vm_info.pp_dir_base = RING_PP_DIR_BASE(ring);
 900                         break;
 901                 case 6:
 902                         ering->vm_info.pp_dir_base = RING_PP_DIR_BASE_READ(ring);
 903                         break;
 904                 }
 905         }
 906 }
 907
 908
 909 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
 910                                            struct drm_i915_error_state *error,
 911                                            struct drm_i915_error_ring *ering)
 912 {
 913         struct drm_i915_private *dev_priv = ring->dev->dev_private;
 914         struct drm_i915_gem_object *obj;
 915
 916         /* Currently render ring is the only HW context user */
 917         if (ring->id != RCS || !error->ccid)
 918                 return;
 919
 920         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 921                 if ((error->ccid & PAGE_MASK) == i915_gem_obj_ggtt_offset(obj)) {
 922                         ering->ctx = i915_error_object_create_sized(dev_priv,
 923                                                                     obj,
 924                                                                     &dev_priv->gtt.base,
 925                                                                     1);
 926                         break;
 927                 }
 928         }
 929 }
 930
 931 static void i915_gem_record_rings(struct drm_device *dev,
 932                                   struct drm_i915_error_state *error)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         struct drm_i915_gem_request *request;
 936         int i, count;
 937
 938         for (i = 0; i < I915_NUM_RINGS; i++) {
 939                 struct intel_ring_buffer *ring = &dev_priv->ring[i];
 940
 941                 if (ring->dev == NULL)
 942                         continue;
 943
 944                 error->ring[i].valid = true;
 945
 946                 i915_record_ring_state(dev, ring, &error->ring[i]);
 947
 948                 error->ring[i].batchbuffer =
 949                         i915_error_first_batchbuffer(dev_priv, ring);
 950
 951                 error->ring[i].ringbuffer =
 952                         i915_error_ggtt_object_create(dev_priv, ring->obj);
 953
 954                 if (ring->status_page.obj)
 955                         error->ring[i].hws_page =
 956                                 i915_error_ggtt_object_create(dev_priv, ring->status_page.obj);
 957
 958                 i915_gem_record_active_context(ring, error, &error->ring[i]);
 959
 960                 count = 0;
 961                 list_for_each_entry(request, &ring->request_list, list)
 962                         count++;
 963
 964                 error->ring[i].num_requests = count;
 965                 error->ring[i].requests =
 966                         kcalloc(count, sizeof(*error->ring[i].requests),
 967                                 GFP_ATOMIC);
 968                 if (error->ring[i].requests == NULL) {
 969                         error->ring[i].num_requests = 0;
 970                         continue;
 971                 }
 972
 973                 count = 0;
 974                 list_for_each_entry(request, &ring->request_list, list) {
 975                         struct drm_i915_error_request *erq;
 976
 977                         erq = &error->ring[i].requests[count++];
 978                         erq->seqno = request->seqno;
 979                         erq->jiffies = request->emitted_jiffies;
 980                         erq->tail = request->tail;
 981                 }
 982         }
 983 }
 984
 985 /* FIXME: Since pin count/bound list is global, we duplicate what we capture per
 986  * VM.
 987  */
 988 static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
 989                                 struct drm_i915_error_state *error,
 990                                 struct i915_address_space *vm,
 991                                 const int ndx)
 992 {
 993         struct drm_i915_error_buffer *active_bo = NULL, *pinned_bo = NULL;
 994         struct drm_i915_gem_object *obj;
 995         struct i915_vma *vma;
 996         int i;
 997
 998         i = 0;
 999         list_for_each_entry(vma, &vm->active_list, mm_list)
1000                 i++;
1001         error->active_bo_count[ndx] = i;
1002         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list)
1003                 if (i915_gem_obj_is_pinned(obj))
1004                         i++;
1005         error->pinned_bo_count[ndx] = i - error->active_bo_count[ndx];
1006
1007         if (i) {
1008                 active_bo = kcalloc(i, sizeof(*active_bo), GFP_ATOMIC);
1009                 if (active_bo)
1010                         pinned_bo = active_bo + error->active_bo_count[ndx];
1011         }
1012
1013         if (active_bo)
1014                 error->active_bo_count[ndx] =
1015                         capture_active_bo(active_bo,
1016                                           error->active_bo_count[ndx],
1017                                           &vm->active_list);
1018
1019         if (pinned_bo)
1020                 error->pinned_bo_count[ndx] =
1021                         capture_pinned_bo(pinned_bo,
1022                                           error->pinned_bo_count[ndx],
1023                                           &dev_priv->mm.bound_list);
1024         error->active_bo[ndx] = active_bo;
1025         error->pinned_bo[ndx] = pinned_bo;
1026 }
1027
1028 static void i915_gem_capture_buffers(struct drm_i915_private *dev_priv,
1029                                      struct drm_i915_error_state *error)
1030 {
1031         struct i915_address_space *vm;
1032         int cnt = 0, i = 0;
1033
1034         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1035                 cnt++;
1036
1037         error->active_bo = kcalloc(cnt, sizeof(*error->active_bo), GFP_ATOMIC);
1038         error->pinned_bo = kcalloc(cnt, sizeof(*error->pinned_bo), GFP_ATOMIC);
1039         error->active_bo_count = kcalloc(cnt, sizeof(*error->active_bo_count),
1040                                          GFP_ATOMIC);
1041         error->pinned_bo_count = kcalloc(cnt, sizeof(*error->pinned_bo_count),
1042                                          GFP_ATOMIC);
1043
1044         list_for_each_entry(vm, &dev_priv->vm_list, global_link)
1045                 i915_gem_capture_vm(dev_priv, error, vm, i++);
1046 }
1047
1048 /* Capture all registers which don't fit into another category. */
1049 static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
1050                                    struct drm_i915_error_state *error)
1051 {
1052         struct drm_device *dev = dev_priv->dev;
1053         int pipe;
1054
1055         /* General organization
1056          * 1. Registers specific to a single generation
1057          * 2. Registers which belong to multiple generations
1058          * 3. Feature specific registers.
1059          * 4. Everything else
1060          * Please try to follow the order.
1061          */
1062
1063         /* 1: Registers specific to a single generation */
1064         if (IS_VALLEYVIEW(dev)) {
1065                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1066                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1067         }
1068
1069         if (IS_GEN7(dev))
1070                 error->err_int = I915_READ(GEN7_ERR_INT);
1071
1072         if (IS_GEN6(dev)) {
1073                 error->forcewake = I915_READ(FORCEWAKE);
1074                 error->gab_ctl = I915_READ(GAB_CTL);
1075                 error->gfx_mode = I915_READ(GFX_MODE);
1076         }
1077
1078         if (IS_GEN2(dev))
1079                 error->ier = I915_READ16(IER);
1080
1081         /* 2: Registers which belong to multiple generations */
1082         if (INTEL_INFO(dev)->gen >= 7)
1083                 error->forcewake = I915_READ(FORCEWAKE_MT);
1084
1085         if (INTEL_INFO(dev)->gen >= 6) {
1086                 error->derrmr = I915_READ(DERRMR);
1087                 error->error = I915_READ(ERROR_GEN6);
1088                 error->done_reg = I915_READ(DONE_REG);
1089         }
1090
1091         /* 3: Feature specific registers */
1092         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1093                 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1094                 error->gac_eco = I915_READ(GAC_ECO_BITS);
1095         }
1096
1097         /* 4: Everything else */
1098         if (HAS_HW_CONTEXTS(dev))
1099                 error->ccid = I915_READ(CCID);
1100
1101         if (HAS_PCH_SPLIT(dev))
1102                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1103         else {
1104                 error->ier = I915_READ(IER);
1105                 for_each_pipe(pipe)
1106                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1107         }
1108
1109         /* 4: Everything else */
1110         error->eir = I915_READ(EIR);
1111         error->pgtbl_er = I915_READ(PGTBL_ER);
1112
1113         i915_get_extra_instdone(dev, error->extra_instdone);
1114 }
1115
1116 /**
1117  * i915_capture_error_state - capture an error record for later analysis
1118  * @dev: drm device
1119  *
1120  * Should be called when an error is detected (either a hang or an error
1121  * interrupt) to capture error state from the time of the error.  Fills
1122  * out a structure which becomes available in debugfs for user level tools
1123  * to pick up.
1124  */
1125 void i915_capture_error_state(struct drm_device *dev)
1126 {
1127         static bool warned;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129         struct drm_i915_error_state *error;
1130         unsigned long flags;
1131         uint32_t ecode;
1132
1133         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1134         error = dev_priv->gpu_error.first_error;
1135         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1136         if (error)
1137                 return;
1138
1139         /* Account for pipe specific data like PIPE*STAT */
1140         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1141         if (!error) {
1142                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1143                 return;
1144         }
1145
1146         DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1147                  dev->primary->index);
1148         kref_init(&error->ref);
1149
1150         i915_capture_reg_state(dev_priv, error);
1151         i915_gem_capture_buffers(dev_priv, error);
1152         i915_gem_record_fences(dev, error);
1153         i915_gem_record_rings(dev, error);
1154         ecode = i915_error_generate_code(dev_priv, error);
1155
1156         if (!warned) {
1157                 DRM_INFO("GPU HANG [%x]\n", ecode);
1158                 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1159                 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1160                 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1161                 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1162                 warned = true;
1163         }
1164
1165         do_gettimeofday(&error->time);
1166
1167         error->overlay = intel_overlay_capture_error_state(dev);
1168         error->display = intel_display_capture_error_state(dev);
1169
1170         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1171         if (dev_priv->gpu_error.first_error == NULL) {
1172                 dev_priv->gpu_error.first_error = error;
1173                 error = NULL;
1174         }
1175         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1176
1177         if (error)
1178                 i915_error_state_free(&error->ref);
1179 }
1180
1181 void i915_error_state_get(struct drm_device *dev,
1182                           struct i915_error_state_file_priv *error_priv)
1183 {
1184         struct drm_i915_private *dev_priv = dev->dev_private;
1185         unsigned long flags;
1186
1187         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1188         error_priv->error = dev_priv->gpu_error.first_error;
1189         if (error_priv->error)
1190                 kref_get(&error_priv->error->ref);
1191         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1192
1193 }
1194
1195 void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
1196 {
1197         if (error_priv->error)
1198                 kref_put(&error_priv->error->ref, i915_error_state_free);
1199 }
1200
1201 void i915_destroy_error_state(struct drm_device *dev)
1202 {
1203         struct drm_i915_private *dev_priv = dev->dev_private;
1204         struct drm_i915_error_state *error;
1205         unsigned long flags;
1206
1207         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1208         error = dev_priv->gpu_error.first_error;
1209         dev_priv->gpu_error.first_error = NULL;
1210         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1211
1212         if (error)
1213                 kref_put(&error->ref, i915_error_state_free);
1214 }
1215
1216 const char *i915_cache_level_str(int type)
1217 {
1218         switch (type) {
1219         case I915_CACHE_NONE: return " uncached";
1220         case I915_CACHE_LLC: return " snooped or LLC";
1221         case I915_CACHE_L3_LLC: return " L3+LLC";
1222         case I915_CACHE_WT: return " WT";
1223         default: return "";
1224         }
1225 }
1226
1227 /* NB: please notice the memset */
1228 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
1229 {
1230         struct drm_i915_private *dev_priv = dev->dev_private;
1231         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1232
1233         switch (INTEL_INFO(dev)->gen) {
1234         case 2:
1235         case 3:
1236                 instdone[0] = I915_READ(INSTDONE);
1237                 break;
1238         case 4:
1239         case 5:
1240         case 6:
1241                 instdone[0] = I915_READ(INSTDONE_I965);
1242                 instdone[1] = I915_READ(INSTDONE1);
1243                 break;
1244         default:
1245                 WARN_ONCE(1, "Unsupported platform\n");
1246         case 7:
1247         case 8:
1248                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1249                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1250                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1251                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1252                 break;
1253         }
1254 }