drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  50         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  51         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  52         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  53 };
  54
  55 static const u32 hpd_mask_i915[] = {
  56         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  57         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  58         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  59         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  60         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  61         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  62 };
  63
  64 static const u32 hpd_status_gen4[] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  71 };
  72
  73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 /* For display hotplug interrupt */
  83 static void
  84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85 {
  86         assert_spin_locked(&dev_priv->irq_lock);
  87
  88         if (dev_priv->pc8.irqs_disabled) {
  89                 WARN(1, "IRQs disabled\n");
  90                 dev_priv->pc8.regsave.deimr &= ~mask;
  91                 return;
  92         }
  93
  94         if ((dev_priv->irq_mask & mask) != 0) {
  95                 dev_priv->irq_mask &= ~mask;
  96                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  97                 POSTING_READ(DEIMR);
  98         }
  99 }
 100
 101 static void
 102 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 103 {
 104         assert_spin_locked(&dev_priv->irq_lock);
 105
 106         if (dev_priv->pc8.irqs_disabled) {
 107                 WARN(1, "IRQs disabled\n");
 108                 dev_priv->pc8.regsave.deimr |= mask;
 109                 return;
 110         }
 111
 112         if ((dev_priv->irq_mask & mask) != mask) {
 113                 dev_priv->irq_mask |= mask;
 114                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 115                 POSTING_READ(DEIMR);
 116         }
 117 }
 118
 119 /**
 120  * ilk_update_gt_irq - update GTIMR
 121  * @dev_priv: driver private
 122  * @interrupt_mask: mask of interrupt bits to update
 123  * @enabled_irq_mask: mask of interrupt bits to enable
 124  */
 125 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 126                               uint32_t interrupt_mask,
 127                               uint32_t enabled_irq_mask)
 128 {
 129         assert_spin_locked(&dev_priv->irq_lock);
 130
 131         if (dev_priv->pc8.irqs_disabled) {
 132                 WARN(1, "IRQs disabled\n");
 133                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 134                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 135                                                 interrupt_mask);
 136                 return;
 137         }
 138
 139         dev_priv->gt_irq_mask &= ~interrupt_mask;
 140         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 141         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 142         POSTING_READ(GTIMR);
 143 }
 144
 145 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 146 {
 147         ilk_update_gt_irq(dev_priv, mask, mask);
 148 }
 149
 150 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 151 {
 152         ilk_update_gt_irq(dev_priv, mask, 0);
 153 }
 154
 155 /**
 156   * snb_update_pm_irq - update GEN6_PMIMR
 157   * @dev_priv: driver private
 158   * @interrupt_mask: mask of interrupt bits to update
 159   * @enabled_irq_mask: mask of interrupt bits to enable
 160   */
 161 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 162                               uint32_t interrupt_mask,
 163                               uint32_t enabled_irq_mask)
 164 {
 165         uint32_t new_val;
 166
 167         assert_spin_locked(&dev_priv->irq_lock);
 168
 169         if (dev_priv->pc8.irqs_disabled) {
 170                 WARN(1, "IRQs disabled\n");
 171                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 172                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 173                                                      interrupt_mask);
 174                 return;
 175         }
 176
 177         new_val = dev_priv->pm_irq_mask;
 178         new_val &= ~interrupt_mask;
 179         new_val |= (~enabled_irq_mask & interrupt_mask);
 180
 181         if (new_val != dev_priv->pm_irq_mask) {
 182                 dev_priv->pm_irq_mask = new_val;
 183                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 184                 POSTING_READ(GEN6_PMIMR);
 185         }
 186 }
 187
 188 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 189 {
 190         snb_update_pm_irq(dev_priv, mask, mask);
 191 }
 192
 193 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 194 {
 195         snb_update_pm_irq(dev_priv, mask, 0);
 196 }
 197
 198 static bool ivb_can_enable_err_int(struct drm_device *dev)
 199 {
 200         struct drm_i915_private *dev_priv = dev->dev_private;
 201         struct intel_crtc *crtc;
 202         enum pipe pipe;
 203
 204         assert_spin_locked(&dev_priv->irq_lock);
 205
 206         for_each_pipe(pipe) {
 207                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 208
 209                 if (crtc->cpu_fifo_underrun_disabled)
 210                         return false;
 211         }
 212
 213         return true;
 214 }
 215
 216 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 217 {
 218         struct drm_i915_private *dev_priv = dev->dev_private;
 219         enum pipe pipe;
 220         struct intel_crtc *crtc;
 221
 222         assert_spin_locked(&dev_priv->irq_lock);
 223
 224         for_each_pipe(pipe) {
 225                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 226
 227                 if (crtc->pch_fifo_underrun_disabled)
 228                         return false;
 229         }
 230
 231         return true;
 232 }
 233
 234 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 235                                                  enum pipe pipe, bool enable)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 239                                           DE_PIPEB_FIFO_UNDERRUN;
 240
 241         if (enable)
 242                 ironlake_enable_display_irq(dev_priv, bit);
 243         else
 244                 ironlake_disable_display_irq(dev_priv, bit);
 245 }
 246
 247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                   enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         if (enable) {
 252                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 253
 254                 if (!ivb_can_enable_err_int(dev))
 255                         return;
 256
 257                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 258         } else {
 259                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 260
 261                 /* Change the state _after_ we've read out the current one. */
 262                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 263
 264                 if (!was_enabled &&
 265                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 266                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 267                                       pipe_name(pipe));
 268                 }
 269         }
 270 }
 271
 272 /**
 273  * ibx_display_interrupt_update - update SDEIMR
 274  * @dev_priv: driver private
 275  * @interrupt_mask: mask of interrupt bits to update
 276  * @enabled_irq_mask: mask of interrupt bits to enable
 277  */
 278 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 279                                          uint32_t interrupt_mask,
 280                                          uint32_t enabled_irq_mask)
 281 {
 282         uint32_t sdeimr = I915_READ(SDEIMR);
 283         sdeimr &= ~interrupt_mask;
 284         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 285
 286         assert_spin_locked(&dev_priv->irq_lock);
 287
 288         if (dev_priv->pc8.irqs_disabled &&
 289             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 290                 WARN(1, "IRQs disabled\n");
 291                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 292                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 293                                                  interrupt_mask);
 294                 return;
 295         }
 296
 297         I915_WRITE(SDEIMR, sdeimr);
 298         POSTING_READ(SDEIMR);
 299 }
 300 #define ibx_enable_display_interrupt(dev_priv, bits) \
 301         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 302 #define ibx_disable_display_interrupt(dev_priv, bits) \
 303         ibx_display_interrupt_update((dev_priv), (bits), 0)
 304
 305 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 306                                             enum transcoder pch_transcoder,
 307                                             bool enable)
 308 {
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 311                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 312
 313         if (enable)
 314                 ibx_enable_display_interrupt(dev_priv, bit);
 315         else
 316                 ibx_disable_display_interrupt(dev_priv, bit);
 317 }
 318
 319 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 320                                             enum transcoder pch_transcoder,
 321                                             bool enable)
 322 {
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324
 325         if (enable) {
 326                 I915_WRITE(SERR_INT,
 327                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 328
 329                 if (!cpt_can_enable_serr_int(dev))
 330                         return;
 331
 332                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 333         } else {
 334                 uint32_t tmp = I915_READ(SERR_INT);
 335                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 336
 337                 /* Change the state _after_ we've read out the current one. */
 338                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 339
 340                 if (!was_enabled &&
 341                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 342                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 343                                       transcoder_name(pch_transcoder));
 344                 }
 345         }
 346 }
 347
 348 /**
 349  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 350  * @dev: drm device
 351  * @pipe: pipe
 352  * @enable: true if we want to report FIFO underrun errors, false otherwise
 353  *
 354  * This function makes us disable or enable CPU fifo underruns for a specific
 355  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 356  * reporting for one pipe may also disable all the other CPU error interruts for
 357  * the other pipes, due to the fact that there's just one interrupt mask/enable
 358  * bit for all the pipes.
 359  *
 360  * Returns the previous state of underrun reporting.
 361  */
 362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 363                                            enum pipe pipe, bool enable)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 368         unsigned long flags;
 369         bool ret;
 370
 371         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 372
 373         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 374
 375         if (enable == ret)
 376                 goto done;
 377
 378         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 379
 380         if (IS_GEN5(dev) || IS_GEN6(dev))
 381                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 382         else if (IS_GEN7(dev))
 383                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 384
 385 done:
 386         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 387         return ret;
 388 }
 389
 390 /**
 391  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 392  * @dev: drm device
 393  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 394  * @enable: true if we want to report FIFO underrun errors, false otherwise
 395  *
 396  * This function makes us disable or enable PCH fifo underruns for a specific
 397  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 398  * underrun reporting for one transcoder may also disable all the other PCH
 399  * error interruts for the other transcoders, due to the fact that there's just
 400  * one interrupt mask/enable bit for all the transcoders.
 401  *
 402  * Returns the previous state of underrun reporting.
 403  */
 404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 405                                            enum transcoder pch_transcoder,
 406                                            bool enable)
 407 {
 408         struct drm_i915_private *dev_priv = dev->dev_private;
 409         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 411         unsigned long flags;
 412         bool ret;
 413
 414         /*
 415          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 416          * has only one pch transcoder A that all pipes can use. To avoid racy
 417          * pch transcoder -> pipe lookups from interrupt code simply store the
 418          * underrun statistics in crtc A. Since we never expose this anywhere
 419          * nor use it outside of the fifo underrun code here using the "wrong"
 420          * crtc on LPT won't cause issues.
 421          */
 422
 423         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 424
 425         ret = !intel_crtc->pch_fifo_underrun_disabled;
 426
 427         if (enable == ret)
 428                 goto done;
 429
 430         intel_crtc->pch_fifo_underrun_disabled = !enable;
 431
 432         if (HAS_PCH_IBX(dev))
 433                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 434         else
 435                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 436
 437 done:
 438         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 439         return ret;
 440 }
 441
 442
 443 void
 444 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 445 {
 446         u32 reg = PIPESTAT(pipe);
 447         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 448
 449         assert_spin_locked(&dev_priv->irq_lock);
 450
 451         if ((pipestat & mask) == mask)
 452                 return;
 453
 454         /* Enable the interrupt, clear any pending status */
 455         pipestat |= mask | (mask >> 16);
 456         I915_WRITE(reg, pipestat);
 457         POSTING_READ(reg);
 458 }
 459
 460 void
 461 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 462 {
 463         u32 reg = PIPESTAT(pipe);
 464         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 465
 466         assert_spin_locked(&dev_priv->irq_lock);
 467
 468         if ((pipestat & mask) == 0)
 469                 return;
 470
 471         pipestat &= ~mask;
 472         I915_WRITE(reg, pipestat);
 473         POSTING_READ(reg);
 474 }
 475
 476 /**
 477  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 478  */
 479 static void i915_enable_asle_pipestat(struct drm_device *dev)
 480 {
 481         drm_i915_private_t *dev_priv = dev->dev_private;
 482         unsigned long irqflags;
 483
 484         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 485                 return;
 486
 487         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 488
 489         i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
 490         if (INTEL_INFO(dev)->gen >= 4)
 491                 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
 492
 493         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 494 }
 495
 496 /**
 497  * i915_pipe_enabled - check if a pipe is enabled
 498  * @dev: DRM device
 499  * @pipe: pipe to check
 500  *
 501  * Reading certain registers when the pipe is disabled can hang the chip.
 502  * Use this routine to make sure the PLL is running and the pipe is active
 503  * before reading such registers if unsure.
 504  */
 505 static int
 506 i915_pipe_enabled(struct drm_device *dev, int pipe)
 507 {
 508         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 509
 510         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 511                 /* Locking is horribly broken here, but whatever. */
 512                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 513                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 514
 515                 return intel_crtc->active;
 516         } else {
 517                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 518         }
 519 }
 520
 521 /* Called from drm generic code, passed a 'crtc', which
 522  * we use as a pipe index
 523  */
 524 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 525 {
 526         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 527         unsigned long high_frame;
 528         unsigned long low_frame;
 529         u32 high1, high2, low;
 530
 531         if (!i915_pipe_enabled(dev, pipe)) {
 532                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 533                                 "pipe %c\n", pipe_name(pipe));
 534                 return 0;
 535         }
 536
 537         high_frame = PIPEFRAME(pipe);
 538         low_frame = PIPEFRAMEPIXEL(pipe);
 539
 540         /*
 541          * High & low register fields aren't synchronized, so make sure
 542          * we get a low value that's stable across two reads of the high
 543          * register.
 544          */
 545         do {
 546                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 547                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 548                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 549         } while (high1 != high2);
 550
 551         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 552         low >>= PIPE_FRAME_LOW_SHIFT;
 553         return (high1 << 8) | low;
 554 }
 555
 556 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 557 {
 558         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 559         int reg = PIPE_FRMCOUNT_GM45(pipe);
 560
 561         if (!i915_pipe_enabled(dev, pipe)) {
 562                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 563                                  "pipe %c\n", pipe_name(pipe));
 564                 return 0;
 565         }
 566
 567         return I915_READ(reg);
 568 }
 569
 570 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 571                              int *vpos, int *hpos)
 572 {
 573         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 574         u32 vbl = 0, position = 0;
 575         int vbl_start, vbl_end, htotal, vtotal;
 576         bool in_vbl = true;
 577         int ret = 0;
 578         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 579                                                                       pipe);
 580
 581         if (!i915_pipe_enabled(dev, pipe)) {
 582                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 583                                  "pipe %c\n", pipe_name(pipe));
 584                 return 0;
 585         }
 586
 587         /* Get vtotal. */
 588         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 589
 590         if (INTEL_INFO(dev)->gen >= 4) {
 591                 /* No obvious pixelcount register. Only query vertical
 592                  * scanout position from Display scan line register.
 593                  */
 594                 position = I915_READ(PIPEDSL(pipe));
 595
 596                 /* Decode into vertical scanout position. Don't have
 597                  * horizontal scanout position.
 598                  */
 599                 *vpos = position & 0x1fff;
 600                 *hpos = 0;
 601         } else {
 602                 /* Have access to pixelcount since start of frame.
 603                  * We can split this into vertical and horizontal
 604                  * scanout position.
 605                  */
 606                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 607
 608                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 609                 *vpos = position / htotal;
 610                 *hpos = position - (*vpos * htotal);
 611         }
 612
 613         /* Query vblank area. */
 614         vbl = I915_READ(VBLANK(cpu_transcoder));
 615
 616         /* Test position against vblank region. */
 617         vbl_start = vbl & 0x1fff;
 618         vbl_end = (vbl >> 16) & 0x1fff;
 619
 620         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 621                 in_vbl = false;
 622
 623         /* Inside "upper part" of vblank area? Apply corrective offset: */
 624         if (in_vbl && (*vpos >= vbl_start))
 625                 *vpos = *vpos - vtotal;
 626
 627         /* Readouts valid? */
 628         if (vbl > 0)
 629                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 630
 631         /* In vblank? */
 632         if (in_vbl)
 633                 ret |= DRM_SCANOUTPOS_INVBL;
 634
 635         return ret;
 636 }
 637
 638 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 639                               int *max_error,
 640                               struct timeval *vblank_time,
 641                               unsigned flags)
 642 {
 643         struct drm_crtc *crtc;
 644
 645         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 646                 DRM_ERROR("Invalid crtc %d\n", pipe);
 647                 return -EINVAL;
 648         }
 649
 650         /* Get drm_crtc to timestamp: */
 651         crtc = intel_get_crtc_for_pipe(dev, pipe);
 652         if (crtc == NULL) {
 653                 DRM_ERROR("Invalid crtc %d\n", pipe);
 654                 return -EINVAL;
 655         }
 656
 657         if (!crtc->enabled) {
 658                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 659                 return -EBUSY;
 660         }
 661
 662         /* Helper routine in DRM core does all the work: */
 663         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 664                                                      vblank_time, flags,
 665                                                      crtc);
 666 }
 667
 668 static bool intel_hpd_irq_event(struct drm_device *dev,
 669                                 struct drm_connector *connector)
 670 {
 671         enum drm_connector_status old_status;
 672
 673         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 674         old_status = connector->status;
 675
 676         connector->status = connector->funcs->detect(connector, false);
 677         if (old_status == connector->status)
 678                 return false;
 679
 680         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 681                       connector->base.id,
 682                       drm_get_connector_name(connector),
 683                       drm_get_connector_status_name(old_status),
 684                       drm_get_connector_status_name(connector->status));
 685
 686         return true;
 687 }
 688
 689 /*
 690  * Handle hotplug events outside the interrupt handler proper.
 691  */
 692 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 693
 694 static void i915_hotplug_work_func(struct work_struct *work)
 695 {
 696         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 697                                                     hotplug_work);
 698         struct drm_device *dev = dev_priv->dev;
 699         struct drm_mode_config *mode_config = &dev->mode_config;
 700         struct intel_connector *intel_connector;
 701         struct intel_encoder *intel_encoder;
 702         struct drm_connector *connector;
 703         unsigned long irqflags;
 704         bool hpd_disabled = false;
 705         bool changed = false;
 706         u32 hpd_event_bits;
 707
 708         /* HPD irq before everything is fully set up. */
 709         if (!dev_priv->enable_hotplug_processing)
 710                 return;
 711
 712         mutex_lock(&mode_config->mutex);
 713         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 714
 715         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 716
 717         hpd_event_bits = dev_priv->hpd_event_bits;
 718         dev_priv->hpd_event_bits = 0;
 719         list_for_each_entry(connector, &mode_config->connector_list, head) {
 720                 intel_connector = to_intel_connector(connector);
 721                 intel_encoder = intel_connector->encoder;
 722                 if (intel_encoder->hpd_pin > HPD_NONE &&
 723                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 724                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 725                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 726                                  "switching from hotplug detection to polling\n",
 727                                 drm_get_connector_name(connector));
 728                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 729                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 730                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 731                         hpd_disabled = true;
 732                 }
 733                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 734                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 735                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 736                 }
 737         }
 738          /* if there were no outputs to poll, poll was disabled,
 739           * therefore make sure it's enabled when disabling HPD on
 740           * some connectors */
 741         if (hpd_disabled) {
 742                 drm_kms_helper_poll_enable(dev);
 743                 mod_timer(&dev_priv->hotplug_reenable_timer,
 744                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 745         }
 746
 747         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 748
 749         list_for_each_entry(connector, &mode_config->connector_list, head) {
 750                 intel_connector = to_intel_connector(connector);
 751                 intel_encoder = intel_connector->encoder;
 752                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 753                         if (intel_encoder->hot_plug)
 754                                 intel_encoder->hot_plug(intel_encoder);
 755                         if (intel_hpd_irq_event(dev, connector))
 756                                 changed = true;
 757                 }
 758         }
 759         mutex_unlock(&mode_config->mutex);
 760
 761         if (changed)
 762                 drm_kms_helper_hotplug_event(dev);
 763 }
 764
 765 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 766 {
 767         drm_i915_private_t *dev_priv = dev->dev_private;
 768         u32 busy_up, busy_down, max_avg, min_avg;
 769         u8 new_delay;
 770
 771         spin_lock(&mchdev_lock);
 772
 773         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 774
 775         new_delay = dev_priv->ips.cur_delay;
 776
 777         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 778         busy_up = I915_READ(RCPREVBSYTUPAVG);
 779         busy_down = I915_READ(RCPREVBSYTDNAVG);
 780         max_avg = I915_READ(RCBMAXAVG);
 781         min_avg = I915_READ(RCBMINAVG);
 782
 783         /* Handle RCS change request from hw */
 784         if (busy_up > max_avg) {
 785                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 786                         new_delay = dev_priv->ips.cur_delay - 1;
 787                 if (new_delay < dev_priv->ips.max_delay)
 788                         new_delay = dev_priv->ips.max_delay;
 789         } else if (busy_down < min_avg) {
 790                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 791                         new_delay = dev_priv->ips.cur_delay + 1;
 792                 if (new_delay > dev_priv->ips.min_delay)
 793                         new_delay = dev_priv->ips.min_delay;
 794         }
 795
 796         if (ironlake_set_drps(dev, new_delay))
 797                 dev_priv->ips.cur_delay = new_delay;
 798
 799         spin_unlock(&mchdev_lock);
 800
 801         return;
 802 }
 803
 804 static void notify_ring(struct drm_device *dev,
 805                         struct intel_ring_buffer *ring)
 806 {
 807         if (ring->obj == NULL)
 808                 return;
 809
 810         trace_i915_gem_request_complete(ring);
 811
 812         wake_up_all(&ring->irq_queue);
 813         i915_queue_hangcheck(dev);
 814 }
 815
 816 static void gen6_pm_rps_work(struct work_struct *work)
 817 {
 818         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 819                                                     rps.work);
 820         u32 pm_iir;
 821         int new_delay, adj;
 822
 823         spin_lock_irq(&dev_priv->irq_lock);
 824         pm_iir = dev_priv->rps.pm_iir;
 825         dev_priv->rps.pm_iir = 0;
 826         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 827         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 828         spin_unlock_irq(&dev_priv->irq_lock);
 829
 830         /* Make sure we didn't queue anything we're not going to process. */
 831         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 832
 833         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 834                 return;
 835
 836         mutex_lock(&dev_priv->rps.hw_lock);
 837
 838         adj = dev_priv->rps.last_adj;
 839         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 840                 if (adj > 0)
 841                         adj *= 2;
 842                 else
 843                         adj = 1;
 844                 new_delay = dev_priv->rps.cur_delay + adj;
 845
 846                 /*
 847                  * For better performance, jump directly
 848                  * to RPe if we're below it.
 849                  */
 850                 if (new_delay < dev_priv->rps.rpe_delay)
 851                         new_delay = dev_priv->rps.rpe_delay;
 852         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
 853                 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
 854                         new_delay = dev_priv->rps.rpe_delay;
 855                 else
 856                         new_delay = dev_priv->rps.min_delay;
 857                 adj = 0;
 858         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
 859                 if (adj < 0)
 860                         adj *= 2;
 861                 else
 862                         adj = -1;
 863                 new_delay = dev_priv->rps.cur_delay + adj;
 864         } else { /* unknown event */
 865                 new_delay = dev_priv->rps.cur_delay;
 866         }
 867
 868         /* sysfs frequency interfaces may have snuck in while servicing the
 869          * interrupt
 870          */
 871         if (new_delay < (int)dev_priv->rps.min_delay)
 872                 new_delay = dev_priv->rps.min_delay;
 873         if (new_delay > (int)dev_priv->rps.max_delay)
 874                 new_delay = dev_priv->rps.max_delay;
 875         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
 876
 877         if (IS_VALLEYVIEW(dev_priv->dev))
 878                 valleyview_set_rps(dev_priv->dev, new_delay);
 879         else
 880                 gen6_set_rps(dev_priv->dev, new_delay);
 881
 882         mutex_unlock(&dev_priv->rps.hw_lock);
 883 }
 884
 885
 886 /**
 887  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 888  * occurred.
 889  * @work: workqueue struct
 890  *
 891  * Doesn't actually do anything except notify userspace. As a consequence of
 892  * this event, userspace should try to remap the bad rows since statistically
 893  * it is likely the same row is more likely to go bad again.
 894  */
 895 static void ivybridge_parity_work(struct work_struct *work)
 896 {
 897         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 898                                                     l3_parity.error_work);
 899         u32 error_status, row, bank, subbank;
 900         char *parity_event[6];
 901         uint32_t misccpctl;
 902         unsigned long flags;
 903         uint8_t slice = 0;
 904
 905         /* We must turn off DOP level clock gating to access the L3 registers.
 906          * In order to prevent a get/put style interface, acquire struct mutex
 907          * any time we access those registers.
 908          */
 909         mutex_lock(&dev_priv->dev->struct_mutex);
 910
 911         /* If we've screwed up tracking, just let the interrupt fire again */
 912         if (WARN_ON(!dev_priv->l3_parity.which_slice))
 913                 goto out;
 914
 915         misccpctl = I915_READ(GEN7_MISCCPCTL);
 916         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 917         POSTING_READ(GEN7_MISCCPCTL);
 918
 919         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
 920                 u32 reg;
 921
 922                 slice--;
 923                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
 924                         break;
 925
 926                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
 927
 928                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
 929
 930                 error_status = I915_READ(reg);
 931                 row = GEN7_PARITY_ERROR_ROW(error_status);
 932                 bank = GEN7_PARITY_ERROR_BANK(error_status);
 933                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 934
 935                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
 936                 POSTING_READ(reg);
 937
 938                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
 939                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 940                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 941                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 942                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
 943                 parity_event[5] = NULL;
 944
 945                 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 946                                    KOBJ_CHANGE, parity_event);
 947
 948                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
 949                           slice, row, bank, subbank);
 950
 951                 kfree(parity_event[4]);
 952                 kfree(parity_event[3]);
 953                 kfree(parity_event[2]);
 954                 kfree(parity_event[1]);
 955         }
 956
 957         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 958
 959 out:
 960         WARN_ON(dev_priv->l3_parity.which_slice);
 961         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 962         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
 963         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 964
 965         mutex_unlock(&dev_priv->dev->struct_mutex);
 966 }
 967
 968 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
 969 {
 970         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 971
 972         if (!HAS_L3_DPF(dev))
 973                 return;
 974
 975         spin_lock(&dev_priv->irq_lock);
 976         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
 977         spin_unlock(&dev_priv->irq_lock);
 978
 979         iir &= GT_PARITY_ERROR(dev);
 980         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
 981                 dev_priv->l3_parity.which_slice |= 1 << 1;
 982
 983         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
 984                 dev_priv->l3_parity.which_slice |= 1 << 0;
 985
 986         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 987 }
 988
 989 static void ilk_gt_irq_handler(struct drm_device *dev,
 990                                struct drm_i915_private *dev_priv,
 991                                u32 gt_iir)
 992 {
 993         if (gt_iir &
 994             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 995                 notify_ring(dev, &dev_priv->ring[RCS]);
 996         if (gt_iir & ILK_BSD_USER_INTERRUPT)
 997                 notify_ring(dev, &dev_priv->ring[VCS]);
 998 }
 999
1000 static void snb_gt_irq_handler(struct drm_device *dev,
1001                                struct drm_i915_private *dev_priv,
1002                                u32 gt_iir)
1003 {
1004
1005         if (gt_iir &
1006             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1007                 notify_ring(dev, &dev_priv->ring[RCS]);
1008         if (gt_iir & GT_BSD_USER_INTERRUPT)
1009                 notify_ring(dev, &dev_priv->ring[VCS]);
1010         if (gt_iir & GT_BLT_USER_INTERRUPT)
1011                 notify_ring(dev, &dev_priv->ring[BCS]);
1012
1013         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1014                       GT_BSD_CS_ERROR_INTERRUPT |
1015                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1016                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
1017                 i915_handle_error(dev, false);
1018         }
1019
1020         if (gt_iir & GT_PARITY_ERROR(dev))
1021                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1022 }
1023
1024 #define HPD_STORM_DETECT_PERIOD 1000
1025 #define HPD_STORM_THRESHOLD 5
1026
1027 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1028                                          u32 hotplug_trigger,
1029                                          const u32 *hpd)
1030 {
1031         drm_i915_private_t *dev_priv = dev->dev_private;
1032         int i;
1033         bool storm_detected = false;
1034
1035         if (!hotplug_trigger)
1036                 return;
1037
1038         spin_lock(&dev_priv->irq_lock);
1039         for (i = 1; i < HPD_NUM_PINS; i++) {
1040
1041                 WARN(((hpd[i] & hotplug_trigger) &&
1042                       dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1043                      "Received HPD interrupt although disabled\n");
1044
1045                 if (!(hpd[i] & hotplug_trigger) ||
1046                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1047                         continue;
1048
1049                 dev_priv->hpd_event_bits |= (1 << i);
1050                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1051                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1052                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1053                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1054                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1055                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1056                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1057                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1058                         dev_priv->hpd_event_bits &= ~(1 << i);
1059                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1060                         storm_detected = true;
1061                 } else {
1062                         dev_priv->hpd_stats[i].hpd_cnt++;
1063                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1064                                       dev_priv->hpd_stats[i].hpd_cnt);
1065                 }
1066         }
1067
1068         if (storm_detected)
1069                 dev_priv->display.hpd_irq_setup(dev);
1070         spin_unlock(&dev_priv->irq_lock);
1071
1072         /*
1073          * Our hotplug handler can grab modeset locks (by calling down into the
1074          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1075          * queue for otherwise the flush_work in the pageflip code will
1076          * deadlock.
1077          */
1078         schedule_work(&dev_priv->hotplug_work);
1079 }
1080
1081 static void gmbus_irq_handler(struct drm_device *dev)
1082 {
1083         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1084
1085         wake_up_all(&dev_priv->gmbus_wait_queue);
1086 }
1087
1088 static void dp_aux_irq_handler(struct drm_device *dev)
1089 {
1090         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1091
1092         wake_up_all(&dev_priv->gmbus_wait_queue);
1093 }
1094
1095 /* The RPS events need forcewake, so we add them to a work queue and mask their
1096  * IMR bits until the work is done. Other interrupts can be processed without
1097  * the work queue. */
1098 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1099 {
1100         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1101                 spin_lock(&dev_priv->irq_lock);
1102                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1103                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1104                 spin_unlock(&dev_priv->irq_lock);
1105
1106                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1107         }
1108
1109         if (HAS_VEBOX(dev_priv->dev)) {
1110                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1111                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1112
1113                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1114                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1115                         i915_handle_error(dev_priv->dev, false);
1116                 }
1117         }
1118 }
1119
1120 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1121 {
1122         struct drm_device *dev = (struct drm_device *) arg;
1123         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1124         u32 iir, gt_iir, pm_iir;
1125         irqreturn_t ret = IRQ_NONE;
1126         unsigned long irqflags;
1127         int pipe;
1128         u32 pipe_stats[I915_MAX_PIPES];
1129
1130         atomic_inc(&dev_priv->irq_received);
1131
1132         while (true) {
1133                 iir = I915_READ(VLV_IIR);
1134                 gt_iir = I915_READ(GTIIR);
1135                 pm_iir = I915_READ(GEN6_PMIIR);
1136
1137                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1138                         goto out;
1139
1140                 ret = IRQ_HANDLED;
1141
1142                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1143
1144                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1145                 for_each_pipe(pipe) {
1146                         int reg = PIPESTAT(pipe);
1147                         pipe_stats[pipe] = I915_READ(reg);
1148
1149                         /*
1150                          * Clear the PIPE*STAT regs before the IIR
1151                          */
1152                         if (pipe_stats[pipe] & 0x8000ffff) {
1153                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1154                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1155                                                          pipe_name(pipe));
1156                                 I915_WRITE(reg, pipe_stats[pipe]);
1157                         }
1158                 }
1159                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1160
1161                 for_each_pipe(pipe) {
1162                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1163                                 drm_handle_vblank(dev, pipe);
1164
1165                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1166                                 intel_prepare_page_flip(dev, pipe);
1167                                 intel_finish_page_flip(dev, pipe);
1168                         }
1169                 }
1170
1171                 /* Consume port.  Then clear IIR or we'll miss events */
1172                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1173                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1174                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1175
1176                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1177                                          hotplug_status);
1178
1179                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1180
1181                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1182                         I915_READ(PORT_HOTPLUG_STAT);
1183                 }
1184
1185                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1186                         gmbus_irq_handler(dev);
1187
1188                 if (pm_iir)
1189                         gen6_rps_irq_handler(dev_priv, pm_iir);
1190
1191                 I915_WRITE(GTIIR, gt_iir);
1192                 I915_WRITE(GEN6_PMIIR, pm_iir);
1193                 I915_WRITE(VLV_IIR, iir);
1194         }
1195
1196 out:
1197         return ret;
1198 }
1199
1200 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1201 {
1202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1203         int pipe;
1204         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1205
1206         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1207
1208         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1209                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1210                                SDE_AUDIO_POWER_SHIFT);
1211                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1212                                  port_name(port));
1213         }
1214
1215         if (pch_iir & SDE_AUX_MASK)
1216                 dp_aux_irq_handler(dev);
1217
1218         if (pch_iir & SDE_GMBUS)
1219                 gmbus_irq_handler(dev);
1220
1221         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1222                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1223
1224         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1225                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1226
1227         if (pch_iir & SDE_POISON)
1228                 DRM_ERROR("PCH poison interrupt\n");
1229
1230         if (pch_iir & SDE_FDI_MASK)
1231                 for_each_pipe(pipe)
1232                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1233                                          pipe_name(pipe),
1234                                          I915_READ(FDI_RX_IIR(pipe)));
1235
1236         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1237                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1238
1239         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1240                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1241
1242         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1243                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1244                                                           false))
1245                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1246
1247         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1248                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1249                                                           false))
1250                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1251 }
1252
1253 static void ivb_err_int_handler(struct drm_device *dev)
1254 {
1255         struct drm_i915_private *dev_priv = dev->dev_private;
1256         u32 err_int = I915_READ(GEN7_ERR_INT);
1257
1258         if (err_int & ERR_INT_POISON)
1259                 DRM_ERROR("Poison interrupt\n");
1260
1261         if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1262                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1263                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1264
1265         if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1266                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1267                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1268
1269         if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1270                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1271                         DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1272
1273         I915_WRITE(GEN7_ERR_INT, err_int);
1274 }
1275
1276 static void cpt_serr_int_handler(struct drm_device *dev)
1277 {
1278         struct drm_i915_private *dev_priv = dev->dev_private;
1279         u32 serr_int = I915_READ(SERR_INT);
1280
1281         if (serr_int & SERR_INT_POISON)
1282                 DRM_ERROR("PCH poison interrupt\n");
1283
1284         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1285                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1286                                                           false))
1287                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1288
1289         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1290                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1291                                                           false))
1292                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1293
1294         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1295                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1296                                                           false))
1297                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1298
1299         I915_WRITE(SERR_INT, serr_int);
1300 }
1301
1302 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1303 {
1304         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1305         int pipe;
1306         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1307
1308         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1309
1310         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1311                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1312                                SDE_AUDIO_POWER_SHIFT_CPT);
1313                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1314                                  port_name(port));
1315         }
1316
1317         if (pch_iir & SDE_AUX_MASK_CPT)
1318                 dp_aux_irq_handler(dev);
1319
1320         if (pch_iir & SDE_GMBUS_CPT)
1321                 gmbus_irq_handler(dev);
1322
1323         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1324                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1325
1326         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1327                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1328
1329         if (pch_iir & SDE_FDI_MASK_CPT)
1330                 for_each_pipe(pipe)
1331                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1332                                          pipe_name(pipe),
1333                                          I915_READ(FDI_RX_IIR(pipe)));
1334
1335         if (pch_iir & SDE_ERROR_CPT)
1336                 cpt_serr_int_handler(dev);
1337 }
1338
1339 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1340 {
1341         struct drm_i915_private *dev_priv = dev->dev_private;
1342
1343         if (de_iir & DE_AUX_CHANNEL_A)
1344                 dp_aux_irq_handler(dev);
1345
1346         if (de_iir & DE_GSE)
1347                 intel_opregion_asle_intr(dev);
1348
1349         if (de_iir & DE_PIPEA_VBLANK)
1350                 drm_handle_vblank(dev, 0);
1351
1352         if (de_iir & DE_PIPEB_VBLANK)
1353                 drm_handle_vblank(dev, 1);
1354
1355         if (de_iir & DE_POISON)
1356                 DRM_ERROR("Poison interrupt\n");
1357
1358         if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1359                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1360                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1361
1362         if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1363                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1364                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1365
1366         if (de_iir & DE_PLANEA_FLIP_DONE) {
1367                 intel_prepare_page_flip(dev, 0);
1368                 intel_finish_page_flip_plane(dev, 0);
1369         }
1370
1371         if (de_iir & DE_PLANEB_FLIP_DONE) {
1372                 intel_prepare_page_flip(dev, 1);
1373                 intel_finish_page_flip_plane(dev, 1);
1374         }
1375
1376         /* check event from PCH */
1377         if (de_iir & DE_PCH_EVENT) {
1378                 u32 pch_iir = I915_READ(SDEIIR);
1379
1380                 if (HAS_PCH_CPT(dev))
1381                         cpt_irq_handler(dev, pch_iir);
1382                 else
1383                         ibx_irq_handler(dev, pch_iir);
1384
1385                 /* should clear PCH hotplug event before clear CPU irq */
1386                 I915_WRITE(SDEIIR, pch_iir);
1387         }
1388
1389         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1390                 ironlake_rps_change_irq_handler(dev);
1391 }
1392
1393 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1394 {
1395         struct drm_i915_private *dev_priv = dev->dev_private;
1396         int i;
1397
1398         if (de_iir & DE_ERR_INT_IVB)
1399                 ivb_err_int_handler(dev);
1400
1401         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1402                 dp_aux_irq_handler(dev);
1403
1404         if (de_iir & DE_GSE_IVB)
1405                 intel_opregion_asle_intr(dev);
1406
1407         for (i = 0; i < 3; i++) {
1408                 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1409                         drm_handle_vblank(dev, i);
1410                 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1411                         intel_prepare_page_flip(dev, i);
1412                         intel_finish_page_flip_plane(dev, i);
1413                 }
1414         }
1415
1416         /* check event from PCH */
1417         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1418                 u32 pch_iir = I915_READ(SDEIIR);
1419
1420                 cpt_irq_handler(dev, pch_iir);
1421
1422                 /* clear PCH hotplug event before clear CPU irq */
1423                 I915_WRITE(SDEIIR, pch_iir);
1424         }
1425 }
1426
1427 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1428 {
1429         struct drm_device *dev = (struct drm_device *) arg;
1430         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1431         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1432         irqreturn_t ret = IRQ_NONE;
1433
1434         atomic_inc(&dev_priv->irq_received);
1435
1436         /* We get interrupts on unclaimed registers, so check for this before we
1437          * do any I915_{READ,WRITE}. */
1438         intel_uncore_check_errors(dev);
1439
1440         /* disable master interrupt before clearing iir  */
1441         de_ier = I915_READ(DEIER);
1442         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1443         POSTING_READ(DEIER);
1444
1445         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1446          * interrupts will will be stored on its back queue, and then we'll be
1447          * able to process them after we restore SDEIER (as soon as we restore
1448          * it, we'll get an interrupt if SDEIIR still has something to process
1449          * due to its back queue). */
1450         if (!HAS_PCH_NOP(dev)) {
1451                 sde_ier = I915_READ(SDEIER);
1452                 I915_WRITE(SDEIER, 0);
1453                 POSTING_READ(SDEIER);
1454         }
1455
1456         gt_iir = I915_READ(GTIIR);
1457         if (gt_iir) {
1458                 if (INTEL_INFO(dev)->gen >= 6)
1459                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1460                 else
1461                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1462                 I915_WRITE(GTIIR, gt_iir);
1463                 ret = IRQ_HANDLED;
1464         }
1465
1466         de_iir = I915_READ(DEIIR);
1467         if (de_iir) {
1468                 if (INTEL_INFO(dev)->gen >= 7)
1469                         ivb_display_irq_handler(dev, de_iir);
1470                 else
1471                         ilk_display_irq_handler(dev, de_iir);
1472                 I915_WRITE(DEIIR, de_iir);
1473                 ret = IRQ_HANDLED;
1474         }
1475
1476         if (INTEL_INFO(dev)->gen >= 6) {
1477                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1478                 if (pm_iir) {
1479                         gen6_rps_irq_handler(dev_priv, pm_iir);
1480                         I915_WRITE(GEN6_PMIIR, pm_iir);
1481                         ret = IRQ_HANDLED;
1482                 }
1483         }
1484
1485         I915_WRITE(DEIER, de_ier);
1486         POSTING_READ(DEIER);
1487         if (!HAS_PCH_NOP(dev)) {
1488                 I915_WRITE(SDEIER, sde_ier);
1489                 POSTING_READ(SDEIER);
1490         }
1491
1492         return ret;
1493 }
1494
1495 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1496                                bool reset_completed)
1497 {
1498         struct intel_ring_buffer *ring;
1499         int i;
1500
1501         /*
1502          * Notify all waiters for GPU completion events that reset state has
1503          * been changed, and that they need to restart their wait after
1504          * checking for potential errors (and bail out to drop locks if there is
1505          * a gpu reset pending so that i915_error_work_func can acquire them).
1506          */
1507
1508         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1509         for_each_ring(ring, dev_priv, i)
1510                 wake_up_all(&ring->irq_queue);
1511
1512         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1513         wake_up_all(&dev_priv->pending_flip_queue);
1514
1515         /*
1516          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1517          * reset state is cleared.
1518          */
1519         if (reset_completed)
1520                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1521 }
1522
1523 /**
1524  * i915_error_work_func - do process context error handling work
1525  * @work: work struct
1526  *
1527  * Fire an error uevent so userspace can see that a hang or error
1528  * was detected.
1529  */
1530 static void i915_error_work_func(struct work_struct *work)
1531 {
1532         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1533                                                     work);
1534         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1535                                                     gpu_error);
1536         struct drm_device *dev = dev_priv->dev;
1537         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1538         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1539         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1540         int ret;
1541
1542         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1543
1544         /*
1545          * Note that there's only one work item which does gpu resets, so we
1546          * need not worry about concurrent gpu resets potentially incrementing
1547          * error->reset_counter twice. We only need to take care of another
1548          * racing irq/hangcheck declaring the gpu dead for a second time. A
1549          * quick check for that is good enough: schedule_work ensures the
1550          * correct ordering between hang detection and this work item, and since
1551          * the reset in-progress bit is only ever set by code outside of this
1552          * work we don't need to worry about any other races.
1553          */
1554         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1555                 DRM_DEBUG_DRIVER("resetting chip\n");
1556                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1557                                    reset_event);
1558
1559                 /*
1560                  * All state reset _must_ be completed before we update the
1561                  * reset counter, for otherwise waiters might miss the reset
1562                  * pending state and not properly drop locks, resulting in
1563                  * deadlocks with the reset work.
1564                  */
1565                 ret = i915_reset(dev);
1566
1567                 intel_display_handle_reset(dev);
1568
1569                 if (ret == 0) {
1570                         /*
1571                          * After all the gem state is reset, increment the reset
1572                          * counter and wake up everyone waiting for the reset to
1573                          * complete.
1574                          *
1575                          * Since unlock operations are a one-sided barrier only,
1576                          * we need to insert a barrier here to order any seqno
1577                          * updates before
1578                          * the counter increment.
1579                          */
1580                         smp_mb__before_atomic_inc();
1581                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1582
1583                         kobject_uevent_env(&dev->primary->kdev.kobj,
1584                                            KOBJ_CHANGE, reset_done_event);
1585                 } else {
1586                         atomic_set(&error->reset_counter, I915_WEDGED);
1587                 }
1588
1589                 /*
1590                  * Note: The wake_up also serves as a memory barrier so that
1591                  * waiters see the update value of the reset counter atomic_t.
1592                  */
1593                 i915_error_wake_up(dev_priv, true);
1594         }
1595 }
1596
1597 static void i915_report_and_clear_eir(struct drm_device *dev)
1598 {
1599         struct drm_i915_private *dev_priv = dev->dev_private;
1600         uint32_t instdone[I915_NUM_INSTDONE_REG];
1601         u32 eir = I915_READ(EIR);
1602         int pipe, i;
1603
1604         if (!eir)
1605                 return;
1606
1607         pr_err("render error detected, EIR: 0x%08x\n", eir);
1608
1609         i915_get_extra_instdone(dev, instdone);
1610
1611         if (IS_G4X(dev)) {
1612                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1613                         u32 ipeir = I915_READ(IPEIR_I965);
1614
1615                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1616                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1617                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1618                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1619                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1620                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1621                         I915_WRITE(IPEIR_I965, ipeir);
1622                         POSTING_READ(IPEIR_I965);
1623                 }
1624                 if (eir & GM45_ERROR_PAGE_TABLE) {
1625                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1626                         pr_err("page table error\n");
1627                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1628                         I915_WRITE(PGTBL_ER, pgtbl_err);
1629                         POSTING_READ(PGTBL_ER);
1630                 }
1631         }
1632
1633         if (!IS_GEN2(dev)) {
1634                 if (eir & I915_ERROR_PAGE_TABLE) {
1635                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1636                         pr_err("page table error\n");
1637                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1638                         I915_WRITE(PGTBL_ER, pgtbl_err);
1639                         POSTING_READ(PGTBL_ER);
1640                 }
1641         }
1642
1643         if (eir & I915_ERROR_MEMORY_REFRESH) {
1644                 pr_err("memory refresh error:\n");
1645                 for_each_pipe(pipe)
1646                         pr_err("pipe %c stat: 0x%08x\n",
1647                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1648                 /* pipestat has already been acked */
1649         }
1650         if (eir & I915_ERROR_INSTRUCTION) {
1651                 pr_err("instruction error\n");
1652                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1653                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1654                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1655                 if (INTEL_INFO(dev)->gen < 4) {
1656                         u32 ipeir = I915_READ(IPEIR);
1657
1658                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1659                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1660                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1661                         I915_WRITE(IPEIR, ipeir);
1662                         POSTING_READ(IPEIR);
1663                 } else {
1664                         u32 ipeir = I915_READ(IPEIR_I965);
1665
1666                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1667                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1668                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1669                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1670                         I915_WRITE(IPEIR_I965, ipeir);
1671                         POSTING_READ(IPEIR_I965);
1672                 }
1673         }
1674
1675         I915_WRITE(EIR, eir);
1676         POSTING_READ(EIR);
1677         eir = I915_READ(EIR);
1678         if (eir) {
1679                 /*
1680                  * some errors might have become stuck,
1681                  * mask them.
1682                  */
1683                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1684                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1685                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1686         }
1687 }
1688
1689 /**
1690  * i915_handle_error - handle an error interrupt
1691  * @dev: drm device
1692  *
1693  * Do some basic checking of regsiter state at error interrupt time and
1694  * dump it to the syslog.  Also call i915_capture_error_state() to make
1695  * sure we get a record and make it available in debugfs.  Fire a uevent
1696  * so userspace knows something bad happened (should trigger collection
1697  * of a ring dump etc.).
1698  */
1699 void i915_handle_error(struct drm_device *dev, bool wedged)
1700 {
1701         struct drm_i915_private *dev_priv = dev->dev_private;
1702
1703         i915_capture_error_state(dev);
1704         i915_report_and_clear_eir(dev);
1705
1706         if (wedged) {
1707                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1708                                 &dev_priv->gpu_error.reset_counter);
1709
1710                 /*
1711                  * Wakeup waiting processes so that the reset work function
1712                  * i915_error_work_func doesn't deadlock trying to grab various
1713                  * locks. By bumping the reset counter first, the woken
1714                  * processes will see a reset in progress and back off,
1715                  * releasing their locks and then wait for the reset completion.
1716                  * We must do this for _all_ gpu waiters that might hold locks
1717                  * that the reset work needs to acquire.
1718                  *
1719                  * Note: The wake_up serves as the required memory barrier to
1720                  * ensure that the waiters see the updated value of the reset
1721                  * counter atomic_t.
1722                  */
1723                 i915_error_wake_up(dev_priv, false);
1724         }
1725
1726         /*
1727          * Our reset work can grab modeset locks (since it needs to reset the
1728          * state of outstanding pagelips). Hence it must not be run on our own
1729          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1730          * code will deadlock.
1731          */
1732         schedule_work(&dev_priv->gpu_error.work);
1733 }
1734
1735 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1736 {
1737         drm_i915_private_t *dev_priv = dev->dev_private;
1738         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1740         struct drm_i915_gem_object *obj;
1741         struct intel_unpin_work *work;
1742         unsigned long flags;
1743         bool stall_detected;
1744
1745         /* Ignore early vblank irqs */
1746         if (intel_crtc == NULL)
1747                 return;
1748
1749         spin_lock_irqsave(&dev->event_lock, flags);
1750         work = intel_crtc->unpin_work;
1751
1752         if (work == NULL ||
1753             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1754             !work->enable_stall_check) {
1755                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1756                 spin_unlock_irqrestore(&dev->event_lock, flags);
1757                 return;
1758         }
1759
1760         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1761         obj = work->pending_flip_obj;
1762         if (INTEL_INFO(dev)->gen >= 4) {
1763                 int dspsurf = DSPSURF(intel_crtc->plane);
1764                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1765                                         i915_gem_obj_ggtt_offset(obj);
1766         } else {
1767                 int dspaddr = DSPADDR(intel_crtc->plane);
1768                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1769                                                         crtc->y * crtc->fb->pitches[0] +
1770                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1771         }
1772
1773         spin_unlock_irqrestore(&dev->event_lock, flags);
1774
1775         if (stall_detected) {
1776                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1777                 intel_prepare_page_flip(dev, intel_crtc->plane);
1778         }
1779 }
1780
1781 /* Called from drm generic code, passed 'crtc' which
1782  * we use as a pipe index
1783  */
1784 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1785 {
1786         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1787         unsigned long irqflags;
1788
1789         if (!i915_pipe_enabled(dev, pipe))
1790                 return -EINVAL;
1791
1792         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1793         if (INTEL_INFO(dev)->gen >= 4)
1794                 i915_enable_pipestat(dev_priv, pipe,
1795                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1796         else
1797                 i915_enable_pipestat(dev_priv, pipe,
1798                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1799
1800         /* maintain vblank delivery even in deep C-states */
1801         if (dev_priv->info->gen == 3)
1802                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1803         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1804
1805         return 0;
1806 }
1807
1808 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1809 {
1810         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1811         unsigned long irqflags;
1812         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1813                                                      DE_PIPE_VBLANK_ILK(pipe);
1814
1815         if (!i915_pipe_enabled(dev, pipe))
1816                 return -EINVAL;
1817
1818         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1819         ironlake_enable_display_irq(dev_priv, bit);
1820         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1821
1822         return 0;
1823 }
1824
1825 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1826 {
1827         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1828         unsigned long irqflags;
1829         u32 imr;
1830
1831         if (!i915_pipe_enabled(dev, pipe))
1832                 return -EINVAL;
1833
1834         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1835         imr = I915_READ(VLV_IMR);
1836         if (pipe == 0)
1837                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1838         else
1839                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1840         I915_WRITE(VLV_IMR, imr);
1841         i915_enable_pipestat(dev_priv, pipe,
1842                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1843         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1844
1845         return 0;
1846 }
1847
1848 /* Called from drm generic code, passed 'crtc' which
1849  * we use as a pipe index
1850  */
1851 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1852 {
1853         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1854         unsigned long irqflags;
1855
1856         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1857         if (dev_priv->info->gen == 3)
1858                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1859
1860         i915_disable_pipestat(dev_priv, pipe,
1861                               PIPE_VBLANK_INTERRUPT_ENABLE |
1862                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1863         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1864 }
1865
1866 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1867 {
1868         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1869         unsigned long irqflags;
1870         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1871                                                      DE_PIPE_VBLANK_ILK(pipe);
1872
1873         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1874         ironlake_disable_display_irq(dev_priv, bit);
1875         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1876 }
1877
1878 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1879 {
1880         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1881         unsigned long irqflags;
1882         u32 imr;
1883
1884         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1885         i915_disable_pipestat(dev_priv, pipe,
1886                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1887         imr = I915_READ(VLV_IMR);
1888         if (pipe == 0)
1889                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1890         else
1891                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1892         I915_WRITE(VLV_IMR, imr);
1893         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1894 }
1895
1896 static u32
1897 ring_last_seqno(struct intel_ring_buffer *ring)
1898 {
1899         return list_entry(ring->request_list.prev,
1900                           struct drm_i915_gem_request, list)->seqno;
1901 }
1902
1903 static bool
1904 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1905 {
1906         return (list_empty(&ring->request_list) ||
1907                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
1908 }
1909
1910 static struct intel_ring_buffer *
1911 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
1912 {
1913         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1914         u32 cmd, ipehr, acthd, acthd_min;
1915
1916         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1917         if ((ipehr & ~(0x3 << 16)) !=
1918             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1919                 return NULL;
1920
1921         /* ACTHD is likely pointing to the dword after the actual command,
1922          * so scan backwards until we find the MBOX.
1923          */
1924         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1925         acthd_min = max((int)acthd - 3 * 4, 0);
1926         do {
1927                 cmd = ioread32(ring->virtual_start + acthd);
1928                 if (cmd == ipehr)
1929                         break;
1930
1931                 acthd -= 4;
1932                 if (acthd < acthd_min)
1933                         return NULL;
1934         } while (1);
1935
1936         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1937         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1938 }
1939
1940 static int semaphore_passed(struct intel_ring_buffer *ring)
1941 {
1942         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1943         struct intel_ring_buffer *signaller;
1944         u32 seqno, ctl;
1945
1946         ring->hangcheck.deadlock = true;
1947
1948         signaller = semaphore_waits_for(ring, &seqno);
1949         if (signaller == NULL || signaller->hangcheck.deadlock)
1950                 return -1;
1951
1952         /* cursory check for an unkickable deadlock */
1953         ctl = I915_READ_CTL(signaller);
1954         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1955                 return -1;
1956
1957         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1958 }
1959
1960 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1961 {
1962         struct intel_ring_buffer *ring;
1963         int i;
1964
1965         for_each_ring(ring, dev_priv, i)
1966                 ring->hangcheck.deadlock = false;
1967 }
1968
1969 static enum intel_ring_hangcheck_action
1970 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1971 {
1972         struct drm_device *dev = ring->dev;
1973         struct drm_i915_private *dev_priv = dev->dev_private;
1974         u32 tmp;
1975
1976         if (ring->hangcheck.acthd != acthd)
1977                 return HANGCHECK_ACTIVE;
1978
1979         if (IS_GEN2(dev))
1980                 return HANGCHECK_HUNG;
1981
1982         /* Is the chip hanging on a WAIT_FOR_EVENT?
1983          * If so we can simply poke the RB_WAIT bit
1984          * and break the hang. This should work on
1985          * all but the second generation chipsets.
1986          */
1987         tmp = I915_READ_CTL(ring);
1988         if (tmp & RING_WAIT) {
1989                 DRM_ERROR("Kicking stuck wait on %s\n",
1990                           ring->name);
1991                 I915_WRITE_CTL(ring, tmp);
1992                 return HANGCHECK_KICK;
1993         }
1994
1995         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1996                 switch (semaphore_passed(ring)) {
1997                 default:
1998                         return HANGCHECK_HUNG;
1999                 case 1:
2000                         DRM_ERROR("Kicking stuck semaphore on %s\n",
2001                                   ring->name);
2002                         I915_WRITE_CTL(ring, tmp);
2003                         return HANGCHECK_KICK;
2004                 case 0:
2005                         return HANGCHECK_WAIT;
2006                 }
2007         }
2008
2009         return HANGCHECK_HUNG;
2010 }
2011
2012 /**
2013  * This is called when the chip hasn't reported back with completed
2014  * batchbuffers in a long time. We keep track per ring seqno progress and
2015  * if there are no progress, hangcheck score for that ring is increased.
2016  * Further, acthd is inspected to see if the ring is stuck. On stuck case
2017  * we kick the ring. If we see no progress on three subsequent calls
2018  * we assume chip is wedged and try to fix it by resetting the chip.
2019  */
2020 static void i915_hangcheck_elapsed(unsigned long data)
2021 {
2022         struct drm_device *dev = (struct drm_device *)data;
2023         drm_i915_private_t *dev_priv = dev->dev_private;
2024         struct intel_ring_buffer *ring;
2025         int i;
2026         int busy_count = 0, rings_hung = 0;
2027         bool stuck[I915_NUM_RINGS] = { 0 };
2028 #define BUSY 1
2029 #define KICK 5
2030 #define HUNG 20
2031 #define FIRE 30
2032
2033         if (!i915_enable_hangcheck)
2034                 return;
2035
2036         for_each_ring(ring, dev_priv, i) {
2037                 u32 seqno, acthd;
2038                 bool busy = true;
2039
2040                 semaphore_clear_deadlocks(dev_priv);
2041
2042                 seqno = ring->get_seqno(ring, false);
2043                 acthd = intel_ring_get_active_head(ring);
2044
2045                 if (ring->hangcheck.seqno == seqno) {
2046                         if (ring_idle(ring, seqno)) {
2047                                 ring->hangcheck.action = HANGCHECK_IDLE;
2048
2049                                 if (waitqueue_active(&ring->irq_queue)) {
2050                                         /* Issue a wake-up to catch stuck h/w. */
2051                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2052                                                 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2053                                                           ring->name);
2054                                                 wake_up_all(&ring->irq_queue);
2055                                         }
2056                                         /* Safeguard against driver failure */
2057                                         ring->hangcheck.score += BUSY;
2058                                 } else
2059                                         busy = false;
2060                         } else {
2061                                 /* We always increment the hangcheck score
2062                                  * if the ring is busy and still processing
2063                                  * the same request, so that no single request
2064                                  * can run indefinitely (such as a chain of
2065                                  * batches). The only time we do not increment
2066                                  * the hangcheck score on this ring, if this
2067                                  * ring is in a legitimate wait for another
2068                                  * ring. In that case the waiting ring is a
2069                                  * victim and we want to be sure we catch the
2070                                  * right culprit. Then every time we do kick
2071                                  * the ring, add a small increment to the
2072                                  * score so that we can catch a batch that is
2073                                  * being repeatedly kicked and so responsible
2074                                  * for stalling the machine.
2075                                  */
2076                                 ring->hangcheck.action = ring_stuck(ring,
2077                                                                     acthd);
2078
2079                                 switch (ring->hangcheck.action) {
2080                                 case HANGCHECK_IDLE:
2081                                 case HANGCHECK_WAIT:
2082                                         break;
2083                                 case HANGCHECK_ACTIVE:
2084                                         ring->hangcheck.score += BUSY;
2085                                         break;
2086                                 case HANGCHECK_KICK:
2087                                         ring->hangcheck.score += KICK;
2088                                         break;
2089                                 case HANGCHECK_HUNG:
2090                                         ring->hangcheck.score += HUNG;
2091                                         stuck[i] = true;
2092                                         break;
2093                                 }
2094                         }
2095                 } else {
2096                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2097
2098                         /* Gradually reduce the count so that we catch DoS
2099                          * attempts across multiple batches.
2100                          */
2101                         if (ring->hangcheck.score > 0)
2102                                 ring->hangcheck.score--;
2103                 }
2104
2105                 ring->hangcheck.seqno = seqno;
2106                 ring->hangcheck.acthd = acthd;
2107                 busy_count += busy;
2108         }
2109
2110         for_each_ring(ring, dev_priv, i) {
2111                 if (ring->hangcheck.score > FIRE) {
2112                         DRM_INFO("%s on %s\n",
2113                                  stuck[i] ? "stuck" : "no progress",
2114                                  ring->name);
2115                         rings_hung++;
2116                 }
2117         }
2118
2119         if (rings_hung)
2120                 return i915_handle_error(dev, true);
2121
2122         if (busy_count)
2123                 /* Reset timer case chip hangs without another request
2124                  * being added */
2125                 i915_queue_hangcheck(dev);
2126 }
2127
2128 void i915_queue_hangcheck(struct drm_device *dev)
2129 {
2130         struct drm_i915_private *dev_priv = dev->dev_private;
2131         if (!i915_enable_hangcheck)
2132                 return;
2133
2134         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2135                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2136 }
2137
2138 static void ibx_irq_preinstall(struct drm_device *dev)
2139 {
2140         struct drm_i915_private *dev_priv = dev->dev_private;
2141
2142         if (HAS_PCH_NOP(dev))
2143                 return;
2144
2145         /* south display irq */
2146         I915_WRITE(SDEIMR, 0xffffffff);
2147         /*
2148          * SDEIER is also touched by the interrupt handler to work around missed
2149          * PCH interrupts. Hence we can't update it after the interrupt handler
2150          * is enabled - instead we unconditionally enable all PCH interrupt
2151          * sources here, but then only unmask them as needed with SDEIMR.
2152          */
2153         I915_WRITE(SDEIER, 0xffffffff);
2154         POSTING_READ(SDEIER);
2155 }
2156
2157 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2158 {
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160
2161         /* and GT */
2162         I915_WRITE(GTIMR, 0xffffffff);
2163         I915_WRITE(GTIER, 0x0);
2164         POSTING_READ(GTIER);
2165
2166         if (INTEL_INFO(dev)->gen >= 6) {
2167                 /* and PM */
2168                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2169                 I915_WRITE(GEN6_PMIER, 0x0);
2170                 POSTING_READ(GEN6_PMIER);
2171         }
2172 }
2173
2174 /* drm_dma.h hooks
2175 */
2176 static void ironlake_irq_preinstall(struct drm_device *dev)
2177 {
2178         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2179
2180         atomic_set(&dev_priv->irq_received, 0);
2181
2182         I915_WRITE(HWSTAM, 0xeffe);
2183
2184         I915_WRITE(DEIMR, 0xffffffff);
2185         I915_WRITE(DEIER, 0x0);
2186         POSTING_READ(DEIER);
2187
2188         gen5_gt_irq_preinstall(dev);
2189
2190         ibx_irq_preinstall(dev);
2191 }
2192
2193 static void valleyview_irq_preinstall(struct drm_device *dev)
2194 {
2195         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2196         int pipe;
2197
2198         atomic_set(&dev_priv->irq_received, 0);
2199
2200         /* VLV magic */
2201         I915_WRITE(VLV_IMR, 0);
2202         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2203         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2204         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2205
2206         /* and GT */
2207         I915_WRITE(GTIIR, I915_READ(GTIIR));
2208         I915_WRITE(GTIIR, I915_READ(GTIIR));
2209
2210         gen5_gt_irq_preinstall(dev);
2211
2212         I915_WRITE(DPINVGTT, 0xff);
2213
2214         I915_WRITE(PORT_HOTPLUG_EN, 0);
2215         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2216         for_each_pipe(pipe)
2217                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2218         I915_WRITE(VLV_IIR, 0xffffffff);
2219         I915_WRITE(VLV_IMR, 0xffffffff);
2220         I915_WRITE(VLV_IER, 0x0);
2221         POSTING_READ(VLV_IER);
2222 }
2223
2224 static void ibx_hpd_irq_setup(struct drm_device *dev)
2225 {
2226         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2227         struct drm_mode_config *mode_config = &dev->mode_config;
2228         struct intel_encoder *intel_encoder;
2229         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2230
2231         if (HAS_PCH_IBX(dev)) {
2232                 hotplug_irqs = SDE_HOTPLUG_MASK;
2233                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2234                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2235                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2236         } else {
2237                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2238                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2239                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2240                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2241         }
2242
2243         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2244
2245         /*
2246          * Enable digital hotplug on the PCH, and configure the DP short pulse
2247          * duration to 2ms (which is the minimum in the Display Port spec)
2248          *
2249          * This register is the same on all known PCH chips.
2250          */
2251         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2252         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2253         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2254         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2255         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2256         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2257 }
2258
2259 static void ibx_irq_postinstall(struct drm_device *dev)
2260 {
2261         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2262         u32 mask;
2263
2264         if (HAS_PCH_NOP(dev))
2265                 return;
2266
2267         if (HAS_PCH_IBX(dev)) {
2268                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2269                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2270         } else {
2271                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2272
2273                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2274         }
2275
2276         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2277         I915_WRITE(SDEIMR, ~mask);
2278 }
2279
2280 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2281 {
2282         struct drm_i915_private *dev_priv = dev->dev_private;
2283         u32 pm_irqs, gt_irqs;
2284
2285         pm_irqs = gt_irqs = 0;
2286
2287         dev_priv->gt_irq_mask = ~0;
2288         if (HAS_L3_DPF(dev)) {
2289                 /* L3 parity interrupt is always unmasked. */
2290                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2291                 gt_irqs |= GT_PARITY_ERROR(dev);
2292         }
2293
2294         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2295         if (IS_GEN5(dev)) {
2296                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2297                            ILK_BSD_USER_INTERRUPT;
2298         } else {
2299                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2300         }
2301
2302         I915_WRITE(GTIIR, I915_READ(GTIIR));
2303         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2304         I915_WRITE(GTIER, gt_irqs);
2305         POSTING_READ(GTIER);
2306
2307         if (INTEL_INFO(dev)->gen >= 6) {
2308                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2309
2310                 if (HAS_VEBOX(dev))
2311                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2312
2313                 dev_priv->pm_irq_mask = 0xffffffff;
2314                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2315                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2316                 I915_WRITE(GEN6_PMIER, pm_irqs);
2317                 POSTING_READ(GEN6_PMIER);
2318         }
2319 }
2320
2321 static int ironlake_irq_postinstall(struct drm_device *dev)
2322 {
2323         unsigned long irqflags;
2324         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2325         u32 display_mask, extra_mask;
2326
2327         if (INTEL_INFO(dev)->gen >= 7) {
2328                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2329                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2330                                 DE_PLANEB_FLIP_DONE_IVB |
2331                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2332                                 DE_ERR_INT_IVB);
2333                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2334                               DE_PIPEA_VBLANK_IVB);
2335
2336                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2337         } else {
2338                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2339                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2340                                 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2341                                 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2342                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2343         }
2344
2345         dev_priv->irq_mask = ~display_mask;
2346
2347         /* should always can generate irq */
2348         I915_WRITE(DEIIR, I915_READ(DEIIR));
2349         I915_WRITE(DEIMR, dev_priv->irq_mask);
2350         I915_WRITE(DEIER, display_mask | extra_mask);
2351         POSTING_READ(DEIER);
2352
2353         gen5_gt_irq_postinstall(dev);
2354
2355         ibx_irq_postinstall(dev);
2356
2357         if (IS_IRONLAKE_M(dev)) {
2358                 /* Enable PCU event interrupts
2359                  *
2360                  * spinlocking not required here for correctness since interrupt
2361                  * setup is guaranteed to run in single-threaded context. But we
2362                  * need it to make the assert_spin_locked happy. */
2363                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2364                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2365                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2366         }
2367
2368         return 0;
2369 }
2370
2371 static int valleyview_irq_postinstall(struct drm_device *dev)
2372 {
2373         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2374         u32 enable_mask;
2375         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2376         unsigned long irqflags;
2377
2378         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2379         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2380                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2381                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2382                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2383
2384         /*
2385          *Leave vblank interrupts masked initially.  enable/disable will
2386          * toggle them based on usage.
2387          */
2388         dev_priv->irq_mask = (~enable_mask) |
2389                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2390                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2391
2392         I915_WRITE(PORT_HOTPLUG_EN, 0);
2393         POSTING_READ(PORT_HOTPLUG_EN);
2394
2395         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2396         I915_WRITE(VLV_IER, enable_mask);
2397         I915_WRITE(VLV_IIR, 0xffffffff);
2398         I915_WRITE(PIPESTAT(0), 0xffff);
2399         I915_WRITE(PIPESTAT(1), 0xffff);
2400         POSTING_READ(VLV_IER);
2401
2402         /* Interrupt setup is already guaranteed to be single-threaded, this is
2403          * just to make the assert_spin_locked check happy. */
2404         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2405         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2406         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2407         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2408         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2409
2410         I915_WRITE(VLV_IIR, 0xffffffff);
2411         I915_WRITE(VLV_IIR, 0xffffffff);
2412
2413         gen5_gt_irq_postinstall(dev);
2414
2415         /* ack & enable invalid PTE error interrupts */
2416 #if 0 /* FIXME: add support to irq handler for checking these bits */
2417         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2418         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2419 #endif
2420
2421         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2422
2423         return 0;
2424 }
2425
2426 static void valleyview_irq_uninstall(struct drm_device *dev)
2427 {
2428         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2429         int pipe;
2430
2431         if (!dev_priv)
2432                 return;
2433
2434         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2435
2436         for_each_pipe(pipe)
2437                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2438
2439         I915_WRITE(HWSTAM, 0xffffffff);
2440         I915_WRITE(PORT_HOTPLUG_EN, 0);
2441         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2442         for_each_pipe(pipe)
2443                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2444         I915_WRITE(VLV_IIR, 0xffffffff);
2445         I915_WRITE(VLV_IMR, 0xffffffff);
2446         I915_WRITE(VLV_IER, 0x0);
2447         POSTING_READ(VLV_IER);
2448 }
2449
2450 static void ironlake_irq_uninstall(struct drm_device *dev)
2451 {
2452         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2453
2454         if (!dev_priv)
2455                 return;
2456
2457         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2458
2459         I915_WRITE(HWSTAM, 0xffffffff);
2460
2461         I915_WRITE(DEIMR, 0xffffffff);
2462         I915_WRITE(DEIER, 0x0);
2463         I915_WRITE(DEIIR, I915_READ(DEIIR));
2464         if (IS_GEN7(dev))
2465                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2466
2467         I915_WRITE(GTIMR, 0xffffffff);
2468         I915_WRITE(GTIER, 0x0);
2469         I915_WRITE(GTIIR, I915_READ(GTIIR));
2470
2471         if (HAS_PCH_NOP(dev))
2472                 return;
2473
2474         I915_WRITE(SDEIMR, 0xffffffff);
2475         I915_WRITE(SDEIER, 0x0);
2476         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2477         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2478                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2479 }
2480
2481 static void i8xx_irq_preinstall(struct drm_device * dev)
2482 {
2483         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2484         int pipe;
2485
2486         atomic_set(&dev_priv->irq_received, 0);
2487
2488         for_each_pipe(pipe)
2489                 I915_WRITE(PIPESTAT(pipe), 0);
2490         I915_WRITE16(IMR, 0xffff);
2491         I915_WRITE16(IER, 0x0);
2492         POSTING_READ16(IER);
2493 }
2494
2495 static int i8xx_irq_postinstall(struct drm_device *dev)
2496 {
2497         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2498
2499         I915_WRITE16(EMR,
2500                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2501
2502         /* Unmask the interrupts that we always want on. */
2503         dev_priv->irq_mask =
2504                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2505                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2506                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2507                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2508                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2509         I915_WRITE16(IMR, dev_priv->irq_mask);
2510
2511         I915_WRITE16(IER,
2512                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2513                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2514                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2515                      I915_USER_INTERRUPT);
2516         POSTING_READ16(IER);
2517
2518         return 0;
2519 }
2520
2521 /*
2522  * Returns true when a page flip has completed.
2523  */
2524 static bool i8xx_handle_vblank(struct drm_device *dev,
2525                                int pipe, u16 iir)
2526 {
2527         drm_i915_private_t *dev_priv = dev->dev_private;
2528         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2529
2530         if (!drm_handle_vblank(dev, pipe))
2531                 return false;
2532
2533         if ((iir & flip_pending) == 0)
2534                 return false;
2535
2536         intel_prepare_page_flip(dev, pipe);
2537
2538         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2539          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2540          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2541          * the flip is completed (no longer pending). Since this doesn't raise
2542          * an interrupt per se, we watch for the change at vblank.
2543          */
2544         if (I915_READ16(ISR) & flip_pending)
2545                 return false;
2546
2547         intel_finish_page_flip(dev, pipe);
2548
2549         return true;
2550 }
2551
2552 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2553 {
2554         struct drm_device *dev = (struct drm_device *) arg;
2555         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2556         u16 iir, new_iir;
2557         u32 pipe_stats[2];
2558         unsigned long irqflags;
2559         int pipe;
2560         u16 flip_mask =
2561                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2562                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2563
2564         atomic_inc(&dev_priv->irq_received);
2565
2566         iir = I915_READ16(IIR);
2567         if (iir == 0)
2568                 return IRQ_NONE;
2569
2570         while (iir & ~flip_mask) {
2571                 /* Can't rely on pipestat interrupt bit in iir as it might
2572                  * have been cleared after the pipestat interrupt was received.
2573                  * It doesn't set the bit in iir again, but it still produces
2574                  * interrupts (for non-MSI).
2575                  */
2576                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2577                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2578                         i915_handle_error(dev, false);
2579
2580                 for_each_pipe(pipe) {
2581                         int reg = PIPESTAT(pipe);
2582                         pipe_stats[pipe] = I915_READ(reg);
2583
2584                         /*
2585                          * Clear the PIPE*STAT regs before the IIR
2586                          */
2587                         if (pipe_stats[pipe] & 0x8000ffff) {
2588                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2589                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2590                                                          pipe_name(pipe));
2591                                 I915_WRITE(reg, pipe_stats[pipe]);
2592                         }
2593                 }
2594                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2595
2596                 I915_WRITE16(IIR, iir & ~flip_mask);
2597                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2598
2599                 i915_update_dri1_breadcrumb(dev);
2600
2601                 if (iir & I915_USER_INTERRUPT)
2602                         notify_ring(dev, &dev_priv->ring[RCS]);
2603
2604                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2605                     i8xx_handle_vblank(dev, 0, iir))
2606                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2607
2608                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2609                     i8xx_handle_vblank(dev, 1, iir))
2610                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2611
2612                 iir = new_iir;
2613         }
2614
2615         return IRQ_HANDLED;
2616 }
2617
2618 static void i8xx_irq_uninstall(struct drm_device * dev)
2619 {
2620         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2621         int pipe;
2622
2623         for_each_pipe(pipe) {
2624                 /* Clear enable bits; then clear status bits */
2625                 I915_WRITE(PIPESTAT(pipe), 0);
2626                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2627         }
2628         I915_WRITE16(IMR, 0xffff);
2629         I915_WRITE16(IER, 0x0);
2630         I915_WRITE16(IIR, I915_READ16(IIR));
2631 }
2632
2633 static void i915_irq_preinstall(struct drm_device * dev)
2634 {
2635         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2636         int pipe;
2637
2638         atomic_set(&dev_priv->irq_received, 0);
2639
2640         if (I915_HAS_HOTPLUG(dev)) {
2641                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2642                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2643         }
2644
2645         I915_WRITE16(HWSTAM, 0xeffe);
2646         for_each_pipe(pipe)
2647                 I915_WRITE(PIPESTAT(pipe), 0);
2648         I915_WRITE(IMR, 0xffffffff);
2649         I915_WRITE(IER, 0x0);
2650         POSTING_READ(IER);
2651 }
2652
2653 static int i915_irq_postinstall(struct drm_device *dev)
2654 {
2655         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2656         u32 enable_mask;
2657
2658         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2659
2660         /* Unmask the interrupts that we always want on. */
2661         dev_priv->irq_mask =
2662                 ~(I915_ASLE_INTERRUPT |
2663                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2664                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2665                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2666                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2667                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2668
2669         enable_mask =
2670                 I915_ASLE_INTERRUPT |
2671                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2672                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2673                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2674                 I915_USER_INTERRUPT;
2675
2676         if (I915_HAS_HOTPLUG(dev)) {
2677                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2678                 POSTING_READ(PORT_HOTPLUG_EN);
2679
2680                 /* Enable in IER... */
2681                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2682                 /* and unmask in IMR */
2683                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2684         }
2685
2686         I915_WRITE(IMR, dev_priv->irq_mask);
2687         I915_WRITE(IER, enable_mask);
2688         POSTING_READ(IER);
2689
2690         i915_enable_asle_pipestat(dev);
2691
2692         return 0;
2693 }
2694
2695 /*
2696  * Returns true when a page flip has completed.
2697  */
2698 static bool i915_handle_vblank(struct drm_device *dev,
2699                                int plane, int pipe, u32 iir)
2700 {
2701         drm_i915_private_t *dev_priv = dev->dev_private;
2702         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2703
2704         if (!drm_handle_vblank(dev, pipe))
2705                 return false;
2706
2707         if ((iir & flip_pending) == 0)
2708                 return false;
2709
2710         intel_prepare_page_flip(dev, plane);
2711
2712         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2713          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2714          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2715          * the flip is completed (no longer pending). Since this doesn't raise
2716          * an interrupt per se, we watch for the change at vblank.
2717          */
2718         if (I915_READ(ISR) & flip_pending)
2719                 return false;
2720
2721         intel_finish_page_flip(dev, pipe);
2722
2723         return true;
2724 }
2725
2726 static irqreturn_t i915_irq_handler(int irq, void *arg)
2727 {
2728         struct drm_device *dev = (struct drm_device *) arg;
2729         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2730         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2731         unsigned long irqflags;
2732         u32 flip_mask =
2733                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2734                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2735         int pipe, ret = IRQ_NONE;
2736
2737         atomic_inc(&dev_priv->irq_received);
2738
2739         iir = I915_READ(IIR);
2740         do {
2741                 bool irq_received = (iir & ~flip_mask) != 0;
2742                 bool blc_event = false;
2743
2744                 /* Can't rely on pipestat interrupt bit in iir as it might
2745                  * have been cleared after the pipestat interrupt was received.
2746                  * It doesn't set the bit in iir again, but it still produces
2747                  * interrupts (for non-MSI).
2748                  */
2749                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2750                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2751                         i915_handle_error(dev, false);
2752
2753                 for_each_pipe(pipe) {
2754                         int reg = PIPESTAT(pipe);
2755                         pipe_stats[pipe] = I915_READ(reg);
2756
2757                         /* Clear the PIPE*STAT regs before the IIR */
2758                         if (pipe_stats[pipe] & 0x8000ffff) {
2759                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2760                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2761                                                          pipe_name(pipe));
2762                                 I915_WRITE(reg, pipe_stats[pipe]);
2763                                 irq_received = true;
2764                         }
2765                 }
2766                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2767
2768                 if (!irq_received)
2769                         break;
2770
2771                 /* Consume port.  Then clear IIR or we'll miss events */
2772                 if ((I915_HAS_HOTPLUG(dev)) &&
2773                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2774                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2775                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2776
2777                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2778                                   hotplug_status);
2779
2780                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2781
2782                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2783                         POSTING_READ(PORT_HOTPLUG_STAT);
2784                 }
2785
2786                 I915_WRITE(IIR, iir & ~flip_mask);
2787                 new_iir = I915_READ(IIR); /* Flush posted writes */
2788
2789                 if (iir & I915_USER_INTERRUPT)
2790                         notify_ring(dev, &dev_priv->ring[RCS]);
2791
2792                 for_each_pipe(pipe) {
2793                         int plane = pipe;
2794                         if (IS_MOBILE(dev))
2795                                 plane = !plane;
2796
2797                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2798                             i915_handle_vblank(dev, plane, pipe, iir))
2799                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2800
2801                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2802                                 blc_event = true;
2803                 }
2804
2805                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2806                         intel_opregion_asle_intr(dev);
2807
2808                 /* With MSI, interrupts are only generated when iir
2809                  * transitions from zero to nonzero.  If another bit got
2810                  * set while we were handling the existing iir bits, then
2811                  * we would never get another interrupt.
2812                  *
2813                  * This is fine on non-MSI as well, as if we hit this path
2814                  * we avoid exiting the interrupt handler only to generate
2815                  * another one.
2816                  *
2817                  * Note that for MSI this could cause a stray interrupt report
2818                  * if an interrupt landed in the time between writing IIR and
2819                  * the posting read.  This should be rare enough to never
2820                  * trigger the 99% of 100,000 interrupts test for disabling
2821                  * stray interrupts.
2822                  */
2823                 ret = IRQ_HANDLED;
2824                 iir = new_iir;
2825         } while (iir & ~flip_mask);
2826
2827         i915_update_dri1_breadcrumb(dev);
2828
2829         return ret;
2830 }
2831
2832 static void i915_irq_uninstall(struct drm_device * dev)
2833 {
2834         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2835         int pipe;
2836
2837         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2838
2839         if (I915_HAS_HOTPLUG(dev)) {
2840                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2841                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2842         }
2843
2844         I915_WRITE16(HWSTAM, 0xffff);
2845         for_each_pipe(pipe) {
2846                 /* Clear enable bits; then clear status bits */
2847                 I915_WRITE(PIPESTAT(pipe), 0);
2848                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2849         }
2850         I915_WRITE(IMR, 0xffffffff);
2851         I915_WRITE(IER, 0x0);
2852
2853         I915_WRITE(IIR, I915_READ(IIR));
2854 }
2855
2856 static void i965_irq_preinstall(struct drm_device * dev)
2857 {
2858         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2859         int pipe;
2860
2861         atomic_set(&dev_priv->irq_received, 0);
2862
2863         I915_WRITE(PORT_HOTPLUG_EN, 0);
2864         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2865
2866         I915_WRITE(HWSTAM, 0xeffe);
2867         for_each_pipe(pipe)
2868                 I915_WRITE(PIPESTAT(pipe), 0);
2869         I915_WRITE(IMR, 0xffffffff);
2870         I915_WRITE(IER, 0x0);
2871         POSTING_READ(IER);
2872 }
2873
2874 static int i965_irq_postinstall(struct drm_device *dev)
2875 {
2876         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2877         u32 enable_mask;
2878         u32 error_mask;
2879         unsigned long irqflags;
2880
2881         /* Unmask the interrupts that we always want on. */
2882         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2883                                I915_DISPLAY_PORT_INTERRUPT |
2884                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2885                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2886                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2887                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2888                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2889
2890         enable_mask = ~dev_priv->irq_mask;
2891         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2892                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2893         enable_mask |= I915_USER_INTERRUPT;
2894
2895         if (IS_G4X(dev))
2896                 enable_mask |= I915_BSD_USER_INTERRUPT;
2897
2898         /* Interrupt setup is already guaranteed to be single-threaded, this is
2899          * just to make the assert_spin_locked check happy. */
2900         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2901         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2902         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2903
2904         /*
2905          * Enable some error detection, note the instruction error mask
2906          * bit is reserved, so we leave it masked.
2907          */
2908         if (IS_G4X(dev)) {
2909                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2910                                GM45_ERROR_MEM_PRIV |
2911                                GM45_ERROR_CP_PRIV |
2912                                I915_ERROR_MEMORY_REFRESH);
2913         } else {
2914                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2915                                I915_ERROR_MEMORY_REFRESH);
2916         }
2917         I915_WRITE(EMR, error_mask);
2918
2919         I915_WRITE(IMR, dev_priv->irq_mask);
2920         I915_WRITE(IER, enable_mask);
2921         POSTING_READ(IER);
2922
2923         I915_WRITE(PORT_HOTPLUG_EN, 0);
2924         POSTING_READ(PORT_HOTPLUG_EN);
2925
2926         i915_enable_asle_pipestat(dev);
2927
2928         return 0;
2929 }
2930
2931 static void i915_hpd_irq_setup(struct drm_device *dev)
2932 {
2933         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2934         struct drm_mode_config *mode_config = &dev->mode_config;
2935         struct intel_encoder *intel_encoder;
2936         u32 hotplug_en;
2937
2938         assert_spin_locked(&dev_priv->irq_lock);
2939
2940         if (I915_HAS_HOTPLUG(dev)) {
2941                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2942                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2943                 /* Note HDMI and DP share hotplug bits */
2944                 /* enable bits are the same for all generations */
2945                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2946                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2947                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2948                 /* Programming the CRT detection parameters tends
2949                    to generate a spurious hotplug event about three
2950                    seconds later.  So just do it once.
2951                 */
2952                 if (IS_G4X(dev))
2953                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2954                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2955                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2956
2957                 /* Ignore TV since it's buggy */
2958                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2959         }
2960 }
2961
2962 static irqreturn_t i965_irq_handler(int irq, void *arg)
2963 {
2964         struct drm_device *dev = (struct drm_device *) arg;
2965         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2966         u32 iir, new_iir;
2967         u32 pipe_stats[I915_MAX_PIPES];
2968         unsigned long irqflags;
2969         int irq_received;
2970         int ret = IRQ_NONE, pipe;
2971         u32 flip_mask =
2972                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2973                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2974
2975         atomic_inc(&dev_priv->irq_received);
2976
2977         iir = I915_READ(IIR);
2978
2979         for (;;) {
2980                 bool blc_event = false;
2981
2982                 irq_received = (iir & ~flip_mask) != 0;
2983
2984                 /* Can't rely on pipestat interrupt bit in iir as it might
2985                  * have been cleared after the pipestat interrupt was received.
2986                  * It doesn't set the bit in iir again, but it still produces
2987                  * interrupts (for non-MSI).
2988                  */
2989                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2990                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2991                         i915_handle_error(dev, false);
2992
2993                 for_each_pipe(pipe) {
2994                         int reg = PIPESTAT(pipe);
2995                         pipe_stats[pipe] = I915_READ(reg);
2996
2997                         /*
2998                          * Clear the PIPE*STAT regs before the IIR
2999                          */
3000                         if (pipe_stats[pipe] & 0x8000ffff) {
3001                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3002                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
3003                                                          pipe_name(pipe));
3004                                 I915_WRITE(reg, pipe_stats[pipe]);
3005                                 irq_received = 1;
3006                         }
3007                 }
3008                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3009
3010                 if (!irq_received)
3011                         break;
3012
3013                 ret = IRQ_HANDLED;
3014
3015                 /* Consume port.  Then clear IIR or we'll miss events */
3016                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
3017                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
3018                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
3019                                                                   HOTPLUG_INT_STATUS_G4X :
3020                                                                   HOTPLUG_INT_STATUS_I915);
3021
3022                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3023                                   hotplug_status);
3024
3025                         intel_hpd_irq_handler(dev, hotplug_trigger,
3026                                               IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3027
3028                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3029                         I915_READ(PORT_HOTPLUG_STAT);
3030                 }
3031
3032                 I915_WRITE(IIR, iir & ~flip_mask);
3033                 new_iir = I915_READ(IIR); /* Flush posted writes */
3034
3035                 if (iir & I915_USER_INTERRUPT)
3036                         notify_ring(dev, &dev_priv->ring[RCS]);
3037                 if (iir & I915_BSD_USER_INTERRUPT)
3038                         notify_ring(dev, &dev_priv->ring[VCS]);
3039
3040                 for_each_pipe(pipe) {
3041                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3042                             i915_handle_vblank(dev, pipe, pipe, iir))
3043                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3044
3045                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3046                                 blc_event = true;
3047                 }
3048
3049
3050                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3051                         intel_opregion_asle_intr(dev);
3052
3053                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3054                         gmbus_irq_handler(dev);
3055
3056                 /* With MSI, interrupts are only generated when iir
3057                  * transitions from zero to nonzero.  If another bit got
3058                  * set while we were handling the existing iir bits, then
3059                  * we would never get another interrupt.
3060                  *
3061                  * This is fine on non-MSI as well, as if we hit this path
3062                  * we avoid exiting the interrupt handler only to generate
3063                  * another one.
3064                  *
3065                  * Note that for MSI this could cause a stray interrupt report
3066                  * if an interrupt landed in the time between writing IIR and
3067                  * the posting read.  This should be rare enough to never
3068                  * trigger the 99% of 100,000 interrupts test for disabling
3069                  * stray interrupts.
3070                  */
3071                 iir = new_iir;
3072         }
3073
3074         i915_update_dri1_breadcrumb(dev);
3075
3076         return ret;
3077 }
3078
3079 static void i965_irq_uninstall(struct drm_device * dev)
3080 {
3081         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3082         int pipe;
3083
3084         if (!dev_priv)
3085                 return;
3086
3087         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3088
3089         I915_WRITE(PORT_HOTPLUG_EN, 0);
3090         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3091
3092         I915_WRITE(HWSTAM, 0xffffffff);
3093         for_each_pipe(pipe)
3094                 I915_WRITE(PIPESTAT(pipe), 0);
3095         I915_WRITE(IMR, 0xffffffff);
3096         I915_WRITE(IER, 0x0);
3097
3098         for_each_pipe(pipe)
3099                 I915_WRITE(PIPESTAT(pipe),
3100                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3101         I915_WRITE(IIR, I915_READ(IIR));
3102 }
3103
3104 static void i915_reenable_hotplug_timer_func(unsigned long data)
3105 {
3106         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3107         struct drm_device *dev = dev_priv->dev;
3108         struct drm_mode_config *mode_config = &dev->mode_config;
3109         unsigned long irqflags;
3110         int i;
3111
3112         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3113         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3114                 struct drm_connector *connector;
3115
3116                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3117                         continue;
3118
3119                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3120
3121                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3122                         struct intel_connector *intel_connector = to_intel_connector(connector);
3123
3124                         if (intel_connector->encoder->hpd_pin == i) {
3125                                 if (connector->polled != intel_connector->polled)
3126                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3127                                                          drm_get_connector_name(connector));
3128                                 connector->polled = intel_connector->polled;
3129                                 if (!connector->polled)
3130                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3131                         }
3132                 }
3133         }
3134         if (dev_priv->display.hpd_irq_setup)
3135                 dev_priv->display.hpd_irq_setup(dev);
3136         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3137 }
3138
3139 void intel_irq_init(struct drm_device *dev)
3140 {
3141         struct drm_i915_private *dev_priv = dev->dev_private;
3142
3143         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3144         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3145         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3146         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3147
3148         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3149                     i915_hangcheck_elapsed,
3150                     (unsigned long) dev);
3151         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3152                     (unsigned long) dev_priv);
3153
3154         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3155
3156         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3157         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3158         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3159                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3160                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3161         }
3162
3163         if (drm_core_check_feature(dev, DRIVER_MODESET))
3164                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3165         else
3166                 dev->driver->get_vblank_timestamp = NULL;
3167         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3168
3169         if (IS_VALLEYVIEW(dev)) {
3170                 dev->driver->irq_handler = valleyview_irq_handler;
3171                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3172                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3173                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3174                 dev->driver->enable_vblank = valleyview_enable_vblank;
3175                 dev->driver->disable_vblank = valleyview_disable_vblank;
3176                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3177         } else if (HAS_PCH_SPLIT(dev)) {
3178                 dev->driver->irq_handler = ironlake_irq_handler;
3179                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3180                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3181                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3182                 dev->driver->enable_vblank = ironlake_enable_vblank;
3183                 dev->driver->disable_vblank = ironlake_disable_vblank;
3184                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3185         } else {
3186                 if (INTEL_INFO(dev)->gen == 2) {
3187                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3188                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3189                         dev->driver->irq_handler = i8xx_irq_handler;
3190                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3191                 } else if (INTEL_INFO(dev)->gen == 3) {
3192                         dev->driver->irq_preinstall = i915_irq_preinstall;
3193                         dev->driver->irq_postinstall = i915_irq_postinstall;
3194                         dev->driver->irq_uninstall = i915_irq_uninstall;
3195                         dev->driver->irq_handler = i915_irq_handler;
3196                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3197                 } else {
3198                         dev->driver->irq_preinstall = i965_irq_preinstall;
3199                         dev->driver->irq_postinstall = i965_irq_postinstall;
3200                         dev->driver->irq_uninstall = i965_irq_uninstall;
3201                         dev->driver->irq_handler = i965_irq_handler;
3202                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3203                 }
3204                 dev->driver->enable_vblank = i915_enable_vblank;
3205                 dev->driver->disable_vblank = i915_disable_vblank;
3206         }
3207 }
3208
3209 void intel_hpd_init(struct drm_device *dev)
3210 {
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         struct drm_mode_config *mode_config = &dev->mode_config;
3213         struct drm_connector *connector;
3214         unsigned long irqflags;
3215         int i;
3216
3217         for (i = 1; i < HPD_NUM_PINS; i++) {
3218                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3219                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3220         }
3221         list_for_each_entry(connector, &mode_config->connector_list, head) {
3222                 struct intel_connector *intel_connector = to_intel_connector(connector);
3223                 connector->polled = intel_connector->polled;
3224                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3225                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3226         }
3227
3228         /* Interrupt setup is already guaranteed to be single-threaded, this is
3229          * just to make the assert_spin_locked checks happy. */
3230         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3231         if (dev_priv->display.hpd_irq_setup)
3232                 dev_priv->display.hpd_irq_setup(dev);
3233         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3234 }
3235
3236 /* Disable interrupts so we can allow Package C8+. */
3237 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240         unsigned long irqflags;
3241
3242         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3243
3244         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3245         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3246         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3247         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3248         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3249
3250         ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3251         ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3252         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3253         snb_disable_pm_irq(dev_priv, 0xffffffff);
3254
3255         dev_priv->pc8.irqs_disabled = true;
3256
3257         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3258 }
3259
3260 /* Restore interrupts so we can recover from Package C8+. */
3261 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3262 {
3263         struct drm_i915_private *dev_priv = dev->dev_private;
3264         unsigned long irqflags;
3265         uint32_t val, expected;
3266
3267         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3268
3269         val = I915_READ(DEIMR);
3270         expected = ~DE_PCH_EVENT_IVB;
3271         WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3272
3273         val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3274         expected = ~SDE_HOTPLUG_MASK_CPT;
3275         WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3276              val, expected);
3277
3278         val = I915_READ(GTIMR);
3279         expected = 0xffffffff;
3280         WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3281
3282         val = I915_READ(GEN6_PMIMR);
3283         expected = 0xffffffff;
3284         WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3285              expected);
3286
3287         dev_priv->pc8.irqs_disabled = false;
3288
3289         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3290         ibx_enable_display_interrupt(dev_priv,
3291                                      ~dev_priv->pc8.regsave.sdeimr &
3292                                      ~SDE_HOTPLUG_MASK_CPT);
3293         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3294         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3295         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3296
3297         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3298 }