1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31 #include <linux/sysrq.h>
32 #include <linux/slab.h>
33 #include <linux/circ_buf.h>
35 #include <drm/i915_drm.h>
37 #include "i915_trace.h"
38 #include "intel_drv.h"
41 * DOC: interrupt handling
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
49 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
53 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
57 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
61 [HPD_CRT] = SDE_CRT_HOTPLUG,
62 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
63 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
64 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
65 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
69 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
70 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
71 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
72 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
73 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
76 static const u32 hpd_spt[HPD_NUM_PINS] = {
77 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
78 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
79 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
80 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
81 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
85 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
86 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
87 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
88 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
89 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
90 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
94 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
95 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
96 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
97 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
98 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
99 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
103 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
104 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
105 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
106 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
107 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
108 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
113 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
114 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
115 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
118 /* IIR can theoretically queue up two events. Be paranoid. */
119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
120 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
121 POSTING_READ(GEN8_##type##_IMR(which)); \
122 I915_WRITE(GEN8_##type##_IER(which), 0); \
123 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
124 POSTING_READ(GEN8_##type##_IIR(which)); \
125 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
126 POSTING_READ(GEN8_##type##_IIR(which)); \
129 #define GEN5_IRQ_RESET(type) do { \
130 I915_WRITE(type##IMR, 0xffffffff); \
131 POSTING_READ(type##IMR); \
132 I915_WRITE(type##IER, 0); \
133 I915_WRITE(type##IIR, 0xffffffff); \
134 POSTING_READ(type##IIR); \
135 I915_WRITE(type##IIR, 0xffffffff); \
136 POSTING_READ(type##IIR); \
140 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
145 u32 val = I915_READ(reg);
150 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
151 i915_mmio_reg_offset(reg), val);
152 I915_WRITE(reg, 0xffffffff);
154 I915_WRITE(reg, 0xffffffff);
158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
159 gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
160 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
161 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
162 POSTING_READ(GEN8_##type##_IMR(which)); \
165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
166 gen5_assert_iir_is_zero(dev_priv, type##IIR); \
167 I915_WRITE(type##IER, (ier_val)); \
168 I915_WRITE(type##IMR, (imr_val)); \
169 POSTING_READ(type##IMR); \
172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
174 /* For display hotplug interrupt */
176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
182 assert_spin_locked(&dev_priv->irq_lock);
183 WARN_ON(bits & ~mask);
185 val = I915_READ(PORT_HOTPLUG_EN);
188 I915_WRITE(PORT_HOTPLUG_EN, val);
192 * i915_hotplug_interrupt_update - update hotplug interrupt enable
193 * @dev_priv: driver private
194 * @mask: bits to update
195 * @bits: bits to enable
196 * NOTE: the HPD enable bits are modified both inside and outside
197 * of an interrupt context. To avoid that read-modify-write cycles
198 * interfer, these bits are protected by a spinlock. Since this
199 * function is usually not called from a context where the lock is
200 * held already, this function acquires the lock itself. A non-locking
201 * version is also available.
203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
207 spin_lock_irq(&dev_priv->irq_lock);
208 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
209 spin_unlock_irq(&dev_priv->irq_lock);
213 * ilk_update_display_irq - update DEIMR
214 * @dev_priv: driver private
215 * @interrupt_mask: mask of interrupt bits to update
216 * @enabled_irq_mask: mask of interrupt bits to enable
218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
219 uint32_t interrupt_mask,
220 uint32_t enabled_irq_mask)
224 assert_spin_locked(&dev_priv->irq_lock);
226 WARN_ON(enabled_irq_mask & ~interrupt_mask);
228 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
231 new_val = dev_priv->irq_mask;
232 new_val &= ~interrupt_mask;
233 new_val |= (~enabled_irq_mask & interrupt_mask);
235 if (new_val != dev_priv->irq_mask) {
236 dev_priv->irq_mask = new_val;
237 I915_WRITE(DEIMR, dev_priv->irq_mask);
243 * ilk_update_gt_irq - update GTIMR
244 * @dev_priv: driver private
245 * @interrupt_mask: mask of interrupt bits to update
246 * @enabled_irq_mask: mask of interrupt bits to enable
248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
249 uint32_t interrupt_mask,
250 uint32_t enabled_irq_mask)
252 assert_spin_locked(&dev_priv->irq_lock);
254 WARN_ON(enabled_irq_mask & ~interrupt_mask);
256 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
259 dev_priv->gt_irq_mask &= ~interrupt_mask;
260 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
261 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
264 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
266 ilk_update_gt_irq(dev_priv, mask, mask);
267 POSTING_READ_FW(GTIMR);
270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
272 ilk_update_gt_irq(dev_priv, mask, 0);
275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
277 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
282 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
287 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
291 * snb_update_pm_irq - update GEN6_PMIMR
292 * @dev_priv: driver private
293 * @interrupt_mask: mask of interrupt bits to update
294 * @enabled_irq_mask: mask of interrupt bits to enable
296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
297 uint32_t interrupt_mask,
298 uint32_t enabled_irq_mask)
302 WARN_ON(enabled_irq_mask & ~interrupt_mask);
304 assert_spin_locked(&dev_priv->irq_lock);
306 new_val = dev_priv->pm_irq_mask;
307 new_val &= ~interrupt_mask;
308 new_val |= (~enabled_irq_mask & interrupt_mask);
310 if (new_val != dev_priv->pm_irq_mask) {
311 dev_priv->pm_irq_mask = new_val;
312 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
313 POSTING_READ(gen6_pm_imr(dev_priv));
317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
319 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
322 snb_update_pm_irq(dev_priv, mask, mask);
325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
328 snb_update_pm_irq(dev_priv, mask, 0);
331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
333 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
336 __gen6_disable_pm_irq(dev_priv, mask);
339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
341 i915_reg_t reg = gen6_pm_iir(dev_priv);
343 spin_lock_irq(&dev_priv->irq_lock);
344 I915_WRITE(reg, dev_priv->pm_rps_events);
345 I915_WRITE(reg, dev_priv->pm_rps_events);
347 dev_priv->rps.pm_iir = 0;
348 spin_unlock_irq(&dev_priv->irq_lock);
351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
353 spin_lock_irq(&dev_priv->irq_lock);
355 WARN_ON(dev_priv->rps.pm_iir);
356 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
357 dev_priv->rps.interrupts_enabled = true;
358 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
359 dev_priv->pm_rps_events);
360 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
362 spin_unlock_irq(&dev_priv->irq_lock);
365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
367 return (mask & ~dev_priv->rps.pm_intr_keep);
370 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
372 spin_lock_irq(&dev_priv->irq_lock);
373 dev_priv->rps.interrupts_enabled = false;
374 spin_unlock_irq(&dev_priv->irq_lock);
376 cancel_work_sync(&dev_priv->rps.work);
378 spin_lock_irq(&dev_priv->irq_lock);
380 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
382 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
383 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
384 ~dev_priv->pm_rps_events);
386 spin_unlock_irq(&dev_priv->irq_lock);
388 synchronize_irq(dev_priv->dev->irq);
392 * bdw_update_port_irq - update DE port interrupt
393 * @dev_priv: driver private
394 * @interrupt_mask: mask of interrupt bits to update
395 * @enabled_irq_mask: mask of interrupt bits to enable
397 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
398 uint32_t interrupt_mask,
399 uint32_t enabled_irq_mask)
404 assert_spin_locked(&dev_priv->irq_lock);
406 WARN_ON(enabled_irq_mask & ~interrupt_mask);
408 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
411 old_val = I915_READ(GEN8_DE_PORT_IMR);
414 new_val &= ~interrupt_mask;
415 new_val |= (~enabled_irq_mask & interrupt_mask);
417 if (new_val != old_val) {
418 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
419 POSTING_READ(GEN8_DE_PORT_IMR);
424 * bdw_update_pipe_irq - update DE pipe interrupt
425 * @dev_priv: driver private
426 * @pipe: pipe whose interrupt to update
427 * @interrupt_mask: mask of interrupt bits to update
428 * @enabled_irq_mask: mask of interrupt bits to enable
430 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
432 uint32_t interrupt_mask,
433 uint32_t enabled_irq_mask)
437 assert_spin_locked(&dev_priv->irq_lock);
439 WARN_ON(enabled_irq_mask & ~interrupt_mask);
441 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
444 new_val = dev_priv->de_irq_mask[pipe];
445 new_val &= ~interrupt_mask;
446 new_val |= (~enabled_irq_mask & interrupt_mask);
448 if (new_val != dev_priv->de_irq_mask[pipe]) {
449 dev_priv->de_irq_mask[pipe] = new_val;
450 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
451 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
456 * ibx_display_interrupt_update - update SDEIMR
457 * @dev_priv: driver private
458 * @interrupt_mask: mask of interrupt bits to update
459 * @enabled_irq_mask: mask of interrupt bits to enable
461 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
462 uint32_t interrupt_mask,
463 uint32_t enabled_irq_mask)
465 uint32_t sdeimr = I915_READ(SDEIMR);
466 sdeimr &= ~interrupt_mask;
467 sdeimr |= (~enabled_irq_mask & interrupt_mask);
469 WARN_ON(enabled_irq_mask & ~interrupt_mask);
471 assert_spin_locked(&dev_priv->irq_lock);
473 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
476 I915_WRITE(SDEIMR, sdeimr);
477 POSTING_READ(SDEIMR);
481 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
482 u32 enable_mask, u32 status_mask)
484 i915_reg_t reg = PIPESTAT(pipe);
485 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
487 assert_spin_locked(&dev_priv->irq_lock);
488 WARN_ON(!intel_irqs_enabled(dev_priv));
490 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
491 status_mask & ~PIPESTAT_INT_STATUS_MASK,
492 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
493 pipe_name(pipe), enable_mask, status_mask))
496 if ((pipestat & enable_mask) == enable_mask)
499 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
501 /* Enable the interrupt, clear any pending status */
502 pipestat |= enable_mask | status_mask;
503 I915_WRITE(reg, pipestat);
508 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
509 u32 enable_mask, u32 status_mask)
511 i915_reg_t reg = PIPESTAT(pipe);
512 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
514 assert_spin_locked(&dev_priv->irq_lock);
515 WARN_ON(!intel_irqs_enabled(dev_priv));
517 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
518 status_mask & ~PIPESTAT_INT_STATUS_MASK,
519 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
520 pipe_name(pipe), enable_mask, status_mask))
523 if ((pipestat & enable_mask) == 0)
526 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
528 pipestat &= ~enable_mask;
529 I915_WRITE(reg, pipestat);
533 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
535 u32 enable_mask = status_mask << 16;
538 * On pipe A we don't support the PSR interrupt yet,
539 * on pipe B and C the same bit MBZ.
541 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
544 * On pipe B and C we don't support the PSR interrupt yet, on pipe
545 * A the same bit is for perf counters which we don't use either.
547 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
550 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
551 SPRITE0_FLIP_DONE_INT_EN_VLV |
552 SPRITE1_FLIP_DONE_INT_EN_VLV);
553 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
554 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
555 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
556 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
562 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
567 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
568 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
571 enable_mask = status_mask << 16;
572 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
576 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
581 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
582 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
585 enable_mask = status_mask << 16;
586 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
590 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
591 * @dev_priv: i915 device private
593 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
595 if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
598 spin_lock_irq(&dev_priv->irq_lock);
600 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
601 if (INTEL_GEN(dev_priv) >= 4)
602 i915_enable_pipestat(dev_priv, PIPE_A,
603 PIPE_LEGACY_BLC_EVENT_STATUS);
605 spin_unlock_irq(&dev_priv->irq_lock);
609 * This timing diagram depicts the video signal in and
610 * around the vertical blanking period.
612 * Assumptions about the fictitious mode used in this example:
614 * vsync_start = vblank_start + 1
615 * vsync_end = vblank_start + 2
616 * vtotal = vblank_start + 3
619 * latch double buffered registers
620 * increment frame counter (ctg+)
621 * generate start of vblank interrupt (gen4+)
624 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
625 * | may be shifted forward 1-3 extra lines via PIPECONF
627 * | | start of vsync:
628 * | | generate vsync interrupt
630 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
631 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
632 * ----va---> <-----------------vb--------------------> <--------va-------------
633 * | | <----vs-----> |
634 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
635 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
636 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
638 * last visible pixel first visible pixel
639 * | increment frame counter (gen3/4)
640 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
642 * x = horizontal active
643 * _ = horizontal blanking
644 * hs = horizontal sync
645 * va = vertical active
646 * vb = vertical blanking
648 * vbs = vblank_start (number)
651 * - most events happen at the start of horizontal sync
652 * - frame start happens at the start of horizontal blank, 1-4 lines
653 * (depending on PIPECONF settings) after the start of vblank
654 * - gen3/4 pixel and frame counter are synchronized with the start
655 * of horizontal active on the first line of vertical active
658 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
660 /* Gen2 doesn't have a hardware frame counter */
664 /* Called from drm generic code, passed a 'crtc', which
665 * we use as a pipe index
667 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
669 struct drm_i915_private *dev_priv = dev->dev_private;
670 i915_reg_t high_frame, low_frame;
671 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
672 struct intel_crtc *intel_crtc =
673 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
674 const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
676 htotal = mode->crtc_htotal;
677 hsync_start = mode->crtc_hsync_start;
678 vbl_start = mode->crtc_vblank_start;
679 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
680 vbl_start = DIV_ROUND_UP(vbl_start, 2);
682 /* Convert to pixel count */
685 /* Start of vblank event occurs at start of hsync */
686 vbl_start -= htotal - hsync_start;
688 high_frame = PIPEFRAME(pipe);
689 low_frame = PIPEFRAMEPIXEL(pipe);
692 * High & low register fields aren't synchronized, so make sure
693 * we get a low value that's stable across two reads of the high
697 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
698 low = I915_READ(low_frame);
699 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
700 } while (high1 != high2);
702 high1 >>= PIPE_FRAME_HIGH_SHIFT;
703 pixel = low & PIPE_PIXEL_MASK;
704 low >>= PIPE_FRAME_LOW_SHIFT;
707 * The frame counter increments at beginning of active.
708 * Cook up a vblank counter by also checking the pixel
709 * counter against vblank start.
711 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
714 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
716 struct drm_i915_private *dev_priv = dev->dev_private;
718 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
721 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
722 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
724 struct drm_device *dev = crtc->base.dev;
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 const struct drm_display_mode *mode = &crtc->base.hwmode;
727 enum pipe pipe = crtc->pipe;
728 int position, vtotal;
730 vtotal = mode->crtc_vtotal;
731 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
734 if (IS_GEN2(dev_priv))
735 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
737 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
740 * On HSW, the DSL reg (0x70000) appears to return 0 if we
741 * read it just before the start of vblank. So try it again
742 * so we don't accidentally end up spanning a vblank frame
743 * increment, causing the pipe_update_end() code to squak at us.
745 * The nature of this problem means we can't simply check the ISR
746 * bit and return the vblank start value; nor can we use the scanline
747 * debug register in the transcoder as it appears to have the same
748 * problem. We may need to extend this to include other platforms,
749 * but so far testing only shows the problem on HSW.
751 if (HAS_DDI(dev_priv) && !position) {
754 for (i = 0; i < 100; i++) {
756 temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
758 if (temp != position) {
766 * See update_scanline_offset() for the details on the
767 * scanline_offset adjustment.
769 return (position + crtc->scanline_offset) % vtotal;
772 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
773 unsigned int flags, int *vpos, int *hpos,
774 ktime_t *stime, ktime_t *etime,
775 const struct drm_display_mode *mode)
777 struct drm_i915_private *dev_priv = dev->dev_private;
778 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
781 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
784 unsigned long irqflags;
786 if (WARN_ON(!mode->crtc_clock)) {
787 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
788 "pipe %c\n", pipe_name(pipe));
792 htotal = mode->crtc_htotal;
793 hsync_start = mode->crtc_hsync_start;
794 vtotal = mode->crtc_vtotal;
795 vbl_start = mode->crtc_vblank_start;
796 vbl_end = mode->crtc_vblank_end;
798 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
799 vbl_start = DIV_ROUND_UP(vbl_start, 2);
804 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
807 * Lock uncore.lock, as we will do multiple timing critical raw
808 * register reads, potentially with preemption disabled, so the
809 * following code must not block on uncore.lock.
811 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
813 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
815 /* Get optional system timestamp before query. */
817 *stime = ktime_get();
819 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
820 /* No obvious pixelcount register. Only query vertical
821 * scanout position from Display scan line register.
823 position = __intel_get_crtc_scanline(intel_crtc);
825 /* Have access to pixelcount since start of frame.
826 * We can split this into vertical and horizontal
829 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
831 /* convert to pixel counts */
837 * In interlaced modes, the pixel counter counts all pixels,
838 * so one field will have htotal more pixels. In order to avoid
839 * the reported position from jumping backwards when the pixel
840 * counter is beyond the length of the shorter field, just
841 * clamp the position the length of the shorter field. This
842 * matches how the scanline counter based position works since
843 * the scanline counter doesn't count the two half lines.
845 if (position >= vtotal)
846 position = vtotal - 1;
849 * Start of vblank interrupt is triggered at start of hsync,
850 * just prior to the first active line of vblank. However we
851 * consider lines to start at the leading edge of horizontal
852 * active. So, should we get here before we've crossed into
853 * the horizontal active of the first line in vblank, we would
854 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
855 * always add htotal-hsync_start to the current pixel position.
857 position = (position + htotal - hsync_start) % vtotal;
860 /* Get optional system timestamp after query. */
862 *etime = ktime_get();
864 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
866 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
868 in_vbl = position >= vbl_start && position < vbl_end;
871 * While in vblank, position will be negative
872 * counting up towards 0 at vbl_end. And outside
873 * vblank, position will be positive counting
876 if (position >= vbl_start)
879 position += vtotal - vbl_end;
881 if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
885 *vpos = position / htotal;
886 *hpos = position - (*vpos * htotal);
891 ret |= DRM_SCANOUTPOS_IN_VBLANK;
896 int intel_get_crtc_scanline(struct intel_crtc *crtc)
898 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
899 unsigned long irqflags;
902 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
903 position = __intel_get_crtc_scanline(crtc);
904 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
909 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
911 struct timeval *vblank_time,
914 struct drm_crtc *crtc;
916 if (pipe >= INTEL_INFO(dev)->num_pipes) {
917 DRM_ERROR("Invalid crtc %u\n", pipe);
921 /* Get drm_crtc to timestamp: */
922 crtc = intel_get_crtc_for_pipe(dev, pipe);
924 DRM_ERROR("Invalid crtc %u\n", pipe);
928 if (!crtc->hwmode.crtc_clock) {
929 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
933 /* Helper routine in DRM core does all the work: */
934 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
939 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
941 u32 busy_up, busy_down, max_avg, min_avg;
944 spin_lock(&mchdev_lock);
946 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
948 new_delay = dev_priv->ips.cur_delay;
950 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
951 busy_up = I915_READ(RCPREVBSYTUPAVG);
952 busy_down = I915_READ(RCPREVBSYTDNAVG);
953 max_avg = I915_READ(RCBMAXAVG);
954 min_avg = I915_READ(RCBMINAVG);
956 /* Handle RCS change request from hw */
957 if (busy_up > max_avg) {
958 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
959 new_delay = dev_priv->ips.cur_delay - 1;
960 if (new_delay < dev_priv->ips.max_delay)
961 new_delay = dev_priv->ips.max_delay;
962 } else if (busy_down < min_avg) {
963 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
964 new_delay = dev_priv->ips.cur_delay + 1;
965 if (new_delay > dev_priv->ips.min_delay)
966 new_delay = dev_priv->ips.min_delay;
969 if (ironlake_set_drps(dev_priv, new_delay))
970 dev_priv->ips.cur_delay = new_delay;
972 spin_unlock(&mchdev_lock);
977 static void notify_ring(struct intel_engine_cs *engine)
979 smp_store_mb(engine->irq_posted, true);
980 if (intel_engine_wakeup(engine)) {
981 trace_i915_gem_request_notify(engine);
982 engine->user_interrupts++;
986 static void vlv_c0_read(struct drm_i915_private *dev_priv,
987 struct intel_rps_ei *ei)
989 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
990 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
991 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
994 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
995 const struct intel_rps_ei *old,
996 const struct intel_rps_ei *now,
1000 unsigned int mul = 100;
1002 if (old->cz_clock == 0)
1005 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1008 time = now->cz_clock - old->cz_clock;
1009 time *= threshold * dev_priv->czclk_freq;
1011 /* Workload can be split between render + media, e.g. SwapBuffers
1012 * being blitted in X after being rendered in mesa. To account for
1013 * this we need to combine both engines into our activity counter.
1015 c0 = now->render_c0 - old->render_c0;
1016 c0 += now->media_c0 - old->media_c0;
1017 c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1022 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1024 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1025 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1028 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1030 struct intel_rps_ei now;
1033 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1036 vlv_c0_read(dev_priv, &now);
1037 if (now.cz_clock == 0)
1040 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1041 if (!vlv_c0_above(dev_priv,
1042 &dev_priv->rps.down_ei, &now,
1043 dev_priv->rps.down_threshold))
1044 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1045 dev_priv->rps.down_ei = now;
1048 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1049 if (vlv_c0_above(dev_priv,
1050 &dev_priv->rps.up_ei, &now,
1051 dev_priv->rps.up_threshold))
1052 events |= GEN6_PM_RP_UP_THRESHOLD;
1053 dev_priv->rps.up_ei = now;
1059 static bool any_waiters(struct drm_i915_private *dev_priv)
1061 struct intel_engine_cs *engine;
1063 for_each_engine(engine, dev_priv)
1064 if (intel_engine_has_waiter(engine))
1070 static void gen6_pm_rps_work(struct work_struct *work)
1072 struct drm_i915_private *dev_priv =
1073 container_of(work, struct drm_i915_private, rps.work);
1075 int new_delay, adj, min, max;
1078 spin_lock_irq(&dev_priv->irq_lock);
1079 /* Speed up work cancelation during disabling rps interrupts. */
1080 if (!dev_priv->rps.interrupts_enabled) {
1081 spin_unlock_irq(&dev_priv->irq_lock);
1086 * The RPS work is synced during runtime suspend, we don't require a
1087 * wakeref. TODO: instead of disabling the asserts make sure that we
1088 * always hold an RPM reference while the work is running.
1090 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1092 pm_iir = dev_priv->rps.pm_iir;
1093 dev_priv->rps.pm_iir = 0;
1094 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1095 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1096 client_boost = dev_priv->rps.client_boost;
1097 dev_priv->rps.client_boost = false;
1098 spin_unlock_irq(&dev_priv->irq_lock);
1100 /* Make sure we didn't queue anything we're not going to process. */
1101 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1103 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1106 mutex_lock(&dev_priv->rps.hw_lock);
1108 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1110 adj = dev_priv->rps.last_adj;
1111 new_delay = dev_priv->rps.cur_freq;
1112 min = dev_priv->rps.min_freq_softlimit;
1113 max = dev_priv->rps.max_freq_softlimit;
1116 new_delay = dev_priv->rps.max_freq_softlimit;
1118 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1121 else /* CHV needs even encode values */
1122 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1124 * For better performance, jump directly
1125 * to RPe if we're below it.
1127 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1128 new_delay = dev_priv->rps.efficient_freq;
1131 } else if (any_waiters(dev_priv)) {
1133 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1134 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1135 new_delay = dev_priv->rps.efficient_freq;
1137 new_delay = dev_priv->rps.min_freq_softlimit;
1139 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1142 else /* CHV needs even encode values */
1143 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1144 } else { /* unknown event */
1148 dev_priv->rps.last_adj = adj;
1150 /* sysfs frequency interfaces may have snuck in while servicing the
1154 new_delay = clamp_t(int, new_delay, min, max);
1156 intel_set_rps(dev_priv, new_delay);
1158 mutex_unlock(&dev_priv->rps.hw_lock);
1160 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1165 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1167 * @work: workqueue struct
1169 * Doesn't actually do anything except notify userspace. As a consequence of
1170 * this event, userspace should try to remap the bad rows since statistically
1171 * it is likely the same row is more likely to go bad again.
1173 static void ivybridge_parity_work(struct work_struct *work)
1175 struct drm_i915_private *dev_priv =
1176 container_of(work, struct drm_i915_private, l3_parity.error_work);
1177 u32 error_status, row, bank, subbank;
1178 char *parity_event[6];
1182 /* We must turn off DOP level clock gating to access the L3 registers.
1183 * In order to prevent a get/put style interface, acquire struct mutex
1184 * any time we access those registers.
1186 mutex_lock(&dev_priv->dev->struct_mutex);
1188 /* If we've screwed up tracking, just let the interrupt fire again */
1189 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1192 misccpctl = I915_READ(GEN7_MISCCPCTL);
1193 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1194 POSTING_READ(GEN7_MISCCPCTL);
1196 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1200 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1203 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1205 reg = GEN7_L3CDERRST1(slice);
1207 error_status = I915_READ(reg);
1208 row = GEN7_PARITY_ERROR_ROW(error_status);
1209 bank = GEN7_PARITY_ERROR_BANK(error_status);
1210 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1212 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1215 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1216 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1217 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1218 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1219 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1220 parity_event[5] = NULL;
1222 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1223 KOBJ_CHANGE, parity_event);
1225 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1226 slice, row, bank, subbank);
1228 kfree(parity_event[4]);
1229 kfree(parity_event[3]);
1230 kfree(parity_event[2]);
1231 kfree(parity_event[1]);
1234 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1237 WARN_ON(dev_priv->l3_parity.which_slice);
1238 spin_lock_irq(&dev_priv->irq_lock);
1239 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1240 spin_unlock_irq(&dev_priv->irq_lock);
1242 mutex_unlock(&dev_priv->dev->struct_mutex);
1245 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1248 if (!HAS_L3_DPF(dev_priv))
1251 spin_lock(&dev_priv->irq_lock);
1252 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1253 spin_unlock(&dev_priv->irq_lock);
1255 iir &= GT_PARITY_ERROR(dev_priv);
1256 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1257 dev_priv->l3_parity.which_slice |= 1 << 1;
1259 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1260 dev_priv->l3_parity.which_slice |= 1 << 0;
1262 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1265 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1268 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1269 notify_ring(&dev_priv->engine[RCS]);
1270 if (gt_iir & ILK_BSD_USER_INTERRUPT)
1271 notify_ring(&dev_priv->engine[VCS]);
1274 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1277 if (gt_iir & GT_RENDER_USER_INTERRUPT)
1278 notify_ring(&dev_priv->engine[RCS]);
1279 if (gt_iir & GT_BSD_USER_INTERRUPT)
1280 notify_ring(&dev_priv->engine[VCS]);
1281 if (gt_iir & GT_BLT_USER_INTERRUPT)
1282 notify_ring(&dev_priv->engine[BCS]);
1284 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1285 GT_BSD_CS_ERROR_INTERRUPT |
1286 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1287 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1289 if (gt_iir & GT_PARITY_ERROR(dev_priv))
1290 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1293 static __always_inline void
1294 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1296 if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1297 notify_ring(engine);
1298 if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1299 tasklet_schedule(&engine->irq_tasklet);
1302 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1306 irqreturn_t ret = IRQ_NONE;
1308 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1309 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1311 I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1314 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1317 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1318 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1320 I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1323 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1326 if (master_ctl & GEN8_GT_VECS_IRQ) {
1327 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1329 I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1332 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1335 if (master_ctl & GEN8_GT_PM_IRQ) {
1336 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1337 if (gt_iir[2] & dev_priv->pm_rps_events) {
1338 I915_WRITE_FW(GEN8_GT_IIR(2),
1339 gt_iir[2] & dev_priv->pm_rps_events);
1342 DRM_ERROR("The master control interrupt lied (PM)!\n");
1348 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1352 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1353 gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1354 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1355 gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1359 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1360 gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1361 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1362 gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1366 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1367 gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1369 if (gt_iir[2] & dev_priv->pm_rps_events)
1370 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1373 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1377 return val & PORTA_HOTPLUG_LONG_DETECT;
1379 return val & PORTB_HOTPLUG_LONG_DETECT;
1381 return val & PORTC_HOTPLUG_LONG_DETECT;
1387 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1391 return val & PORTE_HOTPLUG_LONG_DETECT;
1397 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1401 return val & PORTA_HOTPLUG_LONG_DETECT;
1403 return val & PORTB_HOTPLUG_LONG_DETECT;
1405 return val & PORTC_HOTPLUG_LONG_DETECT;
1407 return val & PORTD_HOTPLUG_LONG_DETECT;
1413 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1417 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1423 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1427 return val & PORTB_HOTPLUG_LONG_DETECT;
1429 return val & PORTC_HOTPLUG_LONG_DETECT;
1431 return val & PORTD_HOTPLUG_LONG_DETECT;
1437 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1441 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1443 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1445 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1452 * Get a bit mask of pins that have triggered, and which ones may be long.
1453 * This can be called multiple times with the same masks to accumulate
1454 * hotplug detection results from several registers.
1456 * Note that the caller is expected to zero out the masks initially.
1458 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1459 u32 hotplug_trigger, u32 dig_hotplug_reg,
1460 const u32 hpd[HPD_NUM_PINS],
1461 bool long_pulse_detect(enum port port, u32 val))
1466 for_each_hpd_pin(i) {
1467 if ((hpd[i] & hotplug_trigger) == 0)
1470 *pin_mask |= BIT(i);
1472 if (!intel_hpd_pin_to_port(i, &port))
1475 if (long_pulse_detect(port, dig_hotplug_reg))
1476 *long_mask |= BIT(i);
1479 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1480 hotplug_trigger, dig_hotplug_reg, *pin_mask);
1484 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1486 wake_up_all(&dev_priv->gmbus_wait_queue);
1489 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1491 wake_up_all(&dev_priv->gmbus_wait_queue);
1494 #if defined(CONFIG_DEBUG_FS)
1495 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1497 uint32_t crc0, uint32_t crc1,
1498 uint32_t crc2, uint32_t crc3,
1501 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1502 struct intel_pipe_crc_entry *entry;
1505 spin_lock(&pipe_crc->lock);
1507 if (!pipe_crc->entries) {
1508 spin_unlock(&pipe_crc->lock);
1509 DRM_DEBUG_KMS("spurious interrupt\n");
1513 head = pipe_crc->head;
1514 tail = pipe_crc->tail;
1516 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1517 spin_unlock(&pipe_crc->lock);
1518 DRM_ERROR("CRC buffer overflowing\n");
1522 entry = &pipe_crc->entries[head];
1524 entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1526 entry->crc[0] = crc0;
1527 entry->crc[1] = crc1;
1528 entry->crc[2] = crc2;
1529 entry->crc[3] = crc3;
1530 entry->crc[4] = crc4;
1532 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1533 pipe_crc->head = head;
1535 spin_unlock(&pipe_crc->lock);
1537 wake_up_interruptible(&pipe_crc->wq);
1541 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1543 uint32_t crc0, uint32_t crc1,
1544 uint32_t crc2, uint32_t crc3,
1549 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1552 display_pipe_crc_irq_handler(dev_priv, pipe,
1553 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1557 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1560 display_pipe_crc_irq_handler(dev_priv, pipe,
1561 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1562 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1563 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1564 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1565 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1568 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1571 uint32_t res1, res2;
1573 if (INTEL_GEN(dev_priv) >= 3)
1574 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1578 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1579 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1583 display_pipe_crc_irq_handler(dev_priv, pipe,
1584 I915_READ(PIPE_CRC_RES_RED(pipe)),
1585 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1586 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1590 /* The RPS events need forcewake, so we add them to a work queue and mask their
1591 * IMR bits until the work is done. Other interrupts can be processed without
1592 * the work queue. */
1593 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1595 if (pm_iir & dev_priv->pm_rps_events) {
1596 spin_lock(&dev_priv->irq_lock);
1597 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1598 if (dev_priv->rps.interrupts_enabled) {
1599 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1600 queue_work(dev_priv->wq, &dev_priv->rps.work);
1602 spin_unlock(&dev_priv->irq_lock);
1605 if (INTEL_INFO(dev_priv)->gen >= 8)
1608 if (HAS_VEBOX(dev_priv)) {
1609 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1610 notify_ring(&dev_priv->engine[VECS]);
1612 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1613 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1617 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1622 ret = drm_handle_vblank(dev_priv->dev, pipe);
1624 intel_finish_page_flip_mmio(dev_priv, pipe);
1629 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1630 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1634 spin_lock(&dev_priv->irq_lock);
1636 if (!dev_priv->display_irqs_enabled) {
1637 spin_unlock(&dev_priv->irq_lock);
1641 for_each_pipe(dev_priv, pipe) {
1643 u32 mask, iir_bit = 0;
1646 * PIPESTAT bits get signalled even when the interrupt is
1647 * disabled with the mask bits, and some of the status bits do
1648 * not generate interrupts at all (like the underrun bit). Hence
1649 * we need to be careful that we only handle what we want to
1653 /* fifo underruns are filterered in the underrun handler. */
1654 mask = PIPE_FIFO_UNDERRUN_STATUS;
1658 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1661 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1664 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1668 mask |= dev_priv->pipestat_irq_mask[pipe];
1673 reg = PIPESTAT(pipe);
1674 mask |= PIPESTAT_INT_ENABLE_MASK;
1675 pipe_stats[pipe] = I915_READ(reg) & mask;
1678 * Clear the PIPE*STAT regs before the IIR
1680 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1681 PIPESTAT_INT_STATUS_MASK))
1682 I915_WRITE(reg, pipe_stats[pipe]);
1684 spin_unlock(&dev_priv->irq_lock);
1687 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1688 u32 pipe_stats[I915_MAX_PIPES])
1692 for_each_pipe(dev_priv, pipe) {
1693 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1694 intel_pipe_handle_vblank(dev_priv, pipe))
1695 intel_check_page_flip(dev_priv, pipe);
1697 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1698 intel_finish_page_flip_cs(dev_priv, pipe);
1700 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1701 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1703 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1704 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1707 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1708 gmbus_irq_handler(dev_priv);
1711 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1713 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1716 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1718 return hotplug_status;
1721 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1724 u32 pin_mask = 0, long_mask = 0;
1726 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1727 IS_CHERRYVIEW(dev_priv)) {
1728 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1730 if (hotplug_trigger) {
1731 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1732 hotplug_trigger, hpd_status_g4x,
1733 i9xx_port_hotplug_long_detect);
1735 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1738 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1739 dp_aux_irq_handler(dev_priv);
1741 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1743 if (hotplug_trigger) {
1744 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1745 hotplug_trigger, hpd_status_i915,
1746 i9xx_port_hotplug_long_detect);
1747 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1752 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1754 struct drm_device *dev = arg;
1755 struct drm_i915_private *dev_priv = dev->dev_private;
1756 irqreturn_t ret = IRQ_NONE;
1758 if (!intel_irqs_enabled(dev_priv))
1761 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1762 disable_rpm_wakeref_asserts(dev_priv);
1765 u32 iir, gt_iir, pm_iir;
1766 u32 pipe_stats[I915_MAX_PIPES] = {};
1767 u32 hotplug_status = 0;
1770 gt_iir = I915_READ(GTIIR);
1771 pm_iir = I915_READ(GEN6_PMIIR);
1772 iir = I915_READ(VLV_IIR);
1774 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1780 * Theory on interrupt generation, based on empirical evidence:
1782 * x = ((VLV_IIR & VLV_IER) ||
1783 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1784 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1786 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1787 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1788 * guarantee the CPU interrupt will be raised again even if we
1789 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1790 * bits this time around.
1792 I915_WRITE(VLV_MASTER_IER, 0);
1793 ier = I915_READ(VLV_IER);
1794 I915_WRITE(VLV_IER, 0);
1797 I915_WRITE(GTIIR, gt_iir);
1799 I915_WRITE(GEN6_PMIIR, pm_iir);
1801 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1802 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1804 /* Call regardless, as some status bits might not be
1805 * signalled in iir */
1806 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1809 * VLV_IIR is single buffered, and reflects the level
1810 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1813 I915_WRITE(VLV_IIR, iir);
1815 I915_WRITE(VLV_IER, ier);
1816 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1817 POSTING_READ(VLV_MASTER_IER);
1820 snb_gt_irq_handler(dev_priv, gt_iir);
1822 gen6_rps_irq_handler(dev_priv, pm_iir);
1825 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1827 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1830 enable_rpm_wakeref_asserts(dev_priv);
1835 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1837 struct drm_device *dev = arg;
1838 struct drm_i915_private *dev_priv = dev->dev_private;
1839 irqreturn_t ret = IRQ_NONE;
1841 if (!intel_irqs_enabled(dev_priv))
1844 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1845 disable_rpm_wakeref_asserts(dev_priv);
1848 u32 master_ctl, iir;
1850 u32 pipe_stats[I915_MAX_PIPES] = {};
1851 u32 hotplug_status = 0;
1854 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1855 iir = I915_READ(VLV_IIR);
1857 if (master_ctl == 0 && iir == 0)
1863 * Theory on interrupt generation, based on empirical evidence:
1865 * x = ((VLV_IIR & VLV_IER) ||
1866 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1867 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1869 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1870 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1871 * guarantee the CPU interrupt will be raised again even if we
1872 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1873 * bits this time around.
1875 I915_WRITE(GEN8_MASTER_IRQ, 0);
1876 ier = I915_READ(VLV_IER);
1877 I915_WRITE(VLV_IER, 0);
1879 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1881 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1882 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1884 /* Call regardless, as some status bits might not be
1885 * signalled in iir */
1886 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1889 * VLV_IIR is single buffered, and reflects the level
1890 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1893 I915_WRITE(VLV_IIR, iir);
1895 I915_WRITE(VLV_IER, ier);
1896 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1897 POSTING_READ(GEN8_MASTER_IRQ);
1899 gen8_gt_irq_handler(dev_priv, gt_iir);
1902 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1904 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1907 enable_rpm_wakeref_asserts(dev_priv);
1912 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1913 u32 hotplug_trigger,
1914 const u32 hpd[HPD_NUM_PINS])
1916 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1919 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1920 * unless we touch the hotplug register, even if hotplug_trigger is
1921 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1924 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1925 if (!hotplug_trigger) {
1926 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1927 PORTD_HOTPLUG_STATUS_MASK |
1928 PORTC_HOTPLUG_STATUS_MASK |
1929 PORTB_HOTPLUG_STATUS_MASK;
1930 dig_hotplug_reg &= ~mask;
1933 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1934 if (!hotplug_trigger)
1937 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1938 dig_hotplug_reg, hpd,
1939 pch_port_hotplug_long_detect);
1941 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1944 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1947 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1949 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1951 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1952 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1953 SDE_AUDIO_POWER_SHIFT);
1954 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1958 if (pch_iir & SDE_AUX_MASK)
1959 dp_aux_irq_handler(dev_priv);
1961 if (pch_iir & SDE_GMBUS)
1962 gmbus_irq_handler(dev_priv);
1964 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1965 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1967 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1968 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1970 if (pch_iir & SDE_POISON)
1971 DRM_ERROR("PCH poison interrupt\n");
1973 if (pch_iir & SDE_FDI_MASK)
1974 for_each_pipe(dev_priv, pipe)
1975 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1977 I915_READ(FDI_RX_IIR(pipe)));
1979 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1980 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1982 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1983 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1985 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1986 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1988 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1989 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1992 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1994 u32 err_int = I915_READ(GEN7_ERR_INT);
1997 if (err_int & ERR_INT_POISON)
1998 DRM_ERROR("Poison interrupt\n");
2000 for_each_pipe(dev_priv, pipe) {
2001 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2002 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2004 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2005 if (IS_IVYBRIDGE(dev_priv))
2006 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2008 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2012 I915_WRITE(GEN7_ERR_INT, err_int);
2015 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2017 u32 serr_int = I915_READ(SERR_INT);
2019 if (serr_int & SERR_INT_POISON)
2020 DRM_ERROR("PCH poison interrupt\n");
2022 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2023 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2025 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2026 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2028 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2029 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2031 I915_WRITE(SERR_INT, serr_int);
2034 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2037 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2039 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2041 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2042 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2043 SDE_AUDIO_POWER_SHIFT_CPT);
2044 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2048 if (pch_iir & SDE_AUX_MASK_CPT)
2049 dp_aux_irq_handler(dev_priv);
2051 if (pch_iir & SDE_GMBUS_CPT)
2052 gmbus_irq_handler(dev_priv);
2054 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2055 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2057 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2058 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2060 if (pch_iir & SDE_FDI_MASK_CPT)
2061 for_each_pipe(dev_priv, pipe)
2062 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2064 I915_READ(FDI_RX_IIR(pipe)));
2066 if (pch_iir & SDE_ERROR_CPT)
2067 cpt_serr_int_handler(dev_priv);
2070 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2072 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2073 ~SDE_PORTE_HOTPLUG_SPT;
2074 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2075 u32 pin_mask = 0, long_mask = 0;
2077 if (hotplug_trigger) {
2078 u32 dig_hotplug_reg;
2080 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2081 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2083 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2084 dig_hotplug_reg, hpd_spt,
2085 spt_port_hotplug_long_detect);
2088 if (hotplug2_trigger) {
2089 u32 dig_hotplug_reg;
2091 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2092 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2094 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2095 dig_hotplug_reg, hpd_spt,
2096 spt_port_hotplug2_long_detect);
2100 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2102 if (pch_iir & SDE_GMBUS_CPT)
2103 gmbus_irq_handler(dev_priv);
2106 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2107 u32 hotplug_trigger,
2108 const u32 hpd[HPD_NUM_PINS])
2110 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2112 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2113 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2115 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2116 dig_hotplug_reg, hpd,
2117 ilk_port_hotplug_long_detect);
2119 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2122 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2126 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2128 if (hotplug_trigger)
2129 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2131 if (de_iir & DE_AUX_CHANNEL_A)
2132 dp_aux_irq_handler(dev_priv);
2134 if (de_iir & DE_GSE)
2135 intel_opregion_asle_intr(dev_priv);
2137 if (de_iir & DE_POISON)
2138 DRM_ERROR("Poison interrupt\n");
2140 for_each_pipe(dev_priv, pipe) {
2141 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2142 intel_pipe_handle_vblank(dev_priv, pipe))
2143 intel_check_page_flip(dev_priv, pipe);
2145 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2146 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2148 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2149 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2151 /* plane/pipes map 1:1 on ilk+ */
2152 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2153 intel_finish_page_flip_cs(dev_priv, pipe);
2156 /* check event from PCH */
2157 if (de_iir & DE_PCH_EVENT) {
2158 u32 pch_iir = I915_READ(SDEIIR);
2160 if (HAS_PCH_CPT(dev_priv))
2161 cpt_irq_handler(dev_priv, pch_iir);
2163 ibx_irq_handler(dev_priv, pch_iir);
2165 /* should clear PCH hotplug event before clear CPU irq */
2166 I915_WRITE(SDEIIR, pch_iir);
2169 if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2170 ironlake_rps_change_irq_handler(dev_priv);
2173 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2177 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2179 if (hotplug_trigger)
2180 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2182 if (de_iir & DE_ERR_INT_IVB)
2183 ivb_err_int_handler(dev_priv);
2185 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2186 dp_aux_irq_handler(dev_priv);
2188 if (de_iir & DE_GSE_IVB)
2189 intel_opregion_asle_intr(dev_priv);
2191 for_each_pipe(dev_priv, pipe) {
2192 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2193 intel_pipe_handle_vblank(dev_priv, pipe))
2194 intel_check_page_flip(dev_priv, pipe);
2196 /* plane/pipes map 1:1 on ilk+ */
2197 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2198 intel_finish_page_flip_cs(dev_priv, pipe);
2201 /* check event from PCH */
2202 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2203 u32 pch_iir = I915_READ(SDEIIR);
2205 cpt_irq_handler(dev_priv, pch_iir);
2207 /* clear PCH hotplug event before clear CPU irq */
2208 I915_WRITE(SDEIIR, pch_iir);
2213 * To handle irqs with the minimum potential races with fresh interrupts, we:
2214 * 1 - Disable Master Interrupt Control.
2215 * 2 - Find the source(s) of the interrupt.
2216 * 3 - Clear the Interrupt Identity bits (IIR).
2217 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2218 * 5 - Re-enable Master Interrupt Control.
2220 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2222 struct drm_device *dev = arg;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2225 irqreturn_t ret = IRQ_NONE;
2227 if (!intel_irqs_enabled(dev_priv))
2230 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2231 disable_rpm_wakeref_asserts(dev_priv);
2233 /* disable master interrupt before clearing iir */
2234 de_ier = I915_READ(DEIER);
2235 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2236 POSTING_READ(DEIER);
2238 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2239 * interrupts will will be stored on its back queue, and then we'll be
2240 * able to process them after we restore SDEIER (as soon as we restore
2241 * it, we'll get an interrupt if SDEIIR still has something to process
2242 * due to its back queue). */
2243 if (!HAS_PCH_NOP(dev_priv)) {
2244 sde_ier = I915_READ(SDEIER);
2245 I915_WRITE(SDEIER, 0);
2246 POSTING_READ(SDEIER);
2249 /* Find, clear, then process each source of interrupt */
2251 gt_iir = I915_READ(GTIIR);
2253 I915_WRITE(GTIIR, gt_iir);
2255 if (INTEL_GEN(dev_priv) >= 6)
2256 snb_gt_irq_handler(dev_priv, gt_iir);
2258 ilk_gt_irq_handler(dev_priv, gt_iir);
2261 de_iir = I915_READ(DEIIR);
2263 I915_WRITE(DEIIR, de_iir);
2265 if (INTEL_GEN(dev_priv) >= 7)
2266 ivb_display_irq_handler(dev_priv, de_iir);
2268 ilk_display_irq_handler(dev_priv, de_iir);
2271 if (INTEL_GEN(dev_priv) >= 6) {
2272 u32 pm_iir = I915_READ(GEN6_PMIIR);
2274 I915_WRITE(GEN6_PMIIR, pm_iir);
2276 gen6_rps_irq_handler(dev_priv, pm_iir);
2280 I915_WRITE(DEIER, de_ier);
2281 POSTING_READ(DEIER);
2282 if (!HAS_PCH_NOP(dev_priv)) {
2283 I915_WRITE(SDEIER, sde_ier);
2284 POSTING_READ(SDEIER);
2287 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2288 enable_rpm_wakeref_asserts(dev_priv);
2293 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2294 u32 hotplug_trigger,
2295 const u32 hpd[HPD_NUM_PINS])
2297 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2299 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2300 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2302 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2303 dig_hotplug_reg, hpd,
2304 bxt_port_hotplug_long_detect);
2306 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2310 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2312 irqreturn_t ret = IRQ_NONE;
2316 if (master_ctl & GEN8_DE_MISC_IRQ) {
2317 iir = I915_READ(GEN8_DE_MISC_IIR);
2319 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2321 if (iir & GEN8_DE_MISC_GSE)
2322 intel_opregion_asle_intr(dev_priv);
2324 DRM_ERROR("Unexpected DE Misc interrupt\n");
2327 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2330 if (master_ctl & GEN8_DE_PORT_IRQ) {
2331 iir = I915_READ(GEN8_DE_PORT_IIR);
2336 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2339 tmp_mask = GEN8_AUX_CHANNEL_A;
2340 if (INTEL_INFO(dev_priv)->gen >= 9)
2341 tmp_mask |= GEN9_AUX_CHANNEL_B |
2342 GEN9_AUX_CHANNEL_C |
2345 if (iir & tmp_mask) {
2346 dp_aux_irq_handler(dev_priv);
2350 if (IS_BROXTON(dev_priv)) {
2351 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2353 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2357 } else if (IS_BROADWELL(dev_priv)) {
2358 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2360 ilk_hpd_irq_handler(dev_priv,
2366 if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2367 gmbus_irq_handler(dev_priv);
2372 DRM_ERROR("Unexpected DE Port interrupt\n");
2375 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2378 for_each_pipe(dev_priv, pipe) {
2379 u32 flip_done, fault_errors;
2381 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2384 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2386 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2391 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2393 if (iir & GEN8_PIPE_VBLANK &&
2394 intel_pipe_handle_vblank(dev_priv, pipe))
2395 intel_check_page_flip(dev_priv, pipe);
2398 if (INTEL_INFO(dev_priv)->gen >= 9)
2399 flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2401 flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2404 intel_finish_page_flip_cs(dev_priv, pipe);
2406 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2407 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2409 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2410 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2413 if (INTEL_INFO(dev_priv)->gen >= 9)
2414 fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2416 fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2419 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2424 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2425 master_ctl & GEN8_DE_PCH_IRQ) {
2427 * FIXME(BDW): Assume for now that the new interrupt handling
2428 * scheme also closed the SDE interrupt handling race we've seen
2429 * on older pch-split platforms. But this needs testing.
2431 iir = I915_READ(SDEIIR);
2433 I915_WRITE(SDEIIR, iir);
2436 if (HAS_PCH_SPT(dev_priv))
2437 spt_irq_handler(dev_priv, iir);
2439 cpt_irq_handler(dev_priv, iir);
2442 * Like on previous PCH there seems to be something
2443 * fishy going on with forwarding PCH interrupts.
2445 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2452 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2454 struct drm_device *dev = arg;
2455 struct drm_i915_private *dev_priv = dev->dev_private;
2460 if (!intel_irqs_enabled(dev_priv))
2463 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2464 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2468 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2470 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2471 disable_rpm_wakeref_asserts(dev_priv);
2473 /* Find, clear, then process each source of interrupt */
2474 ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2475 gen8_gt_irq_handler(dev_priv, gt_iir);
2476 ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2478 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2479 POSTING_READ_FW(GEN8_MASTER_IRQ);
2481 enable_rpm_wakeref_asserts(dev_priv);
2486 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2489 * Notify all waiters for GPU completion events that reset state has
2490 * been changed, and that they need to restart their wait after
2491 * checking for potential errors (and bail out to drop locks if there is
2492 * a gpu reset pending so that i915_error_work_func can acquire them).
2495 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2496 wake_up_all(&dev_priv->gpu_error.wait_queue);
2498 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2499 wake_up_all(&dev_priv->pending_flip_queue);
2503 * i915_reset_and_wakeup - do process context error handling work
2504 * @dev_priv: i915 device private
2506 * Fire an error uevent so userspace can see that a hang or error
2509 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2511 struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2512 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2513 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2514 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2517 kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2520 * Note that there's only one work item which does gpu resets, so we
2521 * need not worry about concurrent gpu resets potentially incrementing
2522 * error->reset_counter twice. We only need to take care of another
2523 * racing irq/hangcheck declaring the gpu dead for a second time. A
2524 * quick check for that is good enough: schedule_work ensures the
2525 * correct ordering between hang detection and this work item, and since
2526 * the reset in-progress bit is only ever set by code outside of this
2527 * work we don't need to worry about any other races.
2529 if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2530 DRM_DEBUG_DRIVER("resetting chip\n");
2531 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2534 * In most cases it's guaranteed that we get here with an RPM
2535 * reference held, for example because there is a pending GPU
2536 * request that won't finish until the reset is done. This
2537 * isn't the case at least when we get here by doing a
2538 * simulated reset via debugs, so get an RPM reference.
2540 intel_runtime_pm_get(dev_priv);
2542 intel_prepare_reset(dev_priv);
2545 * All state reset _must_ be completed before we update the
2546 * reset counter, for otherwise waiters might miss the reset
2547 * pending state and not properly drop locks, resulting in
2548 * deadlocks with the reset work.
2550 ret = i915_reset(dev_priv);
2552 intel_finish_reset(dev_priv);
2554 intel_runtime_pm_put(dev_priv);
2557 kobject_uevent_env(kobj,
2558 KOBJ_CHANGE, reset_done_event);
2561 * Note: The wake_up also serves as a memory barrier so that
2562 * waiters see the update value of the reset counter atomic_t.
2564 wake_up_all(&dev_priv->gpu_error.reset_queue);
2568 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2570 uint32_t instdone[I915_NUM_INSTDONE_REG];
2571 u32 eir = I915_READ(EIR);
2577 pr_err("render error detected, EIR: 0x%08x\n", eir);
2579 i915_get_extra_instdone(dev_priv, instdone);
2581 if (IS_G4X(dev_priv)) {
2582 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2583 u32 ipeir = I915_READ(IPEIR_I965);
2585 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2586 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2587 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2588 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2589 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2590 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2591 I915_WRITE(IPEIR_I965, ipeir);
2592 POSTING_READ(IPEIR_I965);
2594 if (eir & GM45_ERROR_PAGE_TABLE) {
2595 u32 pgtbl_err = I915_READ(PGTBL_ER);
2596 pr_err("page table error\n");
2597 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2598 I915_WRITE(PGTBL_ER, pgtbl_err);
2599 POSTING_READ(PGTBL_ER);
2603 if (!IS_GEN2(dev_priv)) {
2604 if (eir & I915_ERROR_PAGE_TABLE) {
2605 u32 pgtbl_err = I915_READ(PGTBL_ER);
2606 pr_err("page table error\n");
2607 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
2608 I915_WRITE(PGTBL_ER, pgtbl_err);
2609 POSTING_READ(PGTBL_ER);
2613 if (eir & I915_ERROR_MEMORY_REFRESH) {
2614 pr_err("memory refresh error:\n");
2615 for_each_pipe(dev_priv, pipe)
2616 pr_err("pipe %c stat: 0x%08x\n",
2617 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2618 /* pipestat has already been acked */
2620 if (eir & I915_ERROR_INSTRUCTION) {
2621 pr_err("instruction error\n");
2622 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
2623 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2624 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2625 if (INTEL_GEN(dev_priv) < 4) {
2626 u32 ipeir = I915_READ(IPEIR);
2628 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2629 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
2630 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
2631 I915_WRITE(IPEIR, ipeir);
2632 POSTING_READ(IPEIR);
2634 u32 ipeir = I915_READ(IPEIR_I965);
2636 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2637 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2638 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
2639 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2640 I915_WRITE(IPEIR_I965, ipeir);
2641 POSTING_READ(IPEIR_I965);
2645 I915_WRITE(EIR, eir);
2647 eir = I915_READ(EIR);
2650 * some errors might have become stuck,
2653 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2654 I915_WRITE(EMR, I915_READ(EMR) | eir);
2655 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2660 * i915_handle_error - handle a gpu error
2661 * @dev_priv: i915 device private
2662 * @engine_mask: mask representing engines that are hung
2663 * Do some basic checking of register state at error time and
2664 * dump it to the syslog. Also call i915_capture_error_state() to make
2665 * sure we get a record and make it available in debugfs. Fire a uevent
2666 * so userspace knows something bad happened (should trigger collection
2667 * of a ring dump etc.).
2668 * @fmt: Error message format string
2670 void i915_handle_error(struct drm_i915_private *dev_priv,
2672 const char *fmt, ...)
2677 va_start(args, fmt);
2678 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2681 i915_capture_error_state(dev_priv, engine_mask, error_msg);
2682 i915_report_and_clear_eir(dev_priv);
2685 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2686 &dev_priv->gpu_error.reset_counter);
2689 * Wakeup waiting processes so that the reset function
2690 * i915_reset_and_wakeup doesn't deadlock trying to grab
2691 * various locks. By bumping the reset counter first, the woken
2692 * processes will see a reset in progress and back off,
2693 * releasing their locks and then wait for the reset completion.
2694 * We must do this for _all_ gpu waiters that might hold locks
2695 * that the reset work needs to acquire.
2697 * Note: The wake_up serves as the required memory barrier to
2698 * ensure that the waiters see the updated value of the reset
2701 i915_error_wake_up(dev_priv);
2704 i915_reset_and_wakeup(dev_priv);
2707 /* Called from drm generic code, passed 'crtc' which
2708 * we use as a pipe index
2710 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2712 struct drm_i915_private *dev_priv = dev->dev_private;
2713 unsigned long irqflags;
2715 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2716 if (INTEL_INFO(dev)->gen >= 4)
2717 i915_enable_pipestat(dev_priv, pipe,
2718 PIPE_START_VBLANK_INTERRUPT_STATUS);
2720 i915_enable_pipestat(dev_priv, pipe,
2721 PIPE_VBLANK_INTERRUPT_STATUS);
2722 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2727 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 unsigned long irqflags;
2731 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2732 DE_PIPE_VBLANK(pipe);
2734 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2735 ilk_enable_display_irq(dev_priv, bit);
2736 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2741 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 unsigned long irqflags;
2746 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2747 i915_enable_pipestat(dev_priv, pipe,
2748 PIPE_START_VBLANK_INTERRUPT_STATUS);
2749 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2754 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 unsigned long irqflags;
2759 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2760 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2761 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2766 /* Called from drm generic code, passed 'crtc' which
2767 * we use as a pipe index
2769 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 unsigned long irqflags;
2774 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2775 i915_disable_pipestat(dev_priv, pipe,
2776 PIPE_VBLANK_INTERRUPT_STATUS |
2777 PIPE_START_VBLANK_INTERRUPT_STATUS);
2778 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2781 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 unsigned long irqflags;
2785 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2786 DE_PIPE_VBLANK(pipe);
2788 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2789 ilk_disable_display_irq(dev_priv, bit);
2790 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2793 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 unsigned long irqflags;
2798 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2799 i915_disable_pipestat(dev_priv, pipe,
2800 PIPE_START_VBLANK_INTERRUPT_STATUS);
2801 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2804 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2806 struct drm_i915_private *dev_priv = dev->dev_private;
2807 unsigned long irqflags;
2809 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2810 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2811 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2815 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2817 return i915_seqno_passed(seqno,
2818 READ_ONCE(engine->last_submitted_seqno));
2822 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2824 if (INTEL_GEN(engine->i915) >= 8) {
2825 return (ipehr >> 23) == 0x1c;
2827 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2828 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2829 MI_SEMAPHORE_REGISTER);
2833 static struct intel_engine_cs *
2834 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2837 struct drm_i915_private *dev_priv = engine->i915;
2838 struct intel_engine_cs *signaller;
2840 if (INTEL_GEN(dev_priv) >= 8) {
2841 for_each_engine(signaller, dev_priv) {
2842 if (engine == signaller)
2845 if (offset == signaller->semaphore.signal_ggtt[engine->id])
2849 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2851 for_each_engine(signaller, dev_priv) {
2852 if(engine == signaller)
2855 if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2860 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2861 engine->id, ipehr, offset);
2866 static struct intel_engine_cs *
2867 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2869 struct drm_i915_private *dev_priv = engine->i915;
2870 u32 cmd, ipehr, head;
2875 * This function does not support execlist mode - any attempt to
2876 * proceed further into this function will result in a kernel panic
2877 * when dereferencing ring->buffer, which is not set up in execlist
2880 * The correct way of doing it would be to derive the currently
2881 * executing ring buffer from the current context, which is derived
2882 * from the currently running request. Unfortunately, to get the
2883 * current request we would have to grab the struct_mutex before doing
2884 * anything else, which would be ill-advised since some other thread
2885 * might have grabbed it already and managed to hang itself, causing
2886 * the hang checker to deadlock.
2888 * Therefore, this function does not support execlist mode in its
2889 * current form. Just return NULL and move on.
2891 if (engine->buffer == NULL)
2894 ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2895 if (!ipehr_is_semaphore_wait(engine, ipehr))
2899 * HEAD is likely pointing to the dword after the actual command,
2900 * so scan backwards until we find the MBOX. But limit it to just 3
2901 * or 4 dwords depending on the semaphore wait command size.
2902 * Note that we don't care about ACTHD here since that might
2903 * point at at batch, and semaphores are always emitted into the
2904 * ringbuffer itself.
2906 head = I915_READ_HEAD(engine) & HEAD_ADDR;
2907 backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2909 for (i = backwards; i; --i) {
2911 * Be paranoid and presume the hw has gone off into the wild -
2912 * our ring is smaller than what the hardware (and hence
2913 * HEAD_ADDR) allows. Also handles wrap-around.
2915 head &= engine->buffer->size - 1;
2917 /* This here seems to blow up */
2918 cmd = ioread32(engine->buffer->virtual_start + head);
2928 *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2929 if (INTEL_GEN(dev_priv) >= 8) {
2930 offset = ioread32(engine->buffer->virtual_start + head + 12);
2932 offset = ioread32(engine->buffer->virtual_start + head + 8);
2934 return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2937 static int semaphore_passed(struct intel_engine_cs *engine)
2939 struct drm_i915_private *dev_priv = engine->i915;
2940 struct intel_engine_cs *signaller;
2943 engine->hangcheck.deadlock++;
2945 signaller = semaphore_waits_for(engine, &seqno);
2946 if (signaller == NULL)
2949 /* Prevent pathological recursion due to driver bugs */
2950 if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2953 if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2956 /* cursory check for an unkickable deadlock */
2957 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2958 semaphore_passed(signaller) < 0)
2964 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2966 struct intel_engine_cs *engine;
2968 for_each_engine(engine, dev_priv)
2969 engine->hangcheck.deadlock = 0;
2972 static bool subunits_stuck(struct intel_engine_cs *engine)
2974 u32 instdone[I915_NUM_INSTDONE_REG];
2978 if (engine->id != RCS)
2981 i915_get_extra_instdone(engine->i915, instdone);
2983 /* There might be unstable subunit states even when
2984 * actual head is not moving. Filter out the unstable ones by
2985 * accumulating the undone -> done transitions and only
2986 * consider those as progress.
2989 for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2990 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2992 if (tmp != engine->hangcheck.instdone[i])
2995 engine->hangcheck.instdone[i] |= tmp;
3001 static enum intel_ring_hangcheck_action
3002 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3004 if (acthd != engine->hangcheck.acthd) {
3006 /* Clear subunit states on head movement */
3007 memset(engine->hangcheck.instdone, 0,
3008 sizeof(engine->hangcheck.instdone));
3010 return HANGCHECK_ACTIVE;
3013 if (!subunits_stuck(engine))
3014 return HANGCHECK_ACTIVE;
3016 return HANGCHECK_HUNG;
3019 static enum intel_ring_hangcheck_action
3020 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3022 struct drm_i915_private *dev_priv = engine->i915;
3023 enum intel_ring_hangcheck_action ha;
3026 ha = head_stuck(engine, acthd);
3027 if (ha != HANGCHECK_HUNG)
3030 if (IS_GEN2(dev_priv))
3031 return HANGCHECK_HUNG;
3033 /* Is the chip hanging on a WAIT_FOR_EVENT?
3034 * If so we can simply poke the RB_WAIT bit
3035 * and break the hang. This should work on
3036 * all but the second generation chipsets.
3038 tmp = I915_READ_CTL(engine);
3039 if (tmp & RING_WAIT) {
3040 i915_handle_error(dev_priv, 0,
3041 "Kicking stuck wait on %s",
3043 I915_WRITE_CTL(engine, tmp);
3044 return HANGCHECK_KICK;
3047 if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3048 switch (semaphore_passed(engine)) {
3050 return HANGCHECK_HUNG;
3052 i915_handle_error(dev_priv, 0,
3053 "Kicking stuck semaphore on %s",
3055 I915_WRITE_CTL(engine, tmp);
3056 return HANGCHECK_KICK;
3058 return HANGCHECK_WAIT;
3062 return HANGCHECK_HUNG;
3065 static unsigned kick_waiters(struct intel_engine_cs *engine)
3067 struct drm_i915_private *i915 = engine->i915;
3068 unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3070 if (engine->hangcheck.user_interrupts == user_interrupts &&
3071 !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3072 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3073 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3076 intel_engine_enable_fake_irq(engine);
3079 return user_interrupts;
3082 * This is called when the chip hasn't reported back with completed
3083 * batchbuffers in a long time. We keep track per ring seqno progress and
3084 * if there are no progress, hangcheck score for that ring is increased.
3085 * Further, acthd is inspected to see if the ring is stuck. On stuck case
3086 * we kick the ring. If we see no progress on three subsequent calls
3087 * we assume chip is wedged and try to fix it by resetting the chip.
3089 static void i915_hangcheck_elapsed(struct work_struct *work)
3091 struct drm_i915_private *dev_priv =
3092 container_of(work, typeof(*dev_priv),
3093 gpu_error.hangcheck_work.work);
3094 struct intel_engine_cs *engine;
3095 enum intel_engine_id id;
3096 int busy_count = 0, rings_hung = 0;
3097 bool stuck[I915_NUM_ENGINES] = { 0 };
3101 #define ACTIVE_DECAY 15
3103 if (!i915.enable_hangcheck)
3107 * The hangcheck work is synced during runtime suspend, we don't
3108 * require a wakeref. TODO: instead of disabling the asserts make
3109 * sure that we hold a reference when this work is running.
3111 DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3113 /* As enabling the GPU requires fairly extensive mmio access,
3114 * periodically arm the mmio checker to see if we are triggering
3115 * any invalid access.
3117 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3119 for_each_engine_id(engine, dev_priv, id) {
3120 bool busy = intel_engine_has_waiter(engine);
3123 unsigned user_interrupts;
3125 semaphore_clear_deadlocks(dev_priv);
3127 /* We don't strictly need an irq-barrier here, as we are not
3128 * serving an interrupt request, be paranoid in case the
3129 * barrier has side-effects (such as preventing a broken
3130 * cacheline snoop) and so be sure that we can see the seqno
3131 * advance. If the seqno should stick, due to a stale
3132 * cacheline, we would erroneously declare the GPU hung.
3134 if (engine->irq_seqno_barrier)
3135 engine->irq_seqno_barrier(engine);
3137 acthd = intel_ring_get_active_head(engine);
3138 seqno = intel_engine_get_seqno(engine);
3140 /* Reset stuck interrupts between batch advances */
3141 user_interrupts = 0;
3143 if (engine->hangcheck.seqno == seqno) {
3144 if (ring_idle(engine, seqno)) {
3145 engine->hangcheck.action = HANGCHECK_IDLE;
3147 /* Safeguard against driver failure */
3148 user_interrupts = kick_waiters(engine);
3149 engine->hangcheck.score += BUSY;
3152 /* We always increment the hangcheck score
3153 * if the ring is busy and still processing
3154 * the same request, so that no single request
3155 * can run indefinitely (such as a chain of
3156 * batches). The only time we do not increment
3157 * the hangcheck score on this ring, if this
3158 * ring is in a legitimate wait for another
3159 * ring. In that case the waiting ring is a
3160 * victim and we want to be sure we catch the
3161 * right culprit. Then every time we do kick
3162 * the ring, add a small increment to the
3163 * score so that we can catch a batch that is
3164 * being repeatedly kicked and so responsible
3165 * for stalling the machine.
3167 engine->hangcheck.action = ring_stuck(engine,
3170 switch (engine->hangcheck.action) {
3171 case HANGCHECK_IDLE:
3172 case HANGCHECK_WAIT:
3174 case HANGCHECK_ACTIVE:
3175 engine->hangcheck.score += BUSY;
3177 case HANGCHECK_KICK:
3178 engine->hangcheck.score += KICK;
3180 case HANGCHECK_HUNG:
3181 engine->hangcheck.score += HUNG;
3187 engine->hangcheck.action = HANGCHECK_ACTIVE;
3189 /* Gradually reduce the count so that we catch DoS
3190 * attempts across multiple batches.
3192 if (engine->hangcheck.score > 0)
3193 engine->hangcheck.score -= ACTIVE_DECAY;
3194 if (engine->hangcheck.score < 0)
3195 engine->hangcheck.score = 0;
3197 /* Clear head and subunit states on seqno movement */
3200 memset(engine->hangcheck.instdone, 0,
3201 sizeof(engine->hangcheck.instdone));
3204 engine->hangcheck.seqno = seqno;
3205 engine->hangcheck.acthd = acthd;
3206 engine->hangcheck.user_interrupts = user_interrupts;
3210 for_each_engine_id(engine, dev_priv, id) {
3211 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3212 DRM_INFO("%s on %s\n",
3213 stuck[id] ? "stuck" : "no progress",
3215 rings_hung |= intel_engine_flag(engine);
3220 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3224 /* Reset timer in case GPU hangs without another request being added */
3226 i915_queue_hangcheck(dev_priv);
3229 ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3232 static void ibx_irq_reset(struct drm_device *dev)
3234 struct drm_i915_private *dev_priv = dev->dev_private;
3236 if (HAS_PCH_NOP(dev))
3239 GEN5_IRQ_RESET(SDE);
3241 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3242 I915_WRITE(SERR_INT, 0xffffffff);
3246 * SDEIER is also touched by the interrupt handler to work around missed PCH
3247 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3248 * instead we unconditionally enable all PCH interrupt sources here, but then
3249 * only unmask them as needed with SDEIMR.
3251 * This function needs to be called before interrupts are enabled.
3253 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3255 struct drm_i915_private *dev_priv = dev->dev_private;
3257 if (HAS_PCH_NOP(dev))
3260 WARN_ON(I915_READ(SDEIER) != 0);
3261 I915_WRITE(SDEIER, 0xffffffff);
3262 POSTING_READ(SDEIER);
3265 static void gen5_gt_irq_reset(struct drm_device *dev)
3267 struct drm_i915_private *dev_priv = dev->dev_private;
3270 if (INTEL_INFO(dev)->gen >= 6)
3271 GEN5_IRQ_RESET(GEN6_PM);
3274 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3278 if (IS_CHERRYVIEW(dev_priv))
3279 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3281 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3283 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3284 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3286 for_each_pipe(dev_priv, pipe) {
3287 I915_WRITE(PIPESTAT(pipe),
3288 PIPE_FIFO_UNDERRUN_STATUS |
3289 PIPESTAT_INT_STATUS_MASK);
3290 dev_priv->pipestat_irq_mask[pipe] = 0;
3293 GEN5_IRQ_RESET(VLV_);
3294 dev_priv->irq_mask = ~0;
3297 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3303 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3304 PIPE_CRC_DONE_INTERRUPT_STATUS;
3306 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3307 for_each_pipe(dev_priv, pipe)
3308 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3310 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3311 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3312 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3313 if (IS_CHERRYVIEW(dev_priv))
3314 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3316 WARN_ON(dev_priv->irq_mask != ~0);
3318 dev_priv->irq_mask = ~enable_mask;
3320 GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3325 static void ironlake_irq_reset(struct drm_device *dev)
3327 struct drm_i915_private *dev_priv = dev->dev_private;
3329 I915_WRITE(HWSTAM, 0xffffffff);
3333 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3335 gen5_gt_irq_reset(dev);
3340 static void valleyview_irq_preinstall(struct drm_device *dev)
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3344 I915_WRITE(VLV_MASTER_IER, 0);
3345 POSTING_READ(VLV_MASTER_IER);
3347 gen5_gt_irq_reset(dev);
3349 spin_lock_irq(&dev_priv->irq_lock);
3350 if (dev_priv->display_irqs_enabled)
3351 vlv_display_irq_reset(dev_priv);
3352 spin_unlock_irq(&dev_priv->irq_lock);
3355 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3357 GEN8_IRQ_RESET_NDX(GT, 0);
3358 GEN8_IRQ_RESET_NDX(GT, 1);
3359 GEN8_IRQ_RESET_NDX(GT, 2);
3360 GEN8_IRQ_RESET_NDX(GT, 3);
3363 static void gen8_irq_reset(struct drm_device *dev)
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3368 I915_WRITE(GEN8_MASTER_IRQ, 0);
3369 POSTING_READ(GEN8_MASTER_IRQ);
3371 gen8_gt_irq_reset(dev_priv);
3373 for_each_pipe(dev_priv, pipe)
3374 if (intel_display_power_is_enabled(dev_priv,
3375 POWER_DOMAIN_PIPE(pipe)))
3376 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3378 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3379 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3380 GEN5_IRQ_RESET(GEN8_PCU_);
3382 if (HAS_PCH_SPLIT(dev))
3386 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3387 unsigned int pipe_mask)
3389 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3392 spin_lock_irq(&dev_priv->irq_lock);
3393 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3394 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3395 dev_priv->de_irq_mask[pipe],
3396 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3397 spin_unlock_irq(&dev_priv->irq_lock);
3400 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3401 unsigned int pipe_mask)
3405 spin_lock_irq(&dev_priv->irq_lock);
3406 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3407 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3408 spin_unlock_irq(&dev_priv->irq_lock);
3410 /* make sure we're done processing display irqs */
3411 synchronize_irq(dev_priv->dev->irq);
3414 static void cherryview_irq_preinstall(struct drm_device *dev)
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3418 I915_WRITE(GEN8_MASTER_IRQ, 0);
3419 POSTING_READ(GEN8_MASTER_IRQ);
3421 gen8_gt_irq_reset(dev_priv);
3423 GEN5_IRQ_RESET(GEN8_PCU_);
3425 spin_lock_irq(&dev_priv->irq_lock);
3426 if (dev_priv->display_irqs_enabled)
3427 vlv_display_irq_reset(dev_priv);
3428 spin_unlock_irq(&dev_priv->irq_lock);
3431 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3432 const u32 hpd[HPD_NUM_PINS])
3434 struct intel_encoder *encoder;
3435 u32 enabled_irqs = 0;
3437 for_each_intel_encoder(dev_priv->dev, encoder)
3438 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3439 enabled_irqs |= hpd[encoder->hpd_pin];
3441 return enabled_irqs;
3444 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3446 u32 hotplug_irqs, hotplug, enabled_irqs;
3448 if (HAS_PCH_IBX(dev_priv)) {
3449 hotplug_irqs = SDE_HOTPLUG_MASK;
3450 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3452 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3453 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3456 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3459 * Enable digital hotplug on the PCH, and configure the DP short pulse
3460 * duration to 2ms (which is the minimum in the Display Port spec).
3461 * The pulse duration bits are reserved on LPT+.
3463 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3464 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3465 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3466 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3467 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3469 * When CPU and PCH are on the same package, port A
3470 * HPD must be enabled in both north and south.
3472 if (HAS_PCH_LPT_LP(dev_priv))
3473 hotplug |= PORTA_HOTPLUG_ENABLE;
3474 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3477 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3479 u32 hotplug_irqs, hotplug, enabled_irqs;
3481 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3482 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3484 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3486 /* Enable digital hotplug on the PCH */
3487 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3488 hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3489 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3490 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3492 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3493 hotplug |= PORTE_HOTPLUG_ENABLE;
3494 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3497 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3499 u32 hotplug_irqs, hotplug, enabled_irqs;
3501 if (INTEL_GEN(dev_priv) >= 8) {
3502 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3503 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3505 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3506 } else if (INTEL_GEN(dev_priv) >= 7) {
3507 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3508 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3510 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3512 hotplug_irqs = DE_DP_A_HOTPLUG;
3513 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3515 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3519 * Enable digital hotplug on the CPU, and configure the DP short pulse
3520 * duration to 2ms (which is the minimum in the Display Port spec)
3521 * The pulse duration bits are reserved on HSW+.
3523 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3524 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3525 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3526 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3528 ibx_hpd_irq_setup(dev_priv);
3531 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3533 u32 hotplug_irqs, hotplug, enabled_irqs;
3535 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3536 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3538 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3540 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3541 hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3542 PORTA_HOTPLUG_ENABLE;
3544 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3545 hotplug, enabled_irqs);
3546 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3549 * For BXT invert bit has to be set based on AOB design
3550 * for HPD detection logic, update it based on VBT fields.
3553 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3554 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3555 hotplug |= BXT_DDIA_HPD_INVERT;
3556 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3557 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3558 hotplug |= BXT_DDIB_HPD_INVERT;
3559 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3560 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3561 hotplug |= BXT_DDIC_HPD_INVERT;
3563 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3566 static void ibx_irq_postinstall(struct drm_device *dev)
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3571 if (HAS_PCH_NOP(dev))
3574 if (HAS_PCH_IBX(dev))
3575 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3577 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3579 gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3580 I915_WRITE(SDEIMR, ~mask);
3583 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 u32 pm_irqs, gt_irqs;
3588 pm_irqs = gt_irqs = 0;
3590 dev_priv->gt_irq_mask = ~0;
3591 if (HAS_L3_DPF(dev)) {
3592 /* L3 parity interrupt is always unmasked. */
3593 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3594 gt_irqs |= GT_PARITY_ERROR(dev);
3597 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3599 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3601 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3604 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3606 if (INTEL_INFO(dev)->gen >= 6) {
3608 * RPS interrupts will get enabled/disabled on demand when RPS
3609 * itself is enabled/disabled.
3612 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3614 dev_priv->pm_irq_mask = 0xffffffff;
3615 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3619 static int ironlake_irq_postinstall(struct drm_device *dev)
3621 struct drm_i915_private *dev_priv = dev->dev_private;
3622 u32 display_mask, extra_mask;
3624 if (INTEL_INFO(dev)->gen >= 7) {
3625 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3626 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3627 DE_PLANEB_FLIP_DONE_IVB |
3628 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3629 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3630 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3631 DE_DP_A_HOTPLUG_IVB);
3633 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3634 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3636 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3638 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3639 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3643 dev_priv->irq_mask = ~display_mask;
3645 I915_WRITE(HWSTAM, 0xeffe);
3647 ibx_irq_pre_postinstall(dev);
3649 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3651 gen5_gt_irq_postinstall(dev);
3653 ibx_irq_postinstall(dev);
3655 if (IS_IRONLAKE_M(dev)) {
3656 /* Enable PCU event interrupts
3658 * spinlocking not required here for correctness since interrupt
3659 * setup is guaranteed to run in single-threaded context. But we
3660 * need it to make the assert_spin_locked happy. */
3661 spin_lock_irq(&dev_priv->irq_lock);
3662 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3663 spin_unlock_irq(&dev_priv->irq_lock);
3669 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3671 assert_spin_locked(&dev_priv->irq_lock);
3673 if (dev_priv->display_irqs_enabled)
3676 dev_priv->display_irqs_enabled = true;
3678 if (intel_irqs_enabled(dev_priv)) {
3679 vlv_display_irq_reset(dev_priv);
3680 vlv_display_irq_postinstall(dev_priv);
3684 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3686 assert_spin_locked(&dev_priv->irq_lock);
3688 if (!dev_priv->display_irqs_enabled)
3691 dev_priv->display_irqs_enabled = false;
3693 if (intel_irqs_enabled(dev_priv))
3694 vlv_display_irq_reset(dev_priv);
3698 static int valleyview_irq_postinstall(struct drm_device *dev)
3700 struct drm_i915_private *dev_priv = dev->dev_private;
3702 gen5_gt_irq_postinstall(dev);
3704 spin_lock_irq(&dev_priv->irq_lock);
3705 if (dev_priv->display_irqs_enabled)
3706 vlv_display_irq_postinstall(dev_priv);
3707 spin_unlock_irq(&dev_priv->irq_lock);
3709 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3710 POSTING_READ(VLV_MASTER_IER);
3715 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3717 /* These are interrupts we'll toggle with the ring mask register */
3718 uint32_t gt_interrupts[] = {
3719 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3720 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3721 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3722 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3723 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3724 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3725 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3726 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3728 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3729 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3732 if (HAS_L3_DPF(dev_priv))
3733 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3735 dev_priv->pm_irq_mask = 0xffffffff;
3736 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3737 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3739 * RPS interrupts will get enabled/disabled on demand when RPS itself
3740 * is enabled/disabled.
3742 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3743 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3746 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3748 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3749 uint32_t de_pipe_enables;
3750 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3751 u32 de_port_enables;
3752 u32 de_misc_masked = GEN8_DE_MISC_GSE;
3755 if (INTEL_INFO(dev_priv)->gen >= 9) {
3756 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3757 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3758 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3760 if (IS_BROXTON(dev_priv))
3761 de_port_masked |= BXT_DE_PORT_GMBUS;
3763 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3764 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3767 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3768 GEN8_PIPE_FIFO_UNDERRUN;
3770 de_port_enables = de_port_masked;
3771 if (IS_BROXTON(dev_priv))
3772 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3773 else if (IS_BROADWELL(dev_priv))
3774 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3776 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3777 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3778 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3780 for_each_pipe(dev_priv, pipe)
3781 if (intel_display_power_is_enabled(dev_priv,
3782 POWER_DOMAIN_PIPE(pipe)))
3783 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3784 dev_priv->de_irq_mask[pipe],
3787 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3788 GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3791 static int gen8_irq_postinstall(struct drm_device *dev)
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3795 if (HAS_PCH_SPLIT(dev))
3796 ibx_irq_pre_postinstall(dev);
3798 gen8_gt_irq_postinstall(dev_priv);
3799 gen8_de_irq_postinstall(dev_priv);
3801 if (HAS_PCH_SPLIT(dev))
3802 ibx_irq_postinstall(dev);
3804 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3805 POSTING_READ(GEN8_MASTER_IRQ);
3810 static int cherryview_irq_postinstall(struct drm_device *dev)
3812 struct drm_i915_private *dev_priv = dev->dev_private;
3814 gen8_gt_irq_postinstall(dev_priv);
3816 spin_lock_irq(&dev_priv->irq_lock);
3817 if (dev_priv->display_irqs_enabled)
3818 vlv_display_irq_postinstall(dev_priv);
3819 spin_unlock_irq(&dev_priv->irq_lock);
3821 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3822 POSTING_READ(GEN8_MASTER_IRQ);
3827 static void gen8_irq_uninstall(struct drm_device *dev)
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3834 gen8_irq_reset(dev);
3837 static void valleyview_irq_uninstall(struct drm_device *dev)
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3844 I915_WRITE(VLV_MASTER_IER, 0);
3845 POSTING_READ(VLV_MASTER_IER);
3847 gen5_gt_irq_reset(dev);
3849 I915_WRITE(HWSTAM, 0xffffffff);
3851 spin_lock_irq(&dev_priv->irq_lock);
3852 if (dev_priv->display_irqs_enabled)
3853 vlv_display_irq_reset(dev_priv);
3854 spin_unlock_irq(&dev_priv->irq_lock);
3857 static void cherryview_irq_uninstall(struct drm_device *dev)
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3864 I915_WRITE(GEN8_MASTER_IRQ, 0);
3865 POSTING_READ(GEN8_MASTER_IRQ);
3867 gen8_gt_irq_reset(dev_priv);
3869 GEN5_IRQ_RESET(GEN8_PCU_);
3871 spin_lock_irq(&dev_priv->irq_lock);
3872 if (dev_priv->display_irqs_enabled)
3873 vlv_display_irq_reset(dev_priv);
3874 spin_unlock_irq(&dev_priv->irq_lock);
3877 static void ironlake_irq_uninstall(struct drm_device *dev)
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3884 ironlake_irq_reset(dev);
3887 static void i8xx_irq_preinstall(struct drm_device * dev)
3889 struct drm_i915_private *dev_priv = dev->dev_private;
3892 for_each_pipe(dev_priv, pipe)
3893 I915_WRITE(PIPESTAT(pipe), 0);
3894 I915_WRITE16(IMR, 0xffff);
3895 I915_WRITE16(IER, 0x0);
3896 POSTING_READ16(IER);
3899 static int i8xx_irq_postinstall(struct drm_device *dev)
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3904 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3906 /* Unmask the interrupts that we always want on. */
3907 dev_priv->irq_mask =
3908 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3909 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3910 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3911 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3912 I915_WRITE16(IMR, dev_priv->irq_mask);
3915 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3916 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3917 I915_USER_INTERRUPT);
3918 POSTING_READ16(IER);
3920 /* Interrupt setup is already guaranteed to be single-threaded, this is
3921 * just to make the assert_spin_locked check happy. */
3922 spin_lock_irq(&dev_priv->irq_lock);
3923 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3924 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3925 spin_unlock_irq(&dev_priv->irq_lock);
3931 * Returns true when a page flip has completed.
3933 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3934 int plane, int pipe, u32 iir)
3936 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3938 if (!intel_pipe_handle_vblank(dev_priv, pipe))
3941 if ((iir & flip_pending) == 0)
3942 goto check_page_flip;
3944 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3945 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3946 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3947 * the flip is completed (no longer pending). Since this doesn't raise
3948 * an interrupt per se, we watch for the change at vblank.
3950 if (I915_READ16(ISR) & flip_pending)
3951 goto check_page_flip;
3953 intel_finish_page_flip_cs(dev_priv, pipe);
3957 intel_check_page_flip(dev_priv, pipe);
3961 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3963 struct drm_device *dev = arg;
3964 struct drm_i915_private *dev_priv = dev->dev_private;
3969 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3970 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3973 if (!intel_irqs_enabled(dev_priv))
3976 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3977 disable_rpm_wakeref_asserts(dev_priv);
3980 iir = I915_READ16(IIR);
3984 while (iir & ~flip_mask) {
3985 /* Can't rely on pipestat interrupt bit in iir as it might
3986 * have been cleared after the pipestat interrupt was received.
3987 * It doesn't set the bit in iir again, but it still produces
3988 * interrupts (for non-MSI).
3990 spin_lock(&dev_priv->irq_lock);
3991 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3992 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3994 for_each_pipe(dev_priv, pipe) {
3995 i915_reg_t reg = PIPESTAT(pipe);
3996 pipe_stats[pipe] = I915_READ(reg);
3999 * Clear the PIPE*STAT regs before the IIR
4001 if (pipe_stats[pipe] & 0x8000ffff)
4002 I915_WRITE(reg, pipe_stats[pipe]);
4004 spin_unlock(&dev_priv->irq_lock);
4006 I915_WRITE16(IIR, iir & ~flip_mask);
4007 new_iir = I915_READ16(IIR); /* Flush posted writes */
4009 if (iir & I915_USER_INTERRUPT)
4010 notify_ring(&dev_priv->engine[RCS]);
4012 for_each_pipe(dev_priv, pipe) {
4014 if (HAS_FBC(dev_priv))
4017 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4018 i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4019 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4021 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4022 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4024 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4025 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4034 enable_rpm_wakeref_asserts(dev_priv);
4039 static void i8xx_irq_uninstall(struct drm_device * dev)
4041 struct drm_i915_private *dev_priv = dev->dev_private;
4044 for_each_pipe(dev_priv, pipe) {
4045 /* Clear enable bits; then clear status bits */
4046 I915_WRITE(PIPESTAT(pipe), 0);
4047 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4049 I915_WRITE16(IMR, 0xffff);
4050 I915_WRITE16(IER, 0x0);
4051 I915_WRITE16(IIR, I915_READ16(IIR));
4054 static void i915_irq_preinstall(struct drm_device * dev)
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4059 if (I915_HAS_HOTPLUG(dev)) {
4060 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4061 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4064 I915_WRITE16(HWSTAM, 0xeffe);
4065 for_each_pipe(dev_priv, pipe)
4066 I915_WRITE(PIPESTAT(pipe), 0);
4067 I915_WRITE(IMR, 0xffffffff);
4068 I915_WRITE(IER, 0x0);
4072 static int i915_irq_postinstall(struct drm_device *dev)
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4077 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4079 /* Unmask the interrupts that we always want on. */
4080 dev_priv->irq_mask =
4081 ~(I915_ASLE_INTERRUPT |
4082 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4083 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4084 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4085 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4088 I915_ASLE_INTERRUPT |
4089 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4090 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4091 I915_USER_INTERRUPT;
4093 if (I915_HAS_HOTPLUG(dev)) {
4094 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4095 POSTING_READ(PORT_HOTPLUG_EN);
4097 /* Enable in IER... */
4098 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4099 /* and unmask in IMR */
4100 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4103 I915_WRITE(IMR, dev_priv->irq_mask);
4104 I915_WRITE(IER, enable_mask);
4107 i915_enable_asle_pipestat(dev_priv);
4109 /* Interrupt setup is already guaranteed to be single-threaded, this is
4110 * just to make the assert_spin_locked check happy. */
4111 spin_lock_irq(&dev_priv->irq_lock);
4112 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4113 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4114 spin_unlock_irq(&dev_priv->irq_lock);
4120 * Returns true when a page flip has completed.
4122 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4123 int plane, int pipe, u32 iir)
4125 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4127 if (!intel_pipe_handle_vblank(dev_priv, pipe))
4130 if ((iir & flip_pending) == 0)
4131 goto check_page_flip;
4133 /* We detect FlipDone by looking for the change in PendingFlip from '1'
4134 * to '0' on the following vblank, i.e. IIR has the Pendingflip
4135 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4136 * the flip is completed (no longer pending). Since this doesn't raise
4137 * an interrupt per se, we watch for the change at vblank.
4139 if (I915_READ(ISR) & flip_pending)
4140 goto check_page_flip;
4142 intel_finish_page_flip_cs(dev_priv, pipe);
4146 intel_check_page_flip(dev_priv, pipe);
4150 static irqreturn_t i915_irq_handler(int irq, void *arg)
4152 struct drm_device *dev = arg;
4153 struct drm_i915_private *dev_priv = dev->dev_private;
4154 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4156 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4157 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4158 int pipe, ret = IRQ_NONE;
4160 if (!intel_irqs_enabled(dev_priv))
4163 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4164 disable_rpm_wakeref_asserts(dev_priv);
4166 iir = I915_READ(IIR);
4168 bool irq_received = (iir & ~flip_mask) != 0;
4169 bool blc_event = false;
4171 /* Can't rely on pipestat interrupt bit in iir as it might
4172 * have been cleared after the pipestat interrupt was received.
4173 * It doesn't set the bit in iir again, but it still produces
4174 * interrupts (for non-MSI).
4176 spin_lock(&dev_priv->irq_lock);
4177 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4178 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4180 for_each_pipe(dev_priv, pipe) {
4181 i915_reg_t reg = PIPESTAT(pipe);
4182 pipe_stats[pipe] = I915_READ(reg);
4184 /* Clear the PIPE*STAT regs before the IIR */
4185 if (pipe_stats[pipe] & 0x8000ffff) {
4186 I915_WRITE(reg, pipe_stats[pipe]);
4187 irq_received = true;
4190 spin_unlock(&dev_priv->irq_lock);
4195 /* Consume port. Then clear IIR or we'll miss events */
4196 if (I915_HAS_HOTPLUG(dev_priv) &&
4197 iir & I915_DISPLAY_PORT_INTERRUPT) {
4198 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4200 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4203 I915_WRITE(IIR, iir & ~flip_mask);
4204 new_iir = I915_READ(IIR); /* Flush posted writes */
4206 if (iir & I915_USER_INTERRUPT)
4207 notify_ring(&dev_priv->engine[RCS]);
4209 for_each_pipe(dev_priv, pipe) {
4211 if (HAS_FBC(dev_priv))
4214 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4215 i915_handle_vblank(dev_priv, plane, pipe, iir))
4216 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4218 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4221 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4222 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4224 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4225 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4229 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4230 intel_opregion_asle_intr(dev_priv);
4232 /* With MSI, interrupts are only generated when iir
4233 * transitions from zero to nonzero. If another bit got
4234 * set while we were handling the existing iir bits, then
4235 * we would never get another interrupt.
4237 * This is fine on non-MSI as well, as if we hit this path
4238 * we avoid exiting the interrupt handler only to generate
4241 * Note that for MSI this could cause a stray interrupt report
4242 * if an interrupt landed in the time between writing IIR and
4243 * the posting read. This should be rare enough to never
4244 * trigger the 99% of 100,000 interrupts test for disabling
4249 } while (iir & ~flip_mask);
4251 enable_rpm_wakeref_asserts(dev_priv);
4256 static void i915_irq_uninstall(struct drm_device * dev)
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4261 if (I915_HAS_HOTPLUG(dev)) {
4262 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4263 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4266 I915_WRITE16(HWSTAM, 0xffff);
4267 for_each_pipe(dev_priv, pipe) {
4268 /* Clear enable bits; then clear status bits */
4269 I915_WRITE(PIPESTAT(pipe), 0);
4270 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4272 I915_WRITE(IMR, 0xffffffff);
4273 I915_WRITE(IER, 0x0);
4275 I915_WRITE(IIR, I915_READ(IIR));
4278 static void i965_irq_preinstall(struct drm_device * dev)
4280 struct drm_i915_private *dev_priv = dev->dev_private;
4283 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4284 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4286 I915_WRITE(HWSTAM, 0xeffe);
4287 for_each_pipe(dev_priv, pipe)
4288 I915_WRITE(PIPESTAT(pipe), 0);
4289 I915_WRITE(IMR, 0xffffffff);
4290 I915_WRITE(IER, 0x0);
4294 static int i965_irq_postinstall(struct drm_device *dev)
4296 struct drm_i915_private *dev_priv = dev->dev_private;
4300 /* Unmask the interrupts that we always want on. */
4301 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4302 I915_DISPLAY_PORT_INTERRUPT |
4303 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4304 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4305 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4306 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4307 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4309 enable_mask = ~dev_priv->irq_mask;
4310 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4311 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4312 enable_mask |= I915_USER_INTERRUPT;
4314 if (IS_G4X(dev_priv))
4315 enable_mask |= I915_BSD_USER_INTERRUPT;
4317 /* Interrupt setup is already guaranteed to be single-threaded, this is
4318 * just to make the assert_spin_locked check happy. */
4319 spin_lock_irq(&dev_priv->irq_lock);
4320 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4321 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4322 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4323 spin_unlock_irq(&dev_priv->irq_lock);
4326 * Enable some error detection, note the instruction error mask
4327 * bit is reserved, so we leave it masked.
4329 if (IS_G4X(dev_priv)) {
4330 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4331 GM45_ERROR_MEM_PRIV |
4332 GM45_ERROR_CP_PRIV |
4333 I915_ERROR_MEMORY_REFRESH);
4335 error_mask = ~(I915_ERROR_PAGE_TABLE |
4336 I915_ERROR_MEMORY_REFRESH);
4338 I915_WRITE(EMR, error_mask);
4340 I915_WRITE(IMR, dev_priv->irq_mask);
4341 I915_WRITE(IER, enable_mask);
4344 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4345 POSTING_READ(PORT_HOTPLUG_EN);
4347 i915_enable_asle_pipestat(dev_priv);
4352 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4356 assert_spin_locked(&dev_priv->irq_lock);
4358 /* Note HDMI and DP share hotplug bits */
4359 /* enable bits are the same for all generations */
4360 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4361 /* Programming the CRT detection parameters tends
4362 to generate a spurious hotplug event about three
4363 seconds later. So just do it once.
4365 if (IS_G4X(dev_priv))
4366 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4367 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4369 /* Ignore TV since it's buggy */
4370 i915_hotplug_interrupt_update_locked(dev_priv,
4371 HOTPLUG_INT_EN_MASK |
4372 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4373 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4377 static irqreturn_t i965_irq_handler(int irq, void *arg)
4379 struct drm_device *dev = arg;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4382 u32 pipe_stats[I915_MAX_PIPES];
4383 int ret = IRQ_NONE, pipe;
4385 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4386 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4388 if (!intel_irqs_enabled(dev_priv))
4391 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4392 disable_rpm_wakeref_asserts(dev_priv);
4394 iir = I915_READ(IIR);
4397 bool irq_received = (iir & ~flip_mask) != 0;
4398 bool blc_event = false;
4400 /* Can't rely on pipestat interrupt bit in iir as it might
4401 * have been cleared after the pipestat interrupt was received.
4402 * It doesn't set the bit in iir again, but it still produces
4403 * interrupts (for non-MSI).
4405 spin_lock(&dev_priv->irq_lock);
4406 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4407 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4409 for_each_pipe(dev_priv, pipe) {
4410 i915_reg_t reg = PIPESTAT(pipe);
4411 pipe_stats[pipe] = I915_READ(reg);
4414 * Clear the PIPE*STAT regs before the IIR
4416 if (pipe_stats[pipe] & 0x8000ffff) {
4417 I915_WRITE(reg, pipe_stats[pipe]);
4418 irq_received = true;
4421 spin_unlock(&dev_priv->irq_lock);
4428 /* Consume port. Then clear IIR or we'll miss events */
4429 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4430 u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4432 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4435 I915_WRITE(IIR, iir & ~flip_mask);
4436 new_iir = I915_READ(IIR); /* Flush posted writes */
4438 if (iir & I915_USER_INTERRUPT)
4439 notify_ring(&dev_priv->engine[RCS]);
4440 if (iir & I915_BSD_USER_INTERRUPT)
4441 notify_ring(&dev_priv->engine[VCS]);
4443 for_each_pipe(dev_priv, pipe) {
4444 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4445 i915_handle_vblank(dev_priv, pipe, pipe, iir))
4446 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4448 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4451 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4452 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4454 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4455 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4458 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4459 intel_opregion_asle_intr(dev_priv);
4461 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4462 gmbus_irq_handler(dev_priv);
4464 /* With MSI, interrupts are only generated when iir
4465 * transitions from zero to nonzero. If another bit got
4466 * set while we were handling the existing iir bits, then
4467 * we would never get another interrupt.
4469 * This is fine on non-MSI as well, as if we hit this path
4470 * we avoid exiting the interrupt handler only to generate
4473 * Note that for MSI this could cause a stray interrupt report
4474 * if an interrupt landed in the time between writing IIR and
4475 * the posting read. This should be rare enough to never
4476 * trigger the 99% of 100,000 interrupts test for disabling
4482 enable_rpm_wakeref_asserts(dev_priv);
4487 static void i965_irq_uninstall(struct drm_device * dev)
4489 struct drm_i915_private *dev_priv = dev->dev_private;
4495 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4496 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4498 I915_WRITE(HWSTAM, 0xffffffff);
4499 for_each_pipe(dev_priv, pipe)
4500 I915_WRITE(PIPESTAT(pipe), 0);
4501 I915_WRITE(IMR, 0xffffffff);
4502 I915_WRITE(IER, 0x0);
4504 for_each_pipe(dev_priv, pipe)
4505 I915_WRITE(PIPESTAT(pipe),
4506 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4507 I915_WRITE(IIR, I915_READ(IIR));
4511 * intel_irq_init - initializes irq support
4512 * @dev_priv: i915 device instance
4514 * This function initializes all the irq support including work items, timers
4515 * and all the vtables. It does not setup the interrupt itself though.
4517 void intel_irq_init(struct drm_i915_private *dev_priv)
4519 struct drm_device *dev = dev_priv->dev;
4521 intel_hpd_init_work(dev_priv);
4523 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4524 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4526 /* Let's track the enabled rps events */
4527 if (IS_VALLEYVIEW(dev_priv))
4528 /* WaGsvRC0ResidencyMethod:vlv */
4529 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4531 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4533 dev_priv->rps.pm_intr_keep = 0;
4536 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4537 * if GEN6_PM_UP_EI_EXPIRED is masked.
4539 * TODO: verify if this can be reproduced on VLV,CHV.
4541 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4542 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4544 if (INTEL_INFO(dev_priv)->gen >= 8)
4545 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4547 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4548 i915_hangcheck_elapsed);
4550 if (IS_GEN2(dev_priv)) {
4551 dev->max_vblank_count = 0;
4552 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4553 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4554 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4555 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4557 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4558 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4562 * Opt out of the vblank disable timer on everything except gen2.
4563 * Gen2 doesn't have a hardware frame counter and so depends on
4564 * vblank interrupts to produce sane vblank seuquence numbers.
4566 if (!IS_GEN2(dev_priv))
4567 dev->vblank_disable_immediate = true;
4569 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4570 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4572 if (IS_CHERRYVIEW(dev_priv)) {
4573 dev->driver->irq_handler = cherryview_irq_handler;
4574 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4575 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4576 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4577 dev->driver->enable_vblank = valleyview_enable_vblank;
4578 dev->driver->disable_vblank = valleyview_disable_vblank;
4579 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4580 } else if (IS_VALLEYVIEW(dev_priv)) {
4581 dev->driver->irq_handler = valleyview_irq_handler;
4582 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4583 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4584 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4585 dev->driver->enable_vblank = valleyview_enable_vblank;
4586 dev->driver->disable_vblank = valleyview_disable_vblank;
4587 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4588 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4589 dev->driver->irq_handler = gen8_irq_handler;
4590 dev->driver->irq_preinstall = gen8_irq_reset;
4591 dev->driver->irq_postinstall = gen8_irq_postinstall;
4592 dev->driver->irq_uninstall = gen8_irq_uninstall;
4593 dev->driver->enable_vblank = gen8_enable_vblank;
4594 dev->driver->disable_vblank = gen8_disable_vblank;
4595 if (IS_BROXTON(dev))
4596 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4597 else if (HAS_PCH_SPT(dev))
4598 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4600 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4601 } else if (HAS_PCH_SPLIT(dev)) {
4602 dev->driver->irq_handler = ironlake_irq_handler;
4603 dev->driver->irq_preinstall = ironlake_irq_reset;
4604 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4605 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4606 dev->driver->enable_vblank = ironlake_enable_vblank;
4607 dev->driver->disable_vblank = ironlake_disable_vblank;
4608 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4610 if (IS_GEN2(dev_priv)) {
4611 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4612 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4613 dev->driver->irq_handler = i8xx_irq_handler;
4614 dev->driver->irq_uninstall = i8xx_irq_uninstall;
4615 } else if (IS_GEN3(dev_priv)) {
4616 dev->driver->irq_preinstall = i915_irq_preinstall;
4617 dev->driver->irq_postinstall = i915_irq_postinstall;
4618 dev->driver->irq_uninstall = i915_irq_uninstall;
4619 dev->driver->irq_handler = i915_irq_handler;
4621 dev->driver->irq_preinstall = i965_irq_preinstall;
4622 dev->driver->irq_postinstall = i965_irq_postinstall;
4623 dev->driver->irq_uninstall = i965_irq_uninstall;
4624 dev->driver->irq_handler = i965_irq_handler;
4626 if (I915_HAS_HOTPLUG(dev_priv))
4627 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4628 dev->driver->enable_vblank = i915_enable_vblank;
4629 dev->driver->disable_vblank = i915_disable_vblank;
4634 * intel_irq_install - enables the hardware interrupt
4635 * @dev_priv: i915 device instance
4637 * This function enables the hardware interrupt handling, but leaves the hotplug
4638 * handling still disabled. It is called after intel_irq_init().
4640 * In the driver load and resume code we need working interrupts in a few places
4641 * but don't want to deal with the hassle of concurrent probe and hotplug
4642 * workers. Hence the split into this two-stage approach.
4644 int intel_irq_install(struct drm_i915_private *dev_priv)
4647 * We enable some interrupt sources in our postinstall hooks, so mark
4648 * interrupts as enabled _before_ actually enabling them to avoid
4649 * special cases in our ordering checks.
4651 dev_priv->pm.irqs_enabled = true;
4653 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4657 * intel_irq_uninstall - finilizes all irq handling
4658 * @dev_priv: i915 device instance
4660 * This stops interrupt and hotplug handling and unregisters and frees all
4661 * resources acquired in the init functions.
4663 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4665 drm_irq_uninstall(dev_priv->dev);
4666 intel_hpd_cancel_work(dev_priv);
4667 dev_priv->pm.irqs_enabled = false;
4671 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4672 * @dev_priv: i915 device instance
4674 * This function is used to disable interrupts at runtime, both in the runtime
4675 * pm and the system suspend/resume code.
4677 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4679 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4680 dev_priv->pm.irqs_enabled = false;
4681 synchronize_irq(dev_priv->dev->irq);
4685 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4686 * @dev_priv: i915 device instance
4688 * This function is used to enable interrupts at runtime, both in the runtime
4689 * pm and the system suspend/resume code.
4691 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4693 dev_priv->pm.irqs_enabled = true;
4694 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4695 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);