drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262 }
 263
 264 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 265 {
 266         ilk_update_gt_irq(dev_priv, mask, mask);
 267         POSTING_READ_FW(GTIMR);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         spin_lock_irq(&dev_priv->irq_lock);
 354
 355         WARN_ON(dev_priv->rps.pm_iir);
 356         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 357         dev_priv->rps.interrupts_enabled = true;
 358         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 359                                 dev_priv->pm_rps_events);
 360         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 361
 362         spin_unlock_irq(&dev_priv->irq_lock);
 363 }
 364
 365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 366 {
 367         return (mask & ~dev_priv->rps.pm_intr_keep);
 368 }
 369
 370 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         dev_priv->rps.interrupts_enabled = false;
 374         spin_unlock_irq(&dev_priv->irq_lock);
 375
 376         cancel_work_sync(&dev_priv->rps.work);
 377
 378         spin_lock_irq(&dev_priv->irq_lock);
 379
 380         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 381
 382         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 383         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 384                                 ~dev_priv->pm_rps_events);
 385
 386         spin_unlock_irq(&dev_priv->irq_lock);
 387
 388         synchronize_irq(dev_priv->dev->irq);
 389 }
 390
 391 /**
 392  * bdw_update_port_irq - update DE port interrupt
 393  * @dev_priv: driver private
 394  * @interrupt_mask: mask of interrupt bits to update
 395  * @enabled_irq_mask: mask of interrupt bits to enable
 396  */
 397 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 398                                 uint32_t interrupt_mask,
 399                                 uint32_t enabled_irq_mask)
 400 {
 401         uint32_t new_val;
 402         uint32_t old_val;
 403
 404         assert_spin_locked(&dev_priv->irq_lock);
 405
 406         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 407
 408         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 409                 return;
 410
 411         old_val = I915_READ(GEN8_DE_PORT_IMR);
 412
 413         new_val = old_val;
 414         new_val &= ~interrupt_mask;
 415         new_val |= (~enabled_irq_mask & interrupt_mask);
 416
 417         if (new_val != old_val) {
 418                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 419                 POSTING_READ(GEN8_DE_PORT_IMR);
 420         }
 421 }
 422
 423 /**
 424  * bdw_update_pipe_irq - update DE pipe interrupt
 425  * @dev_priv: driver private
 426  * @pipe: pipe whose interrupt to update
 427  * @interrupt_mask: mask of interrupt bits to update
 428  * @enabled_irq_mask: mask of interrupt bits to enable
 429  */
 430 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 431                          enum pipe pipe,
 432                          uint32_t interrupt_mask,
 433                          uint32_t enabled_irq_mask)
 434 {
 435         uint32_t new_val;
 436
 437         assert_spin_locked(&dev_priv->irq_lock);
 438
 439         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 440
 441         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 442                 return;
 443
 444         new_val = dev_priv->de_irq_mask[pipe];
 445         new_val &= ~interrupt_mask;
 446         new_val |= (~enabled_irq_mask & interrupt_mask);
 447
 448         if (new_val != dev_priv->de_irq_mask[pipe]) {
 449                 dev_priv->de_irq_mask[pipe] = new_val;
 450                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 451                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 452         }
 453 }
 454
 455 /**
 456  * ibx_display_interrupt_update - update SDEIMR
 457  * @dev_priv: driver private
 458  * @interrupt_mask: mask of interrupt bits to update
 459  * @enabled_irq_mask: mask of interrupt bits to enable
 460  */
 461 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 462                                   uint32_t interrupt_mask,
 463                                   uint32_t enabled_irq_mask)
 464 {
 465         uint32_t sdeimr = I915_READ(SDEIMR);
 466         sdeimr &= ~interrupt_mask;
 467         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 468
 469         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 470
 471         assert_spin_locked(&dev_priv->irq_lock);
 472
 473         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 474                 return;
 475
 476         I915_WRITE(SDEIMR, sdeimr);
 477         POSTING_READ(SDEIMR);
 478 }
 479
 480 static void
 481 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 482                        u32 enable_mask, u32 status_mask)
 483 {
 484         i915_reg_t reg = PIPESTAT(pipe);
 485         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 486
 487         assert_spin_locked(&dev_priv->irq_lock);
 488         WARN_ON(!intel_irqs_enabled(dev_priv));
 489
 490         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 491                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 492                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 493                       pipe_name(pipe), enable_mask, status_mask))
 494                 return;
 495
 496         if ((pipestat & enable_mask) == enable_mask)
 497                 return;
 498
 499         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 500
 501         /* Enable the interrupt, clear any pending status */
 502         pipestat |= enable_mask | status_mask;
 503         I915_WRITE(reg, pipestat);
 504         POSTING_READ(reg);
 505 }
 506
 507 static void
 508 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 509                         u32 enable_mask, u32 status_mask)
 510 {
 511         i915_reg_t reg = PIPESTAT(pipe);
 512         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 513
 514         assert_spin_locked(&dev_priv->irq_lock);
 515         WARN_ON(!intel_irqs_enabled(dev_priv));
 516
 517         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 518                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 519                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 520                       pipe_name(pipe), enable_mask, status_mask))
 521                 return;
 522
 523         if ((pipestat & enable_mask) == 0)
 524                 return;
 525
 526         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 527
 528         pipestat &= ~enable_mask;
 529         I915_WRITE(reg, pipestat);
 530         POSTING_READ(reg);
 531 }
 532
 533 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 534 {
 535         u32 enable_mask = status_mask << 16;
 536
 537         /*
 538          * On pipe A we don't support the PSR interrupt yet,
 539          * on pipe B and C the same bit MBZ.
 540          */
 541         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 542                 return 0;
 543         /*
 544          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 545          * A the same bit is for perf counters which we don't use either.
 546          */
 547         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 548                 return 0;
 549
 550         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 551                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 552                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 553         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 554                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 555         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 556                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 557
 558         return enable_mask;
 559 }
 560
 561 void
 562 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 563                      u32 status_mask)
 564 {
 565         u32 enable_mask;
 566
 567         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 568                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 569                                                            status_mask);
 570         else
 571                 enable_mask = status_mask << 16;
 572         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 573 }
 574
 575 void
 576 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 577                       u32 status_mask)
 578 {
 579         u32 enable_mask;
 580
 581         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 582                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 583                                                            status_mask);
 584         else
 585                 enable_mask = status_mask << 16;
 586         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 587 }
 588
 589 /**
 590  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 591  * @dev_priv: i915 device private
 592  */
 593 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 594 {
 595         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 596                 return;
 597
 598         spin_lock_irq(&dev_priv->irq_lock);
 599
 600         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 601         if (INTEL_GEN(dev_priv) >= 4)
 602                 i915_enable_pipestat(dev_priv, PIPE_A,
 603                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 604
 605         spin_unlock_irq(&dev_priv->irq_lock);
 606 }
 607
 608 /*
 609  * This timing diagram depicts the video signal in and
 610  * around the vertical blanking period.
 611  *
 612  * Assumptions about the fictitious mode used in this example:
 613  *  vblank_start >= 3
 614  *  vsync_start = vblank_start + 1
 615  *  vsync_end = vblank_start + 2
 616  *  vtotal = vblank_start + 3
 617  *
 618  *           start of vblank:
 619  *           latch double buffered registers
 620  *           increment frame counter (ctg+)
 621  *           generate start of vblank interrupt (gen4+)
 622  *           |
 623  *           |          frame start:
 624  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 625  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 626  *           |          |
 627  *           |          |  start of vsync:
 628  *           |          |  generate vsync interrupt
 629  *           |          |  |
 630  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 631  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 632  * ----va---> <-----------------vb--------------------> <--------va-------------
 633  *       |          |       <----vs----->                     |
 634  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 635  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 636  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 637  *       |          |                                         |
 638  *       last visible pixel                                   first visible pixel
 639  *                  |                                         increment frame counter (gen3/4)
 640  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 641  *
 642  * x  = horizontal active
 643  * _  = horizontal blanking
 644  * hs = horizontal sync
 645  * va = vertical active
 646  * vb = vertical blanking
 647  * vs = vertical sync
 648  * vbs = vblank_start (number)
 649  *
 650  * Summary:
 651  * - most events happen at the start of horizontal sync
 652  * - frame start happens at the start of horizontal blank, 1-4 lines
 653  *   (depending on PIPECONF settings) after the start of vblank
 654  * - gen3/4 pixel and frame counter are synchronized with the start
 655  *   of horizontal active on the first line of vertical active
 656  */
 657
 658 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 659 {
 660         /* Gen2 doesn't have a hardware frame counter */
 661         return 0;
 662 }
 663
 664 /* Called from drm generic code, passed a 'crtc', which
 665  * we use as a pipe index
 666  */
 667 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 668 {
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         i915_reg_t high_frame, low_frame;
 671         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 672         struct intel_crtc *intel_crtc =
 673                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 674         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 675
 676         htotal = mode->crtc_htotal;
 677         hsync_start = mode->crtc_hsync_start;
 678         vbl_start = mode->crtc_vblank_start;
 679         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 680                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 681
 682         /* Convert to pixel count */
 683         vbl_start *= htotal;
 684
 685         /* Start of vblank event occurs at start of hsync */
 686         vbl_start -= htotal - hsync_start;
 687
 688         high_frame = PIPEFRAME(pipe);
 689         low_frame = PIPEFRAMEPIXEL(pipe);
 690
 691         /*
 692          * High & low register fields aren't synchronized, so make sure
 693          * we get a low value that's stable across two reads of the high
 694          * register.
 695          */
 696         do {
 697                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 698                 low   = I915_READ(low_frame);
 699                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 700         } while (high1 != high2);
 701
 702         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 703         pixel = low & PIPE_PIXEL_MASK;
 704         low >>= PIPE_FRAME_LOW_SHIFT;
 705
 706         /*
 707          * The frame counter increments at beginning of active.
 708          * Cook up a vblank counter by also checking the pixel
 709          * counter against vblank start.
 710          */
 711         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 712 }
 713
 714 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 715 {
 716         struct drm_i915_private *dev_priv = dev->dev_private;
 717
 718         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 719 }
 720
 721 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 722 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 723 {
 724         struct drm_device *dev = crtc->base.dev;
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         const struct drm_display_mode *mode = &crtc->base.hwmode;
 727         enum pipe pipe = crtc->pipe;
 728         int position, vtotal;
 729
 730         vtotal = mode->crtc_vtotal;
 731         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 732                 vtotal /= 2;
 733
 734         if (IS_GEN2(dev_priv))
 735                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 736         else
 737                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 738
 739         /*
 740          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 741          * read it just before the start of vblank.  So try it again
 742          * so we don't accidentally end up spanning a vblank frame
 743          * increment, causing the pipe_update_end() code to squak at us.
 744          *
 745          * The nature of this problem means we can't simply check the ISR
 746          * bit and return the vblank start value; nor can we use the scanline
 747          * debug register in the transcoder as it appears to have the same
 748          * problem.  We may need to extend this to include other platforms,
 749          * but so far testing only shows the problem on HSW.
 750          */
 751         if (HAS_DDI(dev_priv) && !position) {
 752                 int i, temp;
 753
 754                 for (i = 0; i < 100; i++) {
 755                         udelay(1);
 756                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 757                                 DSL_LINEMASK_GEN3;
 758                         if (temp != position) {
 759                                 position = temp;
 760                                 break;
 761                         }
 762                 }
 763         }
 764
 765         /*
 766          * See update_scanline_offset() for the details on the
 767          * scanline_offset adjustment.
 768          */
 769         return (position + crtc->scanline_offset) % vtotal;
 770 }
 771
 772 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 773                                     unsigned int flags, int *vpos, int *hpos,
 774                                     ktime_t *stime, ktime_t *etime,
 775                                     const struct drm_display_mode *mode)
 776 {
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 780         int position;
 781         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 782         bool in_vbl = true;
 783         int ret = 0;
 784         unsigned long irqflags;
 785
 786         if (WARN_ON(!mode->crtc_clock)) {
 787                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 788                                  "pipe %c\n", pipe_name(pipe));
 789                 return 0;
 790         }
 791
 792         htotal = mode->crtc_htotal;
 793         hsync_start = mode->crtc_hsync_start;
 794         vtotal = mode->crtc_vtotal;
 795         vbl_start = mode->crtc_vblank_start;
 796         vbl_end = mode->crtc_vblank_end;
 797
 798         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 799                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 800                 vbl_end /= 2;
 801                 vtotal /= 2;
 802         }
 803
 804         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 805
 806         /*
 807          * Lock uncore.lock, as we will do multiple timing critical raw
 808          * register reads, potentially with preemption disabled, so the
 809          * following code must not block on uncore.lock.
 810          */
 811         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 812
 813         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 814
 815         /* Get optional system timestamp before query. */
 816         if (stime)
 817                 *stime = ktime_get();
 818
 819         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 820                 /* No obvious pixelcount register. Only query vertical
 821                  * scanout position from Display scan line register.
 822                  */
 823                 position = __intel_get_crtc_scanline(intel_crtc);
 824         } else {
 825                 /* Have access to pixelcount since start of frame.
 826                  * We can split this into vertical and horizontal
 827                  * scanout position.
 828                  */
 829                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 830
 831                 /* convert to pixel counts */
 832                 vbl_start *= htotal;
 833                 vbl_end *= htotal;
 834                 vtotal *= htotal;
 835
 836                 /*
 837                  * In interlaced modes, the pixel counter counts all pixels,
 838                  * so one field will have htotal more pixels. In order to avoid
 839                  * the reported position from jumping backwards when the pixel
 840                  * counter is beyond the length of the shorter field, just
 841                  * clamp the position the length of the shorter field. This
 842                  * matches how the scanline counter based position works since
 843                  * the scanline counter doesn't count the two half lines.
 844                  */
 845                 if (position >= vtotal)
 846                         position = vtotal - 1;
 847
 848                 /*
 849                  * Start of vblank interrupt is triggered at start of hsync,
 850                  * just prior to the first active line of vblank. However we
 851                  * consider lines to start at the leading edge of horizontal
 852                  * active. So, should we get here before we've crossed into
 853                  * the horizontal active of the first line in vblank, we would
 854                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 855                  * always add htotal-hsync_start to the current pixel position.
 856                  */
 857                 position = (position + htotal - hsync_start) % vtotal;
 858         }
 859
 860         /* Get optional system timestamp after query. */
 861         if (etime)
 862                 *etime = ktime_get();
 863
 864         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 865
 866         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 867
 868         in_vbl = position >= vbl_start && position < vbl_end;
 869
 870         /*
 871          * While in vblank, position will be negative
 872          * counting up towards 0 at vbl_end. And outside
 873          * vblank, position will be positive counting
 874          * up since vbl_end.
 875          */
 876         if (position >= vbl_start)
 877                 position -= vbl_end;
 878         else
 879                 position += vtotal - vbl_end;
 880
 881         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 882                 *vpos = position;
 883                 *hpos = 0;
 884         } else {
 885                 *vpos = position / htotal;
 886                 *hpos = position - (*vpos * htotal);
 887         }
 888
 889         /* In vblank? */
 890         if (in_vbl)
 891                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 892
 893         return ret;
 894 }
 895
 896 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 897 {
 898         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 899         unsigned long irqflags;
 900         int position;
 901
 902         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 903         position = __intel_get_crtc_scanline(crtc);
 904         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 905
 906         return position;
 907 }
 908
 909 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 910                               int *max_error,
 911                               struct timeval *vblank_time,
 912                               unsigned flags)
 913 {
 914         struct drm_crtc *crtc;
 915
 916         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 917                 DRM_ERROR("Invalid crtc %u\n", pipe);
 918                 return -EINVAL;
 919         }
 920
 921         /* Get drm_crtc to timestamp: */
 922         crtc = intel_get_crtc_for_pipe(dev, pipe);
 923         if (crtc == NULL) {
 924                 DRM_ERROR("Invalid crtc %u\n", pipe);
 925                 return -EINVAL;
 926         }
 927
 928         if (!crtc->hwmode.crtc_clock) {
 929                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 930                 return -EBUSY;
 931         }
 932
 933         /* Helper routine in DRM core does all the work: */
 934         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 935                                                      vblank_time, flags,
 936                                                      &crtc->hwmode);
 937 }
 938
 939 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 940 {
 941         u32 busy_up, busy_down, max_avg, min_avg;
 942         u8 new_delay;
 943
 944         spin_lock(&mchdev_lock);
 945
 946         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 947
 948         new_delay = dev_priv->ips.cur_delay;
 949
 950         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 951         busy_up = I915_READ(RCPREVBSYTUPAVG);
 952         busy_down = I915_READ(RCPREVBSYTDNAVG);
 953         max_avg = I915_READ(RCBMAXAVG);
 954         min_avg = I915_READ(RCBMINAVG);
 955
 956         /* Handle RCS change request from hw */
 957         if (busy_up > max_avg) {
 958                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 959                         new_delay = dev_priv->ips.cur_delay - 1;
 960                 if (new_delay < dev_priv->ips.max_delay)
 961                         new_delay = dev_priv->ips.max_delay;
 962         } else if (busy_down < min_avg) {
 963                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 964                         new_delay = dev_priv->ips.cur_delay + 1;
 965                 if (new_delay > dev_priv->ips.min_delay)
 966                         new_delay = dev_priv->ips.min_delay;
 967         }
 968
 969         if (ironlake_set_drps(dev_priv, new_delay))
 970                 dev_priv->ips.cur_delay = new_delay;
 971
 972         spin_unlock(&mchdev_lock);
 973
 974         return;
 975 }
 976
 977 static void notify_ring(struct intel_engine_cs *engine)
 978 {
 979         smp_store_mb(engine->irq_posted, true);
 980         if (intel_engine_wakeup(engine)) {
 981                 trace_i915_gem_request_notify(engine);
 982                 engine->user_interrupts++;
 983         }
 984 }
 985
 986 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 987                         struct intel_rps_ei *ei)
 988 {
 989         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 990         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 991         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 992 }
 993
 994 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
 995                          const struct intel_rps_ei *old,
 996                          const struct intel_rps_ei *now,
 997                          int threshold)
 998 {
 999         u64 time, c0;
1000         unsigned int mul = 100;
1001
1002         if (old->cz_clock == 0)
1003                 return false;
1004
1005         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1006                 mul <<= 8;
1007
1008         time = now->cz_clock - old->cz_clock;
1009         time *= threshold * dev_priv->czclk_freq;
1010
1011         /* Workload can be split between render + media, e.g. SwapBuffers
1012          * being blitted in X after being rendered in mesa. To account for
1013          * this we need to combine both engines into our activity counter.
1014          */
1015         c0 = now->render_c0 - old->render_c0;
1016         c0 += now->media_c0 - old->media_c0;
1017         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1018
1019         return c0 >= time;
1020 }
1021
1022 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1023 {
1024         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1025         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1026 }
1027
1028 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1029 {
1030         struct intel_rps_ei now;
1031         u32 events = 0;
1032
1033         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1034                 return 0;
1035
1036         vlv_c0_read(dev_priv, &now);
1037         if (now.cz_clock == 0)
1038                 return 0;
1039
1040         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1041                 if (!vlv_c0_above(dev_priv,
1042                                   &dev_priv->rps.down_ei, &now,
1043                                   dev_priv->rps.down_threshold))
1044                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1045                 dev_priv->rps.down_ei = now;
1046         }
1047
1048         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1049                 if (vlv_c0_above(dev_priv,
1050                                  &dev_priv->rps.up_ei, &now,
1051                                  dev_priv->rps.up_threshold))
1052                         events |= GEN6_PM_RP_UP_THRESHOLD;
1053                 dev_priv->rps.up_ei = now;
1054         }
1055
1056         return events;
1057 }
1058
1059 static bool any_waiters(struct drm_i915_private *dev_priv)
1060 {
1061         struct intel_engine_cs *engine;
1062
1063         for_each_engine(engine, dev_priv)
1064                 if (intel_engine_has_waiter(engine))
1065                         return true;
1066
1067         return false;
1068 }
1069
1070 static void gen6_pm_rps_work(struct work_struct *work)
1071 {
1072         struct drm_i915_private *dev_priv =
1073                 container_of(work, struct drm_i915_private, rps.work);
1074         bool client_boost;
1075         int new_delay, adj, min, max;
1076         u32 pm_iir;
1077
1078         spin_lock_irq(&dev_priv->irq_lock);
1079         /* Speed up work cancelation during disabling rps interrupts. */
1080         if (!dev_priv->rps.interrupts_enabled) {
1081                 spin_unlock_irq(&dev_priv->irq_lock);
1082                 return;
1083         }
1084
1085         /*
1086          * The RPS work is synced during runtime suspend, we don't require a
1087          * wakeref. TODO: instead of disabling the asserts make sure that we
1088          * always hold an RPM reference while the work is running.
1089          */
1090         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1091
1092         pm_iir = dev_priv->rps.pm_iir;
1093         dev_priv->rps.pm_iir = 0;
1094         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1095         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1096         client_boost = dev_priv->rps.client_boost;
1097         dev_priv->rps.client_boost = false;
1098         spin_unlock_irq(&dev_priv->irq_lock);
1099
1100         /* Make sure we didn't queue anything we're not going to process. */
1101         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1102
1103         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1104                 goto out;
1105
1106         mutex_lock(&dev_priv->rps.hw_lock);
1107
1108         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1109
1110         adj = dev_priv->rps.last_adj;
1111         new_delay = dev_priv->rps.cur_freq;
1112         min = dev_priv->rps.min_freq_softlimit;
1113         max = dev_priv->rps.max_freq_softlimit;
1114
1115         if (client_boost) {
1116                 new_delay = dev_priv->rps.max_freq_softlimit;
1117                 adj = 0;
1118         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1119                 if (adj > 0)
1120                         adj *= 2;
1121                 else /* CHV needs even encode values */
1122                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1123                 /*
1124                  * For better performance, jump directly
1125                  * to RPe if we're below it.
1126                  */
1127                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1128                         new_delay = dev_priv->rps.efficient_freq;
1129                         adj = 0;
1130                 }
1131         } else if (any_waiters(dev_priv)) {
1132                 adj = 0;
1133         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1134                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1135                         new_delay = dev_priv->rps.efficient_freq;
1136                 else
1137                         new_delay = dev_priv->rps.min_freq_softlimit;
1138                 adj = 0;
1139         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1140                 if (adj < 0)
1141                         adj *= 2;
1142                 else /* CHV needs even encode values */
1143                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1144         } else { /* unknown event */
1145                 adj = 0;
1146         }
1147
1148         dev_priv->rps.last_adj = adj;
1149
1150         /* sysfs frequency interfaces may have snuck in while servicing the
1151          * interrupt
1152          */
1153         new_delay += adj;
1154         new_delay = clamp_t(int, new_delay, min, max);
1155
1156         intel_set_rps(dev_priv, new_delay);
1157
1158         mutex_unlock(&dev_priv->rps.hw_lock);
1159 out:
1160         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1161 }
1162
1163
1164 /**
1165  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1166  * occurred.
1167  * @work: workqueue struct
1168  *
1169  * Doesn't actually do anything except notify userspace. As a consequence of
1170  * this event, userspace should try to remap the bad rows since statistically
1171  * it is likely the same row is more likely to go bad again.
1172  */
1173 static void ivybridge_parity_work(struct work_struct *work)
1174 {
1175         struct drm_i915_private *dev_priv =
1176                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1177         u32 error_status, row, bank, subbank;
1178         char *parity_event[6];
1179         uint32_t misccpctl;
1180         uint8_t slice = 0;
1181
1182         /* We must turn off DOP level clock gating to access the L3 registers.
1183          * In order to prevent a get/put style interface, acquire struct mutex
1184          * any time we access those registers.
1185          */
1186         mutex_lock(&dev_priv->dev->struct_mutex);
1187
1188         /* If we've screwed up tracking, just let the interrupt fire again */
1189         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1190                 goto out;
1191
1192         misccpctl = I915_READ(GEN7_MISCCPCTL);
1193         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1194         POSTING_READ(GEN7_MISCCPCTL);
1195
1196         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1197                 i915_reg_t reg;
1198
1199                 slice--;
1200                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1201                         break;
1202
1203                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1204
1205                 reg = GEN7_L3CDERRST1(slice);
1206
1207                 error_status = I915_READ(reg);
1208                 row = GEN7_PARITY_ERROR_ROW(error_status);
1209                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1210                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1211
1212                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1213                 POSTING_READ(reg);
1214
1215                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1216                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1217                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1218                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1219                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1220                 parity_event[5] = NULL;
1221
1222                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1223                                    KOBJ_CHANGE, parity_event);
1224
1225                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1226                           slice, row, bank, subbank);
1227
1228                 kfree(parity_event[4]);
1229                 kfree(parity_event[3]);
1230                 kfree(parity_event[2]);
1231                 kfree(parity_event[1]);
1232         }
1233
1234         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1235
1236 out:
1237         WARN_ON(dev_priv->l3_parity.which_slice);
1238         spin_lock_irq(&dev_priv->irq_lock);
1239         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1240         spin_unlock_irq(&dev_priv->irq_lock);
1241
1242         mutex_unlock(&dev_priv->dev->struct_mutex);
1243 }
1244
1245 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1246                                                u32 iir)
1247 {
1248         if (!HAS_L3_DPF(dev_priv))
1249                 return;
1250
1251         spin_lock(&dev_priv->irq_lock);
1252         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1253         spin_unlock(&dev_priv->irq_lock);
1254
1255         iir &= GT_PARITY_ERROR(dev_priv);
1256         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1257                 dev_priv->l3_parity.which_slice |= 1 << 1;
1258
1259         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1260                 dev_priv->l3_parity.which_slice |= 1 << 0;
1261
1262         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1263 }
1264
1265 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1266                                u32 gt_iir)
1267 {
1268         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1269                 notify_ring(&dev_priv->engine[RCS]);
1270         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1271                 notify_ring(&dev_priv->engine[VCS]);
1272 }
1273
1274 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1275                                u32 gt_iir)
1276 {
1277         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1278                 notify_ring(&dev_priv->engine[RCS]);
1279         if (gt_iir & GT_BSD_USER_INTERRUPT)
1280                 notify_ring(&dev_priv->engine[VCS]);
1281         if (gt_iir & GT_BLT_USER_INTERRUPT)
1282                 notify_ring(&dev_priv->engine[BCS]);
1283
1284         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1285                       GT_BSD_CS_ERROR_INTERRUPT |
1286                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1287                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1288
1289         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1290                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1291 }
1292
1293 static __always_inline void
1294 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1295 {
1296         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1297                 notify_ring(engine);
1298         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1299                 tasklet_schedule(&engine->irq_tasklet);
1300 }
1301
1302 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1303                                    u32 master_ctl,
1304                                    u32 gt_iir[4])
1305 {
1306         irqreturn_t ret = IRQ_NONE;
1307
1308         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1309                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1310                 if (gt_iir[0]) {
1311                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1312                         ret = IRQ_HANDLED;
1313                 } else
1314                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1315         }
1316
1317         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1318                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1319                 if (gt_iir[1]) {
1320                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1321                         ret = IRQ_HANDLED;
1322                 } else
1323                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1324         }
1325
1326         if (master_ctl & GEN8_GT_VECS_IRQ) {
1327                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1328                 if (gt_iir[3]) {
1329                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1330                         ret = IRQ_HANDLED;
1331                 } else
1332                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1333         }
1334
1335         if (master_ctl & GEN8_GT_PM_IRQ) {
1336                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1337                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1338                         I915_WRITE_FW(GEN8_GT_IIR(2),
1339                                       gt_iir[2] & dev_priv->pm_rps_events);
1340                         ret = IRQ_HANDLED;
1341                 } else
1342                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1343         }
1344
1345         return ret;
1346 }
1347
1348 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1349                                 u32 gt_iir[4])
1350 {
1351         if (gt_iir[0]) {
1352                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1353                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1354                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1355                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1356         }
1357
1358         if (gt_iir[1]) {
1359                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1360                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1361                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1362                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1363         }
1364
1365         if (gt_iir[3])
1366                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1367                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1368
1369         if (gt_iir[2] & dev_priv->pm_rps_events)
1370                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1371 }
1372
1373 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1374 {
1375         switch (port) {
1376         case PORT_A:
1377                 return val & PORTA_HOTPLUG_LONG_DETECT;
1378         case PORT_B:
1379                 return val & PORTB_HOTPLUG_LONG_DETECT;
1380         case PORT_C:
1381                 return val & PORTC_HOTPLUG_LONG_DETECT;
1382         default:
1383                 return false;
1384         }
1385 }
1386
1387 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1388 {
1389         switch (port) {
1390         case PORT_E:
1391                 return val & PORTE_HOTPLUG_LONG_DETECT;
1392         default:
1393                 return false;
1394         }
1395 }
1396
1397 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1398 {
1399         switch (port) {
1400         case PORT_A:
1401                 return val & PORTA_HOTPLUG_LONG_DETECT;
1402         case PORT_B:
1403                 return val & PORTB_HOTPLUG_LONG_DETECT;
1404         case PORT_C:
1405                 return val & PORTC_HOTPLUG_LONG_DETECT;
1406         case PORT_D:
1407                 return val & PORTD_HOTPLUG_LONG_DETECT;
1408         default:
1409                 return false;
1410         }
1411 }
1412
1413 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1414 {
1415         switch (port) {
1416         case PORT_A:
1417                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1418         default:
1419                 return false;
1420         }
1421 }
1422
1423 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1424 {
1425         switch (port) {
1426         case PORT_B:
1427                 return val & PORTB_HOTPLUG_LONG_DETECT;
1428         case PORT_C:
1429                 return val & PORTC_HOTPLUG_LONG_DETECT;
1430         case PORT_D:
1431                 return val & PORTD_HOTPLUG_LONG_DETECT;
1432         default:
1433                 return false;
1434         }
1435 }
1436
1437 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1438 {
1439         switch (port) {
1440         case PORT_B:
1441                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1442         case PORT_C:
1443                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1444         case PORT_D:
1445                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1446         default:
1447                 return false;
1448         }
1449 }
1450
1451 /*
1452  * Get a bit mask of pins that have triggered, and which ones may be long.
1453  * This can be called multiple times with the same masks to accumulate
1454  * hotplug detection results from several registers.
1455  *
1456  * Note that the caller is expected to zero out the masks initially.
1457  */
1458 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1459                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1460                              const u32 hpd[HPD_NUM_PINS],
1461                              bool long_pulse_detect(enum port port, u32 val))
1462 {
1463         enum port port;
1464         int i;
1465
1466         for_each_hpd_pin(i) {
1467                 if ((hpd[i] & hotplug_trigger) == 0)
1468                         continue;
1469
1470                 *pin_mask |= BIT(i);
1471
1472                 if (!intel_hpd_pin_to_port(i, &port))
1473                         continue;
1474
1475                 if (long_pulse_detect(port, dig_hotplug_reg))
1476                         *long_mask |= BIT(i);
1477         }
1478
1479         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1480                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1481
1482 }
1483
1484 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1485 {
1486         wake_up_all(&dev_priv->gmbus_wait_queue);
1487 }
1488
1489 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1490 {
1491         wake_up_all(&dev_priv->gmbus_wait_queue);
1492 }
1493
1494 #if defined(CONFIG_DEBUG_FS)
1495 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1496                                          enum pipe pipe,
1497                                          uint32_t crc0, uint32_t crc1,
1498                                          uint32_t crc2, uint32_t crc3,
1499                                          uint32_t crc4)
1500 {
1501         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1502         struct intel_pipe_crc_entry *entry;
1503         int head, tail;
1504
1505         spin_lock(&pipe_crc->lock);
1506
1507         if (!pipe_crc->entries) {
1508                 spin_unlock(&pipe_crc->lock);
1509                 DRM_DEBUG_KMS("spurious interrupt\n");
1510                 return;
1511         }
1512
1513         head = pipe_crc->head;
1514         tail = pipe_crc->tail;
1515
1516         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1517                 spin_unlock(&pipe_crc->lock);
1518                 DRM_ERROR("CRC buffer overflowing\n");
1519                 return;
1520         }
1521
1522         entry = &pipe_crc->entries[head];
1523
1524         entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1525                                                                  pipe);
1526         entry->crc[0] = crc0;
1527         entry->crc[1] = crc1;
1528         entry->crc[2] = crc2;
1529         entry->crc[3] = crc3;
1530         entry->crc[4] = crc4;
1531
1532         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1533         pipe_crc->head = head;
1534
1535         spin_unlock(&pipe_crc->lock);
1536
1537         wake_up_interruptible(&pipe_crc->wq);
1538 }
1539 #else
1540 static inline void
1541 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1542                              enum pipe pipe,
1543                              uint32_t crc0, uint32_t crc1,
1544                              uint32_t crc2, uint32_t crc3,
1545                              uint32_t crc4) {}
1546 #endif
1547
1548
1549 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1550                                      enum pipe pipe)
1551 {
1552         display_pipe_crc_irq_handler(dev_priv, pipe,
1553                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1554                                      0, 0, 0, 0);
1555 }
1556
1557 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1558                                      enum pipe pipe)
1559 {
1560         display_pipe_crc_irq_handler(dev_priv, pipe,
1561                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1562                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1563                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1564                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1565                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1566 }
1567
1568 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1569                                       enum pipe pipe)
1570 {
1571         uint32_t res1, res2;
1572
1573         if (INTEL_GEN(dev_priv) >= 3)
1574                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1575         else
1576                 res1 = 0;
1577
1578         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1579                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1580         else
1581                 res2 = 0;
1582
1583         display_pipe_crc_irq_handler(dev_priv, pipe,
1584                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1585                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1586                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1587                                      res1, res2);
1588 }
1589
1590 /* The RPS events need forcewake, so we add them to a work queue and mask their
1591  * IMR bits until the work is done. Other interrupts can be processed without
1592  * the work queue. */
1593 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1594 {
1595         if (pm_iir & dev_priv->pm_rps_events) {
1596                 spin_lock(&dev_priv->irq_lock);
1597                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1598                 if (dev_priv->rps.interrupts_enabled) {
1599                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1600                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1601                 }
1602                 spin_unlock(&dev_priv->irq_lock);
1603         }
1604
1605         if (INTEL_INFO(dev_priv)->gen >= 8)
1606                 return;
1607
1608         if (HAS_VEBOX(dev_priv)) {
1609                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1610                         notify_ring(&dev_priv->engine[VECS]);
1611
1612                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1613                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1614         }
1615 }
1616
1617 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1618                                      enum pipe pipe)
1619 {
1620         bool ret;
1621
1622         ret = drm_handle_vblank(dev_priv->dev, pipe);
1623         if (ret)
1624                 intel_finish_page_flip_mmio(dev_priv, pipe);
1625
1626         return ret;
1627 }
1628
1629 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1630                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1631 {
1632         int pipe;
1633
1634         spin_lock(&dev_priv->irq_lock);
1635
1636         if (!dev_priv->display_irqs_enabled) {
1637                 spin_unlock(&dev_priv->irq_lock);
1638                 return;
1639         }
1640
1641         for_each_pipe(dev_priv, pipe) {
1642                 i915_reg_t reg;
1643                 u32 mask, iir_bit = 0;
1644
1645                 /*
1646                  * PIPESTAT bits get signalled even when the interrupt is
1647                  * disabled with the mask bits, and some of the status bits do
1648                  * not generate interrupts at all (like the underrun bit). Hence
1649                  * we need to be careful that we only handle what we want to
1650                  * handle.
1651                  */
1652
1653                 /* fifo underruns are filterered in the underrun handler. */
1654                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1655
1656                 switch (pipe) {
1657                 case PIPE_A:
1658                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1659                         break;
1660                 case PIPE_B:
1661                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1662                         break;
1663                 case PIPE_C:
1664                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1665                         break;
1666                 }
1667                 if (iir & iir_bit)
1668                         mask |= dev_priv->pipestat_irq_mask[pipe];
1669
1670                 if (!mask)
1671                         continue;
1672
1673                 reg = PIPESTAT(pipe);
1674                 mask |= PIPESTAT_INT_ENABLE_MASK;
1675                 pipe_stats[pipe] = I915_READ(reg) & mask;
1676
1677                 /*
1678                  * Clear the PIPE*STAT regs before the IIR
1679                  */
1680                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1681                                         PIPESTAT_INT_STATUS_MASK))
1682                         I915_WRITE(reg, pipe_stats[pipe]);
1683         }
1684         spin_unlock(&dev_priv->irq_lock);
1685 }
1686
1687 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1688                                             u32 pipe_stats[I915_MAX_PIPES])
1689 {
1690         enum pipe pipe;
1691
1692         for_each_pipe(dev_priv, pipe) {
1693                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1694                     intel_pipe_handle_vblank(dev_priv, pipe))
1695                         intel_check_page_flip(dev_priv, pipe);
1696
1697                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1698                         intel_finish_page_flip_cs(dev_priv, pipe);
1699
1700                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1701                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1702
1703                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1704                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1705         }
1706
1707         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1708                 gmbus_irq_handler(dev_priv);
1709 }
1710
1711 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1712 {
1713         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1714
1715         if (hotplug_status)
1716                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1717
1718         return hotplug_status;
1719 }
1720
1721 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1722                                  u32 hotplug_status)
1723 {
1724         u32 pin_mask = 0, long_mask = 0;
1725
1726         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1727             IS_CHERRYVIEW(dev_priv)) {
1728                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1729
1730                 if (hotplug_trigger) {
1731                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1732                                            hotplug_trigger, hpd_status_g4x,
1733                                            i9xx_port_hotplug_long_detect);
1734
1735                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1736                 }
1737
1738                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1739                         dp_aux_irq_handler(dev_priv);
1740         } else {
1741                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1742
1743                 if (hotplug_trigger) {
1744                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1745                                            hotplug_trigger, hpd_status_i915,
1746                                            i9xx_port_hotplug_long_detect);
1747                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1748                 }
1749         }
1750 }
1751
1752 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1753 {
1754         struct drm_device *dev = arg;
1755         struct drm_i915_private *dev_priv = dev->dev_private;
1756         irqreturn_t ret = IRQ_NONE;
1757
1758         if (!intel_irqs_enabled(dev_priv))
1759                 return IRQ_NONE;
1760
1761         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1762         disable_rpm_wakeref_asserts(dev_priv);
1763
1764         do {
1765                 u32 iir, gt_iir, pm_iir;
1766                 u32 pipe_stats[I915_MAX_PIPES] = {};
1767                 u32 hotplug_status = 0;
1768                 u32 ier = 0;
1769
1770                 gt_iir = I915_READ(GTIIR);
1771                 pm_iir = I915_READ(GEN6_PMIIR);
1772                 iir = I915_READ(VLV_IIR);
1773
1774                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1775                         break;
1776
1777                 ret = IRQ_HANDLED;
1778
1779                 /*
1780                  * Theory on interrupt generation, based on empirical evidence:
1781                  *
1782                  * x = ((VLV_IIR & VLV_IER) ||
1783                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1784                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1785                  *
1786                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1787                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1788                  * guarantee the CPU interrupt will be raised again even if we
1789                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1790                  * bits this time around.
1791                  */
1792                 I915_WRITE(VLV_MASTER_IER, 0);
1793                 ier = I915_READ(VLV_IER);
1794                 I915_WRITE(VLV_IER, 0);
1795
1796                 if (gt_iir)
1797                         I915_WRITE(GTIIR, gt_iir);
1798                 if (pm_iir)
1799                         I915_WRITE(GEN6_PMIIR, pm_iir);
1800
1801                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1802                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1803
1804                 /* Call regardless, as some status bits might not be
1805                  * signalled in iir */
1806                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1807
1808                 /*
1809                  * VLV_IIR is single buffered, and reflects the level
1810                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1811                  */
1812                 if (iir)
1813                         I915_WRITE(VLV_IIR, iir);
1814
1815                 I915_WRITE(VLV_IER, ier);
1816                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1817                 POSTING_READ(VLV_MASTER_IER);
1818
1819                 if (gt_iir)
1820                         snb_gt_irq_handler(dev_priv, gt_iir);
1821                 if (pm_iir)
1822                         gen6_rps_irq_handler(dev_priv, pm_iir);
1823
1824                 if (hotplug_status)
1825                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1826
1827                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1828         } while (0);
1829
1830         enable_rpm_wakeref_asserts(dev_priv);
1831
1832         return ret;
1833 }
1834
1835 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1836 {
1837         struct drm_device *dev = arg;
1838         struct drm_i915_private *dev_priv = dev->dev_private;
1839         irqreturn_t ret = IRQ_NONE;
1840
1841         if (!intel_irqs_enabled(dev_priv))
1842                 return IRQ_NONE;
1843
1844         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1845         disable_rpm_wakeref_asserts(dev_priv);
1846
1847         do {
1848                 u32 master_ctl, iir;
1849                 u32 gt_iir[4] = {};
1850                 u32 pipe_stats[I915_MAX_PIPES] = {};
1851                 u32 hotplug_status = 0;
1852                 u32 ier = 0;
1853
1854                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1855                 iir = I915_READ(VLV_IIR);
1856
1857                 if (master_ctl == 0 && iir == 0)
1858                         break;
1859
1860                 ret = IRQ_HANDLED;
1861
1862                 /*
1863                  * Theory on interrupt generation, based on empirical evidence:
1864                  *
1865                  * x = ((VLV_IIR & VLV_IER) ||
1866                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1867                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1868                  *
1869                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1870                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1871                  * guarantee the CPU interrupt will be raised again even if we
1872                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1873                  * bits this time around.
1874                  */
1875                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1876                 ier = I915_READ(VLV_IER);
1877                 I915_WRITE(VLV_IER, 0);
1878
1879                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1880
1881                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1882                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1883
1884                 /* Call regardless, as some status bits might not be
1885                  * signalled in iir */
1886                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1887
1888                 /*
1889                  * VLV_IIR is single buffered, and reflects the level
1890                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1891                  */
1892                 if (iir)
1893                         I915_WRITE(VLV_IIR, iir);
1894
1895                 I915_WRITE(VLV_IER, ier);
1896                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1897                 POSTING_READ(GEN8_MASTER_IRQ);
1898
1899                 gen8_gt_irq_handler(dev_priv, gt_iir);
1900
1901                 if (hotplug_status)
1902                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1903
1904                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1905         } while (0);
1906
1907         enable_rpm_wakeref_asserts(dev_priv);
1908
1909         return ret;
1910 }
1911
1912 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1913                                 u32 hotplug_trigger,
1914                                 const u32 hpd[HPD_NUM_PINS])
1915 {
1916         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1917
1918         /*
1919          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1920          * unless we touch the hotplug register, even if hotplug_trigger is
1921          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1922          * errors.
1923          */
1924         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1925         if (!hotplug_trigger) {
1926                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1927                         PORTD_HOTPLUG_STATUS_MASK |
1928                         PORTC_HOTPLUG_STATUS_MASK |
1929                         PORTB_HOTPLUG_STATUS_MASK;
1930                 dig_hotplug_reg &= ~mask;
1931         }
1932
1933         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1934         if (!hotplug_trigger)
1935                 return;
1936
1937         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1938                            dig_hotplug_reg, hpd,
1939                            pch_port_hotplug_long_detect);
1940
1941         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1942 }
1943
1944 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1945 {
1946         int pipe;
1947         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1948
1949         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1950
1951         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1952                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1953                                SDE_AUDIO_POWER_SHIFT);
1954                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1955                                  port_name(port));
1956         }
1957
1958         if (pch_iir & SDE_AUX_MASK)
1959                 dp_aux_irq_handler(dev_priv);
1960
1961         if (pch_iir & SDE_GMBUS)
1962                 gmbus_irq_handler(dev_priv);
1963
1964         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1965                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1966
1967         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1968                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1969
1970         if (pch_iir & SDE_POISON)
1971                 DRM_ERROR("PCH poison interrupt\n");
1972
1973         if (pch_iir & SDE_FDI_MASK)
1974                 for_each_pipe(dev_priv, pipe)
1975                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1976                                          pipe_name(pipe),
1977                                          I915_READ(FDI_RX_IIR(pipe)));
1978
1979         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1980                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1981
1982         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1983                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1984
1985         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1986                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1987
1988         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1989                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1990 }
1991
1992 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1993 {
1994         u32 err_int = I915_READ(GEN7_ERR_INT);
1995         enum pipe pipe;
1996
1997         if (err_int & ERR_INT_POISON)
1998                 DRM_ERROR("Poison interrupt\n");
1999
2000         for_each_pipe(dev_priv, pipe) {
2001                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2002                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2003
2004                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2005                         if (IS_IVYBRIDGE(dev_priv))
2006                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2007                         else
2008                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2009                 }
2010         }
2011
2012         I915_WRITE(GEN7_ERR_INT, err_int);
2013 }
2014
2015 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2016 {
2017         u32 serr_int = I915_READ(SERR_INT);
2018
2019         if (serr_int & SERR_INT_POISON)
2020                 DRM_ERROR("PCH poison interrupt\n");
2021
2022         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2023                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2024
2025         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2026                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2027
2028         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2029                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2030
2031         I915_WRITE(SERR_INT, serr_int);
2032 }
2033
2034 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2035 {
2036         int pipe;
2037         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2038
2039         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2040
2041         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2042                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2043                                SDE_AUDIO_POWER_SHIFT_CPT);
2044                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2045                                  port_name(port));
2046         }
2047
2048         if (pch_iir & SDE_AUX_MASK_CPT)
2049                 dp_aux_irq_handler(dev_priv);
2050
2051         if (pch_iir & SDE_GMBUS_CPT)
2052                 gmbus_irq_handler(dev_priv);
2053
2054         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2055                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2056
2057         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2058                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2059
2060         if (pch_iir & SDE_FDI_MASK_CPT)
2061                 for_each_pipe(dev_priv, pipe)
2062                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2063                                          pipe_name(pipe),
2064                                          I915_READ(FDI_RX_IIR(pipe)));
2065
2066         if (pch_iir & SDE_ERROR_CPT)
2067                 cpt_serr_int_handler(dev_priv);
2068 }
2069
2070 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2071 {
2072         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2073                 ~SDE_PORTE_HOTPLUG_SPT;
2074         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2075         u32 pin_mask = 0, long_mask = 0;
2076
2077         if (hotplug_trigger) {
2078                 u32 dig_hotplug_reg;
2079
2080                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2081                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2082
2083                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2084                                    dig_hotplug_reg, hpd_spt,
2085                                    spt_port_hotplug_long_detect);
2086         }
2087
2088         if (hotplug2_trigger) {
2089                 u32 dig_hotplug_reg;
2090
2091                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2092                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2093
2094                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2095                                    dig_hotplug_reg, hpd_spt,
2096                                    spt_port_hotplug2_long_detect);
2097         }
2098
2099         if (pin_mask)
2100                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2101
2102         if (pch_iir & SDE_GMBUS_CPT)
2103                 gmbus_irq_handler(dev_priv);
2104 }
2105
2106 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2107                                 u32 hotplug_trigger,
2108                                 const u32 hpd[HPD_NUM_PINS])
2109 {
2110         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2111
2112         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2113         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2114
2115         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2116                            dig_hotplug_reg, hpd,
2117                            ilk_port_hotplug_long_detect);
2118
2119         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2120 }
2121
2122 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2123                                     u32 de_iir)
2124 {
2125         enum pipe pipe;
2126         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2127
2128         if (hotplug_trigger)
2129                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2130
2131         if (de_iir & DE_AUX_CHANNEL_A)
2132                 dp_aux_irq_handler(dev_priv);
2133
2134         if (de_iir & DE_GSE)
2135                 intel_opregion_asle_intr(dev_priv);
2136
2137         if (de_iir & DE_POISON)
2138                 DRM_ERROR("Poison interrupt\n");
2139
2140         for_each_pipe(dev_priv, pipe) {
2141                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2142                     intel_pipe_handle_vblank(dev_priv, pipe))
2143                         intel_check_page_flip(dev_priv, pipe);
2144
2145                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2146                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2147
2148                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2149                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2150
2151                 /* plane/pipes map 1:1 on ilk+ */
2152                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2153                         intel_finish_page_flip_cs(dev_priv, pipe);
2154         }
2155
2156         /* check event from PCH */
2157         if (de_iir & DE_PCH_EVENT) {
2158                 u32 pch_iir = I915_READ(SDEIIR);
2159
2160                 if (HAS_PCH_CPT(dev_priv))
2161                         cpt_irq_handler(dev_priv, pch_iir);
2162                 else
2163                         ibx_irq_handler(dev_priv, pch_iir);
2164
2165                 /* should clear PCH hotplug event before clear CPU irq */
2166                 I915_WRITE(SDEIIR, pch_iir);
2167         }
2168
2169         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2170                 ironlake_rps_change_irq_handler(dev_priv);
2171 }
2172
2173 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2174                                     u32 de_iir)
2175 {
2176         enum pipe pipe;
2177         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2178
2179         if (hotplug_trigger)
2180                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2181
2182         if (de_iir & DE_ERR_INT_IVB)
2183                 ivb_err_int_handler(dev_priv);
2184
2185         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2186                 dp_aux_irq_handler(dev_priv);
2187
2188         if (de_iir & DE_GSE_IVB)
2189                 intel_opregion_asle_intr(dev_priv);
2190
2191         for_each_pipe(dev_priv, pipe) {
2192                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2193                     intel_pipe_handle_vblank(dev_priv, pipe))
2194                         intel_check_page_flip(dev_priv, pipe);
2195
2196                 /* plane/pipes map 1:1 on ilk+ */
2197                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2198                         intel_finish_page_flip_cs(dev_priv, pipe);
2199         }
2200
2201         /* check event from PCH */
2202         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2203                 u32 pch_iir = I915_READ(SDEIIR);
2204
2205                 cpt_irq_handler(dev_priv, pch_iir);
2206
2207                 /* clear PCH hotplug event before clear CPU irq */
2208                 I915_WRITE(SDEIIR, pch_iir);
2209         }
2210 }
2211
2212 /*
2213  * To handle irqs with the minimum potential races with fresh interrupts, we:
2214  * 1 - Disable Master Interrupt Control.
2215  * 2 - Find the source(s) of the interrupt.
2216  * 3 - Clear the Interrupt Identity bits (IIR).
2217  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2218  * 5 - Re-enable Master Interrupt Control.
2219  */
2220 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2221 {
2222         struct drm_device *dev = arg;
2223         struct drm_i915_private *dev_priv = dev->dev_private;
2224         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2225         irqreturn_t ret = IRQ_NONE;
2226
2227         if (!intel_irqs_enabled(dev_priv))
2228                 return IRQ_NONE;
2229
2230         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2231         disable_rpm_wakeref_asserts(dev_priv);
2232
2233         /* disable master interrupt before clearing iir  */
2234         de_ier = I915_READ(DEIER);
2235         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2236         POSTING_READ(DEIER);
2237
2238         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2239          * interrupts will will be stored on its back queue, and then we'll be
2240          * able to process them after we restore SDEIER (as soon as we restore
2241          * it, we'll get an interrupt if SDEIIR still has something to process
2242          * due to its back queue). */
2243         if (!HAS_PCH_NOP(dev_priv)) {
2244                 sde_ier = I915_READ(SDEIER);
2245                 I915_WRITE(SDEIER, 0);
2246                 POSTING_READ(SDEIER);
2247         }
2248
2249         /* Find, clear, then process each source of interrupt */
2250
2251         gt_iir = I915_READ(GTIIR);
2252         if (gt_iir) {
2253                 I915_WRITE(GTIIR, gt_iir);
2254                 ret = IRQ_HANDLED;
2255                 if (INTEL_GEN(dev_priv) >= 6)
2256                         snb_gt_irq_handler(dev_priv, gt_iir);
2257                 else
2258                         ilk_gt_irq_handler(dev_priv, gt_iir);
2259         }
2260
2261         de_iir = I915_READ(DEIIR);
2262         if (de_iir) {
2263                 I915_WRITE(DEIIR, de_iir);
2264                 ret = IRQ_HANDLED;
2265                 if (INTEL_GEN(dev_priv) >= 7)
2266                         ivb_display_irq_handler(dev_priv, de_iir);
2267                 else
2268                         ilk_display_irq_handler(dev_priv, de_iir);
2269         }
2270
2271         if (INTEL_GEN(dev_priv) >= 6) {
2272                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2273                 if (pm_iir) {
2274                         I915_WRITE(GEN6_PMIIR, pm_iir);
2275                         ret = IRQ_HANDLED;
2276                         gen6_rps_irq_handler(dev_priv, pm_iir);
2277                 }
2278         }
2279
2280         I915_WRITE(DEIER, de_ier);
2281         POSTING_READ(DEIER);
2282         if (!HAS_PCH_NOP(dev_priv)) {
2283                 I915_WRITE(SDEIER, sde_ier);
2284                 POSTING_READ(SDEIER);
2285         }
2286
2287         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2288         enable_rpm_wakeref_asserts(dev_priv);
2289
2290         return ret;
2291 }
2292
2293 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2294                                 u32 hotplug_trigger,
2295                                 const u32 hpd[HPD_NUM_PINS])
2296 {
2297         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2298
2299         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2300         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2301
2302         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2303                            dig_hotplug_reg, hpd,
2304                            bxt_port_hotplug_long_detect);
2305
2306         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2307 }
2308
2309 static irqreturn_t
2310 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2311 {
2312         irqreturn_t ret = IRQ_NONE;
2313         u32 iir;
2314         enum pipe pipe;
2315
2316         if (master_ctl & GEN8_DE_MISC_IRQ) {
2317                 iir = I915_READ(GEN8_DE_MISC_IIR);
2318                 if (iir) {
2319                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2320                         ret = IRQ_HANDLED;
2321                         if (iir & GEN8_DE_MISC_GSE)
2322                                 intel_opregion_asle_intr(dev_priv);
2323                         else
2324                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2325                 }
2326                 else
2327                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2328         }
2329
2330         if (master_ctl & GEN8_DE_PORT_IRQ) {
2331                 iir = I915_READ(GEN8_DE_PORT_IIR);
2332                 if (iir) {
2333                         u32 tmp_mask;
2334                         bool found = false;
2335
2336                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2337                         ret = IRQ_HANDLED;
2338
2339                         tmp_mask = GEN8_AUX_CHANNEL_A;
2340                         if (INTEL_INFO(dev_priv)->gen >= 9)
2341                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2342                                             GEN9_AUX_CHANNEL_C |
2343                                             GEN9_AUX_CHANNEL_D;
2344
2345                         if (iir & tmp_mask) {
2346                                 dp_aux_irq_handler(dev_priv);
2347                                 found = true;
2348                         }
2349
2350                         if (IS_BROXTON(dev_priv)) {
2351                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2352                                 if (tmp_mask) {
2353                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2354                                                             hpd_bxt);
2355                                         found = true;
2356                                 }
2357                         } else if (IS_BROADWELL(dev_priv)) {
2358                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2359                                 if (tmp_mask) {
2360                                         ilk_hpd_irq_handler(dev_priv,
2361                                                             tmp_mask, hpd_bdw);
2362                                         found = true;
2363                                 }
2364                         }
2365
2366                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2367                                 gmbus_irq_handler(dev_priv);
2368                                 found = true;
2369                         }
2370
2371                         if (!found)
2372                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2373                 }
2374                 else
2375                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2376         }
2377
2378         for_each_pipe(dev_priv, pipe) {
2379                 u32 flip_done, fault_errors;
2380
2381                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2382                         continue;
2383
2384                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2385                 if (!iir) {
2386                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2387                         continue;
2388                 }
2389
2390                 ret = IRQ_HANDLED;
2391                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2392
2393                 if (iir & GEN8_PIPE_VBLANK &&
2394                     intel_pipe_handle_vblank(dev_priv, pipe))
2395                         intel_check_page_flip(dev_priv, pipe);
2396
2397                 flip_done = iir;
2398                 if (INTEL_INFO(dev_priv)->gen >= 9)
2399                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2400                 else
2401                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2402
2403                 if (flip_done)
2404                         intel_finish_page_flip_cs(dev_priv, pipe);
2405
2406                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2407                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2408
2409                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2410                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2411
2412                 fault_errors = iir;
2413                 if (INTEL_INFO(dev_priv)->gen >= 9)
2414                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2415                 else
2416                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2417
2418                 if (fault_errors)
2419                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2420                                   pipe_name(pipe),
2421                                   fault_errors);
2422         }
2423
2424         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2425             master_ctl & GEN8_DE_PCH_IRQ) {
2426                 /*
2427                  * FIXME(BDW): Assume for now that the new interrupt handling
2428                  * scheme also closed the SDE interrupt handling race we've seen
2429                  * on older pch-split platforms. But this needs testing.
2430                  */
2431                 iir = I915_READ(SDEIIR);
2432                 if (iir) {
2433                         I915_WRITE(SDEIIR, iir);
2434                         ret = IRQ_HANDLED;
2435
2436                         if (HAS_PCH_SPT(dev_priv))
2437                                 spt_irq_handler(dev_priv, iir);
2438                         else
2439                                 cpt_irq_handler(dev_priv, iir);
2440                 } else {
2441                         /*
2442                          * Like on previous PCH there seems to be something
2443                          * fishy going on with forwarding PCH interrupts.
2444                          */
2445                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2446                 }
2447         }
2448
2449         return ret;
2450 }
2451
2452 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2453 {
2454         struct drm_device *dev = arg;
2455         struct drm_i915_private *dev_priv = dev->dev_private;
2456         u32 master_ctl;
2457         u32 gt_iir[4] = {};
2458         irqreturn_t ret;
2459
2460         if (!intel_irqs_enabled(dev_priv))
2461                 return IRQ_NONE;
2462
2463         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2464         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2465         if (!master_ctl)
2466                 return IRQ_NONE;
2467
2468         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2469
2470         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2471         disable_rpm_wakeref_asserts(dev_priv);
2472
2473         /* Find, clear, then process each source of interrupt */
2474         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2475         gen8_gt_irq_handler(dev_priv, gt_iir);
2476         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2477
2478         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2479         POSTING_READ_FW(GEN8_MASTER_IRQ);
2480
2481         enable_rpm_wakeref_asserts(dev_priv);
2482
2483         return ret;
2484 }
2485
2486 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2487 {
2488         /*
2489          * Notify all waiters for GPU completion events that reset state has
2490          * been changed, and that they need to restart their wait after
2491          * checking for potential errors (and bail out to drop locks if there is
2492          * a gpu reset pending so that i915_error_work_func can acquire them).
2493          */
2494
2495         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2496         wake_up_all(&dev_priv->gpu_error.wait_queue);
2497
2498         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2499         wake_up_all(&dev_priv->pending_flip_queue);
2500 }
2501
2502 /**
2503  * i915_reset_and_wakeup - do process context error handling work
2504  * @dev_priv: i915 device private
2505  *
2506  * Fire an error uevent so userspace can see that a hang or error
2507  * was detected.
2508  */
2509 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2510 {
2511         struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2512         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2513         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2514         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2515         int ret;
2516
2517         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2518
2519         /*
2520          * Note that there's only one work item which does gpu resets, so we
2521          * need not worry about concurrent gpu resets potentially incrementing
2522          * error->reset_counter twice. We only need to take care of another
2523          * racing irq/hangcheck declaring the gpu dead for a second time. A
2524          * quick check for that is good enough: schedule_work ensures the
2525          * correct ordering between hang detection and this work item, and since
2526          * the reset in-progress bit is only ever set by code outside of this
2527          * work we don't need to worry about any other races.
2528          */
2529         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2530                 DRM_DEBUG_DRIVER("resetting chip\n");
2531                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2532
2533                 /*
2534                  * In most cases it's guaranteed that we get here with an RPM
2535                  * reference held, for example because there is a pending GPU
2536                  * request that won't finish until the reset is done. This
2537                  * isn't the case at least when we get here by doing a
2538                  * simulated reset via debugs, so get an RPM reference.
2539                  */
2540                 intel_runtime_pm_get(dev_priv);
2541
2542                 intel_prepare_reset(dev_priv);
2543
2544                 /*
2545                  * All state reset _must_ be completed before we update the
2546                  * reset counter, for otherwise waiters might miss the reset
2547                  * pending state and not properly drop locks, resulting in
2548                  * deadlocks with the reset work.
2549                  */
2550                 ret = i915_reset(dev_priv);
2551
2552                 intel_finish_reset(dev_priv);
2553
2554                 intel_runtime_pm_put(dev_priv);
2555
2556                 if (ret == 0)
2557                         kobject_uevent_env(kobj,
2558                                            KOBJ_CHANGE, reset_done_event);
2559
2560                 /*
2561                  * Note: The wake_up also serves as a memory barrier so that
2562                  * waiters see the update value of the reset counter atomic_t.
2563                  */
2564                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2565         }
2566 }
2567
2568 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2569 {
2570         uint32_t instdone[I915_NUM_INSTDONE_REG];
2571         u32 eir = I915_READ(EIR);
2572         int pipe, i;
2573
2574         if (!eir)
2575                 return;
2576
2577         pr_err("render error detected, EIR: 0x%08x\n", eir);
2578
2579         i915_get_extra_instdone(dev_priv, instdone);
2580
2581         if (IS_G4X(dev_priv)) {
2582                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2583                         u32 ipeir = I915_READ(IPEIR_I965);
2584
2585                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2586                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2587                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2588                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2589                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2590                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2591                         I915_WRITE(IPEIR_I965, ipeir);
2592                         POSTING_READ(IPEIR_I965);
2593                 }
2594                 if (eir & GM45_ERROR_PAGE_TABLE) {
2595                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2596                         pr_err("page table error\n");
2597                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2598                         I915_WRITE(PGTBL_ER, pgtbl_err);
2599                         POSTING_READ(PGTBL_ER);
2600                 }
2601         }
2602
2603         if (!IS_GEN2(dev_priv)) {
2604                 if (eir & I915_ERROR_PAGE_TABLE) {
2605                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2606                         pr_err("page table error\n");
2607                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2608                         I915_WRITE(PGTBL_ER, pgtbl_err);
2609                         POSTING_READ(PGTBL_ER);
2610                 }
2611         }
2612
2613         if (eir & I915_ERROR_MEMORY_REFRESH) {
2614                 pr_err("memory refresh error:\n");
2615                 for_each_pipe(dev_priv, pipe)
2616                         pr_err("pipe %c stat: 0x%08x\n",
2617                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2618                 /* pipestat has already been acked */
2619         }
2620         if (eir & I915_ERROR_INSTRUCTION) {
2621                 pr_err("instruction error\n");
2622                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2623                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2624                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2625                 if (INTEL_GEN(dev_priv) < 4) {
2626                         u32 ipeir = I915_READ(IPEIR);
2627
2628                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2629                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2630                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2631                         I915_WRITE(IPEIR, ipeir);
2632                         POSTING_READ(IPEIR);
2633                 } else {
2634                         u32 ipeir = I915_READ(IPEIR_I965);
2635
2636                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2637                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2638                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2639                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2640                         I915_WRITE(IPEIR_I965, ipeir);
2641                         POSTING_READ(IPEIR_I965);
2642                 }
2643         }
2644
2645         I915_WRITE(EIR, eir);
2646         POSTING_READ(EIR);
2647         eir = I915_READ(EIR);
2648         if (eir) {
2649                 /*
2650                  * some errors might have become stuck,
2651                  * mask them.
2652                  */
2653                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2654                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2655                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2656         }
2657 }
2658
2659 /**
2660  * i915_handle_error - handle a gpu error
2661  * @dev_priv: i915 device private
2662  * @engine_mask: mask representing engines that are hung
2663  * Do some basic checking of register state at error time and
2664  * dump it to the syslog.  Also call i915_capture_error_state() to make
2665  * sure we get a record and make it available in debugfs.  Fire a uevent
2666  * so userspace knows something bad happened (should trigger collection
2667  * of a ring dump etc.).
2668  * @fmt: Error message format string
2669  */
2670 void i915_handle_error(struct drm_i915_private *dev_priv,
2671                        u32 engine_mask,
2672                        const char *fmt, ...)
2673 {
2674         va_list args;
2675         char error_msg[80];
2676
2677         va_start(args, fmt);
2678         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2679         va_end(args);
2680
2681         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2682         i915_report_and_clear_eir(dev_priv);
2683
2684         if (engine_mask) {
2685                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2686                                 &dev_priv->gpu_error.reset_counter);
2687
2688                 /*
2689                  * Wakeup waiting processes so that the reset function
2690                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2691                  * various locks. By bumping the reset counter first, the woken
2692                  * processes will see a reset in progress and back off,
2693                  * releasing their locks and then wait for the reset completion.
2694                  * We must do this for _all_ gpu waiters that might hold locks
2695                  * that the reset work needs to acquire.
2696                  *
2697                  * Note: The wake_up serves as the required memory barrier to
2698                  * ensure that the waiters see the updated value of the reset
2699                  * counter atomic_t.
2700                  */
2701                 i915_error_wake_up(dev_priv);
2702         }
2703
2704         i915_reset_and_wakeup(dev_priv);
2705 }
2706
2707 /* Called from drm generic code, passed 'crtc' which
2708  * we use as a pipe index
2709  */
2710 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2711 {
2712         struct drm_i915_private *dev_priv = dev->dev_private;
2713         unsigned long irqflags;
2714
2715         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2716         if (INTEL_INFO(dev)->gen >= 4)
2717                 i915_enable_pipestat(dev_priv, pipe,
2718                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2719         else
2720                 i915_enable_pipestat(dev_priv, pipe,
2721                                      PIPE_VBLANK_INTERRUPT_STATUS);
2722         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2723
2724         return 0;
2725 }
2726
2727 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2728 {
2729         struct drm_i915_private *dev_priv = dev->dev_private;
2730         unsigned long irqflags;
2731         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2732                                                      DE_PIPE_VBLANK(pipe);
2733
2734         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2735         ilk_enable_display_irq(dev_priv, bit);
2736         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2737
2738         return 0;
2739 }
2740
2741 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744         unsigned long irqflags;
2745
2746         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2747         i915_enable_pipestat(dev_priv, pipe,
2748                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2749         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2750
2751         return 0;
2752 }
2753
2754 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2755 {
2756         struct drm_i915_private *dev_priv = dev->dev_private;
2757         unsigned long irqflags;
2758
2759         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2760         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2761         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2762
2763         return 0;
2764 }
2765
2766 /* Called from drm generic code, passed 'crtc' which
2767  * we use as a pipe index
2768  */
2769 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2770 {
2771         struct drm_i915_private *dev_priv = dev->dev_private;
2772         unsigned long irqflags;
2773
2774         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2775         i915_disable_pipestat(dev_priv, pipe,
2776                               PIPE_VBLANK_INTERRUPT_STATUS |
2777                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2778         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2779 }
2780
2781 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2782 {
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         unsigned long irqflags;
2785         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2786                                                      DE_PIPE_VBLANK(pipe);
2787
2788         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2789         ilk_disable_display_irq(dev_priv, bit);
2790         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2791 }
2792
2793 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2794 {
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         unsigned long irqflags;
2797
2798         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2799         i915_disable_pipestat(dev_priv, pipe,
2800                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2801         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2802 }
2803
2804 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2805 {
2806         struct drm_i915_private *dev_priv = dev->dev_private;
2807         unsigned long irqflags;
2808
2809         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2810         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2811         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2812 }
2813
2814 static bool
2815 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2816 {
2817         return i915_seqno_passed(seqno,
2818                                  READ_ONCE(engine->last_submitted_seqno));
2819 }
2820
2821 static bool
2822 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2823 {
2824         if (INTEL_GEN(engine->i915) >= 8) {
2825                 return (ipehr >> 23) == 0x1c;
2826         } else {
2827                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2828                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2829                                  MI_SEMAPHORE_REGISTER);
2830         }
2831 }
2832
2833 static struct intel_engine_cs *
2834 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2835                                  u64 offset)
2836 {
2837         struct drm_i915_private *dev_priv = engine->i915;
2838         struct intel_engine_cs *signaller;
2839
2840         if (INTEL_GEN(dev_priv) >= 8) {
2841                 for_each_engine(signaller, dev_priv) {
2842                         if (engine == signaller)
2843                                 continue;
2844
2845                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2846                                 return signaller;
2847                 }
2848         } else {
2849                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2850
2851                 for_each_engine(signaller, dev_priv) {
2852                         if(engine == signaller)
2853                                 continue;
2854
2855                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2856                                 return signaller;
2857                 }
2858         }
2859
2860         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2861                   engine->id, ipehr, offset);
2862
2863         return NULL;
2864 }
2865
2866 static struct intel_engine_cs *
2867 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2868 {
2869         struct drm_i915_private *dev_priv = engine->i915;
2870         u32 cmd, ipehr, head;
2871         u64 offset = 0;
2872         int i, backwards;
2873
2874         /*
2875          * This function does not support execlist mode - any attempt to
2876          * proceed further into this function will result in a kernel panic
2877          * when dereferencing ring->buffer, which is not set up in execlist
2878          * mode.
2879          *
2880          * The correct way of doing it would be to derive the currently
2881          * executing ring buffer from the current context, which is derived
2882          * from the currently running request. Unfortunately, to get the
2883          * current request we would have to grab the struct_mutex before doing
2884          * anything else, which would be ill-advised since some other thread
2885          * might have grabbed it already and managed to hang itself, causing
2886          * the hang checker to deadlock.
2887          *
2888          * Therefore, this function does not support execlist mode in its
2889          * current form. Just return NULL and move on.
2890          */
2891         if (engine->buffer == NULL)
2892                 return NULL;
2893
2894         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2895         if (!ipehr_is_semaphore_wait(engine, ipehr))
2896                 return NULL;
2897
2898         /*
2899          * HEAD is likely pointing to the dword after the actual command,
2900          * so scan backwards until we find the MBOX. But limit it to just 3
2901          * or 4 dwords depending on the semaphore wait command size.
2902          * Note that we don't care about ACTHD here since that might
2903          * point at at batch, and semaphores are always emitted into the
2904          * ringbuffer itself.
2905          */
2906         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2907         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2908
2909         for (i = backwards; i; --i) {
2910                 /*
2911                  * Be paranoid and presume the hw has gone off into the wild -
2912                  * our ring is smaller than what the hardware (and hence
2913                  * HEAD_ADDR) allows. Also handles wrap-around.
2914                  */
2915                 head &= engine->buffer->size - 1;
2916
2917                 /* This here seems to blow up */
2918                 cmd = ioread32(engine->buffer->virtual_start + head);
2919                 if (cmd == ipehr)
2920                         break;
2921
2922                 head -= 4;
2923         }
2924
2925         if (!i)
2926                 return NULL;
2927
2928         *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2929         if (INTEL_GEN(dev_priv) >= 8) {
2930                 offset = ioread32(engine->buffer->virtual_start + head + 12);
2931                 offset <<= 32;
2932                 offset = ioread32(engine->buffer->virtual_start + head + 8);
2933         }
2934         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2935 }
2936
2937 static int semaphore_passed(struct intel_engine_cs *engine)
2938 {
2939         struct drm_i915_private *dev_priv = engine->i915;
2940         struct intel_engine_cs *signaller;
2941         u32 seqno;
2942
2943         engine->hangcheck.deadlock++;
2944
2945         signaller = semaphore_waits_for(engine, &seqno);
2946         if (signaller == NULL)
2947                 return -1;
2948
2949         /* Prevent pathological recursion due to driver bugs */
2950         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2951                 return -1;
2952
2953         if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2954                 return 1;
2955
2956         /* cursory check for an unkickable deadlock */
2957         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2958             semaphore_passed(signaller) < 0)
2959                 return -1;
2960
2961         return 0;
2962 }
2963
2964 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2965 {
2966         struct intel_engine_cs *engine;
2967
2968         for_each_engine(engine, dev_priv)
2969                 engine->hangcheck.deadlock = 0;
2970 }
2971
2972 static bool subunits_stuck(struct intel_engine_cs *engine)
2973 {
2974         u32 instdone[I915_NUM_INSTDONE_REG];
2975         bool stuck;
2976         int i;
2977
2978         if (engine->id != RCS)
2979                 return true;
2980
2981         i915_get_extra_instdone(engine->i915, instdone);
2982
2983         /* There might be unstable subunit states even when
2984          * actual head is not moving. Filter out the unstable ones by
2985          * accumulating the undone -> done transitions and only
2986          * consider those as progress.
2987          */
2988         stuck = true;
2989         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2990                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2991
2992                 if (tmp != engine->hangcheck.instdone[i])
2993                         stuck = false;
2994
2995                 engine->hangcheck.instdone[i] |= tmp;
2996         }
2997
2998         return stuck;
2999 }
3000
3001 static enum intel_ring_hangcheck_action
3002 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3003 {
3004         if (acthd != engine->hangcheck.acthd) {
3005
3006                 /* Clear subunit states on head movement */
3007                 memset(engine->hangcheck.instdone, 0,
3008                        sizeof(engine->hangcheck.instdone));
3009
3010                 return HANGCHECK_ACTIVE;
3011         }
3012
3013         if (!subunits_stuck(engine))
3014                 return HANGCHECK_ACTIVE;
3015
3016         return HANGCHECK_HUNG;
3017 }
3018
3019 static enum intel_ring_hangcheck_action
3020 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3021 {
3022         struct drm_i915_private *dev_priv = engine->i915;
3023         enum intel_ring_hangcheck_action ha;
3024         u32 tmp;
3025
3026         ha = head_stuck(engine, acthd);
3027         if (ha != HANGCHECK_HUNG)
3028                 return ha;
3029
3030         if (IS_GEN2(dev_priv))
3031                 return HANGCHECK_HUNG;
3032
3033         /* Is the chip hanging on a WAIT_FOR_EVENT?
3034          * If so we can simply poke the RB_WAIT bit
3035          * and break the hang. This should work on
3036          * all but the second generation chipsets.
3037          */
3038         tmp = I915_READ_CTL(engine);
3039         if (tmp & RING_WAIT) {
3040                 i915_handle_error(dev_priv, 0,
3041                                   "Kicking stuck wait on %s",
3042                                   engine->name);
3043                 I915_WRITE_CTL(engine, tmp);
3044                 return HANGCHECK_KICK;
3045         }
3046
3047         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3048                 switch (semaphore_passed(engine)) {
3049                 default:
3050                         return HANGCHECK_HUNG;
3051                 case 1:
3052                         i915_handle_error(dev_priv, 0,
3053                                           "Kicking stuck semaphore on %s",
3054                                           engine->name);
3055                         I915_WRITE_CTL(engine, tmp);
3056                         return HANGCHECK_KICK;
3057                 case 0:
3058                         return HANGCHECK_WAIT;
3059                 }
3060         }
3061
3062         return HANGCHECK_HUNG;
3063 }
3064
3065 static unsigned kick_waiters(struct intel_engine_cs *engine)
3066 {
3067         struct drm_i915_private *i915 = engine->i915;
3068         unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3069
3070         if (engine->hangcheck.user_interrupts == user_interrupts &&
3071             !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3072                 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3073                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3074                                   engine->name);
3075
3076                 intel_engine_enable_fake_irq(engine);
3077         }
3078
3079         return user_interrupts;
3080 }
3081 /*
3082  * This is called when the chip hasn't reported back with completed
3083  * batchbuffers in a long time. We keep track per ring seqno progress and
3084  * if there are no progress, hangcheck score for that ring is increased.
3085  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3086  * we kick the ring. If we see no progress on three subsequent calls
3087  * we assume chip is wedged and try to fix it by resetting the chip.
3088  */
3089 static void i915_hangcheck_elapsed(struct work_struct *work)
3090 {
3091         struct drm_i915_private *dev_priv =
3092                 container_of(work, typeof(*dev_priv),
3093                              gpu_error.hangcheck_work.work);
3094         struct intel_engine_cs *engine;
3095         enum intel_engine_id id;
3096         int busy_count = 0, rings_hung = 0;
3097         bool stuck[I915_NUM_ENGINES] = { 0 };
3098 #define BUSY 1
3099 #define KICK 5
3100 #define HUNG 20
3101 #define ACTIVE_DECAY 15
3102
3103         if (!i915.enable_hangcheck)
3104                 return;
3105
3106         /*
3107          * The hangcheck work is synced during runtime suspend, we don't
3108          * require a wakeref. TODO: instead of disabling the asserts make
3109          * sure that we hold a reference when this work is running.
3110          */
3111         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3112
3113         /* As enabling the GPU requires fairly extensive mmio access,
3114          * periodically arm the mmio checker to see if we are triggering
3115          * any invalid access.
3116          */
3117         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3118
3119         for_each_engine_id(engine, dev_priv, id) {
3120                 bool busy = intel_engine_has_waiter(engine);
3121                 u64 acthd;
3122                 u32 seqno;
3123                 unsigned user_interrupts;
3124
3125                 semaphore_clear_deadlocks(dev_priv);
3126
3127                 /* We don't strictly need an irq-barrier here, as we are not
3128                  * serving an interrupt request, be paranoid in case the
3129                  * barrier has side-effects (such as preventing a broken
3130                  * cacheline snoop) and so be sure that we can see the seqno
3131                  * advance. If the seqno should stick, due to a stale
3132                  * cacheline, we would erroneously declare the GPU hung.
3133                  */
3134                 if (engine->irq_seqno_barrier)
3135                         engine->irq_seqno_barrier(engine);
3136
3137                 acthd = intel_ring_get_active_head(engine);
3138                 seqno = intel_engine_get_seqno(engine);
3139
3140                 /* Reset stuck interrupts between batch advances */
3141                 user_interrupts = 0;
3142
3143                 if (engine->hangcheck.seqno == seqno) {
3144                         if (ring_idle(engine, seqno)) {
3145                                 engine->hangcheck.action = HANGCHECK_IDLE;
3146                                 if (busy) {
3147                                         /* Safeguard against driver failure */
3148                                         user_interrupts = kick_waiters(engine);
3149                                         engine->hangcheck.score += BUSY;
3150                                 }
3151                         } else {
3152                                 /* We always increment the hangcheck score
3153                                  * if the ring is busy and still processing
3154                                  * the same request, so that no single request
3155                                  * can run indefinitely (such as a chain of
3156                                  * batches). The only time we do not increment
3157                                  * the hangcheck score on this ring, if this
3158                                  * ring is in a legitimate wait for another
3159                                  * ring. In that case the waiting ring is a
3160                                  * victim and we want to be sure we catch the
3161                                  * right culprit. Then every time we do kick
3162                                  * the ring, add a small increment to the
3163                                  * score so that we can catch a batch that is
3164                                  * being repeatedly kicked and so responsible
3165                                  * for stalling the machine.
3166                                  */
3167                                 engine->hangcheck.action = ring_stuck(engine,
3168                                                                       acthd);
3169
3170                                 switch (engine->hangcheck.action) {
3171                                 case HANGCHECK_IDLE:
3172                                 case HANGCHECK_WAIT:
3173                                         break;
3174                                 case HANGCHECK_ACTIVE:
3175                                         engine->hangcheck.score += BUSY;
3176                                         break;
3177                                 case HANGCHECK_KICK:
3178                                         engine->hangcheck.score += KICK;
3179                                         break;
3180                                 case HANGCHECK_HUNG:
3181                                         engine->hangcheck.score += HUNG;
3182                                         stuck[id] = true;
3183                                         break;
3184                                 }
3185                         }
3186                 } else {
3187                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3188
3189                         /* Gradually reduce the count so that we catch DoS
3190                          * attempts across multiple batches.
3191                          */
3192                         if (engine->hangcheck.score > 0)
3193                                 engine->hangcheck.score -= ACTIVE_DECAY;
3194                         if (engine->hangcheck.score < 0)
3195                                 engine->hangcheck.score = 0;
3196
3197                         /* Clear head and subunit states on seqno movement */
3198                         acthd = 0;
3199
3200                         memset(engine->hangcheck.instdone, 0,
3201                                sizeof(engine->hangcheck.instdone));
3202                 }
3203
3204                 engine->hangcheck.seqno = seqno;
3205                 engine->hangcheck.acthd = acthd;
3206                 engine->hangcheck.user_interrupts = user_interrupts;
3207                 busy_count += busy;
3208         }
3209
3210         for_each_engine_id(engine, dev_priv, id) {
3211                 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3212                         DRM_INFO("%s on %s\n",
3213                                  stuck[id] ? "stuck" : "no progress",
3214                                  engine->name);
3215                         rings_hung |= intel_engine_flag(engine);
3216                 }
3217         }
3218
3219         if (rings_hung) {
3220                 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3221                 goto out;
3222         }
3223
3224         /* Reset timer in case GPU hangs without another request being added */
3225         if (busy_count)
3226                 i915_queue_hangcheck(dev_priv);
3227
3228 out:
3229         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3230 }
3231
3232 static void ibx_irq_reset(struct drm_device *dev)
3233 {
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235
3236         if (HAS_PCH_NOP(dev))
3237                 return;
3238
3239         GEN5_IRQ_RESET(SDE);
3240
3241         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3242                 I915_WRITE(SERR_INT, 0xffffffff);
3243 }
3244
3245 /*
3246  * SDEIER is also touched by the interrupt handler to work around missed PCH
3247  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3248  * instead we unconditionally enable all PCH interrupt sources here, but then
3249  * only unmask them as needed with SDEIMR.
3250  *
3251  * This function needs to be called before interrupts are enabled.
3252  */
3253 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3254 {
3255         struct drm_i915_private *dev_priv = dev->dev_private;
3256
3257         if (HAS_PCH_NOP(dev))
3258                 return;
3259
3260         WARN_ON(I915_READ(SDEIER) != 0);
3261         I915_WRITE(SDEIER, 0xffffffff);
3262         POSTING_READ(SDEIER);
3263 }
3264
3265 static void gen5_gt_irq_reset(struct drm_device *dev)
3266 {
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268
3269         GEN5_IRQ_RESET(GT);
3270         if (INTEL_INFO(dev)->gen >= 6)
3271                 GEN5_IRQ_RESET(GEN6_PM);
3272 }
3273
3274 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3275 {
3276         enum pipe pipe;
3277
3278         if (IS_CHERRYVIEW(dev_priv))
3279                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3280         else
3281                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3282
3283         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3284         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3285
3286         for_each_pipe(dev_priv, pipe) {
3287                 I915_WRITE(PIPESTAT(pipe),
3288                            PIPE_FIFO_UNDERRUN_STATUS |
3289                            PIPESTAT_INT_STATUS_MASK);
3290                 dev_priv->pipestat_irq_mask[pipe] = 0;
3291         }
3292
3293         GEN5_IRQ_RESET(VLV_);
3294         dev_priv->irq_mask = ~0;
3295 }
3296
3297 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3298 {
3299         u32 pipestat_mask;
3300         u32 enable_mask;
3301         enum pipe pipe;
3302
3303         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3304                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3305
3306         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3307         for_each_pipe(dev_priv, pipe)
3308                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3309
3310         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3311                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3312                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3313         if (IS_CHERRYVIEW(dev_priv))
3314                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3315
3316         WARN_ON(dev_priv->irq_mask != ~0);
3317
3318         dev_priv->irq_mask = ~enable_mask;
3319
3320         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3321 }
3322
3323 /* drm_dma.h hooks
3324 */
3325 static void ironlake_irq_reset(struct drm_device *dev)
3326 {
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328
3329         I915_WRITE(HWSTAM, 0xffffffff);
3330
3331         GEN5_IRQ_RESET(DE);
3332         if (IS_GEN7(dev))
3333                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3334
3335         gen5_gt_irq_reset(dev);
3336
3337         ibx_irq_reset(dev);
3338 }
3339
3340 static void valleyview_irq_preinstall(struct drm_device *dev)
3341 {
3342         struct drm_i915_private *dev_priv = dev->dev_private;
3343
3344         I915_WRITE(VLV_MASTER_IER, 0);
3345         POSTING_READ(VLV_MASTER_IER);
3346
3347         gen5_gt_irq_reset(dev);
3348
3349         spin_lock_irq(&dev_priv->irq_lock);
3350         if (dev_priv->display_irqs_enabled)
3351                 vlv_display_irq_reset(dev_priv);
3352         spin_unlock_irq(&dev_priv->irq_lock);
3353 }
3354
3355 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3356 {
3357         GEN8_IRQ_RESET_NDX(GT, 0);
3358         GEN8_IRQ_RESET_NDX(GT, 1);
3359         GEN8_IRQ_RESET_NDX(GT, 2);
3360         GEN8_IRQ_RESET_NDX(GT, 3);
3361 }
3362
3363 static void gen8_irq_reset(struct drm_device *dev)
3364 {
3365         struct drm_i915_private *dev_priv = dev->dev_private;
3366         int pipe;
3367
3368         I915_WRITE(GEN8_MASTER_IRQ, 0);
3369         POSTING_READ(GEN8_MASTER_IRQ);
3370
3371         gen8_gt_irq_reset(dev_priv);
3372
3373         for_each_pipe(dev_priv, pipe)
3374                 if (intel_display_power_is_enabled(dev_priv,
3375                                                    POWER_DOMAIN_PIPE(pipe)))
3376                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3377
3378         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3379         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3380         GEN5_IRQ_RESET(GEN8_PCU_);
3381
3382         if (HAS_PCH_SPLIT(dev))
3383                 ibx_irq_reset(dev);
3384 }
3385
3386 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3387                                      unsigned int pipe_mask)
3388 {
3389         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3390         enum pipe pipe;
3391
3392         spin_lock_irq(&dev_priv->irq_lock);
3393         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3394                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3395                                   dev_priv->de_irq_mask[pipe],
3396                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3397         spin_unlock_irq(&dev_priv->irq_lock);
3398 }
3399
3400 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3401                                      unsigned int pipe_mask)
3402 {
3403         enum pipe pipe;
3404
3405         spin_lock_irq(&dev_priv->irq_lock);
3406         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3407                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3408         spin_unlock_irq(&dev_priv->irq_lock);
3409
3410         /* make sure we're done processing display irqs */
3411         synchronize_irq(dev_priv->dev->irq);
3412 }
3413
3414 static void cherryview_irq_preinstall(struct drm_device *dev)
3415 {
3416         struct drm_i915_private *dev_priv = dev->dev_private;
3417
3418         I915_WRITE(GEN8_MASTER_IRQ, 0);
3419         POSTING_READ(GEN8_MASTER_IRQ);
3420
3421         gen8_gt_irq_reset(dev_priv);
3422
3423         GEN5_IRQ_RESET(GEN8_PCU_);
3424
3425         spin_lock_irq(&dev_priv->irq_lock);
3426         if (dev_priv->display_irqs_enabled)
3427                 vlv_display_irq_reset(dev_priv);
3428         spin_unlock_irq(&dev_priv->irq_lock);
3429 }
3430
3431 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3432                                   const u32 hpd[HPD_NUM_PINS])
3433 {
3434         struct intel_encoder *encoder;
3435         u32 enabled_irqs = 0;
3436
3437         for_each_intel_encoder(dev_priv->dev, encoder)
3438                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3439                         enabled_irqs |= hpd[encoder->hpd_pin];
3440
3441         return enabled_irqs;
3442 }
3443
3444 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3445 {
3446         u32 hotplug_irqs, hotplug, enabled_irqs;
3447
3448         if (HAS_PCH_IBX(dev_priv)) {
3449                 hotplug_irqs = SDE_HOTPLUG_MASK;
3450                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3451         } else {
3452                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3453                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3454         }
3455
3456         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3457
3458         /*
3459          * Enable digital hotplug on the PCH, and configure the DP short pulse
3460          * duration to 2ms (which is the minimum in the Display Port spec).
3461          * The pulse duration bits are reserved on LPT+.
3462          */
3463         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3464         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3465         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3466         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3467         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3468         /*
3469          * When CPU and PCH are on the same package, port A
3470          * HPD must be enabled in both north and south.
3471          */
3472         if (HAS_PCH_LPT_LP(dev_priv))
3473                 hotplug |= PORTA_HOTPLUG_ENABLE;
3474         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3475 }
3476
3477 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3478 {
3479         u32 hotplug_irqs, hotplug, enabled_irqs;
3480
3481         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3482         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3483
3484         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3485
3486         /* Enable digital hotplug on the PCH */
3487         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3488         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3489                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3490         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3491
3492         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3493         hotplug |= PORTE_HOTPLUG_ENABLE;
3494         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3495 }
3496
3497 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3498 {
3499         u32 hotplug_irqs, hotplug, enabled_irqs;
3500
3501         if (INTEL_GEN(dev_priv) >= 8) {
3502                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3503                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3504
3505                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3506         } else if (INTEL_GEN(dev_priv) >= 7) {
3507                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3508                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3509
3510                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3511         } else {
3512                 hotplug_irqs = DE_DP_A_HOTPLUG;
3513                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3514
3515                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3516         }
3517
3518         /*
3519          * Enable digital hotplug on the CPU, and configure the DP short pulse
3520          * duration to 2ms (which is the minimum in the Display Port spec)
3521          * The pulse duration bits are reserved on HSW+.
3522          */
3523         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3524         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3525         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3526         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3527
3528         ibx_hpd_irq_setup(dev_priv);
3529 }
3530
3531 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3532 {
3533         u32 hotplug_irqs, hotplug, enabled_irqs;
3534
3535         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3536         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3537
3538         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3539
3540         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3541         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3542                 PORTA_HOTPLUG_ENABLE;
3543
3544         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3545                       hotplug, enabled_irqs);
3546         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3547
3548         /*
3549          * For BXT invert bit has to be set based on AOB design
3550          * for HPD detection logic, update it based on VBT fields.
3551          */
3552
3553         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3554             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3555                 hotplug |= BXT_DDIA_HPD_INVERT;
3556         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3557             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3558                 hotplug |= BXT_DDIB_HPD_INVERT;
3559         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3560             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3561                 hotplug |= BXT_DDIC_HPD_INVERT;
3562
3563         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3564 }
3565
3566 static void ibx_irq_postinstall(struct drm_device *dev)
3567 {
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569         u32 mask;
3570
3571         if (HAS_PCH_NOP(dev))
3572                 return;
3573
3574         if (HAS_PCH_IBX(dev))
3575                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3576         else
3577                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3578
3579         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3580         I915_WRITE(SDEIMR, ~mask);
3581 }
3582
3583 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3584 {
3585         struct drm_i915_private *dev_priv = dev->dev_private;
3586         u32 pm_irqs, gt_irqs;
3587
3588         pm_irqs = gt_irqs = 0;
3589
3590         dev_priv->gt_irq_mask = ~0;
3591         if (HAS_L3_DPF(dev)) {
3592                 /* L3 parity interrupt is always unmasked. */
3593                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3594                 gt_irqs |= GT_PARITY_ERROR(dev);
3595         }
3596
3597         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3598         if (IS_GEN5(dev)) {
3599                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3600         } else {
3601                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3602         }
3603
3604         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3605
3606         if (INTEL_INFO(dev)->gen >= 6) {
3607                 /*
3608                  * RPS interrupts will get enabled/disabled on demand when RPS
3609                  * itself is enabled/disabled.
3610                  */
3611                 if (HAS_VEBOX(dev))
3612                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3613
3614                 dev_priv->pm_irq_mask = 0xffffffff;
3615                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3616         }
3617 }
3618
3619 static int ironlake_irq_postinstall(struct drm_device *dev)
3620 {
3621         struct drm_i915_private *dev_priv = dev->dev_private;
3622         u32 display_mask, extra_mask;
3623
3624         if (INTEL_INFO(dev)->gen >= 7) {
3625                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3626                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3627                                 DE_PLANEB_FLIP_DONE_IVB |
3628                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3629                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3630                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3631                               DE_DP_A_HOTPLUG_IVB);
3632         } else {
3633                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3634                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3635                                 DE_AUX_CHANNEL_A |
3636                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3637                                 DE_POISON);
3638                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3639                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3640                               DE_DP_A_HOTPLUG);
3641         }
3642
3643         dev_priv->irq_mask = ~display_mask;
3644
3645         I915_WRITE(HWSTAM, 0xeffe);
3646
3647         ibx_irq_pre_postinstall(dev);
3648
3649         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3650
3651         gen5_gt_irq_postinstall(dev);
3652
3653         ibx_irq_postinstall(dev);
3654
3655         if (IS_IRONLAKE_M(dev)) {
3656                 /* Enable PCU event interrupts
3657                  *
3658                  * spinlocking not required here for correctness since interrupt
3659                  * setup is guaranteed to run in single-threaded context. But we
3660                  * need it to make the assert_spin_locked happy. */
3661                 spin_lock_irq(&dev_priv->irq_lock);
3662                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3663                 spin_unlock_irq(&dev_priv->irq_lock);
3664         }
3665
3666         return 0;
3667 }
3668
3669 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3670 {
3671         assert_spin_locked(&dev_priv->irq_lock);
3672
3673         if (dev_priv->display_irqs_enabled)
3674                 return;
3675
3676         dev_priv->display_irqs_enabled = true;
3677
3678         if (intel_irqs_enabled(dev_priv)) {
3679                 vlv_display_irq_reset(dev_priv);
3680                 vlv_display_irq_postinstall(dev_priv);
3681         }
3682 }
3683
3684 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3685 {
3686         assert_spin_locked(&dev_priv->irq_lock);
3687
3688         if (!dev_priv->display_irqs_enabled)
3689                 return;
3690
3691         dev_priv->display_irqs_enabled = false;
3692
3693         if (intel_irqs_enabled(dev_priv))
3694                 vlv_display_irq_reset(dev_priv);
3695 }
3696
3697
3698 static int valleyview_irq_postinstall(struct drm_device *dev)
3699 {
3700         struct drm_i915_private *dev_priv = dev->dev_private;
3701
3702         gen5_gt_irq_postinstall(dev);
3703
3704         spin_lock_irq(&dev_priv->irq_lock);
3705         if (dev_priv->display_irqs_enabled)
3706                 vlv_display_irq_postinstall(dev_priv);
3707         spin_unlock_irq(&dev_priv->irq_lock);
3708
3709         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3710         POSTING_READ(VLV_MASTER_IER);
3711
3712         return 0;
3713 }
3714
3715 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3716 {
3717         /* These are interrupts we'll toggle with the ring mask register */
3718         uint32_t gt_interrupts[] = {
3719                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3720                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3721                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3722                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3723                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3724                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3725                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3726                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3727                 0,
3728                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3729                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3730                 };
3731
3732         if (HAS_L3_DPF(dev_priv))
3733                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3734
3735         dev_priv->pm_irq_mask = 0xffffffff;
3736         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3737         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3738         /*
3739          * RPS interrupts will get enabled/disabled on demand when RPS itself
3740          * is enabled/disabled.
3741          */
3742         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3743         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3744 }
3745
3746 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3747 {
3748         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3749         uint32_t de_pipe_enables;
3750         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3751         u32 de_port_enables;
3752         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3753         enum pipe pipe;
3754
3755         if (INTEL_INFO(dev_priv)->gen >= 9) {
3756                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3757                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3758                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3759                                   GEN9_AUX_CHANNEL_D;
3760                 if (IS_BROXTON(dev_priv))
3761                         de_port_masked |= BXT_DE_PORT_GMBUS;
3762         } else {
3763                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3764                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3765         }
3766
3767         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3768                                            GEN8_PIPE_FIFO_UNDERRUN;
3769
3770         de_port_enables = de_port_masked;
3771         if (IS_BROXTON(dev_priv))
3772                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3773         else if (IS_BROADWELL(dev_priv))
3774                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3775
3776         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3777         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3778         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3779
3780         for_each_pipe(dev_priv, pipe)
3781                 if (intel_display_power_is_enabled(dev_priv,
3782                                 POWER_DOMAIN_PIPE(pipe)))
3783                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3784                                           dev_priv->de_irq_mask[pipe],
3785                                           de_pipe_enables);
3786
3787         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3788         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3789 }
3790
3791 static int gen8_irq_postinstall(struct drm_device *dev)
3792 {
3793         struct drm_i915_private *dev_priv = dev->dev_private;
3794
3795         if (HAS_PCH_SPLIT(dev))
3796                 ibx_irq_pre_postinstall(dev);
3797
3798         gen8_gt_irq_postinstall(dev_priv);
3799         gen8_de_irq_postinstall(dev_priv);
3800
3801         if (HAS_PCH_SPLIT(dev))
3802                 ibx_irq_postinstall(dev);
3803
3804         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3805         POSTING_READ(GEN8_MASTER_IRQ);
3806
3807         return 0;
3808 }
3809
3810 static int cherryview_irq_postinstall(struct drm_device *dev)
3811 {
3812         struct drm_i915_private *dev_priv = dev->dev_private;
3813
3814         gen8_gt_irq_postinstall(dev_priv);
3815
3816         spin_lock_irq(&dev_priv->irq_lock);
3817         if (dev_priv->display_irqs_enabled)
3818                 vlv_display_irq_postinstall(dev_priv);
3819         spin_unlock_irq(&dev_priv->irq_lock);
3820
3821         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3822         POSTING_READ(GEN8_MASTER_IRQ);
3823
3824         return 0;
3825 }
3826
3827 static void gen8_irq_uninstall(struct drm_device *dev)
3828 {
3829         struct drm_i915_private *dev_priv = dev->dev_private;
3830
3831         if (!dev_priv)
3832                 return;
3833
3834         gen8_irq_reset(dev);
3835 }
3836
3837 static void valleyview_irq_uninstall(struct drm_device *dev)
3838 {
3839         struct drm_i915_private *dev_priv = dev->dev_private;
3840
3841         if (!dev_priv)
3842                 return;
3843
3844         I915_WRITE(VLV_MASTER_IER, 0);
3845         POSTING_READ(VLV_MASTER_IER);
3846
3847         gen5_gt_irq_reset(dev);
3848
3849         I915_WRITE(HWSTAM, 0xffffffff);
3850
3851         spin_lock_irq(&dev_priv->irq_lock);
3852         if (dev_priv->display_irqs_enabled)
3853                 vlv_display_irq_reset(dev_priv);
3854         spin_unlock_irq(&dev_priv->irq_lock);
3855 }
3856
3857 static void cherryview_irq_uninstall(struct drm_device *dev)
3858 {
3859         struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861         if (!dev_priv)
3862                 return;
3863
3864         I915_WRITE(GEN8_MASTER_IRQ, 0);
3865         POSTING_READ(GEN8_MASTER_IRQ);
3866
3867         gen8_gt_irq_reset(dev_priv);
3868
3869         GEN5_IRQ_RESET(GEN8_PCU_);
3870
3871         spin_lock_irq(&dev_priv->irq_lock);
3872         if (dev_priv->display_irqs_enabled)
3873                 vlv_display_irq_reset(dev_priv);
3874         spin_unlock_irq(&dev_priv->irq_lock);
3875 }
3876
3877 static void ironlake_irq_uninstall(struct drm_device *dev)
3878 {
3879         struct drm_i915_private *dev_priv = dev->dev_private;
3880
3881         if (!dev_priv)
3882                 return;
3883
3884         ironlake_irq_reset(dev);
3885 }
3886
3887 static void i8xx_irq_preinstall(struct drm_device * dev)
3888 {
3889         struct drm_i915_private *dev_priv = dev->dev_private;
3890         int pipe;
3891
3892         for_each_pipe(dev_priv, pipe)
3893                 I915_WRITE(PIPESTAT(pipe), 0);
3894         I915_WRITE16(IMR, 0xffff);
3895         I915_WRITE16(IER, 0x0);
3896         POSTING_READ16(IER);
3897 }
3898
3899 static int i8xx_irq_postinstall(struct drm_device *dev)
3900 {
3901         struct drm_i915_private *dev_priv = dev->dev_private;
3902
3903         I915_WRITE16(EMR,
3904                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3905
3906         /* Unmask the interrupts that we always want on. */
3907         dev_priv->irq_mask =
3908                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3909                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3910                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3911                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3912         I915_WRITE16(IMR, dev_priv->irq_mask);
3913
3914         I915_WRITE16(IER,
3915                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3916                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3917                      I915_USER_INTERRUPT);
3918         POSTING_READ16(IER);
3919
3920         /* Interrupt setup is already guaranteed to be single-threaded, this is
3921          * just to make the assert_spin_locked check happy. */
3922         spin_lock_irq(&dev_priv->irq_lock);
3923         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3924         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3925         spin_unlock_irq(&dev_priv->irq_lock);
3926
3927         return 0;
3928 }
3929
3930 /*
3931  * Returns true when a page flip has completed.
3932  */
3933 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3934                                int plane, int pipe, u32 iir)
3935 {
3936         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3937
3938         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3939                 return false;
3940
3941         if ((iir & flip_pending) == 0)
3942                 goto check_page_flip;
3943
3944         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3945          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3946          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3947          * the flip is completed (no longer pending). Since this doesn't raise
3948          * an interrupt per se, we watch for the change at vblank.
3949          */
3950         if (I915_READ16(ISR) & flip_pending)
3951                 goto check_page_flip;
3952
3953         intel_finish_page_flip_cs(dev_priv, pipe);
3954         return true;
3955
3956 check_page_flip:
3957         intel_check_page_flip(dev_priv, pipe);
3958         return false;
3959 }
3960
3961 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3962 {
3963         struct drm_device *dev = arg;
3964         struct drm_i915_private *dev_priv = dev->dev_private;
3965         u16 iir, new_iir;
3966         u32 pipe_stats[2];
3967         int pipe;
3968         u16 flip_mask =
3969                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3970                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3971         irqreturn_t ret;
3972
3973         if (!intel_irqs_enabled(dev_priv))
3974                 return IRQ_NONE;
3975
3976         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3977         disable_rpm_wakeref_asserts(dev_priv);
3978
3979         ret = IRQ_NONE;
3980         iir = I915_READ16(IIR);
3981         if (iir == 0)
3982                 goto out;
3983
3984         while (iir & ~flip_mask) {
3985                 /* Can't rely on pipestat interrupt bit in iir as it might
3986                  * have been cleared after the pipestat interrupt was received.
3987                  * It doesn't set the bit in iir again, but it still produces
3988                  * interrupts (for non-MSI).
3989                  */
3990                 spin_lock(&dev_priv->irq_lock);
3991                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3992                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3993
3994                 for_each_pipe(dev_priv, pipe) {
3995                         i915_reg_t reg = PIPESTAT(pipe);
3996                         pipe_stats[pipe] = I915_READ(reg);
3997
3998                         /*
3999                          * Clear the PIPE*STAT regs before the IIR
4000                          */
4001                         if (pipe_stats[pipe] & 0x8000ffff)
4002                                 I915_WRITE(reg, pipe_stats[pipe]);
4003                 }
4004                 spin_unlock(&dev_priv->irq_lock);
4005
4006                 I915_WRITE16(IIR, iir & ~flip_mask);
4007                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4008
4009                 if (iir & I915_USER_INTERRUPT)
4010                         notify_ring(&dev_priv->engine[RCS]);
4011
4012                 for_each_pipe(dev_priv, pipe) {
4013                         int plane = pipe;
4014                         if (HAS_FBC(dev_priv))
4015                                 plane = !plane;
4016
4017                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4018                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4019                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4020
4021                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4022                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4023
4024                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4025                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4026                                                                     pipe);
4027                 }
4028
4029                 iir = new_iir;
4030         }
4031         ret = IRQ_HANDLED;
4032
4033 out:
4034         enable_rpm_wakeref_asserts(dev_priv);
4035
4036         return ret;
4037 }
4038
4039 static void i8xx_irq_uninstall(struct drm_device * dev)
4040 {
4041         struct drm_i915_private *dev_priv = dev->dev_private;
4042         int pipe;
4043
4044         for_each_pipe(dev_priv, pipe) {
4045                 /* Clear enable bits; then clear status bits */
4046                 I915_WRITE(PIPESTAT(pipe), 0);
4047                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4048         }
4049         I915_WRITE16(IMR, 0xffff);
4050         I915_WRITE16(IER, 0x0);
4051         I915_WRITE16(IIR, I915_READ16(IIR));
4052 }
4053
4054 static void i915_irq_preinstall(struct drm_device * dev)
4055 {
4056         struct drm_i915_private *dev_priv = dev->dev_private;
4057         int pipe;
4058
4059         if (I915_HAS_HOTPLUG(dev)) {
4060                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4061                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4062         }
4063
4064         I915_WRITE16(HWSTAM, 0xeffe);
4065         for_each_pipe(dev_priv, pipe)
4066                 I915_WRITE(PIPESTAT(pipe), 0);
4067         I915_WRITE(IMR, 0xffffffff);
4068         I915_WRITE(IER, 0x0);
4069         POSTING_READ(IER);
4070 }
4071
4072 static int i915_irq_postinstall(struct drm_device *dev)
4073 {
4074         struct drm_i915_private *dev_priv = dev->dev_private;
4075         u32 enable_mask;
4076
4077         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4078
4079         /* Unmask the interrupts that we always want on. */
4080         dev_priv->irq_mask =
4081                 ~(I915_ASLE_INTERRUPT |
4082                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4083                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4084                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4085                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4086
4087         enable_mask =
4088                 I915_ASLE_INTERRUPT |
4089                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4090                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4091                 I915_USER_INTERRUPT;
4092
4093         if (I915_HAS_HOTPLUG(dev)) {
4094                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4095                 POSTING_READ(PORT_HOTPLUG_EN);
4096
4097                 /* Enable in IER... */
4098                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4099                 /* and unmask in IMR */
4100                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4101         }
4102
4103         I915_WRITE(IMR, dev_priv->irq_mask);
4104         I915_WRITE(IER, enable_mask);
4105         POSTING_READ(IER);
4106
4107         i915_enable_asle_pipestat(dev_priv);
4108
4109         /* Interrupt setup is already guaranteed to be single-threaded, this is
4110          * just to make the assert_spin_locked check happy. */
4111         spin_lock_irq(&dev_priv->irq_lock);
4112         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4113         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4114         spin_unlock_irq(&dev_priv->irq_lock);
4115
4116         return 0;
4117 }
4118
4119 /*
4120  * Returns true when a page flip has completed.
4121  */
4122 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4123                                int plane, int pipe, u32 iir)
4124 {
4125         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4126
4127         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4128                 return false;
4129
4130         if ((iir & flip_pending) == 0)
4131                 goto check_page_flip;
4132
4133         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4134          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4135          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4136          * the flip is completed (no longer pending). Since this doesn't raise
4137          * an interrupt per se, we watch for the change at vblank.
4138          */
4139         if (I915_READ(ISR) & flip_pending)
4140                 goto check_page_flip;
4141
4142         intel_finish_page_flip_cs(dev_priv, pipe);
4143         return true;
4144
4145 check_page_flip:
4146         intel_check_page_flip(dev_priv, pipe);
4147         return false;
4148 }
4149
4150 static irqreturn_t i915_irq_handler(int irq, void *arg)
4151 {
4152         struct drm_device *dev = arg;
4153         struct drm_i915_private *dev_priv = dev->dev_private;
4154         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4155         u32 flip_mask =
4156                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4157                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4158         int pipe, ret = IRQ_NONE;
4159
4160         if (!intel_irqs_enabled(dev_priv))
4161                 return IRQ_NONE;
4162
4163         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4164         disable_rpm_wakeref_asserts(dev_priv);
4165
4166         iir = I915_READ(IIR);
4167         do {
4168                 bool irq_received = (iir & ~flip_mask) != 0;
4169                 bool blc_event = false;
4170
4171                 /* Can't rely on pipestat interrupt bit in iir as it might
4172                  * have been cleared after the pipestat interrupt was received.
4173                  * It doesn't set the bit in iir again, but it still produces
4174                  * interrupts (for non-MSI).
4175                  */
4176                 spin_lock(&dev_priv->irq_lock);
4177                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4178                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4179
4180                 for_each_pipe(dev_priv, pipe) {
4181                         i915_reg_t reg = PIPESTAT(pipe);
4182                         pipe_stats[pipe] = I915_READ(reg);
4183
4184                         /* Clear the PIPE*STAT regs before the IIR */
4185                         if (pipe_stats[pipe] & 0x8000ffff) {
4186                                 I915_WRITE(reg, pipe_stats[pipe]);
4187                                 irq_received = true;
4188                         }
4189                 }
4190                 spin_unlock(&dev_priv->irq_lock);
4191
4192                 if (!irq_received)
4193                         break;
4194
4195                 /* Consume port.  Then clear IIR or we'll miss events */
4196                 if (I915_HAS_HOTPLUG(dev_priv) &&
4197                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4198                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4199                         if (hotplug_status)
4200                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4201                 }
4202
4203                 I915_WRITE(IIR, iir & ~flip_mask);
4204                 new_iir = I915_READ(IIR); /* Flush posted writes */
4205
4206                 if (iir & I915_USER_INTERRUPT)
4207                         notify_ring(&dev_priv->engine[RCS]);
4208
4209                 for_each_pipe(dev_priv, pipe) {
4210                         int plane = pipe;
4211                         if (HAS_FBC(dev_priv))
4212                                 plane = !plane;
4213
4214                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4215                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4216                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4217
4218                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4219                                 blc_event = true;
4220
4221                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4222                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4223
4224                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4225                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4226                                                                     pipe);
4227                 }
4228
4229                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4230                         intel_opregion_asle_intr(dev_priv);
4231
4232                 /* With MSI, interrupts are only generated when iir
4233                  * transitions from zero to nonzero.  If another bit got
4234                  * set while we were handling the existing iir bits, then
4235                  * we would never get another interrupt.
4236                  *
4237                  * This is fine on non-MSI as well, as if we hit this path
4238                  * we avoid exiting the interrupt handler only to generate
4239                  * another one.
4240                  *
4241                  * Note that for MSI this could cause a stray interrupt report
4242                  * if an interrupt landed in the time between writing IIR and
4243                  * the posting read.  This should be rare enough to never
4244                  * trigger the 99% of 100,000 interrupts test for disabling
4245                  * stray interrupts.
4246                  */
4247                 ret = IRQ_HANDLED;
4248                 iir = new_iir;
4249         } while (iir & ~flip_mask);
4250
4251         enable_rpm_wakeref_asserts(dev_priv);
4252
4253         return ret;
4254 }
4255
4256 static void i915_irq_uninstall(struct drm_device * dev)
4257 {
4258         struct drm_i915_private *dev_priv = dev->dev_private;
4259         int pipe;
4260
4261         if (I915_HAS_HOTPLUG(dev)) {
4262                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4263                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4264         }
4265
4266         I915_WRITE16(HWSTAM, 0xffff);
4267         for_each_pipe(dev_priv, pipe) {
4268                 /* Clear enable bits; then clear status bits */
4269                 I915_WRITE(PIPESTAT(pipe), 0);
4270                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4271         }
4272         I915_WRITE(IMR, 0xffffffff);
4273         I915_WRITE(IER, 0x0);
4274
4275         I915_WRITE(IIR, I915_READ(IIR));
4276 }
4277
4278 static void i965_irq_preinstall(struct drm_device * dev)
4279 {
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281         int pipe;
4282
4283         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4284         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4285
4286         I915_WRITE(HWSTAM, 0xeffe);
4287         for_each_pipe(dev_priv, pipe)
4288                 I915_WRITE(PIPESTAT(pipe), 0);
4289         I915_WRITE(IMR, 0xffffffff);
4290         I915_WRITE(IER, 0x0);
4291         POSTING_READ(IER);
4292 }
4293
4294 static int i965_irq_postinstall(struct drm_device *dev)
4295 {
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297         u32 enable_mask;
4298         u32 error_mask;
4299
4300         /* Unmask the interrupts that we always want on. */
4301         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4302                                I915_DISPLAY_PORT_INTERRUPT |
4303                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4304                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4305                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4306                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4307                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4308
4309         enable_mask = ~dev_priv->irq_mask;
4310         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4311                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4312         enable_mask |= I915_USER_INTERRUPT;
4313
4314         if (IS_G4X(dev_priv))
4315                 enable_mask |= I915_BSD_USER_INTERRUPT;
4316
4317         /* Interrupt setup is already guaranteed to be single-threaded, this is
4318          * just to make the assert_spin_locked check happy. */
4319         spin_lock_irq(&dev_priv->irq_lock);
4320         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4321         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4322         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4323         spin_unlock_irq(&dev_priv->irq_lock);
4324
4325         /*
4326          * Enable some error detection, note the instruction error mask
4327          * bit is reserved, so we leave it masked.
4328          */
4329         if (IS_G4X(dev_priv)) {
4330                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4331                                GM45_ERROR_MEM_PRIV |
4332                                GM45_ERROR_CP_PRIV |
4333                                I915_ERROR_MEMORY_REFRESH);
4334         } else {
4335                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4336                                I915_ERROR_MEMORY_REFRESH);
4337         }
4338         I915_WRITE(EMR, error_mask);
4339
4340         I915_WRITE(IMR, dev_priv->irq_mask);
4341         I915_WRITE(IER, enable_mask);
4342         POSTING_READ(IER);
4343
4344         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4345         POSTING_READ(PORT_HOTPLUG_EN);
4346
4347         i915_enable_asle_pipestat(dev_priv);
4348
4349         return 0;
4350 }
4351
4352 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4353 {
4354         u32 hotplug_en;
4355
4356         assert_spin_locked(&dev_priv->irq_lock);
4357
4358         /* Note HDMI and DP share hotplug bits */
4359         /* enable bits are the same for all generations */
4360         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4361         /* Programming the CRT detection parameters tends
4362            to generate a spurious hotplug event about three
4363            seconds later.  So just do it once.
4364         */
4365         if (IS_G4X(dev_priv))
4366                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4367         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4368
4369         /* Ignore TV since it's buggy */
4370         i915_hotplug_interrupt_update_locked(dev_priv,
4371                                              HOTPLUG_INT_EN_MASK |
4372                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4373                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4374                                              hotplug_en);
4375 }
4376
4377 static irqreturn_t i965_irq_handler(int irq, void *arg)
4378 {
4379         struct drm_device *dev = arg;
4380         struct drm_i915_private *dev_priv = dev->dev_private;
4381         u32 iir, new_iir;
4382         u32 pipe_stats[I915_MAX_PIPES];
4383         int ret = IRQ_NONE, pipe;
4384         u32 flip_mask =
4385                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4386                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4387
4388         if (!intel_irqs_enabled(dev_priv))
4389                 return IRQ_NONE;
4390
4391         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4392         disable_rpm_wakeref_asserts(dev_priv);
4393
4394         iir = I915_READ(IIR);
4395
4396         for (;;) {
4397                 bool irq_received = (iir & ~flip_mask) != 0;
4398                 bool blc_event = false;
4399
4400                 /* Can't rely on pipestat interrupt bit in iir as it might
4401                  * have been cleared after the pipestat interrupt was received.
4402                  * It doesn't set the bit in iir again, but it still produces
4403                  * interrupts (for non-MSI).
4404                  */
4405                 spin_lock(&dev_priv->irq_lock);
4406                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4407                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4408
4409                 for_each_pipe(dev_priv, pipe) {
4410                         i915_reg_t reg = PIPESTAT(pipe);
4411                         pipe_stats[pipe] = I915_READ(reg);
4412
4413                         /*
4414                          * Clear the PIPE*STAT regs before the IIR
4415                          */
4416                         if (pipe_stats[pipe] & 0x8000ffff) {
4417                                 I915_WRITE(reg, pipe_stats[pipe]);
4418                                 irq_received = true;
4419                         }
4420                 }
4421                 spin_unlock(&dev_priv->irq_lock);
4422
4423                 if (!irq_received)
4424                         break;
4425
4426                 ret = IRQ_HANDLED;
4427
4428                 /* Consume port.  Then clear IIR or we'll miss events */
4429                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4430                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4431                         if (hotplug_status)
4432                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4433                 }
4434
4435                 I915_WRITE(IIR, iir & ~flip_mask);
4436                 new_iir = I915_READ(IIR); /* Flush posted writes */
4437
4438                 if (iir & I915_USER_INTERRUPT)
4439                         notify_ring(&dev_priv->engine[RCS]);
4440                 if (iir & I915_BSD_USER_INTERRUPT)
4441                         notify_ring(&dev_priv->engine[VCS]);
4442
4443                 for_each_pipe(dev_priv, pipe) {
4444                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4445                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4446                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4447
4448                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4449                                 blc_event = true;
4450
4451                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4452                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4453
4454                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4455                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4456                 }
4457
4458                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4459                         intel_opregion_asle_intr(dev_priv);
4460
4461                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4462                         gmbus_irq_handler(dev_priv);
4463
4464                 /* With MSI, interrupts are only generated when iir
4465                  * transitions from zero to nonzero.  If another bit got
4466                  * set while we were handling the existing iir bits, then
4467                  * we would never get another interrupt.
4468                  *
4469                  * This is fine on non-MSI as well, as if we hit this path
4470                  * we avoid exiting the interrupt handler only to generate
4471                  * another one.
4472                  *
4473                  * Note that for MSI this could cause a stray interrupt report
4474                  * if an interrupt landed in the time between writing IIR and
4475                  * the posting read.  This should be rare enough to never
4476                  * trigger the 99% of 100,000 interrupts test for disabling
4477                  * stray interrupts.
4478                  */
4479                 iir = new_iir;
4480         }
4481
4482         enable_rpm_wakeref_asserts(dev_priv);
4483
4484         return ret;
4485 }
4486
4487 static void i965_irq_uninstall(struct drm_device * dev)
4488 {
4489         struct drm_i915_private *dev_priv = dev->dev_private;
4490         int pipe;
4491
4492         if (!dev_priv)
4493                 return;
4494
4495         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4496         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4497
4498         I915_WRITE(HWSTAM, 0xffffffff);
4499         for_each_pipe(dev_priv, pipe)
4500                 I915_WRITE(PIPESTAT(pipe), 0);
4501         I915_WRITE(IMR, 0xffffffff);
4502         I915_WRITE(IER, 0x0);
4503
4504         for_each_pipe(dev_priv, pipe)
4505                 I915_WRITE(PIPESTAT(pipe),
4506                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4507         I915_WRITE(IIR, I915_READ(IIR));
4508 }
4509
4510 /**
4511  * intel_irq_init - initializes irq support
4512  * @dev_priv: i915 device instance
4513  *
4514  * This function initializes all the irq support including work items, timers
4515  * and all the vtables. It does not setup the interrupt itself though.
4516  */
4517 void intel_irq_init(struct drm_i915_private *dev_priv)
4518 {
4519         struct drm_device *dev = dev_priv->dev;
4520
4521         intel_hpd_init_work(dev_priv);
4522
4523         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4524         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4525
4526         /* Let's track the enabled rps events */
4527         if (IS_VALLEYVIEW(dev_priv))
4528                 /* WaGsvRC0ResidencyMethod:vlv */
4529                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4530         else
4531                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4532
4533         dev_priv->rps.pm_intr_keep = 0;
4534
4535         /*
4536          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4537          * if GEN6_PM_UP_EI_EXPIRED is masked.
4538          *
4539          * TODO: verify if this can be reproduced on VLV,CHV.
4540          */
4541         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4542                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4543
4544         if (INTEL_INFO(dev_priv)->gen >= 8)
4545                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4546
4547         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4548                           i915_hangcheck_elapsed);
4549
4550         if (IS_GEN2(dev_priv)) {
4551                 dev->max_vblank_count = 0;
4552                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4553         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4554                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4555                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4556         } else {
4557                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4558                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4559         }
4560
4561         /*
4562          * Opt out of the vblank disable timer on everything except gen2.
4563          * Gen2 doesn't have a hardware frame counter and so depends on
4564          * vblank interrupts to produce sane vblank seuquence numbers.
4565          */
4566         if (!IS_GEN2(dev_priv))
4567                 dev->vblank_disable_immediate = true;
4568
4569         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4570         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4571
4572         if (IS_CHERRYVIEW(dev_priv)) {
4573                 dev->driver->irq_handler = cherryview_irq_handler;
4574                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4575                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4576                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4577                 dev->driver->enable_vblank = valleyview_enable_vblank;
4578                 dev->driver->disable_vblank = valleyview_disable_vblank;
4579                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4580         } else if (IS_VALLEYVIEW(dev_priv)) {
4581                 dev->driver->irq_handler = valleyview_irq_handler;
4582                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4583                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4584                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4585                 dev->driver->enable_vblank = valleyview_enable_vblank;
4586                 dev->driver->disable_vblank = valleyview_disable_vblank;
4587                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4588         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4589                 dev->driver->irq_handler = gen8_irq_handler;
4590                 dev->driver->irq_preinstall = gen8_irq_reset;
4591                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4592                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4593                 dev->driver->enable_vblank = gen8_enable_vblank;
4594                 dev->driver->disable_vblank = gen8_disable_vblank;
4595                 if (IS_BROXTON(dev))
4596                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4597                 else if (HAS_PCH_SPT(dev))
4598                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4599                 else
4600                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4601         } else if (HAS_PCH_SPLIT(dev)) {
4602                 dev->driver->irq_handler = ironlake_irq_handler;
4603                 dev->driver->irq_preinstall = ironlake_irq_reset;
4604                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4605                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4606                 dev->driver->enable_vblank = ironlake_enable_vblank;
4607                 dev->driver->disable_vblank = ironlake_disable_vblank;
4608                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4609         } else {
4610                 if (IS_GEN2(dev_priv)) {
4611                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4612                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4613                         dev->driver->irq_handler = i8xx_irq_handler;
4614                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4615                 } else if (IS_GEN3(dev_priv)) {
4616                         dev->driver->irq_preinstall = i915_irq_preinstall;
4617                         dev->driver->irq_postinstall = i915_irq_postinstall;
4618                         dev->driver->irq_uninstall = i915_irq_uninstall;
4619                         dev->driver->irq_handler = i915_irq_handler;
4620                 } else {
4621                         dev->driver->irq_preinstall = i965_irq_preinstall;
4622                         dev->driver->irq_postinstall = i965_irq_postinstall;
4623                         dev->driver->irq_uninstall = i965_irq_uninstall;
4624                         dev->driver->irq_handler = i965_irq_handler;
4625                 }
4626                 if (I915_HAS_HOTPLUG(dev_priv))
4627                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4628                 dev->driver->enable_vblank = i915_enable_vblank;
4629                 dev->driver->disable_vblank = i915_disable_vblank;
4630         }
4631 }
4632
4633 /**
4634  * intel_irq_install - enables the hardware interrupt
4635  * @dev_priv: i915 device instance
4636  *
4637  * This function enables the hardware interrupt handling, but leaves the hotplug
4638  * handling still disabled. It is called after intel_irq_init().
4639  *
4640  * In the driver load and resume code we need working interrupts in a few places
4641  * but don't want to deal with the hassle of concurrent probe and hotplug
4642  * workers. Hence the split into this two-stage approach.
4643  */
4644 int intel_irq_install(struct drm_i915_private *dev_priv)
4645 {
4646         /*
4647          * We enable some interrupt sources in our postinstall hooks, so mark
4648          * interrupts as enabled _before_ actually enabling them to avoid
4649          * special cases in our ordering checks.
4650          */
4651         dev_priv->pm.irqs_enabled = true;
4652
4653         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4654 }
4655
4656 /**
4657  * intel_irq_uninstall - finilizes all irq handling
4658  * @dev_priv: i915 device instance
4659  *
4660  * This stops interrupt and hotplug handling and unregisters and frees all
4661  * resources acquired in the init functions.
4662  */
4663 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4664 {
4665         drm_irq_uninstall(dev_priv->dev);
4666         intel_hpd_cancel_work(dev_priv);
4667         dev_priv->pm.irqs_enabled = false;
4668 }
4669
4670 /**
4671  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4672  * @dev_priv: i915 device instance
4673  *
4674  * This function is used to disable interrupts at runtime, both in the runtime
4675  * pm and the system suspend/resume code.
4676  */
4677 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4678 {
4679         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4680         dev_priv->pm.irqs_enabled = false;
4681         synchronize_irq(dev_priv->dev->irq);
4682 }
4683
4684 /**
4685  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4686  * @dev_priv: i915 device instance
4687  *
4688  * This function is used to enable interrupts at runtime, both in the runtime
4689  * pm and the system suspend/resume code.
4690  */
4691 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4692 {
4693         dev_priv->pm.irqs_enabled = true;
4694         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4695         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4696 }