drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  50         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  51         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  52         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  53 };
  54
  55 static const u32 hpd_mask_i915[] = {
  56         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  57         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  58         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  59         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  60         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  61         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  62 };
  63
  64 static const u32 hpd_status_gen4[] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  71 };
  72
  73 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  74         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  76         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  77         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 /* For display hotplug interrupt */
  83 static void
  84 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  85 {
  86         assert_spin_locked(&dev_priv->irq_lock);
  87
  88         if (dev_priv->pc8.irqs_disabled) {
  89                 WARN(1, "IRQs disabled\n");
  90                 dev_priv->pc8.regsave.deimr &= ~mask;
  91                 return;
  92         }
  93
  94         if ((dev_priv->irq_mask & mask) != 0) {
  95                 dev_priv->irq_mask &= ~mask;
  96                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  97                 POSTING_READ(DEIMR);
  98         }
  99 }
 100
 101 static void
 102 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 103 {
 104         assert_spin_locked(&dev_priv->irq_lock);
 105
 106         if (dev_priv->pc8.irqs_disabled) {
 107                 WARN(1, "IRQs disabled\n");
 108                 dev_priv->pc8.regsave.deimr |= mask;
 109                 return;
 110         }
 111
 112         if ((dev_priv->irq_mask & mask) != mask) {
 113                 dev_priv->irq_mask |= mask;
 114                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 115                 POSTING_READ(DEIMR);
 116         }
 117 }
 118
 119 /**
 120  * ilk_update_gt_irq - update GTIMR
 121  * @dev_priv: driver private
 122  * @interrupt_mask: mask of interrupt bits to update
 123  * @enabled_irq_mask: mask of interrupt bits to enable
 124  */
 125 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 126                               uint32_t interrupt_mask,
 127                               uint32_t enabled_irq_mask)
 128 {
 129         assert_spin_locked(&dev_priv->irq_lock);
 130
 131         if (dev_priv->pc8.irqs_disabled) {
 132                 WARN(1, "IRQs disabled\n");
 133                 dev_priv->pc8.regsave.gtimr &= ~interrupt_mask;
 134                 dev_priv->pc8.regsave.gtimr |= (~enabled_irq_mask &
 135                                                 interrupt_mask);
 136                 return;
 137         }
 138
 139         dev_priv->gt_irq_mask &= ~interrupt_mask;
 140         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 141         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 142         POSTING_READ(GTIMR);
 143 }
 144
 145 void ilk_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 146 {
 147         ilk_update_gt_irq(dev_priv, mask, mask);
 148 }
 149
 150 void ilk_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 151 {
 152         ilk_update_gt_irq(dev_priv, mask, 0);
 153 }
 154
 155 /**
 156   * snb_update_pm_irq - update GEN6_PMIMR
 157   * @dev_priv: driver private
 158   * @interrupt_mask: mask of interrupt bits to update
 159   * @enabled_irq_mask: mask of interrupt bits to enable
 160   */
 161 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 162                               uint32_t interrupt_mask,
 163                               uint32_t enabled_irq_mask)
 164 {
 165         uint32_t new_val;
 166
 167         assert_spin_locked(&dev_priv->irq_lock);
 168
 169         if (dev_priv->pc8.irqs_disabled) {
 170                 WARN(1, "IRQs disabled\n");
 171                 dev_priv->pc8.regsave.gen6_pmimr &= ~interrupt_mask;
 172                 dev_priv->pc8.regsave.gen6_pmimr |= (~enabled_irq_mask &
 173                                                      interrupt_mask);
 174                 return;
 175         }
 176
 177         new_val = dev_priv->pm_irq_mask;
 178         new_val &= ~interrupt_mask;
 179         new_val |= (~enabled_irq_mask & interrupt_mask);
 180
 181         if (new_val != dev_priv->pm_irq_mask) {
 182                 dev_priv->pm_irq_mask = new_val;
 183                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 184                 POSTING_READ(GEN6_PMIMR);
 185         }
 186 }
 187
 188 void snb_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 189 {
 190         snb_update_pm_irq(dev_priv, mask, mask);
 191 }
 192
 193 void snb_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 194 {
 195         snb_update_pm_irq(dev_priv, mask, 0);
 196 }
 197
 198 static bool ivb_can_enable_err_int(struct drm_device *dev)
 199 {
 200         struct drm_i915_private *dev_priv = dev->dev_private;
 201         struct intel_crtc *crtc;
 202         enum pipe pipe;
 203
 204         assert_spin_locked(&dev_priv->irq_lock);
 205
 206         for_each_pipe(pipe) {
 207                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 208
 209                 if (crtc->cpu_fifo_underrun_disabled)
 210                         return false;
 211         }
 212
 213         return true;
 214 }
 215
 216 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 217 {
 218         struct drm_i915_private *dev_priv = dev->dev_private;
 219         enum pipe pipe;
 220         struct intel_crtc *crtc;
 221
 222         assert_spin_locked(&dev_priv->irq_lock);
 223
 224         for_each_pipe(pipe) {
 225                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 226
 227                 if (crtc->pch_fifo_underrun_disabled)
 228                         return false;
 229         }
 230
 231         return true;
 232 }
 233
 234 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 235                                                  enum pipe pipe, bool enable)
 236 {
 237         struct drm_i915_private *dev_priv = dev->dev_private;
 238         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 239                                           DE_PIPEB_FIFO_UNDERRUN;
 240
 241         if (enable)
 242                 ironlake_enable_display_irq(dev_priv, bit);
 243         else
 244                 ironlake_disable_display_irq(dev_priv, bit);
 245 }
 246
 247 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 248                                                   enum pipe pipe, bool enable)
 249 {
 250         struct drm_i915_private *dev_priv = dev->dev_private;
 251         if (enable) {
 252                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 253
 254                 if (!ivb_can_enable_err_int(dev))
 255                         return;
 256
 257                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 258         } else {
 259                 bool was_enabled = !(I915_READ(DEIMR) & DE_ERR_INT_IVB);
 260
 261                 /* Change the state _after_ we've read out the current one. */
 262                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 263
 264                 if (!was_enabled &&
 265                     (I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe))) {
 266                         DRM_DEBUG_KMS("uncleared fifo underrun on pipe %c\n",
 267                                       pipe_name(pipe));
 268                 }
 269         }
 270 }
 271
 272 /**
 273  * ibx_display_interrupt_update - update SDEIMR
 274  * @dev_priv: driver private
 275  * @interrupt_mask: mask of interrupt bits to update
 276  * @enabled_irq_mask: mask of interrupt bits to enable
 277  */
 278 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 279                                          uint32_t interrupt_mask,
 280                                          uint32_t enabled_irq_mask)
 281 {
 282         uint32_t sdeimr = I915_READ(SDEIMR);
 283         sdeimr &= ~interrupt_mask;
 284         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 285
 286         assert_spin_locked(&dev_priv->irq_lock);
 287
 288         if (dev_priv->pc8.irqs_disabled &&
 289             (interrupt_mask & SDE_HOTPLUG_MASK_CPT)) {
 290                 WARN(1, "IRQs disabled\n");
 291                 dev_priv->pc8.regsave.sdeimr &= ~interrupt_mask;
 292                 dev_priv->pc8.regsave.sdeimr |= (~enabled_irq_mask &
 293                                                  interrupt_mask);
 294                 return;
 295         }
 296
 297         I915_WRITE(SDEIMR, sdeimr);
 298         POSTING_READ(SDEIMR);
 299 }
 300 #define ibx_enable_display_interrupt(dev_priv, bits) \
 301         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 302 #define ibx_disable_display_interrupt(dev_priv, bits) \
 303         ibx_display_interrupt_update((dev_priv), (bits), 0)
 304
 305 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 306                                             enum transcoder pch_transcoder,
 307                                             bool enable)
 308 {
 309         struct drm_i915_private *dev_priv = dev->dev_private;
 310         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 311                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 312
 313         if (enable)
 314                 ibx_enable_display_interrupt(dev_priv, bit);
 315         else
 316                 ibx_disable_display_interrupt(dev_priv, bit);
 317 }
 318
 319 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 320                                             enum transcoder pch_transcoder,
 321                                             bool enable)
 322 {
 323         struct drm_i915_private *dev_priv = dev->dev_private;
 324
 325         if (enable) {
 326                 I915_WRITE(SERR_INT,
 327                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 328
 329                 if (!cpt_can_enable_serr_int(dev))
 330                         return;
 331
 332                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 333         } else {
 334                 uint32_t tmp = I915_READ(SERR_INT);
 335                 bool was_enabled = !(I915_READ(SDEIMR) & SDE_ERROR_CPT);
 336
 337                 /* Change the state _after_ we've read out the current one. */
 338                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 339
 340                 if (!was_enabled &&
 341                     (tmp & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder))) {
 342                         DRM_DEBUG_KMS("uncleared pch fifo underrun on pch transcoder %c\n",
 343                                       transcoder_name(pch_transcoder));
 344                 }
 345         }
 346 }
 347
 348 /**
 349  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 350  * @dev: drm device
 351  * @pipe: pipe
 352  * @enable: true if we want to report FIFO underrun errors, false otherwise
 353  *
 354  * This function makes us disable or enable CPU fifo underruns for a specific
 355  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 356  * reporting for one pipe may also disable all the other CPU error interruts for
 357  * the other pipes, due to the fact that there's just one interrupt mask/enable
 358  * bit for all the pipes.
 359  *
 360  * Returns the previous state of underrun reporting.
 361  */
 362 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 363                                            enum pipe pipe, bool enable)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 368         unsigned long flags;
 369         bool ret;
 370
 371         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 372
 373         ret = !intel_crtc->cpu_fifo_underrun_disabled;
 374
 375         if (enable == ret)
 376                 goto done;
 377
 378         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 379
 380         if (IS_GEN5(dev) || IS_GEN6(dev))
 381                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 382         else if (IS_GEN7(dev))
 383                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable);
 384
 385 done:
 386         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 387         return ret;
 388 }
 389
 390 /**
 391  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 392  * @dev: drm device
 393  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 394  * @enable: true if we want to report FIFO underrun errors, false otherwise
 395  *
 396  * This function makes us disable or enable PCH fifo underruns for a specific
 397  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 398  * underrun reporting for one transcoder may also disable all the other PCH
 399  * error interruts for the other transcoders, due to the fact that there's just
 400  * one interrupt mask/enable bit for all the transcoders.
 401  *
 402  * Returns the previous state of underrun reporting.
 403  */
 404 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 405                                            enum transcoder pch_transcoder,
 406                                            bool enable)
 407 {
 408         struct drm_i915_private *dev_priv = dev->dev_private;
 409         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 410         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 411         unsigned long flags;
 412         bool ret;
 413
 414         /*
 415          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 416          * has only one pch transcoder A that all pipes can use. To avoid racy
 417          * pch transcoder -> pipe lookups from interrupt code simply store the
 418          * underrun statistics in crtc A. Since we never expose this anywhere
 419          * nor use it outside of the fifo underrun code here using the "wrong"
 420          * crtc on LPT won't cause issues.
 421          */
 422
 423         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 424
 425         ret = !intel_crtc->pch_fifo_underrun_disabled;
 426
 427         if (enable == ret)
 428                 goto done;
 429
 430         intel_crtc->pch_fifo_underrun_disabled = !enable;
 431
 432         if (HAS_PCH_IBX(dev))
 433                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 434         else
 435                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 436
 437 done:
 438         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 439         return ret;
 440 }
 441
 442
 443 void
 444 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 445 {
 446         u32 reg = PIPESTAT(pipe);
 447         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 448
 449         assert_spin_locked(&dev_priv->irq_lock);
 450
 451         if ((pipestat & mask) == mask)
 452                 return;
 453
 454         /* Enable the interrupt, clear any pending status */
 455         pipestat |= mask | (mask >> 16);
 456         I915_WRITE(reg, pipestat);
 457         POSTING_READ(reg);
 458 }
 459
 460 void
 461 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 462 {
 463         u32 reg = PIPESTAT(pipe);
 464         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 465
 466         assert_spin_locked(&dev_priv->irq_lock);
 467
 468         if ((pipestat & mask) == 0)
 469                 return;
 470
 471         pipestat &= ~mask;
 472         I915_WRITE(reg, pipestat);
 473         POSTING_READ(reg);
 474 }
 475
 476 /**
 477  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 478  */
 479 static void i915_enable_asle_pipestat(struct drm_device *dev)
 480 {
 481         drm_i915_private_t *dev_priv = dev->dev_private;
 482         unsigned long irqflags;
 483
 484         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 485                 return;
 486
 487         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 488
 489         i915_enable_pipestat(dev_priv, 1, PIPE_LEGACY_BLC_EVENT_ENABLE);
 490         if (INTEL_INFO(dev)->gen >= 4)
 491                 i915_enable_pipestat(dev_priv, 0, PIPE_LEGACY_BLC_EVENT_ENABLE);
 492
 493         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 494 }
 495
 496 /**
 497  * i915_pipe_enabled - check if a pipe is enabled
 498  * @dev: DRM device
 499  * @pipe: pipe to check
 500  *
 501  * Reading certain registers when the pipe is disabled can hang the chip.
 502  * Use this routine to make sure the PLL is running and the pipe is active
 503  * before reading such registers if unsure.
 504  */
 505 static int
 506 i915_pipe_enabled(struct drm_device *dev, int pipe)
 507 {
 508         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 509
 510         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 511                 /* Locking is horribly broken here, but whatever. */
 512                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 513                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 514
 515                 return intel_crtc->active;
 516         } else {
 517                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 518         }
 519 }
 520
 521 /* Called from drm generic code, passed a 'crtc', which
 522  * we use as a pipe index
 523  */
 524 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 525 {
 526         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 527         unsigned long high_frame;
 528         unsigned long low_frame;
 529         u32 high1, high2, low;
 530
 531         if (!i915_pipe_enabled(dev, pipe)) {
 532                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 533                                 "pipe %c\n", pipe_name(pipe));
 534                 return 0;
 535         }
 536
 537         high_frame = PIPEFRAME(pipe);
 538         low_frame = PIPEFRAMEPIXEL(pipe);
 539
 540         /*
 541          * High & low register fields aren't synchronized, so make sure
 542          * we get a low value that's stable across two reads of the high
 543          * register.
 544          */
 545         do {
 546                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 547                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 548                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 549         } while (high1 != high2);
 550
 551         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 552         low >>= PIPE_FRAME_LOW_SHIFT;
 553         return (high1 << 8) | low;
 554 }
 555
 556 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 557 {
 558         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 559         int reg = PIPE_FRMCOUNT_GM45(pipe);
 560
 561         if (!i915_pipe_enabled(dev, pipe)) {
 562                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 563                                  "pipe %c\n", pipe_name(pipe));
 564                 return 0;
 565         }
 566
 567         return I915_READ(reg);
 568 }
 569
 570 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 571                              int *vpos, int *hpos)
 572 {
 573         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 574         u32 vbl = 0, position = 0;
 575         int vbl_start, vbl_end, htotal, vtotal;
 576         bool in_vbl = true;
 577         int ret = 0;
 578         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 579                                                                       pipe);
 580
 581         if (!i915_pipe_enabled(dev, pipe)) {
 582                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 583                                  "pipe %c\n", pipe_name(pipe));
 584                 return 0;
 585         }
 586
 587         /* Get vtotal. */
 588         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 589
 590         if (INTEL_INFO(dev)->gen >= 4) {
 591                 /* No obvious pixelcount register. Only query vertical
 592                  * scanout position from Display scan line register.
 593                  */
 594                 position = I915_READ(PIPEDSL(pipe));
 595
 596                 /* Decode into vertical scanout position. Don't have
 597                  * horizontal scanout position.
 598                  */
 599                 *vpos = position & 0x1fff;
 600                 *hpos = 0;
 601         } else {
 602                 /* Have access to pixelcount since start of frame.
 603                  * We can split this into vertical and horizontal
 604                  * scanout position.
 605                  */
 606                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 607
 608                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 609                 *vpos = position / htotal;
 610                 *hpos = position - (*vpos * htotal);
 611         }
 612
 613         /* Query vblank area. */
 614         vbl = I915_READ(VBLANK(cpu_transcoder));
 615
 616         /* Test position against vblank region. */
 617         vbl_start = vbl & 0x1fff;
 618         vbl_end = (vbl >> 16) & 0x1fff;
 619
 620         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 621                 in_vbl = false;
 622
 623         /* Inside "upper part" of vblank area? Apply corrective offset: */
 624         if (in_vbl && (*vpos >= vbl_start))
 625                 *vpos = *vpos - vtotal;
 626
 627         /* Readouts valid? */
 628         if (vbl > 0)
 629                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 630
 631         /* In vblank? */
 632         if (in_vbl)
 633                 ret |= DRM_SCANOUTPOS_INVBL;
 634
 635         return ret;
 636 }
 637
 638 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 639                               int *max_error,
 640                               struct timeval *vblank_time,
 641                               unsigned flags)
 642 {
 643         struct drm_crtc *crtc;
 644
 645         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 646                 DRM_ERROR("Invalid crtc %d\n", pipe);
 647                 return -EINVAL;
 648         }
 649
 650         /* Get drm_crtc to timestamp: */
 651         crtc = intel_get_crtc_for_pipe(dev, pipe);
 652         if (crtc == NULL) {
 653                 DRM_ERROR("Invalid crtc %d\n", pipe);
 654                 return -EINVAL;
 655         }
 656
 657         if (!crtc->enabled) {
 658                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 659                 return -EBUSY;
 660         }
 661
 662         /* Helper routine in DRM core does all the work: */
 663         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 664                                                      vblank_time, flags,
 665                                                      crtc);
 666 }
 667
 668 static bool intel_hpd_irq_event(struct drm_device *dev,
 669                                 struct drm_connector *connector)
 670 {
 671         enum drm_connector_status old_status;
 672
 673         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
 674         old_status = connector->status;
 675
 676         connector->status = connector->funcs->detect(connector, false);
 677         if (old_status == connector->status)
 678                 return false;
 679
 680         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
 681                       connector->base.id,
 682                       drm_get_connector_name(connector),
 683                       drm_get_connector_status_name(old_status),
 684                       drm_get_connector_status_name(connector->status));
 685
 686         return true;
 687 }
 688
 689 /*
 690  * Handle hotplug events outside the interrupt handler proper.
 691  */
 692 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 693
 694 static void i915_hotplug_work_func(struct work_struct *work)
 695 {
 696         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 697                                                     hotplug_work);
 698         struct drm_device *dev = dev_priv->dev;
 699         struct drm_mode_config *mode_config = &dev->mode_config;
 700         struct intel_connector *intel_connector;
 701         struct intel_encoder *intel_encoder;
 702         struct drm_connector *connector;
 703         unsigned long irqflags;
 704         bool hpd_disabled = false;
 705         bool changed = false;
 706         u32 hpd_event_bits;
 707
 708         /* HPD irq before everything is fully set up. */
 709         if (!dev_priv->enable_hotplug_processing)
 710                 return;
 711
 712         mutex_lock(&mode_config->mutex);
 713         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 714
 715         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 716
 717         hpd_event_bits = dev_priv->hpd_event_bits;
 718         dev_priv->hpd_event_bits = 0;
 719         list_for_each_entry(connector, &mode_config->connector_list, head) {
 720                 intel_connector = to_intel_connector(connector);
 721                 intel_encoder = intel_connector->encoder;
 722                 if (intel_encoder->hpd_pin > HPD_NONE &&
 723                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 724                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 725                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 726                                  "switching from hotplug detection to polling\n",
 727                                 drm_get_connector_name(connector));
 728                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 729                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 730                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 731                         hpd_disabled = true;
 732                 }
 733                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 734                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
 735                                       drm_get_connector_name(connector), intel_encoder->hpd_pin);
 736                 }
 737         }
 738          /* if there were no outputs to poll, poll was disabled,
 739           * therefore make sure it's enabled when disabling HPD on
 740           * some connectors */
 741         if (hpd_disabled) {
 742                 drm_kms_helper_poll_enable(dev);
 743                 mod_timer(&dev_priv->hotplug_reenable_timer,
 744                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 745         }
 746
 747         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 748
 749         list_for_each_entry(connector, &mode_config->connector_list, head) {
 750                 intel_connector = to_intel_connector(connector);
 751                 intel_encoder = intel_connector->encoder;
 752                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
 753                         if (intel_encoder->hot_plug)
 754                                 intel_encoder->hot_plug(intel_encoder);
 755                         if (intel_hpd_irq_event(dev, connector))
 756                                 changed = true;
 757                 }
 758         }
 759         mutex_unlock(&mode_config->mutex);
 760
 761         if (changed)
 762                 drm_kms_helper_hotplug_event(dev);
 763 }
 764
 765 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
 766 {
 767         drm_i915_private_t *dev_priv = dev->dev_private;
 768         u32 busy_up, busy_down, max_avg, min_avg;
 769         u8 new_delay;
 770
 771         spin_lock(&mchdev_lock);
 772
 773         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 774
 775         new_delay = dev_priv->ips.cur_delay;
 776
 777         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 778         busy_up = I915_READ(RCPREVBSYTUPAVG);
 779         busy_down = I915_READ(RCPREVBSYTDNAVG);
 780         max_avg = I915_READ(RCBMAXAVG);
 781         min_avg = I915_READ(RCBMINAVG);
 782
 783         /* Handle RCS change request from hw */
 784         if (busy_up > max_avg) {
 785                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 786                         new_delay = dev_priv->ips.cur_delay - 1;
 787                 if (new_delay < dev_priv->ips.max_delay)
 788                         new_delay = dev_priv->ips.max_delay;
 789         } else if (busy_down < min_avg) {
 790                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 791                         new_delay = dev_priv->ips.cur_delay + 1;
 792                 if (new_delay > dev_priv->ips.min_delay)
 793                         new_delay = dev_priv->ips.min_delay;
 794         }
 795
 796         if (ironlake_set_drps(dev, new_delay))
 797                 dev_priv->ips.cur_delay = new_delay;
 798
 799         spin_unlock(&mchdev_lock);
 800
 801         return;
 802 }
 803
 804 static void notify_ring(struct drm_device *dev,
 805                         struct intel_ring_buffer *ring)
 806 {
 807         if (ring->obj == NULL)
 808                 return;
 809
 810         trace_i915_gem_request_complete(ring);
 811
 812         wake_up_all(&ring->irq_queue);
 813         i915_queue_hangcheck(dev);
 814 }
 815
 816 static void gen6_pm_rps_work(struct work_struct *work)
 817 {
 818         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 819                                                     rps.work);
 820         u32 pm_iir;
 821         u8 new_delay;
 822
 823         spin_lock_irq(&dev_priv->irq_lock);
 824         pm_iir = dev_priv->rps.pm_iir;
 825         dev_priv->rps.pm_iir = 0;
 826         /* Make sure not to corrupt PMIMR state used by ringbuffer code */
 827         snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
 828         spin_unlock_irq(&dev_priv->irq_lock);
 829
 830         /* Make sure we didn't queue anything we're not going to process. */
 831         WARN_ON(pm_iir & ~GEN6_PM_RPS_EVENTS);
 832
 833         if ((pm_iir & GEN6_PM_RPS_EVENTS) == 0)
 834                 return;
 835
 836         mutex_lock(&dev_priv->rps.hw_lock);
 837
 838         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
 839                 new_delay = dev_priv->rps.cur_delay + 1;
 840
 841                 /*
 842                  * For better performance, jump directly
 843                  * to RPe if we're below it.
 844                  */
 845                 if (IS_VALLEYVIEW(dev_priv->dev) &&
 846                     dev_priv->rps.cur_delay < dev_priv->rps.rpe_delay)
 847                         new_delay = dev_priv->rps.rpe_delay;
 848         } else
 849                 new_delay = dev_priv->rps.cur_delay - 1;
 850
 851         /* sysfs frequency interfaces may have snuck in while servicing the
 852          * interrupt
 853          */
 854         if (new_delay >= dev_priv->rps.min_delay &&
 855             new_delay <= dev_priv->rps.max_delay) {
 856                 if (IS_VALLEYVIEW(dev_priv->dev))
 857                         valleyview_set_rps(dev_priv->dev, new_delay);
 858                 else
 859                         gen6_set_rps(dev_priv->dev, new_delay);
 860         }
 861
 862         mutex_unlock(&dev_priv->rps.hw_lock);
 863 }
 864
 865
 866 /**
 867  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 868  * occurred.
 869  * @work: workqueue struct
 870  *
 871  * Doesn't actually do anything except notify userspace. As a consequence of
 872  * this event, userspace should try to remap the bad rows since statistically
 873  * it is likely the same row is more likely to go bad again.
 874  */
 875 static void ivybridge_parity_work(struct work_struct *work)
 876 {
 877         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 878                                                     l3_parity.error_work);
 879         u32 error_status, row, bank, subbank;
 880         char *parity_event[6];
 881         uint32_t misccpctl;
 882         unsigned long flags;
 883         uint8_t slice = 0;
 884
 885         /* We must turn off DOP level clock gating to access the L3 registers.
 886          * In order to prevent a get/put style interface, acquire struct mutex
 887          * any time we access those registers.
 888          */
 889         mutex_lock(&dev_priv->dev->struct_mutex);
 890
 891         /* If we've screwed up tracking, just let the interrupt fire again */
 892         if (WARN_ON(!dev_priv->l3_parity.which_slice))
 893                 goto out;
 894
 895         misccpctl = I915_READ(GEN7_MISCCPCTL);
 896         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 897         POSTING_READ(GEN7_MISCCPCTL);
 898
 899         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
 900                 u32 reg;
 901
 902                 slice--;
 903                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
 904                         break;
 905
 906                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
 907
 908                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
 909
 910                 error_status = I915_READ(reg);
 911                 row = GEN7_PARITY_ERROR_ROW(error_status);
 912                 bank = GEN7_PARITY_ERROR_BANK(error_status);
 913                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 914
 915                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
 916                 POSTING_READ(reg);
 917
 918                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
 919                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 920                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 921                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 922                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
 923                 parity_event[5] = NULL;
 924
 925                 kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 926                                    KOBJ_CHANGE, parity_event);
 927
 928                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
 929                           slice, row, bank, subbank);
 930
 931                 kfree(parity_event[4]);
 932                 kfree(parity_event[3]);
 933                 kfree(parity_event[2]);
 934                 kfree(parity_event[1]);
 935         }
 936
 937         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 938
 939 out:
 940         WARN_ON(dev_priv->l3_parity.which_slice);
 941         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 942         ilk_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
 943         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 944
 945         mutex_unlock(&dev_priv->dev->struct_mutex);
 946 }
 947
 948 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
 949 {
 950         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 951
 952         if (!HAS_L3_DPF(dev))
 953                 return;
 954
 955         spin_lock(&dev_priv->irq_lock);
 956         ilk_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
 957         spin_unlock(&dev_priv->irq_lock);
 958
 959         iir &= GT_PARITY_ERROR(dev);
 960         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
 961                 dev_priv->l3_parity.which_slice |= 1 << 1;
 962
 963         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
 964                 dev_priv->l3_parity.which_slice |= 1 << 0;
 965
 966         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 967 }
 968
 969 static void ilk_gt_irq_handler(struct drm_device *dev,
 970                                struct drm_i915_private *dev_priv,
 971                                u32 gt_iir)
 972 {
 973         if (gt_iir &
 974             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 975                 notify_ring(dev, &dev_priv->ring[RCS]);
 976         if (gt_iir & ILK_BSD_USER_INTERRUPT)
 977                 notify_ring(dev, &dev_priv->ring[VCS]);
 978 }
 979
 980 static void snb_gt_irq_handler(struct drm_device *dev,
 981                                struct drm_i915_private *dev_priv,
 982                                u32 gt_iir)
 983 {
 984
 985         if (gt_iir &
 986             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
 987                 notify_ring(dev, &dev_priv->ring[RCS]);
 988         if (gt_iir & GT_BSD_USER_INTERRUPT)
 989                 notify_ring(dev, &dev_priv->ring[VCS]);
 990         if (gt_iir & GT_BLT_USER_INTERRUPT)
 991                 notify_ring(dev, &dev_priv->ring[BCS]);
 992
 993         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
 994                       GT_BSD_CS_ERROR_INTERRUPT |
 995                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
 996                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 997                 i915_handle_error(dev, false);
 998         }
 999
1000         if (gt_iir & GT_PARITY_ERROR(dev))
1001                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1002 }
1003
1004 #define HPD_STORM_DETECT_PERIOD 1000
1005 #define HPD_STORM_THRESHOLD 5
1006
1007 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1008                                          u32 hotplug_trigger,
1009                                          const u32 *hpd)
1010 {
1011         drm_i915_private_t *dev_priv = dev->dev_private;
1012         int i;
1013         bool storm_detected = false;
1014
1015         if (!hotplug_trigger)
1016                 return;
1017
1018         spin_lock(&dev_priv->irq_lock);
1019         for (i = 1; i < HPD_NUM_PINS; i++) {
1020
1021                 WARN(((hpd[i] & hotplug_trigger) &&
1022                       dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED),
1023                      "Received HPD interrupt although disabled\n");
1024
1025                 if (!(hpd[i] & hotplug_trigger) ||
1026                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1027                         continue;
1028
1029                 dev_priv->hpd_event_bits |= (1 << i);
1030                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1031                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1032                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1033                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1034                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1035                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1036                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1037                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1038                         dev_priv->hpd_event_bits &= ~(1 << i);
1039                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1040                         storm_detected = true;
1041                 } else {
1042                         dev_priv->hpd_stats[i].hpd_cnt++;
1043                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1044                                       dev_priv->hpd_stats[i].hpd_cnt);
1045                 }
1046         }
1047
1048         if (storm_detected)
1049                 dev_priv->display.hpd_irq_setup(dev);
1050         spin_unlock(&dev_priv->irq_lock);
1051
1052         /*
1053          * Our hotplug handler can grab modeset locks (by calling down into the
1054          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1055          * queue for otherwise the flush_work in the pageflip code will
1056          * deadlock.
1057          */
1058         schedule_work(&dev_priv->hotplug_work);
1059 }
1060
1061 static void gmbus_irq_handler(struct drm_device *dev)
1062 {
1063         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1064
1065         wake_up_all(&dev_priv->gmbus_wait_queue);
1066 }
1067
1068 static void dp_aux_irq_handler(struct drm_device *dev)
1069 {
1070         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
1071
1072         wake_up_all(&dev_priv->gmbus_wait_queue);
1073 }
1074
1075 /* The RPS events need forcewake, so we add them to a work queue and mask their
1076  * IMR bits until the work is done. Other interrupts can be processed without
1077  * the work queue. */
1078 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1079 {
1080         if (pm_iir & GEN6_PM_RPS_EVENTS) {
1081                 spin_lock(&dev_priv->irq_lock);
1082                 dev_priv->rps.pm_iir |= pm_iir & GEN6_PM_RPS_EVENTS;
1083                 snb_disable_pm_irq(dev_priv, pm_iir & GEN6_PM_RPS_EVENTS);
1084                 spin_unlock(&dev_priv->irq_lock);
1085
1086                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1087         }
1088
1089         if (HAS_VEBOX(dev_priv->dev)) {
1090                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1091                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1092
1093                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
1094                         DRM_ERROR("VEBOX CS error interrupt 0x%08x\n", pm_iir);
1095                         i915_handle_error(dev_priv->dev, false);
1096                 }
1097         }
1098 }
1099
1100 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1101 {
1102         struct drm_device *dev = (struct drm_device *) arg;
1103         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1104         u32 iir, gt_iir, pm_iir;
1105         irqreturn_t ret = IRQ_NONE;
1106         unsigned long irqflags;
1107         int pipe;
1108         u32 pipe_stats[I915_MAX_PIPES];
1109
1110         atomic_inc(&dev_priv->irq_received);
1111
1112         while (true) {
1113                 iir = I915_READ(VLV_IIR);
1114                 gt_iir = I915_READ(GTIIR);
1115                 pm_iir = I915_READ(GEN6_PMIIR);
1116
1117                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1118                         goto out;
1119
1120                 ret = IRQ_HANDLED;
1121
1122                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
1123
1124                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1125                 for_each_pipe(pipe) {
1126                         int reg = PIPESTAT(pipe);
1127                         pipe_stats[pipe] = I915_READ(reg);
1128
1129                         /*
1130                          * Clear the PIPE*STAT regs before the IIR
1131                          */
1132                         if (pipe_stats[pipe] & 0x8000ffff) {
1133                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1134                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
1135                                                          pipe_name(pipe));
1136                                 I915_WRITE(reg, pipe_stats[pipe]);
1137                         }
1138                 }
1139                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1140
1141                 for_each_pipe(pipe) {
1142                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1143                                 drm_handle_vblank(dev, pipe);
1144
1145                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
1146                                 intel_prepare_page_flip(dev, pipe);
1147                                 intel_finish_page_flip(dev, pipe);
1148                         }
1149                 }
1150
1151                 /* Consume port.  Then clear IIR or we'll miss events */
1152                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
1153                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1154                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1155
1156                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
1157                                          hotplug_status);
1158
1159                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1160
1161                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1162                         I915_READ(PORT_HOTPLUG_STAT);
1163                 }
1164
1165                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1166                         gmbus_irq_handler(dev);
1167
1168                 if (pm_iir)
1169                         gen6_rps_irq_handler(dev_priv, pm_iir);
1170
1171                 I915_WRITE(GTIIR, gt_iir);
1172                 I915_WRITE(GEN6_PMIIR, pm_iir);
1173                 I915_WRITE(VLV_IIR, iir);
1174         }
1175
1176 out:
1177         return ret;
1178 }
1179
1180 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
1181 {
1182         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1183         int pipe;
1184         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1185
1186         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_ibx);
1187
1188         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1189                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1190                                SDE_AUDIO_POWER_SHIFT);
1191                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1192                                  port_name(port));
1193         }
1194
1195         if (pch_iir & SDE_AUX_MASK)
1196                 dp_aux_irq_handler(dev);
1197
1198         if (pch_iir & SDE_GMBUS)
1199                 gmbus_irq_handler(dev);
1200
1201         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1202                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1203
1204         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1205                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1206
1207         if (pch_iir & SDE_POISON)
1208                 DRM_ERROR("PCH poison interrupt\n");
1209
1210         if (pch_iir & SDE_FDI_MASK)
1211                 for_each_pipe(pipe)
1212                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1213                                          pipe_name(pipe),
1214                                          I915_READ(FDI_RX_IIR(pipe)));
1215
1216         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1217                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1218
1219         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1220                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1221
1222         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1223                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1224                                                           false))
1225                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1226
1227         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1228                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1229                                                           false))
1230                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1231 }
1232
1233 static void ivb_err_int_handler(struct drm_device *dev)
1234 {
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236         u32 err_int = I915_READ(GEN7_ERR_INT);
1237
1238         if (err_int & ERR_INT_POISON)
1239                 DRM_ERROR("Poison interrupt\n");
1240
1241         if (err_int & ERR_INT_FIFO_UNDERRUN_A)
1242                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1243                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1244
1245         if (err_int & ERR_INT_FIFO_UNDERRUN_B)
1246                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1247                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1248
1249         if (err_int & ERR_INT_FIFO_UNDERRUN_C)
1250                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_C, false))
1251                         DRM_DEBUG_DRIVER("Pipe C FIFO underrun\n");
1252
1253         I915_WRITE(GEN7_ERR_INT, err_int);
1254 }
1255
1256 static void cpt_serr_int_handler(struct drm_device *dev)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         u32 serr_int = I915_READ(SERR_INT);
1260
1261         if (serr_int & SERR_INT_POISON)
1262                 DRM_ERROR("PCH poison interrupt\n");
1263
1264         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
1265                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
1266                                                           false))
1267                         DRM_DEBUG_DRIVER("PCH transcoder A FIFO underrun\n");
1268
1269         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
1270                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
1271                                                           false))
1272                         DRM_DEBUG_DRIVER("PCH transcoder B FIFO underrun\n");
1273
1274         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
1275                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
1276                                                           false))
1277                         DRM_DEBUG_DRIVER("PCH transcoder C FIFO underrun\n");
1278
1279         I915_WRITE(SERR_INT, serr_int);
1280 }
1281
1282 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1283 {
1284         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1285         int pipe;
1286         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1287
1288         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_cpt);
1289
1290         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1291                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1292                                SDE_AUDIO_POWER_SHIFT_CPT);
1293                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1294                                  port_name(port));
1295         }
1296
1297         if (pch_iir & SDE_AUX_MASK_CPT)
1298                 dp_aux_irq_handler(dev);
1299
1300         if (pch_iir & SDE_GMBUS_CPT)
1301                 gmbus_irq_handler(dev);
1302
1303         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1304                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1305
1306         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1307                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
1308
1309         if (pch_iir & SDE_FDI_MASK_CPT)
1310                 for_each_pipe(pipe)
1311                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1312                                          pipe_name(pipe),
1313                                          I915_READ(FDI_RX_IIR(pipe)));
1314
1315         if (pch_iir & SDE_ERROR_CPT)
1316                 cpt_serr_int_handler(dev);
1317 }
1318
1319 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
1320 {
1321         struct drm_i915_private *dev_priv = dev->dev_private;
1322
1323         if (de_iir & DE_AUX_CHANNEL_A)
1324                 dp_aux_irq_handler(dev);
1325
1326         if (de_iir & DE_GSE)
1327                 intel_opregion_asle_intr(dev);
1328
1329         if (de_iir & DE_PIPEA_VBLANK)
1330                 drm_handle_vblank(dev, 0);
1331
1332         if (de_iir & DE_PIPEB_VBLANK)
1333                 drm_handle_vblank(dev, 1);
1334
1335         if (de_iir & DE_POISON)
1336                 DRM_ERROR("Poison interrupt\n");
1337
1338         if (de_iir & DE_PIPEA_FIFO_UNDERRUN)
1339                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_A, false))
1340                         DRM_DEBUG_DRIVER("Pipe A FIFO underrun\n");
1341
1342         if (de_iir & DE_PIPEB_FIFO_UNDERRUN)
1343                 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false))
1344                         DRM_DEBUG_DRIVER("Pipe B FIFO underrun\n");
1345
1346         if (de_iir & DE_PLANEA_FLIP_DONE) {
1347                 intel_prepare_page_flip(dev, 0);
1348                 intel_finish_page_flip_plane(dev, 0);
1349         }
1350
1351         if (de_iir & DE_PLANEB_FLIP_DONE) {
1352                 intel_prepare_page_flip(dev, 1);
1353                 intel_finish_page_flip_plane(dev, 1);
1354         }
1355
1356         /* check event from PCH */
1357         if (de_iir & DE_PCH_EVENT) {
1358                 u32 pch_iir = I915_READ(SDEIIR);
1359
1360                 if (HAS_PCH_CPT(dev))
1361                         cpt_irq_handler(dev, pch_iir);
1362                 else
1363                         ibx_irq_handler(dev, pch_iir);
1364
1365                 /* should clear PCH hotplug event before clear CPU irq */
1366                 I915_WRITE(SDEIIR, pch_iir);
1367         }
1368
1369         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
1370                 ironlake_rps_change_irq_handler(dev);
1371 }
1372
1373 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
1374 {
1375         struct drm_i915_private *dev_priv = dev->dev_private;
1376         int i;
1377
1378         if (de_iir & DE_ERR_INT_IVB)
1379                 ivb_err_int_handler(dev);
1380
1381         if (de_iir & DE_AUX_CHANNEL_A_IVB)
1382                 dp_aux_irq_handler(dev);
1383
1384         if (de_iir & DE_GSE_IVB)
1385                 intel_opregion_asle_intr(dev);
1386
1387         for (i = 0; i < 3; i++) {
1388                 if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
1389                         drm_handle_vblank(dev, i);
1390                 if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
1391                         intel_prepare_page_flip(dev, i);
1392                         intel_finish_page_flip_plane(dev, i);
1393                 }
1394         }
1395
1396         /* check event from PCH */
1397         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
1398                 u32 pch_iir = I915_READ(SDEIIR);
1399
1400                 cpt_irq_handler(dev, pch_iir);
1401
1402                 /* clear PCH hotplug event before clear CPU irq */
1403                 I915_WRITE(SDEIIR, pch_iir);
1404         }
1405 }
1406
1407 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
1408 {
1409         struct drm_device *dev = (struct drm_device *) arg;
1410         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1411         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
1412         irqreturn_t ret = IRQ_NONE;
1413
1414         atomic_inc(&dev_priv->irq_received);
1415
1416         /* We get interrupts on unclaimed registers, so check for this before we
1417          * do any I915_{READ,WRITE}. */
1418         intel_uncore_check_errors(dev);
1419
1420         /* disable master interrupt before clearing iir  */
1421         de_ier = I915_READ(DEIER);
1422         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
1423         POSTING_READ(DEIER);
1424
1425         /* Disable south interrupts. We'll only write to SDEIIR once, so further
1426          * interrupts will will be stored on its back queue, and then we'll be
1427          * able to process them after we restore SDEIER (as soon as we restore
1428          * it, we'll get an interrupt if SDEIIR still has something to process
1429          * due to its back queue). */
1430         if (!HAS_PCH_NOP(dev)) {
1431                 sde_ier = I915_READ(SDEIER);
1432                 I915_WRITE(SDEIER, 0);
1433                 POSTING_READ(SDEIER);
1434         }
1435
1436         gt_iir = I915_READ(GTIIR);
1437         if (gt_iir) {
1438                 if (INTEL_INFO(dev)->gen >= 6)
1439                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
1440                 else
1441                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
1442                 I915_WRITE(GTIIR, gt_iir);
1443                 ret = IRQ_HANDLED;
1444         }
1445
1446         de_iir = I915_READ(DEIIR);
1447         if (de_iir) {
1448                 if (INTEL_INFO(dev)->gen >= 7)
1449                         ivb_display_irq_handler(dev, de_iir);
1450                 else
1451                         ilk_display_irq_handler(dev, de_iir);
1452                 I915_WRITE(DEIIR, de_iir);
1453                 ret = IRQ_HANDLED;
1454         }
1455
1456         if (INTEL_INFO(dev)->gen >= 6) {
1457                 u32 pm_iir = I915_READ(GEN6_PMIIR);
1458                 if (pm_iir) {
1459                         gen6_rps_irq_handler(dev_priv, pm_iir);
1460                         I915_WRITE(GEN6_PMIIR, pm_iir);
1461                         ret = IRQ_HANDLED;
1462                 }
1463         }
1464
1465         I915_WRITE(DEIER, de_ier);
1466         POSTING_READ(DEIER);
1467         if (!HAS_PCH_NOP(dev)) {
1468                 I915_WRITE(SDEIER, sde_ier);
1469                 POSTING_READ(SDEIER);
1470         }
1471
1472         return ret;
1473 }
1474
1475 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
1476                                bool reset_completed)
1477 {
1478         struct intel_ring_buffer *ring;
1479         int i;
1480
1481         /*
1482          * Notify all waiters for GPU completion events that reset state has
1483          * been changed, and that they need to restart their wait after
1484          * checking for potential errors (and bail out to drop locks if there is
1485          * a gpu reset pending so that i915_error_work_func can acquire them).
1486          */
1487
1488         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
1489         for_each_ring(ring, dev_priv, i)
1490                 wake_up_all(&ring->irq_queue);
1491
1492         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
1493         wake_up_all(&dev_priv->pending_flip_queue);
1494
1495         /*
1496          * Signal tasks blocked in i915_gem_wait_for_error that the pending
1497          * reset state is cleared.
1498          */
1499         if (reset_completed)
1500                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1501 }
1502
1503 /**
1504  * i915_error_work_func - do process context error handling work
1505  * @work: work struct
1506  *
1507  * Fire an error uevent so userspace can see that a hang or error
1508  * was detected.
1509  */
1510 static void i915_error_work_func(struct work_struct *work)
1511 {
1512         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1513                                                     work);
1514         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1515                                                     gpu_error);
1516         struct drm_device *dev = dev_priv->dev;
1517         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1518         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1519         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1520         int ret;
1521
1522         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1523
1524         /*
1525          * Note that there's only one work item which does gpu resets, so we
1526          * need not worry about concurrent gpu resets potentially incrementing
1527          * error->reset_counter twice. We only need to take care of another
1528          * racing irq/hangcheck declaring the gpu dead for a second time. A
1529          * quick check for that is good enough: schedule_work ensures the
1530          * correct ordering between hang detection and this work item, and since
1531          * the reset in-progress bit is only ever set by code outside of this
1532          * work we don't need to worry about any other races.
1533          */
1534         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1535                 DRM_DEBUG_DRIVER("resetting chip\n");
1536                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1537                                    reset_event);
1538
1539                 /*
1540                  * All state reset _must_ be completed before we update the
1541                  * reset counter, for otherwise waiters might miss the reset
1542                  * pending state and not properly drop locks, resulting in
1543                  * deadlocks with the reset work.
1544                  */
1545                 ret = i915_reset(dev);
1546
1547                 intel_display_handle_reset(dev);
1548
1549                 if (ret == 0) {
1550                         /*
1551                          * After all the gem state is reset, increment the reset
1552                          * counter and wake up everyone waiting for the reset to
1553                          * complete.
1554                          *
1555                          * Since unlock operations are a one-sided barrier only,
1556                          * we need to insert a barrier here to order any seqno
1557                          * updates before
1558                          * the counter increment.
1559                          */
1560                         smp_mb__before_atomic_inc();
1561                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1562
1563                         kobject_uevent_env(&dev->primary->kdev.kobj,
1564                                            KOBJ_CHANGE, reset_done_event);
1565                 } else {
1566                         atomic_set(&error->reset_counter, I915_WEDGED);
1567                 }
1568
1569                 /*
1570                  * Note: The wake_up also serves as a memory barrier so that
1571                  * waiters see the update value of the reset counter atomic_t.
1572                  */
1573                 i915_error_wake_up(dev_priv, true);
1574         }
1575 }
1576
1577 static void i915_report_and_clear_eir(struct drm_device *dev)
1578 {
1579         struct drm_i915_private *dev_priv = dev->dev_private;
1580         uint32_t instdone[I915_NUM_INSTDONE_REG];
1581         u32 eir = I915_READ(EIR);
1582         int pipe, i;
1583
1584         if (!eir)
1585                 return;
1586
1587         pr_err("render error detected, EIR: 0x%08x\n", eir);
1588
1589         i915_get_extra_instdone(dev, instdone);
1590
1591         if (IS_G4X(dev)) {
1592                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1593                         u32 ipeir = I915_READ(IPEIR_I965);
1594
1595                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1596                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1597                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1598                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1599                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1600                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1601                         I915_WRITE(IPEIR_I965, ipeir);
1602                         POSTING_READ(IPEIR_I965);
1603                 }
1604                 if (eir & GM45_ERROR_PAGE_TABLE) {
1605                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1606                         pr_err("page table error\n");
1607                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1608                         I915_WRITE(PGTBL_ER, pgtbl_err);
1609                         POSTING_READ(PGTBL_ER);
1610                 }
1611         }
1612
1613         if (!IS_GEN2(dev)) {
1614                 if (eir & I915_ERROR_PAGE_TABLE) {
1615                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1616                         pr_err("page table error\n");
1617                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1618                         I915_WRITE(PGTBL_ER, pgtbl_err);
1619                         POSTING_READ(PGTBL_ER);
1620                 }
1621         }
1622
1623         if (eir & I915_ERROR_MEMORY_REFRESH) {
1624                 pr_err("memory refresh error:\n");
1625                 for_each_pipe(pipe)
1626                         pr_err("pipe %c stat: 0x%08x\n",
1627                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1628                 /* pipestat has already been acked */
1629         }
1630         if (eir & I915_ERROR_INSTRUCTION) {
1631                 pr_err("instruction error\n");
1632                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1633                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1634                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1635                 if (INTEL_INFO(dev)->gen < 4) {
1636                         u32 ipeir = I915_READ(IPEIR);
1637
1638                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1639                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1640                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1641                         I915_WRITE(IPEIR, ipeir);
1642                         POSTING_READ(IPEIR);
1643                 } else {
1644                         u32 ipeir = I915_READ(IPEIR_I965);
1645
1646                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1647                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1648                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1649                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1650                         I915_WRITE(IPEIR_I965, ipeir);
1651                         POSTING_READ(IPEIR_I965);
1652                 }
1653         }
1654
1655         I915_WRITE(EIR, eir);
1656         POSTING_READ(EIR);
1657         eir = I915_READ(EIR);
1658         if (eir) {
1659                 /*
1660                  * some errors might have become stuck,
1661                  * mask them.
1662                  */
1663                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1664                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1665                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1666         }
1667 }
1668
1669 /**
1670  * i915_handle_error - handle an error interrupt
1671  * @dev: drm device
1672  *
1673  * Do some basic checking of regsiter state at error interrupt time and
1674  * dump it to the syslog.  Also call i915_capture_error_state() to make
1675  * sure we get a record and make it available in debugfs.  Fire a uevent
1676  * so userspace knows something bad happened (should trigger collection
1677  * of a ring dump etc.).
1678  */
1679 void i915_handle_error(struct drm_device *dev, bool wedged)
1680 {
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683         i915_capture_error_state(dev);
1684         i915_report_and_clear_eir(dev);
1685
1686         if (wedged) {
1687                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1688                                 &dev_priv->gpu_error.reset_counter);
1689
1690                 /*
1691                  * Wakeup waiting processes so that the reset work function
1692                  * i915_error_work_func doesn't deadlock trying to grab various
1693                  * locks. By bumping the reset counter first, the woken
1694                  * processes will see a reset in progress and back off,
1695                  * releasing their locks and then wait for the reset completion.
1696                  * We must do this for _all_ gpu waiters that might hold locks
1697                  * that the reset work needs to acquire.
1698                  *
1699                  * Note: The wake_up serves as the required memory barrier to
1700                  * ensure that the waiters see the updated value of the reset
1701                  * counter atomic_t.
1702                  */
1703                 i915_error_wake_up(dev_priv, false);
1704         }
1705
1706         /*
1707          * Our reset work can grab modeset locks (since it needs to reset the
1708          * state of outstanding pagelips). Hence it must not be run on our own
1709          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
1710          * code will deadlock.
1711          */
1712         schedule_work(&dev_priv->gpu_error.work);
1713 }
1714
1715 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1716 {
1717         drm_i915_private_t *dev_priv = dev->dev_private;
1718         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1719         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1720         struct drm_i915_gem_object *obj;
1721         struct intel_unpin_work *work;
1722         unsigned long flags;
1723         bool stall_detected;
1724
1725         /* Ignore early vblank irqs */
1726         if (intel_crtc == NULL)
1727                 return;
1728
1729         spin_lock_irqsave(&dev->event_lock, flags);
1730         work = intel_crtc->unpin_work;
1731
1732         if (work == NULL ||
1733             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1734             !work->enable_stall_check) {
1735                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1736                 spin_unlock_irqrestore(&dev->event_lock, flags);
1737                 return;
1738         }
1739
1740         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1741         obj = work->pending_flip_obj;
1742         if (INTEL_INFO(dev)->gen >= 4) {
1743                 int dspsurf = DSPSURF(intel_crtc->plane);
1744                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1745                                         i915_gem_obj_ggtt_offset(obj);
1746         } else {
1747                 int dspaddr = DSPADDR(intel_crtc->plane);
1748                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
1749                                                         crtc->y * crtc->fb->pitches[0] +
1750                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1751         }
1752
1753         spin_unlock_irqrestore(&dev->event_lock, flags);
1754
1755         if (stall_detected) {
1756                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1757                 intel_prepare_page_flip(dev, intel_crtc->plane);
1758         }
1759 }
1760
1761 /* Called from drm generic code, passed 'crtc' which
1762  * we use as a pipe index
1763  */
1764 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1765 {
1766         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1767         unsigned long irqflags;
1768
1769         if (!i915_pipe_enabled(dev, pipe))
1770                 return -EINVAL;
1771
1772         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1773         if (INTEL_INFO(dev)->gen >= 4)
1774                 i915_enable_pipestat(dev_priv, pipe,
1775                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1776         else
1777                 i915_enable_pipestat(dev_priv, pipe,
1778                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1779
1780         /* maintain vblank delivery even in deep C-states */
1781         if (dev_priv->info->gen == 3)
1782                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1783         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1784
1785         return 0;
1786 }
1787
1788 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1789 {
1790         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1791         unsigned long irqflags;
1792         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1793                                                      DE_PIPE_VBLANK_ILK(pipe);
1794
1795         if (!i915_pipe_enabled(dev, pipe))
1796                 return -EINVAL;
1797
1798         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1799         ironlake_enable_display_irq(dev_priv, bit);
1800         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1801
1802         return 0;
1803 }
1804
1805 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1806 {
1807         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1808         unsigned long irqflags;
1809         u32 imr;
1810
1811         if (!i915_pipe_enabled(dev, pipe))
1812                 return -EINVAL;
1813
1814         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1815         imr = I915_READ(VLV_IMR);
1816         if (pipe == 0)
1817                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1818         else
1819                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1820         I915_WRITE(VLV_IMR, imr);
1821         i915_enable_pipestat(dev_priv, pipe,
1822                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1823         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1824
1825         return 0;
1826 }
1827
1828 /* Called from drm generic code, passed 'crtc' which
1829  * we use as a pipe index
1830  */
1831 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1832 {
1833         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1834         unsigned long irqflags;
1835
1836         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1837         if (dev_priv->info->gen == 3)
1838                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1839
1840         i915_disable_pipestat(dev_priv, pipe,
1841                               PIPE_VBLANK_INTERRUPT_ENABLE |
1842                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1843         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1844 }
1845
1846 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1847 {
1848         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1849         unsigned long irqflags;
1850         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
1851                                                      DE_PIPE_VBLANK_ILK(pipe);
1852
1853         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1854         ironlake_disable_display_irq(dev_priv, bit);
1855         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1856 }
1857
1858 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1859 {
1860         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1861         unsigned long irqflags;
1862         u32 imr;
1863
1864         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1865         i915_disable_pipestat(dev_priv, pipe,
1866                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1867         imr = I915_READ(VLV_IMR);
1868         if (pipe == 0)
1869                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1870         else
1871                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1872         I915_WRITE(VLV_IMR, imr);
1873         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1874 }
1875
1876 static u32
1877 ring_last_seqno(struct intel_ring_buffer *ring)
1878 {
1879         return list_entry(ring->request_list.prev,
1880                           struct drm_i915_gem_request, list)->seqno;
1881 }
1882
1883 static bool
1884 ring_idle(struct intel_ring_buffer *ring, u32 seqno)
1885 {
1886         return (list_empty(&ring->request_list) ||
1887                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
1888 }
1889
1890 static struct intel_ring_buffer *
1891 semaphore_waits_for(struct intel_ring_buffer *ring, u32 *seqno)
1892 {
1893         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1894         u32 cmd, ipehr, acthd, acthd_min;
1895
1896         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1897         if ((ipehr & ~(0x3 << 16)) !=
1898             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1899                 return NULL;
1900
1901         /* ACTHD is likely pointing to the dword after the actual command,
1902          * so scan backwards until we find the MBOX.
1903          */
1904         acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1905         acthd_min = max((int)acthd - 3 * 4, 0);
1906         do {
1907                 cmd = ioread32(ring->virtual_start + acthd);
1908                 if (cmd == ipehr)
1909                         break;
1910
1911                 acthd -= 4;
1912                 if (acthd < acthd_min)
1913                         return NULL;
1914         } while (1);
1915
1916         *seqno = ioread32(ring->virtual_start+acthd+4)+1;
1917         return &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1918 }
1919
1920 static int semaphore_passed(struct intel_ring_buffer *ring)
1921 {
1922         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1923         struct intel_ring_buffer *signaller;
1924         u32 seqno, ctl;
1925
1926         ring->hangcheck.deadlock = true;
1927
1928         signaller = semaphore_waits_for(ring, &seqno);
1929         if (signaller == NULL || signaller->hangcheck.deadlock)
1930                 return -1;
1931
1932         /* cursory check for an unkickable deadlock */
1933         ctl = I915_READ_CTL(signaller);
1934         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
1935                 return -1;
1936
1937         return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
1938 }
1939
1940 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
1941 {
1942         struct intel_ring_buffer *ring;
1943         int i;
1944
1945         for_each_ring(ring, dev_priv, i)
1946                 ring->hangcheck.deadlock = false;
1947 }
1948
1949 static enum intel_ring_hangcheck_action
1950 ring_stuck(struct intel_ring_buffer *ring, u32 acthd)
1951 {
1952         struct drm_device *dev = ring->dev;
1953         struct drm_i915_private *dev_priv = dev->dev_private;
1954         u32 tmp;
1955
1956         if (ring->hangcheck.acthd != acthd)
1957                 return HANGCHECK_ACTIVE;
1958
1959         if (IS_GEN2(dev))
1960                 return HANGCHECK_HUNG;
1961
1962         /* Is the chip hanging on a WAIT_FOR_EVENT?
1963          * If so we can simply poke the RB_WAIT bit
1964          * and break the hang. This should work on
1965          * all but the second generation chipsets.
1966          */
1967         tmp = I915_READ_CTL(ring);
1968         if (tmp & RING_WAIT) {
1969                 DRM_ERROR("Kicking stuck wait on %s\n",
1970                           ring->name);
1971                 I915_WRITE_CTL(ring, tmp);
1972                 return HANGCHECK_KICK;
1973         }
1974
1975         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
1976                 switch (semaphore_passed(ring)) {
1977                 default:
1978                         return HANGCHECK_HUNG;
1979                 case 1:
1980                         DRM_ERROR("Kicking stuck semaphore on %s\n",
1981                                   ring->name);
1982                         I915_WRITE_CTL(ring, tmp);
1983                         return HANGCHECK_KICK;
1984                 case 0:
1985                         return HANGCHECK_WAIT;
1986                 }
1987         }
1988
1989         return HANGCHECK_HUNG;
1990 }
1991
1992 /**
1993  * This is called when the chip hasn't reported back with completed
1994  * batchbuffers in a long time. We keep track per ring seqno progress and
1995  * if there are no progress, hangcheck score for that ring is increased.
1996  * Further, acthd is inspected to see if the ring is stuck. On stuck case
1997  * we kick the ring. If we see no progress on three subsequent calls
1998  * we assume chip is wedged and try to fix it by resetting the chip.
1999  */
2000 static void i915_hangcheck_elapsed(unsigned long data)
2001 {
2002         struct drm_device *dev = (struct drm_device *)data;
2003         drm_i915_private_t *dev_priv = dev->dev_private;
2004         struct intel_ring_buffer *ring;
2005         int i;
2006         int busy_count = 0, rings_hung = 0;
2007         bool stuck[I915_NUM_RINGS] = { 0 };
2008 #define BUSY 1
2009 #define KICK 5
2010 #define HUNG 20
2011 #define FIRE 30
2012
2013         if (!i915_enable_hangcheck)
2014                 return;
2015
2016         for_each_ring(ring, dev_priv, i) {
2017                 u32 seqno, acthd;
2018                 bool busy = true;
2019
2020                 semaphore_clear_deadlocks(dev_priv);
2021
2022                 seqno = ring->get_seqno(ring, false);
2023                 acthd = intel_ring_get_active_head(ring);
2024
2025                 if (ring->hangcheck.seqno == seqno) {
2026                         if (ring_idle(ring, seqno)) {
2027                                 ring->hangcheck.action = HANGCHECK_IDLE;
2028
2029                                 if (waitqueue_active(&ring->irq_queue)) {
2030                                         /* Issue a wake-up to catch stuck h/w. */
2031                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
2032                                                 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2033                                                           ring->name);
2034                                                 wake_up_all(&ring->irq_queue);
2035                                         }
2036                                         /* Safeguard against driver failure */
2037                                         ring->hangcheck.score += BUSY;
2038                                 } else
2039                                         busy = false;
2040                         } else {
2041                                 /* We always increment the hangcheck score
2042                                  * if the ring is busy and still processing
2043                                  * the same request, so that no single request
2044                                  * can run indefinitely (such as a chain of
2045                                  * batches). The only time we do not increment
2046                                  * the hangcheck score on this ring, if this
2047                                  * ring is in a legitimate wait for another
2048                                  * ring. In that case the waiting ring is a
2049                                  * victim and we want to be sure we catch the
2050                                  * right culprit. Then every time we do kick
2051                                  * the ring, add a small increment to the
2052                                  * score so that we can catch a batch that is
2053                                  * being repeatedly kicked and so responsible
2054                                  * for stalling the machine.
2055                                  */
2056                                 ring->hangcheck.action = ring_stuck(ring,
2057                                                                     acthd);
2058
2059                                 switch (ring->hangcheck.action) {
2060                                 case HANGCHECK_IDLE:
2061                                 case HANGCHECK_WAIT:
2062                                         break;
2063                                 case HANGCHECK_ACTIVE:
2064                                         ring->hangcheck.score += BUSY;
2065                                         break;
2066                                 case HANGCHECK_KICK:
2067                                         ring->hangcheck.score += KICK;
2068                                         break;
2069                                 case HANGCHECK_HUNG:
2070                                         ring->hangcheck.score += HUNG;
2071                                         stuck[i] = true;
2072                                         break;
2073                                 }
2074                         }
2075                 } else {
2076                         ring->hangcheck.action = HANGCHECK_ACTIVE;
2077
2078                         /* Gradually reduce the count so that we catch DoS
2079                          * attempts across multiple batches.
2080                          */
2081                         if (ring->hangcheck.score > 0)
2082                                 ring->hangcheck.score--;
2083                 }
2084
2085                 ring->hangcheck.seqno = seqno;
2086                 ring->hangcheck.acthd = acthd;
2087                 busy_count += busy;
2088         }
2089
2090         for_each_ring(ring, dev_priv, i) {
2091                 if (ring->hangcheck.score > FIRE) {
2092                         DRM_INFO("%s on %s\n",
2093                                  stuck[i] ? "stuck" : "no progress",
2094                                  ring->name);
2095                         rings_hung++;
2096                 }
2097         }
2098
2099         if (rings_hung)
2100                 return i915_handle_error(dev, true);
2101
2102         if (busy_count)
2103                 /* Reset timer case chip hangs without another request
2104                  * being added */
2105                 i915_queue_hangcheck(dev);
2106 }
2107
2108 void i915_queue_hangcheck(struct drm_device *dev)
2109 {
2110         struct drm_i915_private *dev_priv = dev->dev_private;
2111         if (!i915_enable_hangcheck)
2112                 return;
2113
2114         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2115                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2116 }
2117
2118 static void ibx_irq_preinstall(struct drm_device *dev)
2119 {
2120         struct drm_i915_private *dev_priv = dev->dev_private;
2121
2122         if (HAS_PCH_NOP(dev))
2123                 return;
2124
2125         /* south display irq */
2126         I915_WRITE(SDEIMR, 0xffffffff);
2127         /*
2128          * SDEIER is also touched by the interrupt handler to work around missed
2129          * PCH interrupts. Hence we can't update it after the interrupt handler
2130          * is enabled - instead we unconditionally enable all PCH interrupt
2131          * sources here, but then only unmask them as needed with SDEIMR.
2132          */
2133         I915_WRITE(SDEIER, 0xffffffff);
2134         POSTING_READ(SDEIER);
2135 }
2136
2137 static void gen5_gt_irq_preinstall(struct drm_device *dev)
2138 {
2139         struct drm_i915_private *dev_priv = dev->dev_private;
2140
2141         /* and GT */
2142         I915_WRITE(GTIMR, 0xffffffff);
2143         I915_WRITE(GTIER, 0x0);
2144         POSTING_READ(GTIER);
2145
2146         if (INTEL_INFO(dev)->gen >= 6) {
2147                 /* and PM */
2148                 I915_WRITE(GEN6_PMIMR, 0xffffffff);
2149                 I915_WRITE(GEN6_PMIER, 0x0);
2150                 POSTING_READ(GEN6_PMIER);
2151         }
2152 }
2153
2154 /* drm_dma.h hooks
2155 */
2156 static void ironlake_irq_preinstall(struct drm_device *dev)
2157 {
2158         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2159
2160         atomic_set(&dev_priv->irq_received, 0);
2161
2162         I915_WRITE(HWSTAM, 0xeffe);
2163
2164         I915_WRITE(DEIMR, 0xffffffff);
2165         I915_WRITE(DEIER, 0x0);
2166         POSTING_READ(DEIER);
2167
2168         gen5_gt_irq_preinstall(dev);
2169
2170         ibx_irq_preinstall(dev);
2171 }
2172
2173 static void valleyview_irq_preinstall(struct drm_device *dev)
2174 {
2175         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2176         int pipe;
2177
2178         atomic_set(&dev_priv->irq_received, 0);
2179
2180         /* VLV magic */
2181         I915_WRITE(VLV_IMR, 0);
2182         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2183         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2184         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2185
2186         /* and GT */
2187         I915_WRITE(GTIIR, I915_READ(GTIIR));
2188         I915_WRITE(GTIIR, I915_READ(GTIIR));
2189
2190         gen5_gt_irq_preinstall(dev);
2191
2192         I915_WRITE(DPINVGTT, 0xff);
2193
2194         I915_WRITE(PORT_HOTPLUG_EN, 0);
2195         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2196         for_each_pipe(pipe)
2197                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2198         I915_WRITE(VLV_IIR, 0xffffffff);
2199         I915_WRITE(VLV_IMR, 0xffffffff);
2200         I915_WRITE(VLV_IER, 0x0);
2201         POSTING_READ(VLV_IER);
2202 }
2203
2204 static void ibx_hpd_irq_setup(struct drm_device *dev)
2205 {
2206         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2207         struct drm_mode_config *mode_config = &dev->mode_config;
2208         struct intel_encoder *intel_encoder;
2209         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
2210
2211         if (HAS_PCH_IBX(dev)) {
2212                 hotplug_irqs = SDE_HOTPLUG_MASK;
2213                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2214                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2215                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
2216         } else {
2217                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
2218                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2219                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2220                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
2221         }
2222
2223         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
2224
2225         /*
2226          * Enable digital hotplug on the PCH, and configure the DP short pulse
2227          * duration to 2ms (which is the minimum in the Display Port spec)
2228          *
2229          * This register is the same on all known PCH chips.
2230          */
2231         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2232         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2233         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2234         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2235         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2236         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2237 }
2238
2239 static void ibx_irq_postinstall(struct drm_device *dev)
2240 {
2241         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2242         u32 mask;
2243
2244         if (HAS_PCH_NOP(dev))
2245                 return;
2246
2247         if (HAS_PCH_IBX(dev)) {
2248                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_TRANSB_FIFO_UNDER |
2249                        SDE_TRANSA_FIFO_UNDER | SDE_POISON;
2250         } else {
2251                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT | SDE_ERROR_CPT;
2252
2253                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2254         }
2255
2256         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2257         I915_WRITE(SDEIMR, ~mask);
2258 }
2259
2260 static void gen5_gt_irq_postinstall(struct drm_device *dev)
2261 {
2262         struct drm_i915_private *dev_priv = dev->dev_private;
2263         u32 pm_irqs, gt_irqs;
2264
2265         pm_irqs = gt_irqs = 0;
2266
2267         dev_priv->gt_irq_mask = ~0;
2268         if (HAS_L3_DPF(dev)) {
2269                 /* L3 parity interrupt is always unmasked. */
2270                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
2271                 gt_irqs |= GT_PARITY_ERROR(dev);
2272         }
2273
2274         gt_irqs |= GT_RENDER_USER_INTERRUPT;
2275         if (IS_GEN5(dev)) {
2276                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
2277                            ILK_BSD_USER_INTERRUPT;
2278         } else {
2279                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
2280         }
2281
2282         I915_WRITE(GTIIR, I915_READ(GTIIR));
2283         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2284         I915_WRITE(GTIER, gt_irqs);
2285         POSTING_READ(GTIER);
2286
2287         if (INTEL_INFO(dev)->gen >= 6) {
2288                 pm_irqs |= GEN6_PM_RPS_EVENTS;
2289
2290                 if (HAS_VEBOX(dev))
2291                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
2292
2293                 dev_priv->pm_irq_mask = 0xffffffff;
2294                 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2295                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
2296                 I915_WRITE(GEN6_PMIER, pm_irqs);
2297                 POSTING_READ(GEN6_PMIER);
2298         }
2299 }
2300
2301 static int ironlake_irq_postinstall(struct drm_device *dev)
2302 {
2303         unsigned long irqflags;
2304         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2305         u32 display_mask, extra_mask;
2306
2307         if (INTEL_INFO(dev)->gen >= 7) {
2308                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2309                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
2310                                 DE_PLANEB_FLIP_DONE_IVB |
2311                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB |
2312                                 DE_ERR_INT_IVB);
2313                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
2314                               DE_PIPEA_VBLANK_IVB);
2315
2316                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2317         } else {
2318                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2319                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2320                                 DE_AUX_CHANNEL_A | DE_PIPEB_FIFO_UNDERRUN |
2321                                 DE_PIPEA_FIFO_UNDERRUN | DE_POISON);
2322                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT;
2323         }
2324
2325         dev_priv->irq_mask = ~display_mask;
2326
2327         /* should always can generate irq */
2328         I915_WRITE(DEIIR, I915_READ(DEIIR));
2329         I915_WRITE(DEIMR, dev_priv->irq_mask);
2330         I915_WRITE(DEIER, display_mask | extra_mask);
2331         POSTING_READ(DEIER);
2332
2333         gen5_gt_irq_postinstall(dev);
2334
2335         ibx_irq_postinstall(dev);
2336
2337         if (IS_IRONLAKE_M(dev)) {
2338                 /* Enable PCU event interrupts
2339                  *
2340                  * spinlocking not required here for correctness since interrupt
2341                  * setup is guaranteed to run in single-threaded context. But we
2342                  * need it to make the assert_spin_locked happy. */
2343                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2344                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2345                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2346         }
2347
2348         return 0;
2349 }
2350
2351 static int valleyview_irq_postinstall(struct drm_device *dev)
2352 {
2353         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2354         u32 enable_mask;
2355         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2356         unsigned long irqflags;
2357
2358         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2359         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2360                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2361                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2362                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2363
2364         /*
2365          *Leave vblank interrupts masked initially.  enable/disable will
2366          * toggle them based on usage.
2367          */
2368         dev_priv->irq_mask = (~enable_mask) |
2369                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2370                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2371
2372         I915_WRITE(PORT_HOTPLUG_EN, 0);
2373         POSTING_READ(PORT_HOTPLUG_EN);
2374
2375         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2376         I915_WRITE(VLV_IER, enable_mask);
2377         I915_WRITE(VLV_IIR, 0xffffffff);
2378         I915_WRITE(PIPESTAT(0), 0xffff);
2379         I915_WRITE(PIPESTAT(1), 0xffff);
2380         POSTING_READ(VLV_IER);
2381
2382         /* Interrupt setup is already guaranteed to be single-threaded, this is
2383          * just to make the assert_spin_locked check happy. */
2384         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2385         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2386         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2387         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2388         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2389
2390         I915_WRITE(VLV_IIR, 0xffffffff);
2391         I915_WRITE(VLV_IIR, 0xffffffff);
2392
2393         gen5_gt_irq_postinstall(dev);
2394
2395         /* ack & enable invalid PTE error interrupts */
2396 #if 0 /* FIXME: add support to irq handler for checking these bits */
2397         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2398         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2399 #endif
2400
2401         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2402
2403         return 0;
2404 }
2405
2406 static void valleyview_irq_uninstall(struct drm_device *dev)
2407 {
2408         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2409         int pipe;
2410
2411         if (!dev_priv)
2412                 return;
2413
2414         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2415
2416         for_each_pipe(pipe)
2417                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2418
2419         I915_WRITE(HWSTAM, 0xffffffff);
2420         I915_WRITE(PORT_HOTPLUG_EN, 0);
2421         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2422         for_each_pipe(pipe)
2423                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2424         I915_WRITE(VLV_IIR, 0xffffffff);
2425         I915_WRITE(VLV_IMR, 0xffffffff);
2426         I915_WRITE(VLV_IER, 0x0);
2427         POSTING_READ(VLV_IER);
2428 }
2429
2430 static void ironlake_irq_uninstall(struct drm_device *dev)
2431 {
2432         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2433
2434         if (!dev_priv)
2435                 return;
2436
2437         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2438
2439         I915_WRITE(HWSTAM, 0xffffffff);
2440
2441         I915_WRITE(DEIMR, 0xffffffff);
2442         I915_WRITE(DEIER, 0x0);
2443         I915_WRITE(DEIIR, I915_READ(DEIIR));
2444         if (IS_GEN7(dev))
2445                 I915_WRITE(GEN7_ERR_INT, I915_READ(GEN7_ERR_INT));
2446
2447         I915_WRITE(GTIMR, 0xffffffff);
2448         I915_WRITE(GTIER, 0x0);
2449         I915_WRITE(GTIIR, I915_READ(GTIIR));
2450
2451         if (HAS_PCH_NOP(dev))
2452                 return;
2453
2454         I915_WRITE(SDEIMR, 0xffffffff);
2455         I915_WRITE(SDEIER, 0x0);
2456         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2457         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
2458                 I915_WRITE(SERR_INT, I915_READ(SERR_INT));
2459 }
2460
2461 static void i8xx_irq_preinstall(struct drm_device * dev)
2462 {
2463         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2464         int pipe;
2465
2466         atomic_set(&dev_priv->irq_received, 0);
2467
2468         for_each_pipe(pipe)
2469                 I915_WRITE(PIPESTAT(pipe), 0);
2470         I915_WRITE16(IMR, 0xffff);
2471         I915_WRITE16(IER, 0x0);
2472         POSTING_READ16(IER);
2473 }
2474
2475 static int i8xx_irq_postinstall(struct drm_device *dev)
2476 {
2477         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2478
2479         I915_WRITE16(EMR,
2480                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2481
2482         /* Unmask the interrupts that we always want on. */
2483         dev_priv->irq_mask =
2484                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2485                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2486                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2487                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2488                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2489         I915_WRITE16(IMR, dev_priv->irq_mask);
2490
2491         I915_WRITE16(IER,
2492                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2493                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2494                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2495                      I915_USER_INTERRUPT);
2496         POSTING_READ16(IER);
2497
2498         return 0;
2499 }
2500
2501 /*
2502  * Returns true when a page flip has completed.
2503  */
2504 static bool i8xx_handle_vblank(struct drm_device *dev,
2505                                int pipe, u16 iir)
2506 {
2507         drm_i915_private_t *dev_priv = dev->dev_private;
2508         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2509
2510         if (!drm_handle_vblank(dev, pipe))
2511                 return false;
2512
2513         if ((iir & flip_pending) == 0)
2514                 return false;
2515
2516         intel_prepare_page_flip(dev, pipe);
2517
2518         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2519          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2520          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2521          * the flip is completed (no longer pending). Since this doesn't raise
2522          * an interrupt per se, we watch for the change at vblank.
2523          */
2524         if (I915_READ16(ISR) & flip_pending)
2525                 return false;
2526
2527         intel_finish_page_flip(dev, pipe);
2528
2529         return true;
2530 }
2531
2532 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2533 {
2534         struct drm_device *dev = (struct drm_device *) arg;
2535         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2536         u16 iir, new_iir;
2537         u32 pipe_stats[2];
2538         unsigned long irqflags;
2539         int pipe;
2540         u16 flip_mask =
2541                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2542                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2543
2544         atomic_inc(&dev_priv->irq_received);
2545
2546         iir = I915_READ16(IIR);
2547         if (iir == 0)
2548                 return IRQ_NONE;
2549
2550         while (iir & ~flip_mask) {
2551                 /* Can't rely on pipestat interrupt bit in iir as it might
2552                  * have been cleared after the pipestat interrupt was received.
2553                  * It doesn't set the bit in iir again, but it still produces
2554                  * interrupts (for non-MSI).
2555                  */
2556                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2557                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2558                         i915_handle_error(dev, false);
2559
2560                 for_each_pipe(pipe) {
2561                         int reg = PIPESTAT(pipe);
2562                         pipe_stats[pipe] = I915_READ(reg);
2563
2564                         /*
2565                          * Clear the PIPE*STAT regs before the IIR
2566                          */
2567                         if (pipe_stats[pipe] & 0x8000ffff) {
2568                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2569                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2570                                                          pipe_name(pipe));
2571                                 I915_WRITE(reg, pipe_stats[pipe]);
2572                         }
2573                 }
2574                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2575
2576                 I915_WRITE16(IIR, iir & ~flip_mask);
2577                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2578
2579                 i915_update_dri1_breadcrumb(dev);
2580
2581                 if (iir & I915_USER_INTERRUPT)
2582                         notify_ring(dev, &dev_priv->ring[RCS]);
2583
2584                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2585                     i8xx_handle_vblank(dev, 0, iir))
2586                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2587
2588                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2589                     i8xx_handle_vblank(dev, 1, iir))
2590                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2591
2592                 iir = new_iir;
2593         }
2594
2595         return IRQ_HANDLED;
2596 }
2597
2598 static void i8xx_irq_uninstall(struct drm_device * dev)
2599 {
2600         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2601         int pipe;
2602
2603         for_each_pipe(pipe) {
2604                 /* Clear enable bits; then clear status bits */
2605                 I915_WRITE(PIPESTAT(pipe), 0);
2606                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2607         }
2608         I915_WRITE16(IMR, 0xffff);
2609         I915_WRITE16(IER, 0x0);
2610         I915_WRITE16(IIR, I915_READ16(IIR));
2611 }
2612
2613 static void i915_irq_preinstall(struct drm_device * dev)
2614 {
2615         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2616         int pipe;
2617
2618         atomic_set(&dev_priv->irq_received, 0);
2619
2620         if (I915_HAS_HOTPLUG(dev)) {
2621                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2622                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2623         }
2624
2625         I915_WRITE16(HWSTAM, 0xeffe);
2626         for_each_pipe(pipe)
2627                 I915_WRITE(PIPESTAT(pipe), 0);
2628         I915_WRITE(IMR, 0xffffffff);
2629         I915_WRITE(IER, 0x0);
2630         POSTING_READ(IER);
2631 }
2632
2633 static int i915_irq_postinstall(struct drm_device *dev)
2634 {
2635         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2636         u32 enable_mask;
2637
2638         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2639
2640         /* Unmask the interrupts that we always want on. */
2641         dev_priv->irq_mask =
2642                 ~(I915_ASLE_INTERRUPT |
2643                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2644                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2645                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2646                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2647                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2648
2649         enable_mask =
2650                 I915_ASLE_INTERRUPT |
2651                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2652                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2653                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2654                 I915_USER_INTERRUPT;
2655
2656         if (I915_HAS_HOTPLUG(dev)) {
2657                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2658                 POSTING_READ(PORT_HOTPLUG_EN);
2659
2660                 /* Enable in IER... */
2661                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2662                 /* and unmask in IMR */
2663                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2664         }
2665
2666         I915_WRITE(IMR, dev_priv->irq_mask);
2667         I915_WRITE(IER, enable_mask);
2668         POSTING_READ(IER);
2669
2670         i915_enable_asle_pipestat(dev);
2671
2672         return 0;
2673 }
2674
2675 /*
2676  * Returns true when a page flip has completed.
2677  */
2678 static bool i915_handle_vblank(struct drm_device *dev,
2679                                int plane, int pipe, u32 iir)
2680 {
2681         drm_i915_private_t *dev_priv = dev->dev_private;
2682         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2683
2684         if (!drm_handle_vblank(dev, pipe))
2685                 return false;
2686
2687         if ((iir & flip_pending) == 0)
2688                 return false;
2689
2690         intel_prepare_page_flip(dev, plane);
2691
2692         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2693          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2694          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2695          * the flip is completed (no longer pending). Since this doesn't raise
2696          * an interrupt per se, we watch for the change at vblank.
2697          */
2698         if (I915_READ(ISR) & flip_pending)
2699                 return false;
2700
2701         intel_finish_page_flip(dev, pipe);
2702
2703         return true;
2704 }
2705
2706 static irqreturn_t i915_irq_handler(int irq, void *arg)
2707 {
2708         struct drm_device *dev = (struct drm_device *) arg;
2709         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2710         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2711         unsigned long irqflags;
2712         u32 flip_mask =
2713                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2714                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2715         int pipe, ret = IRQ_NONE;
2716
2717         atomic_inc(&dev_priv->irq_received);
2718
2719         iir = I915_READ(IIR);
2720         do {
2721                 bool irq_received = (iir & ~flip_mask) != 0;
2722                 bool blc_event = false;
2723
2724                 /* Can't rely on pipestat interrupt bit in iir as it might
2725                  * have been cleared after the pipestat interrupt was received.
2726                  * It doesn't set the bit in iir again, but it still produces
2727                  * interrupts (for non-MSI).
2728                  */
2729                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2730                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2731                         i915_handle_error(dev, false);
2732
2733                 for_each_pipe(pipe) {
2734                         int reg = PIPESTAT(pipe);
2735                         pipe_stats[pipe] = I915_READ(reg);
2736
2737                         /* Clear the PIPE*STAT regs before the IIR */
2738                         if (pipe_stats[pipe] & 0x8000ffff) {
2739                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2740                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2741                                                          pipe_name(pipe));
2742                                 I915_WRITE(reg, pipe_stats[pipe]);
2743                                 irq_received = true;
2744                         }
2745                 }
2746                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2747
2748                 if (!irq_received)
2749                         break;
2750
2751                 /* Consume port.  Then clear IIR or we'll miss events */
2752                 if ((I915_HAS_HOTPLUG(dev)) &&
2753                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2754                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2755                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2756
2757                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2758                                   hotplug_status);
2759
2760                         intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
2761
2762                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2763                         POSTING_READ(PORT_HOTPLUG_STAT);
2764                 }
2765
2766                 I915_WRITE(IIR, iir & ~flip_mask);
2767                 new_iir = I915_READ(IIR); /* Flush posted writes */
2768
2769                 if (iir & I915_USER_INTERRUPT)
2770                         notify_ring(dev, &dev_priv->ring[RCS]);
2771
2772                 for_each_pipe(pipe) {
2773                         int plane = pipe;
2774                         if (IS_MOBILE(dev))
2775                                 plane = !plane;
2776
2777                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2778                             i915_handle_vblank(dev, plane, pipe, iir))
2779                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2780
2781                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2782                                 blc_event = true;
2783                 }
2784
2785                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2786                         intel_opregion_asle_intr(dev);
2787
2788                 /* With MSI, interrupts are only generated when iir
2789                  * transitions from zero to nonzero.  If another bit got
2790                  * set while we were handling the existing iir bits, then
2791                  * we would never get another interrupt.
2792                  *
2793                  * This is fine on non-MSI as well, as if we hit this path
2794                  * we avoid exiting the interrupt handler only to generate
2795                  * another one.
2796                  *
2797                  * Note that for MSI this could cause a stray interrupt report
2798                  * if an interrupt landed in the time between writing IIR and
2799                  * the posting read.  This should be rare enough to never
2800                  * trigger the 99% of 100,000 interrupts test for disabling
2801                  * stray interrupts.
2802                  */
2803                 ret = IRQ_HANDLED;
2804                 iir = new_iir;
2805         } while (iir & ~flip_mask);
2806
2807         i915_update_dri1_breadcrumb(dev);
2808
2809         return ret;
2810 }
2811
2812 static void i915_irq_uninstall(struct drm_device * dev)
2813 {
2814         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2815         int pipe;
2816
2817         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2818
2819         if (I915_HAS_HOTPLUG(dev)) {
2820                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2821                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2822         }
2823
2824         I915_WRITE16(HWSTAM, 0xffff);
2825         for_each_pipe(pipe) {
2826                 /* Clear enable bits; then clear status bits */
2827                 I915_WRITE(PIPESTAT(pipe), 0);
2828                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2829         }
2830         I915_WRITE(IMR, 0xffffffff);
2831         I915_WRITE(IER, 0x0);
2832
2833         I915_WRITE(IIR, I915_READ(IIR));
2834 }
2835
2836 static void i965_irq_preinstall(struct drm_device * dev)
2837 {
2838         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2839         int pipe;
2840
2841         atomic_set(&dev_priv->irq_received, 0);
2842
2843         I915_WRITE(PORT_HOTPLUG_EN, 0);
2844         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2845
2846         I915_WRITE(HWSTAM, 0xeffe);
2847         for_each_pipe(pipe)
2848                 I915_WRITE(PIPESTAT(pipe), 0);
2849         I915_WRITE(IMR, 0xffffffff);
2850         I915_WRITE(IER, 0x0);
2851         POSTING_READ(IER);
2852 }
2853
2854 static int i965_irq_postinstall(struct drm_device *dev)
2855 {
2856         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2857         u32 enable_mask;
2858         u32 error_mask;
2859         unsigned long irqflags;
2860
2861         /* Unmask the interrupts that we always want on. */
2862         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2863                                I915_DISPLAY_PORT_INTERRUPT |
2864                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2865                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2866                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2867                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2868                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2869
2870         enable_mask = ~dev_priv->irq_mask;
2871         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2872                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2873         enable_mask |= I915_USER_INTERRUPT;
2874
2875         if (IS_G4X(dev))
2876                 enable_mask |= I915_BSD_USER_INTERRUPT;
2877
2878         /* Interrupt setup is already guaranteed to be single-threaded, this is
2879          * just to make the assert_spin_locked check happy. */
2880         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2881         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2882         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2883
2884         /*
2885          * Enable some error detection, note the instruction error mask
2886          * bit is reserved, so we leave it masked.
2887          */
2888         if (IS_G4X(dev)) {
2889                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2890                                GM45_ERROR_MEM_PRIV |
2891                                GM45_ERROR_CP_PRIV |
2892                                I915_ERROR_MEMORY_REFRESH);
2893         } else {
2894                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2895                                I915_ERROR_MEMORY_REFRESH);
2896         }
2897         I915_WRITE(EMR, error_mask);
2898
2899         I915_WRITE(IMR, dev_priv->irq_mask);
2900         I915_WRITE(IER, enable_mask);
2901         POSTING_READ(IER);
2902
2903         I915_WRITE(PORT_HOTPLUG_EN, 0);
2904         POSTING_READ(PORT_HOTPLUG_EN);
2905
2906         i915_enable_asle_pipestat(dev);
2907
2908         return 0;
2909 }
2910
2911 static void i915_hpd_irq_setup(struct drm_device *dev)
2912 {
2913         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2914         struct drm_mode_config *mode_config = &dev->mode_config;
2915         struct intel_encoder *intel_encoder;
2916         u32 hotplug_en;
2917
2918         assert_spin_locked(&dev_priv->irq_lock);
2919
2920         if (I915_HAS_HOTPLUG(dev)) {
2921                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2922                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2923                 /* Note HDMI and DP share hotplug bits */
2924                 /* enable bits are the same for all generations */
2925                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2926                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2927                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2928                 /* Programming the CRT detection parameters tends
2929                    to generate a spurious hotplug event about three
2930                    seconds later.  So just do it once.
2931                 */
2932                 if (IS_G4X(dev))
2933                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2934                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2935                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2936
2937                 /* Ignore TV since it's buggy */
2938                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2939         }
2940 }
2941
2942 static irqreturn_t i965_irq_handler(int irq, void *arg)
2943 {
2944         struct drm_device *dev = (struct drm_device *) arg;
2945         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2946         u32 iir, new_iir;
2947         u32 pipe_stats[I915_MAX_PIPES];
2948         unsigned long irqflags;
2949         int irq_received;
2950         int ret = IRQ_NONE, pipe;
2951         u32 flip_mask =
2952                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2953                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2954
2955         atomic_inc(&dev_priv->irq_received);
2956
2957         iir = I915_READ(IIR);
2958
2959         for (;;) {
2960                 bool blc_event = false;
2961
2962                 irq_received = (iir & ~flip_mask) != 0;
2963
2964                 /* Can't rely on pipestat interrupt bit in iir as it might
2965                  * have been cleared after the pipestat interrupt was received.
2966                  * It doesn't set the bit in iir again, but it still produces
2967                  * interrupts (for non-MSI).
2968                  */
2969                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2970                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2971                         i915_handle_error(dev, false);
2972
2973                 for_each_pipe(pipe) {
2974                         int reg = PIPESTAT(pipe);
2975                         pipe_stats[pipe] = I915_READ(reg);
2976
2977                         /*
2978                          * Clear the PIPE*STAT regs before the IIR
2979                          */
2980                         if (pipe_stats[pipe] & 0x8000ffff) {
2981                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2982                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2983                                                          pipe_name(pipe));
2984                                 I915_WRITE(reg, pipe_stats[pipe]);
2985                                 irq_received = 1;
2986                         }
2987                 }
2988                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2989
2990                 if (!irq_received)
2991                         break;
2992
2993                 ret = IRQ_HANDLED;
2994
2995                 /* Consume port.  Then clear IIR or we'll miss events */
2996                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2997                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2998                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2999                                                                   HOTPLUG_INT_STATUS_G4X :
3000                                                                   HOTPLUG_INT_STATUS_I915);
3001
3002                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
3003                                   hotplug_status);
3004
3005                         intel_hpd_irq_handler(dev, hotplug_trigger,
3006                                               IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3007
3008                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3009                         I915_READ(PORT_HOTPLUG_STAT);
3010                 }
3011
3012                 I915_WRITE(IIR, iir & ~flip_mask);
3013                 new_iir = I915_READ(IIR); /* Flush posted writes */
3014
3015                 if (iir & I915_USER_INTERRUPT)
3016                         notify_ring(dev, &dev_priv->ring[RCS]);
3017                 if (iir & I915_BSD_USER_INTERRUPT)
3018                         notify_ring(dev, &dev_priv->ring[VCS]);
3019
3020                 for_each_pipe(pipe) {
3021                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
3022                             i915_handle_vblank(dev, pipe, pipe, iir))
3023                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
3024
3025                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3026                                 blc_event = true;
3027                 }
3028
3029
3030                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
3031                         intel_opregion_asle_intr(dev);
3032
3033                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
3034                         gmbus_irq_handler(dev);
3035
3036                 /* With MSI, interrupts are only generated when iir
3037                  * transitions from zero to nonzero.  If another bit got
3038                  * set while we were handling the existing iir bits, then
3039                  * we would never get another interrupt.
3040                  *
3041                  * This is fine on non-MSI as well, as if we hit this path
3042                  * we avoid exiting the interrupt handler only to generate
3043                  * another one.
3044                  *
3045                  * Note that for MSI this could cause a stray interrupt report
3046                  * if an interrupt landed in the time between writing IIR and
3047                  * the posting read.  This should be rare enough to never
3048                  * trigger the 99% of 100,000 interrupts test for disabling
3049                  * stray interrupts.
3050                  */
3051                 iir = new_iir;
3052         }
3053
3054         i915_update_dri1_breadcrumb(dev);
3055
3056         return ret;
3057 }
3058
3059 static void i965_irq_uninstall(struct drm_device * dev)
3060 {
3061         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3062         int pipe;
3063
3064         if (!dev_priv)
3065                 return;
3066
3067         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3068
3069         I915_WRITE(PORT_HOTPLUG_EN, 0);
3070         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3071
3072         I915_WRITE(HWSTAM, 0xffffffff);
3073         for_each_pipe(pipe)
3074                 I915_WRITE(PIPESTAT(pipe), 0);
3075         I915_WRITE(IMR, 0xffffffff);
3076         I915_WRITE(IER, 0x0);
3077
3078         for_each_pipe(pipe)
3079                 I915_WRITE(PIPESTAT(pipe),
3080                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3081         I915_WRITE(IIR, I915_READ(IIR));
3082 }
3083
3084 static void i915_reenable_hotplug_timer_func(unsigned long data)
3085 {
3086         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3087         struct drm_device *dev = dev_priv->dev;
3088         struct drm_mode_config *mode_config = &dev->mode_config;
3089         unsigned long irqflags;
3090         int i;
3091
3092         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3093         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3094                 struct drm_connector *connector;
3095
3096                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3097                         continue;
3098
3099                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3100
3101                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3102                         struct intel_connector *intel_connector = to_intel_connector(connector);
3103
3104                         if (intel_connector->encoder->hpd_pin == i) {
3105                                 if (connector->polled != intel_connector->polled)
3106                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3107                                                          drm_get_connector_name(connector));
3108                                 connector->polled = intel_connector->polled;
3109                                 if (!connector->polled)
3110                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3111                         }
3112                 }
3113         }
3114         if (dev_priv->display.hpd_irq_setup)
3115                 dev_priv->display.hpd_irq_setup(dev);
3116         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3117 }
3118
3119 void intel_irq_init(struct drm_device *dev)
3120 {
3121         struct drm_i915_private *dev_priv = dev->dev_private;
3122
3123         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3124         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3125         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3126         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3127
3128         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3129                     i915_hangcheck_elapsed,
3130                     (unsigned long) dev);
3131         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3132                     (unsigned long) dev_priv);
3133
3134         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3135
3136         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3137         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3138         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3139                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3140                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3141         }
3142
3143         if (drm_core_check_feature(dev, DRIVER_MODESET))
3144                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3145         else
3146                 dev->driver->get_vblank_timestamp = NULL;
3147         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3148
3149         if (IS_VALLEYVIEW(dev)) {
3150                 dev->driver->irq_handler = valleyview_irq_handler;
3151                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3152                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3153                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3154                 dev->driver->enable_vblank = valleyview_enable_vblank;
3155                 dev->driver->disable_vblank = valleyview_disable_vblank;
3156                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3157         } else if (HAS_PCH_SPLIT(dev)) {
3158                 dev->driver->irq_handler = ironlake_irq_handler;
3159                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3160                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3161                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3162                 dev->driver->enable_vblank = ironlake_enable_vblank;
3163                 dev->driver->disable_vblank = ironlake_disable_vblank;
3164                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3165         } else {
3166                 if (INTEL_INFO(dev)->gen == 2) {
3167                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3168                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3169                         dev->driver->irq_handler = i8xx_irq_handler;
3170                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3171                 } else if (INTEL_INFO(dev)->gen == 3) {
3172                         dev->driver->irq_preinstall = i915_irq_preinstall;
3173                         dev->driver->irq_postinstall = i915_irq_postinstall;
3174                         dev->driver->irq_uninstall = i915_irq_uninstall;
3175                         dev->driver->irq_handler = i915_irq_handler;
3176                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3177                 } else {
3178                         dev->driver->irq_preinstall = i965_irq_preinstall;
3179                         dev->driver->irq_postinstall = i965_irq_postinstall;
3180                         dev->driver->irq_uninstall = i965_irq_uninstall;
3181                         dev->driver->irq_handler = i965_irq_handler;
3182                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3183                 }
3184                 dev->driver->enable_vblank = i915_enable_vblank;
3185                 dev->driver->disable_vblank = i915_disable_vblank;
3186         }
3187 }
3188
3189 void intel_hpd_init(struct drm_device *dev)
3190 {
3191         struct drm_i915_private *dev_priv = dev->dev_private;
3192         struct drm_mode_config *mode_config = &dev->mode_config;
3193         struct drm_connector *connector;
3194         unsigned long irqflags;
3195         int i;
3196
3197         for (i = 1; i < HPD_NUM_PINS; i++) {
3198                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3199                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3200         }
3201         list_for_each_entry(connector, &mode_config->connector_list, head) {
3202                 struct intel_connector *intel_connector = to_intel_connector(connector);
3203                 connector->polled = intel_connector->polled;
3204                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3205                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3206         }
3207
3208         /* Interrupt setup is already guaranteed to be single-threaded, this is
3209          * just to make the assert_spin_locked checks happy. */
3210         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3211         if (dev_priv->display.hpd_irq_setup)
3212                 dev_priv->display.hpd_irq_setup(dev);
3213         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3214 }
3215
3216 /* Disable interrupts so we can allow Package C8+. */
3217 void hsw_pc8_disable_interrupts(struct drm_device *dev)
3218 {
3219         struct drm_i915_private *dev_priv = dev->dev_private;
3220         unsigned long irqflags;
3221
3222         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3223
3224         dev_priv->pc8.regsave.deimr = I915_READ(DEIMR);
3225         dev_priv->pc8.regsave.sdeimr = I915_READ(SDEIMR);
3226         dev_priv->pc8.regsave.gtimr = I915_READ(GTIMR);
3227         dev_priv->pc8.regsave.gtier = I915_READ(GTIER);
3228         dev_priv->pc8.regsave.gen6_pmimr = I915_READ(GEN6_PMIMR);
3229
3230         ironlake_disable_display_irq(dev_priv, ~DE_PCH_EVENT_IVB);
3231         ibx_disable_display_interrupt(dev_priv, ~SDE_HOTPLUG_MASK_CPT);
3232         ilk_disable_gt_irq(dev_priv, 0xffffffff);
3233         snb_disable_pm_irq(dev_priv, 0xffffffff);
3234
3235         dev_priv->pc8.irqs_disabled = true;
3236
3237         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3238 }
3239
3240 /* Restore interrupts so we can recover from Package C8+. */
3241 void hsw_pc8_restore_interrupts(struct drm_device *dev)
3242 {
3243         struct drm_i915_private *dev_priv = dev->dev_private;
3244         unsigned long irqflags;
3245         uint32_t val, expected;
3246
3247         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3248
3249         val = I915_READ(DEIMR);
3250         expected = ~DE_PCH_EVENT_IVB;
3251         WARN(val != expected, "DEIMR is 0x%08x, not 0x%08x\n", val, expected);
3252
3253         val = I915_READ(SDEIMR) & ~SDE_HOTPLUG_MASK_CPT;
3254         expected = ~SDE_HOTPLUG_MASK_CPT;
3255         WARN(val != expected, "SDEIMR non-HPD bits are 0x%08x, not 0x%08x\n",
3256              val, expected);
3257
3258         val = I915_READ(GTIMR);
3259         expected = 0xffffffff;
3260         WARN(val != expected, "GTIMR is 0x%08x, not 0x%08x\n", val, expected);
3261
3262         val = I915_READ(GEN6_PMIMR);
3263         expected = 0xffffffff;
3264         WARN(val != expected, "GEN6_PMIMR is 0x%08x, not 0x%08x\n", val,
3265              expected);
3266
3267         dev_priv->pc8.irqs_disabled = false;
3268
3269         ironlake_enable_display_irq(dev_priv, ~dev_priv->pc8.regsave.deimr);
3270         ibx_enable_display_interrupt(dev_priv,
3271                                      ~dev_priv->pc8.regsave.sdeimr &
3272                                      ~SDE_HOTPLUG_MASK_CPT);
3273         ilk_enable_gt_irq(dev_priv, ~dev_priv->pc8.regsave.gtimr);
3274         snb_enable_pm_irq(dev_priv, ~dev_priv->pc8.regsave.gen6_pmimr);
3275         I915_WRITE(GTIER, dev_priv->pc8.regsave.gtier);
3276
3277         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3278 }