drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 static const u32 hpd_ibx[] = {
  41         [HPD_CRT] = SDE_CRT_HOTPLUG,
  42         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  43         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  44         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  45         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  46 };
  47
  48 static const u32 hpd_cpt[] = {
  49         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  50         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  51         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  52         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  53         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  54 };
  55
  56 static const u32 hpd_mask_i915[] = {
  57         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  58         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  59         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  60         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  61         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  62         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  63 };
  64
  65 static const u32 hpd_status_g4x[] = {
  66         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  67         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  69         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  71         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  72 };
  73
  74 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  75         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  76         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  77         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  78         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  79         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  80         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  81 };
  82
  83 /* IIR can theoretically queue up two events. Be paranoid. */
  84 #define GEN8_IRQ_RESET_NDX(type, which) do { \
  85         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
  86         POSTING_READ(GEN8_##type##_IMR(which)); \
  87         I915_WRITE(GEN8_##type##_IER(which), 0); \
  88         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  89         POSTING_READ(GEN8_##type##_IIR(which)); \
  90         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
  91         POSTING_READ(GEN8_##type##_IIR(which)); \
  92 } while (0)
  93
  94 #define GEN5_IRQ_RESET(type) do { \
  95         I915_WRITE(type##IMR, 0xffffffff); \
  96         POSTING_READ(type##IMR); \
  97         I915_WRITE(type##IER, 0); \
  98         I915_WRITE(type##IIR, 0xffffffff); \
  99         POSTING_READ(type##IIR); \
 100         I915_WRITE(type##IIR, 0xffffffff); \
 101         POSTING_READ(type##IIR); \
 102 } while (0)
 103
 104 /*
 105  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 106  */
 107 #define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
 108         u32 val = I915_READ(reg); \
 109         if (val) { \
 110                 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
 111                      (reg), val); \
 112                 I915_WRITE((reg), 0xffffffff); \
 113                 POSTING_READ(reg); \
 114                 I915_WRITE((reg), 0xffffffff); \
 115                 POSTING_READ(reg); \
 116         } \
 117 } while (0)
 118
 119 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 120         GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
 121         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 122         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 123         POSTING_READ(GEN8_##type##_IER(which)); \
 124 } while (0)
 125
 126 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 127         GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
 128         I915_WRITE(type##IMR, (imr_val)); \
 129         I915_WRITE(type##IER, (ier_val)); \
 130         POSTING_READ(type##IER); \
 131 } while (0)
 132
 133 /* For display hotplug interrupt */
 134 static void
 135 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 136 {
 137         assert_spin_locked(&dev_priv->irq_lock);
 138
 139         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 140                 return;
 141
 142         if ((dev_priv->irq_mask & mask) != 0) {
 143                 dev_priv->irq_mask &= ~mask;
 144                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 145                 POSTING_READ(DEIMR);
 146         }
 147 }
 148
 149 static void
 150 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
 151 {
 152         assert_spin_locked(&dev_priv->irq_lock);
 153
 154         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 155                 return;
 156
 157         if ((dev_priv->irq_mask & mask) != mask) {
 158                 dev_priv->irq_mask |= mask;
 159                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 160                 POSTING_READ(DEIMR);
 161         }
 162 }
 163
 164 /**
 165  * ilk_update_gt_irq - update GTIMR
 166  * @dev_priv: driver private
 167  * @interrupt_mask: mask of interrupt bits to update
 168  * @enabled_irq_mask: mask of interrupt bits to enable
 169  */
 170 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 171                               uint32_t interrupt_mask,
 172                               uint32_t enabled_irq_mask)
 173 {
 174         assert_spin_locked(&dev_priv->irq_lock);
 175
 176         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 177                 return;
 178
 179         dev_priv->gt_irq_mask &= ~interrupt_mask;
 180         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 181         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 182         POSTING_READ(GTIMR);
 183 }
 184
 185 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 186 {
 187         ilk_update_gt_irq(dev_priv, mask, mask);
 188 }
 189
 190 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 191 {
 192         ilk_update_gt_irq(dev_priv, mask, 0);
 193 }
 194
 195 /**
 196   * snb_update_pm_irq - update GEN6_PMIMR
 197   * @dev_priv: driver private
 198   * @interrupt_mask: mask of interrupt bits to update
 199   * @enabled_irq_mask: mask of interrupt bits to enable
 200   */
 201 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 202                               uint32_t interrupt_mask,
 203                               uint32_t enabled_irq_mask)
 204 {
 205         uint32_t new_val;
 206
 207         assert_spin_locked(&dev_priv->irq_lock);
 208
 209         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 210                 return;
 211
 212         new_val = dev_priv->pm_irq_mask;
 213         new_val &= ~interrupt_mask;
 214         new_val |= (~enabled_irq_mask & interrupt_mask);
 215
 216         if (new_val != dev_priv->pm_irq_mask) {
 217                 dev_priv->pm_irq_mask = new_val;
 218                 I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask);
 219                 POSTING_READ(GEN6_PMIMR);
 220         }
 221 }
 222
 223 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 224 {
 225         snb_update_pm_irq(dev_priv, mask, mask);
 226 }
 227
 228 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 229 {
 230         snb_update_pm_irq(dev_priv, mask, 0);
 231 }
 232
 233 static bool ivb_can_enable_err_int(struct drm_device *dev)
 234 {
 235         struct drm_i915_private *dev_priv = dev->dev_private;
 236         struct intel_crtc *crtc;
 237         enum pipe pipe;
 238
 239         assert_spin_locked(&dev_priv->irq_lock);
 240
 241         for_each_pipe(pipe) {
 242                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 243
 244                 if (crtc->cpu_fifo_underrun_disabled)
 245                         return false;
 246         }
 247
 248         return true;
 249 }
 250
 251 /**
 252   * bdw_update_pm_irq - update GT interrupt 2
 253   * @dev_priv: driver private
 254   * @interrupt_mask: mask of interrupt bits to update
 255   * @enabled_irq_mask: mask of interrupt bits to enable
 256   *
 257   * Copied from the snb function, updated with relevant register offsets
 258   */
 259 static void bdw_update_pm_irq(struct drm_i915_private *dev_priv,
 260                               uint32_t interrupt_mask,
 261                               uint32_t enabled_irq_mask)
 262 {
 263         uint32_t new_val;
 264
 265         assert_spin_locked(&dev_priv->irq_lock);
 266
 267         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 268                 return;
 269
 270         new_val = dev_priv->pm_irq_mask;
 271         new_val &= ~interrupt_mask;
 272         new_val |= (~enabled_irq_mask & interrupt_mask);
 273
 274         if (new_val != dev_priv->pm_irq_mask) {
 275                 dev_priv->pm_irq_mask = new_val;
 276                 I915_WRITE(GEN8_GT_IMR(2), dev_priv->pm_irq_mask);
 277                 POSTING_READ(GEN8_GT_IMR(2));
 278         }
 279 }
 280
 281 void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 282 {
 283         bdw_update_pm_irq(dev_priv, mask, mask);
 284 }
 285
 286 void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 287 {
 288         bdw_update_pm_irq(dev_priv, mask, 0);
 289 }
 290
 291 static bool cpt_can_enable_serr_int(struct drm_device *dev)
 292 {
 293         struct drm_i915_private *dev_priv = dev->dev_private;
 294         enum pipe pipe;
 295         struct intel_crtc *crtc;
 296
 297         assert_spin_locked(&dev_priv->irq_lock);
 298
 299         for_each_pipe(pipe) {
 300                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 301
 302                 if (crtc->pch_fifo_underrun_disabled)
 303                         return false;
 304         }
 305
 306         return true;
 307 }
 308
 309 void i9xx_check_fifo_underruns(struct drm_device *dev)
 310 {
 311         struct drm_i915_private *dev_priv = dev->dev_private;
 312         struct intel_crtc *crtc;
 313         unsigned long flags;
 314
 315         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 316
 317         for_each_intel_crtc(dev, crtc) {
 318                 u32 reg = PIPESTAT(crtc->pipe);
 319                 u32 pipestat;
 320
 321                 if (crtc->cpu_fifo_underrun_disabled)
 322                         continue;
 323
 324                 pipestat = I915_READ(reg) & 0xffff0000;
 325                 if ((pipestat & PIPE_FIFO_UNDERRUN_STATUS) == 0)
 326                         continue;
 327
 328                 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 329                 POSTING_READ(reg);
 330
 331                 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe));
 332         }
 333
 334         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 335 }
 336
 337 static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev,
 338                                              enum pipe pipe,
 339                                              bool enable, bool old)
 340 {
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         u32 reg = PIPESTAT(pipe);
 343         u32 pipestat = I915_READ(reg) & 0xffff0000;
 344
 345         assert_spin_locked(&dev_priv->irq_lock);
 346
 347         if (enable) {
 348                 I915_WRITE(reg, pipestat | PIPE_FIFO_UNDERRUN_STATUS);
 349                 POSTING_READ(reg);
 350         } else {
 351                 if (old && pipestat & PIPE_FIFO_UNDERRUN_STATUS)
 352                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
 353         }
 354 }
 355
 356 static void ironlake_set_fifo_underrun_reporting(struct drm_device *dev,
 357                                                  enum pipe pipe, bool enable)
 358 {
 359         struct drm_i915_private *dev_priv = dev->dev_private;
 360         uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN :
 361                                           DE_PIPEB_FIFO_UNDERRUN;
 362
 363         if (enable)
 364                 ironlake_enable_display_irq(dev_priv, bit);
 365         else
 366                 ironlake_disable_display_irq(dev_priv, bit);
 367 }
 368
 369 static void ivybridge_set_fifo_underrun_reporting(struct drm_device *dev,
 370                                                   enum pipe pipe,
 371                                                   bool enable, bool old)
 372 {
 373         struct drm_i915_private *dev_priv = dev->dev_private;
 374         if (enable) {
 375                 I915_WRITE(GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe));
 376
 377                 if (!ivb_can_enable_err_int(dev))
 378                         return;
 379
 380                 ironlake_enable_display_irq(dev_priv, DE_ERR_INT_IVB);
 381         } else {
 382                 ironlake_disable_display_irq(dev_priv, DE_ERR_INT_IVB);
 383
 384                 if (old &&
 385                     I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) {
 386                         DRM_ERROR("uncleared fifo underrun on pipe %c\n",
 387                                   pipe_name(pipe));
 388                 }
 389         }
 390 }
 391
 392 static void broadwell_set_fifo_underrun_reporting(struct drm_device *dev,
 393                                                   enum pipe pipe, bool enable)
 394 {
 395         struct drm_i915_private *dev_priv = dev->dev_private;
 396
 397         assert_spin_locked(&dev_priv->irq_lock);
 398
 399         if (enable)
 400                 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_FIFO_UNDERRUN;
 401         else
 402                 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_FIFO_UNDERRUN;
 403         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 404         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 405 }
 406
 407 /**
 408  * ibx_display_interrupt_update - update SDEIMR
 409  * @dev_priv: driver private
 410  * @interrupt_mask: mask of interrupt bits to update
 411  * @enabled_irq_mask: mask of interrupt bits to enable
 412  */
 413 static void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 414                                          uint32_t interrupt_mask,
 415                                          uint32_t enabled_irq_mask)
 416 {
 417         uint32_t sdeimr = I915_READ(SDEIMR);
 418         sdeimr &= ~interrupt_mask;
 419         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 420
 421         assert_spin_locked(&dev_priv->irq_lock);
 422
 423         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 424                 return;
 425
 426         I915_WRITE(SDEIMR, sdeimr);
 427         POSTING_READ(SDEIMR);
 428 }
 429 #define ibx_enable_display_interrupt(dev_priv, bits) \
 430         ibx_display_interrupt_update((dev_priv), (bits), (bits))
 431 #define ibx_disable_display_interrupt(dev_priv, bits) \
 432         ibx_display_interrupt_update((dev_priv), (bits), 0)
 433
 434 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
 435                                             enum transcoder pch_transcoder,
 436                                             bool enable)
 437 {
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439         uint32_t bit = (pch_transcoder == TRANSCODER_A) ?
 440                        SDE_TRANSA_FIFO_UNDER : SDE_TRANSB_FIFO_UNDER;
 441
 442         if (enable)
 443                 ibx_enable_display_interrupt(dev_priv, bit);
 444         else
 445                 ibx_disable_display_interrupt(dev_priv, bit);
 446 }
 447
 448 static void cpt_set_fifo_underrun_reporting(struct drm_device *dev,
 449                                             enum transcoder pch_transcoder,
 450                                             bool enable, bool old)
 451 {
 452         struct drm_i915_private *dev_priv = dev->dev_private;
 453
 454         if (enable) {
 455                 I915_WRITE(SERR_INT,
 456                            SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder));
 457
 458                 if (!cpt_can_enable_serr_int(dev))
 459                         return;
 460
 461                 ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 462         } else {
 463                 ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);
 464
 465                 if (old && I915_READ(SERR_INT) &
 466                     SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) {
 467                         DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n",
 468                                   transcoder_name(pch_transcoder));
 469                 }
 470         }
 471 }
 472
 473 /**
 474  * intel_set_cpu_fifo_underrun_reporting - enable/disable FIFO underrun messages
 475  * @dev: drm device
 476  * @pipe: pipe
 477  * @enable: true if we want to report FIFO underrun errors, false otherwise
 478  *
 479  * This function makes us disable or enable CPU fifo underruns for a specific
 480  * pipe. Notice that on some Gens (e.g. IVB, HSW), disabling FIFO underrun
 481  * reporting for one pipe may also disable all the other CPU error interruts for
 482  * the other pipes, due to the fact that there's just one interrupt mask/enable
 483  * bit for all the pipes.
 484  *
 485  * Returns the previous state of underrun reporting.
 486  */
 487 static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 488                                                     enum pipe pipe, bool enable)
 489 {
 490         struct drm_i915_private *dev_priv = dev->dev_private;
 491         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 492         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 493         bool old;
 494
 495         assert_spin_locked(&dev_priv->irq_lock);
 496
 497         old = !intel_crtc->cpu_fifo_underrun_disabled;
 498         intel_crtc->cpu_fifo_underrun_disabled = !enable;
 499
 500         if (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
 501                 i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
 502         else if (IS_GEN5(dev) || IS_GEN6(dev))
 503                 ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
 504         else if (IS_GEN7(dev))
 505                 ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
 506         else if (IS_GEN8(dev))
 507                 broadwell_set_fifo_underrun_reporting(dev, pipe, enable);
 508
 509         return old;
 510 }
 511
 512 bool intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
 513                                            enum pipe pipe, bool enable)
 514 {
 515         struct drm_i915_private *dev_priv = dev->dev_private;
 516         unsigned long flags;
 517         bool ret;
 518
 519         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 520         ret = __intel_set_cpu_fifo_underrun_reporting(dev, pipe, enable);
 521         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 522
 523         return ret;
 524 }
 525
 526 static bool __cpu_fifo_underrun_reporting_enabled(struct drm_device *dev,
 527                                                   enum pipe pipe)
 528 {
 529         struct drm_i915_private *dev_priv = dev->dev_private;
 530         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 531         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 532
 533         return !intel_crtc->cpu_fifo_underrun_disabled;
 534 }
 535
 536 /**
 537  * intel_set_pch_fifo_underrun_reporting - enable/disable FIFO underrun messages
 538  * @dev: drm device
 539  * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
 540  * @enable: true if we want to report FIFO underrun errors, false otherwise
 541  *
 542  * This function makes us disable or enable PCH fifo underruns for a specific
 543  * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
 544  * underrun reporting for one transcoder may also disable all the other PCH
 545  * error interruts for the other transcoders, due to the fact that there's just
 546  * one interrupt mask/enable bit for all the transcoders.
 547  *
 548  * Returns the previous state of underrun reporting.
 549  */
 550 bool intel_set_pch_fifo_underrun_reporting(struct drm_device *dev,
 551                                            enum transcoder pch_transcoder,
 552                                            bool enable)
 553 {
 554         struct drm_i915_private *dev_priv = dev->dev_private;
 555         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pch_transcoder];
 556         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 557         unsigned long flags;
 558         bool old;
 559
 560         /*
 561          * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT
 562          * has only one pch transcoder A that all pipes can use. To avoid racy
 563          * pch transcoder -> pipe lookups from interrupt code simply store the
 564          * underrun statistics in crtc A. Since we never expose this anywhere
 565          * nor use it outside of the fifo underrun code here using the "wrong"
 566          * crtc on LPT won't cause issues.
 567          */
 568
 569         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 570
 571         old = !intel_crtc->pch_fifo_underrun_disabled;
 572         intel_crtc->pch_fifo_underrun_disabled = !enable;
 573
 574         if (HAS_PCH_IBX(dev))
 575                 ibx_set_fifo_underrun_reporting(dev, pch_transcoder, enable);
 576         else
 577                 cpt_set_fifo_underrun_reporting(dev, pch_transcoder, enable, old);
 578
 579         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 580         return old;
 581 }
 582
 583
 584 static void
 585 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 586                        u32 enable_mask, u32 status_mask)
 587 {
 588         u32 reg = PIPESTAT(pipe);
 589         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 590
 591         assert_spin_locked(&dev_priv->irq_lock);
 592
 593         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 594                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 595                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 596                       pipe_name(pipe), enable_mask, status_mask))
 597                 return;
 598
 599         if ((pipestat & enable_mask) == enable_mask)
 600                 return;
 601
 602         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 603
 604         /* Enable the interrupt, clear any pending status */
 605         pipestat |= enable_mask | status_mask;
 606         I915_WRITE(reg, pipestat);
 607         POSTING_READ(reg);
 608 }
 609
 610 static void
 611 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 612                         u32 enable_mask, u32 status_mask)
 613 {
 614         u32 reg = PIPESTAT(pipe);
 615         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 616
 617         assert_spin_locked(&dev_priv->irq_lock);
 618
 619         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 620                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 621                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 622                       pipe_name(pipe), enable_mask, status_mask))
 623                 return;
 624
 625         if ((pipestat & enable_mask) == 0)
 626                 return;
 627
 628         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 629
 630         pipestat &= ~enable_mask;
 631         I915_WRITE(reg, pipestat);
 632         POSTING_READ(reg);
 633 }
 634
 635 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 636 {
 637         u32 enable_mask = status_mask << 16;
 638
 639         /*
 640          * On pipe A we don't support the PSR interrupt yet,
 641          * on pipe B and C the same bit MBZ.
 642          */
 643         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 644                 return 0;
 645         /*
 646          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 647          * A the same bit is for perf counters which we don't use either.
 648          */
 649         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 650                 return 0;
 651
 652         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 653                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 654                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 655         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 656                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 657         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 658                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 659
 660         return enable_mask;
 661 }
 662
 663 void
 664 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 665                      u32 status_mask)
 666 {
 667         u32 enable_mask;
 668
 669         if (IS_VALLEYVIEW(dev_priv->dev))
 670                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 671                                                            status_mask);
 672         else
 673                 enable_mask = status_mask << 16;
 674         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 675 }
 676
 677 void
 678 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 679                       u32 status_mask)
 680 {
 681         u32 enable_mask;
 682
 683         if (IS_VALLEYVIEW(dev_priv->dev))
 684                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 685                                                            status_mask);
 686         else
 687                 enable_mask = status_mask << 16;
 688         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 689 }
 690
 691 /**
 692  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 693  */
 694 static void i915_enable_asle_pipestat(struct drm_device *dev)
 695 {
 696         struct drm_i915_private *dev_priv = dev->dev_private;
 697         unsigned long irqflags;
 698
 699         if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
 700                 return;
 701
 702         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 703
 704         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 705         if (INTEL_INFO(dev)->gen >= 4)
 706                 i915_enable_pipestat(dev_priv, PIPE_A,
 707                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 708
 709         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 710 }
 711
 712 /**
 713  * i915_pipe_enabled - check if a pipe is enabled
 714  * @dev: DRM device
 715  * @pipe: pipe to check
 716  *
 717  * Reading certain registers when the pipe is disabled can hang the chip.
 718  * Use this routine to make sure the PLL is running and the pipe is active
 719  * before reading such registers if unsure.
 720  */
 721 static int
 722 i915_pipe_enabled(struct drm_device *dev, int pipe)
 723 {
 724         struct drm_i915_private *dev_priv = dev->dev_private;
 725
 726         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 727                 /* Locking is horribly broken here, but whatever. */
 728                 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 729                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 730
 731                 return intel_crtc->active;
 732         } else {
 733                 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
 734         }
 735 }
 736
 737 /*
 738  * This timing diagram depicts the video signal in and
 739  * around the vertical blanking period.
 740  *
 741  * Assumptions about the fictitious mode used in this example:
 742  *  vblank_start >= 3
 743  *  vsync_start = vblank_start + 1
 744  *  vsync_end = vblank_start + 2
 745  *  vtotal = vblank_start + 3
 746  *
 747  *           start of vblank:
 748  *           latch double buffered registers
 749  *           increment frame counter (ctg+)
 750  *           generate start of vblank interrupt (gen4+)
 751  *           |
 752  *           |          frame start:
 753  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 754  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 755  *           |          |
 756  *           |          |  start of vsync:
 757  *           |          |  generate vsync interrupt
 758  *           |          |  |
 759  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 760  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 761  * ----va---> <-----------------vb--------------------> <--------va-------------
 762  *       |          |       <----vs----->                     |
 763  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 764  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 765  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 766  *       |          |                                         |
 767  *       last visible pixel                                   first visible pixel
 768  *                  |                                         increment frame counter (gen3/4)
 769  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 770  *
 771  * x  = horizontal active
 772  * _  = horizontal blanking
 773  * hs = horizontal sync
 774  * va = vertical active
 775  * vb = vertical blanking
 776  * vs = vertical sync
 777  * vbs = vblank_start (number)
 778  *
 779  * Summary:
 780  * - most events happen at the start of horizontal sync
 781  * - frame start happens at the start of horizontal blank, 1-4 lines
 782  *   (depending on PIPECONF settings) after the start of vblank
 783  * - gen3/4 pixel and frame counter are synchronized with the start
 784  *   of horizontal active on the first line of vertical active
 785  */
 786
 787 static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
 788 {
 789         /* Gen2 doesn't have a hardware frame counter */
 790         return 0;
 791 }
 792
 793 /* Called from drm generic code, passed a 'crtc', which
 794  * we use as a pipe index
 795  */
 796 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 797 {
 798         struct drm_i915_private *dev_priv = dev->dev_private;
 799         unsigned long high_frame;
 800         unsigned long low_frame;
 801         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 802
 803         if (!i915_pipe_enabled(dev, pipe)) {
 804                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 805                                 "pipe %c\n", pipe_name(pipe));
 806                 return 0;
 807         }
 808
 809         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 810                 struct intel_crtc *intel_crtc =
 811                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 812                 const struct drm_display_mode *mode =
 813                         &intel_crtc->config.adjusted_mode;
 814
 815                 htotal = mode->crtc_htotal;
 816                 hsync_start = mode->crtc_hsync_start;
 817                 vbl_start = mode->crtc_vblank_start;
 818                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 819                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 820         } else {
 821                 enum transcoder cpu_transcoder = (enum transcoder) pipe;
 822
 823                 htotal = ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff) + 1;
 824                 hsync_start = (I915_READ(HSYNC(cpu_transcoder))  & 0x1fff) + 1;
 825                 vbl_start = (I915_READ(VBLANK(cpu_transcoder)) & 0x1fff) + 1;
 826                 if ((I915_READ(PIPECONF(cpu_transcoder)) &
 827                      PIPECONF_INTERLACE_MASK) != PIPECONF_PROGRESSIVE)
 828                         vbl_start = DIV_ROUND_UP(vbl_start, 2);
 829         }
 830
 831         /* Convert to pixel count */
 832         vbl_start *= htotal;
 833
 834         /* Start of vblank event occurs at start of hsync */
 835         vbl_start -= htotal - hsync_start;
 836
 837         high_frame = PIPEFRAME(pipe);
 838         low_frame = PIPEFRAMEPIXEL(pipe);
 839
 840         /*
 841          * High & low register fields aren't synchronized, so make sure
 842          * we get a low value that's stable across two reads of the high
 843          * register.
 844          */
 845         do {
 846                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 847                 low   = I915_READ(low_frame);
 848                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 849         } while (high1 != high2);
 850
 851         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 852         pixel = low & PIPE_PIXEL_MASK;
 853         low >>= PIPE_FRAME_LOW_SHIFT;
 854
 855         /*
 856          * The frame counter increments at beginning of active.
 857          * Cook up a vblank counter by also checking the pixel
 858          * counter against vblank start.
 859          */
 860         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 861 }
 862
 863 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 864 {
 865         struct drm_i915_private *dev_priv = dev->dev_private;
 866         int reg = PIPE_FRMCOUNT_GM45(pipe);
 867
 868         if (!i915_pipe_enabled(dev, pipe)) {
 869                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 870                                  "pipe %c\n", pipe_name(pipe));
 871                 return 0;
 872         }
 873
 874         return I915_READ(reg);
 875 }
 876
 877 /* raw reads, only for fast reads of display block, no need for forcewake etc. */
 878 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
 879
 880 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 881 {
 882         struct drm_device *dev = crtc->base.dev;
 883         struct drm_i915_private *dev_priv = dev->dev_private;
 884         const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
 885         enum pipe pipe = crtc->pipe;
 886         int position, vtotal;
 887
 888         vtotal = mode->crtc_vtotal;
 889         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 890                 vtotal /= 2;
 891
 892         if (IS_GEN2(dev))
 893                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 894         else
 895                 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 896
 897         /*
 898          * See update_scanline_offset() for the details on the
 899          * scanline_offset adjustment.
 900          */
 901         return (position + crtc->scanline_offset) % vtotal;
 902 }
 903
 904 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 905                                     unsigned int flags, int *vpos, int *hpos,
 906                                     ktime_t *stime, ktime_t *etime)
 907 {
 908         struct drm_i915_private *dev_priv = dev->dev_private;
 909         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 910         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 911         const struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
 912         int position;
 913         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 914         bool in_vbl = true;
 915         int ret = 0;
 916         unsigned long irqflags;
 917
 918         if (!intel_crtc->active) {
 919                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 920                                  "pipe %c\n", pipe_name(pipe));
 921                 return 0;
 922         }
 923
 924         htotal = mode->crtc_htotal;
 925         hsync_start = mode->crtc_hsync_start;
 926         vtotal = mode->crtc_vtotal;
 927         vbl_start = mode->crtc_vblank_start;
 928         vbl_end = mode->crtc_vblank_end;
 929
 930         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 931                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 932                 vbl_end /= 2;
 933                 vtotal /= 2;
 934         }
 935
 936         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 937
 938         /*
 939          * Lock uncore.lock, as we will do multiple timing critical raw
 940          * register reads, potentially with preemption disabled, so the
 941          * following code must not block on uncore.lock.
 942          */
 943         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 944
 945         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 946
 947         /* Get optional system timestamp before query. */
 948         if (stime)
 949                 *stime = ktime_get();
 950
 951         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
 952                 /* No obvious pixelcount register. Only query vertical
 953                  * scanout position from Display scan line register.
 954                  */
 955                 position = __intel_get_crtc_scanline(intel_crtc);
 956         } else {
 957                 /* Have access to pixelcount since start of frame.
 958                  * We can split this into vertical and horizontal
 959                  * scanout position.
 960                  */
 961                 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 962
 963                 /* convert to pixel counts */
 964                 vbl_start *= htotal;
 965                 vbl_end *= htotal;
 966                 vtotal *= htotal;
 967
 968                 /*
 969                  * In interlaced modes, the pixel counter counts all pixels,
 970                  * so one field will have htotal more pixels. In order to avoid
 971                  * the reported position from jumping backwards when the pixel
 972                  * counter is beyond the length of the shorter field, just
 973                  * clamp the position the length of the shorter field. This
 974                  * matches how the scanline counter based position works since
 975                  * the scanline counter doesn't count the two half lines.
 976                  */
 977                 if (position >= vtotal)
 978                         position = vtotal - 1;
 979
 980                 /*
 981                  * Start of vblank interrupt is triggered at start of hsync,
 982                  * just prior to the first active line of vblank. However we
 983                  * consider lines to start at the leading edge of horizontal
 984                  * active. So, should we get here before we've crossed into
 985                  * the horizontal active of the first line in vblank, we would
 986                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 987                  * always add htotal-hsync_start to the current pixel position.
 988                  */
 989                 position = (position + htotal - hsync_start) % vtotal;
 990         }
 991
 992         /* Get optional system timestamp after query. */
 993         if (etime)
 994                 *etime = ktime_get();
 995
 996         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 997
 998         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 999
1000         in_vbl = position >= vbl_start && position < vbl_end;
1001
1002         /*
1003          * While in vblank, position will be negative
1004          * counting up towards 0 at vbl_end. And outside
1005          * vblank, position will be positive counting
1006          * up since vbl_end.
1007          */
1008         if (position >= vbl_start)
1009                 position -= vbl_end;
1010         else
1011                 position += vtotal - vbl_end;
1012
1013         if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
1014                 *vpos = position;
1015                 *hpos = 0;
1016         } else {
1017                 *vpos = position / htotal;
1018                 *hpos = position - (*vpos * htotal);
1019         }
1020
1021         /* In vblank? */
1022         if (in_vbl)
1023                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
1024
1025         return ret;
1026 }
1027
1028 int intel_get_crtc_scanline(struct intel_crtc *crtc)
1029 {
1030         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1031         unsigned long irqflags;
1032         int position;
1033
1034         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1035         position = __intel_get_crtc_scanline(crtc);
1036         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1037
1038         return position;
1039 }
1040
1041 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
1042                               int *max_error,
1043                               struct timeval *vblank_time,
1044                               unsigned flags)
1045 {
1046         struct drm_crtc *crtc;
1047
1048         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
1049                 DRM_ERROR("Invalid crtc %d\n", pipe);
1050                 return -EINVAL;
1051         }
1052
1053         /* Get drm_crtc to timestamp: */
1054         crtc = intel_get_crtc_for_pipe(dev, pipe);
1055         if (crtc == NULL) {
1056                 DRM_ERROR("Invalid crtc %d\n", pipe);
1057                 return -EINVAL;
1058         }
1059
1060         if (!crtc->enabled) {
1061                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1062                 return -EBUSY;
1063         }
1064
1065         /* Helper routine in DRM core does all the work: */
1066         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
1067                                                      vblank_time, flags,
1068                                                      crtc,
1069                                                      &to_intel_crtc(crtc)->config.adjusted_mode);
1070 }
1071
1072 static bool intel_hpd_irq_event(struct drm_device *dev,
1073                                 struct drm_connector *connector)
1074 {
1075         enum drm_connector_status old_status;
1076
1077         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1078         old_status = connector->status;
1079
1080         connector->status = connector->funcs->detect(connector, false);
1081         if (old_status == connector->status)
1082                 return false;
1083
1084         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
1085                       connector->base.id,
1086                       connector->name,
1087                       drm_get_connector_status_name(old_status),
1088                       drm_get_connector_status_name(connector->status));
1089
1090         return true;
1091 }
1092
1093 static void i915_digport_work_func(struct work_struct *work)
1094 {
1095         struct drm_i915_private *dev_priv =
1096                 container_of(work, struct drm_i915_private, dig_port_work);
1097         unsigned long irqflags;
1098         u32 long_port_mask, short_port_mask;
1099         struct intel_digital_port *intel_dig_port;
1100         int i, ret;
1101         u32 old_bits = 0;
1102
1103         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1104         long_port_mask = dev_priv->long_hpd_port_mask;
1105         dev_priv->long_hpd_port_mask = 0;
1106         short_port_mask = dev_priv->short_hpd_port_mask;
1107         dev_priv->short_hpd_port_mask = 0;
1108         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1109
1110         for (i = 0; i < I915_MAX_PORTS; i++) {
1111                 bool valid = false;
1112                 bool long_hpd = false;
1113                 intel_dig_port = dev_priv->hpd_irq_port[i];
1114                 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
1115                         continue;
1116
1117                 if (long_port_mask & (1 << i))  {
1118                         valid = true;
1119                         long_hpd = true;
1120                 } else if (short_port_mask & (1 << i))
1121                         valid = true;
1122
1123                 if (valid) {
1124                         ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
1125                         if (ret == true) {
1126                                 /* if we get true fallback to old school hpd */
1127                                 old_bits |= (1 << intel_dig_port->base.hpd_pin);
1128                         }
1129                 }
1130         }
1131
1132         if (old_bits) {
1133                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1134                 dev_priv->hpd_event_bits |= old_bits;
1135                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1136                 schedule_work(&dev_priv->hotplug_work);
1137         }
1138 }
1139
1140 /*
1141  * Handle hotplug events outside the interrupt handler proper.
1142  */
1143 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
1144
1145 static void i915_hotplug_work_func(struct work_struct *work)
1146 {
1147         struct drm_i915_private *dev_priv =
1148                 container_of(work, struct drm_i915_private, hotplug_work);
1149         struct drm_device *dev = dev_priv->dev;
1150         struct drm_mode_config *mode_config = &dev->mode_config;
1151         struct intel_connector *intel_connector;
1152         struct intel_encoder *intel_encoder;
1153         struct drm_connector *connector;
1154         unsigned long irqflags;
1155         bool hpd_disabled = false;
1156         bool changed = false;
1157         u32 hpd_event_bits;
1158
1159         mutex_lock(&mode_config->mutex);
1160         DRM_DEBUG_KMS("running encoder hotplug functions\n");
1161
1162         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1163
1164         hpd_event_bits = dev_priv->hpd_event_bits;
1165         dev_priv->hpd_event_bits = 0;
1166         list_for_each_entry(connector, &mode_config->connector_list, head) {
1167                 intel_connector = to_intel_connector(connector);
1168                 if (!intel_connector->encoder)
1169                         continue;
1170                 intel_encoder = intel_connector->encoder;
1171                 if (intel_encoder->hpd_pin > HPD_NONE &&
1172                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
1173                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
1174                         DRM_INFO("HPD interrupt storm detected on connector %s: "
1175                                  "switching from hotplug detection to polling\n",
1176                                 connector->name);
1177                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
1178                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
1179                                 | DRM_CONNECTOR_POLL_DISCONNECT;
1180                         hpd_disabled = true;
1181                 }
1182                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1183                         DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
1184                                       connector->name, intel_encoder->hpd_pin);
1185                 }
1186         }
1187          /* if there were no outputs to poll, poll was disabled,
1188           * therefore make sure it's enabled when disabling HPD on
1189           * some connectors */
1190         if (hpd_disabled) {
1191                 drm_kms_helper_poll_enable(dev);
1192                 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
1193                                  msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
1194         }
1195
1196         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1197
1198         list_for_each_entry(connector, &mode_config->connector_list, head) {
1199                 intel_connector = to_intel_connector(connector);
1200                 if (!intel_connector->encoder)
1201                         continue;
1202                 intel_encoder = intel_connector->encoder;
1203                 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
1204                         if (intel_encoder->hot_plug)
1205                                 intel_encoder->hot_plug(intel_encoder);
1206                         if (intel_hpd_irq_event(dev, connector))
1207                                 changed = true;
1208                 }
1209         }
1210         mutex_unlock(&mode_config->mutex);
1211
1212         if (changed)
1213                 drm_kms_helper_hotplug_event(dev);
1214 }
1215
1216 static void ironlake_rps_change_irq_handler(struct drm_device *dev)
1217 {
1218         struct drm_i915_private *dev_priv = dev->dev_private;
1219         u32 busy_up, busy_down, max_avg, min_avg;
1220         u8 new_delay;
1221
1222         spin_lock(&mchdev_lock);
1223
1224         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
1225
1226         new_delay = dev_priv->ips.cur_delay;
1227
1228         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
1229         busy_up = I915_READ(RCPREVBSYTUPAVG);
1230         busy_down = I915_READ(RCPREVBSYTDNAVG);
1231         max_avg = I915_READ(RCBMAXAVG);
1232         min_avg = I915_READ(RCBMINAVG);
1233
1234         /* Handle RCS change request from hw */
1235         if (busy_up > max_avg) {
1236                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1237                         new_delay = dev_priv->ips.cur_delay - 1;
1238                 if (new_delay < dev_priv->ips.max_delay)
1239                         new_delay = dev_priv->ips.max_delay;
1240         } else if (busy_down < min_avg) {
1241                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1242                         new_delay = dev_priv->ips.cur_delay + 1;
1243                 if (new_delay > dev_priv->ips.min_delay)
1244                         new_delay = dev_priv->ips.min_delay;
1245         }
1246
1247         if (ironlake_set_drps(dev, new_delay))
1248                 dev_priv->ips.cur_delay = new_delay;
1249
1250         spin_unlock(&mchdev_lock);
1251
1252         return;
1253 }
1254
1255 static void notify_ring(struct drm_device *dev,
1256                         struct intel_engine_cs *ring)
1257 {
1258         if (!intel_ring_initialized(ring))
1259                 return;
1260
1261         trace_i915_gem_request_complete(ring);
1262
1263         if (drm_core_check_feature(dev, DRIVER_MODESET))
1264                 intel_notify_mmio_flip(ring);
1265
1266         wake_up_all(&ring->irq_queue);
1267         i915_queue_hangcheck(dev);
1268 }
1269
1270 static u32 vlv_c0_residency(struct drm_i915_private *dev_priv,
1271                             struct intel_rps_ei *rps_ei)
1272 {
1273         u32 cz_ts, cz_freq_khz;
1274         u32 render_count, media_count;
1275         u32 elapsed_render, elapsed_media, elapsed_time;
1276         u32 residency = 0;
1277
1278         cz_ts = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1279         cz_freq_khz = DIV_ROUND_CLOSEST(dev_priv->mem_freq * 1000, 4);
1280
1281         render_count = I915_READ(VLV_RENDER_C0_COUNT_REG);
1282         media_count = I915_READ(VLV_MEDIA_C0_COUNT_REG);
1283
1284         if (rps_ei->cz_clock == 0) {
1285                 rps_ei->cz_clock = cz_ts;
1286                 rps_ei->render_c0 = render_count;
1287                 rps_ei->media_c0 = media_count;
1288
1289                 return dev_priv->rps.cur_freq;
1290         }
1291
1292         elapsed_time = cz_ts - rps_ei->cz_clock;
1293         rps_ei->cz_clock = cz_ts;
1294
1295         elapsed_render = render_count - rps_ei->render_c0;
1296         rps_ei->render_c0 = render_count;
1297
1298         elapsed_media = media_count - rps_ei->media_c0;
1299         rps_ei->media_c0 = media_count;
1300
1301         /* Convert all the counters into common unit of milli sec */
1302         elapsed_time /= VLV_CZ_CLOCK_TO_MILLI_SEC;
1303         elapsed_render /=  cz_freq_khz;
1304         elapsed_media /= cz_freq_khz;
1305
1306         /*
1307          * Calculate overall C0 residency percentage
1308          * only if elapsed time is non zero
1309          */
1310         if (elapsed_time) {
1311                 residency =
1312                         ((max(elapsed_render, elapsed_media) * 100)
1313                                 / elapsed_time);
1314         }
1315
1316         return residency;
1317 }
1318
1319 /**
1320  * vlv_calc_delay_from_C0_counters - Increase/Decrease freq based on GPU
1321  * busy-ness calculated from C0 counters of render & media power wells
1322  * @dev_priv: DRM device private
1323  *
1324  */
1325 static int vlv_calc_delay_from_C0_counters(struct drm_i915_private *dev_priv)
1326 {
1327         u32 residency_C0_up = 0, residency_C0_down = 0;
1328         int new_delay, adj;
1329
1330         dev_priv->rps.ei_interrupt_count++;
1331
1332         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
1333
1334
1335         if (dev_priv->rps.up_ei.cz_clock == 0) {
1336                 vlv_c0_residency(dev_priv, &dev_priv->rps.up_ei);
1337                 vlv_c0_residency(dev_priv, &dev_priv->rps.down_ei);
1338                 return dev_priv->rps.cur_freq;
1339         }
1340
1341
1342         /*
1343          * To down throttle, C0 residency should be less than down threshold
1344          * for continous EI intervals. So calculate down EI counters
1345          * once in VLV_INT_COUNT_FOR_DOWN_EI
1346          */
1347         if (dev_priv->rps.ei_interrupt_count == VLV_INT_COUNT_FOR_DOWN_EI) {
1348
1349                 dev_priv->rps.ei_interrupt_count = 0;
1350
1351                 residency_C0_down = vlv_c0_residency(dev_priv,
1352                                                      &dev_priv->rps.down_ei);
1353         } else {
1354                 residency_C0_up = vlv_c0_residency(dev_priv,
1355                                                    &dev_priv->rps.up_ei);
1356         }
1357
1358         new_delay = dev_priv->rps.cur_freq;
1359
1360         adj = dev_priv->rps.last_adj;
1361         /* C0 residency is greater than UP threshold. Increase Frequency */
1362         if (residency_C0_up >= VLV_RP_UP_EI_THRESHOLD) {
1363                 if (adj > 0)
1364                         adj *= 2;
1365                 else
1366                         adj = 1;
1367
1368                 if (dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit)
1369                         new_delay = dev_priv->rps.cur_freq + adj;
1370
1371                 /*
1372                  * For better performance, jump directly
1373                  * to RPe if we're below it.
1374                  */
1375                 if (new_delay < dev_priv->rps.efficient_freq)
1376                         new_delay = dev_priv->rps.efficient_freq;
1377
1378         } else if (!dev_priv->rps.ei_interrupt_count &&
1379                         (residency_C0_down < VLV_RP_DOWN_EI_THRESHOLD)) {
1380                 if (adj < 0)
1381                         adj *= 2;
1382                 else
1383                         adj = -1;
1384                 /*
1385                  * This means, C0 residency is less than down threshold over
1386                  * a period of VLV_INT_COUNT_FOR_DOWN_EI. So, reduce the freq
1387                  */
1388                 if (dev_priv->rps.cur_freq > dev_priv->rps.min_freq_softlimit)
1389                         new_delay = dev_priv->rps.cur_freq + adj;
1390         }
1391
1392         return new_delay;
1393 }
1394
1395 static void gen6_pm_rps_work(struct work_struct *work)
1396 {
1397         struct drm_i915_private *dev_priv =
1398                 container_of(work, struct drm_i915_private, rps.work);
1399         u32 pm_iir;
1400         int new_delay, adj;
1401
1402         spin_lock_irq(&dev_priv->irq_lock);
1403         pm_iir = dev_priv->rps.pm_iir;
1404         dev_priv->rps.pm_iir = 0;
1405         if (INTEL_INFO(dev_priv->dev)->gen >= 8)
1406                 gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1407         else {
1408                 /* Make sure not to corrupt PMIMR state used by ringbuffer */
1409                 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1410         }
1411         spin_unlock_irq(&dev_priv->irq_lock);
1412
1413         /* Make sure we didn't queue anything we're not going to process. */
1414         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1415
1416         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1417                 return;
1418
1419         mutex_lock(&dev_priv->rps.hw_lock);
1420
1421         adj = dev_priv->rps.last_adj;
1422         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1423                 if (adj > 0)
1424                         adj *= 2;
1425                 else {
1426                         /* CHV needs even encode values */
1427                         adj = IS_CHERRYVIEW(dev_priv->dev) ? 2 : 1;
1428                 }
1429                 new_delay = dev_priv->rps.cur_freq + adj;
1430
1431                 /*
1432                  * For better performance, jump directly
1433                  * to RPe if we're below it.
1434                  */
1435                 if (new_delay < dev_priv->rps.efficient_freq)
1436                         new_delay = dev_priv->rps.efficient_freq;
1437         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1438                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1439                         new_delay = dev_priv->rps.efficient_freq;
1440                 else
1441                         new_delay = dev_priv->rps.min_freq_softlimit;
1442                 adj = 0;
1443         } else if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1444                 new_delay = vlv_calc_delay_from_C0_counters(dev_priv);
1445         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1446                 if (adj < 0)
1447                         adj *= 2;
1448                 else {
1449                         /* CHV needs even encode values */
1450                         adj = IS_CHERRYVIEW(dev_priv->dev) ? -2 : -1;
1451                 }
1452                 new_delay = dev_priv->rps.cur_freq + adj;
1453         } else { /* unknown event */
1454                 new_delay = dev_priv->rps.cur_freq;
1455         }
1456
1457         /* sysfs frequency interfaces may have snuck in while servicing the
1458          * interrupt
1459          */
1460         new_delay = clamp_t(int, new_delay,
1461                             dev_priv->rps.min_freq_softlimit,
1462                             dev_priv->rps.max_freq_softlimit);
1463
1464         dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq;
1465
1466         if (IS_VALLEYVIEW(dev_priv->dev))
1467                 valleyview_set_rps(dev_priv->dev, new_delay);
1468         else
1469                 gen6_set_rps(dev_priv->dev, new_delay);
1470
1471         mutex_unlock(&dev_priv->rps.hw_lock);
1472 }
1473
1474
1475 /**
1476  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1477  * occurred.
1478  * @work: workqueue struct
1479  *
1480  * Doesn't actually do anything except notify userspace. As a consequence of
1481  * this event, userspace should try to remap the bad rows since statistically
1482  * it is likely the same row is more likely to go bad again.
1483  */
1484 static void ivybridge_parity_work(struct work_struct *work)
1485 {
1486         struct drm_i915_private *dev_priv =
1487                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1488         u32 error_status, row, bank, subbank;
1489         char *parity_event[6];
1490         uint32_t misccpctl;
1491         unsigned long flags;
1492         uint8_t slice = 0;
1493
1494         /* We must turn off DOP level clock gating to access the L3 registers.
1495          * In order to prevent a get/put style interface, acquire struct mutex
1496          * any time we access those registers.
1497          */
1498         mutex_lock(&dev_priv->dev->struct_mutex);
1499
1500         /* If we've screwed up tracking, just let the interrupt fire again */
1501         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1502                 goto out;
1503
1504         misccpctl = I915_READ(GEN7_MISCCPCTL);
1505         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1506         POSTING_READ(GEN7_MISCCPCTL);
1507
1508         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1509                 u32 reg;
1510
1511                 slice--;
1512                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1513                         break;
1514
1515                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1516
1517                 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1518
1519                 error_status = I915_READ(reg);
1520                 row = GEN7_PARITY_ERROR_ROW(error_status);
1521                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1522                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1523
1524                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1525                 POSTING_READ(reg);
1526
1527                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1528                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1529                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1530                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1531                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1532                 parity_event[5] = NULL;
1533
1534                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1535                                    KOBJ_CHANGE, parity_event);
1536
1537                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1538                           slice, row, bank, subbank);
1539
1540                 kfree(parity_event[4]);
1541                 kfree(parity_event[3]);
1542                 kfree(parity_event[2]);
1543                 kfree(parity_event[1]);
1544         }
1545
1546         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1547
1548 out:
1549         WARN_ON(dev_priv->l3_parity.which_slice);
1550         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1551         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
1552         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1553
1554         mutex_unlock(&dev_priv->dev->struct_mutex);
1555 }
1556
1557 static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
1558 {
1559         struct drm_i915_private *dev_priv = dev->dev_private;
1560
1561         if (!HAS_L3_DPF(dev))
1562                 return;
1563
1564         spin_lock(&dev_priv->irq_lock);
1565         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
1566         spin_unlock(&dev_priv->irq_lock);
1567
1568         iir &= GT_PARITY_ERROR(dev);
1569         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1570                 dev_priv->l3_parity.which_slice |= 1 << 1;
1571
1572         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1573                 dev_priv->l3_parity.which_slice |= 1 << 0;
1574
1575         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1576 }
1577
1578 static void ilk_gt_irq_handler(struct drm_device *dev,
1579                                struct drm_i915_private *dev_priv,
1580                                u32 gt_iir)
1581 {
1582         if (gt_iir &
1583             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1584                 notify_ring(dev, &dev_priv->ring[RCS]);
1585         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1586                 notify_ring(dev, &dev_priv->ring[VCS]);
1587 }
1588
1589 static void snb_gt_irq_handler(struct drm_device *dev,
1590                                struct drm_i915_private *dev_priv,
1591                                u32 gt_iir)
1592 {
1593
1594         if (gt_iir &
1595             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1596                 notify_ring(dev, &dev_priv->ring[RCS]);
1597         if (gt_iir & GT_BSD_USER_INTERRUPT)
1598                 notify_ring(dev, &dev_priv->ring[VCS]);
1599         if (gt_iir & GT_BLT_USER_INTERRUPT)
1600                 notify_ring(dev, &dev_priv->ring[BCS]);
1601
1602         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1603                       GT_BSD_CS_ERROR_INTERRUPT |
1604                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT)) {
1605                 i915_handle_error(dev, false, "GT error interrupt 0x%08x",
1606                                   gt_iir);
1607         }
1608
1609         if (gt_iir & GT_PARITY_ERROR(dev))
1610                 ivybridge_parity_error_irq_handler(dev, gt_iir);
1611 }
1612
1613 static void gen8_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1614 {
1615         if ((pm_iir & dev_priv->pm_rps_events) == 0)
1616                 return;
1617
1618         spin_lock(&dev_priv->irq_lock);
1619         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1620         gen8_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1621         spin_unlock(&dev_priv->irq_lock);
1622
1623         queue_work(dev_priv->wq, &dev_priv->rps.work);
1624 }
1625
1626 static irqreturn_t gen8_gt_irq_handler(struct drm_device *dev,
1627                                        struct drm_i915_private *dev_priv,
1628                                        u32 master_ctl)
1629 {
1630         struct intel_engine_cs *ring;
1631         u32 rcs, bcs, vcs;
1632         uint32_t tmp = 0;
1633         irqreturn_t ret = IRQ_NONE;
1634
1635         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1636                 tmp = I915_READ(GEN8_GT_IIR(0));
1637                 if (tmp) {
1638                         I915_WRITE(GEN8_GT_IIR(0), tmp);
1639                         ret = IRQ_HANDLED;
1640
1641                         rcs = tmp >> GEN8_RCS_IRQ_SHIFT;
1642                         ring = &dev_priv->ring[RCS];
1643                         if (rcs & GT_RENDER_USER_INTERRUPT)
1644                                 notify_ring(dev, ring);
1645                         if (rcs & GT_CONTEXT_SWITCH_INTERRUPT)
1646                                 intel_execlists_handle_ctx_events(ring);
1647
1648                         bcs = tmp >> GEN8_BCS_IRQ_SHIFT;
1649                         ring = &dev_priv->ring[BCS];
1650                         if (bcs & GT_RENDER_USER_INTERRUPT)
1651                                 notify_ring(dev, ring);
1652                         if (bcs & GT_CONTEXT_SWITCH_INTERRUPT)
1653                                 intel_execlists_handle_ctx_events(ring);
1654                 } else
1655                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1656         }
1657
1658         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1659                 tmp = I915_READ(GEN8_GT_IIR(1));
1660                 if (tmp) {
1661                         I915_WRITE(GEN8_GT_IIR(1), tmp);
1662                         ret = IRQ_HANDLED;
1663
1664                         vcs = tmp >> GEN8_VCS1_IRQ_SHIFT;
1665                         ring = &dev_priv->ring[VCS];
1666                         if (vcs & GT_RENDER_USER_INTERRUPT)
1667                                 notify_ring(dev, ring);
1668                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1669                                 intel_execlists_handle_ctx_events(ring);
1670
1671                         vcs = tmp >> GEN8_VCS2_IRQ_SHIFT;
1672                         ring = &dev_priv->ring[VCS2];
1673                         if (vcs & GT_RENDER_USER_INTERRUPT)
1674                                 notify_ring(dev, ring);
1675                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1676                                 intel_execlists_handle_ctx_events(ring);
1677                 } else
1678                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1679         }
1680
1681         if (master_ctl & GEN8_GT_PM_IRQ) {
1682                 tmp = I915_READ(GEN8_GT_IIR(2));
1683                 if (tmp & dev_priv->pm_rps_events) {
1684                         I915_WRITE(GEN8_GT_IIR(2),
1685                                    tmp & dev_priv->pm_rps_events);
1686                         ret = IRQ_HANDLED;
1687                         gen8_rps_irq_handler(dev_priv, tmp);
1688                 } else
1689                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1690         }
1691
1692         if (master_ctl & GEN8_GT_VECS_IRQ) {
1693                 tmp = I915_READ(GEN8_GT_IIR(3));
1694                 if (tmp) {
1695                         I915_WRITE(GEN8_GT_IIR(3), tmp);
1696                         ret = IRQ_HANDLED;
1697
1698                         vcs = tmp >> GEN8_VECS_IRQ_SHIFT;
1699                         ring = &dev_priv->ring[VECS];
1700                         if (vcs & GT_RENDER_USER_INTERRUPT)
1701                                 notify_ring(dev, ring);
1702                         if (vcs & GT_CONTEXT_SWITCH_INTERRUPT)
1703                                 intel_execlists_handle_ctx_events(ring);
1704                 } else
1705                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1706         }
1707
1708         return ret;
1709 }
1710
1711 #define HPD_STORM_DETECT_PERIOD 1000
1712 #define HPD_STORM_THRESHOLD 5
1713
1714 static int ilk_port_to_hotplug_shift(enum port port)
1715 {
1716         switch (port) {
1717         case PORT_A:
1718         case PORT_E:
1719         default:
1720                 return -1;
1721         case PORT_B:
1722                 return 0;
1723         case PORT_C:
1724                 return 8;
1725         case PORT_D:
1726                 return 16;
1727         }
1728 }
1729
1730 static int g4x_port_to_hotplug_shift(enum port port)
1731 {
1732         switch (port) {
1733         case PORT_A:
1734         case PORT_E:
1735         default:
1736                 return -1;
1737         case PORT_B:
1738                 return 17;
1739         case PORT_C:
1740                 return 19;
1741         case PORT_D:
1742                 return 21;
1743         }
1744 }
1745
1746 static inline enum port get_port_from_pin(enum hpd_pin pin)
1747 {
1748         switch (pin) {
1749         case HPD_PORT_B:
1750                 return PORT_B;
1751         case HPD_PORT_C:
1752                 return PORT_C;
1753         case HPD_PORT_D:
1754                 return PORT_D;
1755         default:
1756                 return PORT_A; /* no hpd */
1757         }
1758 }
1759
1760 static inline void intel_hpd_irq_handler(struct drm_device *dev,
1761                                          u32 hotplug_trigger,
1762                                          u32 dig_hotplug_reg,
1763                                          const u32 *hpd)
1764 {
1765         struct drm_i915_private *dev_priv = dev->dev_private;
1766         int i;
1767         enum port port;
1768         bool storm_detected = false;
1769         bool queue_dig = false, queue_hp = false;
1770         u32 dig_shift;
1771         u32 dig_port_mask = 0;
1772
1773         if (!hotplug_trigger)
1774                 return;
1775
1776         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1777                          hotplug_trigger, dig_hotplug_reg);
1778
1779         spin_lock(&dev_priv->irq_lock);
1780         for (i = 1; i < HPD_NUM_PINS; i++) {
1781                 if (!(hpd[i] & hotplug_trigger))
1782                         continue;
1783
1784                 port = get_port_from_pin(i);
1785                 if (port && dev_priv->hpd_irq_port[port]) {
1786                         bool long_hpd;
1787
1788                         if (IS_G4X(dev)) {
1789                                 dig_shift = g4x_port_to_hotplug_shift(port);
1790                                 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1791                         } else {
1792                                 dig_shift = ilk_port_to_hotplug_shift(port);
1793                                 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
1794                         }
1795
1796                         DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1797                                          port_name(port),
1798                                          long_hpd ? "long" : "short");
1799                         /* for long HPD pulses we want to have the digital queue happen,
1800                            but we still want HPD storm detection to function. */
1801                         if (long_hpd) {
1802                                 dev_priv->long_hpd_port_mask |= (1 << port);
1803                                 dig_port_mask |= hpd[i];
1804                         } else {
1805                                 /* for short HPD just trigger the digital queue */
1806                                 dev_priv->short_hpd_port_mask |= (1 << port);
1807                                 hotplug_trigger &= ~hpd[i];
1808                         }
1809                         queue_dig = true;
1810                 }
1811         }
1812
1813         for (i = 1; i < HPD_NUM_PINS; i++) {
1814                 if (hpd[i] & hotplug_trigger &&
1815                     dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1816                         /*
1817                          * On GMCH platforms the interrupt mask bits only
1818                          * prevent irq generation, not the setting of the
1819                          * hotplug bits itself. So only WARN about unexpected
1820                          * interrupts on saner platforms.
1821                          */
1822                         WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1823                                   "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1824                                   hotplug_trigger, i, hpd[i]);
1825
1826                         continue;
1827                 }
1828
1829                 if (!(hpd[i] & hotplug_trigger) ||
1830                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1831                         continue;
1832
1833                 if (!(dig_port_mask & hpd[i])) {
1834                         dev_priv->hpd_event_bits |= (1 << i);
1835                         queue_hp = true;
1836                 }
1837
1838                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1839                                    dev_priv->hpd_stats[i].hpd_last_jiffies
1840                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1841                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1842                         dev_priv->hpd_stats[i].hpd_cnt = 0;
1843                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
1844                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1845                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
1846                         dev_priv->hpd_event_bits &= ~(1 << i);
1847                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
1848                         storm_detected = true;
1849                 } else {
1850                         dev_priv->hpd_stats[i].hpd_cnt++;
1851                         DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1852                                       dev_priv->hpd_stats[i].hpd_cnt);
1853                 }
1854         }
1855
1856         if (storm_detected)
1857                 dev_priv->display.hpd_irq_setup(dev);
1858         spin_unlock(&dev_priv->irq_lock);
1859
1860         /*
1861          * Our hotplug handler can grab modeset locks (by calling down into the
1862          * fb helpers). Hence it must not be run on our own dev-priv->wq work
1863          * queue for otherwise the flush_work in the pageflip code will
1864          * deadlock.
1865          */
1866         if (queue_dig)
1867                 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
1868         if (queue_hp)
1869                 schedule_work(&dev_priv->hotplug_work);
1870 }
1871
1872 static void gmbus_irq_handler(struct drm_device *dev)
1873 {
1874         struct drm_i915_private *dev_priv = dev->dev_private;
1875
1876         wake_up_all(&dev_priv->gmbus_wait_queue);
1877 }
1878
1879 static void dp_aux_irq_handler(struct drm_device *dev)
1880 {
1881         struct drm_i915_private *dev_priv = dev->dev_private;
1882
1883         wake_up_all(&dev_priv->gmbus_wait_queue);
1884 }
1885
1886 #if defined(CONFIG_DEBUG_FS)
1887 static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1888                                          uint32_t crc0, uint32_t crc1,
1889                                          uint32_t crc2, uint32_t crc3,
1890                                          uint32_t crc4)
1891 {
1892         struct drm_i915_private *dev_priv = dev->dev_private;
1893         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1894         struct intel_pipe_crc_entry *entry;
1895         int head, tail;
1896
1897         spin_lock(&pipe_crc->lock);
1898
1899         if (!pipe_crc->entries) {
1900                 spin_unlock(&pipe_crc->lock);
1901                 DRM_ERROR("spurious interrupt\n");
1902                 return;
1903         }
1904
1905         head = pipe_crc->head;
1906         tail = pipe_crc->tail;
1907
1908         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1909                 spin_unlock(&pipe_crc->lock);
1910                 DRM_ERROR("CRC buffer overflowing\n");
1911                 return;
1912         }
1913
1914         entry = &pipe_crc->entries[head];
1915
1916         entry->frame = dev->driver->get_vblank_counter(dev, pipe);
1917         entry->crc[0] = crc0;
1918         entry->crc[1] = crc1;
1919         entry->crc[2] = crc2;
1920         entry->crc[3] = crc3;
1921         entry->crc[4] = crc4;
1922
1923         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1924         pipe_crc->head = head;
1925
1926         spin_unlock(&pipe_crc->lock);
1927
1928         wake_up_interruptible(&pipe_crc->wq);
1929 }
1930 #else
1931 static inline void
1932 display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1933                              uint32_t crc0, uint32_t crc1,
1934                              uint32_t crc2, uint32_t crc3,
1935                              uint32_t crc4) {}
1936 #endif
1937
1938
1939 static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1940 {
1941         struct drm_i915_private *dev_priv = dev->dev_private;
1942
1943         display_pipe_crc_irq_handler(dev, pipe,
1944                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1945                                      0, 0, 0, 0);
1946 }
1947
1948 static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1949 {
1950         struct drm_i915_private *dev_priv = dev->dev_private;
1951
1952         display_pipe_crc_irq_handler(dev, pipe,
1953                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1954                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1955                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1956                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1957                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1958 }
1959
1960 static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
1961 {
1962         struct drm_i915_private *dev_priv = dev->dev_private;
1963         uint32_t res1, res2;
1964
1965         if (INTEL_INFO(dev)->gen >= 3)
1966                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1967         else
1968                 res1 = 0;
1969
1970         if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1971                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1972         else
1973                 res2 = 0;
1974
1975         display_pipe_crc_irq_handler(dev, pipe,
1976                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1977                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1978                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1979                                      res1, res2);
1980 }
1981
1982 /* The RPS events need forcewake, so we add them to a work queue and mask their
1983  * IMR bits until the work is done. Other interrupts can be processed without
1984  * the work queue. */
1985 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1986 {
1987         if (pm_iir & dev_priv->pm_rps_events) {
1988                 spin_lock(&dev_priv->irq_lock);
1989                 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1990                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1991                 spin_unlock(&dev_priv->irq_lock);
1992
1993                 queue_work(dev_priv->wq, &dev_priv->rps.work);
1994         }
1995
1996         if (HAS_VEBOX(dev_priv->dev)) {
1997                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1998                         notify_ring(dev_priv->dev, &dev_priv->ring[VECS]);
1999
2000                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT) {
2001                         i915_handle_error(dev_priv->dev, false,
2002                                           "VEBOX CS error interrupt 0x%08x",
2003                                           pm_iir);
2004                 }
2005         }
2006 }
2007
2008 static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
2009 {
2010         if (!drm_handle_vblank(dev, pipe))
2011                 return false;
2012
2013         return true;
2014 }
2015
2016 static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
2017 {
2018         struct drm_i915_private *dev_priv = dev->dev_private;
2019         u32 pipe_stats[I915_MAX_PIPES] = { };
2020         int pipe;
2021
2022         spin_lock(&dev_priv->irq_lock);
2023         for_each_pipe(pipe) {
2024                 int reg;
2025                 u32 mask, iir_bit = 0;
2026
2027                 /*
2028                  * PIPESTAT bits get signalled even when the interrupt is
2029                  * disabled with the mask bits, and some of the status bits do
2030                  * not generate interrupts at all (like the underrun bit). Hence
2031                  * we need to be careful that we only handle what we want to
2032                  * handle.
2033                  */
2034                 mask = 0;
2035                 if (__cpu_fifo_underrun_reporting_enabled(dev, pipe))
2036                         mask |= PIPE_FIFO_UNDERRUN_STATUS;
2037
2038                 switch (pipe) {
2039                 case PIPE_A:
2040                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
2041                         break;
2042                 case PIPE_B:
2043                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
2044                         break;
2045                 case PIPE_C:
2046                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
2047                         break;
2048                 }
2049                 if (iir & iir_bit)
2050                         mask |= dev_priv->pipestat_irq_mask[pipe];
2051
2052                 if (!mask)
2053                         continue;
2054
2055                 reg = PIPESTAT(pipe);
2056                 mask |= PIPESTAT_INT_ENABLE_MASK;
2057                 pipe_stats[pipe] = I915_READ(reg) & mask;
2058
2059                 /*
2060                  * Clear the PIPE*STAT regs before the IIR
2061                  */
2062                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
2063                                         PIPESTAT_INT_STATUS_MASK))
2064                         I915_WRITE(reg, pipe_stats[pipe]);
2065         }
2066         spin_unlock(&dev_priv->irq_lock);
2067
2068         for_each_pipe(pipe) {
2069                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
2070                         intel_pipe_handle_vblank(dev, pipe);
2071
2072                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
2073                         intel_prepare_page_flip(dev, pipe);
2074                         intel_finish_page_flip(dev, pipe);
2075                 }
2076
2077                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
2078                         i9xx_pipe_crc_irq_handler(dev, pipe);
2079
2080                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
2081                     intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2082                         DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
2083         }
2084
2085         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2086                 gmbus_irq_handler(dev);
2087 }
2088
2089 static void i9xx_hpd_irq_handler(struct drm_device *dev)
2090 {
2091         struct drm_i915_private *dev_priv = dev->dev_private;
2092         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2093
2094         if (hotplug_status) {
2095                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2096                 /*
2097                  * Make sure hotplug status is cleared before we clear IIR, or else we
2098                  * may miss hotplug events.
2099                  */
2100                 POSTING_READ(PORT_HOTPLUG_STAT);
2101
2102                 if (IS_G4X(dev)) {
2103                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
2104
2105                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
2106                 } else {
2107                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2108
2109                         intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
2110                 }
2111
2112                 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
2113                     hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
2114                         dp_aux_irq_handler(dev);
2115         }
2116 }
2117
2118 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
2119 {
2120         struct drm_device *dev = arg;
2121         struct drm_i915_private *dev_priv = dev->dev_private;
2122         u32 iir, gt_iir, pm_iir;
2123         irqreturn_t ret = IRQ_NONE;
2124
2125         while (true) {
2126                 /* Find, clear, then process each source of interrupt */
2127
2128                 gt_iir = I915_READ(GTIIR);
2129                 if (gt_iir)
2130                         I915_WRITE(GTIIR, gt_iir);
2131
2132                 pm_iir = I915_READ(GEN6_PMIIR);
2133                 if (pm_iir)
2134                         I915_WRITE(GEN6_PMIIR, pm_iir);
2135
2136                 iir = I915_READ(VLV_IIR);
2137                 if (iir) {
2138                         /* Consume port before clearing IIR or we'll miss events */
2139                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
2140                                 i9xx_hpd_irq_handler(dev);
2141                         I915_WRITE(VLV_IIR, iir);
2142                 }
2143
2144                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
2145                         goto out;
2146
2147                 ret = IRQ_HANDLED;
2148
2149                 if (gt_iir)
2150                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2151                 if (pm_iir)
2152                         gen6_rps_irq_handler(dev_priv, pm_iir);
2153                 /* Call regardless, as some status bits might not be
2154                  * signalled in iir */
2155                 valleyview_pipestat_irq_handler(dev, iir);
2156         }
2157
2158 out:
2159         return ret;
2160 }
2161
2162 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2163 {
2164         struct drm_device *dev = arg;
2165         struct drm_i915_private *dev_priv = dev->dev_private;
2166         u32 master_ctl, iir;
2167         irqreturn_t ret = IRQ_NONE;
2168
2169         for (;;) {
2170                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2171                 iir = I915_READ(VLV_IIR);
2172
2173                 if (master_ctl == 0 && iir == 0)
2174                         break;
2175
2176                 ret = IRQ_HANDLED;
2177
2178                 I915_WRITE(GEN8_MASTER_IRQ, 0);
2179
2180                 /* Find, clear, then process each source of interrupt */
2181
2182                 if (iir) {
2183                         /* Consume port before clearing IIR or we'll miss events */
2184                         if (iir & I915_DISPLAY_PORT_INTERRUPT)
2185                                 i9xx_hpd_irq_handler(dev);
2186                         I915_WRITE(VLV_IIR, iir);
2187                 }
2188
2189                 gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2190
2191                 /* Call regardless, as some status bits might not be
2192                  * signalled in iir */
2193                 valleyview_pipestat_irq_handler(dev, iir);
2194
2195                 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
2196                 POSTING_READ(GEN8_MASTER_IRQ);
2197         }
2198
2199         return ret;
2200 }
2201
2202 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
2203 {
2204         struct drm_i915_private *dev_priv = dev->dev_private;
2205         int pipe;
2206         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2207         u32 dig_hotplug_reg;
2208
2209         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2210         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2211
2212         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
2213
2214         if (pch_iir & SDE_AUDIO_POWER_MASK) {
2215                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2216                                SDE_AUDIO_POWER_SHIFT);
2217                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2218                                  port_name(port));
2219         }
2220
2221         if (pch_iir & SDE_AUX_MASK)
2222                 dp_aux_irq_handler(dev);
2223
2224         if (pch_iir & SDE_GMBUS)
2225                 gmbus_irq_handler(dev);
2226
2227         if (pch_iir & SDE_AUDIO_HDCP_MASK)
2228                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2229
2230         if (pch_iir & SDE_AUDIO_TRANS_MASK)
2231                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2232
2233         if (pch_iir & SDE_POISON)
2234                 DRM_ERROR("PCH poison interrupt\n");
2235
2236         if (pch_iir & SDE_FDI_MASK)
2237                 for_each_pipe(pipe)
2238                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2239                                          pipe_name(pipe),
2240                                          I915_READ(FDI_RX_IIR(pipe)));
2241
2242         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2243                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2244
2245         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2246                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2247
2248         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2249                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2250                                                           false))
2251                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
2252
2253         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2254                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2255                                                           false))
2256                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
2257 }
2258
2259 static void ivb_err_int_handler(struct drm_device *dev)
2260 {
2261         struct drm_i915_private *dev_priv = dev->dev_private;
2262         u32 err_int = I915_READ(GEN7_ERR_INT);
2263         enum pipe pipe;
2264
2265         if (err_int & ERR_INT_POISON)
2266                 DRM_ERROR("Poison interrupt\n");
2267
2268         for_each_pipe(pipe) {
2269                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe)) {
2270                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2271                                                                   false))
2272                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2273                                           pipe_name(pipe));
2274                 }
2275
2276                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2277                         if (IS_IVYBRIDGE(dev))
2278                                 ivb_pipe_crc_irq_handler(dev, pipe);
2279                         else
2280                                 hsw_pipe_crc_irq_handler(dev, pipe);
2281                 }
2282         }
2283
2284         I915_WRITE(GEN7_ERR_INT, err_int);
2285 }
2286
2287 static void cpt_serr_int_handler(struct drm_device *dev)
2288 {
2289         struct drm_i915_private *dev_priv = dev->dev_private;
2290         u32 serr_int = I915_READ(SERR_INT);
2291
2292         if (serr_int & SERR_INT_POISON)
2293                 DRM_ERROR("PCH poison interrupt\n");
2294
2295         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2296                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A,
2297                                                           false))
2298                         DRM_ERROR("PCH transcoder A FIFO underrun\n");
2299
2300         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2301                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_B,
2302                                                           false))
2303                         DRM_ERROR("PCH transcoder B FIFO underrun\n");
2304
2305         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2306                 if (intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_C,
2307                                                           false))
2308                         DRM_ERROR("PCH transcoder C FIFO underrun\n");
2309
2310         I915_WRITE(SERR_INT, serr_int);
2311 }
2312
2313 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
2314 {
2315         struct drm_i915_private *dev_priv = dev->dev_private;
2316         int pipe;
2317         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2318         u32 dig_hotplug_reg;
2319
2320         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2321         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2322
2323         intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
2324
2325         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2326                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2327                                SDE_AUDIO_POWER_SHIFT_CPT);
2328                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2329                                  port_name(port));
2330         }
2331
2332         if (pch_iir & SDE_AUX_MASK_CPT)
2333                 dp_aux_irq_handler(dev);
2334
2335         if (pch_iir & SDE_GMBUS_CPT)
2336                 gmbus_irq_handler(dev);
2337
2338         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2339                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2340
2341         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2342                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2343
2344         if (pch_iir & SDE_FDI_MASK_CPT)
2345                 for_each_pipe(pipe)
2346                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2347                                          pipe_name(pipe),
2348                                          I915_READ(FDI_RX_IIR(pipe)));
2349
2350         if (pch_iir & SDE_ERROR_CPT)
2351                 cpt_serr_int_handler(dev);
2352 }
2353
2354 static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2355 {
2356         struct drm_i915_private *dev_priv = dev->dev_private;
2357         enum pipe pipe;
2358
2359         if (de_iir & DE_AUX_CHANNEL_A)
2360                 dp_aux_irq_handler(dev);
2361
2362         if (de_iir & DE_GSE)
2363                 intel_opregion_asle_intr(dev);
2364
2365         if (de_iir & DE_POISON)
2366                 DRM_ERROR("Poison interrupt\n");
2367
2368         for_each_pipe(pipe) {
2369                 if (de_iir & DE_PIPE_VBLANK(pipe))
2370                         intel_pipe_handle_vblank(dev, pipe);
2371
2372                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2373                         if (intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
2374                                 DRM_ERROR("Pipe %c FIFO underrun\n",
2375                                           pipe_name(pipe));
2376
2377                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2378                         i9xx_pipe_crc_irq_handler(dev, pipe);
2379
2380                 /* plane/pipes map 1:1 on ilk+ */
2381                 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2382                         intel_prepare_page_flip(dev, pipe);
2383                         intel_finish_page_flip_plane(dev, pipe);
2384                 }
2385         }
2386
2387         /* check event from PCH */
2388         if (de_iir & DE_PCH_EVENT) {
2389                 u32 pch_iir = I915_READ(SDEIIR);
2390
2391                 if (HAS_PCH_CPT(dev))
2392                         cpt_irq_handler(dev, pch_iir);
2393                 else
2394                         ibx_irq_handler(dev, pch_iir);
2395
2396                 /* should clear PCH hotplug event before clear CPU irq */
2397                 I915_WRITE(SDEIIR, pch_iir);
2398         }
2399
2400         if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2401                 ironlake_rps_change_irq_handler(dev);
2402 }
2403
2404 static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2405 {
2406         struct drm_i915_private *dev_priv = dev->dev_private;
2407         enum pipe pipe;
2408
2409         if (de_iir & DE_ERR_INT_IVB)
2410                 ivb_err_int_handler(dev);
2411
2412         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2413                 dp_aux_irq_handler(dev);
2414
2415         if (de_iir & DE_GSE_IVB)
2416                 intel_opregion_asle_intr(dev);
2417
2418         for_each_pipe(pipe) {
2419                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2420                         intel_pipe_handle_vblank(dev, pipe);
2421
2422                 /* plane/pipes map 1:1 on ilk+ */
2423                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2424                         intel_prepare_page_flip(dev, pipe);
2425                         intel_finish_page_flip_plane(dev, pipe);
2426                 }
2427         }
2428
2429         /* check event from PCH */
2430         if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2431                 u32 pch_iir = I915_READ(SDEIIR);
2432
2433                 cpt_irq_handler(dev, pch_iir);
2434
2435                 /* clear PCH hotplug event before clear CPU irq */
2436                 I915_WRITE(SDEIIR, pch_iir);
2437         }
2438 }
2439
2440 /*
2441  * To handle irqs with the minimum potential races with fresh interrupts, we:
2442  * 1 - Disable Master Interrupt Control.
2443  * 2 - Find the source(s) of the interrupt.
2444  * 3 - Clear the Interrupt Identity bits (IIR).
2445  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2446  * 5 - Re-enable Master Interrupt Control.
2447  */
2448 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2449 {
2450         struct drm_device *dev = arg;
2451         struct drm_i915_private *dev_priv = dev->dev_private;
2452         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2453         irqreturn_t ret = IRQ_NONE;
2454
2455         /* We get interrupts on unclaimed registers, so check for this before we
2456          * do any I915_{READ,WRITE}. */
2457         intel_uncore_check_errors(dev);
2458
2459         /* disable master interrupt before clearing iir  */
2460         de_ier = I915_READ(DEIER);
2461         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2462         POSTING_READ(DEIER);
2463
2464         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2465          * interrupts will will be stored on its back queue, and then we'll be
2466          * able to process them after we restore SDEIER (as soon as we restore
2467          * it, we'll get an interrupt if SDEIIR still has something to process
2468          * due to its back queue). */
2469         if (!HAS_PCH_NOP(dev)) {
2470                 sde_ier = I915_READ(SDEIER);
2471                 I915_WRITE(SDEIER, 0);
2472                 POSTING_READ(SDEIER);
2473         }
2474
2475         /* Find, clear, then process each source of interrupt */
2476
2477         gt_iir = I915_READ(GTIIR);
2478         if (gt_iir) {
2479                 I915_WRITE(GTIIR, gt_iir);
2480                 ret = IRQ_HANDLED;
2481                 if (INTEL_INFO(dev)->gen >= 6)
2482                         snb_gt_irq_handler(dev, dev_priv, gt_iir);
2483                 else
2484                         ilk_gt_irq_handler(dev, dev_priv, gt_iir);
2485         }
2486
2487         de_iir = I915_READ(DEIIR);
2488         if (de_iir) {
2489                 I915_WRITE(DEIIR, de_iir);
2490                 ret = IRQ_HANDLED;
2491                 if (INTEL_INFO(dev)->gen >= 7)
2492                         ivb_display_irq_handler(dev, de_iir);
2493                 else
2494                         ilk_display_irq_handler(dev, de_iir);
2495         }
2496
2497         if (INTEL_INFO(dev)->gen >= 6) {
2498                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2499                 if (pm_iir) {
2500                         I915_WRITE(GEN6_PMIIR, pm_iir);
2501                         ret = IRQ_HANDLED;
2502                         gen6_rps_irq_handler(dev_priv, pm_iir);
2503                 }
2504         }
2505
2506         I915_WRITE(DEIER, de_ier);
2507         POSTING_READ(DEIER);
2508         if (!HAS_PCH_NOP(dev)) {
2509                 I915_WRITE(SDEIER, sde_ier);
2510                 POSTING_READ(SDEIER);
2511         }
2512
2513         return ret;
2514 }
2515
2516 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2517 {
2518         struct drm_device *dev = arg;
2519         struct drm_i915_private *dev_priv = dev->dev_private;
2520         u32 master_ctl;
2521         irqreturn_t ret = IRQ_NONE;
2522         uint32_t tmp = 0;
2523         enum pipe pipe;
2524
2525         master_ctl = I915_READ(GEN8_MASTER_IRQ);
2526         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2527         if (!master_ctl)
2528                 return IRQ_NONE;
2529
2530         I915_WRITE(GEN8_MASTER_IRQ, 0);
2531         POSTING_READ(GEN8_MASTER_IRQ);
2532
2533         /* Find, clear, then process each source of interrupt */
2534
2535         ret = gen8_gt_irq_handler(dev, dev_priv, master_ctl);
2536
2537         if (master_ctl & GEN8_DE_MISC_IRQ) {
2538                 tmp = I915_READ(GEN8_DE_MISC_IIR);
2539                 if (tmp) {
2540                         I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2541                         ret = IRQ_HANDLED;
2542                         if (tmp & GEN8_DE_MISC_GSE)
2543                                 intel_opregion_asle_intr(dev);
2544                         else
2545                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2546                 }
2547                 else
2548                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2549         }
2550
2551         if (master_ctl & GEN8_DE_PORT_IRQ) {
2552                 tmp = I915_READ(GEN8_DE_PORT_IIR);
2553                 if (tmp) {
2554                         I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2555                         ret = IRQ_HANDLED;
2556                         if (tmp & GEN8_AUX_CHANNEL_A)
2557                                 dp_aux_irq_handler(dev);
2558                         else
2559                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2560                 }
2561                 else
2562                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2563         }
2564
2565         for_each_pipe(pipe) {
2566                 uint32_t pipe_iir;
2567
2568                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2569                         continue;
2570
2571                 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2572                 if (pipe_iir) {
2573                         ret = IRQ_HANDLED;
2574                         I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
2575                         if (pipe_iir & GEN8_PIPE_VBLANK)
2576                                 intel_pipe_handle_vblank(dev, pipe);
2577
2578                         if (pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE) {
2579                                 intel_prepare_page_flip(dev, pipe);
2580                                 intel_finish_page_flip_plane(dev, pipe);
2581                         }
2582
2583                         if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2584                                 hsw_pipe_crc_irq_handler(dev, pipe);
2585
2586                         if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN) {
2587                                 if (intel_set_cpu_fifo_underrun_reporting(dev, pipe,
2588                                                                           false))
2589                                         DRM_ERROR("Pipe %c FIFO underrun\n",
2590                                                   pipe_name(pipe));
2591                         }
2592
2593                         if (pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS) {
2594                                 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2595                                           pipe_name(pipe),
2596                                           pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
2597                         }
2598                 } else
2599                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2600         }
2601
2602         if (!HAS_PCH_NOP(dev) && master_ctl & GEN8_DE_PCH_IRQ) {
2603                 /*
2604                  * FIXME(BDW): Assume for now that the new interrupt handling
2605                  * scheme also closed the SDE interrupt handling race we've seen
2606                  * on older pch-split platforms. But this needs testing.
2607                  */
2608                 u32 pch_iir = I915_READ(SDEIIR);
2609                 if (pch_iir) {
2610                         I915_WRITE(SDEIIR, pch_iir);
2611                         ret = IRQ_HANDLED;
2612                         cpt_irq_handler(dev, pch_iir);
2613                 } else
2614                         DRM_ERROR("The master control interrupt lied (SDE)!\n");
2615
2616         }
2617
2618         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2619         POSTING_READ(GEN8_MASTER_IRQ);
2620
2621         return ret;
2622 }
2623
2624 static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2625                                bool reset_completed)
2626 {
2627         struct intel_engine_cs *ring;
2628         int i;
2629
2630         /*
2631          * Notify all waiters for GPU completion events that reset state has
2632          * been changed, and that they need to restart their wait after
2633          * checking for potential errors (and bail out to drop locks if there is
2634          * a gpu reset pending so that i915_error_work_func can acquire them).
2635          */
2636
2637         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2638         for_each_ring(ring, dev_priv, i)
2639                 wake_up_all(&ring->irq_queue);
2640
2641         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2642         wake_up_all(&dev_priv->pending_flip_queue);
2643
2644         /*
2645          * Signal tasks blocked in i915_gem_wait_for_error that the pending
2646          * reset state is cleared.
2647          */
2648         if (reset_completed)
2649                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2650 }
2651
2652 /**
2653  * i915_error_work_func - do process context error handling work
2654  * @work: work struct
2655  *
2656  * Fire an error uevent so userspace can see that a hang or error
2657  * was detected.
2658  */
2659 static void i915_error_work_func(struct work_struct *work)
2660 {
2661         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
2662                                                     work);
2663         struct drm_i915_private *dev_priv =
2664                 container_of(error, struct drm_i915_private, gpu_error);
2665         struct drm_device *dev = dev_priv->dev;
2666         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2667         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2668         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2669         int ret;
2670
2671         kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
2672
2673         /*
2674          * Note that there's only one work item which does gpu resets, so we
2675          * need not worry about concurrent gpu resets potentially incrementing
2676          * error->reset_counter twice. We only need to take care of another
2677          * racing irq/hangcheck declaring the gpu dead for a second time. A
2678          * quick check for that is good enough: schedule_work ensures the
2679          * correct ordering between hang detection and this work item, and since
2680          * the reset in-progress bit is only ever set by code outside of this
2681          * work we don't need to worry about any other races.
2682          */
2683         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
2684                 DRM_DEBUG_DRIVER("resetting chip\n");
2685                 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
2686                                    reset_event);
2687
2688                 /*
2689                  * In most cases it's guaranteed that we get here with an RPM
2690                  * reference held, for example because there is a pending GPU
2691                  * request that won't finish until the reset is done. This
2692                  * isn't the case at least when we get here by doing a
2693                  * simulated reset via debugs, so get an RPM reference.
2694                  */
2695                 intel_runtime_pm_get(dev_priv);
2696                 /*
2697                  * All state reset _must_ be completed before we update the
2698                  * reset counter, for otherwise waiters might miss the reset
2699                  * pending state and not properly drop locks, resulting in
2700                  * deadlocks with the reset work.
2701                  */
2702                 ret = i915_reset(dev);
2703
2704                 intel_display_handle_reset(dev);
2705
2706                 intel_runtime_pm_put(dev_priv);
2707
2708                 if (ret == 0) {
2709                         /*
2710                          * After all the gem state is reset, increment the reset
2711                          * counter and wake up everyone waiting for the reset to
2712                          * complete.
2713                          *
2714                          * Since unlock operations are a one-sided barrier only,
2715                          * we need to insert a barrier here to order any seqno
2716                          * updates before
2717                          * the counter increment.
2718                          */
2719                         smp_mb__before_atomic();
2720                         atomic_inc(&dev_priv->gpu_error.reset_counter);
2721
2722                         kobject_uevent_env(&dev->primary->kdev->kobj,
2723                                            KOBJ_CHANGE, reset_done_event);
2724                 } else {
2725                         atomic_set_mask(I915_WEDGED, &error->reset_counter);
2726                 }
2727
2728                 /*
2729                  * Note: The wake_up also serves as a memory barrier so that
2730                  * waiters see the update value of the reset counter atomic_t.
2731                  */
2732                 i915_error_wake_up(dev_priv, true);
2733         }
2734 }
2735
2736 static void i915_report_and_clear_eir(struct drm_device *dev)
2737 {
2738         struct drm_i915_private *dev_priv = dev->dev_private;
2739         uint32_t instdone[I915_NUM_INSTDONE_REG];
2740         u32 eir = I915_READ(EIR);
2741         int pipe, i;
2742
2743         if (!eir)
2744                 return;
2745
2746         pr_err("render error detected, EIR: 0x%08x\n", eir);
2747
2748         i915_get_extra_instdone(dev, instdone);
2749
2750         if (IS_G4X(dev)) {
2751                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2752                         u32 ipeir = I915_READ(IPEIR_I965);
2753
2754                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2755                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2756                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2757                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2758                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2759                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2760                         I915_WRITE(IPEIR_I965, ipeir);
2761                         POSTING_READ(IPEIR_I965);
2762                 }
2763                 if (eir & GM45_ERROR_PAGE_TABLE) {
2764                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2765                         pr_err("page table error\n");
2766                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2767                         I915_WRITE(PGTBL_ER, pgtbl_err);
2768                         POSTING_READ(PGTBL_ER);
2769                 }
2770         }
2771
2772         if (!IS_GEN2(dev)) {
2773                 if (eir & I915_ERROR_PAGE_TABLE) {
2774                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2775                         pr_err("page table error\n");
2776                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2777                         I915_WRITE(PGTBL_ER, pgtbl_err);
2778                         POSTING_READ(PGTBL_ER);
2779                 }
2780         }
2781
2782         if (eir & I915_ERROR_MEMORY_REFRESH) {
2783                 pr_err("memory refresh error:\n");
2784                 for_each_pipe(pipe)
2785                         pr_err("pipe %c stat: 0x%08x\n",
2786                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2787                 /* pipestat has already been acked */
2788         }
2789         if (eir & I915_ERROR_INSTRUCTION) {
2790                 pr_err("instruction error\n");
2791                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2792                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2793                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2794                 if (INTEL_INFO(dev)->gen < 4) {
2795                         u32 ipeir = I915_READ(IPEIR);
2796
2797                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2798                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2799                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2800                         I915_WRITE(IPEIR, ipeir);
2801                         POSTING_READ(IPEIR);
2802                 } else {
2803                         u32 ipeir = I915_READ(IPEIR_I965);
2804
2805                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2806                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2807                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2808                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2809                         I915_WRITE(IPEIR_I965, ipeir);
2810                         POSTING_READ(IPEIR_I965);
2811                 }
2812         }
2813
2814         I915_WRITE(EIR, eir);
2815         POSTING_READ(EIR);
2816         eir = I915_READ(EIR);
2817         if (eir) {
2818                 /*
2819                  * some errors might have become stuck,
2820                  * mask them.
2821                  */
2822                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2823                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2824                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2825         }
2826 }
2827
2828 /**
2829  * i915_handle_error - handle an error interrupt
2830  * @dev: drm device
2831  *
2832  * Do some basic checking of regsiter state at error interrupt time and
2833  * dump it to the syslog.  Also call i915_capture_error_state() to make
2834  * sure we get a record and make it available in debugfs.  Fire a uevent
2835  * so userspace knows something bad happened (should trigger collection
2836  * of a ring dump etc.).
2837  */
2838 void i915_handle_error(struct drm_device *dev, bool wedged,
2839                        const char *fmt, ...)
2840 {
2841         struct drm_i915_private *dev_priv = dev->dev_private;
2842         va_list args;
2843         char error_msg[80];
2844
2845         va_start(args, fmt);
2846         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2847         va_end(args);
2848
2849         i915_capture_error_state(dev, wedged, error_msg);
2850         i915_report_and_clear_eir(dev);
2851
2852         if (wedged) {
2853                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2854                                 &dev_priv->gpu_error.reset_counter);
2855
2856                 /*
2857                  * Wakeup waiting processes so that the reset work function
2858                  * i915_error_work_func doesn't deadlock trying to grab various
2859                  * locks. By bumping the reset counter first, the woken
2860                  * processes will see a reset in progress and back off,
2861                  * releasing their locks and then wait for the reset completion.
2862                  * We must do this for _all_ gpu waiters that might hold locks
2863                  * that the reset work needs to acquire.
2864                  *
2865                  * Note: The wake_up serves as the required memory barrier to
2866                  * ensure that the waiters see the updated value of the reset
2867                  * counter atomic_t.
2868                  */
2869                 i915_error_wake_up(dev_priv, false);
2870         }
2871
2872         /*
2873          * Our reset work can grab modeset locks (since it needs to reset the
2874          * state of outstanding pagelips). Hence it must not be run on our own
2875          * dev-priv->wq work queue for otherwise the flush_work in the pageflip
2876          * code will deadlock.
2877          */
2878         schedule_work(&dev_priv->gpu_error.work);
2879 }
2880
2881 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
2882 {
2883         struct drm_i915_private *dev_priv = dev->dev_private;
2884         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
2885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2886         struct drm_i915_gem_object *obj;
2887         struct intel_unpin_work *work;
2888         unsigned long flags;
2889         bool stall_detected;
2890
2891         /* Ignore early vblank irqs */
2892         if (intel_crtc == NULL)
2893                 return;
2894
2895         spin_lock_irqsave(&dev->event_lock, flags);
2896         work = intel_crtc->unpin_work;
2897
2898         if (work == NULL ||
2899             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
2900             !work->enable_stall_check) {
2901                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
2902                 spin_unlock_irqrestore(&dev->event_lock, flags);
2903                 return;
2904         }
2905
2906         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
2907         obj = work->pending_flip_obj;
2908         if (INTEL_INFO(dev)->gen >= 4) {
2909                 int dspsurf = DSPSURF(intel_crtc->plane);
2910                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
2911                                         i915_gem_obj_ggtt_offset(obj);
2912         } else {
2913                 int dspaddr = DSPADDR(intel_crtc->plane);
2914                 stall_detected = I915_READ(dspaddr) == (i915_gem_obj_ggtt_offset(obj) +
2915                                                         crtc->y * crtc->primary->fb->pitches[0] +
2916                                                         crtc->x * crtc->primary->fb->bits_per_pixel/8);
2917         }
2918
2919         spin_unlock_irqrestore(&dev->event_lock, flags);
2920
2921         if (stall_detected) {
2922                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
2923                 intel_prepare_page_flip(dev, intel_crtc->plane);
2924         }
2925 }
2926
2927 /* Called from drm generic code, passed 'crtc' which
2928  * we use as a pipe index
2929  */
2930 static int i915_enable_vblank(struct drm_device *dev, int pipe)
2931 {
2932         struct drm_i915_private *dev_priv = dev->dev_private;
2933         unsigned long irqflags;
2934
2935         if (!i915_pipe_enabled(dev, pipe))
2936                 return -EINVAL;
2937
2938         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2939         if (INTEL_INFO(dev)->gen >= 4)
2940                 i915_enable_pipestat(dev_priv, pipe,
2941                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2942         else
2943                 i915_enable_pipestat(dev_priv, pipe,
2944                                      PIPE_VBLANK_INTERRUPT_STATUS);
2945         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2946
2947         return 0;
2948 }
2949
2950 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
2951 {
2952         struct drm_i915_private *dev_priv = dev->dev_private;
2953         unsigned long irqflags;
2954         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2955                                                      DE_PIPE_VBLANK(pipe);
2956
2957         if (!i915_pipe_enabled(dev, pipe))
2958                 return -EINVAL;
2959
2960         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2961         ironlake_enable_display_irq(dev_priv, bit);
2962         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2963
2964         return 0;
2965 }
2966
2967 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2968 {
2969         struct drm_i915_private *dev_priv = dev->dev_private;
2970         unsigned long irqflags;
2971
2972         if (!i915_pipe_enabled(dev, pipe))
2973                 return -EINVAL;
2974
2975         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2976         i915_enable_pipestat(dev_priv, pipe,
2977                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2978         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2979
2980         return 0;
2981 }
2982
2983 static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2984 {
2985         struct drm_i915_private *dev_priv = dev->dev_private;
2986         unsigned long irqflags;
2987
2988         if (!i915_pipe_enabled(dev, pipe))
2989                 return -EINVAL;
2990
2991         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2992         dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2993         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2994         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
2995         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2996         return 0;
2997 }
2998
2999 /* Called from drm generic code, passed 'crtc' which
3000  * we use as a pipe index
3001  */
3002 static void i915_disable_vblank(struct drm_device *dev, int pipe)
3003 {
3004         struct drm_i915_private *dev_priv = dev->dev_private;
3005         unsigned long irqflags;
3006
3007         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3008         i915_disable_pipestat(dev_priv, pipe,
3009                               PIPE_VBLANK_INTERRUPT_STATUS |
3010                               PIPE_START_VBLANK_INTERRUPT_STATUS);
3011         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3012 }
3013
3014 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
3015 {
3016         struct drm_i915_private *dev_priv = dev->dev_private;
3017         unsigned long irqflags;
3018         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
3019                                                      DE_PIPE_VBLANK(pipe);
3020
3021         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3022         ironlake_disable_display_irq(dev_priv, bit);
3023         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3024 }
3025
3026 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
3027 {
3028         struct drm_i915_private *dev_priv = dev->dev_private;
3029         unsigned long irqflags;
3030
3031         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3032         i915_disable_pipestat(dev_priv, pipe,
3033                               PIPE_START_VBLANK_INTERRUPT_STATUS);
3034         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3035 }
3036
3037 static void gen8_disable_vblank(struct drm_device *dev, int pipe)
3038 {
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         unsigned long irqflags;
3041
3042         if (!i915_pipe_enabled(dev, pipe))
3043                 return;
3044
3045         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3046         dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
3047         I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
3048         POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
3049         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3050 }
3051
3052 static u32
3053 ring_last_seqno(struct intel_engine_cs *ring)
3054 {
3055         return list_entry(ring->request_list.prev,
3056                           struct drm_i915_gem_request, list)->seqno;
3057 }
3058
3059 static bool
3060 ring_idle(struct intel_engine_cs *ring, u32 seqno)
3061 {
3062         return (list_empty(&ring->request_list) ||
3063                 i915_seqno_passed(seqno, ring_last_seqno(ring)));
3064 }
3065
3066 static bool
3067 ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
3068 {
3069         if (INTEL_INFO(dev)->gen >= 8) {
3070                 return (ipehr >> 23) == 0x1c;
3071         } else {
3072                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
3073                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
3074                                  MI_SEMAPHORE_REGISTER);
3075         }
3076 }
3077
3078 static struct intel_engine_cs *
3079 semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
3080 {
3081         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3082         struct intel_engine_cs *signaller;
3083         int i;
3084
3085         if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
3086                 for_each_ring(signaller, dev_priv, i) {
3087                         if (ring == signaller)
3088                                 continue;
3089
3090                         if (offset == signaller->semaphore.signal_ggtt[ring->id])
3091                                 return signaller;
3092                 }
3093         } else {
3094                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
3095
3096                 for_each_ring(signaller, dev_priv, i) {
3097                         if(ring == signaller)
3098                                 continue;
3099
3100                         if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
3101                                 return signaller;
3102                 }
3103         }
3104
3105         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
3106                   ring->id, ipehr, offset);
3107
3108         return NULL;
3109 }
3110
3111 static struct intel_engine_cs *
3112 semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
3113 {
3114         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3115         u32 cmd, ipehr, head;
3116         u64 offset = 0;
3117         int i, backwards;
3118
3119         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
3120         if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
3121                 return NULL;
3122
3123         /*
3124          * HEAD is likely pointing to the dword after the actual command,
3125          * so scan backwards until we find the MBOX. But limit it to just 3
3126          * or 4 dwords depending on the semaphore wait command size.
3127          * Note that we don't care about ACTHD here since that might
3128          * point at at batch, and semaphores are always emitted into the
3129          * ringbuffer itself.
3130          */
3131         head = I915_READ_HEAD(ring) & HEAD_ADDR;
3132         backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
3133
3134         for (i = backwards; i; --i) {
3135                 /*
3136                  * Be paranoid and presume the hw has gone off into the wild -
3137                  * our ring is smaller than what the hardware (and hence
3138                  * HEAD_ADDR) allows. Also handles wrap-around.
3139                  */
3140                 head &= ring->buffer->size - 1;
3141
3142                 /* This here seems to blow up */
3143                 cmd = ioread32(ring->buffer->virtual_start + head);
3144                 if (cmd == ipehr)
3145                         break;
3146
3147                 head -= 4;
3148         }
3149
3150         if (!i)
3151                 return NULL;
3152
3153         *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
3154         if (INTEL_INFO(ring->dev)->gen >= 8) {
3155                 offset = ioread32(ring->buffer->virtual_start + head + 12);
3156                 offset <<= 32;
3157                 offset = ioread32(ring->buffer->virtual_start + head + 8);
3158         }
3159         return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
3160 }
3161
3162 static int semaphore_passed(struct intel_engine_cs *ring)
3163 {
3164         struct drm_i915_private *dev_priv = ring->dev->dev_private;
3165         struct intel_engine_cs *signaller;
3166         u32 seqno;
3167
3168         ring->hangcheck.deadlock++;
3169
3170         signaller = semaphore_waits_for(ring, &seqno);
3171         if (signaller == NULL)
3172                 return -1;
3173
3174         /* Prevent pathological recursion due to driver bugs */
3175         if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
3176                 return -1;
3177
3178         if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
3179                 return 1;
3180
3181         /* cursory check for an unkickable deadlock */
3182         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
3183             semaphore_passed(signaller) < 0)
3184                 return -1;
3185
3186         return 0;
3187 }
3188
3189 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
3190 {
3191         struct intel_engine_cs *ring;
3192         int i;
3193
3194         for_each_ring(ring, dev_priv, i)
3195                 ring->hangcheck.deadlock = 0;
3196 }
3197
3198 static enum intel_ring_hangcheck_action
3199 ring_stuck(struct intel_engine_cs *ring, u64 acthd)
3200 {
3201         struct drm_device *dev = ring->dev;
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203         u32 tmp;
3204
3205         if (acthd != ring->hangcheck.acthd) {
3206                 if (acthd > ring->hangcheck.max_acthd) {
3207                         ring->hangcheck.max_acthd = acthd;
3208                         return HANGCHECK_ACTIVE;
3209                 }
3210
3211                 return HANGCHECK_ACTIVE_LOOP;
3212         }
3213
3214         if (IS_GEN2(dev))
3215                 return HANGCHECK_HUNG;
3216
3217         /* Is the chip hanging on a WAIT_FOR_EVENT?
3218          * If so we can simply poke the RB_WAIT bit
3219          * and break the hang. This should work on
3220          * all but the second generation chipsets.
3221          */
3222         tmp = I915_READ_CTL(ring);
3223         if (tmp & RING_WAIT) {
3224                 i915_handle_error(dev, false,
3225                                   "Kicking stuck wait on %s",
3226                                   ring->name);
3227                 I915_WRITE_CTL(ring, tmp);
3228                 return HANGCHECK_KICK;
3229         }
3230
3231         if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3232                 switch (semaphore_passed(ring)) {
3233                 default:
3234                         return HANGCHECK_HUNG;
3235                 case 1:
3236                         i915_handle_error(dev, false,
3237                                           "Kicking stuck semaphore on %s",
3238                                           ring->name);
3239                         I915_WRITE_CTL(ring, tmp);
3240                         return HANGCHECK_KICK;
3241                 case 0:
3242                         return HANGCHECK_WAIT;
3243                 }
3244         }
3245
3246         return HANGCHECK_HUNG;
3247 }
3248
3249 /**
3250  * This is called when the chip hasn't reported back with completed
3251  * batchbuffers in a long time. We keep track per ring seqno progress and
3252  * if there are no progress, hangcheck score for that ring is increased.
3253  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3254  * we kick the ring. If we see no progress on three subsequent calls
3255  * we assume chip is wedged and try to fix it by resetting the chip.
3256  */
3257 static void i915_hangcheck_elapsed(unsigned long data)
3258 {
3259         struct drm_device *dev = (struct drm_device *)data;
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261         struct intel_engine_cs *ring;
3262         int i;
3263         int busy_count = 0, rings_hung = 0;
3264         bool stuck[I915_NUM_RINGS] = { 0 };
3265 #define BUSY 1
3266 #define KICK 5
3267 #define HUNG 20
3268
3269         if (!i915.enable_hangcheck)
3270                 return;
3271
3272         for_each_ring(ring, dev_priv, i) {
3273                 u64 acthd;
3274                 u32 seqno;
3275                 bool busy = true;
3276
3277                 semaphore_clear_deadlocks(dev_priv);
3278
3279                 seqno = ring->get_seqno(ring, false);
3280                 acthd = intel_ring_get_active_head(ring);
3281
3282                 if (ring->hangcheck.seqno == seqno) {
3283                         if (ring_idle(ring, seqno)) {
3284                                 ring->hangcheck.action = HANGCHECK_IDLE;
3285
3286                                 if (waitqueue_active(&ring->irq_queue)) {
3287                                         /* Issue a wake-up to catch stuck h/w. */
3288                                         if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
3289                                                 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
3290                                                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3291                                                                   ring->name);
3292                                                 else
3293                                                         DRM_INFO("Fake missed irq on %s\n",
3294                                                                  ring->name);
3295                                                 wake_up_all(&ring->irq_queue);
3296                                         }
3297                                         /* Safeguard against driver failure */
3298                                         ring->hangcheck.score += BUSY;
3299                                 } else
3300                                         busy = false;
3301                         } else {
3302                                 /* We always increment the hangcheck score
3303                                  * if the ring is busy and still processing
3304                                  * the same request, so that no single request
3305                                  * can run indefinitely (such as a chain of
3306                                  * batches). The only time we do not increment
3307                                  * the hangcheck score on this ring, if this
3308                                  * ring is in a legitimate wait for another
3309                                  * ring. In that case the waiting ring is a
3310                                  * victim and we want to be sure we catch the
3311                                  * right culprit. Then every time we do kick
3312                                  * the ring, add a small increment to the
3313                                  * score so that we can catch a batch that is
3314                                  * being repeatedly kicked and so responsible
3315                                  * for stalling the machine.
3316                                  */
3317                                 ring->hangcheck.action = ring_stuck(ring,
3318                                                                     acthd);
3319
3320                                 switch (ring->hangcheck.action) {
3321                                 case HANGCHECK_IDLE:
3322                                 case HANGCHECK_WAIT:
3323                                 case HANGCHECK_ACTIVE:
3324                                         break;
3325                                 case HANGCHECK_ACTIVE_LOOP:
3326                                         ring->hangcheck.score += BUSY;
3327                                         break;
3328                                 case HANGCHECK_KICK:
3329                                         ring->hangcheck.score += KICK;
3330                                         break;
3331                                 case HANGCHECK_HUNG:
3332                                         ring->hangcheck.score += HUNG;
3333                                         stuck[i] = true;
3334                                         break;
3335                                 }
3336                         }
3337                 } else {
3338                         ring->hangcheck.action = HANGCHECK_ACTIVE;
3339
3340                         /* Gradually reduce the count so that we catch DoS
3341                          * attempts across multiple batches.
3342                          */
3343                         if (ring->hangcheck.score > 0)
3344                                 ring->hangcheck.score--;
3345
3346                         ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
3347                 }
3348
3349                 ring->hangcheck.seqno = seqno;
3350                 ring->hangcheck.acthd = acthd;
3351                 busy_count += busy;
3352         }
3353
3354         for_each_ring(ring, dev_priv, i) {
3355                 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3356                         DRM_INFO("%s on %s\n",
3357                                  stuck[i] ? "stuck" : "no progress",
3358                                  ring->name);
3359                         rings_hung++;
3360                 }
3361         }
3362
3363         if (rings_hung)
3364                 return i915_handle_error(dev, true, "Ring hung");
3365
3366         if (busy_count)
3367                 /* Reset timer case chip hangs without another request
3368                  * being added */
3369                 i915_queue_hangcheck(dev);
3370 }
3371
3372 void i915_queue_hangcheck(struct drm_device *dev)
3373 {
3374         struct drm_i915_private *dev_priv = dev->dev_private;
3375         if (!i915.enable_hangcheck)
3376                 return;
3377
3378         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
3379                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
3380 }
3381
3382 static void ibx_irq_reset(struct drm_device *dev)
3383 {
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385
3386         if (HAS_PCH_NOP(dev))
3387                 return;
3388
3389         GEN5_IRQ_RESET(SDE);
3390
3391         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3392                 I915_WRITE(SERR_INT, 0xffffffff);
3393 }
3394
3395 /*
3396  * SDEIER is also touched by the interrupt handler to work around missed PCH
3397  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3398  * instead we unconditionally enable all PCH interrupt sources here, but then
3399  * only unmask them as needed with SDEIMR.
3400  *
3401  * This function needs to be called before interrupts are enabled.
3402  */
3403 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3404 {
3405         struct drm_i915_private *dev_priv = dev->dev_private;
3406
3407         if (HAS_PCH_NOP(dev))
3408                 return;
3409
3410         WARN_ON(I915_READ(SDEIER) != 0);
3411         I915_WRITE(SDEIER, 0xffffffff);
3412         POSTING_READ(SDEIER);
3413 }
3414
3415 static void gen5_gt_irq_reset(struct drm_device *dev)
3416 {
3417         struct drm_i915_private *dev_priv = dev->dev_private;
3418
3419         GEN5_IRQ_RESET(GT);
3420         if (INTEL_INFO(dev)->gen >= 6)
3421                 GEN5_IRQ_RESET(GEN6_PM);
3422 }
3423
3424 /* drm_dma.h hooks
3425 */
3426 static void ironlake_irq_reset(struct drm_device *dev)
3427 {
3428         struct drm_i915_private *dev_priv = dev->dev_private;
3429
3430         I915_WRITE(HWSTAM, 0xffffffff);
3431
3432         GEN5_IRQ_RESET(DE);
3433         if (IS_GEN7(dev))
3434                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3435
3436         gen5_gt_irq_reset(dev);
3437
3438         ibx_irq_reset(dev);
3439 }
3440
3441 static void valleyview_irq_preinstall(struct drm_device *dev)
3442 {
3443         struct drm_i915_private *dev_priv = dev->dev_private;
3444         int pipe;
3445
3446         /* VLV magic */
3447         I915_WRITE(VLV_IMR, 0);
3448         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3449         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3450         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3451
3452         /* and GT */
3453         I915_WRITE(GTIIR, I915_READ(GTIIR));
3454         I915_WRITE(GTIIR, I915_READ(GTIIR));
3455
3456         gen5_gt_irq_reset(dev);
3457
3458         I915_WRITE(DPINVGTT, 0xff);
3459
3460         I915_WRITE(PORT_HOTPLUG_EN, 0);
3461         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3462         for_each_pipe(pipe)
3463                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3464         I915_WRITE(VLV_IIR, 0xffffffff);
3465         I915_WRITE(VLV_IMR, 0xffffffff);
3466         I915_WRITE(VLV_IER, 0x0);
3467         POSTING_READ(VLV_IER);
3468 }
3469
3470 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3471 {
3472         GEN8_IRQ_RESET_NDX(GT, 0);
3473         GEN8_IRQ_RESET_NDX(GT, 1);
3474         GEN8_IRQ_RESET_NDX(GT, 2);
3475         GEN8_IRQ_RESET_NDX(GT, 3);
3476 }
3477
3478 static void gen8_irq_reset(struct drm_device *dev)
3479 {
3480         struct drm_i915_private *dev_priv = dev->dev_private;
3481         int pipe;
3482
3483         I915_WRITE(GEN8_MASTER_IRQ, 0);
3484         POSTING_READ(GEN8_MASTER_IRQ);
3485
3486         gen8_gt_irq_reset(dev_priv);
3487
3488         for_each_pipe(pipe)
3489                 if (intel_display_power_enabled(dev_priv,
3490                                                 POWER_DOMAIN_PIPE(pipe)))
3491                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3492
3493         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3494         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3495         GEN5_IRQ_RESET(GEN8_PCU_);
3496
3497         ibx_irq_reset(dev);
3498 }
3499
3500 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
3501 {
3502         unsigned long irqflags;
3503
3504         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3505         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
3506                           ~dev_priv->de_irq_mask[PIPE_B]);
3507         GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
3508                           ~dev_priv->de_irq_mask[PIPE_C]);
3509         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3510 }
3511
3512 static void cherryview_irq_preinstall(struct drm_device *dev)
3513 {
3514         struct drm_i915_private *dev_priv = dev->dev_private;
3515         int pipe;
3516
3517         I915_WRITE(GEN8_MASTER_IRQ, 0);
3518         POSTING_READ(GEN8_MASTER_IRQ);
3519
3520         gen8_gt_irq_reset(dev_priv);
3521
3522         GEN5_IRQ_RESET(GEN8_PCU_);
3523
3524         POSTING_READ(GEN8_PCU_IIR);
3525
3526         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3527
3528         I915_WRITE(PORT_HOTPLUG_EN, 0);
3529         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3530
3531         for_each_pipe(pipe)
3532                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3533
3534         I915_WRITE(VLV_IMR, 0xffffffff);
3535         I915_WRITE(VLV_IER, 0x0);
3536         I915_WRITE(VLV_IIR, 0xffffffff);
3537         POSTING_READ(VLV_IIR);
3538 }
3539
3540 static void ibx_hpd_irq_setup(struct drm_device *dev)
3541 {
3542         struct drm_i915_private *dev_priv = dev->dev_private;
3543         struct intel_encoder *intel_encoder;
3544         u32 hotplug_irqs, hotplug, enabled_irqs = 0;
3545
3546         if (HAS_PCH_IBX(dev)) {
3547                 hotplug_irqs = SDE_HOTPLUG_MASK;
3548                 for_each_intel_encoder(dev, intel_encoder)
3549                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3550                                 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
3551         } else {
3552                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3553                 for_each_intel_encoder(dev, intel_encoder)
3554                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
3555                                 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
3556         }
3557
3558         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3559
3560         /*
3561          * Enable digital hotplug on the PCH, and configure the DP short pulse
3562          * duration to 2ms (which is the minimum in the Display Port spec)
3563          *
3564          * This register is the same on all known PCH chips.
3565          */
3566         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3567         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3568         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3569         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3570         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3571         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3572 }
3573
3574 static void ibx_irq_postinstall(struct drm_device *dev)
3575 {
3576         struct drm_i915_private *dev_priv = dev->dev_private;
3577         u32 mask;
3578
3579         if (HAS_PCH_NOP(dev))
3580                 return;
3581
3582         if (HAS_PCH_IBX(dev))
3583                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3584         else
3585                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3586
3587         GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
3588         I915_WRITE(SDEIMR, ~mask);
3589 }
3590
3591 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3592 {
3593         struct drm_i915_private *dev_priv = dev->dev_private;
3594         u32 pm_irqs, gt_irqs;
3595
3596         pm_irqs = gt_irqs = 0;
3597
3598         dev_priv->gt_irq_mask = ~0;
3599         if (HAS_L3_DPF(dev)) {
3600                 /* L3 parity interrupt is always unmasked. */
3601                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3602                 gt_irqs |= GT_PARITY_ERROR(dev);
3603         }
3604
3605         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3606         if (IS_GEN5(dev)) {
3607                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3608                            ILK_BSD_USER_INTERRUPT;
3609         } else {
3610                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3611         }
3612
3613         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3614
3615         if (INTEL_INFO(dev)->gen >= 6) {
3616                 pm_irqs |= dev_priv->pm_rps_events;
3617
3618                 if (HAS_VEBOX(dev))
3619                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3620
3621                 dev_priv->pm_irq_mask = 0xffffffff;
3622                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3623         }
3624 }
3625
3626 static int ironlake_irq_postinstall(struct drm_device *dev)
3627 {
3628         unsigned long irqflags;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         u32 display_mask, extra_mask;
3631
3632         if (INTEL_INFO(dev)->gen >= 7) {
3633                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3634                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3635                                 DE_PLANEB_FLIP_DONE_IVB |
3636                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3637                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3638                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
3639         } else {
3640                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3641                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3642                                 DE_AUX_CHANNEL_A |
3643                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3644                                 DE_POISON);
3645                 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3646                                 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
3647         }
3648
3649         dev_priv->irq_mask = ~display_mask;
3650
3651         I915_WRITE(HWSTAM, 0xeffe);
3652
3653         ibx_irq_pre_postinstall(dev);
3654
3655         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3656
3657         gen5_gt_irq_postinstall(dev);
3658
3659         ibx_irq_postinstall(dev);
3660
3661         if (IS_IRONLAKE_M(dev)) {
3662                 /* Enable PCU event interrupts
3663                  *
3664                  * spinlocking not required here for correctness since interrupt
3665                  * setup is guaranteed to run in single-threaded context. But we
3666                  * need it to make the assert_spin_locked happy. */
3667                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3668                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
3669                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3670         }
3671
3672         return 0;
3673 }
3674
3675 static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3676 {
3677         u32 pipestat_mask;
3678         u32 iir_mask;
3679
3680         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3681                         PIPE_FIFO_UNDERRUN_STATUS;
3682
3683         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3684         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3685         POSTING_READ(PIPESTAT(PIPE_A));
3686
3687         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3688                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3689
3690         i915_enable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3691                                                PIPE_GMBUS_INTERRUPT_STATUS);
3692         i915_enable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3693
3694         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3695                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3696                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3697         dev_priv->irq_mask &= ~iir_mask;
3698
3699         I915_WRITE(VLV_IIR, iir_mask);
3700         I915_WRITE(VLV_IIR, iir_mask);
3701         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3702         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3703         POSTING_READ(VLV_IER);
3704 }
3705
3706 static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3707 {
3708         u32 pipestat_mask;
3709         u32 iir_mask;
3710
3711         iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3712                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3713                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3714
3715         dev_priv->irq_mask |= iir_mask;
3716         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3717         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3718         I915_WRITE(VLV_IIR, iir_mask);
3719         I915_WRITE(VLV_IIR, iir_mask);
3720         POSTING_READ(VLV_IIR);
3721
3722         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3723                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3724
3725         i915_disable_pipestat(dev_priv, PIPE_A, pipestat_mask |
3726                                                 PIPE_GMBUS_INTERRUPT_STATUS);
3727         i915_disable_pipestat(dev_priv, PIPE_B, pipestat_mask);
3728
3729         pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3730                         PIPE_FIFO_UNDERRUN_STATUS;
3731         I915_WRITE(PIPESTAT(PIPE_A), pipestat_mask);
3732         I915_WRITE(PIPESTAT(PIPE_B), pipestat_mask);
3733         POSTING_READ(PIPESTAT(PIPE_A));
3734 }
3735
3736 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3737 {
3738         assert_spin_locked(&dev_priv->irq_lock);
3739
3740         if (dev_priv->display_irqs_enabled)
3741                 return;
3742
3743         dev_priv->display_irqs_enabled = true;
3744
3745         if (dev_priv->dev->irq_enabled)
3746                 valleyview_display_irqs_install(dev_priv);
3747 }
3748
3749 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3750 {
3751         assert_spin_locked(&dev_priv->irq_lock);
3752
3753         if (!dev_priv->display_irqs_enabled)
3754                 return;
3755
3756         dev_priv->display_irqs_enabled = false;
3757
3758         if (dev_priv->dev->irq_enabled)
3759                 valleyview_display_irqs_uninstall(dev_priv);
3760 }
3761
3762 static int valleyview_irq_postinstall(struct drm_device *dev)
3763 {
3764         struct drm_i915_private *dev_priv = dev->dev_private;
3765         unsigned long irqflags;
3766
3767         dev_priv->irq_mask = ~0;
3768
3769         I915_WRITE(PORT_HOTPLUG_EN, 0);
3770         POSTING_READ(PORT_HOTPLUG_EN);
3771
3772         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3773         I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3774         I915_WRITE(VLV_IIR, 0xffffffff);
3775         POSTING_READ(VLV_IER);
3776
3777         /* Interrupt setup is already guaranteed to be single-threaded, this is
3778          * just to make the assert_spin_locked check happy. */
3779         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3780         if (dev_priv->display_irqs_enabled)
3781                 valleyview_display_irqs_install(dev_priv);
3782         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3783
3784         I915_WRITE(VLV_IIR, 0xffffffff);
3785         I915_WRITE(VLV_IIR, 0xffffffff);
3786
3787         gen5_gt_irq_postinstall(dev);
3788
3789         /* ack & enable invalid PTE error interrupts */
3790 #if 0 /* FIXME: add support to irq handler for checking these bits */
3791         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3792         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3793 #endif
3794
3795         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3796
3797         return 0;
3798 }
3799
3800 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3801 {
3802         int i;
3803
3804         /* These are interrupts we'll toggle with the ring mask register */
3805         uint32_t gt_interrupts[] = {
3806                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3807                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3808                         GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
3809                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3810                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3811                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3812                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3813                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3814                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3815                 0,
3816                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3817                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3818                 };
3819
3820         for (i = 0; i < ARRAY_SIZE(gt_interrupts); i++)
3821                 GEN8_IRQ_INIT_NDX(GT, i, ~gt_interrupts[i], gt_interrupts[i]);
3822
3823         dev_priv->pm_irq_mask = 0xffffffff;
3824 }
3825
3826 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3827 {
3828         struct drm_device *dev = dev_priv->dev;
3829         uint32_t de_pipe_masked = GEN8_PIPE_PRIMARY_FLIP_DONE |
3830                 GEN8_PIPE_CDCLK_CRC_DONE |
3831                 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3832         uint32_t de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3833                 GEN8_PIPE_FIFO_UNDERRUN;
3834         int pipe;
3835         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3836         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3837         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3838
3839         for_each_pipe(pipe)
3840                 if (intel_display_power_enabled(dev_priv,
3841                                 POWER_DOMAIN_PIPE(pipe)))
3842                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3843                                           dev_priv->de_irq_mask[pipe],
3844                                           de_pipe_enables);
3845
3846         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~GEN8_AUX_CHANNEL_A, GEN8_AUX_CHANNEL_A);
3847 }
3848
3849 static int gen8_irq_postinstall(struct drm_device *dev)
3850 {
3851         struct drm_i915_private *dev_priv = dev->dev_private;
3852
3853         ibx_irq_pre_postinstall(dev);
3854
3855         gen8_gt_irq_postinstall(dev_priv);
3856         gen8_de_irq_postinstall(dev_priv);
3857
3858         ibx_irq_postinstall(dev);
3859
3860         I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3861         POSTING_READ(GEN8_MASTER_IRQ);
3862
3863         return 0;
3864 }
3865
3866 static int cherryview_irq_postinstall(struct drm_device *dev)
3867 {
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869         u32 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3870                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3871                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3872                 I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3873         u32 pipestat_enable = PLANE_FLIP_DONE_INT_STATUS_VLV |
3874                 PIPE_CRC_DONE_INTERRUPT_STATUS;
3875         unsigned long irqflags;
3876         int pipe;
3877
3878         /*
3879          * Leave vblank interrupts masked initially.  enable/disable will
3880          * toggle them based on usage.
3881          */
3882         dev_priv->irq_mask = ~enable_mask;
3883
3884         for_each_pipe(pipe)
3885                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3886
3887         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3888         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3889         for_each_pipe(pipe)
3890                 i915_enable_pipestat(dev_priv, pipe, pipestat_enable);
3891         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3892
3893         I915_WRITE(VLV_IIR, 0xffffffff);
3894         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3895         I915_WRITE(VLV_IER, enable_mask);
3896
3897         gen8_gt_irq_postinstall(dev_priv);
3898
3899         I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3900         POSTING_READ(GEN8_MASTER_IRQ);
3901
3902         return 0;
3903 }
3904
3905 static void gen8_irq_uninstall(struct drm_device *dev)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909         if (!dev_priv)
3910                 return;
3911
3912         gen8_irq_reset(dev);
3913 }
3914
3915 static void valleyview_irq_uninstall(struct drm_device *dev)
3916 {
3917         struct drm_i915_private *dev_priv = dev->dev_private;
3918         unsigned long irqflags;
3919         int pipe;
3920
3921         if (!dev_priv)
3922                 return;
3923
3924         I915_WRITE(VLV_MASTER_IER, 0);
3925
3926         for_each_pipe(pipe)
3927                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3928
3929         I915_WRITE(HWSTAM, 0xffffffff);
3930         I915_WRITE(PORT_HOTPLUG_EN, 0);
3931         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3932
3933         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3934         if (dev_priv->display_irqs_enabled)
3935                 valleyview_display_irqs_uninstall(dev_priv);
3936         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3937
3938         dev_priv->irq_mask = 0;
3939
3940         I915_WRITE(VLV_IIR, 0xffffffff);
3941         I915_WRITE(VLV_IMR, 0xffffffff);
3942         I915_WRITE(VLV_IER, 0x0);
3943         POSTING_READ(VLV_IER);
3944 }
3945
3946 static void cherryview_irq_uninstall(struct drm_device *dev)
3947 {
3948         struct drm_i915_private *dev_priv = dev->dev_private;
3949         int pipe;
3950
3951         if (!dev_priv)
3952                 return;
3953
3954         I915_WRITE(GEN8_MASTER_IRQ, 0);
3955         POSTING_READ(GEN8_MASTER_IRQ);
3956
3957 #define GEN8_IRQ_FINI_NDX(type, which)                          \
3958 do {                                                            \
3959         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff);       \
3960         I915_WRITE(GEN8_##type##_IER(which), 0);                \
3961         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
3962         POSTING_READ(GEN8_##type##_IIR(which));                 \
3963         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff);       \
3964 } while (0)
3965
3966 #define GEN8_IRQ_FINI(type)                             \
3967 do {                                                    \
3968         I915_WRITE(GEN8_##type##_IMR, 0xffffffff);      \
3969         I915_WRITE(GEN8_##type##_IER, 0);               \
3970         I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
3971         POSTING_READ(GEN8_##type##_IIR);                \
3972         I915_WRITE(GEN8_##type##_IIR, 0xffffffff);      \
3973 } while (0)
3974
3975         GEN8_IRQ_FINI_NDX(GT, 0);
3976         GEN8_IRQ_FINI_NDX(GT, 1);
3977         GEN8_IRQ_FINI_NDX(GT, 2);
3978         GEN8_IRQ_FINI_NDX(GT, 3);
3979
3980         GEN8_IRQ_FINI(PCU);
3981
3982 #undef GEN8_IRQ_FINI
3983 #undef GEN8_IRQ_FINI_NDX
3984
3985         I915_WRITE(PORT_HOTPLUG_EN, 0);
3986         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3987
3988         for_each_pipe(pipe)
3989                 I915_WRITE(PIPESTAT(pipe), 0xffff);
3990
3991         I915_WRITE(VLV_IMR, 0xffffffff);
3992         I915_WRITE(VLV_IER, 0x0);
3993         I915_WRITE(VLV_IIR, 0xffffffff);
3994         POSTING_READ(VLV_IIR);
3995 }
3996
3997 static void ironlake_irq_uninstall(struct drm_device *dev)
3998 {
3999         struct drm_i915_private *dev_priv = dev->dev_private;
4000
4001         if (!dev_priv)
4002                 return;
4003
4004         ironlake_irq_reset(dev);
4005 }
4006
4007 static void i8xx_irq_preinstall(struct drm_device * dev)
4008 {
4009         struct drm_i915_private *dev_priv = dev->dev_private;
4010         int pipe;
4011
4012         for_each_pipe(pipe)
4013                 I915_WRITE(PIPESTAT(pipe), 0);
4014         I915_WRITE16(IMR, 0xffff);
4015         I915_WRITE16(IER, 0x0);
4016         POSTING_READ16(IER);
4017 }
4018
4019 static int i8xx_irq_postinstall(struct drm_device *dev)
4020 {
4021         struct drm_i915_private *dev_priv = dev->dev_private;
4022         unsigned long irqflags;
4023
4024         I915_WRITE16(EMR,
4025                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4026
4027         /* Unmask the interrupts that we always want on. */
4028         dev_priv->irq_mask =
4029                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4030                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4031                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4032                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4033                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4034         I915_WRITE16(IMR, dev_priv->irq_mask);
4035
4036         I915_WRITE16(IER,
4037                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4038                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4039                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4040                      I915_USER_INTERRUPT);
4041         POSTING_READ16(IER);
4042
4043         /* Interrupt setup is already guaranteed to be single-threaded, this is
4044          * just to make the assert_spin_locked check happy. */
4045         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4046         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4047         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4048         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4049
4050         return 0;
4051 }
4052
4053 /*
4054  * Returns true when a page flip has completed.
4055  */
4056 static bool i8xx_handle_vblank(struct drm_device *dev,
4057                                int plane, int pipe, u32 iir)
4058 {
4059         struct drm_i915_private *dev_priv = dev->dev_private;
4060         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4061
4062         if (!intel_pipe_handle_vblank(dev, pipe))
4063                 return false;
4064
4065         if ((iir & flip_pending) == 0)
4066                 return false;
4067
4068         intel_prepare_page_flip(dev, plane);
4069
4070         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4071          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4072          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4073          * the flip is completed (no longer pending). Since this doesn't raise
4074          * an interrupt per se, we watch for the change at vblank.
4075          */
4076         if (I915_READ16(ISR) & flip_pending)
4077                 return false;
4078
4079         intel_finish_page_flip(dev, pipe);
4080
4081         return true;
4082 }
4083
4084 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4085 {
4086         struct drm_device *dev = arg;
4087         struct drm_i915_private *dev_priv = dev->dev_private;
4088         u16 iir, new_iir;
4089         u32 pipe_stats[2];
4090         unsigned long irqflags;
4091         int pipe;
4092         u16 flip_mask =
4093                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4094                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4095
4096         iir = I915_READ16(IIR);
4097         if (iir == 0)
4098                 return IRQ_NONE;
4099
4100         while (iir & ~flip_mask) {
4101                 /* Can't rely on pipestat interrupt bit in iir as it might
4102                  * have been cleared after the pipestat interrupt was received.
4103                  * It doesn't set the bit in iir again, but it still produces
4104                  * interrupts (for non-MSI).
4105                  */
4106                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4107                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4108                         i915_handle_error(dev, false,
4109                                           "Command parser error, iir 0x%08x",
4110                                           iir);
4111
4112                 for_each_pipe(pipe) {
4113                         int reg = PIPESTAT(pipe);
4114                         pipe_stats[pipe] = I915_READ(reg);
4115
4116                         /*
4117                          * Clear the PIPE*STAT regs before the IIR
4118                          */
4119                         if (pipe_stats[pipe] & 0x8000ffff)
4120                                 I915_WRITE(reg, pipe_stats[pipe]);
4121                 }
4122                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4123
4124                 I915_WRITE16(IIR, iir & ~flip_mask);
4125                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4126
4127                 i915_update_dri1_breadcrumb(dev);
4128
4129                 if (iir & I915_USER_INTERRUPT)
4130                         notify_ring(dev, &dev_priv->ring[RCS]);
4131
4132                 for_each_pipe(pipe) {
4133                         int plane = pipe;
4134                         if (HAS_FBC(dev))
4135                                 plane = !plane;
4136
4137                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4138                             i8xx_handle_vblank(dev, plane, pipe, iir))
4139                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4140
4141                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4142                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4143
4144                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4145                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4146                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4147                 }
4148
4149                 iir = new_iir;
4150         }
4151
4152         return IRQ_HANDLED;
4153 }
4154
4155 static void i8xx_irq_uninstall(struct drm_device * dev)
4156 {
4157         struct drm_i915_private *dev_priv = dev->dev_private;
4158         int pipe;
4159
4160         for_each_pipe(pipe) {
4161                 /* Clear enable bits; then clear status bits */
4162                 I915_WRITE(PIPESTAT(pipe), 0);
4163                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4164         }
4165         I915_WRITE16(IMR, 0xffff);
4166         I915_WRITE16(IER, 0x0);
4167         I915_WRITE16(IIR, I915_READ16(IIR));
4168 }
4169
4170 static void i915_irq_preinstall(struct drm_device * dev)
4171 {
4172         struct drm_i915_private *dev_priv = dev->dev_private;
4173         int pipe;
4174
4175         if (I915_HAS_HOTPLUG(dev)) {
4176                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4177                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4178         }
4179
4180         I915_WRITE16(HWSTAM, 0xeffe);
4181         for_each_pipe(pipe)
4182                 I915_WRITE(PIPESTAT(pipe), 0);
4183         I915_WRITE(IMR, 0xffffffff);
4184         I915_WRITE(IER, 0x0);
4185         POSTING_READ(IER);
4186 }
4187
4188 static int i915_irq_postinstall(struct drm_device *dev)
4189 {
4190         struct drm_i915_private *dev_priv = dev->dev_private;
4191         u32 enable_mask;
4192         unsigned long irqflags;
4193
4194         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4195
4196         /* Unmask the interrupts that we always want on. */
4197         dev_priv->irq_mask =
4198                 ~(I915_ASLE_INTERRUPT |
4199                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4200                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4201                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4202                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4203                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4204
4205         enable_mask =
4206                 I915_ASLE_INTERRUPT |
4207                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4208                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4209                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
4210                 I915_USER_INTERRUPT;
4211
4212         if (I915_HAS_HOTPLUG(dev)) {
4213                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4214                 POSTING_READ(PORT_HOTPLUG_EN);
4215
4216                 /* Enable in IER... */
4217                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4218                 /* and unmask in IMR */
4219                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4220         }
4221
4222         I915_WRITE(IMR, dev_priv->irq_mask);
4223         I915_WRITE(IER, enable_mask);
4224         POSTING_READ(IER);
4225
4226         i915_enable_asle_pipestat(dev);
4227
4228         /* Interrupt setup is already guaranteed to be single-threaded, this is
4229          * just to make the assert_spin_locked check happy. */
4230         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4231         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4232         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4233         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4234
4235         return 0;
4236 }
4237
4238 /*
4239  * Returns true when a page flip has completed.
4240  */
4241 static bool i915_handle_vblank(struct drm_device *dev,
4242                                int plane, int pipe, u32 iir)
4243 {
4244         struct drm_i915_private *dev_priv = dev->dev_private;
4245         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4246
4247         if (!intel_pipe_handle_vblank(dev, pipe))
4248                 return false;
4249
4250         if ((iir & flip_pending) == 0)
4251                 return false;
4252
4253         intel_prepare_page_flip(dev, plane);
4254
4255         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4256          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4257          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4258          * the flip is completed (no longer pending). Since this doesn't raise
4259          * an interrupt per se, we watch for the change at vblank.
4260          */
4261         if (I915_READ(ISR) & flip_pending)
4262                 return false;
4263
4264         intel_finish_page_flip(dev, pipe);
4265
4266         return true;
4267 }
4268
4269 static irqreturn_t i915_irq_handler(int irq, void *arg)
4270 {
4271         struct drm_device *dev = arg;
4272         struct drm_i915_private *dev_priv = dev->dev_private;
4273         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4274         unsigned long irqflags;
4275         u32 flip_mask =
4276                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4277                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4278         int pipe, ret = IRQ_NONE;
4279
4280         iir = I915_READ(IIR);
4281         do {
4282                 bool irq_received = (iir & ~flip_mask) != 0;
4283                 bool blc_event = false;
4284
4285                 /* Can't rely on pipestat interrupt bit in iir as it might
4286                  * have been cleared after the pipestat interrupt was received.
4287                  * It doesn't set the bit in iir again, but it still produces
4288                  * interrupts (for non-MSI).
4289                  */
4290                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4291                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4292                         i915_handle_error(dev, false,
4293                                           "Command parser error, iir 0x%08x",
4294                                           iir);
4295
4296                 for_each_pipe(pipe) {
4297                         int reg = PIPESTAT(pipe);
4298                         pipe_stats[pipe] = I915_READ(reg);
4299
4300                         /* Clear the PIPE*STAT regs before the IIR */
4301                         if (pipe_stats[pipe] & 0x8000ffff) {
4302                                 I915_WRITE(reg, pipe_stats[pipe]);
4303                                 irq_received = true;
4304                         }
4305                 }
4306                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4307
4308                 if (!irq_received)
4309                         break;
4310
4311                 /* Consume port.  Then clear IIR or we'll miss events */
4312                 if (I915_HAS_HOTPLUG(dev) &&
4313                     iir & I915_DISPLAY_PORT_INTERRUPT)
4314                         i9xx_hpd_irq_handler(dev);
4315
4316                 I915_WRITE(IIR, iir & ~flip_mask);
4317                 new_iir = I915_READ(IIR); /* Flush posted writes */
4318
4319                 if (iir & I915_USER_INTERRUPT)
4320                         notify_ring(dev, &dev_priv->ring[RCS]);
4321
4322                 for_each_pipe(pipe) {
4323                         int plane = pipe;
4324                         if (HAS_FBC(dev))
4325                                 plane = !plane;
4326
4327                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4328                             i915_handle_vblank(dev, plane, pipe, iir))
4329                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4330
4331                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4332                                 blc_event = true;
4333
4334                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4335                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4336
4337                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4338                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4339                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4340                 }
4341
4342                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4343                         intel_opregion_asle_intr(dev);
4344
4345                 /* With MSI, interrupts are only generated when iir
4346                  * transitions from zero to nonzero.  If another bit got
4347                  * set while we were handling the existing iir bits, then
4348                  * we would never get another interrupt.
4349                  *
4350                  * This is fine on non-MSI as well, as if we hit this path
4351                  * we avoid exiting the interrupt handler only to generate
4352                  * another one.
4353                  *
4354                  * Note that for MSI this could cause a stray interrupt report
4355                  * if an interrupt landed in the time between writing IIR and
4356                  * the posting read.  This should be rare enough to never
4357                  * trigger the 99% of 100,000 interrupts test for disabling
4358                  * stray interrupts.
4359                  */
4360                 ret = IRQ_HANDLED;
4361                 iir = new_iir;
4362         } while (iir & ~flip_mask);
4363
4364         i915_update_dri1_breadcrumb(dev);
4365
4366         return ret;
4367 }
4368
4369 static void i915_irq_uninstall(struct drm_device * dev)
4370 {
4371         struct drm_i915_private *dev_priv = dev->dev_private;
4372         int pipe;
4373
4374         if (I915_HAS_HOTPLUG(dev)) {
4375                 I915_WRITE(PORT_HOTPLUG_EN, 0);
4376                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4377         }
4378
4379         I915_WRITE16(HWSTAM, 0xffff);
4380         for_each_pipe(pipe) {
4381                 /* Clear enable bits; then clear status bits */
4382                 I915_WRITE(PIPESTAT(pipe), 0);
4383                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4384         }
4385         I915_WRITE(IMR, 0xffffffff);
4386         I915_WRITE(IER, 0x0);
4387
4388         I915_WRITE(IIR, I915_READ(IIR));
4389 }
4390
4391 static void i965_irq_preinstall(struct drm_device * dev)
4392 {
4393         struct drm_i915_private *dev_priv = dev->dev_private;
4394         int pipe;
4395
4396         I915_WRITE(PORT_HOTPLUG_EN, 0);
4397         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4398
4399         I915_WRITE(HWSTAM, 0xeffe);
4400         for_each_pipe(pipe)
4401                 I915_WRITE(PIPESTAT(pipe), 0);
4402         I915_WRITE(IMR, 0xffffffff);
4403         I915_WRITE(IER, 0x0);
4404         POSTING_READ(IER);
4405 }
4406
4407 static int i965_irq_postinstall(struct drm_device *dev)
4408 {
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         u32 enable_mask;
4411         u32 error_mask;
4412         unsigned long irqflags;
4413
4414         /* Unmask the interrupts that we always want on. */
4415         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4416                                I915_DISPLAY_PORT_INTERRUPT |
4417                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4418                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4419                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4420                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4421                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4422
4423         enable_mask = ~dev_priv->irq_mask;
4424         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4425                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4426         enable_mask |= I915_USER_INTERRUPT;
4427
4428         if (IS_G4X(dev))
4429                 enable_mask |= I915_BSD_USER_INTERRUPT;
4430
4431         /* Interrupt setup is already guaranteed to be single-threaded, this is
4432          * just to make the assert_spin_locked check happy. */
4433         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4434         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4435         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4436         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4437         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4438
4439         /*
4440          * Enable some error detection, note the instruction error mask
4441          * bit is reserved, so we leave it masked.
4442          */
4443         if (IS_G4X(dev)) {
4444                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4445                                GM45_ERROR_MEM_PRIV |
4446                                GM45_ERROR_CP_PRIV |
4447                                I915_ERROR_MEMORY_REFRESH);
4448         } else {
4449                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4450                                I915_ERROR_MEMORY_REFRESH);
4451         }
4452         I915_WRITE(EMR, error_mask);
4453
4454         I915_WRITE(IMR, dev_priv->irq_mask);
4455         I915_WRITE(IER, enable_mask);
4456         POSTING_READ(IER);
4457
4458         I915_WRITE(PORT_HOTPLUG_EN, 0);
4459         POSTING_READ(PORT_HOTPLUG_EN);
4460
4461         i915_enable_asle_pipestat(dev);
4462
4463         return 0;
4464 }
4465
4466 static void i915_hpd_irq_setup(struct drm_device *dev)
4467 {
4468         struct drm_i915_private *dev_priv = dev->dev_private;
4469         struct intel_encoder *intel_encoder;
4470         u32 hotplug_en;
4471
4472         assert_spin_locked(&dev_priv->irq_lock);
4473
4474         if (I915_HAS_HOTPLUG(dev)) {
4475                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4476                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4477                 /* Note HDMI and DP share hotplug bits */
4478                 /* enable bits are the same for all generations */
4479                 for_each_intel_encoder(dev, intel_encoder)
4480                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4481                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4482                 /* Programming the CRT detection parameters tends
4483                    to generate a spurious hotplug event about three
4484                    seconds later.  So just do it once.
4485                 */
4486                 if (IS_G4X(dev))
4487                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4488                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4489                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4490
4491                 /* Ignore TV since it's buggy */
4492                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
4493         }
4494 }
4495
4496 static irqreturn_t i965_irq_handler(int irq, void *arg)
4497 {
4498         struct drm_device *dev = arg;
4499         struct drm_i915_private *dev_priv = dev->dev_private;
4500         u32 iir, new_iir;
4501         u32 pipe_stats[I915_MAX_PIPES];
4502         unsigned long irqflags;
4503         int ret = IRQ_NONE, pipe;
4504         u32 flip_mask =
4505                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4506                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4507
4508         iir = I915_READ(IIR);
4509
4510         for (;;) {
4511                 bool irq_received = (iir & ~flip_mask) != 0;
4512                 bool blc_event = false;
4513
4514                 /* Can't rely on pipestat interrupt bit in iir as it might
4515                  * have been cleared after the pipestat interrupt was received.
4516                  * It doesn't set the bit in iir again, but it still produces
4517                  * interrupts (for non-MSI).
4518                  */
4519                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4520                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4521                         i915_handle_error(dev, false,
4522                                           "Command parser error, iir 0x%08x",
4523                                           iir);
4524
4525                 for_each_pipe(pipe) {
4526                         int reg = PIPESTAT(pipe);
4527                         pipe_stats[pipe] = I915_READ(reg);
4528
4529                         /*
4530                          * Clear the PIPE*STAT regs before the IIR
4531                          */
4532                         if (pipe_stats[pipe] & 0x8000ffff) {
4533                                 I915_WRITE(reg, pipe_stats[pipe]);
4534                                 irq_received = true;
4535                         }
4536                 }
4537                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4538
4539                 if (!irq_received)
4540                         break;
4541
4542                 ret = IRQ_HANDLED;
4543
4544                 /* Consume port.  Then clear IIR or we'll miss events */
4545                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4546                         i9xx_hpd_irq_handler(dev);
4547
4548                 I915_WRITE(IIR, iir & ~flip_mask);
4549                 new_iir = I915_READ(IIR); /* Flush posted writes */
4550
4551                 if (iir & I915_USER_INTERRUPT)
4552                         notify_ring(dev, &dev_priv->ring[RCS]);
4553                 if (iir & I915_BSD_USER_INTERRUPT)
4554                         notify_ring(dev, &dev_priv->ring[VCS]);
4555
4556                 for_each_pipe(pipe) {
4557                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4558                             i915_handle_vblank(dev, pipe, pipe, iir))
4559                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4560
4561                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4562                                 blc_event = true;
4563
4564                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4565                                 i9xx_pipe_crc_irq_handler(dev, pipe);
4566
4567                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS &&
4568                             intel_set_cpu_fifo_underrun_reporting(dev, pipe, false))
4569                                 DRM_ERROR("pipe %c underrun\n", pipe_name(pipe));
4570                 }
4571
4572                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4573                         intel_opregion_asle_intr(dev);
4574
4575                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4576                         gmbus_irq_handler(dev);
4577
4578                 /* With MSI, interrupts are only generated when iir
4579                  * transitions from zero to nonzero.  If another bit got
4580                  * set while we were handling the existing iir bits, then
4581                  * we would never get another interrupt.
4582                  *
4583                  * This is fine on non-MSI as well, as if we hit this path
4584                  * we avoid exiting the interrupt handler only to generate
4585                  * another one.
4586                  *
4587                  * Note that for MSI this could cause a stray interrupt report
4588                  * if an interrupt landed in the time between writing IIR and
4589                  * the posting read.  This should be rare enough to never
4590                  * trigger the 99% of 100,000 interrupts test for disabling
4591                  * stray interrupts.
4592                  */
4593                 iir = new_iir;
4594         }
4595
4596         i915_update_dri1_breadcrumb(dev);
4597
4598         return ret;
4599 }
4600
4601 static void i965_irq_uninstall(struct drm_device * dev)
4602 {
4603         struct drm_i915_private *dev_priv = dev->dev_private;
4604         int pipe;
4605
4606         if (!dev_priv)
4607                 return;
4608
4609         I915_WRITE(PORT_HOTPLUG_EN, 0);
4610         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4611
4612         I915_WRITE(HWSTAM, 0xffffffff);
4613         for_each_pipe(pipe)
4614                 I915_WRITE(PIPESTAT(pipe), 0);
4615         I915_WRITE(IMR, 0xffffffff);
4616         I915_WRITE(IER, 0x0);
4617
4618         for_each_pipe(pipe)
4619                 I915_WRITE(PIPESTAT(pipe),
4620                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4621         I915_WRITE(IIR, I915_READ(IIR));
4622 }
4623
4624 static void intel_hpd_irq_reenable(struct work_struct *work)
4625 {
4626         struct drm_i915_private *dev_priv =
4627                 container_of(work, typeof(*dev_priv),
4628                              hotplug_reenable_work.work);
4629         struct drm_device *dev = dev_priv->dev;
4630         struct drm_mode_config *mode_config = &dev->mode_config;
4631         unsigned long irqflags;
4632         int i;
4633
4634         intel_runtime_pm_get(dev_priv);
4635
4636         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4637         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4638                 struct drm_connector *connector;
4639
4640                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4641                         continue;
4642
4643                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4644
4645                 list_for_each_entry(connector, &mode_config->connector_list, head) {
4646                         struct intel_connector *intel_connector = to_intel_connector(connector);
4647
4648                         if (intel_connector->encoder->hpd_pin == i) {
4649                                 if (connector->polled != intel_connector->polled)
4650                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
4651                                                          connector->name);
4652                                 connector->polled = intel_connector->polled;
4653                                 if (!connector->polled)
4654                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4655                         }
4656                 }
4657         }
4658         if (dev_priv->display.hpd_irq_setup)
4659                 dev_priv->display.hpd_irq_setup(dev);
4660         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4661
4662         intel_runtime_pm_put(dev_priv);
4663 }
4664
4665 void intel_irq_init(struct drm_device *dev)
4666 {
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668
4669         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
4670         INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
4671         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
4672         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4673         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4674
4675         /* Let's track the enabled rps events */
4676         if (IS_VALLEYVIEW(dev))
4677                 /* WaGsvRC0ResidenncyMethod:VLV */
4678                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4679         else
4680                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4681
4682         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
4683                     i915_hangcheck_elapsed,
4684                     (unsigned long) dev);
4685         INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
4686                           intel_hpd_irq_reenable);
4687
4688         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
4689
4690         /* Haven't installed the IRQ handler yet */
4691         dev_priv->pm._irqs_disabled = true;
4692
4693         if (IS_GEN2(dev)) {
4694                 dev->max_vblank_count = 0;
4695                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4696         } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
4697                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4698                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
4699         } else {
4700                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4701                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4702         }
4703
4704         /*
4705          * Opt out of the vblank disable timer on everything except gen2.
4706          * Gen2 doesn't have a hardware frame counter and so depends on
4707          * vblank interrupts to produce sane vblank seuquence numbers.
4708          */
4709         if (!IS_GEN2(dev))
4710                 dev->vblank_disable_immediate = true;
4711
4712         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
4713                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4714                 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4715         }
4716
4717         if (IS_CHERRYVIEW(dev)) {
4718                 dev->driver->irq_handler = cherryview_irq_handler;
4719                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4720                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4721                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4722                 dev->driver->enable_vblank = valleyview_enable_vblank;
4723                 dev->driver->disable_vblank = valleyview_disable_vblank;
4724                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4725         } else if (IS_VALLEYVIEW(dev)) {
4726                 dev->driver->irq_handler = valleyview_irq_handler;
4727                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4728                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4729                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4730                 dev->driver->enable_vblank = valleyview_enable_vblank;
4731                 dev->driver->disable_vblank = valleyview_disable_vblank;
4732                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4733         } else if (IS_GEN8(dev)) {
4734                 dev->driver->irq_handler = gen8_irq_handler;
4735                 dev->driver->irq_preinstall = gen8_irq_reset;
4736                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4737                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4738                 dev->driver->enable_vblank = gen8_enable_vblank;
4739                 dev->driver->disable_vblank = gen8_disable_vblank;
4740                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4741         } else if (HAS_PCH_SPLIT(dev)) {
4742                 dev->driver->irq_handler = ironlake_irq_handler;
4743                 dev->driver->irq_preinstall = ironlake_irq_reset;
4744                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4745                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4746                 dev->driver->enable_vblank = ironlake_enable_vblank;
4747                 dev->driver->disable_vblank = ironlake_disable_vblank;
4748                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4749         } else {
4750                 if (INTEL_INFO(dev)->gen == 2) {
4751                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4752                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4753                         dev->driver->irq_handler = i8xx_irq_handler;
4754                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4755                 } else if (INTEL_INFO(dev)->gen == 3) {
4756                         dev->driver->irq_preinstall = i915_irq_preinstall;
4757                         dev->driver->irq_postinstall = i915_irq_postinstall;
4758                         dev->driver->irq_uninstall = i915_irq_uninstall;
4759                         dev->driver->irq_handler = i915_irq_handler;
4760                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4761                 } else {
4762                         dev->driver->irq_preinstall = i965_irq_preinstall;
4763                         dev->driver->irq_postinstall = i965_irq_postinstall;
4764                         dev->driver->irq_uninstall = i965_irq_uninstall;
4765                         dev->driver->irq_handler = i965_irq_handler;
4766                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4767                 }
4768                 dev->driver->enable_vblank = i915_enable_vblank;
4769                 dev->driver->disable_vblank = i915_disable_vblank;
4770         }
4771 }
4772
4773 void intel_hpd_init(struct drm_device *dev)
4774 {
4775         struct drm_i915_private *dev_priv = dev->dev_private;
4776         struct drm_mode_config *mode_config = &dev->mode_config;
4777         struct drm_connector *connector;
4778         unsigned long irqflags;
4779         int i;
4780
4781         for (i = 1; i < HPD_NUM_PINS; i++) {
4782                 dev_priv->hpd_stats[i].hpd_cnt = 0;
4783                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4784         }
4785         list_for_each_entry(connector, &mode_config->connector_list, head) {
4786                 struct intel_connector *intel_connector = to_intel_connector(connector);
4787                 connector->polled = intel_connector->polled;
4788                 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4789                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4790                 if (intel_connector->mst_port)
4791                         connector->polled = DRM_CONNECTOR_POLL_HPD;
4792         }
4793
4794         /* Interrupt setup is already guaranteed to be single-threaded, this is
4795          * just to make the assert_spin_locked checks happy. */
4796         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
4797         if (dev_priv->display.hpd_irq_setup)
4798                 dev_priv->display.hpd_irq_setup(dev);
4799         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
4800 }
4801
4802 /* Disable interrupts so we can allow runtime PM. */
4803 void intel_runtime_pm_disable_interrupts(struct drm_device *dev)
4804 {
4805         struct drm_i915_private *dev_priv = dev->dev_private;
4806
4807         dev->driver->irq_uninstall(dev);
4808         dev_priv->pm._irqs_disabled = true;
4809 }
4810
4811 /* Restore interrupts so we can recover from runtime PM. */
4812 void intel_runtime_pm_restore_interrupts(struct drm_device *dev)
4813 {
4814         struct drm_i915_private *dev_priv = dev->dev_private;
4815
4816         dev_priv->pm._irqs_disabled = false;
4817         dev->driver->irq_preinstall(dev);
4818         dev->driver->irq_postinstall(dev);
4819 }