drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262         POSTING_READ(GTIMR);
 263 }
 264
 265 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 266 {
 267         ilk_update_gt_irq(dev_priv, mask, mask);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         spin_lock_irq(&dev_priv->irq_lock);
 354
 355         WARN_ON(dev_priv->rps.pm_iir);
 356         WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 357         dev_priv->rps.interrupts_enabled = true;
 358         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 359                                 dev_priv->pm_rps_events);
 360         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 361
 362         spin_unlock_irq(&dev_priv->irq_lock);
 363 }
 364
 365 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 366 {
 367         return (mask & ~dev_priv->rps.pm_intr_keep);
 368 }
 369
 370 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 371 {
 372         spin_lock_irq(&dev_priv->irq_lock);
 373         dev_priv->rps.interrupts_enabled = false;
 374         spin_unlock_irq(&dev_priv->irq_lock);
 375
 376         cancel_work_sync(&dev_priv->rps.work);
 377
 378         spin_lock_irq(&dev_priv->irq_lock);
 379
 380         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
 381
 382         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 383         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 384                                 ~dev_priv->pm_rps_events);
 385
 386         spin_unlock_irq(&dev_priv->irq_lock);
 387
 388         synchronize_irq(dev_priv->dev->irq);
 389 }
 390
 391 /**
 392  * bdw_update_port_irq - update DE port interrupt
 393  * @dev_priv: driver private
 394  * @interrupt_mask: mask of interrupt bits to update
 395  * @enabled_irq_mask: mask of interrupt bits to enable
 396  */
 397 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 398                                 uint32_t interrupt_mask,
 399                                 uint32_t enabled_irq_mask)
 400 {
 401         uint32_t new_val;
 402         uint32_t old_val;
 403
 404         assert_spin_locked(&dev_priv->irq_lock);
 405
 406         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 407
 408         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 409                 return;
 410
 411         old_val = I915_READ(GEN8_DE_PORT_IMR);
 412
 413         new_val = old_val;
 414         new_val &= ~interrupt_mask;
 415         new_val |= (~enabled_irq_mask & interrupt_mask);
 416
 417         if (new_val != old_val) {
 418                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 419                 POSTING_READ(GEN8_DE_PORT_IMR);
 420         }
 421 }
 422
 423 /**
 424  * bdw_update_pipe_irq - update DE pipe interrupt
 425  * @dev_priv: driver private
 426  * @pipe: pipe whose interrupt to update
 427  * @interrupt_mask: mask of interrupt bits to update
 428  * @enabled_irq_mask: mask of interrupt bits to enable
 429  */
 430 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 431                          enum pipe pipe,
 432                          uint32_t interrupt_mask,
 433                          uint32_t enabled_irq_mask)
 434 {
 435         uint32_t new_val;
 436
 437         assert_spin_locked(&dev_priv->irq_lock);
 438
 439         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 440
 441         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 442                 return;
 443
 444         new_val = dev_priv->de_irq_mask[pipe];
 445         new_val &= ~interrupt_mask;
 446         new_val |= (~enabled_irq_mask & interrupt_mask);
 447
 448         if (new_val != dev_priv->de_irq_mask[pipe]) {
 449                 dev_priv->de_irq_mask[pipe] = new_val;
 450                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 451                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 452         }
 453 }
 454
 455 /**
 456  * ibx_display_interrupt_update - update SDEIMR
 457  * @dev_priv: driver private
 458  * @interrupt_mask: mask of interrupt bits to update
 459  * @enabled_irq_mask: mask of interrupt bits to enable
 460  */
 461 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 462                                   uint32_t interrupt_mask,
 463                                   uint32_t enabled_irq_mask)
 464 {
 465         uint32_t sdeimr = I915_READ(SDEIMR);
 466         sdeimr &= ~interrupt_mask;
 467         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 468
 469         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 470
 471         assert_spin_locked(&dev_priv->irq_lock);
 472
 473         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 474                 return;
 475
 476         I915_WRITE(SDEIMR, sdeimr);
 477         POSTING_READ(SDEIMR);
 478 }
 479
 480 static void
 481 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 482                        u32 enable_mask, u32 status_mask)
 483 {
 484         i915_reg_t reg = PIPESTAT(pipe);
 485         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 486
 487         assert_spin_locked(&dev_priv->irq_lock);
 488         WARN_ON(!intel_irqs_enabled(dev_priv));
 489
 490         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 491                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 492                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 493                       pipe_name(pipe), enable_mask, status_mask))
 494                 return;
 495
 496         if ((pipestat & enable_mask) == enable_mask)
 497                 return;
 498
 499         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 500
 501         /* Enable the interrupt, clear any pending status */
 502         pipestat |= enable_mask | status_mask;
 503         I915_WRITE(reg, pipestat);
 504         POSTING_READ(reg);
 505 }
 506
 507 static void
 508 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 509                         u32 enable_mask, u32 status_mask)
 510 {
 511         i915_reg_t reg = PIPESTAT(pipe);
 512         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 513
 514         assert_spin_locked(&dev_priv->irq_lock);
 515         WARN_ON(!intel_irqs_enabled(dev_priv));
 516
 517         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 518                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 519                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 520                       pipe_name(pipe), enable_mask, status_mask))
 521                 return;
 522
 523         if ((pipestat & enable_mask) == 0)
 524                 return;
 525
 526         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 527
 528         pipestat &= ~enable_mask;
 529         I915_WRITE(reg, pipestat);
 530         POSTING_READ(reg);
 531 }
 532
 533 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 534 {
 535         u32 enable_mask = status_mask << 16;
 536
 537         /*
 538          * On pipe A we don't support the PSR interrupt yet,
 539          * on pipe B and C the same bit MBZ.
 540          */
 541         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 542                 return 0;
 543         /*
 544          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 545          * A the same bit is for perf counters which we don't use either.
 546          */
 547         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 548                 return 0;
 549
 550         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 551                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 552                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 553         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 554                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 555         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 556                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 557
 558         return enable_mask;
 559 }
 560
 561 void
 562 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 563                      u32 status_mask)
 564 {
 565         u32 enable_mask;
 566
 567         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 568                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 569                                                            status_mask);
 570         else
 571                 enable_mask = status_mask << 16;
 572         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 573 }
 574
 575 void
 576 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 577                       u32 status_mask)
 578 {
 579         u32 enable_mask;
 580
 581         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 582                 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
 583                                                            status_mask);
 584         else
 585                 enable_mask = status_mask << 16;
 586         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 587 }
 588
 589 /**
 590  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 591  * @dev_priv: i915 device private
 592  */
 593 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 594 {
 595         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 596                 return;
 597
 598         spin_lock_irq(&dev_priv->irq_lock);
 599
 600         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 601         if (INTEL_GEN(dev_priv) >= 4)
 602                 i915_enable_pipestat(dev_priv, PIPE_A,
 603                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 604
 605         spin_unlock_irq(&dev_priv->irq_lock);
 606 }
 607
 608 /*
 609  * This timing diagram depicts the video signal in and
 610  * around the vertical blanking period.
 611  *
 612  * Assumptions about the fictitious mode used in this example:
 613  *  vblank_start >= 3
 614  *  vsync_start = vblank_start + 1
 615  *  vsync_end = vblank_start + 2
 616  *  vtotal = vblank_start + 3
 617  *
 618  *           start of vblank:
 619  *           latch double buffered registers
 620  *           increment frame counter (ctg+)
 621  *           generate start of vblank interrupt (gen4+)
 622  *           |
 623  *           |          frame start:
 624  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 625  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 626  *           |          |
 627  *           |          |  start of vsync:
 628  *           |          |  generate vsync interrupt
 629  *           |          |  |
 630  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 631  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 632  * ----va---> <-----------------vb--------------------> <--------va-------------
 633  *       |          |       <----vs----->                     |
 634  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 635  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 636  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 637  *       |          |                                         |
 638  *       last visible pixel                                   first visible pixel
 639  *                  |                                         increment frame counter (gen3/4)
 640  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 641  *
 642  * x  = horizontal active
 643  * _  = horizontal blanking
 644  * hs = horizontal sync
 645  * va = vertical active
 646  * vb = vertical blanking
 647  * vs = vertical sync
 648  * vbs = vblank_start (number)
 649  *
 650  * Summary:
 651  * - most events happen at the start of horizontal sync
 652  * - frame start happens at the start of horizontal blank, 1-4 lines
 653  *   (depending on PIPECONF settings) after the start of vblank
 654  * - gen3/4 pixel and frame counter are synchronized with the start
 655  *   of horizontal active on the first line of vertical active
 656  */
 657
 658 static u32 i8xx_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 659 {
 660         /* Gen2 doesn't have a hardware frame counter */
 661         return 0;
 662 }
 663
 664 /* Called from drm generic code, passed a 'crtc', which
 665  * we use as a pipe index
 666  */
 667 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 668 {
 669         struct drm_i915_private *dev_priv = dev->dev_private;
 670         i915_reg_t high_frame, low_frame;
 671         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 672         struct intel_crtc *intel_crtc =
 673                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 674         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 675
 676         htotal = mode->crtc_htotal;
 677         hsync_start = mode->crtc_hsync_start;
 678         vbl_start = mode->crtc_vblank_start;
 679         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 680                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 681
 682         /* Convert to pixel count */
 683         vbl_start *= htotal;
 684
 685         /* Start of vblank event occurs at start of hsync */
 686         vbl_start -= htotal - hsync_start;
 687
 688         high_frame = PIPEFRAME(pipe);
 689         low_frame = PIPEFRAMEPIXEL(pipe);
 690
 691         /*
 692          * High & low register fields aren't synchronized, so make sure
 693          * we get a low value that's stable across two reads of the high
 694          * register.
 695          */
 696         do {
 697                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 698                 low   = I915_READ(low_frame);
 699                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 700         } while (high1 != high2);
 701
 702         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 703         pixel = low & PIPE_PIXEL_MASK;
 704         low >>= PIPE_FRAME_LOW_SHIFT;
 705
 706         /*
 707          * The frame counter increments at beginning of active.
 708          * Cook up a vblank counter by also checking the pixel
 709          * counter against vblank start.
 710          */
 711         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 712 }
 713
 714 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 715 {
 716         struct drm_i915_private *dev_priv = dev->dev_private;
 717
 718         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 719 }
 720
 721 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 722 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 723 {
 724         struct drm_device *dev = crtc->base.dev;
 725         struct drm_i915_private *dev_priv = dev->dev_private;
 726         const struct drm_display_mode *mode = &crtc->base.hwmode;
 727         enum pipe pipe = crtc->pipe;
 728         int position, vtotal;
 729
 730         vtotal = mode->crtc_vtotal;
 731         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 732                 vtotal /= 2;
 733
 734         if (IS_GEN2(dev_priv))
 735                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 736         else
 737                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 738
 739         /*
 740          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 741          * read it just before the start of vblank.  So try it again
 742          * so we don't accidentally end up spanning a vblank frame
 743          * increment, causing the pipe_update_end() code to squak at us.
 744          *
 745          * The nature of this problem means we can't simply check the ISR
 746          * bit and return the vblank start value; nor can we use the scanline
 747          * debug register in the transcoder as it appears to have the same
 748          * problem.  We may need to extend this to include other platforms,
 749          * but so far testing only shows the problem on HSW.
 750          */
 751         if (HAS_DDI(dev_priv) && !position) {
 752                 int i, temp;
 753
 754                 for (i = 0; i < 100; i++) {
 755                         udelay(1);
 756                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 757                                 DSL_LINEMASK_GEN3;
 758                         if (temp != position) {
 759                                 position = temp;
 760                                 break;
 761                         }
 762                 }
 763         }
 764
 765         /*
 766          * See update_scanline_offset() for the details on the
 767          * scanline_offset adjustment.
 768          */
 769         return (position + crtc->scanline_offset) % vtotal;
 770 }
 771
 772 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 773                                     unsigned int flags, int *vpos, int *hpos,
 774                                     ktime_t *stime, ktime_t *etime,
 775                                     const struct drm_display_mode *mode)
 776 {
 777         struct drm_i915_private *dev_priv = dev->dev_private;
 778         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 779         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 780         int position;
 781         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 782         bool in_vbl = true;
 783         int ret = 0;
 784         unsigned long irqflags;
 785
 786         if (WARN_ON(!mode->crtc_clock)) {
 787                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 788                                  "pipe %c\n", pipe_name(pipe));
 789                 return 0;
 790         }
 791
 792         htotal = mode->crtc_htotal;
 793         hsync_start = mode->crtc_hsync_start;
 794         vtotal = mode->crtc_vtotal;
 795         vbl_start = mode->crtc_vblank_start;
 796         vbl_end = mode->crtc_vblank_end;
 797
 798         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 799                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 800                 vbl_end /= 2;
 801                 vtotal /= 2;
 802         }
 803
 804         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 805
 806         /*
 807          * Lock uncore.lock, as we will do multiple timing critical raw
 808          * register reads, potentially with preemption disabled, so the
 809          * following code must not block on uncore.lock.
 810          */
 811         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 812
 813         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 814
 815         /* Get optional system timestamp before query. */
 816         if (stime)
 817                 *stime = ktime_get();
 818
 819         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 820                 /* No obvious pixelcount register. Only query vertical
 821                  * scanout position from Display scan line register.
 822                  */
 823                 position = __intel_get_crtc_scanline(intel_crtc);
 824         } else {
 825                 /* Have access to pixelcount since start of frame.
 826                  * We can split this into vertical and horizontal
 827                  * scanout position.
 828                  */
 829                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 830
 831                 /* convert to pixel counts */
 832                 vbl_start *= htotal;
 833                 vbl_end *= htotal;
 834                 vtotal *= htotal;
 835
 836                 /*
 837                  * In interlaced modes, the pixel counter counts all pixels,
 838                  * so one field will have htotal more pixels. In order to avoid
 839                  * the reported position from jumping backwards when the pixel
 840                  * counter is beyond the length of the shorter field, just
 841                  * clamp the position the length of the shorter field. This
 842                  * matches how the scanline counter based position works since
 843                  * the scanline counter doesn't count the two half lines.
 844                  */
 845                 if (position >= vtotal)
 846                         position = vtotal - 1;
 847
 848                 /*
 849                  * Start of vblank interrupt is triggered at start of hsync,
 850                  * just prior to the first active line of vblank. However we
 851                  * consider lines to start at the leading edge of horizontal
 852                  * active. So, should we get here before we've crossed into
 853                  * the horizontal active of the first line in vblank, we would
 854                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 855                  * always add htotal-hsync_start to the current pixel position.
 856                  */
 857                 position = (position + htotal - hsync_start) % vtotal;
 858         }
 859
 860         /* Get optional system timestamp after query. */
 861         if (etime)
 862                 *etime = ktime_get();
 863
 864         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 865
 866         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 867
 868         in_vbl = position >= vbl_start && position < vbl_end;
 869
 870         /*
 871          * While in vblank, position will be negative
 872          * counting up towards 0 at vbl_end. And outside
 873          * vblank, position will be positive counting
 874          * up since vbl_end.
 875          */
 876         if (position >= vbl_start)
 877                 position -= vbl_end;
 878         else
 879                 position += vtotal - vbl_end;
 880
 881         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 882                 *vpos = position;
 883                 *hpos = 0;
 884         } else {
 885                 *vpos = position / htotal;
 886                 *hpos = position - (*vpos * htotal);
 887         }
 888
 889         /* In vblank? */
 890         if (in_vbl)
 891                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 892
 893         return ret;
 894 }
 895
 896 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 897 {
 898         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
 899         unsigned long irqflags;
 900         int position;
 901
 902         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 903         position = __intel_get_crtc_scanline(crtc);
 904         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 905
 906         return position;
 907 }
 908
 909 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 910                               int *max_error,
 911                               struct timeval *vblank_time,
 912                               unsigned flags)
 913 {
 914         struct drm_crtc *crtc;
 915
 916         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 917                 DRM_ERROR("Invalid crtc %u\n", pipe);
 918                 return -EINVAL;
 919         }
 920
 921         /* Get drm_crtc to timestamp: */
 922         crtc = intel_get_crtc_for_pipe(dev, pipe);
 923         if (crtc == NULL) {
 924                 DRM_ERROR("Invalid crtc %u\n", pipe);
 925                 return -EINVAL;
 926         }
 927
 928         if (!crtc->hwmode.crtc_clock) {
 929                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 930                 return -EBUSY;
 931         }
 932
 933         /* Helper routine in DRM core does all the work: */
 934         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 935                                                      vblank_time, flags,
 936                                                      &crtc->hwmode);
 937 }
 938
 939 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 940 {
 941         u32 busy_up, busy_down, max_avg, min_avg;
 942         u8 new_delay;
 943
 944         spin_lock(&mchdev_lock);
 945
 946         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 947
 948         new_delay = dev_priv->ips.cur_delay;
 949
 950         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 951         busy_up = I915_READ(RCPREVBSYTUPAVG);
 952         busy_down = I915_READ(RCPREVBSYTDNAVG);
 953         max_avg = I915_READ(RCBMAXAVG);
 954         min_avg = I915_READ(RCBMINAVG);
 955
 956         /* Handle RCS change request from hw */
 957         if (busy_up > max_avg) {
 958                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 959                         new_delay = dev_priv->ips.cur_delay - 1;
 960                 if (new_delay < dev_priv->ips.max_delay)
 961                         new_delay = dev_priv->ips.max_delay;
 962         } else if (busy_down < min_avg) {
 963                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 964                         new_delay = dev_priv->ips.cur_delay + 1;
 965                 if (new_delay > dev_priv->ips.min_delay)
 966                         new_delay = dev_priv->ips.min_delay;
 967         }
 968
 969         if (ironlake_set_drps(dev_priv, new_delay))
 970                 dev_priv->ips.cur_delay = new_delay;
 971
 972         spin_unlock(&mchdev_lock);
 973
 974         return;
 975 }
 976
 977 static void notify_ring(struct intel_engine_cs *engine)
 978 {
 979         if (intel_engine_wakeup(engine)) {
 980                 trace_i915_gem_request_notify(engine);
 981                 engine->user_interrupts++;
 982         }
 983 }
 984
 985 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 986                         struct intel_rps_ei *ei)
 987 {
 988         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 989         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 990         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 991 }
 992
 993 static bool vlv_c0_above(struct drm_i915_private *dev_priv,
 994                          const struct intel_rps_ei *old,
 995                          const struct intel_rps_ei *now,
 996                          int threshold)
 997 {
 998         u64 time, c0;
 999         unsigned int mul = 100;
1000
1001         if (old->cz_clock == 0)
1002                 return false;
1003
1004         if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1005                 mul <<= 8;
1006
1007         time = now->cz_clock - old->cz_clock;
1008         time *= threshold * dev_priv->czclk_freq;
1009
1010         /* Workload can be split between render + media, e.g. SwapBuffers
1011          * being blitted in X after being rendered in mesa. To account for
1012          * this we need to combine both engines into our activity counter.
1013          */
1014         c0 = now->render_c0 - old->render_c0;
1015         c0 += now->media_c0 - old->media_c0;
1016         c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
1017
1018         return c0 >= time;
1019 }
1020
1021 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1022 {
1023         vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1024         dev_priv->rps.up_ei = dev_priv->rps.down_ei;
1025 }
1026
1027 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1028 {
1029         struct intel_rps_ei now;
1030         u32 events = 0;
1031
1032         if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
1033                 return 0;
1034
1035         vlv_c0_read(dev_priv, &now);
1036         if (now.cz_clock == 0)
1037                 return 0;
1038
1039         if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1040                 if (!vlv_c0_above(dev_priv,
1041                                   &dev_priv->rps.down_ei, &now,
1042                                   dev_priv->rps.down_threshold))
1043                         events |= GEN6_PM_RP_DOWN_THRESHOLD;
1044                 dev_priv->rps.down_ei = now;
1045         }
1046
1047         if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1048                 if (vlv_c0_above(dev_priv,
1049                                  &dev_priv->rps.up_ei, &now,
1050                                  dev_priv->rps.up_threshold))
1051                         events |= GEN6_PM_RP_UP_THRESHOLD;
1052                 dev_priv->rps.up_ei = now;
1053         }
1054
1055         return events;
1056 }
1057
1058 static bool any_waiters(struct drm_i915_private *dev_priv)
1059 {
1060         struct intel_engine_cs *engine;
1061
1062         for_each_engine(engine, dev_priv)
1063                 if (intel_engine_has_waiter(engine))
1064                         return true;
1065
1066         return false;
1067 }
1068
1069 static void gen6_pm_rps_work(struct work_struct *work)
1070 {
1071         struct drm_i915_private *dev_priv =
1072                 container_of(work, struct drm_i915_private, rps.work);
1073         bool client_boost;
1074         int new_delay, adj, min, max;
1075         u32 pm_iir;
1076
1077         spin_lock_irq(&dev_priv->irq_lock);
1078         /* Speed up work cancelation during disabling rps interrupts. */
1079         if (!dev_priv->rps.interrupts_enabled) {
1080                 spin_unlock_irq(&dev_priv->irq_lock);
1081                 return;
1082         }
1083
1084         /*
1085          * The RPS work is synced during runtime suspend, we don't require a
1086          * wakeref. TODO: instead of disabling the asserts make sure that we
1087          * always hold an RPM reference while the work is running.
1088          */
1089         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1090
1091         pm_iir = dev_priv->rps.pm_iir;
1092         dev_priv->rps.pm_iir = 0;
1093         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1094         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1095         client_boost = dev_priv->rps.client_boost;
1096         dev_priv->rps.client_boost = false;
1097         spin_unlock_irq(&dev_priv->irq_lock);
1098
1099         /* Make sure we didn't queue anything we're not going to process. */
1100         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1101
1102         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1103                 goto out;
1104
1105         mutex_lock(&dev_priv->rps.hw_lock);
1106
1107         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1108
1109         adj = dev_priv->rps.last_adj;
1110         new_delay = dev_priv->rps.cur_freq;
1111         min = dev_priv->rps.min_freq_softlimit;
1112         max = dev_priv->rps.max_freq_softlimit;
1113
1114         if (client_boost) {
1115                 new_delay = dev_priv->rps.max_freq_softlimit;
1116                 adj = 0;
1117         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1118                 if (adj > 0)
1119                         adj *= 2;
1120                 else /* CHV needs even encode values */
1121                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1122                 /*
1123                  * For better performance, jump directly
1124                  * to RPe if we're below it.
1125                  */
1126                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1127                         new_delay = dev_priv->rps.efficient_freq;
1128                         adj = 0;
1129                 }
1130         } else if (any_waiters(dev_priv)) {
1131                 adj = 0;
1132         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1133                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1134                         new_delay = dev_priv->rps.efficient_freq;
1135                 else
1136                         new_delay = dev_priv->rps.min_freq_softlimit;
1137                 adj = 0;
1138         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1139                 if (adj < 0)
1140                         adj *= 2;
1141                 else /* CHV needs even encode values */
1142                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1143         } else { /* unknown event */
1144                 adj = 0;
1145         }
1146
1147         dev_priv->rps.last_adj = adj;
1148
1149         /* sysfs frequency interfaces may have snuck in while servicing the
1150          * interrupt
1151          */
1152         new_delay += adj;
1153         new_delay = clamp_t(int, new_delay, min, max);
1154
1155         intel_set_rps(dev_priv, new_delay);
1156
1157         mutex_unlock(&dev_priv->rps.hw_lock);
1158 out:
1159         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
1160 }
1161
1162
1163 /**
1164  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1165  * occurred.
1166  * @work: workqueue struct
1167  *
1168  * Doesn't actually do anything except notify userspace. As a consequence of
1169  * this event, userspace should try to remap the bad rows since statistically
1170  * it is likely the same row is more likely to go bad again.
1171  */
1172 static void ivybridge_parity_work(struct work_struct *work)
1173 {
1174         struct drm_i915_private *dev_priv =
1175                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1176         u32 error_status, row, bank, subbank;
1177         char *parity_event[6];
1178         uint32_t misccpctl;
1179         uint8_t slice = 0;
1180
1181         /* We must turn off DOP level clock gating to access the L3 registers.
1182          * In order to prevent a get/put style interface, acquire struct mutex
1183          * any time we access those registers.
1184          */
1185         mutex_lock(&dev_priv->dev->struct_mutex);
1186
1187         /* If we've screwed up tracking, just let the interrupt fire again */
1188         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1189                 goto out;
1190
1191         misccpctl = I915_READ(GEN7_MISCCPCTL);
1192         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1193         POSTING_READ(GEN7_MISCCPCTL);
1194
1195         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1196                 i915_reg_t reg;
1197
1198                 slice--;
1199                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1200                         break;
1201
1202                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1203
1204                 reg = GEN7_L3CDERRST1(slice);
1205
1206                 error_status = I915_READ(reg);
1207                 row = GEN7_PARITY_ERROR_ROW(error_status);
1208                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1209                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1210
1211                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1212                 POSTING_READ(reg);
1213
1214                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1215                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1216                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1217                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1218                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1219                 parity_event[5] = NULL;
1220
1221                 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
1222                                    KOBJ_CHANGE, parity_event);
1223
1224                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1225                           slice, row, bank, subbank);
1226
1227                 kfree(parity_event[4]);
1228                 kfree(parity_event[3]);
1229                 kfree(parity_event[2]);
1230                 kfree(parity_event[1]);
1231         }
1232
1233         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1234
1235 out:
1236         WARN_ON(dev_priv->l3_parity.which_slice);
1237         spin_lock_irq(&dev_priv->irq_lock);
1238         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1239         spin_unlock_irq(&dev_priv->irq_lock);
1240
1241         mutex_unlock(&dev_priv->dev->struct_mutex);
1242 }
1243
1244 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1245                                                u32 iir)
1246 {
1247         if (!HAS_L3_DPF(dev_priv))
1248                 return;
1249
1250         spin_lock(&dev_priv->irq_lock);
1251         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1252         spin_unlock(&dev_priv->irq_lock);
1253
1254         iir &= GT_PARITY_ERROR(dev_priv);
1255         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1256                 dev_priv->l3_parity.which_slice |= 1 << 1;
1257
1258         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1259                 dev_priv->l3_parity.which_slice |= 1 << 0;
1260
1261         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1262 }
1263
1264 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1265                                u32 gt_iir)
1266 {
1267         if (gt_iir &
1268             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1269                 notify_ring(&dev_priv->engine[RCS]);
1270         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1271                 notify_ring(&dev_priv->engine[VCS]);
1272 }
1273
1274 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1275                                u32 gt_iir)
1276 {
1277
1278         if (gt_iir &
1279             (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
1280                 notify_ring(&dev_priv->engine[RCS]);
1281         if (gt_iir & GT_BSD_USER_INTERRUPT)
1282                 notify_ring(&dev_priv->engine[VCS]);
1283         if (gt_iir & GT_BLT_USER_INTERRUPT)
1284                 notify_ring(&dev_priv->engine[BCS]);
1285
1286         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1287                       GT_BSD_CS_ERROR_INTERRUPT |
1288                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1289                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1290
1291         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1292                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1293 }
1294
1295 static __always_inline void
1296 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1297 {
1298         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1299                 notify_ring(engine);
1300         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1301                 tasklet_schedule(&engine->irq_tasklet);
1302 }
1303
1304 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1305                                    u32 master_ctl,
1306                                    u32 gt_iir[4])
1307 {
1308         irqreturn_t ret = IRQ_NONE;
1309
1310         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1311                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1312                 if (gt_iir[0]) {
1313                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1314                         ret = IRQ_HANDLED;
1315                 } else
1316                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1317         }
1318
1319         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1320                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1321                 if (gt_iir[1]) {
1322                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1323                         ret = IRQ_HANDLED;
1324                 } else
1325                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1326         }
1327
1328         if (master_ctl & GEN8_GT_VECS_IRQ) {
1329                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1330                 if (gt_iir[3]) {
1331                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1332                         ret = IRQ_HANDLED;
1333                 } else
1334                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1335         }
1336
1337         if (master_ctl & GEN8_GT_PM_IRQ) {
1338                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1339                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1340                         I915_WRITE_FW(GEN8_GT_IIR(2),
1341                                       gt_iir[2] & dev_priv->pm_rps_events);
1342                         ret = IRQ_HANDLED;
1343                 } else
1344                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1345         }
1346
1347         return ret;
1348 }
1349
1350 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1351                                 u32 gt_iir[4])
1352 {
1353         if (gt_iir[0]) {
1354                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1355                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1356                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1357                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1358         }
1359
1360         if (gt_iir[1]) {
1361                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1362                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1363                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1364                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1365         }
1366
1367         if (gt_iir[3])
1368                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1369                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1370
1371         if (gt_iir[2] & dev_priv->pm_rps_events)
1372                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1373 }
1374
1375 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1376 {
1377         switch (port) {
1378         case PORT_A:
1379                 return val & PORTA_HOTPLUG_LONG_DETECT;
1380         case PORT_B:
1381                 return val & PORTB_HOTPLUG_LONG_DETECT;
1382         case PORT_C:
1383                 return val & PORTC_HOTPLUG_LONG_DETECT;
1384         default:
1385                 return false;
1386         }
1387 }
1388
1389 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1390 {
1391         switch (port) {
1392         case PORT_E:
1393                 return val & PORTE_HOTPLUG_LONG_DETECT;
1394         default:
1395                 return false;
1396         }
1397 }
1398
1399 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1400 {
1401         switch (port) {
1402         case PORT_A:
1403                 return val & PORTA_HOTPLUG_LONG_DETECT;
1404         case PORT_B:
1405                 return val & PORTB_HOTPLUG_LONG_DETECT;
1406         case PORT_C:
1407                 return val & PORTC_HOTPLUG_LONG_DETECT;
1408         case PORT_D:
1409                 return val & PORTD_HOTPLUG_LONG_DETECT;
1410         default:
1411                 return false;
1412         }
1413 }
1414
1415 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1416 {
1417         switch (port) {
1418         case PORT_A:
1419                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1420         default:
1421                 return false;
1422         }
1423 }
1424
1425 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1426 {
1427         switch (port) {
1428         case PORT_B:
1429                 return val & PORTB_HOTPLUG_LONG_DETECT;
1430         case PORT_C:
1431                 return val & PORTC_HOTPLUG_LONG_DETECT;
1432         case PORT_D:
1433                 return val & PORTD_HOTPLUG_LONG_DETECT;
1434         default:
1435                 return false;
1436         }
1437 }
1438
1439 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1440 {
1441         switch (port) {
1442         case PORT_B:
1443                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1444         case PORT_C:
1445                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1446         case PORT_D:
1447                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1448         default:
1449                 return false;
1450         }
1451 }
1452
1453 /*
1454  * Get a bit mask of pins that have triggered, and which ones may be long.
1455  * This can be called multiple times with the same masks to accumulate
1456  * hotplug detection results from several registers.
1457  *
1458  * Note that the caller is expected to zero out the masks initially.
1459  */
1460 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1461                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1462                              const u32 hpd[HPD_NUM_PINS],
1463                              bool long_pulse_detect(enum port port, u32 val))
1464 {
1465         enum port port;
1466         int i;
1467
1468         for_each_hpd_pin(i) {
1469                 if ((hpd[i] & hotplug_trigger) == 0)
1470                         continue;
1471
1472                 *pin_mask |= BIT(i);
1473
1474                 if (!intel_hpd_pin_to_port(i, &port))
1475                         continue;
1476
1477                 if (long_pulse_detect(port, dig_hotplug_reg))
1478                         *long_mask |= BIT(i);
1479         }
1480
1481         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1482                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1483
1484 }
1485
1486 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1487 {
1488         wake_up_all(&dev_priv->gmbus_wait_queue);
1489 }
1490
1491 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1492 {
1493         wake_up_all(&dev_priv->gmbus_wait_queue);
1494 }
1495
1496 #if defined(CONFIG_DEBUG_FS)
1497 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1498                                          enum pipe pipe,
1499                                          uint32_t crc0, uint32_t crc1,
1500                                          uint32_t crc2, uint32_t crc3,
1501                                          uint32_t crc4)
1502 {
1503         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1504         struct intel_pipe_crc_entry *entry;
1505         int head, tail;
1506
1507         spin_lock(&pipe_crc->lock);
1508
1509         if (!pipe_crc->entries) {
1510                 spin_unlock(&pipe_crc->lock);
1511                 DRM_DEBUG_KMS("spurious interrupt\n");
1512                 return;
1513         }
1514
1515         head = pipe_crc->head;
1516         tail = pipe_crc->tail;
1517
1518         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1519                 spin_unlock(&pipe_crc->lock);
1520                 DRM_ERROR("CRC buffer overflowing\n");
1521                 return;
1522         }
1523
1524         entry = &pipe_crc->entries[head];
1525
1526         entry->frame = dev_priv->dev->driver->get_vblank_counter(dev_priv->dev,
1527                                                                  pipe);
1528         entry->crc[0] = crc0;
1529         entry->crc[1] = crc1;
1530         entry->crc[2] = crc2;
1531         entry->crc[3] = crc3;
1532         entry->crc[4] = crc4;
1533
1534         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1535         pipe_crc->head = head;
1536
1537         spin_unlock(&pipe_crc->lock);
1538
1539         wake_up_interruptible(&pipe_crc->wq);
1540 }
1541 #else
1542 static inline void
1543 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1544                              enum pipe pipe,
1545                              uint32_t crc0, uint32_t crc1,
1546                              uint32_t crc2, uint32_t crc3,
1547                              uint32_t crc4) {}
1548 #endif
1549
1550
1551 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1552                                      enum pipe pipe)
1553 {
1554         display_pipe_crc_irq_handler(dev_priv, pipe,
1555                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1556                                      0, 0, 0, 0);
1557 }
1558
1559 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1560                                      enum pipe pipe)
1561 {
1562         display_pipe_crc_irq_handler(dev_priv, pipe,
1563                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1564                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1565                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1566                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1567                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1568 }
1569
1570 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1571                                       enum pipe pipe)
1572 {
1573         uint32_t res1, res2;
1574
1575         if (INTEL_GEN(dev_priv) >= 3)
1576                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1577         else
1578                 res1 = 0;
1579
1580         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1581                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1582         else
1583                 res2 = 0;
1584
1585         display_pipe_crc_irq_handler(dev_priv, pipe,
1586                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1587                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1588                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1589                                      res1, res2);
1590 }
1591
1592 /* The RPS events need forcewake, so we add them to a work queue and mask their
1593  * IMR bits until the work is done. Other interrupts can be processed without
1594  * the work queue. */
1595 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1596 {
1597         if (pm_iir & dev_priv->pm_rps_events) {
1598                 spin_lock(&dev_priv->irq_lock);
1599                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1600                 if (dev_priv->rps.interrupts_enabled) {
1601                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1602                         queue_work(dev_priv->wq, &dev_priv->rps.work);
1603                 }
1604                 spin_unlock(&dev_priv->irq_lock);
1605         }
1606
1607         if (INTEL_INFO(dev_priv)->gen >= 8)
1608                 return;
1609
1610         if (HAS_VEBOX(dev_priv)) {
1611                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1612                         notify_ring(&dev_priv->engine[VECS]);
1613
1614                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1615                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1616         }
1617 }
1618
1619 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1620                                      enum pipe pipe)
1621 {
1622         bool ret;
1623
1624         ret = drm_handle_vblank(dev_priv->dev, pipe);
1625         if (ret)
1626                 intel_finish_page_flip_mmio(dev_priv, pipe);
1627
1628         return ret;
1629 }
1630
1631 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1632                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1633 {
1634         int pipe;
1635
1636         spin_lock(&dev_priv->irq_lock);
1637
1638         if (!dev_priv->display_irqs_enabled) {
1639                 spin_unlock(&dev_priv->irq_lock);
1640                 return;
1641         }
1642
1643         for_each_pipe(dev_priv, pipe) {
1644                 i915_reg_t reg;
1645                 u32 mask, iir_bit = 0;
1646
1647                 /*
1648                  * PIPESTAT bits get signalled even when the interrupt is
1649                  * disabled with the mask bits, and some of the status bits do
1650                  * not generate interrupts at all (like the underrun bit). Hence
1651                  * we need to be careful that we only handle what we want to
1652                  * handle.
1653                  */
1654
1655                 /* fifo underruns are filterered in the underrun handler. */
1656                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1657
1658                 switch (pipe) {
1659                 case PIPE_A:
1660                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1661                         break;
1662                 case PIPE_B:
1663                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1664                         break;
1665                 case PIPE_C:
1666                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1667                         break;
1668                 }
1669                 if (iir & iir_bit)
1670                         mask |= dev_priv->pipestat_irq_mask[pipe];
1671
1672                 if (!mask)
1673                         continue;
1674
1675                 reg = PIPESTAT(pipe);
1676                 mask |= PIPESTAT_INT_ENABLE_MASK;
1677                 pipe_stats[pipe] = I915_READ(reg) & mask;
1678
1679                 /*
1680                  * Clear the PIPE*STAT regs before the IIR
1681                  */
1682                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1683                                         PIPESTAT_INT_STATUS_MASK))
1684                         I915_WRITE(reg, pipe_stats[pipe]);
1685         }
1686         spin_unlock(&dev_priv->irq_lock);
1687 }
1688
1689 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1690                                             u32 pipe_stats[I915_MAX_PIPES])
1691 {
1692         enum pipe pipe;
1693
1694         for_each_pipe(dev_priv, pipe) {
1695                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1696                     intel_pipe_handle_vblank(dev_priv, pipe))
1697                         intel_check_page_flip(dev_priv, pipe);
1698
1699                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1700                         intel_finish_page_flip_cs(dev_priv, pipe);
1701
1702                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1703                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1704
1705                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1706                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1707         }
1708
1709         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1710                 gmbus_irq_handler(dev_priv);
1711 }
1712
1713 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1714 {
1715         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1716
1717         if (hotplug_status)
1718                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1719
1720         return hotplug_status;
1721 }
1722
1723 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1724                                  u32 hotplug_status)
1725 {
1726         u32 pin_mask = 0, long_mask = 0;
1727
1728         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1729             IS_CHERRYVIEW(dev_priv)) {
1730                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1731
1732                 if (hotplug_trigger) {
1733                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1734                                            hotplug_trigger, hpd_status_g4x,
1735                                            i9xx_port_hotplug_long_detect);
1736
1737                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1738                 }
1739
1740                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1741                         dp_aux_irq_handler(dev_priv);
1742         } else {
1743                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1744
1745                 if (hotplug_trigger) {
1746                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1747                                            hotplug_trigger, hpd_status_i915,
1748                                            i9xx_port_hotplug_long_detect);
1749                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1750                 }
1751         }
1752 }
1753
1754 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1755 {
1756         struct drm_device *dev = arg;
1757         struct drm_i915_private *dev_priv = dev->dev_private;
1758         irqreturn_t ret = IRQ_NONE;
1759
1760         if (!intel_irqs_enabled(dev_priv))
1761                 return IRQ_NONE;
1762
1763         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1764         disable_rpm_wakeref_asserts(dev_priv);
1765
1766         do {
1767                 u32 iir, gt_iir, pm_iir;
1768                 u32 pipe_stats[I915_MAX_PIPES] = {};
1769                 u32 hotplug_status = 0;
1770                 u32 ier = 0;
1771
1772                 gt_iir = I915_READ(GTIIR);
1773                 pm_iir = I915_READ(GEN6_PMIIR);
1774                 iir = I915_READ(VLV_IIR);
1775
1776                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1777                         break;
1778
1779                 ret = IRQ_HANDLED;
1780
1781                 /*
1782                  * Theory on interrupt generation, based on empirical evidence:
1783                  *
1784                  * x = ((VLV_IIR & VLV_IER) ||
1785                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1786                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1787                  *
1788                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1789                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1790                  * guarantee the CPU interrupt will be raised again even if we
1791                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1792                  * bits this time around.
1793                  */
1794                 I915_WRITE(VLV_MASTER_IER, 0);
1795                 ier = I915_READ(VLV_IER);
1796                 I915_WRITE(VLV_IER, 0);
1797
1798                 if (gt_iir)
1799                         I915_WRITE(GTIIR, gt_iir);
1800                 if (pm_iir)
1801                         I915_WRITE(GEN6_PMIIR, pm_iir);
1802
1803                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1804                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1805
1806                 /* Call regardless, as some status bits might not be
1807                  * signalled in iir */
1808                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1809
1810                 /*
1811                  * VLV_IIR is single buffered, and reflects the level
1812                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1813                  */
1814                 if (iir)
1815                         I915_WRITE(VLV_IIR, iir);
1816
1817                 I915_WRITE(VLV_IER, ier);
1818                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1819                 POSTING_READ(VLV_MASTER_IER);
1820
1821                 if (gt_iir)
1822                         snb_gt_irq_handler(dev_priv, gt_iir);
1823                 if (pm_iir)
1824                         gen6_rps_irq_handler(dev_priv, pm_iir);
1825
1826                 if (hotplug_status)
1827                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1828
1829                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1830         } while (0);
1831
1832         enable_rpm_wakeref_asserts(dev_priv);
1833
1834         return ret;
1835 }
1836
1837 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1838 {
1839         struct drm_device *dev = arg;
1840         struct drm_i915_private *dev_priv = dev->dev_private;
1841         irqreturn_t ret = IRQ_NONE;
1842
1843         if (!intel_irqs_enabled(dev_priv))
1844                 return IRQ_NONE;
1845
1846         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1847         disable_rpm_wakeref_asserts(dev_priv);
1848
1849         do {
1850                 u32 master_ctl, iir;
1851                 u32 gt_iir[4] = {};
1852                 u32 pipe_stats[I915_MAX_PIPES] = {};
1853                 u32 hotplug_status = 0;
1854                 u32 ier = 0;
1855
1856                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1857                 iir = I915_READ(VLV_IIR);
1858
1859                 if (master_ctl == 0 && iir == 0)
1860                         break;
1861
1862                 ret = IRQ_HANDLED;
1863
1864                 /*
1865                  * Theory on interrupt generation, based on empirical evidence:
1866                  *
1867                  * x = ((VLV_IIR & VLV_IER) ||
1868                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1869                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1870                  *
1871                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1872                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1873                  * guarantee the CPU interrupt will be raised again even if we
1874                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1875                  * bits this time around.
1876                  */
1877                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1878                 ier = I915_READ(VLV_IER);
1879                 I915_WRITE(VLV_IER, 0);
1880
1881                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1882
1883                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1884                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1885
1886                 /* Call regardless, as some status bits might not be
1887                  * signalled in iir */
1888                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1889
1890                 /*
1891                  * VLV_IIR is single buffered, and reflects the level
1892                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1893                  */
1894                 if (iir)
1895                         I915_WRITE(VLV_IIR, iir);
1896
1897                 I915_WRITE(VLV_IER, ier);
1898                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1899                 POSTING_READ(GEN8_MASTER_IRQ);
1900
1901                 gen8_gt_irq_handler(dev_priv, gt_iir);
1902
1903                 if (hotplug_status)
1904                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1905
1906                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1907         } while (0);
1908
1909         enable_rpm_wakeref_asserts(dev_priv);
1910
1911         return ret;
1912 }
1913
1914 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1915                                 u32 hotplug_trigger,
1916                                 const u32 hpd[HPD_NUM_PINS])
1917 {
1918         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1919
1920         /*
1921          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1922          * unless we touch the hotplug register, even if hotplug_trigger is
1923          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1924          * errors.
1925          */
1926         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1927         if (!hotplug_trigger) {
1928                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1929                         PORTD_HOTPLUG_STATUS_MASK |
1930                         PORTC_HOTPLUG_STATUS_MASK |
1931                         PORTB_HOTPLUG_STATUS_MASK;
1932                 dig_hotplug_reg &= ~mask;
1933         }
1934
1935         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1936         if (!hotplug_trigger)
1937                 return;
1938
1939         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1940                            dig_hotplug_reg, hpd,
1941                            pch_port_hotplug_long_detect);
1942
1943         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1944 }
1945
1946 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1947 {
1948         int pipe;
1949         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1950
1951         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1952
1953         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1954                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1955                                SDE_AUDIO_POWER_SHIFT);
1956                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1957                                  port_name(port));
1958         }
1959
1960         if (pch_iir & SDE_AUX_MASK)
1961                 dp_aux_irq_handler(dev_priv);
1962
1963         if (pch_iir & SDE_GMBUS)
1964                 gmbus_irq_handler(dev_priv);
1965
1966         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1967                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1968
1969         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1970                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1971
1972         if (pch_iir & SDE_POISON)
1973                 DRM_ERROR("PCH poison interrupt\n");
1974
1975         if (pch_iir & SDE_FDI_MASK)
1976                 for_each_pipe(dev_priv, pipe)
1977                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1978                                          pipe_name(pipe),
1979                                          I915_READ(FDI_RX_IIR(pipe)));
1980
1981         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1982                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1983
1984         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1985                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1986
1987         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1988                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
1989
1990         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1991                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
1992 }
1993
1994 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1995 {
1996         u32 err_int = I915_READ(GEN7_ERR_INT);
1997         enum pipe pipe;
1998
1999         if (err_int & ERR_INT_POISON)
2000                 DRM_ERROR("Poison interrupt\n");
2001
2002         for_each_pipe(dev_priv, pipe) {
2003                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2004                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2005
2006                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2007                         if (IS_IVYBRIDGE(dev_priv))
2008                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2009                         else
2010                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2011                 }
2012         }
2013
2014         I915_WRITE(GEN7_ERR_INT, err_int);
2015 }
2016
2017 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2018 {
2019         u32 serr_int = I915_READ(SERR_INT);
2020
2021         if (serr_int & SERR_INT_POISON)
2022                 DRM_ERROR("PCH poison interrupt\n");
2023
2024         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2025                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
2026
2027         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2028                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
2029
2030         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2031                 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
2032
2033         I915_WRITE(SERR_INT, serr_int);
2034 }
2035
2036 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2037 {
2038         int pipe;
2039         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2040
2041         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2042
2043         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2044                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2045                                SDE_AUDIO_POWER_SHIFT_CPT);
2046                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2047                                  port_name(port));
2048         }
2049
2050         if (pch_iir & SDE_AUX_MASK_CPT)
2051                 dp_aux_irq_handler(dev_priv);
2052
2053         if (pch_iir & SDE_GMBUS_CPT)
2054                 gmbus_irq_handler(dev_priv);
2055
2056         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2057                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2058
2059         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2060                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2061
2062         if (pch_iir & SDE_FDI_MASK_CPT)
2063                 for_each_pipe(dev_priv, pipe)
2064                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2065                                          pipe_name(pipe),
2066                                          I915_READ(FDI_RX_IIR(pipe)));
2067
2068         if (pch_iir & SDE_ERROR_CPT)
2069                 cpt_serr_int_handler(dev_priv);
2070 }
2071
2072 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2073 {
2074         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2075                 ~SDE_PORTE_HOTPLUG_SPT;
2076         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2077         u32 pin_mask = 0, long_mask = 0;
2078
2079         if (hotplug_trigger) {
2080                 u32 dig_hotplug_reg;
2081
2082                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2083                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2084
2085                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2086                                    dig_hotplug_reg, hpd_spt,
2087                                    spt_port_hotplug_long_detect);
2088         }
2089
2090         if (hotplug2_trigger) {
2091                 u32 dig_hotplug_reg;
2092
2093                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2094                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2095
2096                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2097                                    dig_hotplug_reg, hpd_spt,
2098                                    spt_port_hotplug2_long_detect);
2099         }
2100
2101         if (pin_mask)
2102                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2103
2104         if (pch_iir & SDE_GMBUS_CPT)
2105                 gmbus_irq_handler(dev_priv);
2106 }
2107
2108 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2109                                 u32 hotplug_trigger,
2110                                 const u32 hpd[HPD_NUM_PINS])
2111 {
2112         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2113
2114         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2115         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2116
2117         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2118                            dig_hotplug_reg, hpd,
2119                            ilk_port_hotplug_long_detect);
2120
2121         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2122 }
2123
2124 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2125                                     u32 de_iir)
2126 {
2127         enum pipe pipe;
2128         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2129
2130         if (hotplug_trigger)
2131                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2132
2133         if (de_iir & DE_AUX_CHANNEL_A)
2134                 dp_aux_irq_handler(dev_priv);
2135
2136         if (de_iir & DE_GSE)
2137                 intel_opregion_asle_intr(dev_priv);
2138
2139         if (de_iir & DE_POISON)
2140                 DRM_ERROR("Poison interrupt\n");
2141
2142         for_each_pipe(dev_priv, pipe) {
2143                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2144                     intel_pipe_handle_vblank(dev_priv, pipe))
2145                         intel_check_page_flip(dev_priv, pipe);
2146
2147                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2148                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2149
2150                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2151                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2152
2153                 /* plane/pipes map 1:1 on ilk+ */
2154                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2155                         intel_finish_page_flip_cs(dev_priv, pipe);
2156         }
2157
2158         /* check event from PCH */
2159         if (de_iir & DE_PCH_EVENT) {
2160                 u32 pch_iir = I915_READ(SDEIIR);
2161
2162                 if (HAS_PCH_CPT(dev_priv))
2163                         cpt_irq_handler(dev_priv, pch_iir);
2164                 else
2165                         ibx_irq_handler(dev_priv, pch_iir);
2166
2167                 /* should clear PCH hotplug event before clear CPU irq */
2168                 I915_WRITE(SDEIIR, pch_iir);
2169         }
2170
2171         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2172                 ironlake_rps_change_irq_handler(dev_priv);
2173 }
2174
2175 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2176                                     u32 de_iir)
2177 {
2178         enum pipe pipe;
2179         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2180
2181         if (hotplug_trigger)
2182                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2183
2184         if (de_iir & DE_ERR_INT_IVB)
2185                 ivb_err_int_handler(dev_priv);
2186
2187         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2188                 dp_aux_irq_handler(dev_priv);
2189
2190         if (de_iir & DE_GSE_IVB)
2191                 intel_opregion_asle_intr(dev_priv);
2192
2193         for_each_pipe(dev_priv, pipe) {
2194                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2195                     intel_pipe_handle_vblank(dev_priv, pipe))
2196                         intel_check_page_flip(dev_priv, pipe);
2197
2198                 /* plane/pipes map 1:1 on ilk+ */
2199                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2200                         intel_finish_page_flip_cs(dev_priv, pipe);
2201         }
2202
2203         /* check event from PCH */
2204         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2205                 u32 pch_iir = I915_READ(SDEIIR);
2206
2207                 cpt_irq_handler(dev_priv, pch_iir);
2208
2209                 /* clear PCH hotplug event before clear CPU irq */
2210                 I915_WRITE(SDEIIR, pch_iir);
2211         }
2212 }
2213
2214 /*
2215  * To handle irqs with the minimum potential races with fresh interrupts, we:
2216  * 1 - Disable Master Interrupt Control.
2217  * 2 - Find the source(s) of the interrupt.
2218  * 3 - Clear the Interrupt Identity bits (IIR).
2219  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2220  * 5 - Re-enable Master Interrupt Control.
2221  */
2222 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2223 {
2224         struct drm_device *dev = arg;
2225         struct drm_i915_private *dev_priv = dev->dev_private;
2226         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2227         irqreturn_t ret = IRQ_NONE;
2228
2229         if (!intel_irqs_enabled(dev_priv))
2230                 return IRQ_NONE;
2231
2232         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2233         disable_rpm_wakeref_asserts(dev_priv);
2234
2235         /* disable master interrupt before clearing iir  */
2236         de_ier = I915_READ(DEIER);
2237         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2238         POSTING_READ(DEIER);
2239
2240         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2241          * interrupts will will be stored on its back queue, and then we'll be
2242          * able to process them after we restore SDEIER (as soon as we restore
2243          * it, we'll get an interrupt if SDEIIR still has something to process
2244          * due to its back queue). */
2245         if (!HAS_PCH_NOP(dev_priv)) {
2246                 sde_ier = I915_READ(SDEIER);
2247                 I915_WRITE(SDEIER, 0);
2248                 POSTING_READ(SDEIER);
2249         }
2250
2251         /* Find, clear, then process each source of interrupt */
2252
2253         gt_iir = I915_READ(GTIIR);
2254         if (gt_iir) {
2255                 I915_WRITE(GTIIR, gt_iir);
2256                 ret = IRQ_HANDLED;
2257                 if (INTEL_GEN(dev_priv) >= 6)
2258                         snb_gt_irq_handler(dev_priv, gt_iir);
2259                 else
2260                         ilk_gt_irq_handler(dev_priv, gt_iir);
2261         }
2262
2263         de_iir = I915_READ(DEIIR);
2264         if (de_iir) {
2265                 I915_WRITE(DEIIR, de_iir);
2266                 ret = IRQ_HANDLED;
2267                 if (INTEL_GEN(dev_priv) >= 7)
2268                         ivb_display_irq_handler(dev_priv, de_iir);
2269                 else
2270                         ilk_display_irq_handler(dev_priv, de_iir);
2271         }
2272
2273         if (INTEL_GEN(dev_priv) >= 6) {
2274                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2275                 if (pm_iir) {
2276                         I915_WRITE(GEN6_PMIIR, pm_iir);
2277                         ret = IRQ_HANDLED;
2278                         gen6_rps_irq_handler(dev_priv, pm_iir);
2279                 }
2280         }
2281
2282         I915_WRITE(DEIER, de_ier);
2283         POSTING_READ(DEIER);
2284         if (!HAS_PCH_NOP(dev_priv)) {
2285                 I915_WRITE(SDEIER, sde_ier);
2286                 POSTING_READ(SDEIER);
2287         }
2288
2289         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2290         enable_rpm_wakeref_asserts(dev_priv);
2291
2292         return ret;
2293 }
2294
2295 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2296                                 u32 hotplug_trigger,
2297                                 const u32 hpd[HPD_NUM_PINS])
2298 {
2299         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2300
2301         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2302         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2303
2304         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2305                            dig_hotplug_reg, hpd,
2306                            bxt_port_hotplug_long_detect);
2307
2308         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2309 }
2310
2311 static irqreturn_t
2312 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2313 {
2314         irqreturn_t ret = IRQ_NONE;
2315         u32 iir;
2316         enum pipe pipe;
2317
2318         if (master_ctl & GEN8_DE_MISC_IRQ) {
2319                 iir = I915_READ(GEN8_DE_MISC_IIR);
2320                 if (iir) {
2321                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2322                         ret = IRQ_HANDLED;
2323                         if (iir & GEN8_DE_MISC_GSE)
2324                                 intel_opregion_asle_intr(dev_priv);
2325                         else
2326                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2327                 }
2328                 else
2329                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2330         }
2331
2332         if (master_ctl & GEN8_DE_PORT_IRQ) {
2333                 iir = I915_READ(GEN8_DE_PORT_IIR);
2334                 if (iir) {
2335                         u32 tmp_mask;
2336                         bool found = false;
2337
2338                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2339                         ret = IRQ_HANDLED;
2340
2341                         tmp_mask = GEN8_AUX_CHANNEL_A;
2342                         if (INTEL_INFO(dev_priv)->gen >= 9)
2343                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2344                                             GEN9_AUX_CHANNEL_C |
2345                                             GEN9_AUX_CHANNEL_D;
2346
2347                         if (iir & tmp_mask) {
2348                                 dp_aux_irq_handler(dev_priv);
2349                                 found = true;
2350                         }
2351
2352                         if (IS_BROXTON(dev_priv)) {
2353                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2354                                 if (tmp_mask) {
2355                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2356                                                             hpd_bxt);
2357                                         found = true;
2358                                 }
2359                         } else if (IS_BROADWELL(dev_priv)) {
2360                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2361                                 if (tmp_mask) {
2362                                         ilk_hpd_irq_handler(dev_priv,
2363                                                             tmp_mask, hpd_bdw);
2364                                         found = true;
2365                                 }
2366                         }
2367
2368                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2369                                 gmbus_irq_handler(dev_priv);
2370                                 found = true;
2371                         }
2372
2373                         if (!found)
2374                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2375                 }
2376                 else
2377                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2378         }
2379
2380         for_each_pipe(dev_priv, pipe) {
2381                 u32 flip_done, fault_errors;
2382
2383                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2384                         continue;
2385
2386                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2387                 if (!iir) {
2388                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2389                         continue;
2390                 }
2391
2392                 ret = IRQ_HANDLED;
2393                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2394
2395                 if (iir & GEN8_PIPE_VBLANK &&
2396                     intel_pipe_handle_vblank(dev_priv, pipe))
2397                         intel_check_page_flip(dev_priv, pipe);
2398
2399                 flip_done = iir;
2400                 if (INTEL_INFO(dev_priv)->gen >= 9)
2401                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2402                 else
2403                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2404
2405                 if (flip_done)
2406                         intel_finish_page_flip_cs(dev_priv, pipe);
2407
2408                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2409                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2410
2411                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2412                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2413
2414                 fault_errors = iir;
2415                 if (INTEL_INFO(dev_priv)->gen >= 9)
2416                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2417                 else
2418                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2419
2420                 if (fault_errors)
2421                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2422                                   pipe_name(pipe),
2423                                   fault_errors);
2424         }
2425
2426         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2427             master_ctl & GEN8_DE_PCH_IRQ) {
2428                 /*
2429                  * FIXME(BDW): Assume for now that the new interrupt handling
2430                  * scheme also closed the SDE interrupt handling race we've seen
2431                  * on older pch-split platforms. But this needs testing.
2432                  */
2433                 iir = I915_READ(SDEIIR);
2434                 if (iir) {
2435                         I915_WRITE(SDEIIR, iir);
2436                         ret = IRQ_HANDLED;
2437
2438                         if (HAS_PCH_SPT(dev_priv))
2439                                 spt_irq_handler(dev_priv, iir);
2440                         else
2441                                 cpt_irq_handler(dev_priv, iir);
2442                 } else {
2443                         /*
2444                          * Like on previous PCH there seems to be something
2445                          * fishy going on with forwarding PCH interrupts.
2446                          */
2447                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2448                 }
2449         }
2450
2451         return ret;
2452 }
2453
2454 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2455 {
2456         struct drm_device *dev = arg;
2457         struct drm_i915_private *dev_priv = dev->dev_private;
2458         u32 master_ctl;
2459         u32 gt_iir[4] = {};
2460         irqreturn_t ret;
2461
2462         if (!intel_irqs_enabled(dev_priv))
2463                 return IRQ_NONE;
2464
2465         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2466         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2467         if (!master_ctl)
2468                 return IRQ_NONE;
2469
2470         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2471
2472         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2473         disable_rpm_wakeref_asserts(dev_priv);
2474
2475         /* Find, clear, then process each source of interrupt */
2476         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2477         gen8_gt_irq_handler(dev_priv, gt_iir);
2478         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2479
2480         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2481         POSTING_READ_FW(GEN8_MASTER_IRQ);
2482
2483         enable_rpm_wakeref_asserts(dev_priv);
2484
2485         return ret;
2486 }
2487
2488 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2489 {
2490         /*
2491          * Notify all waiters for GPU completion events that reset state has
2492          * been changed, and that they need to restart their wait after
2493          * checking for potential errors (and bail out to drop locks if there is
2494          * a gpu reset pending so that i915_error_work_func can acquire them).
2495          */
2496
2497         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2498         wake_up_all(&dev_priv->gpu_error.wait_queue);
2499
2500         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2501         wake_up_all(&dev_priv->pending_flip_queue);
2502 }
2503
2504 /**
2505  * i915_reset_and_wakeup - do process context error handling work
2506  * @dev_priv: i915 device private
2507  *
2508  * Fire an error uevent so userspace can see that a hang or error
2509  * was detected.
2510  */
2511 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2512 {
2513         struct kobject *kobj = &dev_priv->dev->primary->kdev->kobj;
2514         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2515         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2516         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2517         int ret;
2518
2519         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2520
2521         /*
2522          * Note that there's only one work item which does gpu resets, so we
2523          * need not worry about concurrent gpu resets potentially incrementing
2524          * error->reset_counter twice. We only need to take care of another
2525          * racing irq/hangcheck declaring the gpu dead for a second time. A
2526          * quick check for that is good enough: schedule_work ensures the
2527          * correct ordering between hang detection and this work item, and since
2528          * the reset in-progress bit is only ever set by code outside of this
2529          * work we don't need to worry about any other races.
2530          */
2531         if (i915_reset_in_progress(&dev_priv->gpu_error)) {
2532                 DRM_DEBUG_DRIVER("resetting chip\n");
2533                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2534
2535                 /*
2536                  * In most cases it's guaranteed that we get here with an RPM
2537                  * reference held, for example because there is a pending GPU
2538                  * request that won't finish until the reset is done. This
2539                  * isn't the case at least when we get here by doing a
2540                  * simulated reset via debugs, so get an RPM reference.
2541                  */
2542                 intel_runtime_pm_get(dev_priv);
2543
2544                 intel_prepare_reset(dev_priv);
2545
2546                 /*
2547                  * All state reset _must_ be completed before we update the
2548                  * reset counter, for otherwise waiters might miss the reset
2549                  * pending state and not properly drop locks, resulting in
2550                  * deadlocks with the reset work.
2551                  */
2552                 ret = i915_reset(dev_priv);
2553
2554                 intel_finish_reset(dev_priv);
2555
2556                 intel_runtime_pm_put(dev_priv);
2557
2558                 if (ret == 0)
2559                         kobject_uevent_env(kobj,
2560                                            KOBJ_CHANGE, reset_done_event);
2561
2562                 /*
2563                  * Note: The wake_up also serves as a memory barrier so that
2564                  * waiters see the update value of the reset counter atomic_t.
2565                  */
2566                 wake_up_all(&dev_priv->gpu_error.reset_queue);
2567         }
2568 }
2569
2570 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2571 {
2572         uint32_t instdone[I915_NUM_INSTDONE_REG];
2573         u32 eir = I915_READ(EIR);
2574         int pipe, i;
2575
2576         if (!eir)
2577                 return;
2578
2579         pr_err("render error detected, EIR: 0x%08x\n", eir);
2580
2581         i915_get_extra_instdone(dev_priv, instdone);
2582
2583         if (IS_G4X(dev_priv)) {
2584                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2585                         u32 ipeir = I915_READ(IPEIR_I965);
2586
2587                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2588                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2589                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2590                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2591                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2592                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2593                         I915_WRITE(IPEIR_I965, ipeir);
2594                         POSTING_READ(IPEIR_I965);
2595                 }
2596                 if (eir & GM45_ERROR_PAGE_TABLE) {
2597                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2598                         pr_err("page table error\n");
2599                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2600                         I915_WRITE(PGTBL_ER, pgtbl_err);
2601                         POSTING_READ(PGTBL_ER);
2602                 }
2603         }
2604
2605         if (!IS_GEN2(dev_priv)) {
2606                 if (eir & I915_ERROR_PAGE_TABLE) {
2607                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2608                         pr_err("page table error\n");
2609                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2610                         I915_WRITE(PGTBL_ER, pgtbl_err);
2611                         POSTING_READ(PGTBL_ER);
2612                 }
2613         }
2614
2615         if (eir & I915_ERROR_MEMORY_REFRESH) {
2616                 pr_err("memory refresh error:\n");
2617                 for_each_pipe(dev_priv, pipe)
2618                         pr_err("pipe %c stat: 0x%08x\n",
2619                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2620                 /* pipestat has already been acked */
2621         }
2622         if (eir & I915_ERROR_INSTRUCTION) {
2623                 pr_err("instruction error\n");
2624                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2625                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2626                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2627                 if (INTEL_GEN(dev_priv) < 4) {
2628                         u32 ipeir = I915_READ(IPEIR);
2629
2630                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2631                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2632                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2633                         I915_WRITE(IPEIR, ipeir);
2634                         POSTING_READ(IPEIR);
2635                 } else {
2636                         u32 ipeir = I915_READ(IPEIR_I965);
2637
2638                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2639                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2640                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2641                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2642                         I915_WRITE(IPEIR_I965, ipeir);
2643                         POSTING_READ(IPEIR_I965);
2644                 }
2645         }
2646
2647         I915_WRITE(EIR, eir);
2648         POSTING_READ(EIR);
2649         eir = I915_READ(EIR);
2650         if (eir) {
2651                 /*
2652                  * some errors might have become stuck,
2653                  * mask them.
2654                  */
2655                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2656                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2657                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2658         }
2659 }
2660
2661 /**
2662  * i915_handle_error - handle a gpu error
2663  * @dev_priv: i915 device private
2664  * @engine_mask: mask representing engines that are hung
2665  * Do some basic checking of register state at error time and
2666  * dump it to the syslog.  Also call i915_capture_error_state() to make
2667  * sure we get a record and make it available in debugfs.  Fire a uevent
2668  * so userspace knows something bad happened (should trigger collection
2669  * of a ring dump etc.).
2670  * @fmt: Error message format string
2671  */
2672 void i915_handle_error(struct drm_i915_private *dev_priv,
2673                        u32 engine_mask,
2674                        const char *fmt, ...)
2675 {
2676         va_list args;
2677         char error_msg[80];
2678
2679         va_start(args, fmt);
2680         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2681         va_end(args);
2682
2683         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2684         i915_report_and_clear_eir(dev_priv);
2685
2686         if (engine_mask) {
2687                 atomic_or(I915_RESET_IN_PROGRESS_FLAG,
2688                                 &dev_priv->gpu_error.reset_counter);
2689
2690                 /*
2691                  * Wakeup waiting processes so that the reset function
2692                  * i915_reset_and_wakeup doesn't deadlock trying to grab
2693                  * various locks. By bumping the reset counter first, the woken
2694                  * processes will see a reset in progress and back off,
2695                  * releasing their locks and then wait for the reset completion.
2696                  * We must do this for _all_ gpu waiters that might hold locks
2697                  * that the reset work needs to acquire.
2698                  *
2699                  * Note: The wake_up serves as the required memory barrier to
2700                  * ensure that the waiters see the updated value of the reset
2701                  * counter atomic_t.
2702                  */
2703                 i915_error_wake_up(dev_priv);
2704         }
2705
2706         i915_reset_and_wakeup(dev_priv);
2707 }
2708
2709 /* Called from drm generic code, passed 'crtc' which
2710  * we use as a pipe index
2711  */
2712 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2713 {
2714         struct drm_i915_private *dev_priv = dev->dev_private;
2715         unsigned long irqflags;
2716
2717         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2718         if (INTEL_INFO(dev)->gen >= 4)
2719                 i915_enable_pipestat(dev_priv, pipe,
2720                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2721         else
2722                 i915_enable_pipestat(dev_priv, pipe,
2723                                      PIPE_VBLANK_INTERRUPT_STATUS);
2724         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2725
2726         return 0;
2727 }
2728
2729 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2730 {
2731         struct drm_i915_private *dev_priv = dev->dev_private;
2732         unsigned long irqflags;
2733         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2734                                                      DE_PIPE_VBLANK(pipe);
2735
2736         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2737         ilk_enable_display_irq(dev_priv, bit);
2738         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2739
2740         return 0;
2741 }
2742
2743 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2744 {
2745         struct drm_i915_private *dev_priv = dev->dev_private;
2746         unsigned long irqflags;
2747
2748         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2749         i915_enable_pipestat(dev_priv, pipe,
2750                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2751         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2752
2753         return 0;
2754 }
2755
2756 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2757 {
2758         struct drm_i915_private *dev_priv = dev->dev_private;
2759         unsigned long irqflags;
2760
2761         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2762         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2763         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2764
2765         return 0;
2766 }
2767
2768 /* Called from drm generic code, passed 'crtc' which
2769  * we use as a pipe index
2770  */
2771 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2772 {
2773         struct drm_i915_private *dev_priv = dev->dev_private;
2774         unsigned long irqflags;
2775
2776         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2777         i915_disable_pipestat(dev_priv, pipe,
2778                               PIPE_VBLANK_INTERRUPT_STATUS |
2779                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2780         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2781 }
2782
2783 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2784 {
2785         struct drm_i915_private *dev_priv = dev->dev_private;
2786         unsigned long irqflags;
2787         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2788                                                      DE_PIPE_VBLANK(pipe);
2789
2790         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2791         ilk_disable_display_irq(dev_priv, bit);
2792         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2793 }
2794
2795 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2796 {
2797         struct drm_i915_private *dev_priv = dev->dev_private;
2798         unsigned long irqflags;
2799
2800         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2801         i915_disable_pipestat(dev_priv, pipe,
2802                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2803         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2804 }
2805
2806 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2807 {
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         unsigned long irqflags;
2810
2811         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2812         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2813         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2814 }
2815
2816 static bool
2817 ring_idle(struct intel_engine_cs *engine, u32 seqno)
2818 {
2819         return i915_seqno_passed(seqno,
2820                                  READ_ONCE(engine->last_submitted_seqno));
2821 }
2822
2823 static bool
2824 ipehr_is_semaphore_wait(struct drm_i915_private *dev_priv, u32 ipehr)
2825 {
2826         if (INTEL_GEN(dev_priv) >= 8) {
2827                 return (ipehr >> 23) == 0x1c;
2828         } else {
2829                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2830                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2831                                  MI_SEMAPHORE_REGISTER);
2832         }
2833 }
2834
2835 static struct intel_engine_cs *
2836 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2837                                  u64 offset)
2838 {
2839         struct drm_i915_private *dev_priv = engine->i915;
2840         struct intel_engine_cs *signaller;
2841
2842         if (INTEL_GEN(dev_priv) >= 8) {
2843                 for_each_engine(signaller, dev_priv) {
2844                         if (engine == signaller)
2845                                 continue;
2846
2847                         if (offset == signaller->semaphore.signal_ggtt[engine->id])
2848                                 return signaller;
2849                 }
2850         } else {
2851                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2852
2853                 for_each_engine(signaller, dev_priv) {
2854                         if(engine == signaller)
2855                                 continue;
2856
2857                         if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
2858                                 return signaller;
2859                 }
2860         }
2861
2862         DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2863                   engine->id, ipehr, offset);
2864
2865         return NULL;
2866 }
2867
2868 static struct intel_engine_cs *
2869 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2870 {
2871         struct drm_i915_private *dev_priv = engine->i915;
2872         u32 cmd, ipehr, head;
2873         u64 offset = 0;
2874         int i, backwards;
2875
2876         /*
2877          * This function does not support execlist mode - any attempt to
2878          * proceed further into this function will result in a kernel panic
2879          * when dereferencing ring->buffer, which is not set up in execlist
2880          * mode.
2881          *
2882          * The correct way of doing it would be to derive the currently
2883          * executing ring buffer from the current context, which is derived
2884          * from the currently running request. Unfortunately, to get the
2885          * current request we would have to grab the struct_mutex before doing
2886          * anything else, which would be ill-advised since some other thread
2887          * might have grabbed it already and managed to hang itself, causing
2888          * the hang checker to deadlock.
2889          *
2890          * Therefore, this function does not support execlist mode in its
2891          * current form. Just return NULL and move on.
2892          */
2893         if (engine->buffer == NULL)
2894                 return NULL;
2895
2896         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2897         if (!ipehr_is_semaphore_wait(engine->i915, ipehr))
2898                 return NULL;
2899
2900         /*
2901          * HEAD is likely pointing to the dword after the actual command,
2902          * so scan backwards until we find the MBOX. But limit it to just 3
2903          * or 4 dwords depending on the semaphore wait command size.
2904          * Note that we don't care about ACTHD here since that might
2905          * point at at batch, and semaphores are always emitted into the
2906          * ringbuffer itself.
2907          */
2908         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2909         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2910
2911         for (i = backwards; i; --i) {
2912                 /*
2913                  * Be paranoid and presume the hw has gone off into the wild -
2914                  * our ring is smaller than what the hardware (and hence
2915                  * HEAD_ADDR) allows. Also handles wrap-around.
2916                  */
2917                 head &= engine->buffer->size - 1;
2918
2919                 /* This here seems to blow up */
2920                 cmd = ioread32(engine->buffer->virtual_start + head);
2921                 if (cmd == ipehr)
2922                         break;
2923
2924                 head -= 4;
2925         }
2926
2927         if (!i)
2928                 return NULL;
2929
2930         *seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
2931         if (INTEL_GEN(dev_priv) >= 8) {
2932                 offset = ioread32(engine->buffer->virtual_start + head + 12);
2933                 offset <<= 32;
2934                 offset = ioread32(engine->buffer->virtual_start + head + 8);
2935         }
2936         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2937 }
2938
2939 static int semaphore_passed(struct intel_engine_cs *engine)
2940 {
2941         struct drm_i915_private *dev_priv = engine->i915;
2942         struct intel_engine_cs *signaller;
2943         u32 seqno;
2944
2945         engine->hangcheck.deadlock++;
2946
2947         signaller = semaphore_waits_for(engine, &seqno);
2948         if (signaller == NULL)
2949                 return -1;
2950
2951         /* Prevent pathological recursion due to driver bugs */
2952         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2953                 return -1;
2954
2955         if (i915_seqno_passed(signaller->get_seqno(signaller), seqno))
2956                 return 1;
2957
2958         /* cursory check for an unkickable deadlock */
2959         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2960             semaphore_passed(signaller) < 0)
2961                 return -1;
2962
2963         return 0;
2964 }
2965
2966 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2967 {
2968         struct intel_engine_cs *engine;
2969
2970         for_each_engine(engine, dev_priv)
2971                 engine->hangcheck.deadlock = 0;
2972 }
2973
2974 static bool subunits_stuck(struct intel_engine_cs *engine)
2975 {
2976         u32 instdone[I915_NUM_INSTDONE_REG];
2977         bool stuck;
2978         int i;
2979
2980         if (engine->id != RCS)
2981                 return true;
2982
2983         i915_get_extra_instdone(engine->i915, instdone);
2984
2985         /* There might be unstable subunit states even when
2986          * actual head is not moving. Filter out the unstable ones by
2987          * accumulating the undone -> done transitions and only
2988          * consider those as progress.
2989          */
2990         stuck = true;
2991         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2992                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2993
2994                 if (tmp != engine->hangcheck.instdone[i])
2995                         stuck = false;
2996
2997                 engine->hangcheck.instdone[i] |= tmp;
2998         }
2999
3000         return stuck;
3001 }
3002
3003 static enum intel_ring_hangcheck_action
3004 head_stuck(struct intel_engine_cs *engine, u64 acthd)
3005 {
3006         if (acthd != engine->hangcheck.acthd) {
3007
3008                 /* Clear subunit states on head movement */
3009                 memset(engine->hangcheck.instdone, 0,
3010                        sizeof(engine->hangcheck.instdone));
3011
3012                 return HANGCHECK_ACTIVE;
3013         }
3014
3015         if (!subunits_stuck(engine))
3016                 return HANGCHECK_ACTIVE;
3017
3018         return HANGCHECK_HUNG;
3019 }
3020
3021 static enum intel_ring_hangcheck_action
3022 ring_stuck(struct intel_engine_cs *engine, u64 acthd)
3023 {
3024         struct drm_i915_private *dev_priv = engine->i915;
3025         enum intel_ring_hangcheck_action ha;
3026         u32 tmp;
3027
3028         ha = head_stuck(engine, acthd);
3029         if (ha != HANGCHECK_HUNG)
3030                 return ha;
3031
3032         if (IS_GEN2(dev_priv))
3033                 return HANGCHECK_HUNG;
3034
3035         /* Is the chip hanging on a WAIT_FOR_EVENT?
3036          * If so we can simply poke the RB_WAIT bit
3037          * and break the hang. This should work on
3038          * all but the second generation chipsets.
3039          */
3040         tmp = I915_READ_CTL(engine);
3041         if (tmp & RING_WAIT) {
3042                 i915_handle_error(dev_priv, 0,
3043                                   "Kicking stuck wait on %s",
3044                                   engine->name);
3045                 I915_WRITE_CTL(engine, tmp);
3046                 return HANGCHECK_KICK;
3047         }
3048
3049         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3050                 switch (semaphore_passed(engine)) {
3051                 default:
3052                         return HANGCHECK_HUNG;
3053                 case 1:
3054                         i915_handle_error(dev_priv, 0,
3055                                           "Kicking stuck semaphore on %s",
3056                                           engine->name);
3057                         I915_WRITE_CTL(engine, tmp);
3058                         return HANGCHECK_KICK;
3059                 case 0:
3060                         return HANGCHECK_WAIT;
3061                 }
3062         }
3063
3064         return HANGCHECK_HUNG;
3065 }
3066
3067 static unsigned kick_waiters(struct intel_engine_cs *engine)
3068 {
3069         struct drm_i915_private *i915 = engine->i915;
3070         unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
3071
3072         if (engine->hangcheck.user_interrupts == user_interrupts &&
3073             !test_and_set_bit(engine->id, &i915->gpu_error.missed_irq_rings)) {
3074                 if (!test_bit(engine->id, &i915->gpu_error.test_irq_rings))
3075                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
3076                                   engine->name);
3077                 else
3078                         DRM_INFO("Fake missed irq on %s\n",
3079                                  engine->name);
3080
3081                 intel_engine_enable_fake_irq(engine);
3082         }
3083
3084         return user_interrupts;
3085 }
3086 /*
3087  * This is called when the chip hasn't reported back with completed
3088  * batchbuffers in a long time. We keep track per ring seqno progress and
3089  * if there are no progress, hangcheck score for that ring is increased.
3090  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3091  * we kick the ring. If we see no progress on three subsequent calls
3092  * we assume chip is wedged and try to fix it by resetting the chip.
3093  */
3094 static void i915_hangcheck_elapsed(struct work_struct *work)
3095 {
3096         struct drm_i915_private *dev_priv =
3097                 container_of(work, typeof(*dev_priv),
3098                              gpu_error.hangcheck_work.work);
3099         struct intel_engine_cs *engine;
3100         enum intel_engine_id id;
3101         int busy_count = 0, rings_hung = 0;
3102         bool stuck[I915_NUM_ENGINES] = { 0 };
3103 #define BUSY 1
3104 #define KICK 5
3105 #define HUNG 20
3106 #define ACTIVE_DECAY 15
3107
3108         if (!i915.enable_hangcheck)
3109                 return;
3110
3111         /*
3112          * The hangcheck work is synced during runtime suspend, we don't
3113          * require a wakeref. TODO: instead of disabling the asserts make
3114          * sure that we hold a reference when this work is running.
3115          */
3116         DISABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3117
3118         /* As enabling the GPU requires fairly extensive mmio access,
3119          * periodically arm the mmio checker to see if we are triggering
3120          * any invalid access.
3121          */
3122         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3123
3124         for_each_engine_id(engine, dev_priv, id) {
3125                 bool busy = intel_engine_has_waiter(engine);
3126                 u64 acthd;
3127                 u32 seqno;
3128                 unsigned user_interrupts;
3129
3130                 semaphore_clear_deadlocks(dev_priv);
3131
3132                 /* We don't strictly need an irq-barrier here, as we are not
3133                  * serving an interrupt request, be paranoid in case the
3134                  * barrier has side-effects (such as preventing a broken
3135                  * cacheline snoop) and so be sure that we can see the seqno
3136                  * advance. If the seqno should stick, due to a stale
3137                  * cacheline, we would erroneously declare the GPU hung.
3138                  */
3139                 if (engine->irq_seqno_barrier)
3140                         engine->irq_seqno_barrier(engine);
3141
3142                 acthd = intel_ring_get_active_head(engine);
3143                 seqno = engine->get_seqno(engine);
3144
3145                 /* Reset stuck interrupts between batch advances */
3146                 user_interrupts = 0;
3147
3148                 if (engine->hangcheck.seqno == seqno) {
3149                         if (ring_idle(engine, seqno)) {
3150                                 engine->hangcheck.action = HANGCHECK_IDLE;
3151                                 if (busy) {
3152                                         /* Safeguard against driver failure */
3153                                         user_interrupts = kick_waiters(engine);
3154                                         engine->hangcheck.score += BUSY;
3155                                 }
3156                         } else {
3157                                 /* We always increment the hangcheck score
3158                                  * if the ring is busy and still processing
3159                                  * the same request, so that no single request
3160                                  * can run indefinitely (such as a chain of
3161                                  * batches). The only time we do not increment
3162                                  * the hangcheck score on this ring, if this
3163                                  * ring is in a legitimate wait for another
3164                                  * ring. In that case the waiting ring is a
3165                                  * victim and we want to be sure we catch the
3166                                  * right culprit. Then every time we do kick
3167                                  * the ring, add a small increment to the
3168                                  * score so that we can catch a batch that is
3169                                  * being repeatedly kicked and so responsible
3170                                  * for stalling the machine.
3171                                  */
3172                                 engine->hangcheck.action = ring_stuck(engine,
3173                                                                       acthd);
3174
3175                                 switch (engine->hangcheck.action) {
3176                                 case HANGCHECK_IDLE:
3177                                 case HANGCHECK_WAIT:
3178                                         break;
3179                                 case HANGCHECK_ACTIVE:
3180                                         engine->hangcheck.score += BUSY;
3181                                         break;
3182                                 case HANGCHECK_KICK:
3183                                         engine->hangcheck.score += KICK;
3184                                         break;
3185                                 case HANGCHECK_HUNG:
3186                                         engine->hangcheck.score += HUNG;
3187                                         stuck[id] = true;
3188                                         break;
3189                                 }
3190                         }
3191                 } else {
3192                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3193
3194                         /* Gradually reduce the count so that we catch DoS
3195                          * attempts across multiple batches.
3196                          */
3197                         if (engine->hangcheck.score > 0)
3198                                 engine->hangcheck.score -= ACTIVE_DECAY;
3199                         if (engine->hangcheck.score < 0)
3200                                 engine->hangcheck.score = 0;
3201
3202                         /* Clear head and subunit states on seqno movement */
3203                         acthd = 0;
3204
3205                         memset(engine->hangcheck.instdone, 0,
3206                                sizeof(engine->hangcheck.instdone));
3207                 }
3208
3209                 engine->hangcheck.seqno = seqno;
3210                 engine->hangcheck.acthd = acthd;
3211                 engine->hangcheck.user_interrupts = user_interrupts;
3212                 busy_count += busy;
3213         }
3214
3215         for_each_engine_id(engine, dev_priv, id) {
3216                 if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3217                         DRM_INFO("%s on %s\n",
3218                                  stuck[id] ? "stuck" : "no progress",
3219                                  engine->name);
3220                         rings_hung |= intel_engine_flag(engine);
3221                 }
3222         }
3223
3224         if (rings_hung) {
3225                 i915_handle_error(dev_priv, rings_hung, "Engine(s) hung");
3226                 goto out;
3227         }
3228
3229         /* Reset timer in case GPU hangs without another request being added */
3230         if (busy_count)
3231                 i915_queue_hangcheck(dev_priv);
3232
3233 out:
3234         ENABLE_RPM_WAKEREF_ASSERTS(dev_priv);
3235 }
3236
3237 static void ibx_irq_reset(struct drm_device *dev)
3238 {
3239         struct drm_i915_private *dev_priv = dev->dev_private;
3240
3241         if (HAS_PCH_NOP(dev))
3242                 return;
3243
3244         GEN5_IRQ_RESET(SDE);
3245
3246         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3247                 I915_WRITE(SERR_INT, 0xffffffff);
3248 }
3249
3250 /*
3251  * SDEIER is also touched by the interrupt handler to work around missed PCH
3252  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3253  * instead we unconditionally enable all PCH interrupt sources here, but then
3254  * only unmask them as needed with SDEIMR.
3255  *
3256  * This function needs to be called before interrupts are enabled.
3257  */
3258 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3259 {
3260         struct drm_i915_private *dev_priv = dev->dev_private;
3261
3262         if (HAS_PCH_NOP(dev))
3263                 return;
3264
3265         WARN_ON(I915_READ(SDEIER) != 0);
3266         I915_WRITE(SDEIER, 0xffffffff);
3267         POSTING_READ(SDEIER);
3268 }
3269
3270 static void gen5_gt_irq_reset(struct drm_device *dev)
3271 {
3272         struct drm_i915_private *dev_priv = dev->dev_private;
3273
3274         GEN5_IRQ_RESET(GT);
3275         if (INTEL_INFO(dev)->gen >= 6)
3276                 GEN5_IRQ_RESET(GEN6_PM);
3277 }
3278
3279 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3280 {
3281         enum pipe pipe;
3282
3283         if (IS_CHERRYVIEW(dev_priv))
3284                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3285         else
3286                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3287
3288         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3289         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3290
3291         for_each_pipe(dev_priv, pipe) {
3292                 I915_WRITE(PIPESTAT(pipe),
3293                            PIPE_FIFO_UNDERRUN_STATUS |
3294                            PIPESTAT_INT_STATUS_MASK);
3295                 dev_priv->pipestat_irq_mask[pipe] = 0;
3296         }
3297
3298         GEN5_IRQ_RESET(VLV_);
3299         dev_priv->irq_mask = ~0;
3300 }
3301
3302 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3303 {
3304         u32 pipestat_mask;
3305         u32 enable_mask;
3306         enum pipe pipe;
3307
3308         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3309                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3310
3311         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3312         for_each_pipe(dev_priv, pipe)
3313                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3314
3315         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3316                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3317                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3318         if (IS_CHERRYVIEW(dev_priv))
3319                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3320
3321         WARN_ON(dev_priv->irq_mask != ~0);
3322
3323         dev_priv->irq_mask = ~enable_mask;
3324
3325         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3326 }
3327
3328 /* drm_dma.h hooks
3329 */
3330 static void ironlake_irq_reset(struct drm_device *dev)
3331 {
3332         struct drm_i915_private *dev_priv = dev->dev_private;
3333
3334         I915_WRITE(HWSTAM, 0xffffffff);
3335
3336         GEN5_IRQ_RESET(DE);
3337         if (IS_GEN7(dev))
3338                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3339
3340         gen5_gt_irq_reset(dev);
3341
3342         ibx_irq_reset(dev);
3343 }
3344
3345 static void valleyview_irq_preinstall(struct drm_device *dev)
3346 {
3347         struct drm_i915_private *dev_priv = dev->dev_private;
3348
3349         I915_WRITE(VLV_MASTER_IER, 0);
3350         POSTING_READ(VLV_MASTER_IER);
3351
3352         gen5_gt_irq_reset(dev);
3353
3354         spin_lock_irq(&dev_priv->irq_lock);
3355         if (dev_priv->display_irqs_enabled)
3356                 vlv_display_irq_reset(dev_priv);
3357         spin_unlock_irq(&dev_priv->irq_lock);
3358 }
3359
3360 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3361 {
3362         GEN8_IRQ_RESET_NDX(GT, 0);
3363         GEN8_IRQ_RESET_NDX(GT, 1);
3364         GEN8_IRQ_RESET_NDX(GT, 2);
3365         GEN8_IRQ_RESET_NDX(GT, 3);
3366 }
3367
3368 static void gen8_irq_reset(struct drm_device *dev)
3369 {
3370         struct drm_i915_private *dev_priv = dev->dev_private;
3371         int pipe;
3372
3373         I915_WRITE(GEN8_MASTER_IRQ, 0);
3374         POSTING_READ(GEN8_MASTER_IRQ);
3375
3376         gen8_gt_irq_reset(dev_priv);
3377
3378         for_each_pipe(dev_priv, pipe)
3379                 if (intel_display_power_is_enabled(dev_priv,
3380                                                    POWER_DOMAIN_PIPE(pipe)))
3381                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3382
3383         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3384         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3385         GEN5_IRQ_RESET(GEN8_PCU_);
3386
3387         if (HAS_PCH_SPLIT(dev))
3388                 ibx_irq_reset(dev);
3389 }
3390
3391 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3392                                      unsigned int pipe_mask)
3393 {
3394         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3395         enum pipe pipe;
3396
3397         spin_lock_irq(&dev_priv->irq_lock);
3398         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3399                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3400                                   dev_priv->de_irq_mask[pipe],
3401                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3402         spin_unlock_irq(&dev_priv->irq_lock);
3403 }
3404
3405 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3406                                      unsigned int pipe_mask)
3407 {
3408         enum pipe pipe;
3409
3410         spin_lock_irq(&dev_priv->irq_lock);
3411         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3412                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3413         spin_unlock_irq(&dev_priv->irq_lock);
3414
3415         /* make sure we're done processing display irqs */
3416         synchronize_irq(dev_priv->dev->irq);
3417 }
3418
3419 static void cherryview_irq_preinstall(struct drm_device *dev)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423         I915_WRITE(GEN8_MASTER_IRQ, 0);
3424         POSTING_READ(GEN8_MASTER_IRQ);
3425
3426         gen8_gt_irq_reset(dev_priv);
3427
3428         GEN5_IRQ_RESET(GEN8_PCU_);
3429
3430         spin_lock_irq(&dev_priv->irq_lock);
3431         if (dev_priv->display_irqs_enabled)
3432                 vlv_display_irq_reset(dev_priv);
3433         spin_unlock_irq(&dev_priv->irq_lock);
3434 }
3435
3436 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3437                                   const u32 hpd[HPD_NUM_PINS])
3438 {
3439         struct intel_encoder *encoder;
3440         u32 enabled_irqs = 0;
3441
3442         for_each_intel_encoder(dev_priv->dev, encoder)
3443                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3444                         enabled_irqs |= hpd[encoder->hpd_pin];
3445
3446         return enabled_irqs;
3447 }
3448
3449 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3450 {
3451         u32 hotplug_irqs, hotplug, enabled_irqs;
3452
3453         if (HAS_PCH_IBX(dev_priv)) {
3454                 hotplug_irqs = SDE_HOTPLUG_MASK;
3455                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3456         } else {
3457                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3458                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3459         }
3460
3461         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3462
3463         /*
3464          * Enable digital hotplug on the PCH, and configure the DP short pulse
3465          * duration to 2ms (which is the minimum in the Display Port spec).
3466          * The pulse duration bits are reserved on LPT+.
3467          */
3468         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3469         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3470         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3471         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3472         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3473         /*
3474          * When CPU and PCH are on the same package, port A
3475          * HPD must be enabled in both north and south.
3476          */
3477         if (HAS_PCH_LPT_LP(dev_priv))
3478                 hotplug |= PORTA_HOTPLUG_ENABLE;
3479         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3480 }
3481
3482 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3483 {
3484         u32 hotplug_irqs, hotplug, enabled_irqs;
3485
3486         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3487         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3488
3489         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3490
3491         /* Enable digital hotplug on the PCH */
3492         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3493         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3494                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3495         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3496
3497         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3498         hotplug |= PORTE_HOTPLUG_ENABLE;
3499         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3500 }
3501
3502 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3503 {
3504         u32 hotplug_irqs, hotplug, enabled_irqs;
3505
3506         if (INTEL_GEN(dev_priv) >= 8) {
3507                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3508                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3509
3510                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3511         } else if (INTEL_GEN(dev_priv) >= 7) {
3512                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3513                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3514
3515                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3516         } else {
3517                 hotplug_irqs = DE_DP_A_HOTPLUG;
3518                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3519
3520                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3521         }
3522
3523         /*
3524          * Enable digital hotplug on the CPU, and configure the DP short pulse
3525          * duration to 2ms (which is the minimum in the Display Port spec)
3526          * The pulse duration bits are reserved on HSW+.
3527          */
3528         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3529         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3530         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3531         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3532
3533         ibx_hpd_irq_setup(dev_priv);
3534 }
3535
3536 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3537 {
3538         u32 hotplug_irqs, hotplug, enabled_irqs;
3539
3540         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3541         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3542
3543         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3544
3545         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3546         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3547                 PORTA_HOTPLUG_ENABLE;
3548
3549         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3550                       hotplug, enabled_irqs);
3551         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3552
3553         /*
3554          * For BXT invert bit has to be set based on AOB design
3555          * for HPD detection logic, update it based on VBT fields.
3556          */
3557
3558         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3559             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3560                 hotplug |= BXT_DDIA_HPD_INVERT;
3561         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3562             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3563                 hotplug |= BXT_DDIB_HPD_INVERT;
3564         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3565             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3566                 hotplug |= BXT_DDIC_HPD_INVERT;
3567
3568         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3569 }
3570
3571 static void ibx_irq_postinstall(struct drm_device *dev)
3572 {
3573         struct drm_i915_private *dev_priv = dev->dev_private;
3574         u32 mask;
3575
3576         if (HAS_PCH_NOP(dev))
3577                 return;
3578
3579         if (HAS_PCH_IBX(dev))
3580                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3581         else
3582                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3583
3584         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3585         I915_WRITE(SDEIMR, ~mask);
3586 }
3587
3588 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3589 {
3590         struct drm_i915_private *dev_priv = dev->dev_private;
3591         u32 pm_irqs, gt_irqs;
3592
3593         pm_irqs = gt_irqs = 0;
3594
3595         dev_priv->gt_irq_mask = ~0;
3596         if (HAS_L3_DPF(dev)) {
3597                 /* L3 parity interrupt is always unmasked. */
3598                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3599                 gt_irqs |= GT_PARITY_ERROR(dev);
3600         }
3601
3602         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3603         if (IS_GEN5(dev)) {
3604                 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3605                            ILK_BSD_USER_INTERRUPT;
3606         } else {
3607                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3608         }
3609
3610         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3611
3612         if (INTEL_INFO(dev)->gen >= 6) {
3613                 /*
3614                  * RPS interrupts will get enabled/disabled on demand when RPS
3615                  * itself is enabled/disabled.
3616                  */
3617                 if (HAS_VEBOX(dev))
3618                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3619
3620                 dev_priv->pm_irq_mask = 0xffffffff;
3621                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3622         }
3623 }
3624
3625 static int ironlake_irq_postinstall(struct drm_device *dev)
3626 {
3627         struct drm_i915_private *dev_priv = dev->dev_private;
3628         u32 display_mask, extra_mask;
3629
3630         if (INTEL_INFO(dev)->gen >= 7) {
3631                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3632                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3633                                 DE_PLANEB_FLIP_DONE_IVB |
3634                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3635                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3636                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3637                               DE_DP_A_HOTPLUG_IVB);
3638         } else {
3639                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3640                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3641                                 DE_AUX_CHANNEL_A |
3642                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3643                                 DE_POISON);
3644                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3645                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3646                               DE_DP_A_HOTPLUG);
3647         }
3648
3649         dev_priv->irq_mask = ~display_mask;
3650
3651         I915_WRITE(HWSTAM, 0xeffe);
3652
3653         ibx_irq_pre_postinstall(dev);
3654
3655         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3656
3657         gen5_gt_irq_postinstall(dev);
3658
3659         ibx_irq_postinstall(dev);
3660
3661         if (IS_IRONLAKE_M(dev)) {
3662                 /* Enable PCU event interrupts
3663                  *
3664                  * spinlocking not required here for correctness since interrupt
3665                  * setup is guaranteed to run in single-threaded context. But we
3666                  * need it to make the assert_spin_locked happy. */
3667                 spin_lock_irq(&dev_priv->irq_lock);
3668                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3669                 spin_unlock_irq(&dev_priv->irq_lock);
3670         }
3671
3672         return 0;
3673 }
3674
3675 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3676 {
3677         assert_spin_locked(&dev_priv->irq_lock);
3678
3679         if (dev_priv->display_irqs_enabled)
3680                 return;
3681
3682         dev_priv->display_irqs_enabled = true;
3683
3684         if (intel_irqs_enabled(dev_priv)) {
3685                 vlv_display_irq_reset(dev_priv);
3686                 vlv_display_irq_postinstall(dev_priv);
3687         }
3688 }
3689
3690 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3691 {
3692         assert_spin_locked(&dev_priv->irq_lock);
3693
3694         if (!dev_priv->display_irqs_enabled)
3695                 return;
3696
3697         dev_priv->display_irqs_enabled = false;
3698
3699         if (intel_irqs_enabled(dev_priv))
3700                 vlv_display_irq_reset(dev_priv);
3701 }
3702
3703
3704 static int valleyview_irq_postinstall(struct drm_device *dev)
3705 {
3706         struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708         gen5_gt_irq_postinstall(dev);
3709
3710         spin_lock_irq(&dev_priv->irq_lock);
3711         if (dev_priv->display_irqs_enabled)
3712                 vlv_display_irq_postinstall(dev_priv);
3713         spin_unlock_irq(&dev_priv->irq_lock);
3714
3715         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3716         POSTING_READ(VLV_MASTER_IER);
3717
3718         return 0;
3719 }
3720
3721 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3722 {
3723         /* These are interrupts we'll toggle with the ring mask register */
3724         uint32_t gt_interrupts[] = {
3725                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3726                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3727                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3728                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3729                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3730                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3731                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3732                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3733                 0,
3734                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3735                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3736                 };
3737
3738         if (HAS_L3_DPF(dev_priv))
3739                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3740
3741         dev_priv->pm_irq_mask = 0xffffffff;
3742         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3743         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3744         /*
3745          * RPS interrupts will get enabled/disabled on demand when RPS itself
3746          * is enabled/disabled.
3747          */
3748         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3749         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3750 }
3751
3752 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3753 {
3754         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3755         uint32_t de_pipe_enables;
3756         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3757         u32 de_port_enables;
3758         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3759         enum pipe pipe;
3760
3761         if (INTEL_INFO(dev_priv)->gen >= 9) {
3762                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3763                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3764                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3765                                   GEN9_AUX_CHANNEL_D;
3766                 if (IS_BROXTON(dev_priv))
3767                         de_port_masked |= BXT_DE_PORT_GMBUS;
3768         } else {
3769                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3770                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3771         }
3772
3773         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3774                                            GEN8_PIPE_FIFO_UNDERRUN;
3775
3776         de_port_enables = de_port_masked;
3777         if (IS_BROXTON(dev_priv))
3778                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3779         else if (IS_BROADWELL(dev_priv))
3780                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3781
3782         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3783         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3784         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3785
3786         for_each_pipe(dev_priv, pipe)
3787                 if (intel_display_power_is_enabled(dev_priv,
3788                                 POWER_DOMAIN_PIPE(pipe)))
3789                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3790                                           dev_priv->de_irq_mask[pipe],
3791                                           de_pipe_enables);
3792
3793         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3794         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3795 }
3796
3797 static int gen8_irq_postinstall(struct drm_device *dev)
3798 {
3799         struct drm_i915_private *dev_priv = dev->dev_private;
3800
3801         if (HAS_PCH_SPLIT(dev))
3802                 ibx_irq_pre_postinstall(dev);
3803
3804         gen8_gt_irq_postinstall(dev_priv);
3805         gen8_de_irq_postinstall(dev_priv);
3806
3807         if (HAS_PCH_SPLIT(dev))
3808                 ibx_irq_postinstall(dev);
3809
3810         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3811         POSTING_READ(GEN8_MASTER_IRQ);
3812
3813         return 0;
3814 }
3815
3816 static int cherryview_irq_postinstall(struct drm_device *dev)
3817 {
3818         struct drm_i915_private *dev_priv = dev->dev_private;
3819
3820         gen8_gt_irq_postinstall(dev_priv);
3821
3822         spin_lock_irq(&dev_priv->irq_lock);
3823         if (dev_priv->display_irqs_enabled)
3824                 vlv_display_irq_postinstall(dev_priv);
3825         spin_unlock_irq(&dev_priv->irq_lock);
3826
3827         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3828         POSTING_READ(GEN8_MASTER_IRQ);
3829
3830         return 0;
3831 }
3832
3833 static void gen8_irq_uninstall(struct drm_device *dev)
3834 {
3835         struct drm_i915_private *dev_priv = dev->dev_private;
3836
3837         if (!dev_priv)
3838                 return;
3839
3840         gen8_irq_reset(dev);
3841 }
3842
3843 static void valleyview_irq_uninstall(struct drm_device *dev)
3844 {
3845         struct drm_i915_private *dev_priv = dev->dev_private;
3846
3847         if (!dev_priv)
3848                 return;
3849
3850         I915_WRITE(VLV_MASTER_IER, 0);
3851         POSTING_READ(VLV_MASTER_IER);
3852
3853         gen5_gt_irq_reset(dev);
3854
3855         I915_WRITE(HWSTAM, 0xffffffff);
3856
3857         spin_lock_irq(&dev_priv->irq_lock);
3858         if (dev_priv->display_irqs_enabled)
3859                 vlv_display_irq_reset(dev_priv);
3860         spin_unlock_irq(&dev_priv->irq_lock);
3861 }
3862
3863 static void cherryview_irq_uninstall(struct drm_device *dev)
3864 {
3865         struct drm_i915_private *dev_priv = dev->dev_private;
3866
3867         if (!dev_priv)
3868                 return;
3869
3870         I915_WRITE(GEN8_MASTER_IRQ, 0);
3871         POSTING_READ(GEN8_MASTER_IRQ);
3872
3873         gen8_gt_irq_reset(dev_priv);
3874
3875         GEN5_IRQ_RESET(GEN8_PCU_);
3876
3877         spin_lock_irq(&dev_priv->irq_lock);
3878         if (dev_priv->display_irqs_enabled)
3879                 vlv_display_irq_reset(dev_priv);
3880         spin_unlock_irq(&dev_priv->irq_lock);
3881 }
3882
3883 static void ironlake_irq_uninstall(struct drm_device *dev)
3884 {
3885         struct drm_i915_private *dev_priv = dev->dev_private;
3886
3887         if (!dev_priv)
3888                 return;
3889
3890         ironlake_irq_reset(dev);
3891 }
3892
3893 static void i8xx_irq_preinstall(struct drm_device * dev)
3894 {
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         int pipe;
3897
3898         for_each_pipe(dev_priv, pipe)
3899                 I915_WRITE(PIPESTAT(pipe), 0);
3900         I915_WRITE16(IMR, 0xffff);
3901         I915_WRITE16(IER, 0x0);
3902         POSTING_READ16(IER);
3903 }
3904
3905 static int i8xx_irq_postinstall(struct drm_device *dev)
3906 {
3907         struct drm_i915_private *dev_priv = dev->dev_private;
3908
3909         I915_WRITE16(EMR,
3910                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3911
3912         /* Unmask the interrupts that we always want on. */
3913         dev_priv->irq_mask =
3914                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3915                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3916                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3917                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3918         I915_WRITE16(IMR, dev_priv->irq_mask);
3919
3920         I915_WRITE16(IER,
3921                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3922                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3923                      I915_USER_INTERRUPT);
3924         POSTING_READ16(IER);
3925
3926         /* Interrupt setup is already guaranteed to be single-threaded, this is
3927          * just to make the assert_spin_locked check happy. */
3928         spin_lock_irq(&dev_priv->irq_lock);
3929         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3930         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3931         spin_unlock_irq(&dev_priv->irq_lock);
3932
3933         return 0;
3934 }
3935
3936 /*
3937  * Returns true when a page flip has completed.
3938  */
3939 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3940                                int plane, int pipe, u32 iir)
3941 {
3942         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3943
3944         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3945                 return false;
3946
3947         if ((iir & flip_pending) == 0)
3948                 goto check_page_flip;
3949
3950         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3951          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3952          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3953          * the flip is completed (no longer pending). Since this doesn't raise
3954          * an interrupt per se, we watch for the change at vblank.
3955          */
3956         if (I915_READ16(ISR) & flip_pending)
3957                 goto check_page_flip;
3958
3959         intel_finish_page_flip_cs(dev_priv, pipe);
3960         return true;
3961
3962 check_page_flip:
3963         intel_check_page_flip(dev_priv, pipe);
3964         return false;
3965 }
3966
3967 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3968 {
3969         struct drm_device *dev = arg;
3970         struct drm_i915_private *dev_priv = dev->dev_private;
3971         u16 iir, new_iir;
3972         u32 pipe_stats[2];
3973         int pipe;
3974         u16 flip_mask =
3975                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3976                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3977         irqreturn_t ret;
3978
3979         if (!intel_irqs_enabled(dev_priv))
3980                 return IRQ_NONE;
3981
3982         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3983         disable_rpm_wakeref_asserts(dev_priv);
3984
3985         ret = IRQ_NONE;
3986         iir = I915_READ16(IIR);
3987         if (iir == 0)
3988                 goto out;
3989
3990         while (iir & ~flip_mask) {
3991                 /* Can't rely on pipestat interrupt bit in iir as it might
3992                  * have been cleared after the pipestat interrupt was received.
3993                  * It doesn't set the bit in iir again, but it still produces
3994                  * interrupts (for non-MSI).
3995                  */
3996                 spin_lock(&dev_priv->irq_lock);
3997                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3998                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3999
4000                 for_each_pipe(dev_priv, pipe) {
4001                         i915_reg_t reg = PIPESTAT(pipe);
4002                         pipe_stats[pipe] = I915_READ(reg);
4003
4004                         /*
4005                          * Clear the PIPE*STAT regs before the IIR
4006                          */
4007                         if (pipe_stats[pipe] & 0x8000ffff)
4008                                 I915_WRITE(reg, pipe_stats[pipe]);
4009                 }
4010                 spin_unlock(&dev_priv->irq_lock);
4011
4012                 I915_WRITE16(IIR, iir & ~flip_mask);
4013                 new_iir = I915_READ16(IIR); /* Flush posted writes */
4014
4015                 if (iir & I915_USER_INTERRUPT)
4016                         notify_ring(&dev_priv->engine[RCS]);
4017
4018                 for_each_pipe(dev_priv, pipe) {
4019                         int plane = pipe;
4020                         if (HAS_FBC(dev_priv))
4021                                 plane = !plane;
4022
4023                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4024                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
4025                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4026
4027                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4028                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4029
4030                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4031                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4032                                                                     pipe);
4033                 }
4034
4035                 iir = new_iir;
4036         }
4037         ret = IRQ_HANDLED;
4038
4039 out:
4040         enable_rpm_wakeref_asserts(dev_priv);
4041
4042         return ret;
4043 }
4044
4045 static void i8xx_irq_uninstall(struct drm_device * dev)
4046 {
4047         struct drm_i915_private *dev_priv = dev->dev_private;
4048         int pipe;
4049
4050         for_each_pipe(dev_priv, pipe) {
4051                 /* Clear enable bits; then clear status bits */
4052                 I915_WRITE(PIPESTAT(pipe), 0);
4053                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4054         }
4055         I915_WRITE16(IMR, 0xffff);
4056         I915_WRITE16(IER, 0x0);
4057         I915_WRITE16(IIR, I915_READ16(IIR));
4058 }
4059
4060 static void i915_irq_preinstall(struct drm_device * dev)
4061 {
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         int pipe;
4064
4065         if (I915_HAS_HOTPLUG(dev)) {
4066                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4067                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4068         }
4069
4070         I915_WRITE16(HWSTAM, 0xeffe);
4071         for_each_pipe(dev_priv, pipe)
4072                 I915_WRITE(PIPESTAT(pipe), 0);
4073         I915_WRITE(IMR, 0xffffffff);
4074         I915_WRITE(IER, 0x0);
4075         POSTING_READ(IER);
4076 }
4077
4078 static int i915_irq_postinstall(struct drm_device *dev)
4079 {
4080         struct drm_i915_private *dev_priv = dev->dev_private;
4081         u32 enable_mask;
4082
4083         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4084
4085         /* Unmask the interrupts that we always want on. */
4086         dev_priv->irq_mask =
4087                 ~(I915_ASLE_INTERRUPT |
4088                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4089                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4090                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4091                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4092
4093         enable_mask =
4094                 I915_ASLE_INTERRUPT |
4095                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4096                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4097                 I915_USER_INTERRUPT;
4098
4099         if (I915_HAS_HOTPLUG(dev)) {
4100                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4101                 POSTING_READ(PORT_HOTPLUG_EN);
4102
4103                 /* Enable in IER... */
4104                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4105                 /* and unmask in IMR */
4106                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4107         }
4108
4109         I915_WRITE(IMR, dev_priv->irq_mask);
4110         I915_WRITE(IER, enable_mask);
4111         POSTING_READ(IER);
4112
4113         i915_enable_asle_pipestat(dev_priv);
4114
4115         /* Interrupt setup is already guaranteed to be single-threaded, this is
4116          * just to make the assert_spin_locked check happy. */
4117         spin_lock_irq(&dev_priv->irq_lock);
4118         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4119         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4120         spin_unlock_irq(&dev_priv->irq_lock);
4121
4122         return 0;
4123 }
4124
4125 /*
4126  * Returns true when a page flip has completed.
4127  */
4128 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4129                                int plane, int pipe, u32 iir)
4130 {
4131         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4132
4133         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4134                 return false;
4135
4136         if ((iir & flip_pending) == 0)
4137                 goto check_page_flip;
4138
4139         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4140          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4141          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4142          * the flip is completed (no longer pending). Since this doesn't raise
4143          * an interrupt per se, we watch for the change at vblank.
4144          */
4145         if (I915_READ(ISR) & flip_pending)
4146                 goto check_page_flip;
4147
4148         intel_finish_page_flip_cs(dev_priv, pipe);
4149         return true;
4150
4151 check_page_flip:
4152         intel_check_page_flip(dev_priv, pipe);
4153         return false;
4154 }
4155
4156 static irqreturn_t i915_irq_handler(int irq, void *arg)
4157 {
4158         struct drm_device *dev = arg;
4159         struct drm_i915_private *dev_priv = dev->dev_private;
4160         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4161         u32 flip_mask =
4162                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4163                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4164         int pipe, ret = IRQ_NONE;
4165
4166         if (!intel_irqs_enabled(dev_priv))
4167                 return IRQ_NONE;
4168
4169         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4170         disable_rpm_wakeref_asserts(dev_priv);
4171
4172         iir = I915_READ(IIR);
4173         do {
4174                 bool irq_received = (iir & ~flip_mask) != 0;
4175                 bool blc_event = false;
4176
4177                 /* Can't rely on pipestat interrupt bit in iir as it might
4178                  * have been cleared after the pipestat interrupt was received.
4179                  * It doesn't set the bit in iir again, but it still produces
4180                  * interrupts (for non-MSI).
4181                  */
4182                 spin_lock(&dev_priv->irq_lock);
4183                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4184                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4185
4186                 for_each_pipe(dev_priv, pipe) {
4187                         i915_reg_t reg = PIPESTAT(pipe);
4188                         pipe_stats[pipe] = I915_READ(reg);
4189
4190                         /* Clear the PIPE*STAT regs before the IIR */
4191                         if (pipe_stats[pipe] & 0x8000ffff) {
4192                                 I915_WRITE(reg, pipe_stats[pipe]);
4193                                 irq_received = true;
4194                         }
4195                 }
4196                 spin_unlock(&dev_priv->irq_lock);
4197
4198                 if (!irq_received)
4199                         break;
4200
4201                 /* Consume port.  Then clear IIR or we'll miss events */
4202                 if (I915_HAS_HOTPLUG(dev_priv) &&
4203                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4204                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4205                         if (hotplug_status)
4206                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4207                 }
4208
4209                 I915_WRITE(IIR, iir & ~flip_mask);
4210                 new_iir = I915_READ(IIR); /* Flush posted writes */
4211
4212                 if (iir & I915_USER_INTERRUPT)
4213                         notify_ring(&dev_priv->engine[RCS]);
4214
4215                 for_each_pipe(dev_priv, pipe) {
4216                         int plane = pipe;
4217                         if (HAS_FBC(dev_priv))
4218                                 plane = !plane;
4219
4220                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4221                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4222                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4223
4224                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4225                                 blc_event = true;
4226
4227                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4228                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4229
4230                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4231                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4232                                                                     pipe);
4233                 }
4234
4235                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4236                         intel_opregion_asle_intr(dev_priv);
4237
4238                 /* With MSI, interrupts are only generated when iir
4239                  * transitions from zero to nonzero.  If another bit got
4240                  * set while we were handling the existing iir bits, then
4241                  * we would never get another interrupt.
4242                  *
4243                  * This is fine on non-MSI as well, as if we hit this path
4244                  * we avoid exiting the interrupt handler only to generate
4245                  * another one.
4246                  *
4247                  * Note that for MSI this could cause a stray interrupt report
4248                  * if an interrupt landed in the time between writing IIR and
4249                  * the posting read.  This should be rare enough to never
4250                  * trigger the 99% of 100,000 interrupts test for disabling
4251                  * stray interrupts.
4252                  */
4253                 ret = IRQ_HANDLED;
4254                 iir = new_iir;
4255         } while (iir & ~flip_mask);
4256
4257         enable_rpm_wakeref_asserts(dev_priv);
4258
4259         return ret;
4260 }
4261
4262 static void i915_irq_uninstall(struct drm_device * dev)
4263 {
4264         struct drm_i915_private *dev_priv = dev->dev_private;
4265         int pipe;
4266
4267         if (I915_HAS_HOTPLUG(dev)) {
4268                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4269                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4270         }
4271
4272         I915_WRITE16(HWSTAM, 0xffff);
4273         for_each_pipe(dev_priv, pipe) {
4274                 /* Clear enable bits; then clear status bits */
4275                 I915_WRITE(PIPESTAT(pipe), 0);
4276                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4277         }
4278         I915_WRITE(IMR, 0xffffffff);
4279         I915_WRITE(IER, 0x0);
4280
4281         I915_WRITE(IIR, I915_READ(IIR));
4282 }
4283
4284 static void i965_irq_preinstall(struct drm_device * dev)
4285 {
4286         struct drm_i915_private *dev_priv = dev->dev_private;
4287         int pipe;
4288
4289         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4290         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4291
4292         I915_WRITE(HWSTAM, 0xeffe);
4293         for_each_pipe(dev_priv, pipe)
4294                 I915_WRITE(PIPESTAT(pipe), 0);
4295         I915_WRITE(IMR, 0xffffffff);
4296         I915_WRITE(IER, 0x0);
4297         POSTING_READ(IER);
4298 }
4299
4300 static int i965_irq_postinstall(struct drm_device *dev)
4301 {
4302         struct drm_i915_private *dev_priv = dev->dev_private;
4303         u32 enable_mask;
4304         u32 error_mask;
4305
4306         /* Unmask the interrupts that we always want on. */
4307         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4308                                I915_DISPLAY_PORT_INTERRUPT |
4309                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4310                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4311                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4312                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4313                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4314
4315         enable_mask = ~dev_priv->irq_mask;
4316         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4317                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4318         enable_mask |= I915_USER_INTERRUPT;
4319
4320         if (IS_G4X(dev_priv))
4321                 enable_mask |= I915_BSD_USER_INTERRUPT;
4322
4323         /* Interrupt setup is already guaranteed to be single-threaded, this is
4324          * just to make the assert_spin_locked check happy. */
4325         spin_lock_irq(&dev_priv->irq_lock);
4326         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4327         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4328         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4329         spin_unlock_irq(&dev_priv->irq_lock);
4330
4331         /*
4332          * Enable some error detection, note the instruction error mask
4333          * bit is reserved, so we leave it masked.
4334          */
4335         if (IS_G4X(dev_priv)) {
4336                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4337                                GM45_ERROR_MEM_PRIV |
4338                                GM45_ERROR_CP_PRIV |
4339                                I915_ERROR_MEMORY_REFRESH);
4340         } else {
4341                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4342                                I915_ERROR_MEMORY_REFRESH);
4343         }
4344         I915_WRITE(EMR, error_mask);
4345
4346         I915_WRITE(IMR, dev_priv->irq_mask);
4347         I915_WRITE(IER, enable_mask);
4348         POSTING_READ(IER);
4349
4350         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4351         POSTING_READ(PORT_HOTPLUG_EN);
4352
4353         i915_enable_asle_pipestat(dev_priv);
4354
4355         return 0;
4356 }
4357
4358 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4359 {
4360         u32 hotplug_en;
4361
4362         assert_spin_locked(&dev_priv->irq_lock);
4363
4364         /* Note HDMI and DP share hotplug bits */
4365         /* enable bits are the same for all generations */
4366         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4367         /* Programming the CRT detection parameters tends
4368            to generate a spurious hotplug event about three
4369            seconds later.  So just do it once.
4370         */
4371         if (IS_G4X(dev_priv))
4372                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4373         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4374
4375         /* Ignore TV since it's buggy */
4376         i915_hotplug_interrupt_update_locked(dev_priv,
4377                                              HOTPLUG_INT_EN_MASK |
4378                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4379                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4380                                              hotplug_en);
4381 }
4382
4383 static irqreturn_t i965_irq_handler(int irq, void *arg)
4384 {
4385         struct drm_device *dev = arg;
4386         struct drm_i915_private *dev_priv = dev->dev_private;
4387         u32 iir, new_iir;
4388         u32 pipe_stats[I915_MAX_PIPES];
4389         int ret = IRQ_NONE, pipe;
4390         u32 flip_mask =
4391                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4392                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4393
4394         if (!intel_irqs_enabled(dev_priv))
4395                 return IRQ_NONE;
4396
4397         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4398         disable_rpm_wakeref_asserts(dev_priv);
4399
4400         iir = I915_READ(IIR);
4401
4402         for (;;) {
4403                 bool irq_received = (iir & ~flip_mask) != 0;
4404                 bool blc_event = false;
4405
4406                 /* Can't rely on pipestat interrupt bit in iir as it might
4407                  * have been cleared after the pipestat interrupt was received.
4408                  * It doesn't set the bit in iir again, but it still produces
4409                  * interrupts (for non-MSI).
4410                  */
4411                 spin_lock(&dev_priv->irq_lock);
4412                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4413                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4414
4415                 for_each_pipe(dev_priv, pipe) {
4416                         i915_reg_t reg = PIPESTAT(pipe);
4417                         pipe_stats[pipe] = I915_READ(reg);
4418
4419                         /*
4420                          * Clear the PIPE*STAT regs before the IIR
4421                          */
4422                         if (pipe_stats[pipe] & 0x8000ffff) {
4423                                 I915_WRITE(reg, pipe_stats[pipe]);
4424                                 irq_received = true;
4425                         }
4426                 }
4427                 spin_unlock(&dev_priv->irq_lock);
4428
4429                 if (!irq_received)
4430                         break;
4431
4432                 ret = IRQ_HANDLED;
4433
4434                 /* Consume port.  Then clear IIR or we'll miss events */
4435                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4436                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4437                         if (hotplug_status)
4438                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4439                 }
4440
4441                 I915_WRITE(IIR, iir & ~flip_mask);
4442                 new_iir = I915_READ(IIR); /* Flush posted writes */
4443
4444                 if (iir & I915_USER_INTERRUPT)
4445                         notify_ring(&dev_priv->engine[RCS]);
4446                 if (iir & I915_BSD_USER_INTERRUPT)
4447                         notify_ring(&dev_priv->engine[VCS]);
4448
4449                 for_each_pipe(dev_priv, pipe) {
4450                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4451                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4452                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4453
4454                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4455                                 blc_event = true;
4456
4457                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4458                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4459
4460                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4461                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4462                 }
4463
4464                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4465                         intel_opregion_asle_intr(dev_priv);
4466
4467                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4468                         gmbus_irq_handler(dev_priv);
4469
4470                 /* With MSI, interrupts are only generated when iir
4471                  * transitions from zero to nonzero.  If another bit got
4472                  * set while we were handling the existing iir bits, then
4473                  * we would never get another interrupt.
4474                  *
4475                  * This is fine on non-MSI as well, as if we hit this path
4476                  * we avoid exiting the interrupt handler only to generate
4477                  * another one.
4478                  *
4479                  * Note that for MSI this could cause a stray interrupt report
4480                  * if an interrupt landed in the time between writing IIR and
4481                  * the posting read.  This should be rare enough to never
4482                  * trigger the 99% of 100,000 interrupts test for disabling
4483                  * stray interrupts.
4484                  */
4485                 iir = new_iir;
4486         }
4487
4488         enable_rpm_wakeref_asserts(dev_priv);
4489
4490         return ret;
4491 }
4492
4493 static void i965_irq_uninstall(struct drm_device * dev)
4494 {
4495         struct drm_i915_private *dev_priv = dev->dev_private;
4496         int pipe;
4497
4498         if (!dev_priv)
4499                 return;
4500
4501         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4502         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4503
4504         I915_WRITE(HWSTAM, 0xffffffff);
4505         for_each_pipe(dev_priv, pipe)
4506                 I915_WRITE(PIPESTAT(pipe), 0);
4507         I915_WRITE(IMR, 0xffffffff);
4508         I915_WRITE(IER, 0x0);
4509
4510         for_each_pipe(dev_priv, pipe)
4511                 I915_WRITE(PIPESTAT(pipe),
4512                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4513         I915_WRITE(IIR, I915_READ(IIR));
4514 }
4515
4516 /**
4517  * intel_irq_init - initializes irq support
4518  * @dev_priv: i915 device instance
4519  *
4520  * This function initializes all the irq support including work items, timers
4521  * and all the vtables. It does not setup the interrupt itself though.
4522  */
4523 void intel_irq_init(struct drm_i915_private *dev_priv)
4524 {
4525         struct drm_device *dev = dev_priv->dev;
4526
4527         intel_hpd_init_work(dev_priv);
4528
4529         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4530         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4531
4532         /* Let's track the enabled rps events */
4533         if (IS_VALLEYVIEW(dev_priv))
4534                 /* WaGsvRC0ResidencyMethod:vlv */
4535                 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
4536         else
4537                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4538
4539         dev_priv->rps.pm_intr_keep = 0;
4540
4541         /*
4542          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4543          * if GEN6_PM_UP_EI_EXPIRED is masked.
4544          *
4545          * TODO: verify if this can be reproduced on VLV,CHV.
4546          */
4547         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4548                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4549
4550         if (INTEL_INFO(dev_priv)->gen >= 8)
4551                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_NON_DISP;
4552
4553         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4554                           i915_hangcheck_elapsed);
4555
4556         if (IS_GEN2(dev_priv)) {
4557                 dev->max_vblank_count = 0;
4558                 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
4559         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4560                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4561                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4562         } else {
4563                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4564                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4565         }
4566
4567         /*
4568          * Opt out of the vblank disable timer on everything except gen2.
4569          * Gen2 doesn't have a hardware frame counter and so depends on
4570          * vblank interrupts to produce sane vblank seuquence numbers.
4571          */
4572         if (!IS_GEN2(dev_priv))
4573                 dev->vblank_disable_immediate = true;
4574
4575         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4576         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4577
4578         if (IS_CHERRYVIEW(dev_priv)) {
4579                 dev->driver->irq_handler = cherryview_irq_handler;
4580                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4581                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4582                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4583                 dev->driver->enable_vblank = valleyview_enable_vblank;
4584                 dev->driver->disable_vblank = valleyview_disable_vblank;
4585                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4586         } else if (IS_VALLEYVIEW(dev_priv)) {
4587                 dev->driver->irq_handler = valleyview_irq_handler;
4588                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4589                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4590                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4591                 dev->driver->enable_vblank = valleyview_enable_vblank;
4592                 dev->driver->disable_vblank = valleyview_disable_vblank;
4593                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4594         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4595                 dev->driver->irq_handler = gen8_irq_handler;
4596                 dev->driver->irq_preinstall = gen8_irq_reset;
4597                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4598                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4599                 dev->driver->enable_vblank = gen8_enable_vblank;
4600                 dev->driver->disable_vblank = gen8_disable_vblank;
4601                 if (IS_BROXTON(dev))
4602                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4603                 else if (HAS_PCH_SPT(dev))
4604                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4605                 else
4606                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4607         } else if (HAS_PCH_SPLIT(dev)) {
4608                 dev->driver->irq_handler = ironlake_irq_handler;
4609                 dev->driver->irq_preinstall = ironlake_irq_reset;
4610                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4611                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4612                 dev->driver->enable_vblank = ironlake_enable_vblank;
4613                 dev->driver->disable_vblank = ironlake_disable_vblank;
4614                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4615         } else {
4616                 if (IS_GEN2(dev_priv)) {
4617                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4618                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4619                         dev->driver->irq_handler = i8xx_irq_handler;
4620                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4621                 } else if (IS_GEN3(dev_priv)) {
4622                         dev->driver->irq_preinstall = i915_irq_preinstall;
4623                         dev->driver->irq_postinstall = i915_irq_postinstall;
4624                         dev->driver->irq_uninstall = i915_irq_uninstall;
4625                         dev->driver->irq_handler = i915_irq_handler;
4626                 } else {
4627                         dev->driver->irq_preinstall = i965_irq_preinstall;
4628                         dev->driver->irq_postinstall = i965_irq_postinstall;
4629                         dev->driver->irq_uninstall = i965_irq_uninstall;
4630                         dev->driver->irq_handler = i965_irq_handler;
4631                 }
4632                 if (I915_HAS_HOTPLUG(dev_priv))
4633                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4634                 dev->driver->enable_vblank = i915_enable_vblank;
4635                 dev->driver->disable_vblank = i915_disable_vblank;
4636         }
4637 }
4638
4639 /**
4640  * intel_irq_install - enables the hardware interrupt
4641  * @dev_priv: i915 device instance
4642  *
4643  * This function enables the hardware interrupt handling, but leaves the hotplug
4644  * handling still disabled. It is called after intel_irq_init().
4645  *
4646  * In the driver load and resume code we need working interrupts in a few places
4647  * but don't want to deal with the hassle of concurrent probe and hotplug
4648  * workers. Hence the split into this two-stage approach.
4649  */
4650 int intel_irq_install(struct drm_i915_private *dev_priv)
4651 {
4652         /*
4653          * We enable some interrupt sources in our postinstall hooks, so mark
4654          * interrupts as enabled _before_ actually enabling them to avoid
4655          * special cases in our ordering checks.
4656          */
4657         dev_priv->pm.irqs_enabled = true;
4658
4659         return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4660 }
4661
4662 /**
4663  * intel_irq_uninstall - finilizes all irq handling
4664  * @dev_priv: i915 device instance
4665  *
4666  * This stops interrupt and hotplug handling and unregisters and frees all
4667  * resources acquired in the init functions.
4668  */
4669 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4670 {
4671         drm_irq_uninstall(dev_priv->dev);
4672         intel_hpd_cancel_work(dev_priv);
4673         dev_priv->pm.irqs_enabled = false;
4674 }
4675
4676 /**
4677  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4678  * @dev_priv: i915 device instance
4679  *
4680  * This function is used to disable interrupts at runtime, both in the runtime
4681  * pm and the system suspend/resume code.
4682  */
4683 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4684 {
4685         dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4686         dev_priv->pm.irqs_enabled = false;
4687         synchronize_irq(dev_priv->dev->irq);
4688 }
4689
4690 /**
4691  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4692  * @dev_priv: i915 device instance
4693  *
4694  * This function is used to enable interrupts at runtime, both in the runtime
4695  * pm and the system suspend/resume code.
4696  */
4697 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4698 {
4699         dev_priv->pm.irqs_enabled = true;
4700         dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4701         dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
4702 }