drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 /* For display hotplug interrupt */
  40 static void
  41 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  42 {
  43         if ((dev_priv->irq_mask & mask) != 0) {
  44                 dev_priv->irq_mask &= ~mask;
  45                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  46                 POSTING_READ(DEIMR);
  47         }
  48 }
  49
  50 static inline void
  51 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  52 {
  53         if ((dev_priv->irq_mask & mask) != mask) {
  54                 dev_priv->irq_mask |= mask;
  55                 I915_WRITE(DEIMR, dev_priv->irq_mask);
  56                 POSTING_READ(DEIMR);
  57         }
  58 }
  59
  60 void
  61 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  62 {
  63         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  64                 u32 reg = PIPESTAT(pipe);
  65
  66                 dev_priv->pipestat[pipe] |= mask;
  67                 /* Enable the interrupt, clear any pending status */
  68                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  69                 POSTING_READ(reg);
  70         }
  71 }
  72
  73 void
  74 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  75 {
  76         if ((dev_priv->pipestat[pipe] & mask) != 0) {
  77                 u32 reg = PIPESTAT(pipe);
  78
  79                 dev_priv->pipestat[pipe] &= ~mask;
  80                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
  81                 POSTING_READ(reg);
  82         }
  83 }
  84
  85 /**
  86  * intel_enable_asle - enable ASLE interrupt for OpRegion
  87  */
  88 void intel_enable_asle(struct drm_device *dev)
  89 {
  90         drm_i915_private_t *dev_priv = dev->dev_private;
  91         unsigned long irqflags;
  92
  93         /* FIXME: opregion/asle for VLV */
  94         if (IS_VALLEYVIEW(dev))
  95                 return;
  96
  97         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
  98
  99         if (HAS_PCH_SPLIT(dev))
 100                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 101         else {
 102                 i915_enable_pipestat(dev_priv, 1,
 103                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 104                 if (INTEL_INFO(dev)->gen >= 4)
 105                         i915_enable_pipestat(dev_priv, 0,
 106                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 107         }
 108
 109         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 110 }
 111
 112 /**
 113  * i915_pipe_enabled - check if a pipe is enabled
 114  * @dev: DRM device
 115  * @pipe: pipe to check
 116  *
 117  * Reading certain registers when the pipe is disabled can hang the chip.
 118  * Use this routine to make sure the PLL is running and the pipe is active
 119  * before reading such registers if unsure.
 120  */
 121 static int
 122 i915_pipe_enabled(struct drm_device *dev, int pipe)
 123 {
 124         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 125         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 126                                                                       pipe);
 127
 128         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 129 }
 130
 131 /* Called from drm generic code, passed a 'crtc', which
 132  * we use as a pipe index
 133  */
 134 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 135 {
 136         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 137         unsigned long high_frame;
 138         unsigned long low_frame;
 139         u32 high1, high2, low;
 140
 141         if (!i915_pipe_enabled(dev, pipe)) {
 142                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 143                                 "pipe %c\n", pipe_name(pipe));
 144                 return 0;
 145         }
 146
 147         high_frame = PIPEFRAME(pipe);
 148         low_frame = PIPEFRAMEPIXEL(pipe);
 149
 150         /*
 151          * High & low register fields aren't synchronized, so make sure
 152          * we get a low value that's stable across two reads of the high
 153          * register.
 154          */
 155         do {
 156                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 157                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 158                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 159         } while (high1 != high2);
 160
 161         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 162         low >>= PIPE_FRAME_LOW_SHIFT;
 163         return (high1 << 8) | low;
 164 }
 165
 166 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 167 {
 168         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 169         int reg = PIPE_FRMCOUNT_GM45(pipe);
 170
 171         if (!i915_pipe_enabled(dev, pipe)) {
 172                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 173                                  "pipe %c\n", pipe_name(pipe));
 174                 return 0;
 175         }
 176
 177         return I915_READ(reg);
 178 }
 179
 180 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 181                              int *vpos, int *hpos)
 182 {
 183         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 184         u32 vbl = 0, position = 0;
 185         int vbl_start, vbl_end, htotal, vtotal;
 186         bool in_vbl = true;
 187         int ret = 0;
 188         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 189                                                                       pipe);
 190
 191         if (!i915_pipe_enabled(dev, pipe)) {
 192                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 193                                  "pipe %c\n", pipe_name(pipe));
 194                 return 0;
 195         }
 196
 197         /* Get vtotal. */
 198         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 199
 200         if (INTEL_INFO(dev)->gen >= 4) {
 201                 /* No obvious pixelcount register. Only query vertical
 202                  * scanout position from Display scan line register.
 203                  */
 204                 position = I915_READ(PIPEDSL(pipe));
 205
 206                 /* Decode into vertical scanout position. Don't have
 207                  * horizontal scanout position.
 208                  */
 209                 *vpos = position & 0x1fff;
 210                 *hpos = 0;
 211         } else {
 212                 /* Have access to pixelcount since start of frame.
 213                  * We can split this into vertical and horizontal
 214                  * scanout position.
 215                  */
 216                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 217
 218                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 219                 *vpos = position / htotal;
 220                 *hpos = position - (*vpos * htotal);
 221         }
 222
 223         /* Query vblank area. */
 224         vbl = I915_READ(VBLANK(cpu_transcoder));
 225
 226         /* Test position against vblank region. */
 227         vbl_start = vbl & 0x1fff;
 228         vbl_end = (vbl >> 16) & 0x1fff;
 229
 230         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 231                 in_vbl = false;
 232
 233         /* Inside "upper part" of vblank area? Apply corrective offset: */
 234         if (in_vbl && (*vpos >= vbl_start))
 235                 *vpos = *vpos - vtotal;
 236
 237         /* Readouts valid? */
 238         if (vbl > 0)
 239                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 240
 241         /* In vblank? */
 242         if (in_vbl)
 243                 ret |= DRM_SCANOUTPOS_INVBL;
 244
 245         return ret;
 246 }
 247
 248 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 249                               int *max_error,
 250                               struct timeval *vblank_time,
 251                               unsigned flags)
 252 {
 253         struct drm_i915_private *dev_priv = dev->dev_private;
 254         struct drm_crtc *crtc;
 255
 256         if (pipe < 0 || pipe >= dev_priv->num_pipe) {
 257                 DRM_ERROR("Invalid crtc %d\n", pipe);
 258                 return -EINVAL;
 259         }
 260
 261         /* Get drm_crtc to timestamp: */
 262         crtc = intel_get_crtc_for_pipe(dev, pipe);
 263         if (crtc == NULL) {
 264                 DRM_ERROR("Invalid crtc %d\n", pipe);
 265                 return -EINVAL;
 266         }
 267
 268         if (!crtc->enabled) {
 269                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 270                 return -EBUSY;
 271         }
 272
 273         /* Helper routine in DRM core does all the work: */
 274         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 275                                                      vblank_time, flags,
 276                                                      crtc);
 277 }
 278
 279 /*
 280  * Handle hotplug events outside the interrupt handler proper.
 281  */
 282 static void i915_hotplug_work_func(struct work_struct *work)
 283 {
 284         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 285                                                     hotplug_work);
 286         struct drm_device *dev = dev_priv->dev;
 287         struct drm_mode_config *mode_config = &dev->mode_config;
 288         struct intel_encoder *encoder;
 289
 290         /* HPD irq before everything is fully set up. */
 291         if (!dev_priv->enable_hotplug_processing)
 292                 return;
 293
 294         mutex_lock(&mode_config->mutex);
 295         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 296
 297         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 298                 if (encoder->hot_plug)
 299                         encoder->hot_plug(encoder);
 300
 301         mutex_unlock(&mode_config->mutex);
 302
 303         /* Just fire off a uevent and let userspace tell us what to do */
 304         drm_helper_hpd_irq_event(dev);
 305 }
 306
 307 static void ironlake_handle_rps_change(struct drm_device *dev)
 308 {
 309         drm_i915_private_t *dev_priv = dev->dev_private;
 310         u32 busy_up, busy_down, max_avg, min_avg;
 311         u8 new_delay;
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&mchdev_lock, flags);
 315
 316         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 317
 318         new_delay = dev_priv->ips.cur_delay;
 319
 320         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 321         busy_up = I915_READ(RCPREVBSYTUPAVG);
 322         busy_down = I915_READ(RCPREVBSYTDNAVG);
 323         max_avg = I915_READ(RCBMAXAVG);
 324         min_avg = I915_READ(RCBMINAVG);
 325
 326         /* Handle RCS change request from hw */
 327         if (busy_up > max_avg) {
 328                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 329                         new_delay = dev_priv->ips.cur_delay - 1;
 330                 if (new_delay < dev_priv->ips.max_delay)
 331                         new_delay = dev_priv->ips.max_delay;
 332         } else if (busy_down < min_avg) {
 333                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 334                         new_delay = dev_priv->ips.cur_delay + 1;
 335                 if (new_delay > dev_priv->ips.min_delay)
 336                         new_delay = dev_priv->ips.min_delay;
 337         }
 338
 339         if (ironlake_set_drps(dev, new_delay))
 340                 dev_priv->ips.cur_delay = new_delay;
 341
 342         spin_unlock_irqrestore(&mchdev_lock, flags);
 343
 344         return;
 345 }
 346
 347 static void notify_ring(struct drm_device *dev,
 348                         struct intel_ring_buffer *ring)
 349 {
 350         struct drm_i915_private *dev_priv = dev->dev_private;
 351
 352         if (ring->obj == NULL)
 353                 return;
 354
 355         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 356
 357         wake_up_all(&ring->irq_queue);
 358         if (i915_enable_hangcheck) {
 359                 dev_priv->gpu_error.hangcheck_count = 0;
 360                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 361                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 362         }
 363 }
 364
 365 static void gen6_pm_rps_work(struct work_struct *work)
 366 {
 367         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 368                                                     rps.work);
 369         u32 pm_iir, pm_imr;
 370         u8 new_delay;
 371
 372         spin_lock_irq(&dev_priv->rps.lock);
 373         pm_iir = dev_priv->rps.pm_iir;
 374         dev_priv->rps.pm_iir = 0;
 375         pm_imr = I915_READ(GEN6_PMIMR);
 376         I915_WRITE(GEN6_PMIMR, 0);
 377         spin_unlock_irq(&dev_priv->rps.lock);
 378
 379         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 380                 return;
 381
 382         mutex_lock(&dev_priv->rps.hw_lock);
 383
 384         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 385                 new_delay = dev_priv->rps.cur_delay + 1;
 386         else
 387                 new_delay = dev_priv->rps.cur_delay - 1;
 388
 389         /* sysfs frequency interfaces may have snuck in while servicing the
 390          * interrupt
 391          */
 392         if (!(new_delay > dev_priv->rps.max_delay ||
 393               new_delay < dev_priv->rps.min_delay)) {
 394                 gen6_set_rps(dev_priv->dev, new_delay);
 395         }
 396
 397         mutex_unlock(&dev_priv->rps.hw_lock);
 398 }
 399
 400
 401 /**
 402  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 403  * occurred.
 404  * @work: workqueue struct
 405  *
 406  * Doesn't actually do anything except notify userspace. As a consequence of
 407  * this event, userspace should try to remap the bad rows since statistically
 408  * it is likely the same row is more likely to go bad again.
 409  */
 410 static void ivybridge_parity_work(struct work_struct *work)
 411 {
 412         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 413                                                     l3_parity.error_work);
 414         u32 error_status, row, bank, subbank;
 415         char *parity_event[5];
 416         uint32_t misccpctl;
 417         unsigned long flags;
 418
 419         /* We must turn off DOP level clock gating to access the L3 registers.
 420          * In order to prevent a get/put style interface, acquire struct mutex
 421          * any time we access those registers.
 422          */
 423         mutex_lock(&dev_priv->dev->struct_mutex);
 424
 425         misccpctl = I915_READ(GEN7_MISCCPCTL);
 426         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 427         POSTING_READ(GEN7_MISCCPCTL);
 428
 429         error_status = I915_READ(GEN7_L3CDERRST1);
 430         row = GEN7_PARITY_ERROR_ROW(error_status);
 431         bank = GEN7_PARITY_ERROR_BANK(error_status);
 432         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 433
 434         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 435                                     GEN7_L3CDERRST1_ENABLE);
 436         POSTING_READ(GEN7_L3CDERRST1);
 437
 438         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 439
 440         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 441         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 442         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 443         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 444
 445         mutex_unlock(&dev_priv->dev->struct_mutex);
 446
 447         parity_event[0] = "L3_PARITY_ERROR=1";
 448         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 449         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 450         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 451         parity_event[4] = NULL;
 452
 453         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 454                            KOBJ_CHANGE, parity_event);
 455
 456         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 457                   row, bank, subbank);
 458
 459         kfree(parity_event[3]);
 460         kfree(parity_event[2]);
 461         kfree(parity_event[1]);
 462 }
 463
 464 static void ivybridge_handle_parity_error(struct drm_device *dev)
 465 {
 466         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 467         unsigned long flags;
 468
 469         if (!HAS_L3_GPU_CACHE(dev))
 470                 return;
 471
 472         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 473         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 474         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 475         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 476
 477         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 478 }
 479
 480 static void snb_gt_irq_handler(struct drm_device *dev,
 481                                struct drm_i915_private *dev_priv,
 482                                u32 gt_iir)
 483 {
 484
 485         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 486                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 487                 notify_ring(dev, &dev_priv->ring[RCS]);
 488         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 489                 notify_ring(dev, &dev_priv->ring[VCS]);
 490         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 491                 notify_ring(dev, &dev_priv->ring[BCS]);
 492
 493         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 494                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 495                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 496                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 497                 i915_handle_error(dev, false);
 498         }
 499
 500         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 501                 ivybridge_handle_parity_error(dev);
 502 }
 503
 504 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 505                                 u32 pm_iir)
 506 {
 507         unsigned long flags;
 508
 509         /*
 510          * IIR bits should never already be set because IMR should
 511          * prevent an interrupt from being shown in IIR. The warning
 512          * displays a case where we've unsafely cleared
 513          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 514          * type is not a problem, it displays a problem in the logic.
 515          *
 516          * The mask bit in IMR is cleared by dev_priv->rps.work.
 517          */
 518
 519         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 520         dev_priv->rps.pm_iir |= pm_iir;
 521         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 522         POSTING_READ(GEN6_PMIMR);
 523         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 524
 525         queue_work(dev_priv->wq, &dev_priv->rps.work);
 526 }
 527
 528 static void gmbus_irq_handler(struct drm_device *dev)
 529 {
 530         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 531
 532         wake_up_all(&dev_priv->gmbus_wait_queue);
 533 }
 534
 535 static void dp_aux_irq_handler(struct drm_device *dev)
 536 {
 537         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 538
 539         wake_up_all(&dev_priv->gmbus_wait_queue);
 540 }
 541
 542 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 543 {
 544         struct drm_device *dev = (struct drm_device *) arg;
 545         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 546         u32 iir, gt_iir, pm_iir;
 547         irqreturn_t ret = IRQ_NONE;
 548         unsigned long irqflags;
 549         int pipe;
 550         u32 pipe_stats[I915_MAX_PIPES];
 551
 552         atomic_inc(&dev_priv->irq_received);
 553
 554         while (true) {
 555                 iir = I915_READ(VLV_IIR);
 556                 gt_iir = I915_READ(GTIIR);
 557                 pm_iir = I915_READ(GEN6_PMIIR);
 558
 559                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 560                         goto out;
 561
 562                 ret = IRQ_HANDLED;
 563
 564                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 565
 566                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 567                 for_each_pipe(pipe) {
 568                         int reg = PIPESTAT(pipe);
 569                         pipe_stats[pipe] = I915_READ(reg);
 570
 571                         /*
 572                          * Clear the PIPE*STAT regs before the IIR
 573                          */
 574                         if (pipe_stats[pipe] & 0x8000ffff) {
 575                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 576                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 577                                                          pipe_name(pipe));
 578                                 I915_WRITE(reg, pipe_stats[pipe]);
 579                         }
 580                 }
 581                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 582
 583                 for_each_pipe(pipe) {
 584                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 585                                 drm_handle_vblank(dev, pipe);
 586
 587                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 588                                 intel_prepare_page_flip(dev, pipe);
 589                                 intel_finish_page_flip(dev, pipe);
 590                         }
 591                 }
 592
 593                 /* Consume port.  Then clear IIR or we'll miss events */
 594                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 595                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 596
 597                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 598                                          hotplug_status);
 599                         if (hotplug_status & dev_priv->hotplug_supported_mask)
 600                                 queue_work(dev_priv->wq,
 601                                            &dev_priv->hotplug_work);
 602
 603                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 604                         I915_READ(PORT_HOTPLUG_STAT);
 605                 }
 606
 607                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 608                         gmbus_irq_handler(dev);
 609
 610                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 611                         gen6_queue_rps_work(dev_priv, pm_iir);
 612
 613                 I915_WRITE(GTIIR, gt_iir);
 614                 I915_WRITE(GEN6_PMIIR, pm_iir);
 615                 I915_WRITE(VLV_IIR, iir);
 616         }
 617
 618 out:
 619         return ret;
 620 }
 621
 622 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 623 {
 624         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 625         int pipe;
 626
 627         if (pch_iir & SDE_HOTPLUG_MASK)
 628                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 629
 630         if (pch_iir & SDE_AUDIO_POWER_MASK)
 631                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 632                                  (pch_iir & SDE_AUDIO_POWER_MASK) >>
 633                                  SDE_AUDIO_POWER_SHIFT);
 634
 635         if (pch_iir & SDE_AUX_MASK)
 636                 dp_aux_irq_handler(dev);
 637
 638         if (pch_iir & SDE_GMBUS)
 639                 gmbus_irq_handler(dev);
 640
 641         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 642                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 643
 644         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 645                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 646
 647         if (pch_iir & SDE_POISON)
 648                 DRM_ERROR("PCH poison interrupt\n");
 649
 650         if (pch_iir & SDE_FDI_MASK)
 651                 for_each_pipe(pipe)
 652                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 653                                          pipe_name(pipe),
 654                                          I915_READ(FDI_RX_IIR(pipe)));
 655
 656         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 657                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 658
 659         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 660                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 661
 662         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 663                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 664         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 665                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 666 }
 667
 668 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 669 {
 670         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 671         int pipe;
 672
 673         if (pch_iir & SDE_HOTPLUG_MASK_CPT)
 674                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 675
 676         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT)
 677                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 678                                  (pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 679                                  SDE_AUDIO_POWER_SHIFT_CPT);
 680
 681         if (pch_iir & SDE_AUX_MASK_CPT)
 682                 dp_aux_irq_handler(dev);
 683
 684         if (pch_iir & SDE_GMBUS_CPT)
 685                 gmbus_irq_handler(dev);
 686
 687         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 688                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 689
 690         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 691                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 692
 693         if (pch_iir & SDE_FDI_MASK_CPT)
 694                 for_each_pipe(pipe)
 695                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 696                                          pipe_name(pipe),
 697                                          I915_READ(FDI_RX_IIR(pipe)));
 698 }
 699
 700 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 701 {
 702         struct drm_device *dev = (struct drm_device *) arg;
 703         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 704         u32 de_iir, gt_iir, de_ier, pm_iir;
 705         irqreturn_t ret = IRQ_NONE;
 706         int i;
 707
 708         atomic_inc(&dev_priv->irq_received);
 709
 710         /* disable master interrupt before clearing iir  */
 711         de_ier = I915_READ(DEIER);
 712         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 713
 714         gt_iir = I915_READ(GTIIR);
 715         if (gt_iir) {
 716                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 717                 I915_WRITE(GTIIR, gt_iir);
 718                 ret = IRQ_HANDLED;
 719         }
 720
 721         de_iir = I915_READ(DEIIR);
 722         if (de_iir) {
 723                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 724                         dp_aux_irq_handler(dev);
 725
 726                 if (de_iir & DE_GSE_IVB)
 727                         intel_opregion_gse_intr(dev);
 728
 729                 for (i = 0; i < 3; i++) {
 730                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 731                                 drm_handle_vblank(dev, i);
 732                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 733                                 intel_prepare_page_flip(dev, i);
 734                                 intel_finish_page_flip_plane(dev, i);
 735                         }
 736                 }
 737
 738                 /* check event from PCH */
 739                 if (de_iir & DE_PCH_EVENT_IVB) {
 740                         u32 pch_iir = I915_READ(SDEIIR);
 741
 742                         cpt_irq_handler(dev, pch_iir);
 743
 744                         /* clear PCH hotplug event before clear CPU irq */
 745                         I915_WRITE(SDEIIR, pch_iir);
 746                 }
 747
 748                 I915_WRITE(DEIIR, de_iir);
 749                 ret = IRQ_HANDLED;
 750         }
 751
 752         pm_iir = I915_READ(GEN6_PMIIR);
 753         if (pm_iir) {
 754                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 755                         gen6_queue_rps_work(dev_priv, pm_iir);
 756                 I915_WRITE(GEN6_PMIIR, pm_iir);
 757                 ret = IRQ_HANDLED;
 758         }
 759
 760         I915_WRITE(DEIER, de_ier);
 761         POSTING_READ(DEIER);
 762
 763         return ret;
 764 }
 765
 766 static void ilk_gt_irq_handler(struct drm_device *dev,
 767                                struct drm_i915_private *dev_priv,
 768                                u32 gt_iir)
 769 {
 770         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 771                 notify_ring(dev, &dev_priv->ring[RCS]);
 772         if (gt_iir & GT_BSD_USER_INTERRUPT)
 773                 notify_ring(dev, &dev_priv->ring[VCS]);
 774 }
 775
 776 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 777 {
 778         struct drm_device *dev = (struct drm_device *) arg;
 779         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 780         int ret = IRQ_NONE;
 781         u32 de_iir, gt_iir, de_ier, pm_iir;
 782
 783         atomic_inc(&dev_priv->irq_received);
 784
 785         /* disable master interrupt before clearing iir  */
 786         de_ier = I915_READ(DEIER);
 787         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 788         POSTING_READ(DEIER);
 789
 790         de_iir = I915_READ(DEIIR);
 791         gt_iir = I915_READ(GTIIR);
 792         pm_iir = I915_READ(GEN6_PMIIR);
 793
 794         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 795                 goto done;
 796
 797         ret = IRQ_HANDLED;
 798
 799         if (IS_GEN5(dev))
 800                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 801         else
 802                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 803
 804         if (de_iir & DE_AUX_CHANNEL_A)
 805                 dp_aux_irq_handler(dev);
 806
 807         if (de_iir & DE_GSE)
 808                 intel_opregion_gse_intr(dev);
 809
 810         if (de_iir & DE_PIPEA_VBLANK)
 811                 drm_handle_vblank(dev, 0);
 812
 813         if (de_iir & DE_PIPEB_VBLANK)
 814                 drm_handle_vblank(dev, 1);
 815
 816         if (de_iir & DE_PLANEA_FLIP_DONE) {
 817                 intel_prepare_page_flip(dev, 0);
 818                 intel_finish_page_flip_plane(dev, 0);
 819         }
 820
 821         if (de_iir & DE_PLANEB_FLIP_DONE) {
 822                 intel_prepare_page_flip(dev, 1);
 823                 intel_finish_page_flip_plane(dev, 1);
 824         }
 825
 826         /* check event from PCH */
 827         if (de_iir & DE_PCH_EVENT) {
 828                 u32 pch_iir = I915_READ(SDEIIR);
 829
 830                 if (HAS_PCH_CPT(dev))
 831                         cpt_irq_handler(dev, pch_iir);
 832                 else
 833                         ibx_irq_handler(dev, pch_iir);
 834
 835                 /* should clear PCH hotplug event before clear CPU irq */
 836                 I915_WRITE(SDEIIR, pch_iir);
 837         }
 838
 839         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
 840                 ironlake_handle_rps_change(dev);
 841
 842         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
 843                 gen6_queue_rps_work(dev_priv, pm_iir);
 844
 845         I915_WRITE(GTIIR, gt_iir);
 846         I915_WRITE(DEIIR, de_iir);
 847         I915_WRITE(GEN6_PMIIR, pm_iir);
 848
 849 done:
 850         I915_WRITE(DEIER, de_ier);
 851         POSTING_READ(DEIER);
 852
 853         return ret;
 854 }
 855
 856 /**
 857  * i915_error_work_func - do process context error handling work
 858  * @work: work struct
 859  *
 860  * Fire an error uevent so userspace can see that a hang or error
 861  * was detected.
 862  */
 863 static void i915_error_work_func(struct work_struct *work)
 864 {
 865         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
 866                                                     work);
 867         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
 868                                                     gpu_error);
 869         struct drm_device *dev = dev_priv->dev;
 870         struct intel_ring_buffer *ring;
 871         char *error_event[] = { "ERROR=1", NULL };
 872         char *reset_event[] = { "RESET=1", NULL };
 873         char *reset_done_event[] = { "ERROR=0", NULL };
 874         int i, ret;
 875
 876         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
 877
 878         /*
 879          * Note that there's only one work item which does gpu resets, so we
 880          * need not worry about concurrent gpu resets potentially incrementing
 881          * error->reset_counter twice. We only need to take care of another
 882          * racing irq/hangcheck declaring the gpu dead for a second time. A
 883          * quick check for that is good enough: schedule_work ensures the
 884          * correct ordering between hang detection and this work item, and since
 885          * the reset in-progress bit is only ever set by code outside of this
 886          * work we don't need to worry about any other races.
 887          */
 888         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
 889                 DRM_DEBUG_DRIVER("resetting chip\n");
 890                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
 891                                    reset_event);
 892
 893                 ret = i915_reset(dev);
 894
 895                 if (ret == 0) {
 896                         /*
 897                          * After all the gem state is reset, increment the reset
 898                          * counter and wake up everyone waiting for the reset to
 899                          * complete.
 900                          *
 901                          * Since unlock operations are a one-sided barrier only,
 902                          * we need to insert a barrier here to order any seqno
 903                          * updates before
 904                          * the counter increment.
 905                          */
 906                         smp_mb__before_atomic_inc();
 907                         atomic_inc(&dev_priv->gpu_error.reset_counter);
 908
 909                         kobject_uevent_env(&dev->primary->kdev.kobj,
 910                                            KOBJ_CHANGE, reset_done_event);
 911                 } else {
 912                         atomic_set(&error->reset_counter, I915_WEDGED);
 913                 }
 914
 915                 for_each_ring(ring, dev_priv, i)
 916                         wake_up_all(&ring->irq_queue);
 917
 918                 wake_up_all(&dev_priv->gpu_error.reset_queue);
 919         }
 920 }
 921
 922 /* NB: please notice the memset */
 923 static void i915_get_extra_instdone(struct drm_device *dev,
 924                                     uint32_t *instdone)
 925 {
 926         struct drm_i915_private *dev_priv = dev->dev_private;
 927         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
 928
 929         switch(INTEL_INFO(dev)->gen) {
 930         case 2:
 931         case 3:
 932                 instdone[0] = I915_READ(INSTDONE);
 933                 break;
 934         case 4:
 935         case 5:
 936         case 6:
 937                 instdone[0] = I915_READ(INSTDONE_I965);
 938                 instdone[1] = I915_READ(INSTDONE1);
 939                 break;
 940         default:
 941                 WARN_ONCE(1, "Unsupported platform\n");
 942         case 7:
 943                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
 944                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
 945                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
 946                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
 947                 break;
 948         }
 949 }
 950
 951 #ifdef CONFIG_DEBUG_FS
 952 static struct drm_i915_error_object *
 953 i915_error_object_create(struct drm_i915_private *dev_priv,
 954                          struct drm_i915_gem_object *src)
 955 {
 956         struct drm_i915_error_object *dst;
 957         int i, count;
 958         u32 reloc_offset;
 959
 960         if (src == NULL || src->pages == NULL)
 961                 return NULL;
 962
 963         count = src->base.size / PAGE_SIZE;
 964
 965         dst = kmalloc(sizeof(*dst) + count * sizeof(u32 *), GFP_ATOMIC);
 966         if (dst == NULL)
 967                 return NULL;
 968
 969         reloc_offset = src->gtt_offset;
 970         for (i = 0; i < count; i++) {
 971                 unsigned long flags;
 972                 void *d;
 973
 974                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
 975                 if (d == NULL)
 976                         goto unwind;
 977
 978                 local_irq_save(flags);
 979                 if (reloc_offset < dev_priv->gtt.mappable_end &&
 980                     src->has_global_gtt_mapping) {
 981                         void __iomem *s;
 982
 983                         /* Simply ignore tiling or any overlapping fence.
 984                          * It's part of the error state, and this hopefully
 985                          * captures what the GPU read.
 986                          */
 987
 988                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
 989                                                      reloc_offset);
 990                         memcpy_fromio(d, s, PAGE_SIZE);
 991                         io_mapping_unmap_atomic(s);
 992                 } else if (src->stolen) {
 993                         unsigned long offset;
 994
 995                         offset = dev_priv->mm.stolen_base;
 996                         offset += src->stolen->start;
 997                         offset += i << PAGE_SHIFT;
 998
 999                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1000                 } else {
1001                         struct page *page;
1002                         void *s;
1003
1004                         page = i915_gem_object_get_page(src, i);
1005
1006                         drm_clflush_pages(&page, 1);
1007
1008                         s = kmap_atomic(page);
1009                         memcpy(d, s, PAGE_SIZE);
1010                         kunmap_atomic(s);
1011
1012                         drm_clflush_pages(&page, 1);
1013                 }
1014                 local_irq_restore(flags);
1015
1016                 dst->pages[i] = d;
1017
1018                 reloc_offset += PAGE_SIZE;
1019         }
1020         dst->page_count = count;
1021         dst->gtt_offset = src->gtt_offset;
1022
1023         return dst;
1024
1025 unwind:
1026         while (i--)
1027                 kfree(dst->pages[i]);
1028         kfree(dst);
1029         return NULL;
1030 }
1031
1032 static void
1033 i915_error_object_free(struct drm_i915_error_object *obj)
1034 {
1035         int page;
1036
1037         if (obj == NULL)
1038                 return;
1039
1040         for (page = 0; page < obj->page_count; page++)
1041                 kfree(obj->pages[page]);
1042
1043         kfree(obj);
1044 }
1045
1046 void
1047 i915_error_state_free(struct kref *error_ref)
1048 {
1049         struct drm_i915_error_state *error = container_of(error_ref,
1050                                                           typeof(*error), ref);
1051         int i;
1052
1053         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1054                 i915_error_object_free(error->ring[i].batchbuffer);
1055                 i915_error_object_free(error->ring[i].ringbuffer);
1056                 kfree(error->ring[i].requests);
1057         }
1058
1059         kfree(error->active_bo);
1060         kfree(error->overlay);
1061         kfree(error);
1062 }
1063 static void capture_bo(struct drm_i915_error_buffer *err,
1064                        struct drm_i915_gem_object *obj)
1065 {
1066         err->size = obj->base.size;
1067         err->name = obj->base.name;
1068         err->rseqno = obj->last_read_seqno;
1069         err->wseqno = obj->last_write_seqno;
1070         err->gtt_offset = obj->gtt_offset;
1071         err->read_domains = obj->base.read_domains;
1072         err->write_domain = obj->base.write_domain;
1073         err->fence_reg = obj->fence_reg;
1074         err->pinned = 0;
1075         if (obj->pin_count > 0)
1076                 err->pinned = 1;
1077         if (obj->user_pin_count > 0)
1078                 err->pinned = -1;
1079         err->tiling = obj->tiling_mode;
1080         err->dirty = obj->dirty;
1081         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1082         err->ring = obj->ring ? obj->ring->id : -1;
1083         err->cache_level = obj->cache_level;
1084 }
1085
1086 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1087                              int count, struct list_head *head)
1088 {
1089         struct drm_i915_gem_object *obj;
1090         int i = 0;
1091
1092         list_for_each_entry(obj, head, mm_list) {
1093                 capture_bo(err++, obj);
1094                 if (++i == count)
1095                         break;
1096         }
1097
1098         return i;
1099 }
1100
1101 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1102                              int count, struct list_head *head)
1103 {
1104         struct drm_i915_gem_object *obj;
1105         int i = 0;
1106
1107         list_for_each_entry(obj, head, gtt_list) {
1108                 if (obj->pin_count == 0)
1109                         continue;
1110
1111                 capture_bo(err++, obj);
1112                 if (++i == count)
1113                         break;
1114         }
1115
1116         return i;
1117 }
1118
1119 static void i915_gem_record_fences(struct drm_device *dev,
1120                                    struct drm_i915_error_state *error)
1121 {
1122         struct drm_i915_private *dev_priv = dev->dev_private;
1123         int i;
1124
1125         /* Fences */
1126         switch (INTEL_INFO(dev)->gen) {
1127         case 7:
1128         case 6:
1129                 for (i = 0; i < 16; i++)
1130                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1131                 break;
1132         case 5:
1133         case 4:
1134                 for (i = 0; i < 16; i++)
1135                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1136                 break;
1137         case 3:
1138                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1139                         for (i = 0; i < 8; i++)
1140                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1141         case 2:
1142                 for (i = 0; i < 8; i++)
1143                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1144                 break;
1145
1146         default:
1147                 BUG();
1148         }
1149 }
1150
1151 static struct drm_i915_error_object *
1152 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1153                              struct intel_ring_buffer *ring)
1154 {
1155         struct drm_i915_gem_object *obj;
1156         u32 seqno;
1157
1158         if (!ring->get_seqno)
1159                 return NULL;
1160
1161         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1162                 u32 acthd = I915_READ(ACTHD);
1163
1164                 if (WARN_ON(ring->id != RCS))
1165                         return NULL;
1166
1167                 obj = ring->private;
1168                 if (acthd >= obj->gtt_offset &&
1169                     acthd < obj->gtt_offset + obj->base.size)
1170                         return i915_error_object_create(dev_priv, obj);
1171         }
1172
1173         seqno = ring->get_seqno(ring, false);
1174         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1175                 if (obj->ring != ring)
1176                         continue;
1177
1178                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1179                         continue;
1180
1181                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1182                         continue;
1183
1184                 /* We need to copy these to an anonymous buffer as the simplest
1185                  * method to avoid being overwritten by userspace.
1186                  */
1187                 return i915_error_object_create(dev_priv, obj);
1188         }
1189
1190         return NULL;
1191 }
1192
1193 static void i915_record_ring_state(struct drm_device *dev,
1194                                    struct drm_i915_error_state *error,
1195                                    struct intel_ring_buffer *ring)
1196 {
1197         struct drm_i915_private *dev_priv = dev->dev_private;
1198
1199         if (INTEL_INFO(dev)->gen >= 6) {
1200                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1201                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1202                 error->semaphore_mboxes[ring->id][0]
1203                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1204                 error->semaphore_mboxes[ring->id][1]
1205                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1206                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1207                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1208         }
1209
1210         if (INTEL_INFO(dev)->gen >= 4) {
1211                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1212                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1213                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1214                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1215                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1216                 if (ring->id == RCS)
1217                         error->bbaddr = I915_READ64(BB_ADDR);
1218         } else {
1219                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1220                 error->ipeir[ring->id] = I915_READ(IPEIR);
1221                 error->ipehr[ring->id] = I915_READ(IPEHR);
1222                 error->instdone[ring->id] = I915_READ(INSTDONE);
1223         }
1224
1225         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1226         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1227         error->seqno[ring->id] = ring->get_seqno(ring, false);
1228         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1229         error->head[ring->id] = I915_READ_HEAD(ring);
1230         error->tail[ring->id] = I915_READ_TAIL(ring);
1231         error->ctl[ring->id] = I915_READ_CTL(ring);
1232
1233         error->cpu_ring_head[ring->id] = ring->head;
1234         error->cpu_ring_tail[ring->id] = ring->tail;
1235 }
1236
1237 static void i915_gem_record_rings(struct drm_device *dev,
1238                                   struct drm_i915_error_state *error)
1239 {
1240         struct drm_i915_private *dev_priv = dev->dev_private;
1241         struct intel_ring_buffer *ring;
1242         struct drm_i915_gem_request *request;
1243         int i, count;
1244
1245         for_each_ring(ring, dev_priv, i) {
1246                 i915_record_ring_state(dev, error, ring);
1247
1248                 error->ring[i].batchbuffer =
1249                         i915_error_first_batchbuffer(dev_priv, ring);
1250
1251                 error->ring[i].ringbuffer =
1252                         i915_error_object_create(dev_priv, ring->obj);
1253
1254                 count = 0;
1255                 list_for_each_entry(request, &ring->request_list, list)
1256                         count++;
1257
1258                 error->ring[i].num_requests = count;
1259                 error->ring[i].requests =
1260                         kmalloc(count*sizeof(struct drm_i915_error_request),
1261                                 GFP_ATOMIC);
1262                 if (error->ring[i].requests == NULL) {
1263                         error->ring[i].num_requests = 0;
1264                         continue;
1265                 }
1266
1267                 count = 0;
1268                 list_for_each_entry(request, &ring->request_list, list) {
1269                         struct drm_i915_error_request *erq;
1270
1271                         erq = &error->ring[i].requests[count++];
1272                         erq->seqno = request->seqno;
1273                         erq->jiffies = request->emitted_jiffies;
1274                         erq->tail = request->tail;
1275                 }
1276         }
1277 }
1278
1279 /**
1280  * i915_capture_error_state - capture an error record for later analysis
1281  * @dev: drm device
1282  *
1283  * Should be called when an error is detected (either a hang or an error
1284  * interrupt) to capture error state from the time of the error.  Fills
1285  * out a structure which becomes available in debugfs for user level tools
1286  * to pick up.
1287  */
1288 static void i915_capture_error_state(struct drm_device *dev)
1289 {
1290         struct drm_i915_private *dev_priv = dev->dev_private;
1291         struct drm_i915_gem_object *obj;
1292         struct drm_i915_error_state *error;
1293         unsigned long flags;
1294         int i, pipe;
1295
1296         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1297         error = dev_priv->gpu_error.first_error;
1298         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1299         if (error)
1300                 return;
1301
1302         /* Account for pipe specific data like PIPE*STAT */
1303         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1304         if (!error) {
1305                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1306                 return;
1307         }
1308
1309         DRM_INFO("capturing error event; look for more information in"
1310                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1311                  dev->primary->index);
1312
1313         kref_init(&error->ref);
1314         error->eir = I915_READ(EIR);
1315         error->pgtbl_er = I915_READ(PGTBL_ER);
1316         error->ccid = I915_READ(CCID);
1317
1318         if (HAS_PCH_SPLIT(dev))
1319                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1320         else if (IS_VALLEYVIEW(dev))
1321                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1322         else if (IS_GEN2(dev))
1323                 error->ier = I915_READ16(IER);
1324         else
1325                 error->ier = I915_READ(IER);
1326
1327         if (INTEL_INFO(dev)->gen >= 6)
1328                 error->derrmr = I915_READ(DERRMR);
1329
1330         if (IS_VALLEYVIEW(dev))
1331                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1332         else if (INTEL_INFO(dev)->gen >= 7)
1333                 error->forcewake = I915_READ(FORCEWAKE_MT);
1334         else if (INTEL_INFO(dev)->gen == 6)
1335                 error->forcewake = I915_READ(FORCEWAKE);
1336
1337         for_each_pipe(pipe)
1338                 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1339
1340         if (INTEL_INFO(dev)->gen >= 6) {
1341                 error->error = I915_READ(ERROR_GEN6);
1342                 error->done_reg = I915_READ(DONE_REG);
1343         }
1344
1345         if (INTEL_INFO(dev)->gen == 7)
1346                 error->err_int = I915_READ(GEN7_ERR_INT);
1347
1348         i915_get_extra_instdone(dev, error->extra_instdone);
1349
1350         i915_gem_record_fences(dev, error);
1351         i915_gem_record_rings(dev, error);
1352
1353         /* Record buffers on the active and pinned lists. */
1354         error->active_bo = NULL;
1355         error->pinned_bo = NULL;
1356
1357         i = 0;
1358         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1359                 i++;
1360         error->active_bo_count = i;
1361         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1362                 if (obj->pin_count)
1363                         i++;
1364         error->pinned_bo_count = i - error->active_bo_count;
1365
1366         error->active_bo = NULL;
1367         error->pinned_bo = NULL;
1368         if (i) {
1369                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1370                                            GFP_ATOMIC);
1371                 if (error->active_bo)
1372                         error->pinned_bo =
1373                                 error->active_bo + error->active_bo_count;
1374         }
1375
1376         if (error->active_bo)
1377                 error->active_bo_count =
1378                         capture_active_bo(error->active_bo,
1379                                           error->active_bo_count,
1380                                           &dev_priv->mm.active_list);
1381
1382         if (error->pinned_bo)
1383                 error->pinned_bo_count =
1384                         capture_pinned_bo(error->pinned_bo,
1385                                           error->pinned_bo_count,
1386                                           &dev_priv->mm.bound_list);
1387
1388         do_gettimeofday(&error->time);
1389
1390         error->overlay = intel_overlay_capture_error_state(dev);
1391         error->display = intel_display_capture_error_state(dev);
1392
1393         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1394         if (dev_priv->gpu_error.first_error == NULL) {
1395                 dev_priv->gpu_error.first_error = error;
1396                 error = NULL;
1397         }
1398         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1399
1400         if (error)
1401                 i915_error_state_free(&error->ref);
1402 }
1403
1404 void i915_destroy_error_state(struct drm_device *dev)
1405 {
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         struct drm_i915_error_state *error;
1408         unsigned long flags;
1409
1410         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1411         error = dev_priv->gpu_error.first_error;
1412         dev_priv->gpu_error.first_error = NULL;
1413         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1414
1415         if (error)
1416                 kref_put(&error->ref, i915_error_state_free);
1417 }
1418 #else
1419 #define i915_capture_error_state(x)
1420 #endif
1421
1422 static void i915_report_and_clear_eir(struct drm_device *dev)
1423 {
1424         struct drm_i915_private *dev_priv = dev->dev_private;
1425         uint32_t instdone[I915_NUM_INSTDONE_REG];
1426         u32 eir = I915_READ(EIR);
1427         int pipe, i;
1428
1429         if (!eir)
1430                 return;
1431
1432         pr_err("render error detected, EIR: 0x%08x\n", eir);
1433
1434         i915_get_extra_instdone(dev, instdone);
1435
1436         if (IS_G4X(dev)) {
1437                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1438                         u32 ipeir = I915_READ(IPEIR_I965);
1439
1440                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1441                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1442                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1443                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1444                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1445                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1446                         I915_WRITE(IPEIR_I965, ipeir);
1447                         POSTING_READ(IPEIR_I965);
1448                 }
1449                 if (eir & GM45_ERROR_PAGE_TABLE) {
1450                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1451                         pr_err("page table error\n");
1452                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1453                         I915_WRITE(PGTBL_ER, pgtbl_err);
1454                         POSTING_READ(PGTBL_ER);
1455                 }
1456         }
1457
1458         if (!IS_GEN2(dev)) {
1459                 if (eir & I915_ERROR_PAGE_TABLE) {
1460                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1461                         pr_err("page table error\n");
1462                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1463                         I915_WRITE(PGTBL_ER, pgtbl_err);
1464                         POSTING_READ(PGTBL_ER);
1465                 }
1466         }
1467
1468         if (eir & I915_ERROR_MEMORY_REFRESH) {
1469                 pr_err("memory refresh error:\n");
1470                 for_each_pipe(pipe)
1471                         pr_err("pipe %c stat: 0x%08x\n",
1472                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1473                 /* pipestat has already been acked */
1474         }
1475         if (eir & I915_ERROR_INSTRUCTION) {
1476                 pr_err("instruction error\n");
1477                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1478                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1479                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1480                 if (INTEL_INFO(dev)->gen < 4) {
1481                         u32 ipeir = I915_READ(IPEIR);
1482
1483                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1484                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1485                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1486                         I915_WRITE(IPEIR, ipeir);
1487                         POSTING_READ(IPEIR);
1488                 } else {
1489                         u32 ipeir = I915_READ(IPEIR_I965);
1490
1491                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1492                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1493                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1494                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1495                         I915_WRITE(IPEIR_I965, ipeir);
1496                         POSTING_READ(IPEIR_I965);
1497                 }
1498         }
1499
1500         I915_WRITE(EIR, eir);
1501         POSTING_READ(EIR);
1502         eir = I915_READ(EIR);
1503         if (eir) {
1504                 /*
1505                  * some errors might have become stuck,
1506                  * mask them.
1507                  */
1508                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1509                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1510                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1511         }
1512 }
1513
1514 /**
1515  * i915_handle_error - handle an error interrupt
1516  * @dev: drm device
1517  *
1518  * Do some basic checking of regsiter state at error interrupt time and
1519  * dump it to the syslog.  Also call i915_capture_error_state() to make
1520  * sure we get a record and make it available in debugfs.  Fire a uevent
1521  * so userspace knows something bad happened (should trigger collection
1522  * of a ring dump etc.).
1523  */
1524 void i915_handle_error(struct drm_device *dev, bool wedged)
1525 {
1526         struct drm_i915_private *dev_priv = dev->dev_private;
1527         struct intel_ring_buffer *ring;
1528         int i;
1529
1530         i915_capture_error_state(dev);
1531         i915_report_and_clear_eir(dev);
1532
1533         if (wedged) {
1534                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1535                                 &dev_priv->gpu_error.reset_counter);
1536
1537                 /*
1538                  * Wakeup waiting processes so that the reset work item
1539                  * doesn't deadlock trying to grab various locks.
1540                  */
1541                 for_each_ring(ring, dev_priv, i)
1542                         wake_up_all(&ring->irq_queue);
1543         }
1544
1545         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1546 }
1547
1548 static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1549 {
1550         drm_i915_private_t *dev_priv = dev->dev_private;
1551         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1552         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1553         struct drm_i915_gem_object *obj;
1554         struct intel_unpin_work *work;
1555         unsigned long flags;
1556         bool stall_detected;
1557
1558         /* Ignore early vblank irqs */
1559         if (intel_crtc == NULL)
1560                 return;
1561
1562         spin_lock_irqsave(&dev->event_lock, flags);
1563         work = intel_crtc->unpin_work;
1564
1565         if (work == NULL ||
1566             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1567             !work->enable_stall_check) {
1568                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1569                 spin_unlock_irqrestore(&dev->event_lock, flags);
1570                 return;
1571         }
1572
1573         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1574         obj = work->pending_flip_obj;
1575         if (INTEL_INFO(dev)->gen >= 4) {
1576                 int dspsurf = DSPSURF(intel_crtc->plane);
1577                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1578                                         obj->gtt_offset;
1579         } else {
1580                 int dspaddr = DSPADDR(intel_crtc->plane);
1581                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1582                                                         crtc->y * crtc->fb->pitches[0] +
1583                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1584         }
1585
1586         spin_unlock_irqrestore(&dev->event_lock, flags);
1587
1588         if (stall_detected) {
1589                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1590                 intel_prepare_page_flip(dev, intel_crtc->plane);
1591         }
1592 }
1593
1594 /* Called from drm generic code, passed 'crtc' which
1595  * we use as a pipe index
1596  */
1597 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1598 {
1599         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1600         unsigned long irqflags;
1601
1602         if (!i915_pipe_enabled(dev, pipe))
1603                 return -EINVAL;
1604
1605         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1606         if (INTEL_INFO(dev)->gen >= 4)
1607                 i915_enable_pipestat(dev_priv, pipe,
1608                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1609         else
1610                 i915_enable_pipestat(dev_priv, pipe,
1611                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1612
1613         /* maintain vblank delivery even in deep C-states */
1614         if (dev_priv->info->gen == 3)
1615                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1616         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1617
1618         return 0;
1619 }
1620
1621 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1622 {
1623         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1624         unsigned long irqflags;
1625
1626         if (!i915_pipe_enabled(dev, pipe))
1627                 return -EINVAL;
1628
1629         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1630         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1631                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1632         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1633
1634         return 0;
1635 }
1636
1637 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1638 {
1639         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1640         unsigned long irqflags;
1641
1642         if (!i915_pipe_enabled(dev, pipe))
1643                 return -EINVAL;
1644
1645         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1646         ironlake_enable_display_irq(dev_priv,
1647                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1648         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1649
1650         return 0;
1651 }
1652
1653 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1654 {
1655         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1656         unsigned long irqflags;
1657         u32 imr;
1658
1659         if (!i915_pipe_enabled(dev, pipe))
1660                 return -EINVAL;
1661
1662         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1663         imr = I915_READ(VLV_IMR);
1664         if (pipe == 0)
1665                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1666         else
1667                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1668         I915_WRITE(VLV_IMR, imr);
1669         i915_enable_pipestat(dev_priv, pipe,
1670                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1671         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1672
1673         return 0;
1674 }
1675
1676 /* Called from drm generic code, passed 'crtc' which
1677  * we use as a pipe index
1678  */
1679 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1680 {
1681         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1682         unsigned long irqflags;
1683
1684         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1685         if (dev_priv->info->gen == 3)
1686                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1687
1688         i915_disable_pipestat(dev_priv, pipe,
1689                               PIPE_VBLANK_INTERRUPT_ENABLE |
1690                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1691         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1692 }
1693
1694 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1695 {
1696         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1697         unsigned long irqflags;
1698
1699         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1700         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1701                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1702         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1703 }
1704
1705 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1706 {
1707         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1708         unsigned long irqflags;
1709
1710         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1711         ironlake_disable_display_irq(dev_priv,
1712                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1713         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1714 }
1715
1716 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1717 {
1718         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1719         unsigned long irqflags;
1720         u32 imr;
1721
1722         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1723         i915_disable_pipestat(dev_priv, pipe,
1724                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1725         imr = I915_READ(VLV_IMR);
1726         if (pipe == 0)
1727                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1728         else
1729                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1730         I915_WRITE(VLV_IMR, imr);
1731         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1732 }
1733
1734 static u32
1735 ring_last_seqno(struct intel_ring_buffer *ring)
1736 {
1737         return list_entry(ring->request_list.prev,
1738                           struct drm_i915_gem_request, list)->seqno;
1739 }
1740
1741 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1742 {
1743         if (list_empty(&ring->request_list) ||
1744             i915_seqno_passed(ring->get_seqno(ring, false),
1745                               ring_last_seqno(ring))) {
1746                 /* Issue a wake-up to catch stuck h/w. */
1747                 if (waitqueue_active(&ring->irq_queue)) {
1748                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1749                                   ring->name);
1750                         wake_up_all(&ring->irq_queue);
1751                         *err = true;
1752                 }
1753                 return true;
1754         }
1755         return false;
1756 }
1757
1758 static bool kick_ring(struct intel_ring_buffer *ring)
1759 {
1760         struct drm_device *dev = ring->dev;
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762         u32 tmp = I915_READ_CTL(ring);
1763         if (tmp & RING_WAIT) {
1764                 DRM_ERROR("Kicking stuck wait on %s\n",
1765                           ring->name);
1766                 I915_WRITE_CTL(ring, tmp);
1767                 return true;
1768         }
1769         return false;
1770 }
1771
1772 static bool i915_hangcheck_hung(struct drm_device *dev)
1773 {
1774         drm_i915_private_t *dev_priv = dev->dev_private;
1775
1776         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
1777                 bool hung = true;
1778
1779                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1780                 i915_handle_error(dev, true);
1781
1782                 if (!IS_GEN2(dev)) {
1783                         struct intel_ring_buffer *ring;
1784                         int i;
1785
1786                         /* Is the chip hanging on a WAIT_FOR_EVENT?
1787                          * If so we can simply poke the RB_WAIT bit
1788                          * and break the hang. This should work on
1789                          * all but the second generation chipsets.
1790                          */
1791                         for_each_ring(ring, dev_priv, i)
1792                                 hung &= !kick_ring(ring);
1793                 }
1794
1795                 return hung;
1796         }
1797
1798         return false;
1799 }
1800
1801 /**
1802  * This is called when the chip hasn't reported back with completed
1803  * batchbuffers in a long time. The first time this is called we simply record
1804  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1805  * again, we assume the chip is wedged and try to fix it.
1806  */
1807 void i915_hangcheck_elapsed(unsigned long data)
1808 {
1809         struct drm_device *dev = (struct drm_device *)data;
1810         drm_i915_private_t *dev_priv = dev->dev_private;
1811         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
1812         struct intel_ring_buffer *ring;
1813         bool err = false, idle;
1814         int i;
1815
1816         if (!i915_enable_hangcheck)
1817                 return;
1818
1819         memset(acthd, 0, sizeof(acthd));
1820         idle = true;
1821         for_each_ring(ring, dev_priv, i) {
1822             idle &= i915_hangcheck_ring_idle(ring, &err);
1823             acthd[i] = intel_ring_get_active_head(ring);
1824         }
1825
1826         /* If all work is done then ACTHD clearly hasn't advanced. */
1827         if (idle) {
1828                 if (err) {
1829                         if (i915_hangcheck_hung(dev))
1830                                 return;
1831
1832                         goto repeat;
1833                 }
1834
1835                 dev_priv->gpu_error.hangcheck_count = 0;
1836                 return;
1837         }
1838
1839         i915_get_extra_instdone(dev, instdone);
1840         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
1841                    sizeof(acthd)) == 0 &&
1842             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
1843                    sizeof(instdone)) == 0) {
1844                 if (i915_hangcheck_hung(dev))
1845                         return;
1846         } else {
1847                 dev_priv->gpu_error.hangcheck_count = 0;
1848
1849                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
1850                        sizeof(acthd));
1851                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
1852                        sizeof(instdone));
1853         }
1854
1855 repeat:
1856         /* Reset timer case chip hangs without another request being added */
1857         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
1858                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
1859 }
1860
1861 /* drm_dma.h hooks
1862 */
1863 static void ironlake_irq_preinstall(struct drm_device *dev)
1864 {
1865         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1866
1867         atomic_set(&dev_priv->irq_received, 0);
1868
1869         I915_WRITE(HWSTAM, 0xeffe);
1870
1871         /* XXX hotplug from PCH */
1872
1873         I915_WRITE(DEIMR, 0xffffffff);
1874         I915_WRITE(DEIER, 0x0);
1875         POSTING_READ(DEIER);
1876
1877         /* and GT */
1878         I915_WRITE(GTIMR, 0xffffffff);
1879         I915_WRITE(GTIER, 0x0);
1880         POSTING_READ(GTIER);
1881
1882         /* south display irq */
1883         I915_WRITE(SDEIMR, 0xffffffff);
1884         I915_WRITE(SDEIER, 0x0);
1885         POSTING_READ(SDEIER);
1886 }
1887
1888 static void valleyview_irq_preinstall(struct drm_device *dev)
1889 {
1890         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1891         int pipe;
1892
1893         atomic_set(&dev_priv->irq_received, 0);
1894
1895         /* VLV magic */
1896         I915_WRITE(VLV_IMR, 0);
1897         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1898         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1899         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1900
1901         /* and GT */
1902         I915_WRITE(GTIIR, I915_READ(GTIIR));
1903         I915_WRITE(GTIIR, I915_READ(GTIIR));
1904         I915_WRITE(GTIMR, 0xffffffff);
1905         I915_WRITE(GTIER, 0x0);
1906         POSTING_READ(GTIER);
1907
1908         I915_WRITE(DPINVGTT, 0xff);
1909
1910         I915_WRITE(PORT_HOTPLUG_EN, 0);
1911         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1912         for_each_pipe(pipe)
1913                 I915_WRITE(PIPESTAT(pipe), 0xffff);
1914         I915_WRITE(VLV_IIR, 0xffffffff);
1915         I915_WRITE(VLV_IMR, 0xffffffff);
1916         I915_WRITE(VLV_IER, 0x0);
1917         POSTING_READ(VLV_IER);
1918 }
1919
1920 /*
1921  * Enable digital hotplug on the PCH, and configure the DP short pulse
1922  * duration to 2ms (which is the minimum in the Display Port spec)
1923  *
1924  * This register is the same on all known PCH chips.
1925  */
1926
1927 static void ibx_enable_hotplug(struct drm_device *dev)
1928 {
1929         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1930         u32     hotplug;
1931
1932         hotplug = I915_READ(PCH_PORT_HOTPLUG);
1933         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1934         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1935         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1936         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1937         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1938 }
1939
1940 static void ibx_irq_postinstall(struct drm_device *dev)
1941 {
1942         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1943         u32 mask;
1944
1945         if (HAS_PCH_IBX(dev))
1946                 mask = SDE_HOTPLUG_MASK |
1947                        SDE_GMBUS |
1948                        SDE_AUX_MASK;
1949         else
1950                 mask = SDE_HOTPLUG_MASK_CPT |
1951                        SDE_GMBUS_CPT |
1952                        SDE_AUX_MASK_CPT;
1953
1954         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1955         I915_WRITE(SDEIMR, ~mask);
1956         I915_WRITE(SDEIER, mask);
1957         POSTING_READ(SDEIER);
1958
1959         ibx_enable_hotplug(dev);
1960 }
1961
1962 static int ironlake_irq_postinstall(struct drm_device *dev)
1963 {
1964         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1965         /* enable kind of interrupts always enabled */
1966         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1967                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
1968                            DE_AUX_CHANNEL_A;
1969         u32 render_irqs;
1970
1971         dev_priv->irq_mask = ~display_mask;
1972
1973         /* should always can generate irq */
1974         I915_WRITE(DEIIR, I915_READ(DEIIR));
1975         I915_WRITE(DEIMR, dev_priv->irq_mask);
1976         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
1977         POSTING_READ(DEIER);
1978
1979         dev_priv->gt_irq_mask = ~0;
1980
1981         I915_WRITE(GTIIR, I915_READ(GTIIR));
1982         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1983
1984         if (IS_GEN6(dev))
1985                 render_irqs =
1986                         GT_USER_INTERRUPT |
1987                         GEN6_BSD_USER_INTERRUPT |
1988                         GEN6_BLITTER_USER_INTERRUPT;
1989         else
1990                 render_irqs =
1991                         GT_USER_INTERRUPT |
1992                         GT_PIPE_NOTIFY |
1993                         GT_BSD_USER_INTERRUPT;
1994         I915_WRITE(GTIER, render_irqs);
1995         POSTING_READ(GTIER);
1996
1997         ibx_irq_postinstall(dev);
1998
1999         if (IS_IRONLAKE_M(dev)) {
2000                 /* Clear & enable PCU event interrupts */
2001                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2002                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2003                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int ivybridge_irq_postinstall(struct drm_device *dev)
2010 {
2011         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2012         /* enable kind of interrupts always enabled */
2013         u32 display_mask =
2014                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2015                 DE_PLANEC_FLIP_DONE_IVB |
2016                 DE_PLANEB_FLIP_DONE_IVB |
2017                 DE_PLANEA_FLIP_DONE_IVB |
2018                 DE_AUX_CHANNEL_A_IVB;
2019         u32 render_irqs;
2020
2021         dev_priv->irq_mask = ~display_mask;
2022
2023         /* should always can generate irq */
2024         I915_WRITE(DEIIR, I915_READ(DEIIR));
2025         I915_WRITE(DEIMR, dev_priv->irq_mask);
2026         I915_WRITE(DEIER,
2027                    display_mask |
2028                    DE_PIPEC_VBLANK_IVB |
2029                    DE_PIPEB_VBLANK_IVB |
2030                    DE_PIPEA_VBLANK_IVB);
2031         POSTING_READ(DEIER);
2032
2033         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2034
2035         I915_WRITE(GTIIR, I915_READ(GTIIR));
2036         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2037
2038         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2039                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2040         I915_WRITE(GTIER, render_irqs);
2041         POSTING_READ(GTIER);
2042
2043         ibx_irq_postinstall(dev);
2044
2045         return 0;
2046 }
2047
2048 static int valleyview_irq_postinstall(struct drm_device *dev)
2049 {
2050         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2051         u32 enable_mask;
2052         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2053         u32 render_irqs;
2054         u16 msid;
2055
2056         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2057         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2058                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2059                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2060                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2061
2062         /*
2063          *Leave vblank interrupts masked initially.  enable/disable will
2064          * toggle them based on usage.
2065          */
2066         dev_priv->irq_mask = (~enable_mask) |
2067                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2068                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2069
2070         dev_priv->pipestat[0] = 0;
2071         dev_priv->pipestat[1] = 0;
2072
2073         /* Hack for broken MSIs on VLV */
2074         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2075         pci_read_config_word(dev->pdev, 0x98, &msid);
2076         msid &= 0xff; /* mask out delivery bits */
2077         msid |= (1<<14);
2078         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2079
2080         I915_WRITE(PORT_HOTPLUG_EN, 0);
2081         POSTING_READ(PORT_HOTPLUG_EN);
2082
2083         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2084         I915_WRITE(VLV_IER, enable_mask);
2085         I915_WRITE(VLV_IIR, 0xffffffff);
2086         I915_WRITE(PIPESTAT(0), 0xffff);
2087         I915_WRITE(PIPESTAT(1), 0xffff);
2088         POSTING_READ(VLV_IER);
2089
2090         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2091         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2092         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2093
2094         I915_WRITE(VLV_IIR, 0xffffffff);
2095         I915_WRITE(VLV_IIR, 0xffffffff);
2096
2097         I915_WRITE(GTIIR, I915_READ(GTIIR));
2098         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2099
2100         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2101                 GEN6_BLITTER_USER_INTERRUPT;
2102         I915_WRITE(GTIER, render_irqs);
2103         POSTING_READ(GTIER);
2104
2105         /* ack & enable invalid PTE error interrupts */
2106 #if 0 /* FIXME: add support to irq handler for checking these bits */
2107         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2108         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2109 #endif
2110
2111         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2112
2113         return 0;
2114 }
2115
2116 static void valleyview_hpd_irq_setup(struct drm_device *dev)
2117 {
2118         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2119         u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2120
2121         /* Note HDMI and DP share bits */
2122         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2123                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2124         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2125                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2126         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2127                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2128         if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2129                 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2130         if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2131                 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2132         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2133                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2134                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2135         }
2136
2137         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2138 }
2139
2140 static void valleyview_irq_uninstall(struct drm_device *dev)
2141 {
2142         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2143         int pipe;
2144
2145         if (!dev_priv)
2146                 return;
2147
2148         for_each_pipe(pipe)
2149                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2150
2151         I915_WRITE(HWSTAM, 0xffffffff);
2152         I915_WRITE(PORT_HOTPLUG_EN, 0);
2153         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2154         for_each_pipe(pipe)
2155                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2156         I915_WRITE(VLV_IIR, 0xffffffff);
2157         I915_WRITE(VLV_IMR, 0xffffffff);
2158         I915_WRITE(VLV_IER, 0x0);
2159         POSTING_READ(VLV_IER);
2160 }
2161
2162 static void ironlake_irq_uninstall(struct drm_device *dev)
2163 {
2164         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2165
2166         if (!dev_priv)
2167                 return;
2168
2169         I915_WRITE(HWSTAM, 0xffffffff);
2170
2171         I915_WRITE(DEIMR, 0xffffffff);
2172         I915_WRITE(DEIER, 0x0);
2173         I915_WRITE(DEIIR, I915_READ(DEIIR));
2174
2175         I915_WRITE(GTIMR, 0xffffffff);
2176         I915_WRITE(GTIER, 0x0);
2177         I915_WRITE(GTIIR, I915_READ(GTIIR));
2178
2179         I915_WRITE(SDEIMR, 0xffffffff);
2180         I915_WRITE(SDEIER, 0x0);
2181         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2182 }
2183
2184 static void i8xx_irq_preinstall(struct drm_device * dev)
2185 {
2186         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2187         int pipe;
2188
2189         atomic_set(&dev_priv->irq_received, 0);
2190
2191         for_each_pipe(pipe)
2192                 I915_WRITE(PIPESTAT(pipe), 0);
2193         I915_WRITE16(IMR, 0xffff);
2194         I915_WRITE16(IER, 0x0);
2195         POSTING_READ16(IER);
2196 }
2197
2198 static int i8xx_irq_postinstall(struct drm_device *dev)
2199 {
2200         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2201
2202         dev_priv->pipestat[0] = 0;
2203         dev_priv->pipestat[1] = 0;
2204
2205         I915_WRITE16(EMR,
2206                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2207
2208         /* Unmask the interrupts that we always want on. */
2209         dev_priv->irq_mask =
2210                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2211                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2212                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2213                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2214                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2215         I915_WRITE16(IMR, dev_priv->irq_mask);
2216
2217         I915_WRITE16(IER,
2218                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2219                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2220                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2221                      I915_USER_INTERRUPT);
2222         POSTING_READ16(IER);
2223
2224         return 0;
2225 }
2226
2227 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2228 {
2229         struct drm_device *dev = (struct drm_device *) arg;
2230         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2231         u16 iir, new_iir;
2232         u32 pipe_stats[2];
2233         unsigned long irqflags;
2234         int irq_received;
2235         int pipe;
2236         u16 flip_mask =
2237                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2238                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2239
2240         atomic_inc(&dev_priv->irq_received);
2241
2242         iir = I915_READ16(IIR);
2243         if (iir == 0)
2244                 return IRQ_NONE;
2245
2246         while (iir & ~flip_mask) {
2247                 /* Can't rely on pipestat interrupt bit in iir as it might
2248                  * have been cleared after the pipestat interrupt was received.
2249                  * It doesn't set the bit in iir again, but it still produces
2250                  * interrupts (for non-MSI).
2251                  */
2252                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2253                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2254                         i915_handle_error(dev, false);
2255
2256                 for_each_pipe(pipe) {
2257                         int reg = PIPESTAT(pipe);
2258                         pipe_stats[pipe] = I915_READ(reg);
2259
2260                         /*
2261                          * Clear the PIPE*STAT regs before the IIR
2262                          */
2263                         if (pipe_stats[pipe] & 0x8000ffff) {
2264                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2265                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2266                                                          pipe_name(pipe));
2267                                 I915_WRITE(reg, pipe_stats[pipe]);
2268                                 irq_received = 1;
2269                         }
2270                 }
2271                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2272
2273                 I915_WRITE16(IIR, iir & ~flip_mask);
2274                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2275
2276                 i915_update_dri1_breadcrumb(dev);
2277
2278                 if (iir & I915_USER_INTERRUPT)
2279                         notify_ring(dev, &dev_priv->ring[RCS]);
2280
2281                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2282                     drm_handle_vblank(dev, 0)) {
2283                         if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2284                                 intel_prepare_page_flip(dev, 0);
2285                                 intel_finish_page_flip(dev, 0);
2286                                 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2287                         }
2288                 }
2289
2290                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2291                     drm_handle_vblank(dev, 1)) {
2292                         if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2293                                 intel_prepare_page_flip(dev, 1);
2294                                 intel_finish_page_flip(dev, 1);
2295                                 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2296                         }
2297                 }
2298
2299                 iir = new_iir;
2300         }
2301
2302         return IRQ_HANDLED;
2303 }
2304
2305 static void i8xx_irq_uninstall(struct drm_device * dev)
2306 {
2307         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2308         int pipe;
2309
2310         for_each_pipe(pipe) {
2311                 /* Clear enable bits; then clear status bits */
2312                 I915_WRITE(PIPESTAT(pipe), 0);
2313                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2314         }
2315         I915_WRITE16(IMR, 0xffff);
2316         I915_WRITE16(IER, 0x0);
2317         I915_WRITE16(IIR, I915_READ16(IIR));
2318 }
2319
2320 static void i915_irq_preinstall(struct drm_device * dev)
2321 {
2322         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2323         int pipe;
2324
2325         atomic_set(&dev_priv->irq_received, 0);
2326
2327         if (I915_HAS_HOTPLUG(dev)) {
2328                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2329                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2330         }
2331
2332         I915_WRITE16(HWSTAM, 0xeffe);
2333         for_each_pipe(pipe)
2334                 I915_WRITE(PIPESTAT(pipe), 0);
2335         I915_WRITE(IMR, 0xffffffff);
2336         I915_WRITE(IER, 0x0);
2337         POSTING_READ(IER);
2338 }
2339
2340 static int i915_irq_postinstall(struct drm_device *dev)
2341 {
2342         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2343         u32 enable_mask;
2344
2345         dev_priv->pipestat[0] = 0;
2346         dev_priv->pipestat[1] = 0;
2347
2348         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2349
2350         /* Unmask the interrupts that we always want on. */
2351         dev_priv->irq_mask =
2352                 ~(I915_ASLE_INTERRUPT |
2353                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2354                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2355                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2356                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2357                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2358
2359         enable_mask =
2360                 I915_ASLE_INTERRUPT |
2361                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2362                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2363                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2364                 I915_USER_INTERRUPT;
2365
2366         if (I915_HAS_HOTPLUG(dev)) {
2367                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2368                 POSTING_READ(PORT_HOTPLUG_EN);
2369
2370                 /* Enable in IER... */
2371                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2372                 /* and unmask in IMR */
2373                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2374         }
2375
2376         I915_WRITE(IMR, dev_priv->irq_mask);
2377         I915_WRITE(IER, enable_mask);
2378         POSTING_READ(IER);
2379
2380         intel_opregion_enable_asle(dev);
2381
2382         return 0;
2383 }
2384
2385 static void i915_hpd_irq_setup(struct drm_device *dev)
2386 {
2387         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2388         u32 hotplug_en;
2389
2390         if (I915_HAS_HOTPLUG(dev)) {
2391                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2392
2393                 if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2394                         hotplug_en |= PORTB_HOTPLUG_INT_EN;
2395                 if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2396                         hotplug_en |= PORTC_HOTPLUG_INT_EN;
2397                 if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2398                         hotplug_en |= PORTD_HOTPLUG_INT_EN;
2399                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I915)
2400                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2401                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I915)
2402                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2403                 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2404                         hotplug_en |= CRT_HOTPLUG_INT_EN;
2405                         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2406                 }
2407
2408                 /* Ignore TV since it's buggy */
2409
2410                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2411         }
2412 }
2413
2414 static irqreturn_t i915_irq_handler(int irq, void *arg)
2415 {
2416         struct drm_device *dev = (struct drm_device *) arg;
2417         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2418         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2419         unsigned long irqflags;
2420         u32 flip_mask =
2421                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2422                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2423         u32 flip[2] = {
2424                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2425                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2426         };
2427         int pipe, ret = IRQ_NONE;
2428
2429         atomic_inc(&dev_priv->irq_received);
2430
2431         iir = I915_READ(IIR);
2432         do {
2433                 bool irq_received = (iir & ~flip_mask) != 0;
2434                 bool blc_event = false;
2435
2436                 /* Can't rely on pipestat interrupt bit in iir as it might
2437                  * have been cleared after the pipestat interrupt was received.
2438                  * It doesn't set the bit in iir again, but it still produces
2439                  * interrupts (for non-MSI).
2440                  */
2441                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2442                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2443                         i915_handle_error(dev, false);
2444
2445                 for_each_pipe(pipe) {
2446                         int reg = PIPESTAT(pipe);
2447                         pipe_stats[pipe] = I915_READ(reg);
2448
2449                         /* Clear the PIPE*STAT regs before the IIR */
2450                         if (pipe_stats[pipe] & 0x8000ffff) {
2451                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2452                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2453                                                          pipe_name(pipe));
2454                                 I915_WRITE(reg, pipe_stats[pipe]);
2455                                 irq_received = true;
2456                         }
2457                 }
2458                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2459
2460                 if (!irq_received)
2461                         break;
2462
2463                 /* Consume port.  Then clear IIR or we'll miss events */
2464                 if ((I915_HAS_HOTPLUG(dev)) &&
2465                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2466                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2467
2468                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2469                                   hotplug_status);
2470                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2471                                 queue_work(dev_priv->wq,
2472                                            &dev_priv->hotplug_work);
2473
2474                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2475                         POSTING_READ(PORT_HOTPLUG_STAT);
2476                 }
2477
2478                 I915_WRITE(IIR, iir & ~flip_mask);
2479                 new_iir = I915_READ(IIR); /* Flush posted writes */
2480
2481                 if (iir & I915_USER_INTERRUPT)
2482                         notify_ring(dev, &dev_priv->ring[RCS]);
2483
2484                 for_each_pipe(pipe) {
2485                         int plane = pipe;
2486                         if (IS_MOBILE(dev))
2487                                 plane = !plane;
2488                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2489                             drm_handle_vblank(dev, pipe)) {
2490                                 if (iir & flip[plane]) {
2491                                         intel_prepare_page_flip(dev, plane);
2492                                         intel_finish_page_flip(dev, pipe);
2493                                         flip_mask &= ~flip[plane];
2494                                 }
2495                         }
2496
2497                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2498                                 blc_event = true;
2499                 }
2500
2501                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2502                         intel_opregion_asle_intr(dev);
2503
2504                 /* With MSI, interrupts are only generated when iir
2505                  * transitions from zero to nonzero.  If another bit got
2506                  * set while we were handling the existing iir bits, then
2507                  * we would never get another interrupt.
2508                  *
2509                  * This is fine on non-MSI as well, as if we hit this path
2510                  * we avoid exiting the interrupt handler only to generate
2511                  * another one.
2512                  *
2513                  * Note that for MSI this could cause a stray interrupt report
2514                  * if an interrupt landed in the time between writing IIR and
2515                  * the posting read.  This should be rare enough to never
2516                  * trigger the 99% of 100,000 interrupts test for disabling
2517                  * stray interrupts.
2518                  */
2519                 ret = IRQ_HANDLED;
2520                 iir = new_iir;
2521         } while (iir & ~flip_mask);
2522
2523         i915_update_dri1_breadcrumb(dev);
2524
2525         return ret;
2526 }
2527
2528 static void i915_irq_uninstall(struct drm_device * dev)
2529 {
2530         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2531         int pipe;
2532
2533         if (I915_HAS_HOTPLUG(dev)) {
2534                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2535                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2536         }
2537
2538         I915_WRITE16(HWSTAM, 0xffff);
2539         for_each_pipe(pipe) {
2540                 /* Clear enable bits; then clear status bits */
2541                 I915_WRITE(PIPESTAT(pipe), 0);
2542                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2543         }
2544         I915_WRITE(IMR, 0xffffffff);
2545         I915_WRITE(IER, 0x0);
2546
2547         I915_WRITE(IIR, I915_READ(IIR));
2548 }
2549
2550 static void i965_irq_preinstall(struct drm_device * dev)
2551 {
2552         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2553         int pipe;
2554
2555         atomic_set(&dev_priv->irq_received, 0);
2556
2557         I915_WRITE(PORT_HOTPLUG_EN, 0);
2558         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2559
2560         I915_WRITE(HWSTAM, 0xeffe);
2561         for_each_pipe(pipe)
2562                 I915_WRITE(PIPESTAT(pipe), 0);
2563         I915_WRITE(IMR, 0xffffffff);
2564         I915_WRITE(IER, 0x0);
2565         POSTING_READ(IER);
2566 }
2567
2568 static int i965_irq_postinstall(struct drm_device *dev)
2569 {
2570         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2571         u32 enable_mask;
2572         u32 error_mask;
2573
2574         /* Unmask the interrupts that we always want on. */
2575         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2576                                I915_DISPLAY_PORT_INTERRUPT |
2577                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2578                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2579                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2580                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2581                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2582
2583         enable_mask = ~dev_priv->irq_mask;
2584         enable_mask |= I915_USER_INTERRUPT;
2585
2586         if (IS_G4X(dev))
2587                 enable_mask |= I915_BSD_USER_INTERRUPT;
2588
2589         dev_priv->pipestat[0] = 0;
2590         dev_priv->pipestat[1] = 0;
2591         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2592
2593         /*
2594          * Enable some error detection, note the instruction error mask
2595          * bit is reserved, so we leave it masked.
2596          */
2597         if (IS_G4X(dev)) {
2598                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2599                                GM45_ERROR_MEM_PRIV |
2600                                GM45_ERROR_CP_PRIV |
2601                                I915_ERROR_MEMORY_REFRESH);
2602         } else {
2603                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2604                                I915_ERROR_MEMORY_REFRESH);
2605         }
2606         I915_WRITE(EMR, error_mask);
2607
2608         I915_WRITE(IMR, dev_priv->irq_mask);
2609         I915_WRITE(IER, enable_mask);
2610         POSTING_READ(IER);
2611
2612         I915_WRITE(PORT_HOTPLUG_EN, 0);
2613         POSTING_READ(PORT_HOTPLUG_EN);
2614
2615         intel_opregion_enable_asle(dev);
2616
2617         return 0;
2618 }
2619
2620 static void i965_hpd_irq_setup(struct drm_device *dev)
2621 {
2622         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2623         u32 hotplug_en;
2624
2625         /* Note HDMI and DP share hotplug bits */
2626         hotplug_en = 0;
2627         if (dev_priv->hotplug_supported_mask & PORTB_HOTPLUG_INT_STATUS)
2628                 hotplug_en |= PORTB_HOTPLUG_INT_EN;
2629         if (dev_priv->hotplug_supported_mask & PORTC_HOTPLUG_INT_STATUS)
2630                 hotplug_en |= PORTC_HOTPLUG_INT_EN;
2631         if (dev_priv->hotplug_supported_mask & PORTD_HOTPLUG_INT_STATUS)
2632                 hotplug_en |= PORTD_HOTPLUG_INT_EN;
2633         if (IS_G4X(dev)) {
2634                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_G4X)
2635                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2636                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_G4X)
2637                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2638         } else {
2639                 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS_I965)
2640                         hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2641                 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS_I965)
2642                         hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2643         }
2644         if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2645                 hotplug_en |= CRT_HOTPLUG_INT_EN;
2646
2647                 /* Programming the CRT detection parameters tends
2648                    to generate a spurious hotplug event about three
2649                    seconds later.  So just do it once.
2650                    */
2651                 if (IS_G4X(dev))
2652                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2653                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2654         }
2655
2656         /* Ignore TV since it's buggy */
2657
2658         I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2659 }
2660
2661 static irqreturn_t i965_irq_handler(int irq, void *arg)
2662 {
2663         struct drm_device *dev = (struct drm_device *) arg;
2664         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2665         u32 iir, new_iir;
2666         u32 pipe_stats[I915_MAX_PIPES];
2667         unsigned long irqflags;
2668         int irq_received;
2669         int ret = IRQ_NONE, pipe;
2670
2671         atomic_inc(&dev_priv->irq_received);
2672
2673         iir = I915_READ(IIR);
2674
2675         for (;;) {
2676                 bool blc_event = false;
2677
2678                 irq_received = iir != 0;
2679
2680                 /* Can't rely on pipestat interrupt bit in iir as it might
2681                  * have been cleared after the pipestat interrupt was received.
2682                  * It doesn't set the bit in iir again, but it still produces
2683                  * interrupts (for non-MSI).
2684                  */
2685                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2686                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2687                         i915_handle_error(dev, false);
2688
2689                 for_each_pipe(pipe) {
2690                         int reg = PIPESTAT(pipe);
2691                         pipe_stats[pipe] = I915_READ(reg);
2692
2693                         /*
2694                          * Clear the PIPE*STAT regs before the IIR
2695                          */
2696                         if (pipe_stats[pipe] & 0x8000ffff) {
2697                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2698                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2699                                                          pipe_name(pipe));
2700                                 I915_WRITE(reg, pipe_stats[pipe]);
2701                                 irq_received = 1;
2702                         }
2703                 }
2704                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2705
2706                 if (!irq_received)
2707                         break;
2708
2709                 ret = IRQ_HANDLED;
2710
2711                 /* Consume port.  Then clear IIR or we'll miss events */
2712                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2713                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2714
2715                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2716                                   hotplug_status);
2717                         if (hotplug_status & dev_priv->hotplug_supported_mask)
2718                                 queue_work(dev_priv->wq,
2719                                            &dev_priv->hotplug_work);
2720
2721                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2722                         I915_READ(PORT_HOTPLUG_STAT);
2723                 }
2724
2725                 I915_WRITE(IIR, iir);
2726                 new_iir = I915_READ(IIR); /* Flush posted writes */
2727
2728                 if (iir & I915_USER_INTERRUPT)
2729                         notify_ring(dev, &dev_priv->ring[RCS]);
2730                 if (iir & I915_BSD_USER_INTERRUPT)
2731                         notify_ring(dev, &dev_priv->ring[VCS]);
2732
2733                 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
2734                         intel_prepare_page_flip(dev, 0);
2735
2736                 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
2737                         intel_prepare_page_flip(dev, 1);
2738
2739                 for_each_pipe(pipe) {
2740                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2741                             drm_handle_vblank(dev, pipe)) {
2742                                 i915_pageflip_stall_check(dev, pipe);
2743                                 intel_finish_page_flip(dev, pipe);
2744                         }
2745
2746                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2747                                 blc_event = true;
2748                 }
2749
2750
2751                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2752                         intel_opregion_asle_intr(dev);
2753
2754                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2755                         gmbus_irq_handler(dev);
2756
2757                 /* With MSI, interrupts are only generated when iir
2758                  * transitions from zero to nonzero.  If another bit got
2759                  * set while we were handling the existing iir bits, then
2760                  * we would never get another interrupt.
2761                  *
2762                  * This is fine on non-MSI as well, as if we hit this path
2763                  * we avoid exiting the interrupt handler only to generate
2764                  * another one.
2765                  *
2766                  * Note that for MSI this could cause a stray interrupt report
2767                  * if an interrupt landed in the time between writing IIR and
2768                  * the posting read.  This should be rare enough to never
2769                  * trigger the 99% of 100,000 interrupts test for disabling
2770                  * stray interrupts.
2771                  */
2772                 iir = new_iir;
2773         }
2774
2775         i915_update_dri1_breadcrumb(dev);
2776
2777         return ret;
2778 }
2779
2780 static void i965_irq_uninstall(struct drm_device * dev)
2781 {
2782         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2783         int pipe;
2784
2785         if (!dev_priv)
2786                 return;
2787
2788         I915_WRITE(PORT_HOTPLUG_EN, 0);
2789         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2790
2791         I915_WRITE(HWSTAM, 0xffffffff);
2792         for_each_pipe(pipe)
2793                 I915_WRITE(PIPESTAT(pipe), 0);
2794         I915_WRITE(IMR, 0xffffffff);
2795         I915_WRITE(IER, 0x0);
2796
2797         for_each_pipe(pipe)
2798                 I915_WRITE(PIPESTAT(pipe),
2799                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2800         I915_WRITE(IIR, I915_READ(IIR));
2801 }
2802
2803 void intel_irq_init(struct drm_device *dev)
2804 {
2805         struct drm_i915_private *dev_priv = dev->dev_private;
2806
2807         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2808         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
2809         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
2810         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
2811
2812         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
2813                     i915_hangcheck_elapsed,
2814                     (unsigned long) dev);
2815
2816         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
2817
2818         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2819         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2820         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
2821                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2822                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2823         }
2824
2825         if (drm_core_check_feature(dev, DRIVER_MODESET))
2826                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2827         else
2828                 dev->driver->get_vblank_timestamp = NULL;
2829         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2830
2831         if (IS_VALLEYVIEW(dev)) {
2832                 dev->driver->irq_handler = valleyview_irq_handler;
2833                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2834                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2835                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2836                 dev->driver->enable_vblank = valleyview_enable_vblank;
2837                 dev->driver->disable_vblank = valleyview_disable_vblank;
2838                 dev_priv->display.hpd_irq_setup = valleyview_hpd_irq_setup;
2839         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2840                 /* Share pre & uninstall handlers with ILK/SNB */
2841                 dev->driver->irq_handler = ivybridge_irq_handler;
2842                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2843                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2844                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2845                 dev->driver->enable_vblank = ivybridge_enable_vblank;
2846                 dev->driver->disable_vblank = ivybridge_disable_vblank;
2847         } else if (HAS_PCH_SPLIT(dev)) {
2848                 dev->driver->irq_handler = ironlake_irq_handler;
2849                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2850                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2851                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2852                 dev->driver->enable_vblank = ironlake_enable_vblank;
2853                 dev->driver->disable_vblank = ironlake_disable_vblank;
2854         } else {
2855                 if (INTEL_INFO(dev)->gen == 2) {
2856                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
2857                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
2858                         dev->driver->irq_handler = i8xx_irq_handler;
2859                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
2860                 } else if (INTEL_INFO(dev)->gen == 3) {
2861                         dev->driver->irq_preinstall = i915_irq_preinstall;
2862                         dev->driver->irq_postinstall = i915_irq_postinstall;
2863                         dev->driver->irq_uninstall = i915_irq_uninstall;
2864                         dev->driver->irq_handler = i915_irq_handler;
2865                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
2866                 } else {
2867                         dev->driver->irq_preinstall = i965_irq_preinstall;
2868                         dev->driver->irq_postinstall = i965_irq_postinstall;
2869                         dev->driver->irq_uninstall = i965_irq_uninstall;
2870                         dev->driver->irq_handler = i965_irq_handler;
2871                         dev_priv->display.hpd_irq_setup = i965_hpd_irq_setup;
2872                 }
2873                 dev->driver->enable_vblank = i915_enable_vblank;
2874                 dev->driver->disable_vblank = i915_disable_vblank;
2875         }
2876 }
2877
2878 void intel_hpd_init(struct drm_device *dev)
2879 {
2880         struct drm_i915_private *dev_priv = dev->dev_private;
2881
2882         if (dev_priv->display.hpd_irq_setup)
2883                 dev_priv->display.hpd_irq_setup(dev);
2884 }